*** empty log message ***

diff --git a/media_interfaces/trb_net16_med_ecp_sfp_4.vhd b/media_interfaces/trb_net16_med_ecp_sfp_4.vhd
index 109a2434d5d009c122a38c664887846f2c93c01c..786c6cd4ee232fc8bd744277617a10dfd800b2f2 100644 (file)
--- a/media_interfaces/trb_net16_med_ecp_sfp_4.vhd
+++ b/media_interfaces/trb_net16_med_ecp_sfp_4.vhd
@@ -840,7 +840,7 @@ begin
           elsif( led_counter = 0 ) then
             rx_led(i) <= '0';
           end if;
-          if( fifo_tx_wr_en(i) = '0') then
+          if( fifo_tx_wr_en(i) = '1') then
             tx_led(i) <= '1';
           elsif led_counter = 0 then
             tx_led(i) <= '0';

diff --git a/media_interfaces/trb_net16_med_ecp_sfp_4_gbe.vhd b/media_interfaces/trb_net16_med_ecp_sfp_4_gbe.vhd
index 3e42dbd66107d4e528beed1d6ff4f9efd71eb8f6..cd89976c18d6013b49133a43870935cd81bea005 100755 (executable)
--- a/media_interfaces/trb_net16_med_ecp_sfp_4_gbe.vhd
+++ b/media_interfaces/trb_net16_med_ecp_sfp_4_gbe.vhd
@@ -315,22 +315,22 @@ begin
         );
 
 -- Transfering the komma delimiter in the *training* phase
-    THE_RX_K_SYNC: signal_sync
-      generic map(
-        DEPTH => 3,
-        WIDTH => 2
-        )
-      port map(
-        RESET    => reset_i(i),
-        D_IN     => comb_rx_k(i*2+1 downto i*2),
-        CLK0     => ff_txhalfclk,
-        CLK1     => SYSCLK,
-        D_OUT    => rx_k_q(i*2+1 downto i*2)
-        );
+--     THE_RX_K_SYNC: signal_sync
+--       generic map(
+--         DEPTH => 3,
+--         WIDTH => 2
+--         )
+--       port map(
+--         RESET    => reset_i(i),
+--         D_IN     => comb_rx_k(i*2+1 downto i*2),
+--         CLK0     => SYSCLK,
+--         CLK1     => SYSCLK,
+--         D_OUT    => rx_k_q(i*2+1 downto i*2)
+--         );
 
 
 -- registers for RX_K and RX_DATA between serdes and internal logic
-    THE_RX_DATA_DELAY: signal_sync
+    THE_RX_DATA_SYNC: signal_sync
       generic map(
         DEPTH => 2,
         WIDTH => 18
@@ -339,14 +339,14 @@ begin
         RESET    => reset_i(i),
         D_IN(15 downto 0) => comb_rx_data(i*16+15 downto i*16),
         D_IN(17 downto 16)=> comb_rx_k(i*2+1 downto i*2),
-        CLK0     => ff_txhalfclk,
-        CLK1     => ff_txhalfclk,
+        CLK0     => SYSCLK,
+        CLK1     => SYSCLK,
         D_OUT(15 downto 0)    => rx_data(i*16+15 downto i*16),
         D_OUT(17 downto 16)   => rx_k(i*2+1 downto i*2)
         );
 
 --delay signals for sending and receiving data
-    THE_RX_ALLOW_SYNC: signal_sync
+    THE_RX_ALLOW_DELAY: signal_sync
       generic map(
         DEPTH => 2,
         WIDTH => 2
@@ -371,8 +371,8 @@ begin
         RESET    => reset_i(i),
         D_IN(0)  => rx_allow(i),
         D_IN(1)  => swap_bytes(i),
-        CLK0     => ff_txhalfclk,
-        CLK1     => ff_txhalfclk,
+        CLK0     => SYSCLK,
+        CLK1     => SYSCLK,
         D_OUT(0) => rx_allow_qrx(i),
         D_OUT(1) => swap_bytes_qrx(i)
         );
@@ -395,7 +395,7 @@ begin
           SD_TXCLK_BAD_IN   => ffs_plol,
           SD_RXCLK_BAD_IN   => link_error(i)(7),
           SD_RETRY_IN       => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope
-          SD_ALIGNMENT_IN   => rx_k_q(i*2+1 downto i*2),
+          SD_ALIGNMENT_IN   => rx_k(i*2+1 downto i*2),
           SD_CV_IN          => link_error(i)(1 downto 0),
           FULL_RESET_OUT    => quad_rst(i),
           LANE_RESET_OUT    => lane_rst(i),
@@ -428,8 +428,8 @@ begin
         hdinn0               => SD_RXD_N_IN(0),
         hdoutp0              => SD_TXD_P_OUT(0),
         hdoutn0              => SD_TXD_N_OUT(0),
-        ff_rxiclk_ch0        => ff_txhalfclk,
-        ff_txiclk_ch0        => ff_txhalfclk,
+        ff_rxiclk_ch0        => SYSCLK,
+        ff_txiclk_ch0        => SYSCLK,
         ff_ebrd_clk_0        => ff_txfullclk,
         ff_txdata_ch0        => tx_data(15 downto 0),
         ff_rxdata_ch0        => comb_rx_data(15 downto 0),
@@ -459,8 +459,8 @@ begin
         hdinn1               => SD_RXD_N_IN(1),
         hdoutp1              => SD_TXD_P_OUT(1),
         hdoutn1              => SD_TXD_N_OUT(1),
-        ff_rxiclk_ch1        => ff_txhalfclk,
-        ff_txiclk_ch1        => ff_txhalfclk,
+        ff_rxiclk_ch1        => SYSCLK,
+        ff_txiclk_ch1        => SYSCLK,
         ff_ebrd_clk_1        => ff_txfullclk,
         ff_txdata_ch1        => tx_data(31 downto 16),
         ff_rxdata_ch1        => comb_rx_data(31 downto 16),
@@ -490,8 +490,8 @@ begin
         hdinn2               => SD_RXD_N_IN(2),
         hdoutp2              => SD_TXD_P_OUT(2),
         hdoutn2              => SD_TXD_N_OUT(2),
-        ff_rxiclk_ch2        => ff_txhalfclk,
-        ff_txiclk_ch2        => ff_txhalfclk,
+        ff_rxiclk_ch2        => SYSCLK,
+        ff_txiclk_ch2        => SYSCLK,
         ff_ebrd_clk_2        => ff_txfullclk,
         ff_txdata_ch2        => tx_data(47 downto 32),
         ff_rxdata_ch2        => comb_rx_data(47 downto 32),
@@ -521,8 +521,8 @@ begin
         hdinn3               => SD_RXD_N_IN(3),
         hdoutp3              => SD_TXD_P_OUT(3),
         hdoutn3              => SD_TXD_N_OUT(3),
-        ff_rxiclk_ch3        => ff_txhalfclk,
-        ff_txiclk_ch3        => ff_txhalfclk,
+        ff_rxiclk_ch3        => SYSCLK,
+        ff_txiclk_ch3        => SYSCLK,
         ff_ebrd_clk_3        => ff_txfullclk,
         ff_txdata_ch3        => tx_data(63 downto 48),
         ff_rxdata_ch3        => comb_rx_data(63 downto 48),
@@ -567,8 +567,8 @@ begin
         hdinn0               => SD_RXD_N_IN(0),
         hdoutp0              => SD_TXD_P_OUT(0),
         hdoutn0              => SD_TXD_N_OUT(0),
-        ff_rxiclk_ch0        => ff_txhalfclk,
-        ff_txiclk_ch0        => ff_txhalfclk,
+        ff_rxiclk_ch0        => SYSCLK,
+        ff_txiclk_ch0        => SYSCLK,
         ff_ebrd_clk_0        => ff_txfullclk,
         ff_txdata_ch0        => tx_data(63 downto 48),
         ff_rxdata_ch0        => comb_rx_data(63 downto 48),
@@ -598,8 +598,8 @@ begin
         hdinn1               => SD_RXD_N_IN(1),
         hdoutp1              => SD_TXD_P_OUT(1),
         hdoutn1              => SD_TXD_N_OUT(1),
-        ff_rxiclk_ch1        => ff_txhalfclk,
-        ff_txiclk_ch1        => ff_txhalfclk,
+        ff_rxiclk_ch1        => SYSCLK,
+        ff_txiclk_ch1        => SYSCLK,
         ff_ebrd_clk_1        => ff_txfullclk,
         ff_txdata_ch1        => tx_data(47 downto 32),
         ff_rxdata_ch1        => comb_rx_data(47 downto 32),
@@ -629,8 +629,8 @@ begin
         hdinn2               => SD_RXD_N_IN(2),
         hdoutp2              => SD_TXD_P_OUT(2),
         hdoutn2              => SD_TXD_N_OUT(2),
-        ff_rxiclk_ch2        => ff_txhalfclk,
-        ff_txiclk_ch2        => ff_txhalfclk,
+        ff_rxiclk_ch2        => SYSCLK,
+        ff_txiclk_ch2        => SYSCLK,
         ff_ebrd_clk_2        => ff_txfullclk,
         ff_txdata_ch2        => tx_data(31 downto 16),
         ff_rxdata_ch2        => comb_rx_data(31 downto 16),
@@ -660,8 +660,8 @@ begin
         hdinn3               => SD_RXD_N_IN(3),
         hdoutp3              => SD_TXD_P_OUT(3),
         hdoutn3              => SD_TXD_N_OUT(3),
-        ff_rxiclk_ch3        => ff_txhalfclk,
-        ff_txiclk_ch3        => ff_txhalfclk,
+        ff_rxiclk_ch3        => SYSCLK,
+        ff_txiclk_ch3        => SYSCLK,
         ff_ebrd_clk_3        => ff_txfullclk,
         ff_txdata_ch3        => tx_data(15 downto 0),
         ff_rxdata_ch3        => comb_rx_data(15 downto 0),
@@ -707,7 +707,7 @@ begin
         )
       port map(
         read_clock_in   => SYSCLK,
-        write_clock_in  => ff_txhalfclk,
+        write_clock_in  => SYSCLK,
         read_enable_in  => fifo_rx_rd_en(i),
         write_enable_in => fifo_rx_wr_en(i),
         fifo_gsr_in     => fifo_rx_reset(i),
@@ -724,9 +724,9 @@ begin
 -- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path
 ---------------------------------------------------------------------
 
-    THE_BYTE_SWAP_PROC: process( ff_txhalfclk )
+    THE_BYTE_SWAP_PROC: process( SYSCLK )
       begin
-        if( rising_edge(ff_txhalfclk) ) then
+        if( rising_edge(SYSCLK) ) then
           last_rx(9*i+8 downto 9*i) <= rx_k(i*2+1) & rx_data(i*16+15 downto i*16+8);
           if( swap_bytes_qrx(i) = '0' ) then
             fifo_rx_din(i*18+17 downto i*18) <= rx_k(i*2+1) & rx_k(i*2) & rx_data(i*16+15 downto i*16+8)
@@ -742,7 +742,7 @@ begin
 
 
 ---------------------------------------------------------------------
---Output to Internal Logic)
+--Output to Internal Logic
 ---------------------------------------------------------------------
 
     buf_med_data_out(i*16+15 downto i*16)       <= fifo_rx_dout(i*18+15 downto i*18);
@@ -795,7 +795,7 @@ begin
         USE_STATUS_FLAGS => c_NO
         )
       port map(
-        read_clock_in   => ff_txhalfclk,
+        read_clock_in   => SYSCLK,
         write_clock_in  => SYSCLK,
         read_enable_in  => fifo_tx_rd_en(i),
         write_enable_in => fifo_tx_wr_en(i),
@@ -813,9 +813,9 @@ begin
 
 
 
-    THE_SERDES_INPUT_PROC: process( ff_txhalfclk )
+    THE_SERDES_INPUT_PROC: process( SYSCLK )
       begin
-        if( rising_edge(ff_txhalfclk) ) then
+        if( rising_edge(SYSCLK) ) then
         last_fifo_tx_empty(i) <= fifo_tx_empty(i);
           if( (last_fifo_tx_empty(i) = '1') ) then -- or (tx_allow_qtx(i) = '0')
             tx_data(i*16+15 downto i*16) <= x"50bc";
@@ -841,7 +841,7 @@ begin
           elsif( led_counter = 0 ) then
             rx_led(i) <= '0';
           end if;
-          if( fifo_tx_wr_en(i) = '0') then
+          if( fifo_tx_wr_en(i) = '1') then
             tx_led(i) <= '1';
           elsif led_counter = 0 then
             tx_led(i) <= '0';
@@ -864,7 +864,7 @@ begin
     STAT_DEBUG(i*64+47 downto i*64+32) <= rx_data(i*16+15 downto i*16);
     STAT_DEBUG(i*64+57 downto i*64+48) <= link_error(i);
     STAT_DEBUG(i*64+58)                <= ffs_plol;
-    STAT_DEBUG(i*64+60 downto i*64+59) <= rx_k_q(i*2+1 downto i*2);
+    STAT_DEBUG(i*64+60 downto i*64+59) <= rx_k(i*2+1 downto i*2);
     STAT_DEBUG(i*64+63 downto i*64+61) <= (others => '0');
 
   end generate;

diff --git a/special/trb2_control_endpoint_tlk.vhd b/special/trb2_control_endpoint_tlk.vhd
index fd694a9f2a6dc495926ea1ceaa5e988b2b83c5e1..98f1211f0b562475ded83afcb035f37048f28b6b 100644 (file)
--- a/special/trb2_control_endpoint_tlk.vhd
+++ b/special/trb2_control_endpoint_tlk.vhd
@@ -161,6 +161,7 @@ end component;
   signal counter: std_logic_vector(15 downto 0);
 
   signal TLK_STAT : std_logic_vector(63 downto 0);
+  signal TLK_STAT_MONITOR : std_logic_vector(100 downto 0);
 
   signal MED_DATAREADY_IN, MED_DATAREADY_OUT  : std_logic;
   signal MED_DATA_IN, MED_DATA_OUT            : std_logic_vector(c_DATA_WIDTH-1 downto 0);
@@ -188,7 +189,11 @@ end component;
   signal STAT_ENDP : std_logic_vector(31 downto 0);
   signal STAT_API1 : std_logic_vector(31 downto 0);
   signal MED_STAT_OP : std_logic_vector(15 downto 0);
+  signal MED_CTRL_OP : std_logic_vector(15 downto 0);
   signal EI_STAT   : std_logic_vector(7 downto 0);
+  signal last_CTRL_REGS : std_logic_vector(15 downto 14);
+
+  signal send_reset_counter : std_logic_vector(11 downto 0) := x"FFF";
 
 begin
   CLK <= VIRT_CLK;
@@ -233,11 +238,11 @@ begin
       end if;
     end process;
 
-    DGOOD       <= not TLK_STAT(0);
+    DGOOD       <= not MED_STAT_OP(9);
 
     DBAD        <= not (TLK_STAT(36)); -- no error, but not ERROR_OK
     DINT        <= not (tmp ); --RX_ER and RX_DV;
-    DWAIT       <= not (MED_PACKET_NUM_IN(1));
+    DWAIT       <= not (MED_STAT_OP(10) or MED_STAT_OP(11));
 
 ---------------------------------------------------------------------
 --Media Interface: Optical Link
@@ -270,12 +275,29 @@ begin
       MED_DATA_OUT        => MED_DATA_IN,
       MED_PACKET_NUM_OUT  => MED_PACKET_NUM_IN,
       STAT                => TLK_STAT,
+      STAT_MONITOR        => TLK_STAT_MONITOR,
       STAT_OP             => MED_STAT_OP,
-      CTRL_OP             => MED_STAT_OP
+      CTRL_OP             => MED_CTRL_OP
       );
 
+  MED_CTRL_OP  <= (15 => not send_reset_counter(10), others => '0');
   MED_ERROR_IN <= MED_STAT_OP(2 downto 0);
 
+  process(CLK)
+    begin
+      if rising_edge(CLK) then
+        last_CTRL_REGS(15 downto 14) <= CTRL_REGS(15 downto 14);
+        if RESET = '1' then
+          send_reset_counter <= (others => '1');
+        elsif CTRL_REGS(15) = '1' and last_CTRL_REGS(15) = '0' then
+          send_reset_counter <= (others => '0');
+        elsif send_reset_counter(10) = '0' then
+          send_reset_counter <= send_reset_counter + 1;
+        end if;
+      end if;
+    end process;
+
+
 ---------------------------------------------------------------------
 --The Endpoint generating the connection to etrax-read/write/able registers
 ---------------------------------------------------------------------
@@ -345,9 +367,10 @@ begin
 ---------------------------------------------------------------------
   STAT_REGS(63 downto 0) <= APL_STAT & STAT_ENDP;
 
-  buf_ADO_TTL(0) <= etrax_read;
-  buf_ADO_TTL(6 downto 1)   <= EI_STAT(5 downto 0);
-  buf_ADO_TTL(14 downto 7)  <= (others => 'Z');
+  buf_ADO_TTL(14 downto 0) <= TLK_STAT(15 downto 14) & "0" & TLK_STAT(27 downto 16);
+--   buf_ADO_TTL(0) <= etrax_read;
+--   buf_ADO_TTL(6 downto 1)   <= EI_STAT(5 downto 0);
+--   buf_ADO_TTL(14 downto 7)  <= (others => 'Z');
   buf_ADO_TTL(46 downto 16) <= (others => 'Z');
 
   PROC_LA_CLK : process(CLK)

diff --git a/trb_net16_endpoint_hades_full.vhd b/trb_net16_endpoint_hades_full.vhd
index b7473300594257118ff230625b5a469828e00572..8e5b93fa2af8e01a83fe1f45aa18bdbba2383954 100644 (file)
--- a/trb_net16_endpoint_hades_full.vhd
+++ b/trb_net16_endpoint_hades_full.vhd
@@ -79,6 +79,7 @@ entity trb_net16_endpoint_hades_full is
 
     --Data Port
     IPU_NUMBER_OUT       : out std_logic_vector (15 downto 0);
+    IPU_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0);
     IPU_INFORMATION_OUT  : out std_logic_vector (7 downto 0);
     --start strobe
     IPU_START_READOUT_OUT: out std_logic;
@@ -437,6 +438,7 @@ begin
               MY_ADDRESS_IN          => MY_ADDRESS,
               --Information received with request
               IPU_NUMBER_OUT         => IPU_NUMBER_OUT,
+              IPU_READOUT_TYPE_OUT   => IPU_READOUT_TYPE_OUT,
               IPU_INFORMATION_OUT    => IPU_INFORMATION_OUT,
               --start strobe
               IPU_START_READOUT_OUT  => IPU_START_READOUT_OUT,

diff --git a/trb_net16_ipudata.vhd b/trb_net16_ipudata.vhd
index c3bab535f92f6a5b17ea19ad80b5561e3d4f9e33..b0895ef87dc5cd29c0e2d419f6182f434ef541f7 100644 (file)
--- a/trb_net16_ipudata.vhd
+++ b/trb_net16_ipudata.vhd
@@ -264,10 +264,10 @@ begin
           evt_number_mismatch <= '0';
           evt_code_mismatch   <= '0';
         elsif make_compare = '1' then
-          if reg_IPU_DATA(15 downto 0) /= buf_NUMBER then
+          if IPU_DATA(15 downto 0) /= buf_NUMBER then     --was reg_
             evt_number_mismatch <= '1';
           end if;
-          if reg_IPU_DATA_high(7 downto 0) /= buf_RND_CODE then
+          if IPU_DATA(23 downto 16) /= buf_RND_CODE then  --was reg_
             evt_code_mismatch <= '1';
           end if;
         end if;

diff --git a/trb_net_components.vhd b/trb_net_components.vhd
index 69cb232d0de61e37cd69676449a1e1b1b71488af..05999dcbaefff2770e51cfcf680f25cfdab9035d 100644 (file)
--- a/trb_net_components.vhd
+++ b/trb_net_components.vhd
@@ -253,6 +253,7 @@ package trb_net_components is
 
       --Data Port
       IPU_NUMBER_OUT       : out std_logic_vector (15 downto 0);
+      IPU_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0);
       IPU_INFORMATION_OUT  : out std_logic_vector (7 downto 0);
       --start strobe
       IPU_START_READOUT_OUT: out std_logic;
@@ -589,6 +590,7 @@ package trb_net_components is
 
       --Information received with request
       IPU_NUMBER_OUT   : out std_logic_vector (15 downto 0);
+      IPU_READOUT_TYPE_OUT : out std_logic_vector (7 downto 0);
       IPU_INFORMATION_OUT  : out std_logic_vector (7 downto 0);
       --start strobe
       IPU_START_READOUT_OUT: out std_logic;
@@ -609,7 +611,6 @@ package trb_net_components is
 
 
 
-
   component trb_net16_lsm_sfp is
     port(
       SYSCLK            : in  std_logic; -- fabric clock