CTS: How to operate free-running with 2 freqs

diff --git a/trb3/CtsBuildingBlocks.tex b/trb3/CtsBuildingBlocks.tex
index b56c610ab6ff2033e9018f875402235c62327b86..25ff73dd4f1f32433ef2cdee415f257ad22d83b6 100755 (executable)
--- a/trb3/CtsBuildingBlocks.tex
+++ b/trb3/CtsBuildingBlocks.tex
@@ -265,6 +265,24 @@
    preprocessed general purpose trigger signals, such as bindings to foreign DAQ protocols. Currently only a CBM-MBS adapter
    is available. See chapter \ref{sec:cts_howto_external_trigger} for a short tutorial on how to implement a new module.
 
+
+\subsubsection{Free-Running with Spill-Dependent Frequency}
+    \begin{figure}[h]
+      \begin{center}
+         \includegraphics[width=0.7\textwidth]{figures/cts_free_running.pdf}
+         \caption{Free-Running mode with different onspill/offspill frequencies.}
+         \label{fig:cts_free_running}
+      \end{center}
+   \end{figure}
+   
+   If supported by the experimental set-up it might be beneficial to reduce the trigger frequency of a free-running system during offspill phase.
+   Especially if there are many frontends in the DAQ, substantial data reductions can be achieved.
+   
+   As shown in Figure~\ref{fig:cts_free_running}, you need two pulsers, two coincidence modules, four input modules and a spill-indicator, that is available to an input module (e.g. any input of the CTS-Addon or an appropriate pin of the onboard RJ45-jacks):
+   In the diagram \texttt{Pulser3} is engaged during spill time: While its ITC is disabled, the signal is received from \texttt{InputModule2} and forwarded to \texttt{Coincidence1}.
+   \texttt{InputModule2} is only necessary since coincidence modules are connected only to input~modules and cannot receive the signal otherwise.
+   The spill-signal is fed to the \texttt{Coincidence1}'s inhibit pin via a second input~module: The inhibit signal has to be high, in order to select the pulser; so if the spill-signal is low-active, enable the input module's inverter.
+   The frequency during offspill periods is derived similarly; just use the opposite setting for the spill-signal's inverter.
    
 \subsubsection{Latency and Jitter}
 \label{sec:cts_bb_cts_latency_and_jitter}
@@ -302,6 +320,7 @@
 
    Both latencies measured have a positive jitter of 10~ns, i.e.\ the sampling period of the CTS running at
    100~MHz. Thus, the design itself can be considered jitter free.
+
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