added generic PORT_MASK_ENABLE trb_net16_regio_bus_handler, default is 0 for backward...

diff --git a/trb_net16_regio_bus_handler.vhd b/trb_net16_regio_bus_handler.vhd
index 47919d0ff14c9300ca41e9f93cb4b97bdc2ea363..c596f525f13552870418a0db4ff03009bfa34349 100644 (file)
--- a/trb_net16_regio_bus_handler.vhd
+++ b/trb_net16_regio_bus_handler.vhd
@@ -11,7 +11,8 @@ entity trb_net16_regio_bus_handler is
   generic(
     PORT_NUMBER : integer range 1 to c_BUS_HANDLER_MAX_PORTS := 3;
     PORT_ADDRESSES : c_BUS_HANDLER_ADDR_t := (others => (others => '0'));
-    PORT_ADDR_MASK : c_BUS_HANDLER_WIDTH_t := (others => 0)
+    PORT_ADDR_MASK : c_BUS_HANDLER_WIDTH_t := (others => 0);
+    PORT_MASK_ENABLE : integer range 0 to 1 := 0
     );
   port(
     CLK                   : in  std_logic;
@@ -82,7 +83,8 @@ begin
     begin
       next_port_select_int <= PORT_NUMBER;
       gen_port_select : for i in 0 to PORT_NUMBER-1 loop
-        if (PORT_ADDR_MASK(i) = 16 or (DAT_ADDR_IN(15 downto PORT_ADDR_MASK(i)) = PORT_ADDRESSES(i)(15 downto PORT_ADDR_MASK(i)))) then
+        if (PORT_ADDR_MASK(i) = 16 or
+            (DAT_ADDR_IN(15 downto PORT_ADDR_MASK(i)) = PORT_ADDRESSES(i)(15 downto PORT_ADDR_MASK(i)))) then
           next_port_select_int <= i;
         end if;
       end loop;
@@ -125,11 +127,17 @@ begin
   BUS_WRITE_ENABLE_OUT<= buf_BUS_WRITE_OUT(PORT_NUMBER-1 downto 0);
   gen_bus_outputs : for i in 0 to PORT_NUMBER-1 generate
     BUS_DATA_OUT(i*32+31 downto i*32)  <= buf_BUS_DATA_OUT;
-    BUS_ADDR_OUT(i*16+15 downto i*16)  <= buf_BUS_ADDR_OUT;
+    port_mask_disabled : if PORT_MASK_ENABLE = 0 generate
+      BUS_ADDR_OUT(i*16+15 downto i*16)  <= buf_BUS_ADDR_OUT;
+    end generate;
+     port_mask_enabled : if PORT_MASK_ENABLE = 1 generate
+       BUS_ADDR_OUT(i*16+15 downto i*16+PORT_ADDR_MASK(i)) <= (others => '0');
+       BUS_ADDR_OUT(i*16+PORT_ADDR_MASK(i)-1 downto i*16)
+         <= buf_BUS_ADDR_OUT(PORT_ADDR_MASK(i)-1 downto 0);
+     end generate;
     BUS_TIMEOUT_OUT(i)                 <= DAT_TIMEOUT_IN;
   end generate;
 
-
 ---------------------------------------------------------------------
 --Pack Data Inputs and Dummy Input
 ---------------------------------------------------------------------
@@ -166,4 +174,4 @@ begin
 ---------------------------------------------------------------------
   STAT_DEBUG <= (others => '0');
 
-end architecture;
\ No newline at end of file
+end architecture;

diff --git a/trb_net_components.vhd b/trb_net_components.vhd
index 95b433e789b2c407d0d865ccfdd0c78f88f43638..7507d1ff46e5ebe99f7ff68a6b3de1823c98b063 100644 (file)
--- a/trb_net_components.vhd
+++ b/trb_net_components.vhd
@@ -2633,7 +2633,8 @@ package trb_net_components is
     generic(\r
       PORT_NUMBER    : integer range 1 to c_BUS_HANDLER_MAX_PORTS := 3;\r
       PORT_ADDRESSES : c_BUS_HANDLER_ADDR_t                       := (others => (others => '0'));\r
-      PORT_ADDR_MASK : c_BUS_HANDLER_WIDTH_t                      := (others => 0)\r
+      PORT_ADDR_MASK : c_BUS_HANDLER_WIDTH_t                      := (others => 0);\r
+      PORT_MASK_ENABLE : integer range 0 to 1\r
       );\r
     port(\r
       CLK                  : in  std_logic;\r