--- /dev/null
+../../trb3sc/scripts/compile.pl
\ No newline at end of file
--- /dev/null
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+use work.trb_net_std.all;
+
+package config is
+
+
+------------------------------------------------------------------------------
+--Begin of design configuration
+------------------------------------------------------------------------------
+
+
+--set to 0 for backplane serdes, set to 1 for SFP serdes
+ constant SERDES_NUM : integer := 1;
+
+--TDC settings
+ constant FPGA_TYPE : integer := 5; --3: ECP3, 5: ECP5
+ constant FPGA_SIZE : string := "85KUM";
+-- constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement
+-- constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module
+-- constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons
+-- constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3
+-- -- 0: single edge only,
+-- -- 1: same channel,
+-- -- 2: alternating channels,
+-- -- 3: same channel with stretcher
+-- constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size
+-- -- mode: 0, 1, 2, 3, 7
+-- -- size: 32, 64, 96, 128, dyn
+-- constant TDC_DATA_FORMAT : integer range 0 to 3 := 0; --type of data format for the TDC
+-- -- 0: Single fine time as the sum of the two transitions
+-- -- 1: Double fine time, individual transitions
+-- -- 13: Debug - fine time + (if 0x3ff full chain)
+-- -- 14: Debug - single fine time and the ROM addresses for the two transitions
+-- -- 15: Debug - complete carry chain dump
+
+ constant EVENT_BUFFER_SIZE : integer range 9 to 15 := 10; -- size of the event buffer, 2**N
+ constant EVENT_MAX_SIZE : integer := 500; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2
+ constant USE_GBE : integer := c_NO;
+
+--Runs with 120 MHz instead of 100 MHz
+ constant USE_120_MHZ : integer := c_NO;
+
+--Use sync mode, RX clock for all parts of the FPGA
+ constant USE_RXCLOCK : integer := c_NO;
+
+--Address settings
+ constant INIT_ADDRESS : std_logic_vector := x"F586";
+ constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"86";
+
+ constant INCLUDE_UART : integer := c_NO;
+ constant INCLUDE_SPI : integer := c_YES;
+ constant INCLUDE_ADC : integer := c_YES;
+ constant INCLUDE_I2C : integer := c_NO;
+ constant INCLUDE_DEBUG_INTERFACE: integer := c_NO;
+
+ --input monitor and trigger generation logic
+ constant INCLUDE_TRIGGER_LOGIC : integer := c_YES;
+ constant INCLUDE_STATISTICS : integer := c_YES;
+ constant TRIG_GEN_INPUT_NUM : integer := 16;
+ constant TRIG_GEN_OUTPUT_NUM : integer := 4;
+ constant MONITOR_INPUT_NUM : integer := 16;
+
+------------------------------------------------------------------------------
+--End of design configuration
+------------------------------------------------------------------------------
+
+------------------------------------------------------------------------------
+--Select settings by configuration
+------------------------------------------------------------------------------
+ type intlist_t is array(0 to 7) of integer;
+ type hw_info_t is array(0 to 7) of unsigned(31 downto 0);
+ constant HW_INFO_BASE : unsigned(31 downto 0) := x"A5000200";
+
+ constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0);
+ constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0);
+
+ --declare constants, filled in body
+ constant HARDWARE_INFO : std_logic_vector(31 downto 0);
+ constant CLOCK_FREQUENCY : integer;
+ constant MEDIA_FREQUENCY : integer;
+ constant INCLUDED_FEATURES : std_logic_vector(63 downto 0);
+ constant BROADCAST_BITMASK : std_logic_vector(7 downto 0) := (7 => (not std_logic_vector(to_unsigned(USE_GBE,1))(0)), others => '1');
+
+end;
+
+package body config is
+--compute correct configuration mode
+
+ constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( HW_INFO_BASE );
+ constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ);
+ constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ);
+
+function generateIncludedFeatures return std_logic_vector is
+ variable t : std_logic_vector(63 downto 0);
+ begin
+ t := (others => '0');
+ t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 1
+
+-- t(7 downto 0) := std_logic_vector(to_unsigned(1,8));
+-- t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4));
+-- t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3));
+-- t(15) := '1'; --TDC
+-- t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2));
+ t(16 downto 16) := std_logic_vector(to_unsigned(USE_GBE,1));
+ t(28 downto 28) := std_logic_vector(to_unsigned(1-SERDES_NUM,1));
+
+ t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
+ t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
+ t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
+ t(47 downto 47) := std_logic_vector(to_unsigned(INCLUDE_I2C,1));
+ t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
+ t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
+ t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
+ t(54 downto 54) := "0";--std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1));
+ return t;
+ end function;
+
+ constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures;
+
+end package body;
--- /dev/null
+Familyname => 'ECP5UM',
+Devicename => 'LFE5UM-85F',
+Package => 'CABGA756',
+Speedgrade => '8',
+
+
+TOPNAME => "trb5sc_adc",
+lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
+lm_license_file_for_par => "1710\@jspc29",
+lattice_path => '/d/jspc29/lattice/diamond/3.12',
+synplify_path => '/d/jspc29/lattice/synplify/T-2022.09-SP2/',
+
+nodelist_file => '../nodelist_frankfurt.txt',
+pinout_file => 'trb5sc_adc',
+par_options => '../par.p2t',
+
+
+#Include only necessary lpf files
+include_TDC => 0,
+include_GBE => 0,
+
+#Report settings
+firefox_open => 0,
+twr_number_of_errors => 20,
+no_ltxt2ptxt => 1, #if there is no serdes being used
--- /dev/null
+-w
+#-y
+-l 5
+#-m nodelist.txt # Controlled by the compile.pl script.
+#-n 1 # Controlled by the compile.pl script.
+-s 10
+-t 13
+-c 2
+-e 2
+-i 10
+#-exp parPlcInLimit=0
+#-exp parPlcInNeighborSize=1
+#General PAR Command Line Options
+# -w With this option, any files generated will overwrite existing files
+# (e.g., any .par, .pad files).
+# -y Adds the Delay Summary Report in the .par file and creates the delay
+# file (in .dly format) at the end of the par run.
+#
+#PAR Placement Command Line Options
+# -l Specifies the effort level of the design from 1 (simplest designs)
+# to 5 (most complex designs).
+# -m Multi-tasking option. Controlled by the compile.pl script.
+# -n Sets the number of iterations performed at the effort level
+# specified by the -l option. Controlled by the compile.pl script.
+# -s Save the number of best results for this run.
+# -t Start placement at the specified cost table. Default is 1.
+#
+#PAR Routing Command Line Options
+# -c Run number of cost-based cleanup passes of the router.
+# -e Run number of delay-based cleanup passes of the router on
+# completely-routed designs only.
+# -i Run a maximum number of passes, stopping earlier only if the routing
+# goes to 100 percent completion and all constraints are met.
+#
+#PAR Explorer Command Line Options
+# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is
+# compatible with all Lattice FPGA device families; however, most
+# benefit has been demonstrated with benchmarks targeted to ECP5,
+# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families.
+# parCDR Enable the congestion-driven router (CDR) algorithm.
+# Congestion-driven options like parCDR and parCDP can improve
+# performance given a design with multiple congestion “hotspots.” The
+# Layer > Congestion option of the Design Planner Floorplan View can
+# help visualize routing congestion. Large congested areas may prevent
+# the options from finding a successful solution.
+# CDR is compatible with all Lattice FPGA device families however most
+# benefit has been demonstrated with benchmarks targeted to ECP5,
+# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families.
+# paruseNBR NBR Router or Negotiation-based routing option. Supports all
+# FPGA device families except LatticeXP and MachXO.
+# When turned on, an alternate routing engine from the traditional
+# Rip-up-based routing selection (RBR) is used. This involves an
+# iterative routing algorithm that routes connections to achieve
+# minimum delay cost. It does so by computing the demand on each
+# routing resource and applying cost values per node. It will
+# complete when an optimal solution is arrived at or the number of
+# iterations is reached.
+# parPathBased Path-based placement option. Path-based timing driven
+# placement will yield better performance and more
+# predictable results in many cases.
+# parHold Additional hold time correction option. This option
+# forces the router to automatically insert extra wires to compensate for the
+# hold time violation.
+# parHoldLimit This option allows you to set a limit on the number of
+# hold time violations to be processed by the auto hold time correction option
+# parHold.
+# parPlcInLimit Cannot find in the online help
+# parPlcInNeighborSize Cannot find in the online help
+-exp parHold=ON:parHoldLimit=10000:parCDP=1:parCDR=1:parPathBased=OFF:paruseNBR=1
--- /dev/null
+
+#################################################################
+# Basic Settings
+#################################################################
+
+FREQUENCY PORT CLK_200 200 MHz;
+FREQUENCY PORT CLK_125 125 MHz;
+FREQUENCY PORT CLK_EXT 200 MHz;
+
+FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz;
+FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs1.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz;
+# FREQUENCY NET "med_stat_debug[11]" 200 MHz;
+
+FREQUENCY NET "med2int_0.clk_full" 200 MHz;
+# FREQUENCY NET THE_MEDIA_INTERFACE/clk_rx_full 200 MHz;
+
+FREQUENCY NET "THE_ADDON/THE_INPUT_A/clk_data" 175.000000 MHz ;
+FREQUENCY NET "CLK_A_c" 350.000000 MHz ;
+
+BLOCK PATH TO PORT "LED*";
+BLOCK PATH TO PORT "PROGRAMN";
+BLOCK PATH TO PORT "TEMP_LINE";
+BLOCK PATH FROM PORT "TEMP_LINE";
+BLOCK PATH TO PORT "TEST_LINE*";
+
+#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns;
+#MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns;
+#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns;
+MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns;
+
+MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_SCI_READER/PROC_SCI_CTRL.BUS_TX*" 10 ns;
+MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT*" 10 ns;
+
+GSR_NET NET "clear_i";
+
+# LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/DCU0_inst" SITE "DCU0" ;
+
+
+REGION "MEDIA" "R81C44D" 13 25;
+LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ;
+
+
+BLOCK PATH FROM CELL "THE_ADDON/basic_control_strobe*";
+BLOCK PATH FROM CELL "THE_ADDON/config*";
+BLOCK PATH FROM CLKNET "clk_sys" TO CLKNET "THE_ADDON/THE_INPUT_A/clk_data";
+BLOCK PATH FROM CLKNET "THE_ADDON/THE_INPUT_A/clk_data" TO CLKNET "clk_sys";
+
--- /dev/null
+
+# implementation: "workdir"
+impl -add workdir -type fpga
+
+# device options
+set_option -technology ECP5UM
+set_option -part LFE5UM_85F
+set_option -package BG756C
+set_option -speed_grade -8
+set_option -part_companion ""
+
+# compilation/mapping options
+set_option -default_enum_encoding sequential
+set_option -symbolic_fsm_compiler 1
+set_option -top_module "trb5sc_cts"
+set_option -resource_sharing false
+set_option -vhdl2008 true
+
+# map options
+set_option -frequency 120
+set_option -fanout_limit 100
+set_option -disable_io_insertion 0
+set_option -retiming 1
+set_option -pipe 1
+set_option -forcegsr false
+set_option -fixgatedclocks 3
+set_option -fixgeneratedclocks 3
+set_option -compiler_compatible true
+set_option -multi_file_compilation_unit 1
+
+set_option -max_parallel_jobs 3
+#set_option -automatic_compile_point 1
+#set_option -continue_on_error 1
+set_option -resolve_multiple_driver 1
+
+# simulation options
+set_option -write_verilog 0
+set_option -write_vhdl 1
+
+# automatic place and route (vendor) options
+set_option -write_apr_constraint 0
+
+# set result format/file last
+project -result_format "edif"
+project -result_file "workdir/trb5sc_cts.edf"
+set_option log_file "workdir/trb5sc_cts.srf"
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+impl -active "workdir"
+
+####################
+
+add_file -vhdl -lib work "workdir/lattice-diamond/cae_library/synthesis/vhdl/ecp5um.vhd"
+
+#Packages
+add_file -vhdl -lib work "workdir/version.vhd"
+add_file -vhdl -lib work "config.vhd"
+add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_protocols.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd"
+
+#Basic Infrastructure
+add_file -vhdl -lib work "../../dirich/cores/pll_240_100/pll_240_100.vhd"
+add_file -vhdl -lib work "../../dirich/code/clock_reset_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/ecp5/sedcheck.vhd"
+
+
+#Fifos
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net16_fifo_arch.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16bit_dualport/lattice_ecp5_fifo_16bit_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net_fifo_16bit_bram_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x256_oreg/fifo_36x256_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x2k_oreg/fifo_18x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_9x2k_oreg/fifo_9x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16_dualport/lattice_ecp5_fifo_16x16_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_36x16_dualport_oreg/lattice_ecp5_fifo_36x16_dualport_oreg.vhd"
+
+
+#Flash & Reload, Tools
+add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
+add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/common_i2c.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
+add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd"
+
+#SlowControl files
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
+
+#Media interface
+# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd"
+# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd"
+# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd"
+# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd"
+# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd"
+# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd"
+# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd"
+# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd"
+# add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd"
+# add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd"
+
+
+#########################################
+#channel 0, backplane
+#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd"
+
+#channel 1, SFP
+# add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1/serdes_sync_0.vhd"
+##########################################
+
+# add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd"
+# add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs2.vhd"
+# add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v"
+
+
+#TrbNet Endpoint
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"
+
+add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd"
+add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd"
+
+add_file -vhdl -lib work "../../trbnet/special/trb_net_i2cwire.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim.vhd"
+
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart2.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb2.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim2.vhd"
+
+#Hub
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port_sctrl_cts.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_base.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_logic_2.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_ipu_logic.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/wide_adder_17x16.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16.vhd"
+
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming_internal.vhd"
+
+
+
+#GbE
+add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/base/gbe_wrapper.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/base/gbe_med_interface_single.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_receive_control.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_main_control.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_mac_control.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_prioritizer.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_trans.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_constr.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/ip_configurator.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_KillPing.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd"
+add_file -verilog -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/serdes_gbe_softlogic.v"
+# Choose your SerDes location here
+#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d0ch0/serdes_gbe.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d0ch1/serdes_gbe.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d1ch0/serdes_gbe.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d1ch1/serdes_gbe.vhd"
+
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4096x9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32x8.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x72.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx16x8_mb2.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2048x8x16.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_65536x18x9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/slv_mac_memory.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/ip_mem.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx18x9_wcnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx18x9_wcnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af_cnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9_af_cnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2kx9x18_wcnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4kx18x9_wcnt.vhd"
+
+
+
+add_file -vhdl -lib work "../../trb3/cts/source/cts_pkg.vhd"
+add_file -vhdl -lib work "../../trb3/cts/source/timestamp_generator.vhd"
+add_file -vhdl -lib work "../../trb3/cts/source/cts_fifo.vhd"
+add_file -vhdl -lib work "../../trb3/cts/source/cts_trg_input.vhd"
+add_file -vhdl -lib work "../../trb3/cts/source/cts_trg_coin.vhd"
+add_file -vhdl -lib work "../../trb3/cts/source/cts_trg_pseudorand_pulser.vhd"
+add_file -vhdl -lib work "../../trb3/cts/source/cts_trigger.vhd"
+add_file -vhdl -lib work "../../trb3/cts/source/cts.vhd"
+
+
+
+add_file -vhdl -lib work "./trb5sc_cts.vhd"
+#add_file -fpga_constraint "./synplify.fdc"
+
+
+
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.version.all;\r
+use work.config.all;\r
+use work.trb_net_std.all;\r
+use work.trb_net_components.all;\r
+use work.trb3_components.all;\r
+use work.med_sync_define.all;\r
+\r
+entity trb5sc_cts is\r
+ port(\r
+ CLK_200 : in std_logic;\r
+ CLK_125 : in std_logic;\r
+ CLK_EXT : in std_logic;\r
+\r
+ TRIG_IN_RJ45 : in std_logic; --Reference Time\r
+ IN_SELECT_EXT_CLOCK : in std_logic;\r
+\r
+ SFP_TX_DIS : out std_logic;\r
+ SFP_LOS : in std_logic;\r
+ SFP_MOD_0 : in std_logic;\r
+\r
+ \r
+ --ADC\r
+ ADC_SCLK : out std_logic;\r
+ ADC_NCS : out std_logic;\r
+ ADC_MOSI : out std_logic;\r
+ ADC_MISO : in std_logic;\r
+ --Flash, Reload\r
+ FLASH_SCLK : out std_logic;\r
+ FLASH_NCS : out std_logic;\r
+ FLASH_MOSI : out std_logic;\r
+ FLASH_MISO : in std_logic;\r
+ FLASH_HOLD : out std_logic;\r
+ FLASH_WP : out std_logic;\r
+ PROGRAMN : out std_logic;\r
+ --I2C\r
+ I2C_SDA : inout std_logic;\r
+ I2C_SCL : inout std_logic;\r
+ TMP_ALERT : in std_logic;\r
+\r
+ --LED\r
+ LED : out std_logic_vector(8 downto 1);\r
+ LED_SFP_YELLOW : out std_logic;\r
+ LED_SFP_GREEN : out std_logic;\r
+ LED_SFP_RED : out std_logic;\r
+ LED_RJ_GREEN : out std_logic_vector(1 downto 0);\r
+ LED_RJ_RED : out std_logic_vector(1 downto 0);\r
+ LED_EXT_CLOCK : out std_logic;\r
+\r
+ --Other Connectors\r
+ TEST : inout std_logic_vector(14 downto 1); --on v1 only\r
+ --COMMON_SDA, COMMON_SCL : inout std_logic\r
+ HDR_IO : inout std_logic_vector(23 downto 0) --23..16 on v2 only\r
+ );\r
+\r
+ attribute syn_useioff : boolean;\r
+ attribute syn_useioff of FLASH_NCS : signal is true;\r
+ attribute syn_useioff of FLASH_SCLK : signal is true;\r
+ attribute syn_useioff of FLASH_MOSI : signal is true;\r
+ attribute syn_useioff of FLASH_MISO : signal is true;\r
+\r
+end entity;\r
+\r
+architecture arch of trb5sc_adc is\r
+\r
+ constant ACTIVE_CHANNELS : integer := 5;\r
+\r
+ attribute syn_keep : boolean;\r
+ attribute syn_preserve : boolean;\r
+\r
+ signal clk_sys, clk_full, clk_full_osc : std_logic;\r
+ signal GSR_N : std_logic;\r
+ signal reset_i : std_logic;\r
+ signal clear_i : std_logic;\r
+ signal trigger_in_i : std_logic;\r
+\r
+ attribute syn_keep of GSR_N : signal is true;\r
+ attribute syn_preserve of GSR_N : signal is true;\r
+\r
+ signal debug_clock_reset : std_logic_vector(31 downto 0);\r
+ signal external_clock_lock : std_logic := '0';\r
+ signal debug_tools : std_logic_vector(31 downto 0);\r
+\r
+ --Media Interface\r
+ signal med2int : med2int_array_t(0 to 0);\r
+ signal int2med : int2med_array_t(0 to 0);\r
+ signal med_stat_debug : std_logic_vector (1*64-1 downto 0);\r
+ signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic;\r
+\r
+\r
+ signal readout_rx : READOUT_RX;\r
+ signal readout_tx : readout_tx_array_t(0 to ACTIVE_CHANNELS-1);\r
+\r
+ signal ctrlbus_tx, bussci_tx, bustools_tx, bustc_tx, bus_master_in, busadc_tx, busi2c_tx : CTRLBUS_TX;\r
+ signal ctrlbus_rx, bussci_rx, bustools_rx, bustc_rx, bus_master_out, busadc_rx, busi2c_rx : CTRLBUS_RX;\r
+\r
+ signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');\r
+ signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);\r
+\r
+ signal sed_error_i : std_logic;\r
+ signal clock_select : std_logic;\r
+ signal bus_master_active : std_logic;\r
+ signal flash_ncs_i : std_logic;\r
+\r
+ signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0);\r
+ signal header_io_i : std_logic_vector(10 downto 1);\r
+ signal timer : TIMERS;\r
+ signal add_reg : std_logic_vector(31 downto 0);\r
+ alias led_off : std_logic is add_reg(0);\r
+\r
+ signal gbe_status : std_logic_vector(15 downto 0);\r
+ signal adc_trigger_i : std_logic_vector(11 downto 0);\r
+\r
+ signal clk_350, clk_50, clk_200bypass : std_logic;\r
+\r
+ \r
+begin\r
+\r
+ trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK);\r
+\r
+---------------------------------------------------------------------------\r
+-- Clock & Reset Handling\r
+---------------------------------------------------------------------------\r
+ THE_CLOCK_RESET : entity work.clock_reset_handler\r
+ port map(\r
+ CLOCK_IN => CLK_200,\r
+ RESET_FROM_NET => med2int(0).stat_op(13),\r
+ SEND_RESET_IN => med2int(0).stat_op(15),\r
+\r
+ BUS_RX => bustc_rx,\r
+ BUS_TX => bustc_tx,\r
+\r
+ RESET_OUT => reset_i,\r
+ CLEAR_OUT => clear_i,\r
+ GSR_OUT => GSR_N,\r
+\r
+ REF_CLK_OUT => clk_full,\r
+ SYS_CLK_OUT => clk_sys,\r
+ RAW_CLK_OUT => clk_full_osc,\r
+\r
+ DEBUG_OUT => debug_clock_reset\r
+ );\r
+\r
+ THE_ADC_PLL : entity work.adc_pll\r
+ port map(\r
+ CLKI => clk_full_osc,\r
+ CLKOP => clk_350,\r
+ CLKOS => clk_50,\r
+ CLKOS2 => open\r
+ );\r
+ \r
+ CLK_A <= clk_50; \r
+ \r
+\r
+---------------------------------------------------------------------------\r
+-- TrbNet Uplink\r
+---------------------------------------------------------------------------\r
+\r
+ THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync\r
+ generic map(\r
+ SERDES_NUM => 0,\r
+ USE_NEW_ECP5_RESET => 1,\r
+ IS_SYNC_SLAVE => c_YES\r
+ )\r
+ port map(\r
+ CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full,\r
+ CLK_INTERNAL_FULL => clk_full_osc,\r
+ SYSCLK => clk_sys,\r
+ RESET => reset_i,\r
+ CLEAR => clear_i,\r
+ --Internal Connection\r
+ MEDIA_MED2INT => med2int(0),\r
+ MEDIA_INT2MED => int2med(0),\r
+\r
+ --Sync operation\r
+ RX_DLM => open,\r
+ RX_DLM_WORD => open,\r
+ TX_DLM => open,\r
+ TX_DLM_WORD => open,\r
+\r
+ --SFP Connection\r
+ SD_PRSNT_N_IN => sfp_prsnt_i,\r
+ SD_LOS_IN => sfp_los_i,\r
+ SD_TXDIS_OUT => sfp_txdis_i,\r
+ --Control Interface\r
+ BUS_RX => bussci_rx,\r
+ BUS_TX => bussci_tx,\r
+ -- Status and control port\r
+ STAT_DEBUG => med_stat_debug(63 downto 0),\r
+ CTRL_DEBUG => open\r
+ );\r
+\r
+ gen_sfp_con : if SERDES_NUM = 1 generate\r
+ sfp_los_i <= SFP_LOS;\r
+ sfp_prsnt_i <= SFP_MOD_0;\r
+ SFP_TX_DIS <= sfp_txdis_i;\r
+ end generate;\r
+ gen_bpl_con : if SERDES_NUM = 0 generate\r
+ sfp_los_i <= BACK_GPIO(1);\r
+ sfp_prsnt_i <= BACK_GPIO(1);\r
+ BACK_GPIO(0) <= sfp_txdis_i;\r
+ end generate;\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- Endpoint\r
+---------------------------------------------------------------------------\r
+ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record\r
+ generic map (\r
+ ADDRESS_MASK => x"FFFF",\r
+ BROADCAST_BITMASK => BROADCAST_BITMASK,\r
+ REGIO_INIT_ENDPOINT_ID => x"0001",\r
+ REGIO_USE_1WIRE_INTERFACE => c_I2C,\r
+ TIMING_TRIGGER_RAW => c_YES,\r
+ --Configure data handler\r
+ DATA_INTERFACE_NUMBER => ACTIVE_CHANNELS,\r
+ DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE,\r
+ DATA_BUFFER_WIDTH => 32,\r
+ DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE,\r
+ TRG_RELEASE_AFTER_DATA => c_YES,\r
+ HEADER_BUFFER_DEPTH => 9,\r
+ HEADER_BUFFER_FULL_THRESH => 2**9-16,\r
+ USE_GBE => USE_GBE\r
+ )\r
+\r
+ port map(\r
+ -- Misc\r
+ CLK => clk_sys,\r
+ RESET => reset_i,\r
+ CLK_125 => CLK_125,\r
+ CLEAR_N => GSR_N,\r
+\r
+ -- Media direction port\r
+ MEDIA_MED2INT => med2int(0),\r
+ MEDIA_INT2MED => int2med(0),\r
+\r
+ --Timing trigger in\r
+ TRG_TIMING_TRG_RECEIVED_IN => trigger_in_i,\r
+\r
+ READOUT_RX => readout_rx,\r
+ READOUT_TX => readout_tx,\r
+\r
+ --Slow Control Port\r
+ REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00\r
+ REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20\r
+ BUS_RX => ctrlbus_rx,\r
+ BUS_TX => ctrlbus_tx,\r
+ BUS_MASTER_IN => bus_master_in,\r
+ BUS_MASTER_OUT => bus_master_out,\r
+ BUS_MASTER_ACTIVE => bus_master_active,\r
+\r
+ ONEWIRE_INOUT => open,\r
+ I2C_SCL => I2C_SCL,\r
+ I2C_SDA => I2C_SDA,\r
+ --Timing registers\r
+ TIMERS_OUT => timer,\r
+ STATUS_GBE_OUT=> gbe_status\r
+ );\r
+\r
+---------------------------------------------------------------------------\r
+-- Bus Handler\r
+---------------------------------------------------------------------------\r
+ THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record\r
+ generic map(\r
+ PORT_NUMBER => 4,\r
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"9000", others => x"0000"),\r
+ PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, others => 0),\r
+ PORT_MASK_ENABLE => 1\r
+ )\r
+ port map(\r
+ CLK => clk_sys,\r
+ RESET => reset_i,\r
+\r
+ REGIO_RX => ctrlbus_rx,\r
+ REGIO_TX => ctrlbus_tx,\r
+\r
+ BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED\r
+ BUS_RX(1) => bussci_rx, --SCI Serdes\r
+ BUS_RX(2) => bustc_rx, --Clock switch\r
+ BUS_RX(3) => busadc_rx,\r
+ BUS_TX(0) => bustools_tx,\r
+ BUS_TX(1) => bussci_tx,\r
+ BUS_TX(2) => bustc_tx,\r
+ BUS_TX(3) => busadc_tx,\r
+ STAT_DEBUG => open\r
+ );\r
+\r
+---------------------------------------------------------------------------\r
+-- Control Tools\r
+---------------------------------------------------------------------------\r
+ THE_TOOLS : entity work.trb3sc_tools\r
+ generic map(\r
+ ADC_CMD_1 => x"2c3cb",\r
+ ADC_CMD_2 => x"1d5cb",\r
+ ADC_CMD_3 => x"1e3cb",\r
+ ADC_CMD_4 => x"2f5cb",\r
+ ADC_CMD_T => x"1F393"\r
+ )\r
+ port map(\r
+ CLK => clk_sys,\r
+ RESET => reset_i,\r
+\r
+ --Flash & Reload\r
+ FLASH_CS => flash_ncs_i,\r
+ FLASH_CLK => FLASH_SCLK,\r
+ FLASH_IN => FLASH_MISO,\r
+ FLASH_OUT => FLASH_MOSI,\r
+ PROGRAMN => PROGRAMN,\r
+ REBOOT_IN => common_ctrl_reg(15),\r
+ --SPI\r
+ SPI_CS_OUT => spi_cs,\r
+ SPI_MOSI_OUT => spi_mosi,\r
+ SPI_MISO_IN => spi_miso,\r
+ SPI_CLK_OUT => spi_clk,\r
+ --Header\r
+ --HEADER_IO => open,\r
+ -- HEADER_IO(7) => HDR_IO(6),\r
+ -- HEADER_IO(8) => HDR_IO(7),\r
+ ADDITIONAL_REG => add_reg,\r
+ --ADC\r
+ ADC_CS => ADC_NCS,\r
+ ADC_MOSI => ADC_MOSI,\r
+ ADC_MISO => ADC_MISO,\r
+ ADC_CLK => ADC_SCLK,\r
+ --Trigger & Monitor\r
+ MONITOR_INPUTS(11 downto 0) => adc_trigger_i,\r
+ MONITOR_INPUTS(15 downto 12) => x"0",\r
+ TRIG_GEN_INPUTS(11 downto 0) => adc_trigger_i,\r
+ TRIG_GEN_INPUTS(15 downto 12) => x"0",\r
+\r
+ TRIG_GEN_OUTPUTS(1 downto 0) => BACK_GPIO(3 downto 2),\r
+ TRIG_GEN_OUTPUTS(3 downto 2) => SPARE(1 downto 0),\r
+ --SED\r
+ SED_ERROR_OUT => sed_error_i,\r
+ --Slowcontrol\r
+ BUS_RX => bustools_rx,\r
+ BUS_TX => bustools_tx,\r
+ --Control master for default settings\r
+ BUS_MASTER_IN => bus_master_in,\r
+ BUS_MASTER_OUT => bus_master_out,\r
+ BUS_MASTER_ACTIVE => bus_master_active,\r
+ DEBUG_OUT => debug_tools\r
+ );\r
+\r
+\r
+\r
+ FLASH_HOLD <= '1';\r
+ FLASH_WP <= '1';\r
+\r
+\r
+ SCLK_A <= spi_clk(0);\r
+ CSB_A <= spi_cs(0);\r
+ SDIO_A <= spi_mosi(0);\r
+ spi_miso(0) <= SDIO_A when rising_edge(clk_sys);\r
+\r
+ \r
+---------------------------------------------------------------------------\r
+-- ADC ADDON\r
+--------------------------------------------------------------------------- \r
+ THE_ADDON : entity work.adc_addon\r
+ generic map(\r
+ ACTIVE_CHANNELS => ACTIVE_CHANNELS\r
+ )\r
+ port map(\r
+ CLK => clk_sys,\r
+ CLK_ADCBRAW => clk_full_osc,\r
+ CLK_ADCRAW => clk_350,\r
+ RESET => reset_i,\r
+ \r
+ FCO_A => FCO_A,\r
+ DATA_A => DATA_A,\r
+ DCO_A => DCO_A,\r
+ \r
+ DCO_B => DCO_B, \r
+ DATA_B => DATA_B, \r
+ CLK_B => CLK_B, \r
+ CNV_B => CNV_B, \r
+ TESTPAT_B => TESTPAT_B,\r
+ \r
+ TRIGGER_OUT => adc_trigger_i(ACTIVE_CHANNELS-1 downto 0),\r
+ READOUT_RX => readout_rx,\r
+ READOUT_TX => readout_tx,\r
+ \r
+ BUS_RX => busadc_rx,\r
+ BUS_TX => busadc_tx\r
+ \r
+ );\r
+ \r
+ \r
+---------------------------------------------------------------------------\r
+-- LED\r
+---------------------------------------------------------------------------\r
+\r
+ LED_SFP_GREEN <= not med2int(0).stat_op(9);\r
+ LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11));\r
+ LED_SFP_YELLOW <= not med2int(0).stat_op(8);\r
+ LED <= x"FF";\r
+ LED_RJ_GREEN(1)<= not external_clock_lock or led_off; --on if external clock used\r
+ LED_RJ_GREEN(0)<= '1' when SERDES_NUM = 0 or led_off = '1' else '0'; --on if SFP is used (next to SFP)\r
+ LED_RJ_RED(1) <= external_clock_lock or led_off; --on if internal clock used\r
+ LED_RJ_RED(0) <= '1' when SERDES_NUM = 1 or led_off = '1' else '0'; --on if backplane is used (next to SFP)\r
+ LED_EXT_CLOCK <= IN_SELECT_EXT_CLOCK or led_off; --on if trigger/clock from RJ45 is used\r
+\r
+ TEST(13 downto 1) <= (others => '0');\r
+ TEST(14) <= flash_ncs_i; --for v1 boards\r
+\r
+ FLASH_NCS <= flash_ncs_i;\r
+\r
+ \r
+ \r
+ \r
+end architecture;\r
jspc29 / trb5sc.git / commitdiff