constant EVENT_MAX_SIZE : integer := 4096; --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2
--Include SPI on AddOn connector
- constant INCLUDE_SPI : integer := c_NO;
- constant SPI_FOR_PADI : integer := c_NO; -- YES: PADI SPI NO: Normal SPI
+ constant INCLUDE_UART : integer := c_YES;
+ constant INCLUDE_SPI : integer := c_YES;
+ constant INCLUDE_LCD : integer := c_NO;
+ constant INCLUDE_DEBUG_INTERFACE: integer := c_YES;
+ --constant SPI_FOR_PADI : integer := c_NO; -- YES: PADI SPI NO: Normal SPI
--Add logic to generate configurable trigger signal from input signals.
- constant INCLUDE_TRIGGER_LOGIC : integer := c_NO;
+ constant INCLUDE_TRIGGER_LOGIC : integer := c_YES;
constant INCLUDE_STATISTICS : integer := c_NO; --Do histos of all inputs
constant PHYSICAL_INPUTS : integer := 32; --number of inputs connected
+ constant TRIG_GEN_OUTPUT_NUM : integer := 4;
+ constant MONITOR_INPUT_NUM : integer := PHYSICAL_INPUTS+TRIG_GEN_OUTPUT_NUM;
+ constant TRIG_GEN_INPUT_NUM : integer := PHYSICAL_INPUTS;
constant USE_SINGLE_FIFO : integer := c_YES; -- single fifo for statistics
--Run wih 125 MHz instead of 100 MHz, use received clock from serdes or external clock input
--End of design configuration
------------------------------------------------------------------------------
+ type data_t is array (0 to 1023) of std_logic_vector(7 downto 0);
+ constant LCD_DATA : data_t;
------------------------------------------------------------------------------
--Select settings by configuration
+++ /dev/null
-config_compile_gsi.pl
\ No newline at end of file
-TOPNAME => "trb3_periph_ADA_Addon",
+TOPNAME => "trb3_periph_ADA",
project_path => "ADA_Addon",
-lm_license_file_for_synplify => "1702\@hadeb05.gsi.de", #"27000\@lxcad01.gsi.de";
+lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
lm_license_file_for_par => "1702\@hadeb05.gsi.de",
-lattice_path => '/d/jspc29/lattice/diamond/3.5_x64',
-synplify_path => '/d/jspc29/lattice/synplify/J-2014.09-SP2/',
-synplify_command => "/d/jspc29/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options",
+lattice_path => '/d/jspc29/lattice/diamond/3.6_x64',
+synplify_path => '/d/jspc29/lattice/synplify/K-2015.09/',
+# synplify_command => "/d/jspc29/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options",
#synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
nodelist_file => 'nodelist_frankfurt.txt',
-../../tdc/releases/tdc_v2.3
\ No newline at end of file
+../../tdc/releases/tdc_v2.3.1
\ No newline at end of file
add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd"
add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd"
add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"
add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
-add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd"
add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_9x2k_oreg.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
add_file -vhdl -lib work "../base/cores/pll_in200_out100.vhd"
-add_file -vhdl -lib work "../base/code/input_to_trigger_logic.vhd"
+add_file -vhdl -lib work "../base/code/input_to_trigger_logic_record.vhd"
add_file -vhdl -lib work "../base/code/input_statistics.vhd"
add_file -vhdl -lib work "../base/code/sedcheck.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd"
+add_file -vhdl -lib work "../base/code/trb3_tools.vhd"
+
add_file -vhdl -lib work "tdc_release/tdc_components.vhd"
add_file -vhdl -lib work "tdc_release/bit_sync.vhd"