added testbench stuff

diff --git a/vldb/testbench/tb_gbt_core.vhd b/vldb/testbench/tb_gbt_core.vhd
new file mode 100644 (file)
index 0000000..1fc8076
--- /dev/null
+++ b/vldb/testbench/tb_gbt_core.vhd
@@ -0,0 +1,37 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+
+entity tb_gbt_core is
+end entity;
+
+architecture arch of tb_gbt_core is
+
+  signal clk                    : std_logic := '0';
+  signal clk_sys                : std_logic := '0';
+  signal reset                  : std_logic := '0';
+  signal bus_rx                 : CTRLBUS_RX;
+  signal bus_tx                 : CTRLBUS_TX;
+
+  begin
+
+    THE_GBT_CORE : entity work.gbt_core
+      port map(
+        CLK_SYS   => clk_sys,
+        CLK       => clk,
+        RESET     => reset,
+
+        BUS_RX    => bus_rx,
+        BUS_TX    => bus_tx,
+
+        ELINK_RX  => '0',
+        ELINK_TX  => open
+);
+
+     clk <= not(clk) after 6.25 ns;
+     clk_sys <= not(clk_sys) after 5 ns;
+
+end architecture;

diff --git a/vldb/testbench/testbench.tcl b/vldb/testbench/testbench.tcl
new file mode 100644 (file)
index 0000000..21e38f2
--- /dev/null
+++ b/vldb/testbench/testbench.tcl
@@ -0,0 +1,203 @@
+proc compile_project {} {
+
+       set library_file_list {
+               work {
+                               ../code/GBT-SC/SCA/sca_pkg.vhd
+                               ../code/GBT-SC/SCA/sca_tx.vhd
+                               ../code/GBT-SC/SCA/sca_rx_fifo.vhd
+                               ../code/GBT-SC/SCA/sca_deserializer.vhd
+                               ../code/GBT-SC/SCA/sca_rx.vhd
+                               ../code/GBT-SC/SCA/sca_top.vhd
+                               ../code/GBT-SC/IC/ic_deserializer.vhd
+                               ../code/GBT-SC/IC/ic_rx_fifo.vhd
+                               ../code/GBT-SC/IC/ic_rx.vhd
+                               ../code/GBT-SC/IC/ic_tx.vhd
+                               ../code/GBT-SC/IC/ic_top.vhd
+                               ../code/GBT-SC/gbtsc_top.vhd
+                ../../../trbnet/basics/pulse_sync.vhd
+                ../../../trbnet/basics/signal_sync.vhd
+                           ../../../trbnet/trb_net_std.vhd
+                               ../code/gbt_core.vhd
+                               tb_gbt_core.vhd
+                               }
+       }
+
+       foreach {library file_list} $library_file_list {
+         vlib $library
+         vmap work $library
+         foreach file $file_list {
+                 vcom -2008 $file
+               }
+       }
+}
+
+
+proc simulate {{restart "restart"}} {
+
+       if { $restart == "start" } {
+               eval vsim work.tb_gbt_core -novopt
+               reset_waves 0
+       }
+
+       restart -force
+
+       run 50ns
+
+       wave zoom full
+
+       send_reset
+       # send_reset_go
+       # send_connect_go
+}
+
+
+proc reset_waves { verbosity } {
+       delete wave *
+
+       add wave -noupdate -divider -height 20 "Reset, Clock, Enable"
+       add wave -label "TB Clock 80"                   sim:/tb_gbt_core/clk
+       add wave -label "TB Clock 100"                  sim:/tb_gbt_core/clk_sys
+       add wave -label "TB Reset"                      sim:/tb_gbt_core/reset
+
+       add wave -label "Core Clock TX EN"      sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_tx_clk_en
+       # add wave -label "Core Clock RX EN"    sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_rx_clk_en
+
+       add wave -noupdate -divider -height 20 "HDLC"
+       add wave -label "Core From SCA"                 sim:/tb_gbt_core/THE_GBT_CORE/ELINK_TX
+       add wave -label "Core To SCA"               sim:/tb_gbt_core/THE_GBT_CORE/ELINK_RX
+
+       add wave -noupdate -divider -height 20 "Bus"
+       add wave -label "TB BUS_RX"                     sim:/tb_gbt_core/bus_rx
+       add wave -label "TB BUS_TX"                     sim:/tb_gbt_core/bus_tx
+
+       add wave -noupdate -divider -height 20 "Control"
+       # add wave -label "Core SCA Enable"             sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_sca_enable_i
+       add wave -label "Core Start Reset CMD"  sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_start_reset_cmd_i
+       # add wave -label "Core Start Reset GO"   sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_reset_go
+       add wave -label "Core Start Connect CMD"  sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_start_connect_cmd_i
+       # add wave -label "Core Start Connect GO" sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_connect_go
+       add wave -label "Core Start Command"    sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_start_command_i
+       # add wave -label "Core Start Command GO"       sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_go
+
+       add wave -noupdate -divider -height 20 "Command"
+       add wave -label "Core Address"  sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_tx_address_i
+       add wave -label "Core Trans ID" sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_tx_transID_i
+       add wave -label "Core Channel"  sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_tx_channel_i
+       add wave -label "Core Command"  sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_tx_command_i
+       add wave -label "Core Data"     sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_tx_data_i
+}
+
+
+proc send_reset {} {
+
+       force -freeze sim:/tb_gbt_core/reset 0 0
+       force -freeze sim:/tb_gbt_core/reset 1 50 ns
+       force -freeze sim:/tb_gbt_core/reset 0 100 ns
+
+       run 500ns
+       wave zoom full
+}
+
+
+proc send_reset_go {} {
+
+       force -freeze sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_reset_go 0 0
+       force -freeze sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_reset_go 1 10 ns
+       force -freeze sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_reset_go 0 20 ns
+
+       run 2500ns
+       wave zoom full
+}
+
+proc send_reset_bus {} {
+
+       force -freeze sim:/tb_gbt_core/bus_rx.write 0 0
+       force -freeze sim:/tb_gbt_core/bus_rx.read 0 0
+
+       set data 0x00000300
+       set addr 0x0000
+       force -freeze sim:/tb_gbt_core/bus_rx.data 8'h$data 500 ns
+       force -freeze sim:/tb_gbt_core/bus_rx.addr 8'h$addr 500 ns
+       force -freeze sim:/tb_gbt_core/bus_rx.write 1 500 ns
+
+       set data 0x00000000
+       set addr 0x0000
+       force -freeze sim:/tb_gbt_core/bus_rx.data 8'h$data 510 ns
+       force -freeze sim:/tb_gbt_core/bus_rx.addr 8'h$addr 510 ns
+       force -freeze sim:/tb_gbt_core/bus_rx.write 1 510 ns
+
+       force -freeze sim:/tb_gbt_core/bus_rx.write 0 520 ns
+
+       run 2500ns
+       wave zoom full
+}
+
+
+
+proc send_connect_go {} {
+
+       force -freeze sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_connect_go 0 0
+       force -freeze sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_connect_go 1 500 ns
+       force -freeze sim:/tb_gbt_core/THE_GBT_CORE/gbtsc_connect_go 0 1000 ns
+
+       run 2500ns
+       wave zoom full
+}
+
+
+proc send_connect_bus {} {
+
+       force -freeze sim:/tb_gbt_core/bus_rx.write 0 0
+       force -freeze sim:/tb_gbt_core/bus_rx.read 0 0
+
+       set data 0x00000500
+       set addr 0x0000
+       force -freeze sim:/tb_gbt_core/bus_rx.data 8'h$data 500 ns
+       force -freeze sim:/tb_gbt_core/bus_rx.addr 8'h$addr 500 ns
+       force -freeze sim:/tb_gbt_core/bus_rx.write 1 500 ns
+
+       set data 0x00000000
+       set addr 0x0000
+       force -freeze sim:/tb_gbt_core/bus_rx.data 8'h$data 510 ns
+       force -freeze sim:/tb_gbt_core/bus_rx.addr 8'h$addr 510 ns
+       force -freeze sim:/tb_gbt_core/bus_rx.write 1 510 ns
+
+       force -freeze sim:/tb_gbt_core/bus_rx.write 0 520 ns
+
+       run 2500ns
+       wave zoom full
+}
+
+
+proc send_command_bus {} {
+
+       force -freeze sim:/tb_gbt_core/bus_rx.write 0 0
+       force -freeze sim:/tb_gbt_core/bus_rx.read 0 0
+
+       #set channel, command, etc.
+       set addr 0x0001
+       set data 0x02000001
+       force -freeze sim:/tb_gbt_core/bus_rx.addr 8'h$addr 500 ns
+       force -freeze sim:/tb_gbt_core/bus_rx.data 8'h$data 500 ns
+       force -freeze sim:/tb_gbt_core/bus_rx.write 1 500 ns
+
+       #set data
+       set addr 0x0002
+       set data 0x0000ff00
+       force -freeze sim:/tb_gbt_core/bus_rx.addr 8'h$addr 510 ns
+       force -freeze sim:/tb_gbt_core/bus_rx.data 8'h$data 510 ns
+       force -freeze sim:/tb_gbt_core/bus_rx.write 1 510 ns
+
+       #start
+       set addr 0x0000
+       set data 0x00000800
+       force -freeze sim:/tb_gbt_core/bus_rx.addr 8'h$addr 520 ns
+       force -freeze sim:/tb_gbt_core/bus_rx.data 8'h$data 520 ns
+       force -freeze sim:/tb_gbt_core/bus_rx.write 1 520 ns
+
+       force -freeze sim:/tb_gbt_core/bus_rx.write 0 530 ns
+
+    # run -all
+       run 2500ns
+       wave zoom full
+}