ADDR_IN : in std_logic_vector(15 downto 0) := (others => '0')
);
- end component;
+ end component;
+
+ component input_statistics is
+ generic (
+ INPUTS : integer range 1 to 32);
+ port (
+ CLK : in std_logic;
+ INPUT : in std_logic_vector(INPUTS-1 downto 0);
+ DATA_IN : in std_logic_vector(31 downto 0) := (others => '0');
+ DATA_OUT : out std_logic_vector(31 downto 0);
+ WRITE_IN : in std_logic := '0';
+ READ_IN : in std_logic := '0';
+ ACK_OUT : out std_logic;
+ NACK_OUT : out std_logic;
+ ADDR_IN : in std_logic_vector(15 downto 0) := (others => '0'));
+ end component input_statistics;
component serdes_full_ctc is