fixed reset issue on rx_rsl.vhd

diff --git a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
index 03de147d278aa47c9e14173d5edb7796aef34dce..25202659f3f0a6e5f6371429177a86f191efec12 100644 (file)
--- a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
+++ b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
@@ -163,17 +163,21 @@ begin
 -------------------------------------------------
 -- BUG: link_tx_ready(i) for master ports to be included
 -- BUG: slave ports need also disable with link_tx_ready(i)
-  SD_TXDIS_OUT(3) <= DESTROY_LINK_IN(3) when IS_MODE(3) = c_IS_MASTER else 
-                     '1'                when IS_MODE(3) = c_IS_UNUSED else
+  SD_TXDIS_OUT(3) <= DESTROY_LINK_IN(3)     when IS_MODE(3) = c_IS_MASTER else
+                     not link_rx_ready_i(3) when IS_MODE(3) = c_IS_SLAVE  else
+                     '1'                    when IS_MODE(3) = c_IS_UNUSED else
                      '0';
-  SD_TXDIS_OUT(2) <= DESTROY_LINK_IN(2) when IS_MODE(2) = c_IS_MASTER else 
-                     '1'                when IS_MODE(2) = c_IS_UNUSED else
+  SD_TXDIS_OUT(2) <= DESTROY_LINK_IN(2)     when IS_MODE(2) = c_IS_MASTER else 
+                     not link_rx_ready_i(2) when IS_MODE(2) = c_IS_SLAVE  else
+                     '1'                    when IS_MODE(2) = c_IS_UNUSED else
                      '0';
-  SD_TXDIS_OUT(1) <= DESTROY_LINK_IN(1) when IS_MODE(1) = c_IS_MASTER else 
-                     '1'                when IS_MODE(1) = c_IS_UNUSED else
+  SD_TXDIS_OUT(1) <= DESTROY_LINK_IN(1)     when IS_MODE(1) = c_IS_MASTER else 
+                     not link_rx_ready_i(1) when IS_MODE(1) = c_IS_SLAVE  else
+                     '1'                    when IS_MODE(1) = c_IS_UNUSED else
                      '0';
-  SD_TXDIS_OUT(0) <= DESTROY_LINK_IN(0) when IS_MODE(0) = c_IS_MASTER else 
-                     '1'                when IS_MODE(0) = c_IS_UNUSED else
+  SD_TXDIS_OUT(0) <= DESTROY_LINK_IN(0)     when IS_MODE(0) = c_IS_MASTER else 
+                     not link_rx_ready_i(0) when IS_MODE(0) = c_IS_SLAVE  else
+                     '1'                    when IS_MODE(0) = c_IS_UNUSED else
                      '0';
 
 -------------------------------------------------      

diff --git a/media_interfaces/sync/med_sync_control_RS.vhd b/media_interfaces/sync/med_sync_control_RS.vhd
index 61bf2737e92293da531054a846db47c886a102ac..8f6eda776d5b99037b1681327ade230d54598490 100644 (file)
--- a/media_interfaces/sync/med_sync_control_RS.vhd
+++ b/media_interfaces/sync/med_sync_control_RS.vhd
@@ -124,13 +124,14 @@ begin
 -------------------------------------------------
   THE_RX_RST_FSM: rx_rsl
     port map(
-      CLEAR             => GLOBAL_RESET_IN,
+      CLEAR             => '0', --GLOBAL_RESET_IN,
       CLK_REF           => CLK_REF,
       PLL_LOL_IN        => TX_PLL_LOL_IN,
       CDR_LOL_IN        => RX_CDR_LOL_IN,
       CV_IN             => RX_CV_IN,
       LSM_IN            => RX_LSM_IN,
       LOS_IN            => RX_LOS_IN,
+      SD_LOS_IN         => SFP_LOS_IN,
       WAP_ZERO_IN       => is_wap_zero_i,
       -- outputs
       RX_SERDES_RST_OUT => rx_serdes_rst_i,

diff --git a/media_interfaces/sync/med_sync_define_RS.vhd b/media_interfaces/sync/med_sync_define_RS.vhd
index b52e551fa5ea2564df9a6b843432102febd9d172..49c8052df9f5ee50818cc4e5d4b74903a0faf7f5 100644 (file)
--- a/media_interfaces/sync/med_sync_define_RS.vhd
+++ b/media_interfaces/sync/med_sync_define_RS.vhd
@@ -34,6 +34,7 @@ component rx_rsl is
     CV_IN             : in  std_logic;\r
     LSM_IN            : in  std_logic;\r
     LOS_IN            : in  std_logic;\r
+    SD_LOS_IN         : in  std_logic;\r
     WAP_ZERO_IN       : in  std_logic;\r
     -- outputs\r
     RX_SERDES_RST_OUT : out std_logic;\r

diff --git a/media_interfaces/sync/rx_rsl.vhd b/media_interfaces/sync/rx_rsl.vhd
index 91cfdca84b91740006a4614916634cf735223fe2..a6b725acc7b01d4f564ef903fa35989a52c943b5 100644 (file)
--- a/media_interfaces/sync/rx_rsl.vhd
+++ b/media_interfaces/sync/rx_rsl.vhd
@@ -11,6 +11,7 @@ entity rx_rsl is
     CV_IN             : in  std_logic;\r
     LSM_IN            : in  std_logic;\r
     LOS_IN            : in  std_logic;\r
+    SD_LOS_IN         : in  std_logic;\r
     WAP_ZERO_IN       : in  std_logic;\r
     -- outputs\r
     RX_SERDES_RST_OUT : out std_logic;\r
@@ -38,6 +39,7 @@ architecture rx_rsl_arc of rx_rsl is
   signal cv_s         : std_logic;\r
   signal lsm_s        : std_logic;\r
   signal los_s        : std_logic;\r
+  signal sd_los_s     : std_logic;\r
 \r
   signal cnt          : unsigned(31 downto 0);\r
 \r
@@ -64,6 +66,7 @@ begin
     cv_s              <= '1';\r
     lsm_s             <= '0';\r
     los_s             <= '1';\r
+    sd_los_s          <= '1';\r
 \r
     RX_SERDES_RST_OUT <= '1';\r
     RX_PCS_RST_OUT    <= '1';\r
@@ -77,7 +80,8 @@ begin
     cdr_lol_s     <= CDR_LOL_IN;\r
     cv_s          <= CV_IN;    \r
     lsm_s         <= LSM_IN;    \r
-    los_s         <= LOS_IN;  \r
+    los_s         <= LOS_IN; \r
+    sd_los_s      <= SD_LOS_IN;\r
   \r
     case rx_sm is\r
       when POWERUP =>\r
@@ -85,7 +89,7 @@ begin
         RX_SERDES_RST_OUT <= '0'; -- needed for RX_LOS to be active\r
         RX_PCS_RST_OUT    <= '1';\r
         LINK_RX_READY_OUT <= '0';\r
-        if( (pll_lol_s = '1') or (los_s = '1') ) then\r
+        if( (pll_lol_s = '1') or (los_s = '1') or (sd_los_s = '1') ) then\r
           cnt <= (others => '0');\r
         else\r
           if( cnt = Tplol ) then\r
@@ -213,7 +217,8 @@ begin
   \r
 ------------------------------------------------\r
 --  if (pll_lol_s = '1') or (los_s = '1') then\r
-    if( pll_lol_s = '1' ) then\r
+--    if( pll_lol_s = '1' ) then\r
+    if( (pll_lol_s = '1') or (sd_los_s = '1') ) then\r
       rx_sm <= POWERUP;      \r
       cnt <= (others => '0');\r
     end if;\r