--- /dev/null
+
+LIBRARY ieee ;
+LIBRARY work ;
+USE ieee.NUMERIC_STD.all ;
+USE ieee.std_logic_1164.all ;
+USE work.med_sync_define.all ;
+USE work.trb_net_components.all ;
+USE work.trb_net_std.all ;
+
+entity med_sync_tb is
+end entity;
+
+architecture arch of med_sync_tb is
+
+
+
+component med_sync_control is
+ generic(
+ IS_SYNC_SLAVE : integer := 1;
+ IS_TX_RESET : integer := 1
+ );
+ port(
+ CLK_SYS : in std_logic;
+ CLK_RXI : in std_logic;
+ CLK_RXHALF : in std_logic;
+ CLK_TXI : in std_logic;
+ CLK_REF : in std_logic;
+ RESET : in std_logic;
+ CLEAR : in std_logic;
+
+ SFP_LOS : in std_logic;
+ TX_LOL : in std_logic;
+ RX_CDR_LOL : in std_logic;
+ RX_LOS : in std_logic;
+ WA_POSITION : in std_logic_vector(3 downto 0);
+
+ RX_SERDES_RST : out std_logic;
+ RX_PCS_RST : out std_logic;
+ QUAD_RST : out std_logic;
+ TX_PCS_RST : out std_logic;
+
+ MEDIA_MED2INT : out MED2INT;
+ MEDIA_INT2MED : in INT2MED;
+
+ TX_DATA : out std_logic_vector(7 downto 0);
+ TX_K : out std_logic;
+ RX_DATA : in std_logic_vector(7 downto 0);
+ RX_K : in std_logic;
+
+ TX_DLM_WORD : in std_logic_vector(7 downto 0);
+ TX_DLM : in std_logic;
+ RX_DLM_WORD : out std_logic_vector(7 downto 0);
+ RX_DLM : out std_logic;
+
+ SERDES_RX_READY_IN : in std_logic := '1';
+ SERDES_TX_READY_IN : in std_logic := '1';
+
+ STAT_TX_CONTROL : out std_logic_vector(31 downto 0);
+ STAT_RX_CONTROL : out std_logic_vector(31 downto 0);
+ DEBUG_TX_CONTROL : out std_logic_vector(31 downto 0);
+ DEBUG_RX_CONTROL : out std_logic_vector(31 downto 0);
+ STAT_RESET : out std_logic_vector(31 downto 0);
+ DEBUG_OUT : out std_logic_vector(31 downto 0)
+ );
+end component;
+
+
+signal clk_100_m, clk_100_s : std_logic := '1';
+signal clk_200_m, clk_200_s : std_logic := '1';
+
+signal reset_m : std_logic := '1';
+signal clear_m : std_logic := '1';
+signal reset_s : std_logic := '1';
+signal clear_s : std_logic := '1';
+
+
+signal med2int_m, med2int_s : MED2INT;
+signal int2med_m, int2med_s : INT2MED;
+
+signal tx_data_m, tx_data_s, rx_data_m, rx_data_s : std_logic_vector(7 downto 0);
+signal tx_k_m, tx_k_s, rx_k_m, rx_k_s : std_logic;
+
+
+begin
+
+reset_m <= '0' after 201 ns;
+clear_m <= '0' after 51 ns;
+reset_s <= '0' after 201 ns;
+clear_s <= '0' after 51 ns;
+
+rx_data_s <= transport tx_data_m after 250 ns;
+rx_data_m <= transport tx_data_s after 250 ns;
+rx_k_s <= transport tx_k_m after 250 ns;
+rx_k_m <= transport tx_k_s after 250 ns;
+
+clk_100_m <= not clk_100_m after 5 ns;
+clk_200_m <= not clk_200_m after 2.5 ns;
+clk_100_s <= not clk_100_s after 5 ns;
+clk_200_s <= not clk_200_s after 2.5 ns;
+
+
+
+
+process begin
+ int2med_m.ctrl_op <= x"0000";
+ int2med_s.ctrl_op <= x"0000";
+ int2med_m.data <= x"0000";
+ int2med_m.packet_num <= "000";
+ int2med_m.dataready <= '0';
+ wait for 50 us;
+ wait until rising_edge(clk_100_m); wait for 1 ns;
+ int2med_m.data <= x"1122";
+ int2med_m.packet_num <= "100";
+ int2med_m.dataready <= '1';
+ wait until rising_edge(clk_100_m); wait for 1 ns;
+ int2med_m.data <= x"3344";
+ int2med_m.packet_num <= "000";
+ int2med_m.dataready <= '1';
+ wait until rising_edge(clk_100_m); wait for 1 ns;
+ int2med_m.data <= x"5566";
+ int2med_m.packet_num <= "001";
+ int2med_m.dataready <= '1';
+ wait until rising_edge(clk_100_m); wait for 1 ns;
+ int2med_m.data <= x"7788";
+ int2med_m.packet_num <= "010";
+ int2med_m.dataready <= '1';
+ wait until rising_edge(clk_100_m); wait for 1 ns;
+ int2med_m.data <= x"9900";
+ int2med_m.packet_num <= "011";
+ int2med_m.dataready <= '1';
+ wait until rising_edge(clk_100_m); wait for 1 ns;
+ int2med_m.dataready <= '0';
+
+end process;
+
+
+
+THE_MASTER : med_sync_control
+ generic map(
+ IS_SYNC_SLAVE => 0,
+ IS_TX_RESET => 0
+ )
+ port map(
+ CLK_SYS => clk_100_m,
+ CLK_RXI => clk_200_s,
+ CLK_RXHALF => clk_100_s,
+ CLK_TXI => clk_200_m,
+ CLK_REF => clk_200_m,
+ RESET => reset_m,
+ CLEAR => clear_m,
+
+ SFP_LOS => '0',
+ TX_LOL => '0',
+ RX_CDR_LOL => '0',
+ RX_LOS => '0',
+ WA_POSITION => x"0",
+
+ RX_SERDES_RST=> open,
+ RX_PCS_RST => open,
+ QUAD_RST => open,
+ TX_PCS_RST => open,
+
+ MEDIA_MED2INT => med2int_m,
+ MEDIA_INT2MED => int2med_m,
+
+ TX_DATA => tx_data_m,
+ TX_K => tx_k_m,
+ RX_DATA => rx_data_m,
+ RX_K => rx_k_m,
+
+ TX_DLM_WORD => x"00",
+ TX_DLM => '0',
+ RX_DLM_WORD => open,
+ RX_DLM => open,
+
+ SERDES_RX_READY_IN => '1',
+ SERDES_TX_READY_IN => '1',
+ STAT_TX_CONTROL => open,
+ STAT_RX_CONTROL => open,
+ DEBUG_TX_CONTROL => open,
+ DEBUG_RX_CONTROL => open,
+ STAT_RESET => open,
+ DEBUG_OUT => open
+ );
+
+
+
+THE_SLAVE : med_sync_control
+ generic map(
+ IS_SYNC_SLAVE => 1,
+ IS_TX_RESET => 0
+ )
+ port map(
+ CLK_SYS => clk_100_s,
+ CLK_RXI => clk_200_m,
+ CLK_RXHALF => clk_100_m,
+ CLK_TXI => clk_200_s,
+ CLK_REF => clk_200_s,
+ RESET => reset_s,
+ CLEAR => clear_s,
+
+ SFP_LOS => '0',
+ TX_LOL => '0',
+ RX_CDR_LOL => '0',
+ RX_LOS => '0',
+ WA_POSITION => x"0",
+
+ RX_SERDES_RST=> open,
+ RX_PCS_RST => open,
+ QUAD_RST => open,
+ TX_PCS_RST => open,
+
+ MEDIA_MED2INT => med2int_s,
+ MEDIA_INT2MED => int2med_s,
+
+ TX_DATA => tx_data_s,
+ TX_K => tx_k_s,
+ RX_DATA => rx_data_s,
+ RX_K => rx_k_s,
+
+ TX_DLM_WORD => x"00",
+ TX_DLM => '0',
+ RX_DLM_WORD => open,
+ RX_DLM => open,
+
+ SERDES_RX_READY_IN => '1',
+ SERDES_TX_READY_IN => '1',
+ STAT_TX_CONTROL => open,
+ STAT_RX_CONTROL => open,
+ DEBUG_TX_CONTROL => open,
+ DEBUG_RX_CONTROL => open,
+ STAT_RESET => open,
+ DEBUG_OUT => open
+ );
+
+end architecture;
jspc29 / trbnet.git / commitdiff