<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="lattice_ecp3_fifo_18x16_dualport_oreg" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 01 23 17:47:10.972" version="5.7" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="lattice_ecp3_fifo_18x16_dualport_oreg" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 04 24 16:53:33.866" version="5.7" type="Module" synthesis="synplify" source_format="VHDL">
<Package>
- <File name="lattice_ecp3_fifo_18x16_dualport_oreg.lpc" type="lpc" modified="2015 01 23 17:47:08.000"/>
- <File name="lattice_ecp3_fifo_18x16_dualport_oreg.vhd" type="top_level_vhdl" modified="2015 01 23 17:47:08.000"/>
- <File name="lattice_ecp3_fifo_18x16_dualport_oreg_tmpl.vhd" type="template_vhdl" modified="2015 01 23 17:47:08.000"/>
- <File name="tb_lattice_ecp3_fifo_18x16_dualport_oreg_tmpl.vhd" type="testbench_vhdl" modified="2015 01 23 17:47:08.000"/>
+ <File name="lattice_ecp3_fifo_18x16_dualport_oreg.lpc" type="lpc" modified="2015 04 24 16:53:32.000"/>
+ <File name="lattice_ecp3_fifo_18x16_dualport_oreg.vhd" type="top_level_vhdl" modified="2015 04 24 16:53:32.000"/>
+ <File name="lattice_ecp3_fifo_18x16_dualport_oreg_tmpl.vhd" type="template_vhdl" modified="2015 04 24 16:53:32.000"/>
+ <File name="tb_lattice_ecp3_fifo_18x16_dualport_oreg_tmpl.vhd" type="testbench_vhdl" modified="2015 04 24 16:53:32.000"/>
</Package>
</DiamondModule>
ModuleName=lattice_ecp3_fifo_18x16_dualport_oreg
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=01/23/2015
-Time=17:47:08
+Date=04/24/2015
+Time=16:53:32
[Parameters]
Verilog=0
-- Module Version: 5.7
--/d/jspc29/lattice/diamond/3.4_x64/ispfpga/bin/lin64/scuba -w -n lattice_ecp3_fifo_18x16_dualport_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 16 -width 18 -depth 16 -rdata_width 18 -regout -no_enable -pe -1 -pf 7
--- Fri Jan 23 17:47:08 2015
+-- Fri Apr 24 16:53:32 2015
library IEEE;
use IEEE.std_logic_1164.all;
<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_sync_3" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 05 20 11:29:42.301" version="8.1" type="Module" synthesis="" source_format="VHDL">
+<DiamondModule name="serdes_sync_3" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 05 26 18:57:42.046" version="8.1" type="Module" synthesis="" source_format="VHDL">
<Package>
- <File name="serdes_sync_3.lpc" type="lpc" modified="2015 05 20 11:29:40.000"/>
- <File name="serdes_sync_3.pp" type="pp" modified="2015 05 20 11:29:40.000"/>
- <File name="serdes_sync_3.sym" type="sym" modified="2015 05 20 11:29:41.000"/>
- <File name="serdes_sync_3.tft" type="tft" modified="2015 05 20 11:29:40.000"/>
- <File name="serdes_sync_3.txt" type="pcs_module" modified="2015 05 20 11:29:40.000"/>
- <File name="serdes_sync_3.vhd" type="top_level_vhdl" modified="2015 05 20 11:29:40.000"/>
+ <File name="serdes_sync_3.lpc" type="lpc" modified="2015 05 26 18:57:40.000"/>
+ <File name="serdes_sync_3.pp" type="pp" modified="2015 05 26 18:57:40.000"/>
+ <File name="serdes_sync_3.sym" type="sym" modified="2015 05 26 18:57:40.000"/>
+ <File name="serdes_sync_3.tft" type="tft" modified="2015 05 26 18:57:40.000"/>
+ <File name="serdes_sync_3.txt" type="pcs_module" modified="2015 05 26 18:57:40.000"/>
+ <File name="serdes_sync_3.vhd" type="top_level_vhdl" modified="2015 05 26 18:57:40.000"/>
</Package>
</DiamondModule>
ModuleName=serdes_sync_3
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=05/20/2015
-Time=11:29:40
+Date=05/26/2015
+Time=18:57:40
[Parameters]
Verilog=0
_pll_rxsrc0=INTERNAL
_pll_rxsrc1=EXTERNAL
_pll_rxsrc2=EXTERNAL
-_pll_rxsrc3=EXTERNAL
+_pll_rxsrc3=INTERNAL
Multiplier0=
Multiplier1=
Multiplier2=
CH1_MODE "DISABLED"
CH2_MODE "DISABLED"
CH3_MODE "RXTX"
-CH3_CDR_SRC "REFCLK_EXT"
+CH3_CDR_SRC "REFCLK_CORE"
PLL_SRC "REFCLK_CORE"
TX_DATARATE_RANGE "MEDHIGH"
CH3_RX_DATARATE_RANGE "MEDHIGH"
-- CH0_CDR_SRC : String := "REFCLK_CORE";
-- CH1_CDR_SRC : String := "REFCLK_EXT";
-- CH2_CDR_SRC : String := "REFCLK_EXT";
--- CH3_CDR_SRC : String := "REFCLK_EXT";
+-- CH3_CDR_SRC : String := "REFCLK_CORE";
-- PLL_SRC : String := "REFCLK_CORE"
);
port (
GENERIC (USER_CONFIG_FILE : String := "serdes_sync_3.txt");
port (
------------------
- refclkp, refclkn : in std_logic;
-- CH0 --
-- CH1 --
-- CH2 --
rx_half_clk_ch3 : out std_logic;
tx_full_clk_ch3 : out std_logic;
tx_half_clk_ch3 : out std_logic;
+ fpga_rxrefclk_ch3 : in std_logic;
txdata_ch3 : in std_logic_vector (7 downto 0);
tx_k_ch3 : in std_logic;
tx_force_disp_ch3 : in std_logic;
attribute PLL_SRC: string;
attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
attribute CH3_CDR_SRC: string;
- attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_EXT";
+ attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "200";
attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
--synopsys translate_off
generic map (CONFIG_FILE => USER_CONFIG_FILE,
QUAD_MODE => "SINGLE",
- CH3_CDR_SRC => "REFCLK_EXT",
+ CH3_CDR_SRC => "REFCLK_CORE",
PLL_SRC => "REFCLK_CORE"
)
--synopsys translate_on
port map (
- REFCLKP => refclkp,
- REFCLKN => refclkn,
+ REFCLKP => fpsc_vlo,
+ REFCLKN => fpsc_vlo,
----- CH0 -----
HDOUTP0 => open,
FF_RX_H_CLK_3 => rx_half_clk_ch3,
FF_TX_F_CLK_3 => tx_full_clk_ch3_sig,
FF_TX_H_CLK_3 => tx_half_clk_ch3,
- FFC_CK_CORE_RX_3 => fpsc_vlo,
+ FFC_CK_CORE_RX_3 => fpga_rxrefclk_ch3,
FF_TX_D_3_0 => txdata_ch3(0),
FF_TX_D_3_1 => txdata_ch3(1),
FF_TX_D_3_2 => txdata_ch3(2),
-------------------------------------------------
-- Serdes
-------------------------------------------------
-THE_SERDES : entity work.serdes_sync_0
- port map(
- hdinp_ch0 => SD_RXD_P_IN,
- hdinn_ch0 => SD_RXD_N_IN,
- hdoutp_ch0 => SD_TXD_P_OUT,
- hdoutn_ch0 => SD_TXD_N_OUT,
- rxiclk_ch0 => clk_200_i,
- txiclk_ch0 => clk_200_i,
- rx_full_clk_ch0 => clk_rx_full,
- rx_half_clk_ch0 => clk_rx_half,
- tx_full_clk_ch0 => clk_tx_full,
- tx_half_clk_ch0 => clk_tx_half,
- fpga_rxrefclk_ch0 => clk_200_internal,
- txdata_ch0 => tx_data,
- tx_k_ch0 => tx_k,
- tx_force_disp_ch0 => '0',
- tx_disp_sel_ch0 => '0',
- rxdata_ch0 => rx_data,
- rx_k_ch0 => rx_k,
- rx_disp_err_ch0 => open,
- rx_cv_err_ch0 => rx_error,
- rx_serdes_rst_ch0_c => rx_serdes_rst,
- sb_felb_ch0_c => '0',
- sb_felb_rst_ch0_c => '0',
- tx_pcs_rst_ch0_c => tx_pcs_rst,
- tx_pwrup_ch0_c => '1',
- rx_pcs_rst_ch0_c => rx_pcs_rst,
- rx_pwrup_ch0_c => '1',
- rx_los_low_ch0_s => rx_los_low,
- lsm_status_ch0_s => lsm_status,
- rx_cdr_lol_ch0_s => rx_cdr_lol,
- tx_div2_mode_ch0_c => '0',
- rx_div2_mode_ch0_c => '0',
-
- SCI_WRDATA => sci_data_in_i,
- SCI_RDDATA => sci_data_out_i,
- SCI_ADDR => sci_addr_i(5 downto 0),
- SCI_SEL_QUAD => sci_qd_i,
- SCI_SEL_CH0 => sci_ch_i(0),
- SCI_RD => sci_read_i,
- SCI_WRN => sci_write_i,
-
- fpga_txrefclk => clk_200_i,
- tx_serdes_rst_c => tx_serdes_rst,
- tx_pll_lol_qd_s => tx_pll_lol,
- rst_qd_c => rst_qd,
- serdes_rst_qd_c => serdes_rst_qd
+gen_pcs0 : if SERDES_NUM = 0 generate
+ THE_SERDES : entity work.serdes_sync_0
+ port map(
+ hdinp_ch0 => SD_RXD_P_IN,
+ hdinn_ch0 => SD_RXD_N_IN,
+ hdoutp_ch0 => SD_TXD_P_OUT,
+ hdoutn_ch0 => SD_TXD_N_OUT,
+ rxiclk_ch0 => clk_200_i,
+ txiclk_ch0 => clk_200_i,
+ rx_full_clk_ch0 => clk_rx_full,
+ rx_half_clk_ch0 => clk_rx_half,
+ tx_full_clk_ch0 => clk_tx_full,
+ tx_half_clk_ch0 => clk_tx_half,
+ fpga_rxrefclk_ch0 => clk_200_internal,
+ txdata_ch0 => tx_data,
+ tx_k_ch0 => tx_k,
+ tx_force_disp_ch0 => '0',
+ tx_disp_sel_ch0 => '0',
+ rxdata_ch0 => rx_data,
+ rx_k_ch0 => rx_k,
+ rx_disp_err_ch0 => open,
+ rx_cv_err_ch0 => rx_error,
+ rx_serdes_rst_ch0_c => rx_serdes_rst,
+ sb_felb_ch0_c => '0',
+ sb_felb_rst_ch0_c => '0',
+ tx_pcs_rst_ch0_c => tx_pcs_rst,
+ tx_pwrup_ch0_c => '1',
+ rx_pcs_rst_ch0_c => rx_pcs_rst,
+ rx_pwrup_ch0_c => '1',
+ rx_los_low_ch0_s => rx_los_low,
+ lsm_status_ch0_s => lsm_status,
+ rx_cdr_lol_ch0_s => rx_cdr_lol,
+ tx_div2_mode_ch0_c => '0',
+ rx_div2_mode_ch0_c => '0',
+
+ SCI_WRDATA => sci_data_in_i,
+ SCI_RDDATA => sci_data_out_i,
+ SCI_ADDR => sci_addr_i(5 downto 0),
+ SCI_SEL_QUAD => sci_qd_i,
+ SCI_SEL_CH0 => sci_ch_i(0),
+ SCI_RD => sci_read_i,
+ SCI_WRN => sci_write_i,
+
+ fpga_txrefclk => clk_200_i,
+ tx_serdes_rst_c => tx_serdes_rst,
+ tx_pll_lol_qd_s => tx_pll_lol,
+ rst_qd_c => rst_qd,
+ serdes_rst_qd_c => serdes_rst_qd
+
+ );
+end generate;
+gen_pcs3 : if SERDES_NUM = 3 generate
+ THE_SERDES : entity work.serdes_sync_3
+ port map(
+ hdinp_ch3 => SD_RXD_P_IN,
+ hdinn_ch3 => SD_RXD_N_IN,
+ hdoutp_ch3 => SD_TXD_P_OUT,
+ hdoutn_ch3 => SD_TXD_N_OUT,
+ rxiclk_ch3 => clk_200_i,
+ txiclk_ch3 => clk_200_i,
+ rx_full_clk_ch3 => clk_rx_full,
+ rx_half_clk_ch3 => clk_rx_half,
+ tx_full_clk_ch3 => clk_tx_full,
+ tx_half_clk_ch3 => clk_tx_half,
+ fpga_rxrefclk_ch3 => clk_200_internal,
+ txdata_ch3 => tx_data,
+ tx_k_ch3 => tx_k,
+ tx_force_disp_ch3 => '0',
+ tx_disp_sel_ch3 => '0',
+ rxdata_ch3 => rx_data,
+ rx_k_ch3 => rx_k,
+ rx_disp_err_ch3 => open,
+ rx_cv_err_ch3 => rx_error,
+ rx_serdes_rst_ch3_c => rx_serdes_rst,
+ sb_felb_ch3_c => '0',
+ sb_felb_rst_ch3_c => '0',
+ tx_pcs_rst_ch3_c => tx_pcs_rst,
+ tx_pwrup_ch3_c => '1',
+ rx_pcs_rst_ch3_c => rx_pcs_rst,
+ rx_pwrup_ch3_c => '1',
+ rx_los_low_ch3_s => rx_los_low,
+ lsm_status_ch3_s => lsm_status,
+ rx_cdr_lol_ch3_s => rx_cdr_lol,
+ tx_div2_mode_ch3_c => '0',
+ rx_div2_mode_ch3_c => '0',
+
+ SCI_WRDATA => sci_data_in_i,
+ SCI_RDDATA => sci_data_out_i,
+ SCI_ADDR => sci_addr_i(5 downto 0),
+ SCI_SEL_QUAD => sci_qd_i,
+ SCI_SEL_CH3 => sci_ch_i(0),
+ SCI_RD => sci_read_i,
+ SCI_WRN => sci_write_i,
+
+ fpga_txrefclk => clk_200_i,
+ tx_serdes_rst_c => tx_serdes_rst,
+ tx_pll_lol_qd_s => tx_pll_lol,
+ rst_qd_c => rst_qd,
+ serdes_rst_qd_c => serdes_rst_qd
+
+ );
+end generate;
- );
tx_serdes_rst <= '0'; --no function
serdes_rst_qd <= '0'; --included in rst_qd
----------------------------------------------------------------------
-- Data to Endpoint
----------------------------------------------------------------------
---note: no handshaking, read signal can be ignored!
-ct_fifo_read <= not ct_fifo_reset when rising_edge(CLK_100);
+
+ct_fifo_read <= not ct_fifo_reset and not ct_fifo_empty; -- when rising_edge(CLK_100);
buf_rx_write_out <= last_ct_fifo_read and not last_ct_fifo_empty when rising_edge(CLK_100);
RX_DATA_OUT <= ct_fifo_data_out(15 downto 0) ;
----------------------------------------------------------------------
-- Clock Domain Transfer
----------------------------------------------------------------------
-THE_CT_FIFO : lattice_ecp3_fifo_18x16_dualport_oreg
+THE_CT_FIFO : entity work.lattice_ecp3_fifo_18x16_dualport_oreg
port map(
Data => rx_data,
WrClock => CLK_200,
AlmostFull => ct_fifo_afull
);
-ct_fifo_reset <= not RX_ALLOW_IN;
-
+ct_fifo_reset <= not RX_ALLOW_IN when rising_edge(CLK_200);
----------------------------------------------------------------------
DEBUG_OUT(6) <= ct_fifo_empty;
DEBUG_OUT(7) <= ct_fifo_write;
DEBUG_OUT(15 downto 8) <= reg_rx_data_in(7 downto 0);
-DEBUG_OUT(16) <= rx_data(16);
-DEBUG_OUT(31 downto 18) <= (others => '0');
-
+--DEBUG_OUT(16) <= rx_data(16);
+-- DEBUG_OUT(31 downto 18) <= (others => '0');
+DEBUG_OUT(23 downto 16) <= rx_data(7 downto 0);
+DEBUG_OUT(31 downto 24) <= ct_fifo_data_out(7 downto 0);
--- /dev/null
+
+LIBRARY ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+
+
+entity spi_flash_and_fpga_reload_record is
+ port(
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+
+ BUS_TX : out CTRLBUS_TX;
+ BUS_RX : in CTRLBUS_RX;
+
+ DO_REBOOT_IN : in std_logic;
+ PROGRAMN : out std_logic;
+
+ SPI_CS_OUT : out std_logic;
+ SPI_SCK_OUT : out std_logic;
+ SPI_SDO_OUT : out std_logic;
+ SPI_SDI_IN : in std_logic
+ );
+end entity;
+
+
+architecture flash_reboot_arch of spi_flash_and_fpga_reload_record is
+
+ signal spictrl_read_en : std_logic;
+ signal spictrl_write_en : std_logic;
+ signal spictrl_data_in : std_logic_vector(31 downto 0);
+ signal spictrl_addr : std_logic;
+ signal spictrl_data_out : std_logic_vector(31 downto 0);
+ signal spictrl_ack : std_logic;
+ signal spictrl_busy : std_logic;
+ signal spimem_read_en : std_logic;
+ signal spimem_write_en : std_logic;
+ signal spimem_data_in : std_logic_vector(31 downto 0);
+ signal spimem_addr : std_logic_vector(5 downto 0);
+ signal spimem_data_out : std_logic_vector(31 downto 0);
+ signal spimem_ack : std_logic;
+
+ signal spi_bram_addr : std_logic_vector(7 downto 0);
+ signal spi_bram_wr_d : std_logic_vector(7 downto 0);
+ signal spi_bram_rd_d : std_logic_vector(7 downto 0);
+ signal spi_bram_we : std_logic;
+
+ signal dat_write_ack, dat_dataready : std_logic;
+
+begin
+
+BUS_TX.ack <= dat_dataready or dat_write_ack;
+
+THE_BUS_HANDLER : trb_net16_regio_bus_handler
+ generic map(
+ PORT_NUMBER => 2,
+ PORT_ADDRESSES => (0 => x"0000", 1 => x"0100", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 1, 1 => 6, others => 0)
+ )
+ port map(
+ CLK => CLK_IN,
+ RESET => RESET_IN,
+
+ DAT_ADDR_IN(8 downto 0) => BUS_RX.addr(8 downto 0),
+ DAT_ADDR_IN(15 downto 9)=>(others => '0'),
+ DAT_DATA_IN => BUS_RX.data,
+ DAT_DATA_OUT => BUS_TX.data,
+ DAT_READ_ENABLE_IN => BUS_RX.read,
+ DAT_WRITE_ENABLE_IN => BUS_RX.write,
+ DAT_TIMEOUT_IN => '0',
+ DAT_DATAREADY_OUT => dat_dataready,
+ DAT_WRITE_ACK_OUT => dat_write_ack,
+ DAT_NO_MORE_DATA_OUT => BUS_TX.nack,
+ DAT_UNKNOWN_ADDR_OUT => BUS_TX.unknown,
+
+ --Bus Handler (SPI CTRL)
+ BUS_READ_ENABLE_OUT(0) => spictrl_read_en,
+ BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en,
+ BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in,
+ BUS_ADDR_OUT(0*16) => spictrl_addr,
+ BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open,
+ BUS_TIMEOUT_OUT(0) => open,
+ BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out,
+ BUS_DATAREADY_IN(0) => spictrl_ack,
+ BUS_WRITE_ACK_IN(0) => spictrl_ack,
+ BUS_NO_MORE_DATA_IN(0) => spictrl_busy,
+ BUS_UNKNOWN_ADDR_IN(0) => '0',
+
+ --Bus Handler (SPI Memory)
+ BUS_READ_ENABLE_OUT(1) => spimem_read_en,
+ BUS_WRITE_ENABLE_OUT(1) => spimem_write_en,
+ BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in,
+ BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr,
+ BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open,
+ BUS_TIMEOUT_OUT(1) => open,
+ BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out,
+ BUS_DATAREADY_IN(1) => spimem_ack,
+ BUS_WRITE_ACK_IN(1) => spimem_ack,
+ BUS_NO_MORE_DATA_IN(1) => '0',
+ BUS_UNKNOWN_ADDR_IN(1) => '0',
+ STAT_DEBUG => open
+ );
+
+
+THE_SPI_MASTER: spi_master
+ port map(
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ -- Slave bus
+ BUS_READ_IN => spictrl_read_en,
+ BUS_WRITE_IN => spictrl_write_en,
+ BUS_BUSY_OUT => spictrl_busy,
+ BUS_ACK_OUT => spictrl_ack,
+ BUS_ADDR_IN(0) => spictrl_addr,
+ BUS_DATA_IN => spictrl_data_in,
+ BUS_DATA_OUT => spictrl_data_out,
+ -- SPI connections
+ SPI_CS_OUT => SPI_CS_OUT,
+ SPI_SDI_IN => SPI_SDI_IN,
+ SPI_SDO_OUT => SPI_SDO_OUT,
+ SPI_SCK_OUT => SPI_SCK_OUT,
+ -- BRAM for read/write data
+ BRAM_A_OUT => spi_bram_addr,
+ BRAM_WR_D_IN => spi_bram_wr_d,
+ BRAM_RD_D_OUT => spi_bram_rd_d,
+ BRAM_WE_OUT => spi_bram_we,
+ -- Status lines
+ STAT => open
+ );
+
+-- data memory for SPI accesses
+THE_SPI_MEMORY: spi_databus_memory
+ port map(
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ -- Slave bus
+ BUS_ADDR_IN => spimem_addr,
+ BUS_READ_IN => spimem_read_en,
+ BUS_WRITE_IN => spimem_write_en,
+ BUS_ACK_OUT => spimem_ack,
+ BUS_DATA_IN => spimem_data_in,
+ BUS_DATA_OUT => spimem_data_out,
+ -- state machine connections
+ BRAM_ADDR_IN => spi_bram_addr,
+ BRAM_WR_D_OUT => spi_bram_wr_d,
+ BRAM_RD_D_IN => spi_bram_rd_d,
+ BRAM_WE_IN => spi_bram_we,
+ -- Status lines
+ STAT => open
+ );
+
+---------------------------------------------------------------------------
+-- Reboot FPGA
+---------------------------------------------------------------------------
+THE_FPGA_REBOOT : fpga_reboot
+ port map(
+ CLK => CLK_IN,
+ RESET => RESET_IN,
+ DO_REBOOT => DO_REBOOT_IN,
+ PROGRAMN => PROGRAMN
+ );
+
+
+end architecture;
\ No newline at end of file
--- the full endpoint for HADES: trg, data, unused, regio including data buffer & handling
+-- the full endpoint for TRB3++: trg, data, unused, regio including data buffer & handling
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.trb_net_std.all;
use work.trb_net_components.all;
+use work.config.all;
entity trb_net16_endpoint_hades_full_handler_record is
APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO);
ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF";
BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF";
- BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF";
- REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers
- REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers
- REGIO_INIT_CTRL_REGS : std_logic_vector(16*32-1 downto 0) := (others => '0');
- REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";
- REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222";
REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";
- REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
- REGIO_INCLUDED_FEATURES : std_logic_vector(63 downto 0) := (others => '0');
REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";
- REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR
REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO;
- CLOCK_FREQUENCY : integer range 1 to 200 := 100;
TIMING_TRIGGER_RAW : integer range 0 to 1 := c_YES;
--Configure data handler
DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1;
--Timing trigger in
TRG_TIMING_TRG_RECEIVED_IN : in std_logic;
- --LVL1 trigger to FEE
- LVL1_TRG_DATA_VALID_OUT : out std_logic; --trigger type, number, code, information are valid
- LVL1_VALID_TIMING_TRG_OUT : out std_logic; --valid timing trigger has been received
- LVL1_VALID_NOTIMING_TRG_OUT : out std_logic; --valid trigger without timing trigger has been received
- LVL1_INVALID_TRG_OUT : out std_logic; --the current trigger is invalid (e.g. no timing trigger, no LVL1...)
-
- LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0);
- LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);
- LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0);
- LVL1_TRG_INFORMATION_OUT : out std_logic_vector(23 downto 0);
- LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); --internally generated trigger number, for informational uses only
-
- --Information about trigger handler errors
- TRG_MULTIPLE_TRG_OUT : out std_logic;
- TRG_TIMEOUT_DETECTED_OUT : out std_logic;
- TRG_SPURIOUS_TRG_OUT : out std_logic;
- TRG_MISSING_TMG_TRG_OUT : out std_logic;
- TRG_SPIKE_DETECTED_OUT : out std_logic;
-
- --Response from FEE
- FEE_TRG_RELEASE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
- FEE_TRG_STATUSBITS_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
- FEE_DATA_IN : in std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
- FEE_DATA_WRITE_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
- FEE_DATA_FINISHED_IN : in std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
- FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
+
+ READOUT_RX : out READOUT_RX;
+ READOUT_TX : in readout_tx_array_t(0 to DATA_INTERFACE_NUMBER-1);
--Slow Control Port
--common registers
REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
REGIO_COMMON_STAT_STROBE_OUT : out std_logic_vector(std_COMSTATREG-1 downto 0);
REGIO_COMMON_CTRL_STROBE_OUT : out std_logic_vector(std_COMCTRLREG-1 downto 0);
- --user defined registers
- REGIO_STAT_REG_IN : in std_logic_vector(2**(REGIO_NUM_STAT_REGS)*32-1 downto 0) := (others => '0');
- REGIO_CTRL_REG_OUT : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)*32-1 downto 0);
- REGIO_STAT_STROBE_OUT : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);
- REGIO_CTRL_STROBE_OUT : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
+
--internal data port
BUS_RX : out CTRLBUS_RX;
BUS_TX : in CTRLBUS_TX;
--Onewire
ONEWIRE_INOUT : inout std_logic; --temperature sensor
- ONEWIRE_MONITOR_IN : in std_logic := '0';
- ONEWIRE_MONITOR_OUT : out std_logic;
--Config endpoint id, if not statically assigned
REGIO_VAR_ENDPOINT_ID : in std_logic_vector (15 downto 0) := (others => '0');
signal common_ctrl_reg_i : std_logic_vector (std_COMCTRLREG*32-1 downto 0);
signal common_stat_strobe_i : std_logic_vector (std_COMSTATREG-1 downto 0);
signal common_ctrl_strobe_i : std_logic_vector (std_COMCTRLREG-1 downto 0);
- signal stat_reg_i : std_logic_vector (2**(REGIO_NUM_STAT_REGS)*32-1 downto 0);
- signal ctrl_reg_i : std_logic_vector (2**(REGIO_NUM_CTRL_REGS)*32-1 downto 0);
- signal stat_strobe_i : std_logic_vector (2**(REGIO_NUM_STAT_REGS)-1 downto 0);
- signal ctrl_strobe_i : std_logic_vector (2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
+-- signal stat_reg_i : std_logic_vector (2**(REGIO_NUM_STAT_REGS)*32-1 downto 0);
+-- signal ctrl_reg_i : std_logic_vector (2**(REGIO_NUM_CTRL_REGS)*32-1 downto 0);
+-- signal stat_strobe_i : std_logic_vector (2**(REGIO_NUM_STAT_REGS)-1 downto 0);
+-- signal ctrl_strobe_i : std_logic_vector (2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
signal regio_rx, dbuf_rx, info_rx, stat_handler_rx, stat_buffer_rx : CTRLBUS_RX;
signal regio_tx, dbuf_tx, info_tx, stat_handler_tx, stat_buffer_tx : CTRLBUS_TX;
signal int_lvl1_long_trg : std_logic;
signal tmg_trg_error_i : std_logic;
+ signal fee_data_finished_in : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
+ signal fee_data_write_in : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
+ signal fee_trg_release_in : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
+ signal fee_data_in : std_logic_vector(32*DATA_INTERFACE_NUMBER-1 downto 0);
+ signal fee_trg_statusbits_in : std_logic_vector(32*DATA_INTERFACE_NUMBER-1 downto 0);
+
signal max_event_size : std_logic_vector(15 downto 0);
signal new_max_size : std_logic_vector(15 downto 0);
ADDRESS_MASK => ADDRESS_MASK,
BROADCAST_BITMASK => BROADCAST_BITMASK,
BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR,
- REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS,
- REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS,
- REGIO_INIT_CTRL_REGS => REGIO_INIT_CTRL_REGS,
- REGIO_INIT_ADDRESS => REGIO_INIT_ADDRESS,
- REGIO_INIT_BOARD_INFO => REGIO_INIT_BOARD_INFO,
+ REGIO_NUM_STAT_REGS => 0,
+ REGIO_NUM_CTRL_REGS => 0,
+ REGIO_INIT_CTRL_REGS => (others => '0'),
+ REGIO_INIT_ADDRESS => INIT_ADDRESS,
+ REGIO_INIT_BOARD_INFO => HARDWARE_INFO,
REGIO_INIT_ENDPOINT_ID => REGIO_INIT_ENDPOINT_ID,
- REGIO_COMPILE_TIME => REGIO_COMPILE_TIME,
- REGIO_INCLUDED_FEATURES => REGIO_INCLUDED_FEATURES,
- REGIO_HARDWARE_VERSION => REGIO_HARDWARE_VERSION,
- REGIO_USE_1WIRE_INTERFACE => REGIO_USE_1WIRE_INTERFACE,
+ REGIO_COMPILE_TIME => (others => '0'),
+ REGIO_INCLUDED_FEATURES => INCLUDED_FEATURES,
+ REGIO_HARDWARE_VERSION => HARDWARE_INFO,
+ REGIO_USE_1WIRE_INTERFACE => c_YES,
REGIO_USE_VAR_ENDPOINT_ID => REGIO_USE_VAR_ENDPOINT_ID,
TIMING_TRIGGER_RAW => TIMING_TRIGGER_RAW,
CLOCK_FREQUENCY => CLOCK_FREQUENCY
IPU_ERROR_PATTERN_IN => ipu_error_pattern_i,
-- Slow Control Data Port
- REGIO_COMMON_STAT_REG_IN => common_stat_reg_i,
- REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg_i,
- REGIO_REGISTERS_IN => stat_reg_i,
- REGIO_REGISTERS_OUT => ctrl_reg_i,
+ REGIO_COMMON_STAT_REG_IN => REGIO_COMMON_STAT_REG_IN,
+ REGIO_COMMON_CTRL_REG_OUT => REGIO_COMMON_CTRL_REG_OUT,
+ REGIO_REGISTERS_IN => (others => '0'),
+ REGIO_REGISTERS_OUT => open,
COMMON_STAT_REG_STROBE => common_stat_strobe_i,
COMMON_CTRL_REG_STROBE => common_ctrl_strobe_i,
- STAT_REG_STROBE => stat_strobe_i,
- CTRL_REG_STROBE => ctrl_strobe_i,
+ STAT_REG_STROBE => open,
+ CTRL_REG_STROBE => open,
REGIO_ADDR_OUT => regio_rx.addr, --regio_addr_out,
REGIO_READ_ENABLE_OUT => regio_rx.read, --regio_read_enable_out,
REGIO_TIMEOUT_OUT => regio_rx.timeout, --regio_timeout_out,
REGIO_ONEWIRE_INOUT => ONEWIRE_INOUT,
- REGIO_ONEWIRE_MONITOR_IN => ONEWIRE_MONITOR_IN,
- REGIO_ONEWIRE_MONITOR_OUT => ONEWIRE_MONITOR_OUT,
+ REGIO_ONEWIRE_MONITOR_IN => '0',
+ REGIO_ONEWIRE_MONITOR_OUT => open,
REGIO_VAR_ENDPOINT_ID => REGIO_VAR_ENDPOINT_ID,
GLOBAL_TIME_OUT => time_global_i,
IPU_ERROR_PATTERN_OUT => ipu_error_pattern_i,
--FEE Input
- FEE_TRG_RELEASE_IN => FEE_TRG_RELEASE_IN,
- FEE_TRG_STATUSBITS_IN => FEE_TRG_STATUSBITS_IN,
- FEE_DATA_IN => FEE_DATA_IN,
- FEE_DATA_WRITE_IN => FEE_DATA_WRITE_IN,
- FEE_DATA_FINISHED_IN => FEE_DATA_FINISHED_IN,
+ FEE_TRG_RELEASE_IN => fee_trg_release_in,
+ FEE_TRG_STATUSBITS_IN => fee_trg_statusbits_in,
+ FEE_DATA_IN => fee_data_in,
+ FEE_DATA_WRITE_IN => fee_data_write_in,
+ FEE_DATA_FINISHED_IN => fee_data_finished_in,
FEE_DATA_ALMOST_FULL_OUT => buf_fee_data_almost_full_out,
TMG_TRG_ERROR_IN => tmg_trg_error_i,
STAT_DEBUG_DATA_HANDLER_OUT <= debug_data_handler_i;
tmg_trg_error_i <= int_lvl1_missing_tmg_trg or int_lvl1_spurious_trg or int_lvl1_timeout_detected or int_multiple_trg
or int_spike_detected or int_lvl1_long_trg;
- FEE_DATA_ALMOST_FULL_OUT <= (others => or_all(buf_fee_data_almost_full_out));
-
+
+
+gen_rdo_tx : for i in 0 to DATA_INTERFACE_NUMBER-1 generate
+ fee_trg_release_in(i) <= READOUT_TX(i).busy_release;
+ fee_trg_statusbits_in(i*32+31 downto i*32) <= READOUT_TX(i).statusbits;
+ fee_data_in(i*32+31 downto i*32) <= READOUT_TX(i).data;
+ fee_data_write_in(i) <= READOUT_TX(i).data_write;
+ fee_data_finished_in(i) <= READOUT_TX(i).data_finished;
+end generate;
+
+
---------------------------------------------------------------------------
-- Connect Status Registers
---------------------------------------------------------------------------
-- Connect I/O Ports
---------------------------------------------------------------------------
- TRG_SPIKE_DETECTED_OUT <= int_spike_detected;
- TRG_SPURIOUS_TRG_OUT <= int_lvl1_spurious_trg;
- TRG_TIMEOUT_DETECTED_OUT <= int_lvl1_timeout_detected;
- TRG_MULTIPLE_TRG_OUT <= int_multiple_trg;
- TRG_MISSING_TMG_TRG_OUT <= int_lvl1_missing_tmg_trg;
-
- LVL1_TRG_DATA_VALID_OUT <= lvl1_data_valid_i;
- LVL1_VALID_TIMING_TRG_OUT <= lvl1_valid_timing_i;
- LVL1_VALID_NOTIMING_TRG_OUT <= lvl1_valid_notiming_i;
- LVL1_INVALID_TRG_OUT <= lvl1_invalid_i;
- LVL1_TRG_TYPE_OUT <= lvl1_type_i;
- LVL1_TRG_NUMBER_OUT <= lvl1_number_i;
- LVL1_TRG_CODE_OUT <= lvl1_code_i;
- LVL1_TRG_INFORMATION_OUT <= lvl1_information_i;
- LVL1_INT_TRG_NUMBER_OUT <= lvl1_int_trg_number_i;
+ READOUT_RX.trg_spike <= int_spike_detected;
+ READOUT_RX.trg_spurious <= int_lvl1_spurious_trg;
+ READOUT_RX.trg_timeout <= int_lvl1_timeout_detected;
+ READOUT_RX.trg_multiple <= int_multiple_trg;
+ READOUT_RX.trg_missing <= int_lvl1_missing_tmg_trg;
+ READOUT_RX.buffer_almost_full <= or_all(buf_fee_data_almost_full_out);
+
+ READOUT_RX.data_valid <= lvl1_data_valid_i;
+ READOUT_RX.valid_timing_trg <= lvl1_valid_timing_i;
+ READOUT_RX.valid_notiming_trg <= lvl1_valid_notiming_i;
+ READOUT_RX.invalid_trg <= lvl1_invalid_i;
+ READOUT_RX.trg_type <= lvl1_type_i;
+ READOUT_RX.trg_number <= lvl1_number_i;
+ READOUT_RX.trg_code <= lvl1_code_i;
+ READOUT_RX.trg_information <= lvl1_information_i;
+ READOUT_RX.trg_int_number <= lvl1_int_trg_number_i;
REGIO_COMMON_CTRL_REG_OUT <= common_ctrl_reg_i;
REGIO_COMMON_STAT_STROBE_OUT <= common_stat_strobe_i;
REGIO_COMMON_CTRL_STROBE_OUT <= common_ctrl_strobe_i;
- REGIO_CTRL_REG_OUT <= ctrl_reg_i;
- REGIO_STAT_STROBE_OUT <= stat_strobe_i;
- REGIO_CTRL_STROBE_OUT <= ctrl_strobe_i;
+-- REGIO_CTRL_REG_OUT <= ctrl_reg_i;
+-- REGIO_STAT_STROBE_OUT <= stat_strobe_i;
+-- REGIO_CTRL_STROBE_OUT <= ctrl_strobe_i;
- stat_reg_i <= REGIO_STAT_REG_IN;
+-- stat_reg_i <= REGIO_STAT_REG_IN;
TIME_GLOBAL_OUT <= time_global_i;
TIME_LOCAL_OUT <= time_local_i;
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