pulse_a_in(DEPTH*i) <= PULSE_IN(i-1);
pulse_a_in(DEPTH*i-1 downto DEPTH*(i-1)+1) <= pulse_b_out(DEPTH*i-1 downto DEPTH*(i-1)+1);
pulse_b_in(DEPTH*i-1 downto DEPTH*(i-1)+1) <= pulse_a_out(DEPTH*i-1 downto DEPTH*(i-1)+1);
- PULSE_OUT(i-1) <= transport not pulse_a_out(DEPTH*(i-1)) after 42.186 ns;
+ PULSE_OUT(i-1) <= transport pulse_b_out(DEPTH*(i-1)+1) after 42.186 ns;
end generate GEN;
Stretcher_A_1 : entity work.Stretcher_A
The_Stretcher : entity work.Stretcher
generic map (
CHANNEL => CHANNEL_NUMBER-1,
- DEPTH => 4)
+ DEPTH => 4+(FPGA_TYPE/4)) --4 for ECP3, 5 for ECP5
port map (
PULSE_IN => edge_falling(CHANNEL_NUMBER-1 downto 1),
PULSE_OUT => edge_falling_d(CHANNEL_NUMBER-1 downto 1));
elsif valid_notiming_200 = '1' then
if TRG_TYPE_IN = x"D" then
STATE_TW_NEXT <= COUNT_CALIBRATION;
+ trg_win_cnt_f <= x"005";
else
STATE_TW_NEXT <= WAIT_NEXT_TRIGGER;
end if;