------------------------------------------------------------------------------
--design options: backplane or front SFP, with or without GBE
- constant USE_BACKPLANE : integer := c_YES;
+ constant USE_BACKPLANE : integer := c_NO;
constant INCLUDE_GBE : integer := c_NO;
--Runs with 120 MHz instead of 100 MHz
t(63 downto 56) := std_logic_vector(to_unsigned(1,8)); --table version 1
t(17 downto 17) := std_logic_vector(to_unsigned(INCLUDE_GBE,1)); --sctrl via GbE
t(23 downto 23) := std_logic_vector(to_unsigned(INCLUDE_GBE,1));
--- t(26 downto 24) := std_logic_vector(to_unsigned(1,3)); --num SFPs with TrbNet
+ t(27 downto 24) := std_logic_vector(to_unsigned(INTERFACE_NUM-USE_BACKPLANE,4)); --num SFPs with TrbNet
t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1));
t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
lm_license_file_for_par => "1702\@hadeb05.gsi.de",
lattice_path => '/d/jspc29/lattice/diamond/3.9_x64',
-synplify_path => '/d/jspc29/lattice/synplify/K-2015.09/',
+# synplify_path => '/d/jspc29/lattice/synplify/K-2015.09/',
+synplify_path => '/d/jspc29/lattice/synplify/L-2016.09-1/',
#synplify_command => "/d/jspc29/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options",
#synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
-REGION "MEDIA_DOWN1" "R102C40D" 13 100;
+REGION "MEDIA_DOWN1" "R102C20D" 13 120;
LOCATE UGROUP "gen_PCSA.THE_MEDIA_PCSA/media_interface_group" REGION "MEDIA_DOWN1" ;
LOCATE UGROUP "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/media_interface_group" REGION "MEDIA_DOWN1" ;
LOCATE UGROUP "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/media_interface_group" REGION "MEDIA_DOWN1" ;
RESET => reset_i,
CLEAR => clear_i,
--Internal Connection
- MEDIA_MED2INT => med2int(10-2*INCLUDE_GBE), --10 or 8
- MEDIA_INT2MED => int2med(10-2*INCLUDE_GBE),
+ MEDIA_MED2INT => med2int(INTERFACE_NUM-1), --10 or 8
+ MEDIA_INT2MED => int2med(INTERFACE_NUM-1),
--Sync operation
RX_DLM => open,
MEDIA_MED2INT(0) => med2int(4),
MEDIA_MED2INT(1) => med2int(5),
MEDIA_MED2INT(2) => med2int(6),
- MEDIA_MED2INT(3) => med2int(9-2*INCLUDE_GBE),
+ MEDIA_MED2INT(3) => med2int(INTERFACE_NUM-1),
MEDIA_INT2MED(0) => int2med(4),
MEDIA_INT2MED(1) => int2med(5),
MEDIA_INT2MED(2) => int2med(6),
- MEDIA_INT2MED(3) => int2med(9-2*INCLUDE_GBE),
+ MEDIA_INT2MED(3) => int2med(INTERFACE_NUM-1),
--Sync operation
RX_DLM => open,
TRIGGER_IN => '0',
SD_PRSNT_N_IN(0) => SFP_MOD0(0),
+ SD_PRSNT_N_IN(3 downto 1)=> "111",
SD_LOS_IN(0) => SFP_LOS(0),
+ SD_LOS_IN(3 downto 1) => "111",
SD_TXDIS_OUT(0) => SFP_TX_DIS(0),
CTS_NUMBER_IN => cts_number,
LED_HUB_TX(8) <= not (med2int(7).stat_op(10) or not med2int(7).stat_op(9)) when INCLUDE_GBE = 0 else
'1';
LED_HUB_RX(8) <= not (med2int(7).stat_op(11)) when INCLUDE_GBE = 0 else
-
+ '1';
LED_SFP_GREEN(0) <= not med2int(8).stat_op(9) when INCLUDE_GBE = 0 else
'1';
LED_SFP_RED(0) <= not (med2int(8).stat_op(10) or med2int(8).stat_op(11) or not med2int(8).stat_op(9)) when INCLUDE_GBE = 0 else
LOCATE COMP "HUB_MOD2_7" SITE "AC33";\r
# LOCATE COMP "HUB_RATESEL_7" SITE "AB30"; #was "DQSLR0_T" 141\r
LOCATE COMP "HUB_TXDIS_7" SITE "AC30";\r
- LOCATE COMP "HUB_LOS_7" SITE "AA31"; #was "DQLR0_3_P" 145\r
+ LOCATE COMP "HUB_LOS_7" SITE "L26"; #was "DQUR0_0_P" 105 #SITE "AA31"; #was "DQLR0_3_P" 145\r
# LOCATE COMP "HUB_TXFAULT_7" SITE "AA30"\r
\r
LOCATE COMP "LED_HUB_LINKOK_8" SITE "T32"; #was "DQUR2_0_P" 130\r
IOBUF PORT "SPARE_IN_0" IO_TYPE=LVDS25 DIFFRESISTOR=100 ;\r
IOBUF PORT "SPARE_IN_1" IO_TYPE=LVDS25 DIFFRESISTOR=100 ;\r
\r
+#################################################################\r
+# Backplane I/O\r
+#################################################################\r
+LOCATE COMP "BACK_GPIO_0" SITE "C26";\r
+LOCATE COMP "BACK_GPIO_1" SITE "D26";\r
+LOCATE COMP "BACK_GPIO_2" SITE "B27";\r
+LOCATE COMP "BACK_GPIO_3" SITE "C27";\r
+LOCATE COMP "BACK_GPIO_4" SITE "D27";\r
+LOCATE COMP "BACK_GPIO_5" SITE "E27";\r
+LOCATE COMP "BACK_GPIO_6" SITE "B28";\r
+LOCATE COMP "BACK_GPIO_7" SITE "A28";\r
+LOCATE COMP "BACK_GPIO_8" SITE "A26";\r
+LOCATE COMP "BACK_GPIO_9" SITE "A27";\r
+LOCATE COMP "BACK_GPIO_10" SITE "A29";\r
+LOCATE COMP "BACK_GPIO_11" SITE "A30";\r
+LOCATE COMP "BACK_GPIO_12" SITE "H26";\r
+LOCATE COMP "BACK_GPIO_13" SITE "H25";\r
+LOCATE COMP "BACK_GPIO_14" SITE "A31";\r
+LOCATE COMP "BACK_GPIO_15" SITE "B31";\r
+DEFINE PORT GROUP "BACK_GPIO_group" "BACK_GPIO*" ;\r
+IOBUF GROUP "BACK_GPIO_group" IO_TYPE=LVCMOS25 PULLMODE=UP;\r
+\r
+LOCATE COMP "BACK_LVDS_0" SITE "V2";\r
+LOCATE COMP "BACK_LVDS_1" SITE "T4";\r
+# LOCATE COMP "BACK_LVDS_0_N" SITE "V1";\r
+# LOCATE COMP "BACK_LVDS_1_N" SITE "T3";\r
+DEFINE PORT GROUP "BACK_LVDS_group" "BACK_LVDS*" ;\r
+IOBUF GROUP "BACK_LVDS_group" IO_TYPE=LVDS25;\r
\r
\r
#################################################################\r
\r
\r
#################################################################\r
-# Trigger I/O\r
+# Test I/O\r
#################################################################\r
LOCATE COMP "TEST_LINE_0" SITE "A19";\r
LOCATE COMP "TEST_LINE_1" SITE "B19";\r