Clock: in std_logic;
ClockEn: in std_logic; -- dauerhaft auf 1
Reset: in std_logic; -- dauerhaft 0
- Q: out std_logic_vector(0 downto 0));
+ Q: out std_logic_vector(0 downto 0)
+ );
end delay_shift_reg;
architecture Structure of delay_shift_reg is
signal CLK : std_logic := '1';
-
+-- signal RESET : std_logic := '1';
signal inputs : std_logic_vector(31 downto 0);
signal BUS_RX : CTRLBUS_RX;
begin
+-- RESET<= '0' after 500 ns;
CLK <= not CLK after 5 ns;
-
PROC_INIT_REGISTERS : process begin -- Define the Values for the Registers here
BUS_RX.write <= '0';
BUS_RX.read <= '0';
wait for 100 ns;
wait until rising_edge(CLK); wait for 1 ns;
- BUS_RX.write <= '1'; BUS_RX.addr <= x"0000"; BUS_RX.data <= x"0000FFFF"; -- Bsp adress
+ BUS_RX.write <= '1'; BUS_RX.addr <= x"0000"; BUS_RX.data <= x"FFFFFFFF"; -- Adress for Enable rn: all open
+ wait until rising_edge(CLK); wait for 1 ns;
+ BUS_RX.write <= '1'; BUS_RX.addr <= x"0004"; BUS_RX.data <= x"00000000"; -- Adress for Invert rn: none inverted
+ wait until rising_edge(CLK); wait for 1 ns;
+ BUS_RX.write <= '1'; BUS_RX.addr <= x"0008"; BUS_RX.data <= x"FFFFFFFF"; -- Adress for Edgedetect rn: all switched on
+ wait until rising_edge(CLK); wait for 1 ns;
+ BUS_RX.write <= '1'; BUS_RX.addr <= x"000C"; BUS_RX.data <= x"FFFFFFFF"; -- Adress for Delay rn: all switched on
+ wait until rising_edge(CLK); wait for 1 ns;
+ BUS_RX.write <= '1'; BUS_RX.addr <= x"0010"; BUS_RX.data <= x"FFFFFFFF"; -- Adress for Stretch rn: all switched on
+ wait until rising_edge(CLK); wait for 1 ns;
+
+ --------------------------------------------------- Delay Registers--------------------------------------------------
+ BUS_RX.write <= '1'; BUS_RX.addr <= x"0101"; BUS_RX.data <= x"00000000"; --
+ wait until rising_edge(CLK); wait for 1 ns;
+ BUS_RX.write <= '1'; BUS_RX.addr <= x"0102"; BUS_RX.data <= x"00000001"; --
+ wait until rising_edge(CLK); wait for 1 ns;
+ BUS_RX.write <= '1'; BUS_RX.addr <= x"0103"; BUS_RX.data <= x"00000002"; --
+ wait until rising_edge(CLK); wait for 1 ns;
+ BUS_RX.write <= '1'; BUS_RX.addr <= x"0104"; BUS_RX.data <= x"00000003"; --
+ wait until rising_edge(CLK); wait for 1 ns;
+ BUS_RX.write <= '1'; BUS_RX.addr <= x"0105"; BUS_RX.data <= x"00000004"; --
+ wait until rising_edge(CLK); wait for 1 ns;
+ BUS_RX.write <= '1'; BUS_RX.addr <= x"0106"; BUS_RX.data <= x"00000005"; --
+ wait until rising_edge(CLK); wait for 1 ns;
+ BUS_RX.write <= '1'; BUS_RX.addr <= x"0107"; BUS_RX.data <= x"00000005"; --
+ wait until rising_edge(CLK); wait for 1 ns;
+ BUS_RX.write <= '1'; BUS_RX.addr <= x"0108"; BUS_RX.data <= x"00000005"; --
+ wait until rising_edge(CLK); wait for 1 ns;
+ BUS_RX.write <= '1'; BUS_RX.addr <= x"0109"; BUS_RX.data <= x"0000000F"; --
+ wait until rising_edge(CLK); wait for 1 ns;
+ BUS_RX.write <= '1'; BUS_RX.addr <= x"010A"; BUS_RX.data <= x"0000000F"; --
+ wait until rising_edge(CLK); wait for 1 ns;
+ BUS_RX.write <= '1'; BUS_RX.addr <= x"010B"; BUS_RX.data <= x"0000000E"; --
+ wait until rising_edge(CLK); wait for 1 ns;
+ BUS_RX.write <= '1'; BUS_RX.addr <= x"010C"; BUS_RX.data <= x"0000000D"; --
+ wait until rising_edge(CLK); wait for 1 ns;
+ BUS_RX.write <= '1'; BUS_RX.addr <= x"010D"; BUS_RX.data <= x"0000000C"; --
+ wait until rising_edge(CLK); wait for 1 ns;
+ BUS_RX.write <= '1'; BUS_RX.addr <= x"010E"; BUS_RX.data <= x"0000000B"; --
+ wait until rising_edge(CLK); wait for 1 ns;
+ BUS_RX.write <= '1'; BUS_RX.addr <= x"010F"; BUS_RX.data <= x"0000000A"; --
+ wait until rising_edge(CLK); wait for 1 ns;
+ BUS_RX.write <= '1'; BUS_RX.addr <= x"0110"; BUS_RX.data <= x"00000009"; --
+ wait until rising_edge(CLK); wait for 1 ns;
+ BUS_RX.write <= '1'; BUS_RX.addr <= x"0111"; BUS_RX.data <= x"00000008"; --
wait until rising_edge(CLK); wait for 1 ns;
- BUS_RX.write <= '1'; BUS_RX.addr <= x"0001"; BUS_RX.data <= x"FFFFFFFF"; -- Adress for Enable rn: all open
+ BUS_RX.write <= '1'; BUS_RX.addr <= x"0112"; BUS_RX.data <= x"00000007"; --
wait until rising_edge(CLK); wait for 1 ns;
- BUS_RX.write <= '1'; BUS_RX.addr <= x"0002"; BUS_RX.data <= x"00000000"; -- Adress for Invert rn: none inverted
+ BUS_RX.write <= '1'; BUS_RX.addr <= x"0113"; BUS_RX.data <= x"00000006"; --
wait until rising_edge(CLK); wait for 1 ns;
+ BUS_RX.write <= '1'; BUS_RX.addr <= x"0114"; BUS_RX.data <= x"00000005"; --
+ wait until rising_edge(CLK); wait for 1 ns;
+
+
+ --------------------------------------------------- Stretch Registers --------------------------------------------------
+ BUS_RX.write <= '1'; BUS_RX.addr <= x"0201"; BUS_RX.data <= x"00010008"; --
+ wait until rising_edge(CLK); wait for 1 ns;
+ BUS_RX.write <= '1'; BUS_RX.addr <= x"0202"; BUS_RX.data <= x"00010006"; --
+ wait until rising_edge(CLK); wait for 1 ns;
+ BUS_RX.write <= '1'; BUS_RX.addr <= x"0203"; BUS_RX.data <= x"00010006"; --
+ wait until rising_edge(CLK); wait for 1 ns;
+ BUS_RX.write <= '1'; BUS_RX.addr <= x"0204"; BUS_RX.data <= x"00010006"; --
+ wait until rising_edge(CLK); wait for 1 ns;
+ BUS_RX.write <= '1'; BUS_RX.addr <= x"0205"; BUS_RX.data <= x"00010008"; --
+ wait until rising_edge(CLK); wait for 1 ns;
+ BUS_RX.write <= '1'; BUS_RX.addr <= x"0206"; BUS_RX.data <= x"00010000"; --
+ wait until rising_edge(CLK); wait for 1 ns;
+ BUS_RX.write <= '1'; BUS_RX.addr <= x"0207"; BUS_RX.data <= x"00000000"; --
+ wait until rising_edge(CLK); wait for 1 ns;
+ BUS_RX.write <= '1'; BUS_RX.addr <= x"0208"; BUS_RX.data <= x"00020001"; --
+ wait until rising_edge(CLK); wait for 1 ns;
+ BUS_RX.write <= '1'; BUS_RX.addr <= x"0209"; BUS_RX.data <= x"00030001"; --
+ wait until rising_edge(CLK); wait for 1 ns;
+ BUS_RX.write <= '1'; BUS_RX.addr <= x"020A"; BUS_RX.data <= x"00010014"; --
+ wait until rising_edge(CLK); wait for 1 ns;
+-- BUS_RX.write <= '1'; BUS_RX.addr <= x"020B"; BUS_RX.data <= x"0000000E"; --
+-- wait until rising_edge(CLK); wait for 1 ns;
+-- BUS_RX.write <= '1'; BUS_RX.addr <= x"020C"; BUS_RX.data <= x"0000000D"; --
+-- wait until rising_edge(CLK); wait for 1 ns;
+-- BUS_RX.write <= '1'; BUS_RX.addr <= x"020D"; BUS_RX.data <= x"0000000C"; --
+-- wait until rising_edge(CLK); wait for 1 ns;
+-- BUS_RX.write <= '1'; BUS_RX.addr <= x"020E"; BUS_RX.data <= x"0000000B"; --
+-- wait until rising_edge(CLK); wait for 1 ns;
+-- BUS_RX.write <= '1'; BUS_RX.addr <= x"020F"; BUS_RX.data <= x"0000000A"; --
+-- wait until rising_edge(CLK); wait for 1 ns;
+-- BUS_RX.write <= '1'; BUS_RX.addr <= x"0210"; BUS_RX.data <= x"00000009"; --
+-- wait until rising_edge(CLK); wait for 1 ns;
+-- BUS_RX.write <= '1'; BUS_RX.addr <= x"0211"; BUS_RX.data <= x"00000008"; --
+-- wait until rising_edge(CLK); wait for 1 ns;
+-- BUS_RX.write <= '1'; BUS_RX.addr <= x"0212"; BUS_RX.data <= x"00000007"; --
+-- wait until rising_edge(CLK); wait for 1 ns;
+-- BUS_RX.write <= '1'; BUS_RX.addr <= x"0213"; BUS_RX.data <= x"00000006"; --
+-- wait until rising_edge(CLK); wait for 1 ns;
+-- BUS_RX.write <= '1'; BUS_RX.addr <= x"0214"; BUS_RX.data <= x"00000005"; --
+-- wait until rising_edge(CLK); wait for 1 ns;
+
+
+
BUS_RX.write <= '0';
wait;
end process;
inputs <= x"0000F44F";
wait for 14 ns;
inputs <= x"0000C4CF";
- wait for 6 ns;
+ wait for 16 ns; -- too short to detect
+ inputs <= x"FFFFFFFF";
+ wait for 24 ns;
+ inputs <= x"00000001";
+ wait for 27 ns;
+ inputs <= x"008AB400";
+ wait for 33 ns;
+ inputs <= x"0000F44F";
+ wait for 14 ns;
+ inputs <= x"0000C4CF";
+ wait for 26 ns; -- too short to detect
inputs <= x"00000000";
end process;
entity trg_delay is
port(
clk_in : in std_logic;
- signals : in std_logic_vector(31 downto 0);
- reg_inhalt1 : in std_logic_vector(31 downto 0);
- reg_inhalt2 : in std_logic_vector(31 downto 0);
- reg_inhalt3 : in std_logic_vector(31 downto 0);
- processed_signals : out std_logic_vector(31 downto 0)
- )
+ signal_in : in std_logic;
+ delay_time : in std_logic_vector (7 downto 0);
+ reg_onswitch : in std_logic;
+-- reset_i : in std_logic;
+ processed_signal : out std_logic
+ );
end trg_delay;
-architecture behave of trg_delay is
-
- signal
-
-
+architecture behave of trg_delay is
+ signal from_shift_reg: std_logic;
+ signal reset_i:std_logic:='1';
+
begin
+reset_i<='0' after 100ns;
+
+PROC_ENABLEDELAY: process begin
+wait until rising_edge(clk_in);
+
+ if reg_onswitch='1' then
+ processed_signal <= from_shift_reg;
+ else
+ processed_signal <= signal_in;
+end if;
+end process;
+
+
+
+THE_SHIFT: entity work.delay_shift_reg
+ port map(
+ Din(0) => signal_in,
+ Addr => delay_time,
+ Clock => clk_in,
+ ClockEn => '1',
+ Reset => reset_i,
+ Q(0) => from_shift_reg
+ );
+
+
+
+
+
+
end behave;
architecture behave of trg_edgedetect is
-signal temp_save : std_logic_vector(31 downto 0);
+signal det_signal : std_logic_vector(31 downto 0);
+signal temp_save : std_logic_vector(31 downto 0);
+signal temp_save_2 : std_logic_vector(31 downto 0);
signal testing : std_logic_vector(31 downto 0):=x"00001111";
begin
+-- detect_synchronize: process is
+-- begin
+-- wait until rising_edge(clk_in);
+-- for i in 0 to 31 loop
+--
+--
+--
+-- end process;
+
detect_step1: process is
begin
wait until rising_edge(clk_in);
for i in 0 to 31 loop
temp_save(i)<=signals(i);
end loop;
-
end process;
+
+-- detect_step1_5: process is
+-- begin
+-- wait until rising_edge(clk_in);
+-- for i in 0 to 31 loop
+-- temp_save_2(i)<=temp_save(i);
+-- temp_save(i)<='0';
+-- end loop;
+-- end process;
+--
+
detect_step2: process is
begin
wait until rising_edge(clk_in);
begin
-enable: process is
+enable: process(signals) is
begin
--- wait until rising_edge(clk_in);
+-- wait until rising_edge(clk_in);
for i in 0 to 31 loop
if reg_inhalt(i) = '0' then
processed_signals(i) <= '0';
begin
-invert: process is
+invert: process(signals) is -- Ungetaktet
begin
--- wait until rising_edge(clk_in);
for i in 0 to 31 loop
if reg_inhalt(i) = '1' then
processed_signals(i) <= not signals(i);
end loop;
end process;
+-- invert: process begin -- Getaktet
+-- wait until rising_edge(clk_in);
+-- for i in 0 to 31 loop
+-- if reg_inhalt(i) = '1' then
+-- processed_signals(i) <= not signals(i);
+-- else
+-- processed_signals(i) <= signals(i);
+-- end if;
+-- end loop;
+-- end process;
+
+
end behave;
constant CHANNELS : integer := 32;
--Registers
-signal reg_bsp : std_logic_vector(31 downto 0);
-signal reg_enable : std_logic_vector(31 downto 0);
-signal reg_invert : std_logic_vector(31 downto 0);
-signal reg_delay : std_logic_vector(31 downto 0);
-
+signal reg_enable1 : std_logic_vector(CHANNELS-1 downto 0):=(others => '0');
+-- signal reg_enable2 : std_logic_vector(CHANNELS-1 downto 0);
+-- signal reg_enable3 : std_logic_vector(CHANNELS-1 downto 0);
+-- signal reg_enable4 : std_logic_vector(CHANNELS-1 downto 0);
+signal reg_invert1 : std_logic_vector(CHANNELS-1 downto 0):=(others => '0');
+-- signal reg_invert2 : std_logic_vector(CHANNELS-1 downto 0);
+-- signal reg_invert3 : std_logic_vector(CHANNELS-1 downto 0);
+-- signal reg_invert4 : std_logic_vector(CHANNELS-1 downto 0);
+signal reg_edgedetect1: std_logic_vector(CHANNELS-1 downto 0):=(others => '0');
+-- signal reg_edgedetect2: std_logic_vector(CHANNELS-1 downto 0);
+-- signal reg_edgedetect3: std_logic_vector(CHANNELS-1 downto 0);
+-- signal reg_edgedetect4: std_logic_vector(CHANNELS-1 downto 0);
+signal reg_delay1 : std_logic_vector(CHANNELS-1 downto 0):=(others => '0');
+-- signal reg_delay2 : std_logic_vector(CHANNELS-1 downto 0);
+-- signal reg_delay3 : std_logic_vector(CHANNELS-1 downto 0);
+-- signal reg_delay4 : std_logic_vector(CHANNELS-1 downto 0);
+signal reg_stretch1 : std_logic_vector(CHANNELS-1 downto 0):=(others => '0');
+-- signal reg_stretch2 : std_logic_vector(CHANNELS-1 downto 0);
+-- signal reg_stretch3 : std_logic_vector(CHANNELS-1 downto 0);
+-- signal reg_stretch4 : std_logic_vector(CHANNELS-1 downto 0);
-- Registers with values
-type Array10bit is array(31 downto 0) of std_logic_vector (9 downto 0); --stretch
-type Array7bit is array(31 downto 0) of std_logic_vector (6 downto 0); -- delay
-signal stretch_time : Array10bit;
-signal delay_time : Array7bit;
+type Array10bit is array(CHANNELS-1 downto 0) of std_logic_vector (9 downto 0); --stretch
+type Array8bit is array(CHANNELS-1 downto 0) of std_logic_vector (7 downto 0); -- delay
+type Array2bit is array(CHANNELS-1 downto 0) of std_logic_vector (1 downto 0); -- stretch_type ns us ms
+signal stretch_time : Array10bit:=(others => (others => '0'));
+signal delay_time : Array8bit:=(others => (others => '0'));
+signal stretch_type : Array2bit:=(others => (others => '0'));
-- hand over the signals
-signal enb_2_inv : std_logic_vector(31 downto 0);
-signal inv_2_det : std_logic_vector(31 downto 0);
-signal det_2_delay: std_logic_vector(31 downto 0);
-signal delay_2_str: std_logic_vector(31 downto 0);
-signal str_2_cion : std_logic_vector(31 downto 0);
-signal coin_2_out : std_logic_vector(31 downto 0);
+signal enb_2_inv : std_logic_vector(CHANNELS-1 downto 0);
+signal inv_2_det : std_logic_vector(CHANNELS-1 downto 0);
+signal det_2_delay: std_logic_vector(CHANNELS-1 downto 0);
+signal delay_2_str: std_logic_vector(CHANNELS-1 downto 0);
+signal str_2_cion : std_logic_vector(CHANNELS-1 downto 0);
+signal coin_2_out : std_logic_vector(CHANNELS-1 downto 0);
signal address_i : integer range 0 to 255;
+
--
address_i <= to_integer(unsigned(BUS_RX.addr(7 downto 0)));
-THE_REGS : process begin
+
+PROC_REGS : process begin
wait until rising_edge(CLK);
BUS_TX.ack <= '0';
BUS_TX.nack <= '0';
BUS_TX.unknown <= '0';
- if BUS_RX.read = '1' then
+ if BUS_RX.read = '1' then -- READ
BUS_TX.ack <= '1';
- if BUS_RX.addr(12 downto 8) = x"0" then
+ if BUS_RX.addr(11 downto 8) = x"0" then
case BUS_RX.addr(7 downto 0) is
- when x"00" => BUS_TX.data <= reg_bsp;
- when x"01" => BUS_TX.data <= reg_enable;
- when x"02" => BUS_TX.data <= reg_invert;
- when x"03" => BUS_TX.data <= reg_delay1;
- when x"04" => BUS_TX.data <= reg_delay2;
- when x"05" => BUS_TX.data <= reg_delay3;
+ when x"00" => BUS_TX.data <= reg_enable1;
+-- when x"01" => BUS_TX.data <= reg_enable2;
+-- when x"02" => BUS_TX.data <= reg_enable3;
+-- when x"03" => BUS_TX.data <= reg_enable4;
+ when x"04" => BUS_TX.data <= reg_invert1;
+-- when x"05" => BUS_TX.data <= reg_invert2;
+-- when x"06" => BUS_TX.data <= reg_invert3;
+-- when x"07" => BUS_TX.data <= reg_invert4;
+ when x"08" => BUS_TX.data <= reg_edgedetect1;
+-- when x"09" => BUS_TX.data <= reg_edgedetect2;
+-- when x"0A" => BUS_TX.data <= reg_edgedetect3;
+-- when x"0B" => BUS_TX.data <= reg_edgedetect4;
+ when x"0C" => BUS_TX.data <= reg_delay1;
+-- when x"0D" => BUS_TX.data <= reg_delay2;
+-- when x"0E" => BUS_TX.data <= reg_delay3;
+-- when x"0F" => BUS_TX.data <= reg_delay4;
+ when x"10" => BUS_TX.data <= reg_stretch1;
+-- when x"11" => BUS_TX.data <= reg_stretch2;
+-- when x"12" => BUS_TX.data <= reg_stretch3;
+-- when x"13" => BUS_TX.data <= reg_stretch4;
when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1';
end case;
- elsif BUS_RX.addr(12 downto 8) = x"1" then
+ elsif BUS_RX.addr(11 downto 8) = x"1" then --special adress for delay time declaration
if address_i < CHANNELS then
- BUS_TX.data <= x"00000" & "00000" & delay_time(address_i);
+ BUS_TX.data <= x"00000" & "0000" & delay_time(address_i);
else
BUS_TX.ack <= '0'; BUS_TX.unknown <= '1';
end if;
- elsif BUS_RX.addr(12 downto 8) = x"2" then
+ elsif BUS_RX.addr(11 downto 8) = x"2" then
if address_i < CHANNELS then
BUS_TX.data <= x"000" & "00" & stretch_type(address_i) & "000000" & stretch_time(address_i);
else
BUS_TX.ack <= '0'; BUS_TX.unknown <= '1';
end if;
end if;
- elsif BUS_RX.write = '1' then
+
+ elsif BUS_RX.write = '1' then --WRITE
BUS_TX.ack <= '1';
- case BUS_RX.addr(7 downto 0) is
- when x"00" => reg_bsp <= BUS_RX.data;
- when x"01" => reg_enable <= BUS_RX.data;
- when x"02" => reg_invert <= BUS_RX.data;
- when x"03" => reg_delay1 <= BUS_RX.data;
- when x"04" => reg_delay2 <= BUS_RX.data;
- when x"05" => reg_delay3 <= BUS_RX.data;
- when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1';
- end case;
+ if BUS_RX.addr(11 downto 8) = x"0" then -- better 11 downto 8
+ case BUS_RX.addr(7 downto 0) is
+ when x"00" => reg_enable1 <= BUS_RX.data;
+-- when x"01" => reg_enable2 <= BUS_RX.data;
+-- when x"02" => reg_enable3 <= BUS_RX.data;
+-- when x"03" => reg_enable4 <= BUS_RX.data;
+ when x"04" => reg_invert1 <= BUS_RX.data;
+-- when x"05" => reg_invert2 <= BUS_RX.data;
+-- when x"06" => reg_invert3 <= BUS_RX.data;
+-- when x"07" => reg_invert4 <= BUS_RX.data;
+ when x"08" => reg_edgedetect1 <= BUS_RX.data;
+-- when x"09" => reg_edgedetect2 <= BUS_RX.data;
+-- when x"0A" => reg_edgedetect3 <= BUS_RX.data;
+-- when x"0B" => reg_edgedetect4 <= BUS_RX.data;
+ when x"0C" => reg_delay1 <= BUS_RX.data;
+-- when x"0D" => reg_delay2 <= BUS_RX.data;
+-- when x"0E" => reg_delay3 <= BUS_RX.data;
+-- when x"0F" => reg_delay4 <= BUS_RX.data;
+ when x"10" => reg_stretch1 <= BUS_RX.data;
+-- when x"11" => reg_stretch2 <= BUS_RX.data;
+-- when x"12" => reg_stretch3 <= BUS_RX.data;
+-- when x"13" => reg_stretch4 <= BUS_RX.data;
+ when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1';
+ end case;
+ elsif BUS_RX.addr(11 downto 8) = x"1" then
+ if address_i < CHANNELS then
+ delay_time(address_i) <= BUS_RX.data(7 downto 0); -- better BUS_RX.data (7 downto 0)
+ else
+ BUS_TX.ack <= '0'; BUS_TX.unknown <= '1';
+ end if;
+ elsif BUS_RX.addr(11 downto 8) = x"2" then
+ if address_i < CHANNELS then
+ stretch_type(address_i) <= BUS_RX.data(17 downto 16);
+ stretch_time(address_i) <= BUS_RX.data(9 downto 0);
+ else
+ BUS_TX.ack <= '0'; BUS_TX.unknown <= '1';
+ end if;
+ end if;
end if;
end process;
-ENABLE : entity work.trg_enable
+THE_ENABLE : entity work.trg_enable
port map(
clk_in => CLK,
signals => INPUT,
- reg_inhalt => reg_enable,
+ reg_inhalt => reg_enable1,
processed_signals=> enb_2_inv
);
-INVERTER : entity work.trg_inverter
+THE_INVERTER : entity work.trg_inverter
port map(
clk_in => CLK,
signals => enb_2_inv,
- reg_inhalt => reg_invert,
+ reg_inhalt => reg_invert1,
processed_signals=> inv_2_det
);
-DETECT: entity work.trg_edgedetect
+THE_DETECT: entity work.trg_edgedetect
port map(
clk_in => CLK,
signals => inv_2_det,
+-- reg_inhalt => reg_edgedetect1,
processed_signals=> det_2_delay
);
-GEN_DELAYS : for i in 0 to CHANNELS - 1 generate
+GEN_DELAYS : for i in 0 to CHANNELS-1 generate
THE_DELAY: entity work.trg_delay
port map(
clk_in => CLK,
- signals => det_2_delay,
- reg_inhalt => reg_delay,
-
- processed_signals=> delay_2_str
+ signal_in => det_2_delay(i),
+ reg_onswitch => reg_delay1(i),
+ delay_time => delay_time(i),
+-- reset_i => RESET,
+ processed_signal=> delay_2_str(i)
+ );
+end generate;
+
+
+
+GEN_STRETCH : for i in 0 to CHANNELS-1 generate
+THE_STRETCH: entity work.trg_stretch
+
+ port map(
+ clk_in => CLK,
+ signal_in => delay_2_str(i),
+ stretch_type => stretch_type(i),
+ stretch_time => stretch_time(i),
+ processed_signal=> str_2_cion(i)
);
end generate;
+
+
end architecture;
entity trg_stretch is
port(
-
-
- )
+ clk_in : in std_logic;
+ signal_in : in std_logic;
+ stretch_type : in std_logic_vector (1 downto 0);
+ stretch_time : in std_logic_vector (9 downto 0);
+ processed_signal : out std_logic
+ );
end trg_stretch;
architecture behave of trg_stretch is
- SIGNAL ......:std_logic...;
-
-
-
+signal stretch_type_int : integer range 0 to 5;
+signal stretch_time_int : integer range 0 to 1022;
+signal timer_10 : unsigned(11 downto 0):= x"000";
+signal timer_11 : unsigned(11 downto 0):= x"000";
+signal pulse_10 : std_logic; -- every 10 us
+signal pulse_11 : std_logic; -- every 10 ms
+signal output : std_logic:='0';
+signal tester : unsigned(31 downto 0):= x"00000000";
+signal downcounter : integer range 0 to 1022;
+
+
begin
+ processed_signal<=output;
+ stretch_time_int <= to_integer(unsigned(stretch_time(9 downto 0))); -- umschreiben passt noch nicht
+ stretch_type_int <= to_integer(unsigned(stretch_type(1 downto 0)));
+ -- output <= '1';
+
+PROC_STRETCH_1: process begin
+ wait until rising_edge(clk_in);
+ if signal_in='1' then
+ output<='1';
+ downcounter<=stretch_time_int;
+-- elsif stretch_type=x"0" then
+
+ elsif signal_in='0' then
+ if stretch_type_int = 1 then
+ tester<= tester +1 ;
+ if downcounter> 0 then
+ downcounter <= downcounter -1;
+ else
+ output<='0';
+ end if;
+ end if;
+ if stretch_type_int= 2 then
+ if downcounter > 0 and pulse_10='1' then
+ downcounter<= downcounter -1 ;
+ else
+ output<='0';
+ end if;
+ end if;
+ if stretch_type_int = 3 then
+ if downcounter>0 and pulse_11='1' then
+ downcounter<= downcounter -1 ;
+ else
+ output<='0';
+ end if;
+ end if;
+ end if;
+end process;
+
+
+PROC_PULSEGENERATOR: process begin
+ wait until rising_edge (clk_in);
+
+ if timer_10=x"3E8" then
+ pulse_10<='1';
+ timer_10<=x"000" ;
+ else
+ timer_10 <= timer_10+1;
+ pulse_10<='0';
+ end if;
+ if timer_11= x"3E8"then
+ pulse_11<='1';
+ timer_11<=x"000";
+ elsif pulse_10='1' then
+ timer_11<=timer_11+1;
+ pulse_11<='0';
+ else
+ pulse_11<='0';
+ end if;
+ end process;
+
+
+
end behave;
jspc29 / triggerlogic.git / commitdiff