]> jspc29.x-matter.uni-frankfurt.de Git - TOMcat.git/commitdiff
first Trudy/Eve combination
authorMichael Boehmer <mboehmer@ph.tum.de>
Fri, 5 Aug 2022 06:46:06 +0000 (08:46 +0200)
committerMichael Boehmer <mboehmer@ph.tum.de>
Fri, 5 Aug 2022 06:46:06 +0000 (08:46 +0200)
code/tomcat_tools.vhd
gbe/tomcat_gbe.prj
gbe/tomcat_gbe.vhd

index ad8596e348cb84363eaa9630122fcc97e85702d7..1bb517bd516608a6283711b83835feb878c3591e 100644 (file)
@@ -29,10 +29,13 @@ entity tomcat_tools is
     -- Additional regs
     ADDITIONAL_REG    : out   std_logic_vector(31 downto 0);
     CTRL_REG          : out   std_logic_vector(31 downto 0);
+    AUX_REG           : out   std_logic_vector(31 downto 0);
     -- Ethernet registers
     FWD_MAC_OUT       : out   std_logic_vector(47 downto 0);
     FWD_IP_OUT        : out   std_logic_vector(31 downto 0);
     FWD_PORT_OUT      : out   std_logic_vector(15 downto 0);
+    -- Trigger
+    TRIGGER_OUT       : out   std_logic;
     -- I2C
     SDA_INOUT         : inout std_logic;
     SCL_INOUT         : inout std_logic;
@@ -233,14 +236,16 @@ end generate;
   end process THE_ADD_REG_PROC;
 
   ADDITIONAL_REG <= add_reg0_i;
-
-  CTRL_REG <= add_reg1_i;
+  CTRL_REG       <= add_reg1_i;
+  AUX_REG        <= add_reg2_i;
   
   FWD_MAC_OUT(31 downto 0)  <= add_reg4_i;
   FWD_MAC_OUT(47 downto 32) <= add_reg5_i(15 downto 0);
   FWD_IP_OUT                <= add_reg6_i;
   FWD_PORT_OUT              <= add_reg7_i(15 downto 0);
 
+  TRIGGER_OUT <= '1' when (busctrl_rx.write = '1') and (busctrl_rx.addr(2 downto 0) = b"011") else '0';
+  
 ---------------------------------------------------------------------------
 -- I2C
 ---------------------------------------------------------------------------
index 6fdb4da0c92b7c7a22a7537276a980d5fc12a159..00a917dabae5aa78934a2c45169996d25b00d21e 100644 (file)
@@ -201,6 +201,11 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_
 add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd"
 #add_file -verilog -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5-5g/serdes_gbe_softlogic.v"
 
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/inserter.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/remover.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/cores/fifo_inserter.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/cores/fifo_remover.vhd"
+
 add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4096x9.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x72.vhd"
index a857b5264ce3903b94d2822518128585269e8f9c..24a8146e389d05db9ccdfd8ecb627dc1ffee8331 100644 (file)
@@ -178,6 +178,7 @@ architecture arch of tomcat_gbe is
   signal fwd_busy_int               : std_logic;
   
   signal control_reg                : std_logic_vector(31 downto 0);
+  signal aux_reg                    : std_logic_vector(31 downto 0);
 
   signal tick_ms_int                : std_logic;
   signal tick_us_int                : std_logic;
@@ -193,6 +194,15 @@ architecture arch of tomcat_gbe is
   signal oob_reg_2_int              : std_logic_vector(31 downto 0);
   signal oob_reg_3_int              : std_logic_vector(31 downto 0);
   
+  signal dlm_found_int              : std_logic;
+  signal dlm_inject_int             : std_logic;
+  signal dlm_tx_data_int            : std_logic_vector(7 downto 0);
+  signal dlm_rx_data_int            : std_logic_vector(7 downto 0);
+  
+  signal dlm_ctr                    : unsigned(23 downto 0);
+  signal rst_dlm_ctr_x              : std_logic;
+  signal rst_dlm_ctr                : std_logic;
+  
 begin
 
 ---------------------------------------------------------------------------
@@ -240,12 +250,29 @@ begin
   end if;
 end process THE_BLINK_COUNTER_PROC;
 
+---------------------------------------------------------------------------
+---------------------------------------------------------------------------
+-- DLM timing generator
+THE_DLM_SEND_PROC: process( clk_sys )
+begin
+  if( rising_edge(clk_sys) ) then
+    rst_dlm_ctr <= rst_dlm_ctr_x;
+    if( (reset_i = '1') or (rst_dlm_ctr = '1') or (aux_reg(31) = '0') ) then
+      dlm_ctr <= (others => '0');
+    elsif( aux_reg(31) = '1' ) then
+      dlm_ctr <= dlm_ctr + 1;
+    end if;
+  end if;
+end process THE_DLM_SEND_PROC;
+
+rst_dlm_ctr_x <= '1' when ((std_logic_vector(dlm_ctr) = aux_reg(23 downto 0)) and (aux_reg(31) = '1')) else '0';
+
 ---------------------------------------------------------------------------
 -- GbE interface (SFP)
 ---------------------------------------------------------------------------
   GBE_SFP_INTERFACE: entity gbe_med_fifo
   generic map(
-    SERDES_NUM => 3
+    SERDES_NUM => 0
   )
   port map(
     RESET                 => reset_i,
@@ -279,19 +306,24 @@ end process THE_BLINK_COUNTER_PROC;
     PCS_AN_READY_OUT      => open,
     LINK_ACTIVE_OUT       => link_active, -- only needed on UL port for SCTRL
     TICK_MS_IN            => tick_ms_int,
+    -- DLM
+    DLM_INJECT_IN         => '0',
+    DLM_DATA_IN           => x"00",
+    DLM_FOUND_OUT         => open,
+    DLM_DATA_OUT          => open,
     -- Debug
     STATUS_OUT            => status(7 downto 0),
     DEBUG_OUT             => open
   );
 
-  debug(127 downto 34) <= (others => '0');
+  debug(127 downto 64) <= (others => '0');
   
 ---------------------------------------------------------------------------
 -- GbE interface (copper)
 ---------------------------------------------------------------------------
   GBE_COPPER_INTERFACE: entity gbe_med_fifo
   generic map(
-    SERDES_NUM => 0
+    SERDES_NUM => 3
   )
   port map(
     RESET                 => reset_i,
@@ -321,11 +353,19 @@ end process THE_BLINK_COUNTER_PROC;
     PCS_AN_READY_OUT      => open,
     LINK_ACTIVE_OUT       => open,
     TICK_MS_IN            => tick_ms_int,
+    -- DLM
+    DLM_INJECT_IN         => dlm_inject_int,
+    DLM_DATA_IN           => dlm_tx_data_int,
+    DLM_FOUND_OUT         => dlm_found_int,
+    DLM_DATA_OUT          => dlm_rx_data_int,
     -- Debug
     STATUS_OUT            => open,
-    DEBUG_OUT             => open
+    DEBUG_OUT             => debug(63 downto 0) --open
   );
 
+  dlm_inject_int  <= rst_dlm_ctr;
+  dlm_tx_data_int <= control_reg(7 downto 0);
+  
 ---------------------------------------------------------------------------
 ---------------------------------------------------------------------------
   THE_SGL_CTRL: entity sgl_ctrl
@@ -358,23 +398,23 @@ end process THE_BLINK_COUNTER_PROC;
 -- 33 = CLK2 (white/green)
 -- 32 = CLK1 (white/blue)
   
-  debug(7 downto 0)    <= ul_rx_data(7 downto 0);
-  debug(15 downto 8)   <= ul_tx_data(7 downto 0);
-  debug(16)            <= ul_rx_data(9);
-  debug(17)            <= ul_tx_data(9);
-  debug(18)            <= ul_rx_data(10);
-  debug(19)            <= ul_tx_data(10);
-  debug(20) <= ul_rx_data(8);
-  debug(21) <= ul_tx_data(8);
-  debug(22) <= ul_rx_frame_req;
-  debug(23) <= ul_rx_frame_ack;
-  debug(24) <= ul_rx_frame_avail;
-  debug(25) <= dl_rx_frame_req(0);
-  debug(26) <= dl_rx_frame_ack(0);
-  debug(27) <= dl_rx_frame_avail(0);
-  debug(31 downto 28) <= sgl_debug(3 downto 0);
-  debug(32) <= dl_rx_port_mux(1);
-  debug(33) <= clk_sys;
+--  debug(7 downto 0)    <= ul_rx_data(7 downto 0);
+--  debug(15 downto 8)   <= ul_tx_data(7 downto 0);
+--  debug(16)            <= ul_rx_data(9);
+--  debug(17)            <= ul_tx_data(9);
+--  debug(18)            <= ul_rx_data(10);
+--  debug(19)            <= ul_tx_data(10);
+--  debug(20) <= ul_rx_data(8);
+--  debug(21) <= ul_tx_data(8);
+--  debug(22) <= ul_rx_frame_req;
+--  debug(23) <= ul_rx_frame_ack;
+--  debug(24) <= ul_rx_frame_avail;
+--  debug(25) <= dl_rx_frame_req(0);
+--  debug(26) <= dl_rx_frame_ack(0);
+--  debug(27) <= dl_rx_frame_avail(0);
+--  debug(31 downto 28) <= sgl_debug(3 downto 0);
+--  debug(32) <= dl_rx_port_mux(1);
+--  debug(33) <= clk_sys;
 
 ---------------------------------------------------------------------------
 -- Multiplexers for data streams
@@ -590,10 +630,13 @@ end process THE_BLINK_COUNTER_PROC;
       -- Additional register
       ADDITIONAL_REG     => additional_reg,
       CTRL_REG           => control_reg,
+      AUX_REG            => aux_reg,
       -- Ethernet registers
       FWD_MAC_OUT        => fwd_mac_int,
       FWD_IP_OUT         => fwd_ip_int,
       FWD_PORT_OUT       => fwd_port_int,
+      -- Trigger
+      TRIGGER_OUT        => open,
       --Slowcontrol
       BUS_RX             => bustools_rx,
       BUS_TX             => bustools_tx,
@@ -636,7 +679,7 @@ end process THE_BLINK_COUNTER_PROC;
 --  GPIO(13 downto 13)  <= debug(33 downto 33);
 --  GPIO                <= (others => 'Z');
   
-  TIMING_TEST         <= reset_via_gbe; --'0';
+  TIMING_TEST         <= dlm_found_int; --'0';
 
 -------------------------------------------------------------------------------
 -- LED
@@ -644,10 +687,10 @@ end process THE_BLINK_COUNTER_PROC;
   LED_SFP_GREEN   <= not (status(0) and status(1) and status(2)); --'0';
   LED_SFP_YELLOW  <= not status(5); --'0';
   LED_SFP_RED     <= not status(6); --'0';
-  LED(3)          <= not std_logic(blink_counter(8)); --additional_reg(7); --'0';
-  LED(2)          <= not additional_reg(6); --'0';
-  LED(1)          <= not additional_reg(5); --'0';
-  LED(0)          <= not additional_reg(4); --'0';
+  LED(3)          <= not std_logic(blink_counter(5)); --additional_reg(7); --'0';
+  LED(2)          <= not dlm_rx_data_int(2); --additional_reg(6); --'0';
+  LED(1)          <= not dlm_rx_data_int(1); --additional_reg(5); --'0';
+  LED(0)          <= not dlm_rx_data_int(0); --additional_reg(4); --'0';
 
   -- 0 red
   -- 1 orange