signal fwd_busy_int : std_logic;
signal control_reg : std_logic_vector(31 downto 0);
+ signal aux_reg : std_logic_vector(31 downto 0);
signal tick_ms_int : std_logic;
signal tick_us_int : std_logic;
signal oob_reg_2_int : std_logic_vector(31 downto 0);
signal oob_reg_3_int : std_logic_vector(31 downto 0);
+ signal dlm_found_int : std_logic;
+ signal dlm_inject_int : std_logic;
+ signal dlm_tx_data_int : std_logic_vector(7 downto 0);
+ signal dlm_rx_data_int : std_logic_vector(7 downto 0);
+
+ signal dlm_ctr : unsigned(23 downto 0);
+ signal rst_dlm_ctr_x : std_logic;
+ signal rst_dlm_ctr : std_logic;
+
begin
---------------------------------------------------------------------------
end if;
end process THE_BLINK_COUNTER_PROC;
+---------------------------------------------------------------------------
+---------------------------------------------------------------------------
+-- DLM timing generator
+THE_DLM_SEND_PROC: process( clk_sys )
+begin
+ if( rising_edge(clk_sys) ) then
+ rst_dlm_ctr <= rst_dlm_ctr_x;
+ if( (reset_i = '1') or (rst_dlm_ctr = '1') or (aux_reg(31) = '0') ) then
+ dlm_ctr <= (others => '0');
+ elsif( aux_reg(31) = '1' ) then
+ dlm_ctr <= dlm_ctr + 1;
+ end if;
+ end if;
+end process THE_DLM_SEND_PROC;
+
+rst_dlm_ctr_x <= '1' when ((std_logic_vector(dlm_ctr) = aux_reg(23 downto 0)) and (aux_reg(31) = '1')) else '0';
+
---------------------------------------------------------------------------
-- GbE interface (SFP)
---------------------------------------------------------------------------
GBE_SFP_INTERFACE: entity gbe_med_fifo
generic map(
- SERDES_NUM => 3
+ SERDES_NUM => 0
)
port map(
RESET => reset_i,
PCS_AN_READY_OUT => open,
LINK_ACTIVE_OUT => link_active, -- only needed on UL port for SCTRL
TICK_MS_IN => tick_ms_int,
+ -- DLM
+ DLM_INJECT_IN => '0',
+ DLM_DATA_IN => x"00",
+ DLM_FOUND_OUT => open,
+ DLM_DATA_OUT => open,
-- Debug
STATUS_OUT => status(7 downto 0),
DEBUG_OUT => open
);
- debug(127 downto 34) <= (others => '0');
+ debug(127 downto 64) <= (others => '0');
---------------------------------------------------------------------------
-- GbE interface (copper)
---------------------------------------------------------------------------
GBE_COPPER_INTERFACE: entity gbe_med_fifo
generic map(
- SERDES_NUM => 0
+ SERDES_NUM => 3
)
port map(
RESET => reset_i,
PCS_AN_READY_OUT => open,
LINK_ACTIVE_OUT => open,
TICK_MS_IN => tick_ms_int,
+ -- DLM
+ DLM_INJECT_IN => dlm_inject_int,
+ DLM_DATA_IN => dlm_tx_data_int,
+ DLM_FOUND_OUT => dlm_found_int,
+ DLM_DATA_OUT => dlm_rx_data_int,
-- Debug
STATUS_OUT => open,
- DEBUG_OUT => open
+ DEBUG_OUT => debug(63 downto 0) --open
);
+ dlm_inject_int <= rst_dlm_ctr;
+ dlm_tx_data_int <= control_reg(7 downto 0);
+
---------------------------------------------------------------------------
---------------------------------------------------------------------------
THE_SGL_CTRL: entity sgl_ctrl
-- 33 = CLK2 (white/green)
-- 32 = CLK1 (white/blue)
- debug(7 downto 0) <= ul_rx_data(7 downto 0);
- debug(15 downto 8) <= ul_tx_data(7 downto 0);
- debug(16) <= ul_rx_data(9);
- debug(17) <= ul_tx_data(9);
- debug(18) <= ul_rx_data(10);
- debug(19) <= ul_tx_data(10);
- debug(20) <= ul_rx_data(8);
- debug(21) <= ul_tx_data(8);
- debug(22) <= ul_rx_frame_req;
- debug(23) <= ul_rx_frame_ack;
- debug(24) <= ul_rx_frame_avail;
- debug(25) <= dl_rx_frame_req(0);
- debug(26) <= dl_rx_frame_ack(0);
- debug(27) <= dl_rx_frame_avail(0);
- debug(31 downto 28) <= sgl_debug(3 downto 0);
- debug(32) <= dl_rx_port_mux(1);
- debug(33) <= clk_sys;
+-- debug(7 downto 0) <= ul_rx_data(7 downto 0);
+-- debug(15 downto 8) <= ul_tx_data(7 downto 0);
+-- debug(16) <= ul_rx_data(9);
+-- debug(17) <= ul_tx_data(9);
+-- debug(18) <= ul_rx_data(10);
+-- debug(19) <= ul_tx_data(10);
+-- debug(20) <= ul_rx_data(8);
+-- debug(21) <= ul_tx_data(8);
+-- debug(22) <= ul_rx_frame_req;
+-- debug(23) <= ul_rx_frame_ack;
+-- debug(24) <= ul_rx_frame_avail;
+-- debug(25) <= dl_rx_frame_req(0);
+-- debug(26) <= dl_rx_frame_ack(0);
+-- debug(27) <= dl_rx_frame_avail(0);
+-- debug(31 downto 28) <= sgl_debug(3 downto 0);
+-- debug(32) <= dl_rx_port_mux(1);
+-- debug(33) <= clk_sys;
---------------------------------------------------------------------------
-- Multiplexers for data streams
-- Additional register
ADDITIONAL_REG => additional_reg,
CTRL_REG => control_reg,
+ AUX_REG => aux_reg,
-- Ethernet registers
FWD_MAC_OUT => fwd_mac_int,
FWD_IP_OUT => fwd_ip_int,
FWD_PORT_OUT => fwd_port_int,
+ -- Trigger
+ TRIGGER_OUT => open,
--Slowcontrol
BUS_RX => bustools_rx,
BUS_TX => bustools_tx,
-- GPIO(13 downto 13) <= debug(33 downto 33);
-- GPIO <= (others => 'Z');
- TIMING_TEST <= reset_via_gbe; --'0';
+ TIMING_TEST <= dlm_found_int; --'0';
-------------------------------------------------------------------------------
-- LED
LED_SFP_GREEN <= not (status(0) and status(1) and status(2)); --'0';
LED_SFP_YELLOW <= not status(5); --'0';
LED_SFP_RED <= not status(6); --'0';
- LED(3) <= not std_logic(blink_counter(8)); --additional_reg(7); --'0';
- LED(2) <= not additional_reg(6); --'0';
- LED(1) <= not additional_reg(5); --'0';
- LED(0) <= not additional_reg(4); --'0';
+ LED(3) <= not std_logic(blink_counter(5)); --additional_reg(7); --'0';
+ LED(2) <= not dlm_rx_data_int(2); --additional_reg(6); --'0';
+ LED(1) <= not dlm_rx_data_int(1); --additional_reg(5); --'0';
+ LED(0) <= not dlm_rx_data_int(0); --additional_reg(4); --'0';
-- 0 red
-- 1 orange