package trb3_components is
+ type std_logic_vector_array_24 is array (integer range <>) of std_logic_vector(23 downto 0);
+ type std_logic_vector_array_32 is array (integer range <>) of std_logic_vector(31 downto 0);
+
component pll_in200_out100
port (
CLK : in std_logic;
DATA_OUT : out std_logic_vector(31 downto 0);
DATA_WRITE_OUT : out std_logic;
DATA_FINISHED_OUT : out std_logic;
+ HCB_READ_EN_IN : in std_logic;
+ HCB_WRITE_EN_IN : in std_logic;
+ HCB_ADDR_IN : in std_logic_vector(6 downto 0);
+ HCB_DATA_OUT : out std_logic_vector(31 downto 0);
+ HCB_DATAREADY_OUT : out std_logic;
+ HCB_UNKNOWN_ADDR_OUT : out std_logic;
TDC_DEBUG : out std_logic_vector(32*2**STATUS_REG_NR-1 downto 0);
LOGIC_ANALYSER_OUT : out std_logic_vector(15 downto 0);
CONTROL_REG_IN : in std_logic_vector(32*2**CONTROL_REG_NR-1 downto 0));
generic (
CHANNEL_ID : integer range 0 to 0);
port (
- RESET_WR : in std_logic;
- RESET_RD : in std_logic;
- CLK_WR : in std_logic;
- CLK_RD : in std_logic;
- HIT_IN : in std_logic;
- READ_EN_IN : in std_logic;
- VALID_TMG_TRG_IN : in std_logic;
- SPIKE_DETECTED_IN : in std_logic;
- MULTI_TMG_TRG_IN : in std_logic;
- FIFO_DATA_OUT : out std_logic_vector(31 downto 0);
- FIFO_EMPTY_OUT : out std_logic;
- FIFO_FULL_OUT : out std_logic;
- FIFO_ALMOST_FULL_OUT : out std_logic;
- COARSE_COUNTER_IN : in std_logic_vector(10 downto 0);
- TRIGGER_TIME_OUT : out std_logic_vector(10 downto 0);
- REF_DEBUG_OUT : out std_logic_vector(31 downto 0));
+ RESET_200 : in std_logic;
+ RESET_100 : in std_logic;
+ CLK_200 : in std_logic;
+ CLK_100 : in std_logic;
+ HIT_IN : in std_logic;
+ READ_EN_IN : in std_logic;
+ VALID_TMG_TRG_IN : in std_logic;
+ SPIKE_DETECTED_IN : in std_logic;
+ MULTI_TMG_TRG_IN : in std_logic;
+ FIFO_DATA_OUT : out std_logic_vector(31 downto 0);
+ FIFO_EMPTY_OUT : out std_logic;
+ FIFO_FULL_OUT : out std_logic;
+ FIFO_ALMOST_FULL_OUT : out std_logic;
+ COARSE_COUNTER_IN : in std_logic_vector(10 downto 0);
+ EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0);
+ TRIGGER_WINDOW_END_IN : in std_logic;
+ DATA_FINISHED_IN : in std_logic;
+ RUN_MODE : in std_logic;
+ TRIGGER_TIME_STAMP_OUT : out std_logic_vector(38 downto 0);
+ REF_DEBUG_OUT : out std_logic_vector(31 downto 0));
+ end component;
+
+ component Reference_Channel_200
+ generic (
+ CHANNEL_ID : integer range 0 to 0);
+ port (
+ CLK_200 : in std_logic;
+ RESET_200 : in std_logic;
+ CLK_100 : in std_logic;
+ RESET_100 : in std_logic;
+ VALID_TMG_TRG_IN : in std_logic;
+ SPIKE_DETECTED_IN : in std_logic;
+ MULTI_TMG_TRG_IN : in std_logic;
+ HIT_IN : in std_logic;
+ READ_EN_IN : in std_logic;
+ FIFO_DATA_OUT : out std_logic_vector(31 downto 0);
+ FIFO_EMPTY_OUT : out std_logic;
+ FIFO_FULL_OUT : out std_logic;
+ FIFO_ALMOST_FULL_OUT : out std_logic;
+ EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0);
+ TRIGGER_WINDOW_END_IN : in std_logic;
+ TRIGGER_TIME_STAMP_OUT : out std_logic_vector(38 downto 0);
+ DATA_FINISHED_IN : in std_logic;
+ RUN_MODE : in std_logic;
+ COARSE_COUNTER_IN : in std_logic_vector(10 downto 0));
end component;
component Channel
generic (
CHANNEL_ID : integer range 1 to 64);
port (
- RESET_200 : in std_logic;
- RESET_100 : in std_logic;
- CLK_200 : in std_logic;
- CLK_100 : in std_logic;
- HIT_IN : in std_logic;
- READ_EN_IN : in std_logic;
- FIFO_DATA_OUT : out std_logic_vector(31 downto 0);
- FIFO_EMPTY_OUT : out std_logic;
- FIFO_FULL_OUT : out std_logic;
- FIFO_ALMOST_FULL_OUT : out std_logic;
- COARSE_COUNTER_IN : in std_logic_vector(10 downto 0);
- LOST_HIT_NUMBER : out std_logic_vector(23 downto 0);
- HIT_DETECT_NUMBER : out std_logic_vector(23 downto 0);
- ENCODER_START_NUMBER : out std_logic_vector(23 downto 0);
- FIFO_WR_NUMBER : out std_logic_vector(23 downto 0);
- Channel_DEBUG : out std_logic_vector(31 downto 0));
+ RESET_200 : in std_logic;
+ RESET_100 : in std_logic;
+ RESET_COUNTERS : in std_logic;
+ CLK_200 : in std_logic;
+ CLK_100 : in std_logic;
+ HIT_IN : in std_logic;
+ SCALER_IN : in std_logic;
+ READ_EN_IN : in std_logic;
+ FIFO_DATA_OUT : out std_logic_vector(31 downto 0);
+ FIFO_EMPTY_OUT : out std_logic;
+ FIFO_FULL_OUT : out std_logic;
+ FIFO_ALMOST_FULL_OUT : out std_logic;
+ COARSE_COUNTER_IN : in std_logic_vector(10 downto 0);
+ EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0);
+ TRIGGER_WINDOW_END_IN : in std_logic;
+ DATA_FINISHED_IN : in std_logic;
+ RUN_MODE : in std_logic;
+ LOST_HIT_NUMBER : out std_logic_vector(23 downto 0);
+ HIT_DETECT_NUMBER : out std_logic_vector(23 downto 0);
+ ENCODER_START_NUMBER : out std_logic_vector(23 downto 0);
+ FIFO_WR_NUMBER : out std_logic_vector(23 downto 0);
+ Channel_DEBUG : out std_logic_vector(31 downto 0));
end component;
component Channel_200
generic (
- CHANNEL_ID : integer range 0 to 64);
+ CHANNEL_ID : integer range 1 to 64);
port (
- CLK_200 : in std_logic;
- RESET_200 : in std_logic;
- CLK_100 : in std_logic;
- RESET_100 : in std_logic;
- HIT_IN : in std_logic;
- HIT_DETECT_OUT : out std_logic;
- TIME_STAMP_IN : in std_logic_vector(10 downto 0);
- READ_EN_IN : in std_logic;
- FIFO_DATA_OUT : out std_logic_vector(31 downto 0);
- FIFO_EMPTY_OUT : out std_logic;
- FIFO_FULL_OUT : out std_logic;
- FIFO_ALMOST_FULL_OUT : out std_logic;
- FIFO_WR_OUT : out std_logic;
- ENCODER_START_OUT : out std_logic);
+ CLK_200 : in std_logic;
+ RESET_200 : in std_logic;
+ CLK_100 : in std_logic;
+ RESET_100 : in std_logic;
+ RESET_COUNTERS : in std_logic;
+ HIT_IN : in std_logic;
+-- HIT_DETECT_OUT : out std_logic;
+-- TIME_STAMP_IN : in std_logic_vector(10 downto 0);
+ SCALER_IN : in std_logic;
+ EPOCH_COUNTER_IN : in std_logic_vector(27 downto 0);
+ TRIGGER_WINDOW_END_IN : in std_logic;
+ DATA_FINISHED_IN : in std_logic;
+ RUN_MODE : in std_logic;
+ COARSE_COUNTER_IN : in std_logic_vector(10 downto 0);
+ READ_EN_IN : in std_logic;
+ FIFO_DATA_OUT : out std_logic_vector(31 downto 0);
+ FIFO_EMPTY_OUT : out std_logic;
+ FIFO_FULL_OUT : out std_logic;
+ FIFO_ALMOST_FULL_OUT : out std_logic;
+-- FIFO_WR_OUT : out std_logic;
+-- ENCODER_START_OUT : out std_logic;
+ LOST_HIT_NUMBER : out std_logic_vector(23 downto 0);
+ HIT_DETECT_NUMBER : out std_logic_vector(23 downto 0);
+ ENCODER_START_NUMBER : out std_logic_vector(23 downto 0);
+ FIFO_WR_NUMBER : out std_logic_vector(23 downto 0));
+ end component;
+
+ component BusHandler
+ generic (
+ CHANNEL_NUMBER : integer range 0 to 64 := 2);
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ DATA_IN : in std_logic_vector_array_32(0 to CHANNEL_NUMBER);
+ READ_EN_IN : in std_logic;
+ WRITE_EN_IN : in std_logic;
+ ADDR_IN : in std_logic_vector(6 downto 0);
+ DATA_OUT : out std_logic_vector(31 downto 0);
+ DATAREADY_OUT : out std_logic;
+ UNKNOWN_ADDR_OUT : out std_logic);
end component;
component ROM_FIFO
AlmostFull : out std_logic);
end component;
+ component FIFO_24x2_OutReg
+ port (
+ Data : in std_logic_vector(23 downto 0);
+ WrClock : in std_logic;
+ RdClock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ RPReset : in std_logic;
+ Q : out std_logic_vector(23 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic);
+ end component;
+
component ROM_Encoder
port (
Address : in std_logic_vector(9 downto 0);
signal_in : in std_logic;
pulse : out std_logic);
end component;
-
-component adc_ad9222
- generic(
- CHANNELS : integer range 4 to 4 := 4;
- DEVICES : integer range 2 to 2 := 2;
- RESOLUTION : integer range 12 to 12 := 12
- );
- port(
- CLK : in std_logic;
- CLK_ADCREF : in std_logic;
- CLK_ADCDAT : in std_logic;
- RESTART_IN : in std_logic;
- ADCCLK_OUT : out std_logic;
- ADC_DATA : in std_logic_vector(DEVICES*CHANNELS-1 downto 0);
- ADC_DCO : in std_logic_vector(DEVICES-1 downto 0);
- ADC_FCO : in std_logic_vector(DEVICES-1 downto 0);
-
- DATA_OUT : out std_logic_vector(DEVICES*CHANNELS*RESOLUTION-1 downto 0);
- FCO_OUT : out std_logic_vector(DEVICES*RESOLUTION-1 downto 0);
- DATA_VALID_OUT : out std_logic_vector(DEVICES-1 downto 0);
- DEBUG : out std_logic_vector(31 downto 0)
-
- );
-end component;
-component fifo_32x512
+ component ShiftRegisterSISO
+ generic (
+ DEPTH : integer range 1 to 32;
+ WIDTH : integer range 1 to 32);
port (
- Data: in std_logic_vector(31 downto 0);
- Clock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- Q: out std_logic_vector(31 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end component;
+ CLK : in std_logic;
+ RESET : in std_logic;
+ D_IN : in std_logic_vector(WIDTH-1 downto 0);
+ D_OUT : out std_logic_vector(WIDTH-1 downto 0));
+ end component;
+
+ component adc_ad9222
+ generic(
+ CHANNELS : integer range 4 to 4 := 4;
+ DEVICES : integer range 2 to 2 := 2;
+ RESOLUTION : integer range 12 to 12 := 12
+ );
+ port(
+ CLK : in std_logic;
+ CLK_ADCREF : in std_logic;
+ CLK_ADCDAT : in std_logic;
+ RESTART_IN : in std_logic;
+ ADCCLK_OUT : out std_logic;
+ ADC_DATA : in std_logic_vector(DEVICES*CHANNELS-1 downto 0);
+ ADC_DCO : in std_logic_vector(DEVICES-1 downto 0);
+ ADC_FCO : in std_logic_vector(DEVICES-1 downto 0);
+
+ DATA_OUT : out std_logic_vector(DEVICES*CHANNELS*RESOLUTION-1 downto 0);
+ FCO_OUT : out std_logic_vector(DEVICES*RESOLUTION-1 downto 0);
+ DATA_VALID_OUT : out std_logic_vector(DEVICES-1 downto 0);
+ DEBUG : out std_logic_vector(31 downto 0)
+ );
+ end component;
+ component fifo_32x512
+ port (
+ Data : in std_logic_vector(31 downto 0);
+ Clock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ Q : out std_logic_vector(31 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic);
+ end component;
-component dqsinput
+ component dqsinput
port (
- clk_0: in std_logic;
- clk_1: in std_logic;
- clkdiv_reset: in std_logic;
- eclk: in std_logic;
- reset_0: in std_logic;
- reset_1: in std_logic;
- sclk: out std_logic;
- datain_0: in std_logic_vector(4 downto 0);
- datain_1: in std_logic_vector(4 downto 0);
- q_0: out std_logic_vector(19 downto 0);
- q_1: out std_logic_vector(19 downto 0)
- );
-end component;
+ clk_0 : in std_logic;
+ clk_1 : in std_logic;
+ clkdiv_reset : in std_logic;
+ eclk : in std_logic;
+ reset_0 : in std_logic;
+ reset_1 : in std_logic;
+ sclk : out std_logic;
+ datain_0 : in std_logic_vector(4 downto 0);
+ datain_1 : in std_logic_vector(4 downto 0);
+ q_0 : out std_logic_vector(19 downto 0);
+ q_1 : out std_logic_vector(19 downto 0)
+ );
+ end component;
-component fifo_cdt_200
+ component fifo_cdt_200
port (
- Data: in std_logic_vector(59 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(59 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end component;
+ Data : in std_logic_vector(59 downto 0);
+ WrClock : in std_logic;
+ RdClock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ RPReset : in std_logic;
+ Q : out std_logic_vector(59 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic);
+ end component;
#################################################################
# Basic Settings
#################################################################
+
SYSCONFIG MCCLK_FREQ = 20;
+
FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;
FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;
#################################################################
# Clock I/O
#################################################################
-LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20";
-LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18";
-LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10";
LOCATE COMP "CLK_GPLL_LEFT" SITE "U25";
-
-LOCATE COMP "CLK_PCLK_LEFT" SITE "M4";
LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1";
+LOCATE COMP "CLK_PCLK_LEFT" SITE "M4";
+LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20";
+LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10";
+LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18";
DEFINE PORT GROUP "CLK_group" "CLK*" ;
IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;
-
#################################################################
# Trigger I/O
#################################################################
#Trigger from fan-out
-#LOCATE COMP "TRIGGER_RIGHT" SITE "N24";
-#IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25;
+LOCATE COMP "TRIGGER_RIGHT" SITE "N24";
+IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25;
LOCATE COMP "TRIGGER_LEFT" SITE "V3";
IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25;
-
-
#################################################################
# To central FPGA
#################################################################
-# LOCATE COMP "DQUL_44" SITE "L2";
-# LOCATE COMP "DQUL_45" SITE "L1";
-# LOCATE COMP "OUT_H_SDO" SITE "AA24"; #"DQLR_20" DQLR1_6 #185
-# LOCATE COMP "OUT_H_SDOb" SITE "AA23"; #"DQLR_21" DQLR1_7 #187
-# LOCATE COMP "IN_H_SDI" SITE "AD26"; #"DQLR_22" DQLR1_8 #189
-# LOCATE COMP "IN_H_SDIbD" SITE "AD25"; #"DQLR_23" DQLR1_9 #191
-# LOCATE COMP "OUT_H_SCK" SITE "U24"; #"DQLR_32" DQLR2_6 #186
-# LOCATE COMP "OUT_H_SCKb" SITE "V24"; #"DQLR_33" DQLR2_7 #188
-# LOCATE COMP "OUT_H_CS" SITE "U23"; #"DQLR_34" DQLR2_8 #190
-# LOCATE COMP "OUT_H_CSb" SITE "U22"; #"DQLR_35" DQLR2_9 #192
-# LOCATE COMP "DQUL_0" SITE "B2"; #"DQUL_0" DQUL0_0 #74
-# LOCATE COMP "DQUL_1" SITE "B3"; #"DQUL_1" DQUL0_1 #76
-# LOCATE COMP "OUT_L_SDOb" SITE "E4"; #"DQUL_3" DQUL0_3 #80
-# LOCATE COMP "OUT_L_SCKb" SITE "D3"; #"DQUL_5" DQUL0_5 #84
-# LOCATE COMP "IN_L_SDIb" SITE "G6"; #"DQUL_7" DQSUL0_C #88
-# LOCATE COMP "DQUL_8" SITE "E3"; #"DQUL_8" DQUL0_6 #90
-# LOCATE COMP "DQUL_9" SITE "F4"; #"DQUL_9" DQUL0_7 #92
-# LOCATE COMP "OUT_L_CSb" SITE "J6"; #"DQUL_11" DQUL0_9 #96
-# LOCATE COMP "DQUL_12" SITE "G2"; #"DQUL_12" DQUL1_0 #73
-# LOCATE COMP "DQUL_13" SITE "G3"; #"DQUL_13" DQUL1_1 #75
-# LOCATE COMP "DQUL_14" SITE "F2"; #"DQUL_14" DQUL1_2 #77
-# LOCATE COMP "DQUL_15" SITE "F3"; #"DQUL_15" DQUL1_3 #79
-# LOCATE COMP "DQUL_16" SITE "C2"; #"DQUL_16" DQUL1_4 #81
-# LOCATE COMP "DQUL_17" SITE "D2"; #"DQUL_17" DQUL1_5 #83
-# LOCATE COMP "DQUL_18" SITE "K7"; #"DQUL_18" DQSUL1_T #85
-# LOCATE COMP "DQUL_19" SITE "K6"; #"DQUL_19" DQSUL1_C #87
-# LOCATE COMP "DQUL_20" SITE "H5"; #"DQUL_20" DQUL1_6 #89
-# LOCATE COMP "DQUL_21" SITE "J5"; #"DQUL_21" DQUL1_7 #91
-# LOCATE COMP "DQUL_22" SITE "K8"; #"DQUL_22" DQUL1_8 #93
-# LOCATE COMP "DQUL_23" SITE "J7"; #"DQUL_23" DQUL1_9 #95
-# LOCATE COMP "DQUL_32" SITE "E1"; #"DQUL_32" DQUL2_6 #66
-# LOCATE COMP "DQUL_33" SITE "F1"; #"DQUL_33" DQUL2_7 #68
-# LOCATE COMP "DQUL_34" SITE "L5"; #"DQUL_34" DQUL2_8 #70
-# LOCATE COMP "DQUL_35" SITE "L6"; #"DQUL_35" DQUL2_9 #72
-
-LOCATE COMP "OUT_L_SDO" SITE "D4"; #"DQUL_2" DQUL0_2 #78
-LOCATE COMP "OUT_L_SCK" SITE "C3"; #"DQUL_4" DQUL0_4 #82
-LOCATE COMP "IN_L_SDI" SITE "G5"; #"DQUL_6" DQSUL0_T #86
-LOCATE COMP "OUT_L_CS" SITE "H6"; #"DQUL_10" DQUL0_8 #94
-
-
-DEFINE PORT GROUP "IN_group" "IN_*" ;
-IOBUF GROUP "IN_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-
-DEFINE PORT GROUP "OUT_group" "OUT_*" ;
-IOBUF GROUP "OUT_group" IO_TYPE=LVDS25;
+#LOCATE COMP "OUT_L_SDO" SITE "D4"; #"DQUL_2" DQUL0_2 #78
+#LOCATE COMP "OUT_L_SCK" SITE "C3"; #"DQUL_4" DQUL0_4 #82
+#LOCATE COMP "IN_L_SDI" SITE "G5"; #"DQUL_6" DQSUL0_T #86
+#LOCATE COMP "OUT_L_CS" SITE "H6"; #"DQUL_10" DQUL0_8 #94
+
+
+#DEFINE PORT GROUP "IN_group" "IN_*" ;
+#IOBUF GROUP "IN_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+
+#DEFINE PORT GROUP "OUT_group" "OUT_*" ;
+#IOBUF GROUP "OUT_group" IO_TYPE=LVDS25;
#################################################################
# Additional Lines to AddOn
LOCATE COMP "PROGRAMN" SITE "B11";
IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-LOCATE COMP "DAC_SDI" SITE "G6"; #"DQUL_7" DQSUL0_C #88 #IN_L_SDIb
-LOCATE COMP "DAC_SCK" SITE "E4"; #"DQUL_3" DQUL0_3 #80 #OUT_L_SDOb
-LOCATE COMP "DAC_CS_0" SITE "C3"; #"DQUL_4" DQUL0_4 #82 #OUT_L_SCK
-LOCATE COMP "DAC_CS_1" SITE "D3"; #"DQUL_5" DQUL0_5 #84 #OUT_L_SCKb
-LOCATE COMP "DAC_CS_2" SITE "H6"; #"DQUL_10" DQUL0_8 #94 #OUT_L_CS
-LOCATE COMP "DAC_CS_3" SITE "J6"; #"DQUL_11" DQUL0_9 #96 #OUT_L_CSb
+#LOCATE COMP "DAC_SDI" SITE "G6"; #"DQUL_7" DQSUL0_C #88 #IN_L_SDIb
+#LOCATE COMP "DAC_SCK" SITE "E4"; #"DQUL_3" DQUL0_3 #80 #OUT_L_SDOb
+#LOCATE COMP "DAC_CS_0" SITE "C3"; #"DQUL_4" DQUL0_4 #82 #OUT_L_SCK
+#LOCATE COMP "DAC_CS_1" SITE "D3"; #"DQUL_5" DQUL0_5 #84 #OUT_L_SCKb
+#LOCATE COMP "DAC_CS_2" SITE "H6"; #"DQUL_10" DQUL0_8 #94 #OUT_L_CS
+#LOCATE COMP "DAC_CS_3" SITE "J6"; #"DQUL_11" DQUL0_9 #96 #OUT_L_CSb
-DEFINE PORT GROUP "DAC_group" "DAC*" ;
-IOBUF GROUP "DAC_group" IO_TYPE=LVCMOS33 PULLMODE=NONE;
+#DEFINE PORT GROUP "DAC_group" "DAC*" ;
+#IOBUF GROUP "DAC_group" IO_TYPE=LVCMOS33 PULLMODE=NONE;
#################################################################
jspc29 / trb3.git / commitdiff