Calibration looks good.
1 long fiber and 3 short fibers; calibration times: 0x9A, 0x3D, 0x3B, 0x3C.
ToDo:
- reset calibration registers @ start-of-calibration
- more testing
-- Placer Directives
attribute HGROUP : string;
-- for whole architecture
- attribute HGROUP of med_ecp3_sfp_4_sync_down_arch : architecture is "media_downlink_group";
+ attribute HGROUP of med_ecp3_sfp_4_soda_arch : architecture is "media_downlink_group";
attribute syn_sharing : string;
- attribute syn_sharing of med_ecp3_sfp_4_sync_down_arch : architecture is "off";
+ attribute syn_sharing of med_ecp3_sfp_4_soda_arch : architecture is "off";
generated_logic : for i in 0 to 3 generate
- SD_TXDIS_OUT(i) <= LINK_DISABLE_IN; --not (rx_allow_q(i) or not IS_SLAVE); --slave only switches on when RX is ready
+-- SD_TXDIS_OUT(i) <= LINK_DISABLE_IN; --not (rx_allow_q(i) or not IS_SLAVE); --slave only switches on when RX is ready
+ SD_TXDIS_OUT(i) <= '0'; --not rx_allow_q(i); --slave only switches on when RX is ready
tx_pll_lol(i) <= tx_pll_lol_quad;
end if;
end if;
end process;
--- -------------------------------------------------
--- -- TX Data
--- -------------------------------------------------
--- THE_TX : soda_tx_control
--- port map(
--- CLK_200 => clk_200_txdata, --tx_full_clk(i), --clk_200_i(i),
--- CLK_100 => SYSCLK,
--- RESET_IN => rst(i), --CLEAR, PL!
-
--- TX_DATA_IN => MED_DATA_IN(i),
--- TX_PACKET_NUMBER_IN => MED_PACKET_NUM_IN(i),
--- TX_WRITE_IN => MED_DATAREADY_IN(i),
--- TX_READ_OUT => MED_READ_OUT(i),
-
--- TX_DATA_OUT => tx_data(i),
--- TX_K_OUT => tx_k(i),
-
--- REQUEST_RETRANSMIT_IN => request_retr_i(i), --TODO
--- REQUEST_POSITION_IN => request_retr_position_i(i), --TODO
-
--- START_RETRANSMIT_IN => start_retr_i(i), --TODO
--- START_POSITION_IN => request_retr_position_i(i), --TODO
-
--- TX_DLM_PREVIEW_IN => TX_DLM_PREVIEW_IN(i),
--- SEND_DLM => TX_DLM(i),
--- SEND_DLM_WORD => TX_DLM_WORD(i),
-
--- SEND_LINK_RESET_IN => CTRL_OP(i)(15),
--- TX_ALLOW_IN => tx_allow(i),
--- RX_ALLOW_IN => rx_allow(i),
--- LINK_PHASE_OUT => link_phase_S(i), --PL!
-
--- DEBUG_OUT => debug_tx_control_i(i),
--- STAT_REG_OUT => stat_tx_control_i(i)
--- );
-
--- LINK_PHASE_OUT(i) <= link_phase_S(i); --PL!
--- -------------------------------------------------
--- -- RX Data
--- -------------------------------------------------
--- THE_RX_CONTROL : rx_control
--- port map(
--- CLK_200 => clk_200_txdata, --clk_200_i(i), --PL!
--- CLK_100 => SYSCLK,
--- RESET_IN => rst(i), --CLEAR, PL!
+ -------------------------------------------------
+ -- TX Data
+ -------------------------------------------------
+ THE_TX : soda_tx_control
+ port map(
+ CLK_200 => clk_200_txdata, --tx_full_clk(i), --clk_200_i(i),
+ CLK_100 => SYSCLK,
+ RESET_IN => rst(i), --CLEAR, PL!
+
+ TX_DATA_IN => (others => '0'), -- MED_DATA_IN(i),
+ TX_PACKET_NUMBER_IN => (others => '0'), -- MED_PACKET_NUM_IN(i),
+ TX_WRITE_IN => '0', -- MED_DATAREADY_IN(i),
+ TX_READ_OUT => open, -- MED_READ_OUT(i),
+
+ TX_DATA_OUT => tx_data(i),
+ TX_K_OUT => tx_k(i),
+
+ REQUEST_RETRANSMIT_IN => request_retr_i(i), --TODO
+ REQUEST_POSITION_IN => request_retr_position_i(i), --TODO
+
+ START_RETRANSMIT_IN => start_retr_i(i), --TODO
+ START_POSITION_IN => request_retr_position_i(i), --TODO
+
+ TX_DLM_PREVIEW_IN => TX_DLM_PREVIEW_IN(i),
+ SEND_DLM => TX_DLM_IN(i),
+ SEND_DLM_WORD => TX_DLM_WORD_IN(i),
+
+ SEND_LINK_RESET_IN => '0', --CTRL_OP(i)(15),
+ TX_ALLOW_IN => tx_allow(i),
+ RX_ALLOW_IN => rx_allow(i),
+ LINK_PHASE_OUT => link_phase_S(i), --PL!
+
+ DEBUG_OUT => debug_tx_control_i(i),
+ STAT_REG_OUT => stat_tx_control_i(i)
+ );
+
+ LINK_PHASE_OUT(i) <= link_phase_S(i); --PL!
+ -------------------------------------------------
+ -- RX Data
+ -------------------------------------------------
+ THE_RX_CONTROL : rx_control
+ port map(
+ CLK_200 => clk_200_txdata, --clk_200_i(i), --PL!
+ CLK_100 => SYSCLK,
+ RESET_IN => rst(i), --CLEAR, PL!
--- RX_DATA_OUT => MED_DATA_OUT(i),
--- RX_PACKET_NUMBER_OUT => MED_PACKET_NUM_OUT(i),
--- RX_WRITE_OUT => MED_DATAREADY_OUT(i),
--- RX_READ_IN => MED_READ_IN(i),
+ RX_DATA_OUT => open, -- MED_DATA_OUT(i),
+ RX_PACKET_NUMBER_OUT => open, -- MED_PACKET_NUM_OUT(i),
+ RX_WRITE_OUT => open, -- MED_DATAREADY_OUT(i),
+ RX_READ_IN => '0', -- MED_READ_IN(i),
--- RX_DATA_IN => rx_data(i),
--- RX_K_IN => rx_k(i),
+ RX_DATA_IN => rx_data(i),
+ RX_K_IN => rx_k(i),
--- REQUEST_RETRANSMIT_OUT => request_retr_i(i),
--- REQUEST_POSITION_OUT => request_retr_position_i(i),
+ REQUEST_RETRANSMIT_OUT => request_retr_i(i),
+ REQUEST_POSITION_OUT => request_retr_position_i(i),
--- START_RETRANSMIT_OUT => start_retr_i(i),
--- START_POSITION_OUT => start_retr_position_i(i),
+ START_RETRANSMIT_OUT => start_retr_i(i),
+ START_POSITION_OUT => start_retr_position_i(i),
--send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM
--- RX_DLM => RX_DLM(i),
--- RX_DLM_WORD => RX_DLM_WORD(i),
+ RX_DLM => RX_DLM_OUT(i),
+ RX_DLM_WORD => RX_DLM_WORD_OUT(i),
--- SEND_LINK_RESET_OUT => send_link_reset_i(i),
--- MAKE_RESET_OUT => make_link_reset_i(i),
--- RX_ALLOW_IN => rx_allow(i),
--- GOT_LINK_READY => got_link_ready_i(i),
+ SEND_LINK_RESET_OUT => send_link_reset_i(i),
+ MAKE_RESET_OUT => make_link_reset_i(i),
+ RX_ALLOW_IN => rx_allow(i),
+ GOT_LINK_READY => got_link_ready_i(i),
--- DEBUG_OUT => debug_rx_control_i(i),
--- STAT_REG_OUT => stat_rx_control_i(i)
--- );
+ DEBUG_OUT => debug_rx_control_i(i),
+ STAT_REG_OUT => stat_rx_control_i(i)
+ );
internal_make_link_reset_out(i) <= make_link_reset_i(i) when (IS_SYNC_SLAVE=c_YES) else '0';
sd_los_i(i) <= SD_LOS_IN(i) when rising_edge(SYSCLK); -- PL!
-- internal_make_link_reset_out(i) <= make_link_reset_i(i) when (IS_SYNC_SLAVE=c_YES) else '0';
-- sd_los_i(i) <= SD_LOS_IN(i) when rising_edge(SYSCLK); -- PL!
- STAT_OP(i)(15) <= send_link_reset_i(i) when rising_edge(SYSCLK);
- STAT_OP(i)(14) <= '0';
- STAT_OP(i)(13) <= internal_make_link_reset_out(i) when rising_edge(SYSCLK); --make trbnet reset
- STAT_OP(i)(12) <= '0';
- STAT_OP(i)(11) <= '0';
- STAT_OP(i)(10) <= rx_allow(i);
- STAT_OP(i)(9) <= tx_allow(i);
- STAT_OP(i)(8) <= got_link_ready_i(i);
- STAT_OP(i)(7) <= send_link_reset_i(i);
- STAT_OP(i)(6) <= make_link_reset_i(i);
- STAT_OP(i)(5) <= request_retr_i(i);
- STAT_OP(i)(4) <= start_retr_i(i);
- STAT_OP(i)(3 downto 0) <= x"0" when rx_allow_q(i) = '1' and tx_allow_q(i) = '1' else x"7";
+-- STAT_OP(i)(15) <= send_link_reset_i(i) when rising_edge(SYSCLK);
+-- STAT_OP(i)(14) <= '0';
+-- STAT_OP(i)(13) <= internal_make_link_reset_out(i) when rising_edge(SYSCLK); --make trbnet reset
+-- STAT_OP(i)(12) <= '0';
+-- STAT_OP(i)(11) <= '0';
+-- STAT_OP(i)(10) <= rx_allow(i);
+-- STAT_OP(i)(9) <= tx_allow(i);
+-- STAT_OP(i)(8) <= got_link_ready_i(i);
+-- STAT_OP(i)(7) <= send_link_reset_i(i);
+-- STAT_OP(i)(6) <= make_link_reset_i(i);
+-- STAT_OP(i)(5) <= request_retr_i(i);
+-- STAT_OP(i)(4) <= start_retr_i(i);
+-- STAT_OP(i)(3 downto 0) <= x"0" when rx_allow_q(i) = '1' and tx_allow_q(i) = '1' else x"7";
end generate;
end med_ecp3_sfp_4_soda_arch;
CLEAR : in std_logic; -- asynchronous reset
CLK_EN : in std_logic;
- SODA_BURST_PULSE_IN : in std_logic := '0'; --
+ SODA_BURST_PULSE_IN : in std_logic := '0'; --
-- MULTIPLE DUPLEX DOWN-LINKS
- RX_DLM_IN : in t_HUB_BIT;
- RX_DLM_WORD_IN : in t_HUB_BYTE;
- TX_DLM_OUT : out t_HUB_BIT;
- TX_DLM_WORD_OUT : out t_HUB_BYTE;
- TX_DLM_PREVIEW_OUT : out t_HUB_BIT; --PL!
- LINK_PHASE_IN : in t_HUB_BIT; --PL!
+ RX_DLM_IN : in t_HUB_BIT;
+ RX_DLM_WORD_IN : in t_HUB_BYTE;
+ TX_DLM_OUT : out t_HUB_BIT;
+ TX_DLM_WORD_OUT : out t_HUB_BYTE;
+ TX_DLM_PREVIEW_OUT : out t_HUB_BIT; --PL!
+ LINK_PHASE_IN : in t_HUB_BIT; --PL!
SODA_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0');
- SODA_DATA_OUT : out std_logic_vector(31 downto 0) := (others => '0');
+ SODA_DATA_OUT : out std_logic_vector(31 downto 0) := (others => '0');
SODA_ADDR_IN : in std_logic_vector(3 downto 0) := (others => '0');
SODA_READ_IN : in std_logic := '0';
- SODA_WRITE_IN : in std_logic := '0';
+ SODA_WRITE_IN : in std_logic := '0';
SODA_ACK_OUT : out std_logic := '0';
LEDS_OUT : out std_logic_vector(3 downto 0);
- LINK_DEBUG_IN : in std_logic_vector(31 downto 0) := (others => '0')
+ LINK_DEBUG_IN : in std_logic_vector(31 downto 0) := (others => '0')
);
end soda_4source;
architecture Behavioral of soda_4source is
--SODA
- signal soda_cmd_word_S : std_logic_vector(30 downto 0) := (others => '0');
- signal soda_cmd_valid_S : std_logic := '0';
- signal soda_cmd_strobe_S : std_logic := '0'; -- for commands sent in a SODA package
- signal soda_cmd_strobe_sodaclk_S : std_logic := '0'; -- for commands sent in a SODA package
+-- signal soda_cmd_word_S : std_logic_vector(30 downto 0) := (others => '0');
+-- signal soda_cmd_valid_S : std_logic := '0';
+-- signal soda_cmd_strobe_S : std_logic := '0'; -- for commands sent in a SODA package
+-- signal soda_cmd_strobe_sodaclk_S : std_logic := '0'; -- for commands sent in a SODA package
signal trb_cmd_word_S : std_logic_vector(30 downto 0) := (others => '0');
- signal trb_cmd_valid_S : std_logic := '0';
+-- signal trb_cmd_valid_S : std_logic := '0';
signal trb_cmd_strobe_S : std_logic := '0'; -- for commands sent over trbnet
signal trb_cmd_strobe_sodaclk_S : std_logic := '0'; -- for commands sent over trbnet
--- signal soda_cmd_pending_S : std_logic := '0';
--- signal soda_send_cmd_S : std_logic := '0';
+ signal trb_cmd_pending_S : std_logic := '0';
+ signal trb_send_cmd_S : std_logic := '0';
+ signal soda_cmd_window_S : std_logic := '0';
signal start_of_superburst_S : std_logic := '0';
signal super_burst_nr_S : std_logic_vector(30 downto 0) := (others => '0'); -- from super-burst-nr-generator
signal crc_data_S : std_logic_vector(7 downto 0) := (others => '0');
signal expected_reply_S : t_HUB_BYTE_ARRAY; --std_logic_vector(7 downto 0);
signal reply_data_valid_S : t_HUB_BIT_ARRAY;
signal reply_OK_S : t_HUB_BIT_ARRAY;
- signal recv_start_calibration_S : std_logic := '0';
+-- signal recv_start_calibration_S : std_logic := '0';
signal send_start_calibration_S : t_HUB_BIT_ARRAY;
signal start_calibration_S : t_HUB_BIT_ARRAY;
signal calib_data_valid_S : t_HUB_BIT_ARRAY;
begin
- \r
-
+ superburst_gen : soda_superburst_generator
+ generic map(BURST_COUNT => 16)
+ port map(
+ SODACLK => SODACLK,
+ RESET => RESET,
+ --Internal Connection
+ SODA_BURST_PULSE_IN => SODA_BURST_PULSE_IN,
+ START_OF_SUPERBURST_OUT => start_of_superburst_S,
+ SUPER_BURST_NR_OUT => super_burst_nr_S,
+ SODA_CMD_WINDOW_OUT => soda_cmd_window_S
+ );\r
channel :for i in c_HUB_CHILDREN-1 downto 0 generate
- TXsoda_cmd_valid_S(i) <= soda_cmd_valid_S;
- TXstart_of_superburst_S(i) <= start_of_superburst_S;
- TXsoda_cmd_word_S(i) <= '0' & soda_cmd_word_S;
- TXsuper_burst_nr_S(i) <= '0' & super_burst_nr_S;
- \r
- \r
- \r
- start_calibration_S(i) <= send_start_calibration_S(i);
+ TXsoda_cmd_valid_S(i) <= trb_cmd_strobe_S; --trb_cmd_valid_S;
+ TXstart_of_superburst_S(i) <= start_of_superburst_S;
+ TXsoda_cmd_word_S(i) <= '0' & trb_cmd_word_S;
+ TXsuper_burst_nr_S(i) <= '0' & super_burst_nr_S;
+ \r
+
+ start_calibration_S(i) <= send_start_calibration_S(i);
packet_builder : soda_packet_builder
port map(
SODACLK => SODACLK,
RESET => RESET,
--Internal Connection
+ LINK_PHASE_IN => LINK_PHASE_IN(i), --link_phase_S, PL!
SODA_CMD_STROBE_IN => TXsoda_cmd_valid_S(i),
START_OF_SUPERBURST => TXstart_of_superburst_S(i),
SUPER_BURST_NR_IN => TXsuper_burst_nr_S(i)(30 downto 0),
last_packet_sent_S <= c_NO_PACKET;
elsif (start_of_superburst_S='1') then
last_packet_sent_S <= c_BST_PACKET;
- elsif (soda_cmd_valid_S='1') then
+ elsif (trb_cmd_strobe_S='1') then
last_packet_sent_S <= c_CMD_PACKET;
end if;
end if;
NEXT_STATE <= SLEEP;
end case;
end process TRANSFORM;
+\r
-
+soda_cmd_strobe_posedge_to_pulse: posedge_to_pulse
+ port map(
+ IN_CLK => SYSCLK,
+ OUT_CLK => SODACLK,
+ CLK_EN => '1',
+ SIGNAL_IN => trb_cmd_strobe_S,
+ PULSE_OUT => trb_cmd_strobe_sodaclk_S
+ );
+\r
+SODA_CMD_FLOWCTRL : process(SODACLK)
+ begin
+ if( rising_edge(SODACLK) ) then
+ if( RESET = '1' ) then
+ trb_cmd_pending_S <= '0';
+ trb_send_cmd_S <= '0';
+ elsif trb_cmd_strobe_sodaclk_S = '1' then
+ trb_cmd_pending_S <= '1';
+ elsif soda_cmd_window_S = '1' and trb_cmd_pending_S = '1' then
+ trb_send_cmd_S <= '1';
+ trb_cmd_pending_S <= '0';
+ else
+ trb_cmd_pending_S <= '0';
+ trb_send_cmd_S <= '0';
+ end if;
+ end if;
+ end process SODA_CMD_FLOWCTRL;\r
+
---------------------------------------------------------
-- data handling --
---------------------------------------------------------
dead_channel_S(0) <= CTRL_STATUS_register_S(0)(8); -- slow-control can declare a channel dead
dead_channel_S(1) <= CTRL_STATUS_register_S(1)(8); -- slow-control can declare a channel dead
- dead_channel_S(2) <= CTRL_STATUS_register_S(2)(8); -- slow-control can declare a channel dead
- dead_channel_S(3) <= CTRL_STATUS_register_S(3)(8); -- slow-control can declare a channel dead
+ dead_channel_S(2) <= CTRL_STATUS_register_S(2)(8); -- slow-control can declare a channel dead
+ dead_channel_S(3) <= CTRL_STATUS_register_S(3)(8); -- slow-control can declare a channel dead
-- register read
THE_READ_REG_PROC: process( SYSCLK )
if ( RESET = '1' ) then
buf_bus_data_out <= (others => '0');
elsif( (store_rd = '1') and (SODA_ADDR_IN = "0000") ) then
- buf_bus_data_out <= '0' & soda_cmd_word_S;
+ buf_bus_data_out <= '0' & trb_cmd_word_S;
elsif( (store_rd = '1') and (SODA_ADDR_IN = "0001") ) then
buf_bus_data_out <= '0' & super_burst_nr_S;
elsif( (store_rd = '1') and (SODA_ADDR_IN = "0100") ) then
buf_bus_data_out <= calib_register_S(0);
elsif( (store_rd = '1') and (SODA_ADDR_IN = "0101") ) then
- buf_bus_data_out <= calib_register_S(0);
+ buf_bus_data_out <= calib_register_S(1);
elsif( (store_rd = '1') and (SODA_ADDR_IN = "0110") ) then
- buf_bus_data_out <= calib_register_S(0);
+ buf_bus_data_out <= calib_register_S(2);
elsif( (store_rd = '1') and (SODA_ADDR_IN = "0111") ) then
- buf_bus_data_out <= calib_register_S(0);
- elsif( (store_rd = '1') and (SODA_ADDR_IN = "0011") ) then
+ buf_bus_data_out <= calib_register_S(3);
+ elsif( (store_rd = '1') and (SODA_ADDR_IN = "1000") ) then
buf_bus_data_out <= CTRL_STATUS_register_S(0);
- elsif( (store_rd = '1') and (SODA_ADDR_IN = "0100") ) then
+ elsif( (store_rd = '1') and (SODA_ADDR_IN = "1001") ) then
buf_bus_data_out <= CTRL_STATUS_register_S(1);
- elsif( (store_rd = '1') and (SODA_ADDR_IN = "0101") ) then
+ elsif( (store_rd = '1') and (SODA_ADDR_IN = "1010") ) then
buf_bus_data_out <= CTRL_STATUS_register_S(2);
- elsif( (store_rd = '1') and (SODA_ADDR_IN = "0110") ) then
+ elsif( (store_rd = '1') and (SODA_ADDR_IN = "1011") ) then
buf_bus_data_out <= CTRL_STATUS_register_S(3);
end if;
end if;
SODACLK => SODACLK,
RESET => RESET,
--Internal Connection
+ LINK_PHASE_IN => LINK_PHASE_IN, --link_phase_S, PL! 17092014 vergeten ??? of niet nodig ?
SODA_CMD_STROBE_IN => TXsoda_cmd_valid_S(i),
START_OF_SUPERBURST => TXstart_of_superburst_S(i),
SUPER_BURST_NR_IN => TXsuper_burst_nr_S(i)(30 downto 0),
SODA_DATA_OUT <= buf_bus_data_out;
SODA_ACK_OUT <= bus_ack;
-end architecture;
\ No newline at end of file
+end architecture;
RESET_DELAY => x"FEEE"
)
port map(
- CLEAR_IN => '0', -- reset input (high active, async)
- CLEAR_N_IN => '1', -- reset input (low active, async)
- CLK_IN => clk_200_osc, -- raw master clock, NOT from PLL/DLL!
- SYSCLK_IN => clk_100_osc, -- PLL/DLL remastered clock
- PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
- RESET_IN => '0', -- general reset signal (SYSCLK)
- TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK)
- CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!
- RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
+ CLEAR_IN => '0', -- reset input (high active, async)
+ CLEAR_N_IN => '1', -- reset input (low active, async)
+ CLK_IN => clk_200_osc, -- raw master clock, NOT from PLL/DLL!
+ SYSCLK_IN => clk_100_osc, -- PLL/DLL remastered clock
+ PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
+ RESET_IN => '0', -- general reset signal (SYSCLK)
+ TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK)
+ CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!
+ RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
DEBUG_OUT => open
);
---------------------------------------------------------------------------
-- Clock Handling
---------------------------------------------------------------------------
-gen_200_PLL : if USE_125_MHZ = c_NO generate
+--gen_200_PLL : if USE_125_MHZ = c_NO generate
THE_MAIN_PLL : pll_in200_out100
port map(
CLK => CLK_GPLL_RIGHT,
CLKOK => clk_200_osc,
LOCK => pll_lock
);
-end generate;
+--end generate;
-gen_125 : if USE_125_MHZ = c_YES generate
- clk_100_osc <= CLK_GPLL_LEFT;
- clk_200_osc <= CLK_GPLL_LEFT;
-end generate;
+--gen_125 : if USE_125_MHZ = c_YES generate
+-- clk_100_osc <= CLK_GPLL_LEFT;
+-- clk_200_osc <= CLK_GPLL_LEFT;
+--end generate;
---------------------------------------------------------------------------
BROADCAST_SPECIAL_ADDR => x"45",
REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
REGIO_HARDWARE_VERSION => x"9100b000",
- REGIO_INIT_ADDRESS => x"f356",
+ REGIO_INIT_ADDRESS => x"f358",
REGIO_USE_VAR_ENDPOINT_ID => c_YES,
CLOCK_FREQUENCY => CLOCK_FREQUENCY,
TIMING_TRIGGER_RAW => c_YES,
THE_BUS_HANDLER : trb_net16_regio_bus_handler
generic map(
PORT_NUMBER => 4,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"be00", others => x"0000"),
- PORT_ADDR_MASK => (0 => 9, 1 => 9, 2 => 4, others => 0)
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"b800", 3 => x"be00", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 9, 1 => 9, 2 => 9, 3 => 4, others => 0)
)
port map(
CLK => clk_100_osc,
BUS_DATA_OUT(1*32+31 downto 1*32+8) => open,
BUS_DATA_OUT(2*32+7 downto 2*32) => sci2_data_in,
BUS_DATA_OUT(2*32+31 downto 2*32+8) => open,
- BUS_DATA_OUT(2*32+31 downto 2*32) => soda_data_in,
+ BUS_DATA_OUT(3*32+31 downto 3*32) => soda_data_in,
BUS_ADDR_OUT(0*16+8 downto 0*16) => spimem_addr,
BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
BUS_TIMEOUT_OUT(0) => open,
BUS_TIMEOUT_OUT(1) => open,
BUS_TIMEOUT_OUT(2) => open,
+ BUS_TIMEOUT_OUT(3) => open,
BUS_DATA_IN(0*32+31 downto 0*32) => spimem_data_out,
BUS_DATA_IN(1*32+7 downto 1*32) => sci1_data_out,
);
-
- SFP_TXDIS(1) <= sfp_txdis_S(1);
+\r
+ SFP_TXDIS <= sfp_txdis_S;
+-- SFP_TXDIS(1) <= sfp_txdis_S(1);
---------------------------------------------------------------------------
-- The Soda Central
<BaliProject version="3.0" title="soda_4source_EP" device="LFE3-150EA-8FN672C" default_implementation="soda_4source_EP">
<Options/>
<Implementation title="soda_4source_EP" dir="soda_4source_EP" description="soda_4source_EP" synthesis="synplify" default_strategy="Strategy1">
- <Options def_top="soda_clockscaler"/>
+ <Options def_top="trb3_periph_EP_soda4source" top="trb3_periph_EP_soda4source"/>
<Source name="code/version.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="code/soda_components.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="code/soda_source.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="soda_source"/>
- </Source>
<Source name="code/soda_d8crc8.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="code/soda_packet_handler.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="soda_packet_handler"/>
+ <Options/>
</Source>
<Source name="code/soda_superburst_gen.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="code/soda_SOB_faker.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="soda_start_of_burst_faker"/>
+ <Options/>
</Source>
<Source name="code/soda_calibration_timer.vhd" type="VHDL" type_short="VHDL">
<Options/>
<Source name="code/soda_reply_handler.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
+ <Source name="code/med_ecp3_sfp_4_SODA.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="code/soda_4source.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="code/soda_clockscaler.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
<Source name="code/soda_tx_control.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="soda_tx_control"/>
+ <Options/>
</Source>
<Source name="code/posedge_to_pulse.vhd" type="VHDL" type_short="VHDL">
<Options/>
<Options/>
</Source>
<Source name="code/ip/serdes_4_sync_downstream.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="serdes_4_sync_downstream"/>
+ <Options/>
</Source>
<Source name="code/ip/serdes_4_sync_downstream.lpc" type="LPC_Module" type_short="LPC">
<Options/>
<Source name="code/ip/serdes_4_sync_downstream.ipx" type="IPX_Module" type_short="IPX">
<Options/>
</Source>
+ <Source name="../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
<Source name="../trb3/base/cores/pll_in200_out100.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="pll_in200_out100"/>
+ <Options/>
</Source>
<Source name="../trb3/base/trb3_components.vhd" type="VHDL" type_short="VHDL">
<Options/>
<Options/>
</Source>
<Source name="../trbnet/special/trb_net_reset_handler.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="trb_net_reset_handler"/>
+ <Options/>
</Source>
<Source name="../trbnet/special/fpga_reboot.vhd" type="VHDL" type_short="VHDL">
<Options/>
<Options/>
</Source>
<Source name="../trbnet/special/spi_ltc2600.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="spi_ltc2600"/>
+ <Options/>
</Source>
<Source name="../trbnet/basics/rom_16x8.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../trbnet/basics/ram.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="ram"/>
+ <Options/>
</Source>
<Source name="../trbnet/basics/pulse_sync.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../trbnet/basics/state_sync.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="state_sync"/>
+ <Options/>
</Source>
<Source name="../trbnet/basics/ram_16x8_dp.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="ram_16x8_dp"/>
+ <Options/>
</Source>
<Source name="../trbnet/basics/ram_16x16_dp.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../trbnet/basics/ram_dp.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="ram_dp"/>
+ <Options/>
</Source>
<Source name="../trbnet/basics/signal_sync.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../trbnet/basics/ram_dp_rw.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="ram_dp_rw"/>
+ <Options/>
</Source>
<Source name="../trbnet/basics/pulse_stretch.vhd" type="VHDL" type_short="VHDL">
<Options/>
<Options/>
</Source>
<Source name="../trbnet/trb_net16_endpoint_hades_full_handler.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="trb_net16_endpoint_hades_full_handler"/>
+ <Options/>
</Source>
<Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" type="VHDL" type_short="VHDL">
<Options/>
<Options/>
</Source>
<Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="lattice_ecp3_fifo_16x16_dualport"/>
+ <Options/>
</Source>
<Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="lattice_ecp3_fifo_18x16_dualport"/>
+ <Options/>
</Source>
<Source name="../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="tx_reset_sm_125"/>
+ <Options/>
</Source>
<Source name="../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" type="VHDL" type_short="VHDL">
<Options/>
<Options/>
</Source>
<Source name="../trbnet/media_interfaces/sync/rx_control.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="rx_control"/>
+ <Options/>
</Source>
<Source name="../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="rx_reset_fsm"/>
+ <Options/>
</Source>
<Source name="../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="tx_reset_fsm"/>
+ <Options/>
</Source>
<Source name="../trbnet/trb_net16_hub_base.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="trb_net16_hub_base"/>
+ <Options/>
</Source>
<Source name="../trbnet/trb_net16_hub_func.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="trb_net16_med_ecp3_sfp"/>
- </Source>
<Source name="../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Options/>
</Source>
<Source name="../trbnet/special/spi_flash_and_fpga_reload.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="spi_flash_and_fpga_reload"/>
- </Source>
- <Source name="code/trb3_periph_EP_soda4source.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="code/soda_clockscaler.vhd" type="VHDL" type_short="VHDL">
- <Options top_module="soda_clockscaler"/>
+ <Source name="code/trb3_periph_EP_soda4source.vhd" type="VHDL" type_short="VHDL">
+ <Options top_module="trb3_periph_EP_soda4source"/>
</Source>
- <Source name="code/soda_source_synconstraints.fdc" type="Synplify Design Constraints File" type_short="SDC">
+ <Source name="code/soda_4source_synconstraints.fdc" type="Synplify Design Constraints File" type_short="SDC">
<Options/>
</Source>
<Source name="soda_4source_EP.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
- <Source name="soda_source_probe.rvl" type="Reveal" type_short="Reveal">
+ <Source name="soda_4source_EP.rvl" type="Reveal" type_short="Reveal">
<Options/>
</Source>
<Source name="trb3_soda_source.xcf" type="Programming Project File" type_short="Programming">
-rvl_alias "clk_raw_internal" "clk_raw_internal";
-RVL_ALIAS "clk_raw_internal" "clk_raw_internal";
+rvl_alias "clk_200_osc" "clk_200_osc";
RVL_ALIAS "clk_raw_internal" "clk_raw_internal";
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
#################################################################
# Locate Serdes and media interfaces
#################################################################
-LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200.THE_SERDES/PCSD_INST" SITE "PCSA" ;
-#LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ;
-#LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_200/PCSD_INST" SITE "PCSA" ;
-LOCATE COMP "THE_SYNC_LINK/THE_SERDES/PCSD_INST" SITE "PCSB" ;
-#REGION "MEDIA_UPLINK_REGION" "R90C95D" 20 25 DEVSIZE;
-#REGION "MEDIA_DOWNLINK_REGION" "R90C45D" 25 35 DEVSIZE;
-#REGION "IOBUF_REGION" "R10C43D" 88 86 DEVSIZE;
-#REGION "SPI_REGION" "R10C150D" 15 16 DEVSIZE;
-#LOCATE UGROUP "THE_SPI_RELOAD/THE_SPI_MASTER/SPI_group" REGION "SPI_REGION" ;
-#LOCATE UGROUP "THE_SPI_RELOAD/THE_SPI_MEMORY/SPI_group" REGION "SPI_REGION" ;
-#LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK_REGION" ;
-#LOCATE UGROUP "THE_SYNC_LINK/media_downlink_group" REGION "MEDIA_DOWNLINK_REGION" ;
-#USE SECONDARY NET "THE_MEDIA_UPLINK/rx_clock_half_c" "MEDIA_DOWNLINK_REGION" ;
+#LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200.THE_SERDES/PCSD_INST" SITE "PCSA" ;
+LOCATE COMP "MED_ECP3_SODA_QUAD_SOURCE/THE_SERDES/PCSD_INST" SITE "PCSB" ;
+\r
MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ;
-MULTICYCLE TO CELL "THE_SYNC_LINK/SCI_DATA_OUT*" 20.000000 ns ;
-MULTICYCLE TO CELL "THE_SYNC_LINK/sci*" 20.000000 ns ;
-MULTICYCLE FROM CELL "THE_SYNC_LINK/sci*" 25.000000 ns ;
-MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50.000000 ns ;
+MULTICYCLE TO CELL "MED_ECP3_SODA_QUAD_SOURCE/SCI_DATA_OUT*" 20.000000 ns ;
+MULTICYCLE TO CELL "MED_ECP3_SODA_QUAD_SOURCE/sci*" 20.000000 ns ;
+MULTICYCLE FROM CELL "MED_ECP3_SODA_QUAD_SOURCE/sci*" 25.000000 ns ;
+MULTICYCLE TO CELL "MED_ECP3_SODA_QUAD_SOURCE/SCI_DATA_OUT*" 50.000000 ns ;
+MULTICYCLE FROM CELL "MED_ECP3_SODA_QUAD_SOURCE/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;
+\r
BLOCK JTAGPATHS ;
+\r
## IOBUF ALLPORTS ;
-#USE PRIMARY PURE NET "CLK_PCLK_LEFT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ;
-#USE PRIMARY PURE NET "CLK_GPLL_RIGHT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ;
-#FREQUENCY NET "THE_SYNC_LINK/THE_SERDES.rx_full_clk_ch0" 200.000000 MHz ;
-#FREQUENCY NET "THE_SYNC_LINK/THE_SERDES.rx_half_clk_ch0" 100.000000 MHz ;
-#FREQUENCY NET "THE_SYNC_LINK/THE_SERDES.tx_full_clk_ch0" 200.000000 MHz ;
-#FREQUENCY NET "THE_SYNC_LINK/THE_SERDES.tx_half_clk_ch0" 100.000000 MHz ;
-#USE PRIMARY PURE NET "THE_SYNC_LINK/THE_SERDES.tx_full_clk_ch0" ;
-#USE PRIMARY PURE NET "THE_SYNC_LINK/THE_SERDES.tx_half_clk_ch0" ;
-#USE PRIMARY PURE NET "THE_SYNC_LINK/THE_SERDES.rx_full_clk_ch0" ;
-#USE PRIMARY PURE NET "THE_SYNC_LINK/THE_SERDES.rx_half_clk_ch0" ;
-USE PRIMARY NET "THE_SYNC_LINK/CLK_RX_FULL_OUT_c" ;
-USE PRIMARY NET "clk_sys_internal_c" ;
-MULTICYCLE FROM CELL "THE_SYNC_LINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;
+USE PRIMARY NET "clk_200_osc" ;
+USE PRIMARY NET "clk_100_osc" ;
+FREQUENCY NET "clk_200_osc" 200.000000 MHz ;
+FREQUENCY NET "clk_100_osc" 100.000000 MHz ;
+\r
-<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_client_probe.rvl" Date="2014-08-07">
- <IP Version="1_5_062609"/>
- <Design DesignEntry="Schematic/VHDL" Synthesis="synplify" DeviceFamily="LatticeECP3" DesignName="soda_client"/>
- <Core InsertDataset="0" Insert="1" Reveal_sig="2047784146" Name="trb3_periph_sodaclient_LA0" ID="0">
- <Setting>
- <Clock SampleClk="rx_full_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
- <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="128"/>
- <Capture Mode="0" MinSamplesPerTrig="8"/>
- <Event CntEnable="0" MaxEventCnt="8"/>
- <TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_soda_client_LA0_net"/>
- </Setting>
- <Dataset Name="Base">
- <Trace>
- <Bus Name="the_sync_link/rx_data">
- <Sig Type="SIG" Name="the_sync_link/rx_data:0"/>
- <Sig Type="SIG" Name="the_sync_link/rx_data:1"/>
- <Sig Type="SIG" Name="the_sync_link/rx_data:2"/>
- <Sig Type="SIG" Name="the_sync_link/rx_data:3"/>
- <Sig Type="SIG" Name="the_sync_link/rx_data:4"/>
- <Sig Type="SIG" Name="the_sync_link/rx_data:5"/>
- <Sig Type="SIG" Name="the_sync_link/rx_data:6"/>
- <Sig Type="SIG" Name="the_sync_link/rx_data:7"/>
- </Bus>
- <Sig Type="SIG" Name="the_sync_link/rx_k"/>
- <Sig Type="SIG" Name="the_sync_link/rx_dlm"/>
- <Bus Name="the_sync_link/rx_dlm_word">
- <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:0"/>
- <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:1"/>
- <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:2"/>
- <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:3"/>
- <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:4"/>
- <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:5"/>
- <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:6"/>
- <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:7"/>
- </Bus>
- <Sig Type="SIG" Name="the_sync_link/rx_los_low"/>
- <Sig Type="SIG" Name="the_sync_link/rx_pcs_rst"/>
- <Sig Type="SIG" Name="the_sync_link/rx_serdes_rst"/>
- <Sig Type="SIG" Name="the_sync_link/tx_allow_q"/>
- <Sig Type="SIG" Name="the_sync_link/tx_k"/>
- <Bus Name="the_sync_link/tx_data">
- <Sig Type="SIG" Name="the_sync_link/tx_data:0"/>
- <Sig Type="SIG" Name="the_sync_link/tx_data:1"/>
- <Sig Type="SIG" Name="the_sync_link/tx_data:2"/>
- <Sig Type="SIG" Name="the_sync_link/tx_data:3"/>
- <Sig Type="SIG" Name="the_sync_link/tx_data:4"/>
- <Sig Type="SIG" Name="the_sync_link/tx_data:5"/>
- <Sig Type="SIG" Name="the_sync_link/tx_data:6"/>
- <Sig Type="SIG" Name="the_sync_link/tx_data:7"/>
- </Bus>
- <Sig Type="SIG" Name="the_sync_link/tx_dlm"/>
- <Sig Type="SIG" Name="the_sync_link/tx_dlm_preview_in"/>
- <Bus Name="the_sync_link/tx_dlm_word">
- <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:0"/>
- <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:1"/>
- <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:2"/>
- <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:3"/>
- <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:4"/>
- <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:5"/>
- <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:6"/>
- <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:7"/>
- </Bus>
- <Sig Type="SIG" Name="the_sync_link/watchdog_trigger"/>
- </Trace>
- <Trigger>
- <TU Serialbits="0" Type="0" ID="1" Sig="a_soda_client/start_of_superburst_s,"/>
- <TU Serialbits="0" Type="0" ID="2" Sig="a_soda_client/soda_cmd_valid_s,"/>
- <TU Serialbits="0" Type="0" ID="3" Sig="the_sync_link/watchdog_trigger,"/>
- <TE MaxSequence="1" MaxEvnCnt="1" ID="1" Resource="1"/>
- <TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
- <TE MaxSequence="2" MaxEvnCnt="1" ID="3" Resource="0"/>
- </Trigger>
- </Dataset>
- </Core>
-</Project>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20140624.bit</File>
- <FileTime>06/24/14 17:16:05</FileTime>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20140915.bit</File>
+ <FileTime>09/15/14 16:30:11</FileTime>
<Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20140624.bit</File>
- <FileTime>06/24/14 17:16:05</FileTime>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20140915.bit</File>
+ <FileTime>09/15/14 16:30:11</FileTime>
+ <JedecChecksum>N/A</JedecChecksum>
<Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
jspc29 / soda.git / commitdiff