*** empty log message ***

diff --git a/media_interfaces/trb_net16_tx_control.vhd b/media_interfaces/trb_net16_tx_control.vhd
index 5c577dd928f037b6ee0405e93c79c8f9cafada47..5b680203392e6d99cc32bb42dc2a0c0e15ae6d24 100644 (file)
--- a/media_interfaces/trb_net16_tx_control.vhd
+++ b/media_interfaces/trb_net16_tx_control.vhd
@@ -39,25 +39,38 @@ end entity;
 
 architecture arch of trb_net16_tx_control is
 
-  component lattice_ecp2m_fifo_16x16_dualport
+-- gk 05.10.10
+  component lattice_ecp2m_fifo_18x16_dualport
     port (
-      Data: in  std_logic_vector(15 downto 0);
+      Data: in  std_logic_vector(17 downto 0);
       WrClock: in  std_logic;
       RdClock: in  std_logic;
       WrEn: in  std_logic;
       RdEn: in  std_logic;
       Reset: in  std_logic;
       RPReset: in  std_logic;
-      Q: out  std_logic_vector(15 downto 0);
+      Q: out  std_logic_vector(17 downto 0);
       Empty: out  std_logic;
       Full: out  std_logic;
       AlmostFull: out std_logic
       );
   end component;
 
+-- gk 05.10.10
+component trb_net_CRC8 is
+  port(
+    CLK       : in  std_logic;
+    RESET     : in  std_logic;
+    CLK_EN    : in  std_logic;
+    DATA_IN   : in  std_logic_vector(7 downto 0);
+    CRC_OUT   : out std_logic_vector(7 downto 0);
+    CRC_match : out std_logic
+    );
+end component;
+
   type state_t is (SLEEP, SEND_IDLE_L, SEND_IDLE_H, SEND_DATA_L, SEND_DATA_H,
                    SEND_START_L, SEND_START_H, SEND_REQUEST_L, SEND_REQUEST_H,
-                   SEND_RESET);
+                   SEND_RESET, SEND_CHKSUM_L, SEND_CHKSUM_H);  -- gk 05.10.10
   signal current_state           : state_t;
 
   type ram_t is array(0 to 255) of std_logic_vector(17 downto 0);
@@ -95,24 +108,39 @@ architecture arch of trb_net16_tx_control is
   signal ct_fifo_afull           : std_logic;
   signal ct_fifo_reset           : std_logic;
 
+  -- gk 05.10.10
+  signal save_sop                : std_logic;
+  signal save_eop                : std_logic;
+  signal load_sop                : std_logic;
+  signal load_eop                : std_logic;
+  signal crc_reset               : std_logic;
+  signal crc_q                   : std_logic_vector(7 downto 0);
+  signal crc_en                  : std_logic;
+  signal crc_data                : std_logic_vector(7 downto 0);
+
 begin
 
 ----------------------------------------------------------------------
 -- Clock Domain Transfer
 ----------------------------------------------------------------------
-  THE_CT_FIFO : lattice_ecp2m_fifo_16x16_dualport
+-- gk 05.10.10
+  THE_CT_FIFO : lattice_ecp2m_fifo_18x16_dualport
     port map(
-      Data     => TX_DATA_IN,
-      WrClock  => SYSCLK_IN,
-      RdClock  => TXCLK_IN,
-      WrEn     => ct_fifo_write,
-      RdEn     => ct_fifo_read,
-      Reset    => ct_fifo_reset,
-      RPReset  => ct_fifo_reset,
-      Q        => tx_data_25_i,
-      Empty    => ct_fifo_empty,
-      Full     => ct_fifo_full,
-      AlmostFull => ct_fifo_afull
+      Data(15 downto 0) => TX_DATA_IN,
+      Data(16)          => save_sop,
+      Data(17)          => save_eop,
+      WrClock           => SYSCLK_IN,
+      RdClock           => TXCLK_IN,
+      WrEn              => ct_fifo_write,
+      RdEn              => ct_fifo_read,
+      Reset             => ct_fifo_reset,
+      RPReset           => ct_fifo_reset,
+      Q(15 downto 0)    => tx_data_25_i,
+      Q(16)             => load_sop,
+      Q(17)             => load_eop,
+      Empty             => ct_fifo_empty,
+      Full              => ct_fifo_full,
+      AlmostFull        => ct_fifo_afull
       );
 
   THE_RD_PROC : process(SYSCLK_IN)
@@ -128,6 +156,10 @@ TX_READ_OUT  <= buf_tx_read_out;
 ct_fifo_write<= buf_tx_read_out and TX_WRITE_IN;
 ct_fifo_read <= tx_allow_qtx and not ram_afull and not ct_fifo_empty;
 
+-- gk 05.10.10
+save_sop <= '1' when (TX_PACKET_NUMBER_IN = b"100") else '0';
+save_eop <= '1' when (TX_PACKET_NUMBER_IN = b"011") else '0';
+
 ----------------------------------------------------------------------
 -- RAM
 ----------------------------------------------------------------------
@@ -231,6 +263,18 @@ ct_fifo_read <= tx_allow_qtx and not ram_afull and not ct_fifo_empty;
             TX_K_OUT           <= '0';
             --current_state    <= see below
 
+       -- gk 05.10.10
+          when SEND_CHKSUM_L =>
+            TX_DATA_OUT        <= x"FD";
+            TX_K_OUT           <= '1';
+            current_state      <= SEND_CHKSUM_H;
+
+       -- gk 05.10.10
+          when SEND_CHKSUM_H =>
+            TX_DATA_OUT        <= crc_q;
+            TX_K_OUT           <= '1';
+            current_state      <= SEND_IDLE_L;
+
           when SEND_IDLE_L =>
             TX_DATA_OUT        <= x"BC";
             TX_K_OUT           <= '1';
@@ -285,6 +329,8 @@ ct_fifo_read <= tx_allow_qtx and not ram_afull and not ct_fifo_empty;
             current_state    <= SEND_REQUEST_L;
           elsif make_restart_i = '1' then
             current_state    <= SEND_START_L;
+          elsif (load_eop = '1') then
+            current_state    <= SEND_CHKSUM_L;
           elsif ram_empty = '0' then
             ram_read         <= '1';
             current_state    <= SEND_DATA_L;
@@ -409,6 +455,22 @@ ct_fifo_read <= tx_allow_qtx and not ram_afull and not ct_fifo_empty;
 
   load_read_pointer_i    <= '1' when current_state = SEND_START_L else '0';
 
+  -- gk 05.10.10
+  crc_reset <= '1' when ((RESET_IN = '1') or (current_state = SEND_IDLE_L)) else '0';
+  crc_en    <= '1' when ((current_state = SEND_DATA_L) or (current_state = SEND_DATA_H)) else '0';
+  crc_data  <= ram_dout(15 downto 8) when (current_state = SEND_IDLE_H) else ram_dout(7 downto 0);
+
+  -- gk 05.10.10
+  CRC_CALC : trb_net_CRC8
+  port map(
+       CLK       => TXCLK_IN,
+       RESET     => crc_reset,
+       CLK_EN    => crc_en,
+       DATA_IN   => crc_data,
+       CRC_OUT   => crc_q,
+       CRC_match => open
+  );
+
 
 ----------------------------------------------------------------------
 -- Debug