Project_File_2 = /d/jspc22/trb/git/trb3/ADC/sim/tb_adcprocessor.vhd
Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1409926749 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_3 = /d/jspc22/trb/git/trbnet/trb_net_std.vhd
-Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1408718845 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1408718845 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 6 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_4 = /d/jspc22/trb/git/trb3/ADC/sim/txt_util.vhd
Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1409066711 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_5 = /d/jspc22/trb/git/trb3/ADC/config.vhd
type state_t is (IDLE, RELEASE_DIRECT, WAIT_FOR_END, CHECK_STATUS_TRIGGER, START, SEND_STATUS, READOUT, NEXT_BLOCK);
signal state : state_t;
+signal statebits : std_logic_vector(7 downto 0);
+signal word_counter : unsigned(7 downto 0);
-- 800 - 83f last ADC values (local 0x0 - 0x3)
-- 840 - 87f long-term average / baseline (local 0x4 - 0x7)
std_logic_vector(resize(ram_rd_pointer(0),16));
when x"5" => DEBUG_BUFFER_DATA <= std_logic_vector(resize(ram_rd_pointer(3),16)) &
std_logic_vector(resize(ram_rd_pointer(2),16));
+ when x"6" => DEBUG_BUFFER_DATA(7 downto 0) <= statebits;
when others => null;
end case;
end if;
if READOUT_RX.valid_timing_trg = '1' then
after_trg_cnt(10 downto 0) <= CONF.samples_after;
after_trg_cnt(11) <= '0';
+ elsif state = IDLE then
+ stop_writing_rdo <= '0';
+ after_trg_cnt <= (others => '1');
+ elsif or_all(std_logic_vector(after_trg_cnt)) = '0' then
+ stop_writing_rdo <= '1';
+ after_trg_cnt <= (others => '1');
elsif after_trg_cnt(11) = '0' then
after_trg_cnt <= after_trg_cnt - 1;
end if;
- if or_all(std_logic_vector(after_trg_cnt)) = '0' then
- stop_writing_rdo <= '1';
- after_trg_cnt <= (others => '1');
- end if;
-
- if finished_readout = '1' then
- stop_writing_rdo <= '0';
- end if;
-
stop_writing <= stop_writing_rdo or STOP_IN;
-
- if readout_reset = '1' then
- stop_writing_rdo <= '0';
- after_trg_cnt <= (others => '1');
- end if;
-
+
end process;
reg_ram_data_out(i) <= ram_data_out(i);
if ram_reset = '1' then
- ram_rd_pointer(i) <= (others => '1'); --one behind write pointer
+ ram_rd_pointer(i) <= (others => '1'); --one behind write pointer
elsif ram_clear(i) = '1' then
- ram_rd_pointer(i) <= ram_wr_pointer;
+ ram_rd_pointer(i) <= ram_wr_pointer;
elsif ram_read(i) = '1' then
ram_rd_pointer(i) <= ram_rd_pointer(i) + 1;
elsif ram_debug_read(i) = '1' then
ram_rd_pointer(i) <= ram_rd_pointer(i) + 1;
elsif ram_remove = '1' then
- ram_rd_pointer(i) <= ram_rd_pointer(i) + 1;
+ ram_rd_pointer(i) <= ram_rd_pointer(i) + 1;
end if;
end process;
else
trigger_gen(i) <= '0';
end if;
- elsif stop_writing = '1' then
- trigger_gen(i) <= '0';
+-- elsif stop_writing = '1' then
+-- trigger_gen(i) <= '0';
end if;
end process;
end generate;
if READOUT_RX.data_valid = '1' then
if READOUT_RX.trg_type = x"E" then
state <= SEND_STATUS;
+ word_counter <= (others => '0');
else
state <= RELEASE_DIRECT;
end if;
end if;
when SEND_STATUS =>
- state <= RELEASE_DIRECT;
- READOUT_TX.data <= x"DECAFBAD";
- READOUT_TX.data_write <= '1';
+ READOUT_TX.data_write <= '1';
+ READOUT_TX.data <= x"2" & std_logic_vector(word_counter) & x"00000";
+ word_counter <= word_counter + 1;
+ case word_counter is
+ when x"00" =>
+ if DEVICE = 0 then
+ READOUT_TX.data(31 downto 0) <= x"40" & std_logic_vector(to_unsigned(DEVICE,4)) & x"F00" & x"0d" ;
+ else
+ READOUT_TX.data(31 downto 0) <= x"40" & std_logic_vector(to_unsigned(DEVICE,4)) & x"F00" & x"04" ;
+ word_counter <= x"10";
+ end if;
+ when x"01" =>
+ READOUT_TX.data(10 downto 0) <= std_logic_vector(CONF.buffer_depth);
+ when x"02" =>
+ READOUT_TX.data(10 downto 0) <= std_logic_vector(CONF.samples_after);
+ when x"03" =>
+ READOUT_TX.data(17 downto 0) <= std_logic_vector(CONF.trigger_threshold);
+ when x"04" =>
+ READOUT_TX.data(17 downto 0) <= std_logic_vector(CONF.readout_threshold);
+ when x"05" =>
+ READOUT_TX.data( 7 downto 0) <= std_logic_vector(CONF.presum);
+ READOUT_TX.data(11 downto 8) <= std_logic_vector(CONF.averaging);
+ READOUT_TX.data(13 downto 12) <= std_logic_vector(CONF.block_count);
+ when x"06" =>
+ READOUT_TX.data( 7 downto 0) <= std_logic_vector(CONF.block_avg(0));
+ READOUT_TX.data(15 downto 8) <= std_logic_vector(CONF.block_sums(0));
+ READOUT_TX.data(19 downto 16) <= std_logic_vector(CONF.block_scale(0)(3 downto 0));
+ when x"07" =>
+ READOUT_TX.data( 7 downto 0) <= std_logic_vector(CONF.block_avg(1));
+ READOUT_TX.data(15 downto 8) <= std_logic_vector(CONF.block_sums(1));
+ READOUT_TX.data(19 downto 16) <= std_logic_vector(CONF.block_scale(1)(3 downto 0));
+ when x"08" =>
+ READOUT_TX.data( 7 downto 0) <= std_logic_vector(CONF.block_avg(2));
+ READOUT_TX.data(15 downto 8) <= std_logic_vector(CONF.block_sums(2));
+ READOUT_TX.data(19 downto 16) <= std_logic_vector(CONF.block_scale(2)(3 downto 0));
+ when x"09" =>
+ READOUT_TX.data( 7 downto 0) <= std_logic_vector(CONF.block_avg(3));
+ READOUT_TX.data(15 downto 8) <= std_logic_vector(CONF.block_sums(3));
+ READOUT_TX.data(19 downto 16) <= std_logic_vector(CONF.block_scale(3)(3 downto 0));
+ word_counter <= x"10";
+ when x"10" =>
+ READOUT_TX.data(15 downto 0) <= baseline(0);
+ when x"11" =>
+ READOUT_TX.data(15 downto 0) <= baseline(1);
+ when x"12" =>
+ READOUT_TX.data(15 downto 0) <= baseline(2);
+ when x"13" =>
+ READOUT_TX.data(15 downto 0) <= baseline(3);
+ state <= RELEASE_DIRECT;
+-- when x"14" =>
+-- when x"15" =>
+-- when x"16" =>
+-- when x"17" =>
+-- when x"18" =>
+ end case;
end case;
+
+ if readout_reset = '1' then
+ state <= IDLE;
+ end if;
end process;
+
+statebits <= x"00" when state = IDLE else
+ x"01" when state = RELEASE_DIRECT else
+ x"02" when state = WAIT_FOR_END else
+ x"03" when state = CHECK_STATUS_TRIGGER else
+ x"04" when state = START else
+ x"05" when state = READOUT else
+ x"06" when state = NEXT_BLOCK else
+ x"07" when state = SEND_STATUS else
+ x"FF";
+
end architecture;
+
-- type READOUT_RX is record
-- data_valid : std_logic;
-- valid_timing_trg : std_logic;
-- VVVVVVVV -- ADC data 2x 16 bit, only after 0x4 channel header
-- 1SSSSSSS -- Status word, MSN=0x1
-- 4-AC--LL -- ADC Header, L: number of data words that follow, MSN=0x4
-
+-- 2RRVVVVV -- Configuration data
use work.trb3_components.all;
use work.config.all;
use work.version.all;
-
+use work.adc_package.all;
entity trb3_periph_adc is
port(
signal readout_rx : READOUT_RX;
signal readout_tx : readout_tx_array_t(0 to 11);
+ signal fee_data_finished_in : std_logic_vector(DEVICES-1 downto 0);
+ signal fee_data_write_in : std_logic_vector(DEVICES-1 downto 0);
+ signal fee_trg_release_in : std_logic_vector(DEVICES-1 downto 0);
+ signal fee_data_in : std_logic_vector(32*DEVICES-1 downto 0);
+ signal fee_trg_statusbits_in : std_logic_vector(32*DEVICES-1 downto 0);
+
+
begin
---------------------------------------------------------------------------
-- Reset Generation
USE_CTC => c_NO
)
port map(
- CLK => CLK_PCLK_RIGHT,
+ CLK => CLK_PCLK_RIGHT,
SYSCLK => clk_100_i,
RESET => reset_i,
CLEAR => clear_i,
TRG_SPIKE_DETECTED_OUT => readout_rx.trg_spike,
--Response from FEE
- FEE_TRG_RELEASE_IN(0) => readout_tx(0).busy_release,
- FEE_TRG_STATUSBITS_IN(31 downto 0) => readout_tx(0).statusbits,
- FEE_DATA_IN(31 downto 0) => readout_tx(0).data,
- FEE_DATA_WRITE_IN(0) => readout_tx(0).data_write,
- FEE_DATA_FINISHED_IN(0) => readout_tx(0).data_finished,
- FEE_DATA_ALMOST_FULL_OUT(0) => readout_rx.buffer_almost_full,
+ FEE_TRG_RELEASE_IN => fee_trg_release_in,
+ FEE_TRG_STATUSBITS_IN => fee_trg_statusbits_in,
+ FEE_DATA_IN => fee_data_in,
+ FEE_DATA_WRITE_IN => fee_data_write_in,
+ FEE_DATA_FINISHED_IN => fee_data_finished_in,
+ FEE_DATA_ALMOST_FULL_OUT(0) => readout_rx.buffer_almost_full,
-- Slow Control Data Port
REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00
timing_trg_received_i <= TRIGGER_LEFT; --TRIGGER_RIGHT; --
common_stat_reg <= (others => '0');
+gen_rdo_tx : for i in 0 to DEVICES-1 generate
+ fee_trg_release_in(i) <= readout_tx(i).busy_release;
+ fee_trg_statusbits_in(i*32+31 downto i*32) <= readout_tx(i).statusbits;
+ fee_data_in(i*32+31 downto i*32) <= readout_tx(i).data;
+ fee_data_write_in(i) <= readout_tx(i).data_write;
+ fee_data_finished_in(i) <= readout_tx(i).data_finished;
+end generate;
---------------------------------------------------------------------------
-- AddOn
-------------------------------------------------------------------------------
FPGA_SPI : spi_ltc2600
- generic map (
- BITS => 32,
- WAITCYCLES => 15)
- port map (
- CLK_IN => clk_100_i,
- RESET_IN => reset_i,
- -- Slave bus
- BUS_READ_IN => busspi_rx.read,
- BUS_WRITE_IN => busspi_rx.write,
- BUS_BUSY_OUT => busspi_tx.nack,
- BUS_ACK_OUT => busspi_tx.ack,
- BUS_ADDR_IN => busspi_rx.addr(4 downto 0),
- BUS_DATA_IN => busspi_rx.data,
- BUS_DATA_OUT => busspi_tx.data,
- -- SPI connections
- SPI_CS_OUT => spi_CS,
- SPI_SDI_IN => spi_SDI,
- SPI_SDO_OUT => spi_SDO,
- SPI_SCK_OUT => spi_SCK,
- SPI_CLR_OUT => open
- );
+ generic map (
+ BITS => 32,
+ WAITCYCLES => 15)
+ port map (
+ CLK_IN => clk_100_i,
+ RESET_IN => reset_i,
+ -- Slave bus
+ BUS_READ_IN => busspi_rx.read,
+ BUS_WRITE_IN => busspi_rx.write,
+ BUS_BUSY_OUT => busspi_tx.nack,
+ BUS_ACK_OUT => busspi_tx.ack,
+ BUS_ADDR_IN => busspi_rx.addr(4 downto 0),
+ BUS_DATA_IN => busspi_rx.data,
+ BUS_DATA_OUT => busspi_tx.data,
+ -- SPI connections
+ SPI_CS_OUT => spi_CS,
+ SPI_SDI_IN => spi_SDI,
+ SPI_SDO_OUT => spi_SDO,
+ SPI_SCK_OUT => spi_SCK,
+ SPI_CLR_OUT => open
+ );
-- the bits spi_CS (chip select) determines which SPI device is to be programmed
-- it is already inverted, such that spi_CS=0xffff when nothing is to be programmed
-- when which SPI device should be addressed via software
FPGA_CS_mux: process (spi_CS(2 downto 0)) is
- begin -- process FPGA_CS_mux
- case spi_CS(2 downto 0) is
- when b"110" =>
- FPGA_CS <= b"00";
- when b"101" =>
- FPGA_CS <= b"01";
- when b"011" =>
- FPGA_CS <= b"10";
- when others =>
- FPGA_CS <= b"11";
- end case;
- end process FPGA_CS_mux;
+ begin -- process FPGA_CS_mux
+ case spi_CS(2 downto 0) is
+ when b"110" =>
+ FPGA_CS <= b"00";
+ when b"101" =>
+ FPGA_CS <= b"01";
+ when b"011" =>
+ FPGA_CS <= b"10";
+ when others =>
+ FPGA_CS <= b"11";
+ end case;
+ end process FPGA_CS_mux;
FPGA_SCK(0) <= spi_SCK when spi_CS(2 downto 0) /= b"111" else '1';
FPGA_SDI(0) <= spi_SDO when spi_CS(2 downto 0) /= b"111" else '0';
# UGROUP "Proc_11" BBOX 60 60
# BLKNAME gen_reallogic_THE_ADC/gen_processors_11_THE_ADC_PROC;
-
+INPUT_SETUP ALLPORTS 1.5 ns HOLD 1.5 ns CLKPORT ADC_DCO_1;
+INPUT_SETUP ALLPORTS 1.5 ns HOLD 1.5 ns CLKPORT ADC_DCO_2;
+INPUT_SETUP ALLPORTS 1.5 ns HOLD 1.5 ns CLKPORT ADC_DCO_3;
+INPUT_SETUP ALLPORTS 1.5 ns HOLD 1.5 ns CLKPORT ADC_DCO_4;
+INPUT_SETUP ALLPORTS 1.5 ns HOLD 1.5 ns CLKPORT ADC_DCO_5;
+INPUT_SETUP ALLPORTS 1.5 ns HOLD 1.5 ns CLKPORT ADC_DCO_6;
+INPUT_SETUP ALLPORTS 1.5 ns HOLD 1.5 ns CLKPORT ADC_DCO_7;
+INPUT_SETUP ALLPORTS 1.5 ns HOLD 1.5 ns CLKPORT ADC_DCO_8;
+INPUT_SETUP ALLPORTS 1.5 ns HOLD 1.5 ns CLKPORT ADC_DCO_9;
+INPUT_SETUP ALLPORTS 1.5 ns HOLD 1.5 ns CLKPORT ADC_DCO_10;
+INPUT_SETUP ALLPORTS 1.5 ns HOLD 1.5 ns CLKPORT ADC_DCO_11;
+INPUT_SETUP ALLPORTS 1.5 ns HOLD 1.5 ns CLKPORT ADC_DCO_12;
#################################################################
# Clocks
jspc29 / trb3.git / commitdiff