update

diff --git a/cts.tex b/cts.tex
index e0c4db63b3d442e60a48fa80432c8a0b05a1386e..1a79340ee53948787c60a307d6c31d8cce83301d 100644 (file)
--- a/cts.tex
+++ b/cts.tex
@@ -66,7 +66,7 @@ For all registers described in this subsection refer to the Fig.\ref{cts_logic}
      \item[Bit 6 -- 0] LVL1 trigger information(6 -- 0)
      \item[Bit 13 -- 8] LVL1 trigger information(13 -- 8)
     \end{description}
-  \item [0xA0E7 -- 0xA0E5] Large delays
+  \item [0xA0E7 -- 0xA0E5] Large delays - value * 5ns
 
 \end{description}