LOCK : out std_logic);
end component pll_in200_out100;
+ component pll_in20_out100 is
+ port (
+ CLK : in std_logic; -- 20 MHz
+ CLKOP : out std_logic; -- 100 MHz
+ CLKOS : out std_logic; -- 20 MHz, bypass
+ LOCK : out std_logic);
+ end component pll_in20_out100;
+
component pll_calibration is
port (
CLK : in std_logic; -- clk_in 100MHz
LOCK : out std_logic);
end component pll_calibration;
--- component OSCF -- internal oscillator with a frequency of 2MHz
----- synthesis translate_off
--- generic (NOM_FREQ : string := "20.0");
----- synthesis translate_on
--- port (OSC : out std_logic);
--- end component;
+ component OSCF -- internal oscillator with a frequency of 2MHz
+-- synthesis translate_off
+ generic (NOM_FREQ : string := "20.0");
+-- synthesis translate_on
+ port (OSC : out std_logic);
+ end component;
--component OSCF
-- port (OSC : out
-- std_logic);
--end component;
- component FIFO_32x32_OutReg
- port (
- Data : in std_logic_vector(31 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(31 downto 0);
- Empty : out std_logic;
- Full : out std_logic;
- AlmostFull : out std_logic);
- end component;
-
- component FIFO_36x128_OutReg is
- port (
- Data : in std_logic_vector(35 downto 0);
- Clock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- Q : out std_logic_vector(35 downto 0);
- Empty : out std_logic;
- Full : out std_logic);
- end component FIFO_36x128_OutReg;
-
- component FIFO_36x64_OutReg is
- port (
- Data : in std_logic_vector(35 downto 0);
- Clock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- Q : out std_logic_vector(35 downto 0);
- Empty : out std_logic;
- Full : out std_logic);
- end component;
-
- component FIFO_36x32_OutReg is
- port (
- Data : in std_logic_vector(35 downto 0);
- Clock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- Q : out std_logic_vector(35 downto 0);
- Empty : out std_logic;
- Full : out std_logic);
- end component FIFO_36x32_OutReg;
-
- component FIFO_36x16_OutReg is
- port (
- Data : in std_logic_vector(35 downto 0);
- Clock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- Q : out std_logic_vector(35 downto 0);
- Empty : out std_logic;
- Full : out std_logic);
- end component;
-
- component FIFO_DC_36x128_DynThr_OutReg is
- port (
- Data : in std_logic_vector(35 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- AmFullThresh : in std_logic_vector(6 downto 0);
- Q : out std_logic_vector(35 downto 0);
- Empty : out std_logic;
- Full : out std_logic;
- AlmostFull : out std_logic);
- end component FIFO_DC_36x128_DynThr_OutReg;
-
- component FIFO_DC_36x128_OutReg is
- port (
- Data : in std_logic_vector(35 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(35 downto 0);
- Empty : out std_logic;
- Full : out std_logic;
- AlmostFull : out std_logic);
- end component FIFO_DC_36x128_OutReg;
-
- component FIFO_DC_36x64_OutReg is
- port (
- Data : in std_logic_vector(35 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(35 downto 0);
- Empty : out std_logic;
- Full : out std_logic;
- AlmostFull : out std_logic);
- end component FIFO_DC_36x64_OutReg;
-
- component FIFO_DC_36x32_OutReg is
- port (
- Data : in std_logic_vector(35 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(35 downto 0);
- Empty : out std_logic;
- Full : out std_logic;
- AlmostFull : out std_logic);
- end component;
-
- component FIFO_DC_36x16_OutReg is
- port (
- Data : in std_logic_vector(35 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(35 downto 0);
- Empty : out std_logic;
- Full : out std_logic;
- AlmostFull : out std_logic);
- end component;
-
- component FIFO_36x128_OutReg_Counter is
- port (
- Data : in std_logic_vector(35 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(35 downto 0);
- WCNT : out std_logic_vector(7 downto 0);
- Empty : out std_logic;
- Full : out std_logic);
- end component FIFO_36x128_OutReg_Counter;
-
- component bit_sync
- generic (
- DEPTH : integer);
- port (
- RESET : in std_logic;
- CLK0 : in std_logic;
- CLK1 : in std_logic;
- D_IN : in std_logic;
- D_OUT : out std_logic);
- end component;
-
- component edge_to_pulse
- port (
- clock : in std_logic;
- en_clk : in std_logic;
- signal_in : in std_logic;
- pulse : out std_logic);
- end component;
-
- component risingEdgeDetect is
- port (
- CLK : in std_logic;
- SIGNAL_IN : in std_logic;
- PULSE_OUT : out std_logic);
- end component risingEdgeDetect;
-
- component fallingEdgeDetect is
- port (
- CLK : in std_logic;
- SIGNAL_IN : in std_logic;
- PULSE_OUT : out std_logic);
- end component fallingEdgeDetect;
-
- component ShiftRegisterSISO
- generic (
- DEPTH : integer range 1 to 32;
- WIDTH : integer range 1 to 32);
- port (
- CLK : in std_logic;
- D_IN : in std_logic_vector(WIDTH-1 downto 0);
- D_OUT : out std_logic_vector(WIDTH-1 downto 0));
- end component;
-
- component Stretcher
- port (
- PULSE_IN : in std_logic;
- PULSE_OUT : out std_logic);
- end component;
-
- component WaveLauncher is
- port (
- HIT_IN : in std_logic;
- HIT_OUT : out std_logic);
- end component WaveLauncher;
-
component adc_ad9222
generic(
CHANNELS : integer range 4 to 4 := 4;
use work.trb_net_std.all;
use work.trb_net_components.all;
use work.trb3_components.all;
-use work.version.all;
entity BusHandler is
generic (
-- File : Stretcher.vhd
-- Author : cugur@gsi.de
-- Created : 2012-11-07
--- Last update: 2015-01-30
+-- Last update: 2015-02-17
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
pulse_a_in(DEPTH*i) <= PULSE_IN(i-1);
pulse_a_in(DEPTH*i-1 downto DEPTH*(i-1)+1) <= pulse_b_out(DEPTH*i-1 downto DEPTH*(i-1)+1);
pulse_b_in(DEPTH*i-1 downto DEPTH*(i-1)+1) <= pulse_a_out(DEPTH*i-1 downto DEPTH*(i-1)+1);
- PULSE_OUT(i-1) <= transport not pulse_a_out(DEPTH*(i-1)) after 34 ns;
+ PULSE_OUT(i-1) <= transport not pulse_a_out(DEPTH*(i-1)) after 28 ns;
end generate GEN;
Stretcher_A_1 : entity work.Stretcher_A
use work.config.all;
use work.tdc_components.all;
use work.tdc_version.all;
-use work.version.all;
entity TDC is
generic (
- CHANNEL_NUMBER : integer range 2 to 65;
- STATUS_REG_NR : integer range 0 to 31;
- CONTROL_REG_NR : integer range 1 to 8;
- DEBUG : integer range 0 to 1 := c_NO;
- SIMULATION : integer range 0 to 1 := c_NO);
+ CHANNEL_NUMBER : integer range 2 to 65 := 5;
+ STATUS_REG_NR : integer range 0 to 31 := 21;
+ CONTROL_REG_NR : integer range 1 to 8 := 8;
+ DEBUG : integer range 0 to 1 := c_NO;
+ SIMULATION : integer range 0 to 1 := c_NO);
port (
RESET : in std_logic;
CLK_TDC : in std_logic;
HIT_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 1);
HIT_CAL_IN : in std_logic;
TRG_WIN_PRE : in std_logic_vector(10 downto 0);
- TRG_WIN_POST : in std_logic_vector(10 downto 0);
+ TRG_WIN_POST : in std_logic_vector(10 downto 0) := "00000001010";
--
-- Trigger signals from handler
TRG_DATA_VALID_IN : in std_logic := '0';
-- Logic analyser
signal logic_anal_data : std_logic_vector(3*32-1 downto 0);
-- Hit signals
- signal hit_in_d : std_logic_vector(CHANNEL_NUMBER-1 downto 0);
- signal hit_in_s : std_logic_vector(CHANNEL_NUMBER-1 downto 0);
- signal hit_in_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0);
+ signal hit_in_d : std_logic_vector(CHANNEL_NUMBER-1 downto 0) := (others => '0');
+ signal hit_in_d_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0) := (others => '0');
+ signal hit_in_s : std_logic_vector(CHANNEL_NUMBER-1 downto 0) := (others => '0');
+ signal hit_in_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0) := (others => '0');
signal hit_latch : std_logic_vector(CHANNEL_NUMBER-1 downto 1) := (others => '0');
signal hit_edge : std_logic_vector(CHANNEL_NUMBER-1 downto 1) := (others => '0');
signal edge_rising : std_logic_vector(CHANNEL_NUMBER-1 downto 1) := (others => '0');
- signal edge_rising_r : std_logic_vector(CHANNEL_NUMBER-1 downto 1);
- signal edge_rising_2r : std_logic_vector(CHANNEL_NUMBER-1 downto 1);
- signal edge_rising_3r : std_logic_vector(CHANNEL_NUMBER-1 downto 1);
+ signal edge_rising_r : std_logic_vector(CHANNEL_NUMBER-1 downto 1) := (others => '0');
+ signal edge_rising_2r : std_logic_vector(CHANNEL_NUMBER-1 downto 1) := (others => '0');
+ signal edge_rising_3r : std_logic_vector(CHANNEL_NUMBER-1 downto 1) := (others => '0');
signal edge_falling : std_logic_vector(CHANNEL_NUMBER-1 downto 1) := (others => '0');
- signal edge_falling_r : std_logic_vector(CHANNEL_NUMBER-1 downto 1);
- signal edge_falling_2r : std_logic_vector(CHANNEL_NUMBER-1 downto 1);
- signal edge_falling_3r : std_logic_vector(CHANNEL_NUMBER-1 downto 1);
+ signal edge_falling_r : std_logic_vector(CHANNEL_NUMBER-1 downto 1) := (others => '0');
+ signal edge_falling_2r : std_logic_vector(CHANNEL_NUMBER-1 downto 1) := (others => '0');
+ signal edge_falling_3r : std_logic_vector(CHANNEL_NUMBER-1 downto 1) := (others => '0');
+ signal edge_falling_d : std_logic_vector(CHANNEL_NUMBER-1 downto 1) := (others => '0');
+ signal edge_falling_d_r : std_logic_vector(CHANNEL_NUMBER-1 downto 1) := (others => '0');
+ signal edge_falling_d_2r : std_logic_vector(CHANNEL_NUMBER-1 downto 1) := (others => '0');
+ signal edge_falling_d_3r : std_logic_vector(CHANNEL_NUMBER-1 downto 1) := (others => '0');
-- Calibration
signal hit_cal_cntr : unsigned(15 downto 0) := (others => '0');
signal hit_cal_i : std_logic;
end process HitSelectRef;
GEN_HitSelect : for i in 1 to CHANNEL_NUMBER-1 generate
- HitSelect : process (calibration_on_5r, HIT_IN, hit_cal, ch_invert) is
- begin
- if calibration_on_5r = '0' then
- if ch_invert(i) = '0' then
- hit_in_s(i) <= HIT_IN(i);
+ Double: if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 or (DOUBLE_EDGE_TYPE = 2 and (i mod 2 = 1)) generate
+ HitSelect : process (calibration_on_5r, HIT_IN, hit_cal, ch_invert) is
+ begin
+ if calibration_on_5r = '0' then
+ if ch_invert(i) = '0' then
+ hit_in_s(i) <= HIT_IN(i);
+ else
+ hit_in_s(i) <= not HIT_IN(i);
+ end if;
else
- hit_in_s(i) <= not HIT_IN(i);
+ hit_in_s(i) <= hit_cal;
end if;
- else
- hit_in_s(i) <= hit_cal;
- end if;
- end process HitSelect;
+ end process HitSelect;
+ end generate Double;
+ Single: if DOUBLE_EDGE_TYPE = 2 and (i mod 2 = 0) generate
+ HitSelect : process (calibration_on_5r, HIT_IN, hit_cal, ch_invert) is
+ begin
+ if calibration_on_5r = '0' then
+ if ch_invert(i) = '0' then
+ hit_in_s(i) <= HIT_IN(i);
+ else
+ hit_in_s(i) <= not HIT_IN(i);
+ end if;
+ else
+ hit_in_s(i) <= not hit_cal;
+ end if;
+ end process HitSelect;
+ end generate Single;
end generate GEN_HitSelect;
+
+-------------------------------------------------------------------------------
gen_double_withStretcher : if DOUBLE_EDGE_TYPE = 3 generate
The_Stretcher : entity work.Stretcher
generic map (
CHANNEL => CHANNEL_NUMBER-1,
- DEPTH => 3)
+ DEPTH => 4)
port map (
- PULSE_IN => hit_in_s(CHANNEL_NUMBER-1 downto 1),
- PULSE_OUT => hit_in_d(CHANNEL_NUMBER-1 downto 1));
+ PULSE_IN => edge_falling(CHANNEL_NUMBER-1 downto 1),
+ PULSE_OUT => edge_falling_d(CHANNEL_NUMBER-1 downto 1));
end generate gen_double_withStretcher;
gen_double_withoutStretcher : if DOUBLE_EDGE_TYPE = 1 generate
- hit_in_d(CHANNEL_NUMBER-1 downto 1) <= hit_in_s(CHANNEL_NUMBER-1 downto 1);
+ edge_falling_d(CHANNEL_NUMBER-1 downto 1) <= edge_falling(CHANNEL_NUMBER-1 downto 1);
end generate gen_double_withoutStretcher;
edge_rising_2r(i) <= edge_rising_r(i) when rising_edge(CLK_TDC);
edge_rising_3r(i) <= edge_rising_r(i) and not edge_rising_2r(i) when rising_edge(CLK_TDC);
- edge_falling(i) <= '0' when edge_falling_3r(i) = '1' else
- '1' when falling_edge(hit_in_d(i));
+ edge_falling(i) <= '0' when edge_falling_3r(i) = '1' else
+ '1' when falling_edge(hit_in_s(i));
edge_falling_r(i) <= edge_falling(i) when rising_edge(CLK_TDC);
edge_falling_2r(i) <= edge_falling_r(i) when rising_edge(CLK_TDC);
edge_falling_3r(i) <= edge_falling_r(i) and not edge_falling_2r(i) when rising_edge(CLK_TDC);
- hit_latch(i) <= edge_rising(i) or edge_falling(i);
+ hit_latch(i) <= edge_rising(i) or edge_falling_d(i);
- HitEdgeDefine: process (CLK_TDC) is
+
+ HitEdgeDefine : process (CLK_TDC) is
begin
- if rising_edge(CLK_TDC) then -- rising clock edge
- if edge_falling_2r(i) = '1' then
+ if rising_edge(CLK_TDC) then -- rising clock edge
+ if edge_falling_d(i) = '1' then
hit_edge(i) <= '0';
elsif edge_rising_r(i) = '1' then
hit_edge(i) <= '1';
- end if;
+ end if;
end if;
end process HitEdgeDefine;
+
+ edge_falling_d_r(i) <= edge_falling_d(i) when rising_edge(CLK_TDC);
+ edge_falling_d_2r(i) <= edge_falling_d_r(i) when rising_edge(CLK_TDC);
+ edge_falling_d_3r(i) <= edge_falling_d_r(i) and not edge_falling_d_2r(i) when rising_edge(CLK_TDC);
+
--hit_edge(i) <= '0' when edge_falling_2r(i) = '1' else
-- '1' when rising_edge(edge_rising(i));
end generate gen_double;
-
+-------------------------------------------------------------------------------
+ --gen_double_withStretcher : if DOUBLE_EDGE_TYPE = 3 generate
+ -- The_Stretcher : entity work.Stretcher
+ -- generic map (
+ -- CHANNEL => CHANNEL_NUMBER-1,
+ -- DEPTH => 3)
+ -- port map (
+ -- PULSE_IN => hit_in_s(CHANNEL_NUMBER-1 downto 1),
+ -- PULSE_OUT => hit_in_d(CHANNEL_NUMBER-1 downto 1));
+ --end generate gen_double_withStretcher;
+
+ --gen_double_withoutStretcher : if DOUBLE_EDGE_TYPE = 1 generate
+ -- hit_in_d(CHANNEL_NUMBER-1 downto 1) <= hit_in_s(CHANNEL_NUMBER-1 downto 1);
+ --end generate gen_double_withoutStretcher;
+
+
+ ---- Blocks the input after the rising edge against short pulses
+ --GEN_HitBlock : for i in 1 to CHANNEL_NUMBER-1 generate
+ -- gen_double : if DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate
+ -- edge_rising(i) <= '0' when edge_rising_3r(i) = '1' else
+ -- edge_rising(i) when hit_edge(i) = '1' else
+ -- '1' when rising_edge(hit_in_s(i));
+ -- edge_rising_r(i) <= edge_rising(i) when rising_edge(CLK_TDC);
+ -- edge_rising_2r(i) <= edge_rising_r(i) when rising_edge(CLK_TDC);
+ -- edge_rising_3r(i) <= edge_rising_r(i) and not edge_rising_2r(i) when rising_edge(CLK_TDC);
+
+ -- edge_falling(i) <= '0' when edge_falling_3r(i) = '1' else
+ -- '1' when falling_edge(hit_in_d(i));
+ -- edge_falling_r(i) <= edge_falling(i) when rising_edge(CLK_TDC);
+ -- edge_falling_2r(i) <= edge_falling_r(i) when rising_edge(CLK_TDC);
+ -- edge_falling_3r(i) <= edge_falling_r(i) and not edge_falling_2r(i) when rising_edge(CLK_TDC);
+
+ -- hit_latch(i) <= edge_rising(i) or edge_falling(i);
+
+ -- HitEdgeDefine: process (CLK_TDC) is
+ -- begin
+ -- if rising_edge(CLK_TDC) then -- rising clock edge
+ -- if edge_falling_2r(i) = '1' then
+ -- hit_edge(i) <= '0';
+ -- elsif edge_rising_r(i) = '1' then
+ -- hit_edge(i) <= '1';
+ -- end if;
+ -- end if;
+ -- end process HitEdgeDefine;
+ -- --hit_edge(i) <= '0' when edge_falling_2r(i) = '1' else
+ -- -- '1' when rising_edge(edge_rising(i));
+ -- end generate gen_double;
+-------------------------------------------------------------------------------
-- for single edge and double edge in alternating channel setup
gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 2 generate
edge_rising(i) <= '0' when edge_rising_3r(i) = '1' else
ch_level_hit_number(0)(31) <= REFERENCE_TIME when rising_edge(CLK_READOUT);
ch_level_hit_number(0)(30 downto 0) <= std_logic_vector(ch_hit_detect_cntr(0)) when rising_edge(CLK_READOUT);
GenHitDetectNumber : for i in 1 to CHANNEL_NUMBER-1 generate
- ch_level_hit_number(i)(31) <= hit_in_s(i) when rising_edge(CLK_READOUT);
+ ch_level_hit_number(i)(31) <= HIT_IN(i) when rising_edge(CLK_READOUT);
ch_level_hit_number(i)(30 downto 0) <= std_logic_vector(ch_hit_detect_cntr(i)) when rising_edge(CLK_READOUT);
end generate GenHitDetectNumber;
--logic_anal_data(63 downto 48) <= ch_debug(1)(15 downto 0);
--logic_anal_data(95 downto 64) <= (others => '0');
- LOGIC_ANALYSER_OUT(0) <= hit_cal;
- LOGIC_ANALYSER_OUT(1) <= hit_in_i(0);
- LOGIC_ANALYSER_OUT(2) <= hit_in_i(1);
- LOGIC_ANALYSER_OUT(3) <= hit_in_i(2);
- LOGIC_ANALYSER_OUT(4) <= hit_in_i(3);
- LOGIC_ANALYSER_OUT(5) <= hit_in_i(4);
- --LOGIC_ANALYSER_OUT(6) <= hit_in_i(5);
- --LOGIC_ANALYSER_OUT(7) <= hit_in_i(6);
- --LOGIC_ANALYSER_OUT(8) <= hit_in_i(7);
- --LOGIC_ANALYSER_OUT(9) <= hit_in_i(8);
- --LOGIC_ANALYSER_OUT(10) <= hit_in_i(9);
- --LOGIC_ANALYSER_OUT(11) <= hit_in_i(10);
- --LOGIC_ANALYSER_OUT(12) <= hit_in_i(11);
- --LOGIC_ANALYSER_OUT(13) <= hit_in_i(12);
- --LOGIC_ANALYSER_OUT(14) <= hit_in_i(13);
- --LOGIC_ANALYSER_OUT(15) <= hit_in_i(14);
+ --LOGIC_ANALYSER_OUT(0) <= hit_in_s(1); -- 0 19
+ --LOGIC_ANALYSER_OUT(1) <= edge_rising(1); -- 1 18
+ --LOGIC_ANALYSER_OUT(2) <= hit_in_d(1); -- 2 17
+ --LOGIC_ANALYSER_OUT(3) <= edge_falling(1); -- 3 16
+ --LOGIC_ANALYSER_OUT(4) <= HIT_IN(1); -- 4 15
+ --LOGIC_ANALYSER_OUT(5) <= HIT_IN(2); -- 5 14
+ --LOGIC_ANALYSER_OUT(6) <= HIT_IN(3); -- 6 13
+ --LOGIC_ANALYSER_OUT(7) <= HIT_IN(4); -- 7 12
+ --LOGIC_ANALYSER_OUT(8) <= hit_in_i(1); -- 8 11
+ --LOGIC_ANALYSER_OUT(9) <= hit_in_i(2); -- 9 10
+ --LOGIC_ANALYSER_OUT(10) <= hit_in_i(3); -- 10 9
+ --LOGIC_ANALYSER_OUT(11) <= hit_in_i(4); -- 11 8
+ --LOGIC_ANALYSER_OUT(12) <= hit_edge(1); -- 12 7
+ --LOGIC_ANALYSER_OUT(13) <= hit_latch(1); -- 13 6
+ --LOGIC_ANALYSER_OUT(14) <= hit_in_i(1); -- 14 5
+ --LOGIC_ANALYSER_OUT(13) <= hit_in_i(1);
+ --LOGIC_ANALYSER_OUT(14) <= hit_in_i(1);
+ --LOGIC_ANALYSER_OUT(15) <= hit_in_i(1);
+
end TDC;
-- File : TriggerHandler.vhd
-- Author : Cahit Ugur c.ugur@gsi.de
-- Created : 2013-03-13
--- Last update: 2015-02-13
+-- Last update: 2015-03-10
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
signal valid_notiming_200 : std_logic;
signal valid_trigger_flag : std_logic := '0';
-- trigger window signals
- type TrgWinCounter_FSM is (IDLE, COUNT, COUNT_CALIBRATION, VALIDATE_TRIGGER, WIN_END, MISSING_REFERENCE_TIME,
- WAIT_NEXT_TRIGGER);
+ type TrgWinCounter_FSM is (IDLE, CHECK_TRIGGER_LENGTH, COUNT, COUNT_CALIBRATION, VALIDATE_TRIGGER, WIN_END,
+ MISSING_REFERENCE_TIME, WAIT_NEXT_TRIGGER);
signal TrgWin_STATE : TrgWinCounter_FSM;
signal trg_win_cnt_f : unsigned(11 downto 0);
signal trg_win_cnt_r : unsigned(11 downto 0);
else
case TrgWin_STATE is
when IDLE =>
- if trg_pulse_tdc(0) = '1' then
+ if trg_in_3r(0) = '1' then
if TRG_WIN_EN_IN = '1' then
TrgWin_STATE <= COUNT;
else
else
TrgWin_STATE <= IDLE;
end if;
+
when COUNT =>
- if trg_win_cnt_r(10 downto 0) = TRG_WIN_POST_IN + to_unsigned(4, 11) then
+ if trg_win_cnt_r(10 downto 0) = TRG_WIN_POST_IN then
TrgWin_STATE <= VALIDATE_TRIGGER;
else
TrgWin_STATE <= COUNT;
-- Output depends solely on the current state
TrgWinOutput : process (TrgWin_STATE, trg_win_cnt_r)
begin
- trg_win_cnt_f <= x"003";
+ trg_win_cnt_f <= x"00a";
trg_win_end_f <= '0';
missing_ref_time_f <= '0';
trg_win_state_debug_f <= x"0";
when IDLE =>
trg_win_state_debug_f <= x"1";
+ when CHECK_TRIGGER_LENGTH =>
+ trg_win_state_debug_f <= x"2";
+
when COUNT =>
trg_win_cnt_f <= trg_win_cnt_r + to_unsigned(1, 12);
- trg_win_state_debug_f <= x"2";
+ trg_win_state_debug_f <= x"3";
when COUNT_CALIBRATION =>
trg_win_cnt_f <= trg_win_cnt_r + to_unsigned(1, 12);
- trg_win_state_debug_f <= x"3";
+ trg_win_state_debug_f <= x"4";
when VALIDATE_TRIGGER =>
trg_win_end_f <= '0';
- trg_win_state_debug_f <= x"4";
+ trg_win_state_debug_f <= x"5";
when WIN_END =>
trg_win_end_f <= '1';
- trg_win_state_debug_f <= x"5";
+ trg_win_state_debug_f <= x"6";
when MISSING_REFERENCE_TIME =>
trg_win_end_f <= '1';
missing_ref_time_f <= '1';
- trg_win_state_debug_f <= x"6";
+ trg_win_state_debug_f <= x"7";
when WAIT_NEXT_TRIGGER =>
trg_win_end_f <= '0';
- trg_win_state_debug_f <= x"7";
+ trg_win_state_debug_f <= x"8";
end case;
end process TrgWinOutput;
trg_win_cnt_r <= trg_win_cnt_f when rising_edge(CLK_TDC);
#############################################################################
## Stretcher
#############################################################################
-UGROUP "Stretcher_A" BBOX 7 7
+UGROUP "Stretcher_A" BBOX 6 8
BLKNAME THE_TDC/gen_double_withStretcher.The_Stretcher/Stretcher_A_1
;
-LOCATE UGROUP "Stretcher_A" SITE "R117C175D";
+LOCATE UGROUP "Stretcher_A" SITE "R2C174D";
UGROUP "Stretcher_B" BBOX 6 8
BLKNAME THE_TDC/gen_double_withStretcher.The_Stretcher/Stretcher_B_1
--Clock / Reset
signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
- signal osc_int : std_logic; -- clock for calibrating the tdc, 2.5 MHz, via internal osscilator
+ signal clk_20 : std_logic; --clock for calibration at 20 MHz, via PLL
+ signal clk_20_i : std_logic; --clock for calibration at 20 MHz, via PLL
+ signal osc_int : std_logic; --clock for calibration at 20 MHz, via internal osscilator
signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
+ signal pll_lock2 : std_logic; --Internal PLL locked.
signal clear_i : std_logic;
signal reset_i : std_logic;
signal GSR_N : std_logic;
signal tdc_ctrl_addr : std_logic_vector(2 downto 0);
signal tdc_ctrl_data_in : std_logic_vector(31 downto 0);
signal tdc_ctrl_data_out : std_logic_vector(31 downto 0);
- signal tdc_ctrl_reg : std_logic_vector(5*32+31 downto 0);
+ signal tdc_ctrl_reg : std_logic_vector(7*32+31 downto 0);
signal spi_bram_addr : std_logic_vector(7 downto 0);
signal spi_bram_wr_d : std_logic_vector(7 downto 0);
---------------------------------------------------------------------------
-- Clock Handling
---------------------------------------------------------------------------
- THE_MAIN_PLL : pll_in200_out100
- port map(
- CLK => CLK_GPLL_RIGHT,
- CLKOP => clk_100_i,
- CLKOK => clk_200_i,
- LOCK => pll_lock
- );
-
- -- internal oscillator with frequency of 2.5MHz for tdc calibration
- OSCInst0 : OSCF
+ THE_MAIN_PLL : entity work.pll_in200_out100
port map (
- OSC => osc_int);
+ CLK => CLK_GPLL_RIGHT,
+ RESET => '0',
+ CLKOP => clk_100_i, -- 100 MHz
+ CLKOK => clk_200_i, -- 200 MHz, bypass
+ LOCK => pll_lock);
+
+
+ ---- internal oscillator with frequency of 20MHz for tdc calibration
+ --OSCInst0 : OSCF
+ -- -- synthesis translate_off
+ -- generic map (
+ -- NOM_FREQ => "20.0")
+ -- -- synthesis translate_on
+ -- port map (
+ -- OSC => clk_20);
+
+ --pll_calibration: entity work.pll_in20_out100
+ -- port map (
+ -- CLK => clk_20,
+ -- CLKOP => osc_int,
+ -- CLKOS => clk_20_i,
+ -- LOCK => pll_lock2);
+
+ osc_int <= CLK_GPLL_LEFT;
+
---------------------------------------------------------------------------
-- The TrbNet media interface (to other FPGA)
generic map (
CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels
STATUS_REG_NR => 21, -- Number of status regs
- CONTROL_REG_NR => 6, -- Number of control regs - higher than 8 check tdc_ctrl_addr
- TDC_VERSION => TDC_VERSION, -- TDC version number
+ CONTROL_REG_NR => 8, -- Number of control regs - higher than 8 check tdc_ctrl_addr
DEBUG => c_YES,
SIMULATION => c_NO)
port map (
signal tdc_ctrl_addr : std_logic_vector(2 downto 0);
signal tdc_ctrl_data_in : std_logic_vector(31 downto 0);
signal tdc_ctrl_data_out : std_logic_vector(31 downto 0);
- signal tdc_ctrl_reg : std_logic_vector(6*32-1 downto 0);
+ signal tdc_ctrl_reg : std_logic_vector(8*32-1 downto 0);
signal spi_bram_addr : std_logic_vector(7 downto 0);
signal spi_bram_wr_d : std_logic_vector(7 downto 0);
THE_MAIN_PLL : pll_in200_out100
port map(
CLK => CLK_GPLL_RIGHT,
+ RESET => '0',
CLKOP => clk_100_internal,
CLKOK => clk_200_internal,
LOCK => pll_lock
generic map (
CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels
STATUS_REG_NR => 21, -- Number of status regs
- CONTROL_REG_NR => 6, -- Number of control regs - higher than 8 check tdc_ctrl_addr
- TDC_VERSION => TDC_VERSION, -- TDC version number
+ CONTROL_REG_NR => 8, -- Number of control regs - higher than 8 check tdc_ctrl_addr
DEBUG => c_YES,
SIMULATION => c_NO)
port map (
MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" 30 ns;
+
+
+
+REGION "REGION_SPI" "R2C110D" 16 18 DEVSIZE;
+LOCATE UGROUP "THE_SPI_RELOAD/THE_SPI_MASTER/SPI_group" REGION "REGION_SPI";
+LOCATE UGROUP "THE_SPI_RELOAD/THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI";
+
+
+
+REGION "REGION_TRBNET" "R35C110D" 70 18 DEVSIZE;
+LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/MPLEX/MUX_group" REGION "REGION_TRBNET";
+
+LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers.0.geniobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_TRBNET";
+LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers.1.geniobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_TRBNET";
+LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers.3.geniobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_TRBNET";
+LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers.0.geniobuf.IOBUF/genREPLYOBUF1.REPLYOBUF/OBUF_group" REGION "REGION_TRBNET";
+LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers.1.geniobuf.IOBUF/genREPLYOBUF1.REPLYOBUF/OBUF_group" REGION "REGION_TRBNET";
+LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers.3.geniobuf.IOBUF/genREPLYOBUF1.REPLYOBUF/OBUF_group" REGION "REGION_TRBNET";
+LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers.0.geniobuf.IOBUF/genINITOBUF2.gen_INITOBUF3.INITOBUF/OBUF_group" REGION "REGION_TRBNET";
+LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers.1.geniobuf.IOBUF/genINITOBUF2.gen_INITOBUF3.INITOBUF/OBUF_group" REGION "REGION_TRBNET";
+LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers.3.geniobuf.IOBUF/genINITOBUF2.gen_INITOBUF3.INITOBUF/OBUF_group" REGION "REGION_TRBNET";
+
+LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers.1.geniobuf.gen_api.DAT_PASSIVE_API/API_group" REGION "REGION_TRBNET";
+LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers.3.geniobuf.gen_api.DAT_PASSIVE_API/API_group" REGION "REGION_TRBNET";
+LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers.2.gentermbuf.termbuf/TRMBUF_group" REGION "REGION_TRBNET";
+LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers.3.geniobuf.gen_regio.regIO/the_addresses/HUBLOGIC_group" REGION "REGION_TRBNET";
+LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers.3.geniobuf.gen_regio.regIO/RegIO_group" REGION "REGION_TRBNET";
+
+LOCATE UGROUP "THE_BUS_HANDLER/Bus_handler_group" REGION "REGION_TRBNET";
+LOCATE UGROUP "THE_ENDPOINT/THE_INTERNAL_BUS_HANDLER/Bus_handler_group" REGION "REGION_TRBNET";
+
jspc29 / trb3.git / commitdiff