fixed variable names in DataDecoder

diff --git a/mupix/Mupix8/sources/Datapath/MupixTRBReadout.vhd b/mupix/Mupix8/sources/Datapath/MupixTRBReadout.vhd
index 94eb9eb94fbe9d36198170e5141678afde6fa4ad..a92708e92d1c2e218244af1297c505274fc2fb71 100644 (file)
--- a/mupix/Mupix8/sources/Datapath/MupixTRBReadout.vhd
+++ b/mupix/Mupix8/sources/Datapath/MupixTRBReadout.vhd
@@ -101,27 +101,27 @@ architecture rtl of MupixTRBReadout is
 
   component DataDecoder
     generic (
-      D_W   : integer := 32;  -- width of full data word
-      Pix_W : integer := 8;   -- col/row address width
-      ToT_W : integer := 6;   -- time over threshold width
-      TS_W  : integer := 10;  -- timestamp width
-      LINKS : integer := 4    -- number of links (data + counters)
+      DWidth   : integer := 32;  -- width of full data word
+      PixWidth : integer := 8;   -- col/row address width
+      ToTWidth : integer := 6;   -- time over threshold width
+      TSWidth  : integer := 10;  -- timestamp width
+      LINKS    : integer := 4    -- number of links (data + counters)
     );
     port (
       clk           : in std_logic;
       reset         : in std_logic;
       bypass        : in std_logic;
-      datain        : in std_logic_vector(D_W - 1 downto 0);   -- incoming data word
-      datain_valid  : in std_logic;                            -- valid signal for input data
-      counterA_in   : in std_logic_vector(D_W - 1 downto 0);   -- last counter value link A
-      counterB_in   : in std_logic_vector(D_W - 1 downto 0);   -- last counter value link B
-      counterC_in   : in std_logic_vector(D_W - 1 downto 0);   -- last counter value link C
+      datain        : in std_logic_vector(DWidth - 1 downto 0);   -- incoming data word
+      datain_valid  : in std_logic;                               -- valid signal for input data
+      counterA_in   : in std_logic_vector(DWidth - 1 downto 0);   -- last counter value link A
+      counterB_in   : in std_logic_vector(DWidth - 1 downto 0);   -- last counter value link B
+      counterC_in   : in std_logic_vector(DWidth - 1 downto 0);   -- last counter value link C
     
-      dataout       : out std_logic_vector(D_W - 1 downto 0);  -- decoded data word
-      dataout_valid : out std_logic;                           -- valid output data
-      counterA_out  : out std_logic_vector(D_W - 1 downto 0);  -- last counter value link A
-      counterB_out  : out std_logic_vector(D_W - 1 downto 0);  -- last counter value link B
-      counterC_out  : out std_logic_vector(D_W - 1 downto 0)   -- last counter value link C
+      dataout       : out std_logic_vector(DWidth - 1 downto 0);  -- decoded data word
+      dataout_valid : out std_logic;                              -- valid output data
+      counterA_out  : out std_logic_vector(DWidth - 1 downto 0);  -- last counter value link A
+      counterB_out  : out std_logic_vector(DWidth - 1 downto 0);  -- last counter value link B
+      counterC_out  : out std_logic_vector(DWidth - 1 downto 0)   -- last counter value link C
     );
   end component DataDecoder;
 
@@ -246,10 +246,10 @@ begin
 
   DataDecoder_1 : DataDecoder
     generic map (
-      D_W   => g_datawidthtrb,
-      Pix_W => 8,
-      ToT_W => 6,
-      TS_W  => 10,
+      DWidth   => g_datawidthtrb,
+      PixWidth => 8,
+      ToTWidth => 6,
+      TSWidth  => 10,
       LINKS => g_mupix_links
     )
     port map (