Extended converter board XML file according to register ODS

diff --git a/xml-db/database/CbController.xml b/xml-db/database/CbController.xml
index 3c72d371122ddd6f55731358c771fb8b4773b341..c8f082b0efc3257734d16c6d5d734424811b5ed8 100644 (file)
--- a/xml-db/database/CbController.xml
+++ b/xml-db/database/CbController.xml
@@ -134,20 +134,178 @@
     <register  name="Switches"
               address="0001" purpose="config" mode="rw" >
       <description>Set all Converter Board switches.</description>
+
       <field name="EnaA0"
-              start="13" bits="1"  mode="rw"  purpose="config"  format="bitmask" >
+              start="13" bits="1"  format="bitmask" >
         <description>Enable analog power for chip 0.</description>
       </field>
+      <field name="DisA0"
+              start="12" bits="1"  format="bitmask" >
+        <description>Discharge analog power for chip 0.</description>
+      </field>
       <field name="EnaD0"
-              start="12" bits="1"  mode="rw"  purpose="config"  format="bitmask" >
+              start="11" bits="1"  format="bitmask" >
         <description>Enable digital power for chip 0.</description>
       </field>
+      <field name="DisD0"
+              start="10" bits="1"  format="bitmask" >
+        <description>Discharge digital power for chip 0.</description>
+      </field>
+      <field name="SensorEn0"
+              start="9" bits="1"  format="bitmask" >
+        <description>Enable sensor 0.</description>
+      </field>
+      <field name="JtagEn0"
+              start="8" bits="1"  format="bitmask" >
+        <description>Enable JTAG for sensor 0.</description>
+      </field>
+
+      <field name="EnaA1"
+              start="5" bits="1"  mode="rw"  purpose="config"  format="bitmask" >
+        <description>Enable analog power for chip 1.</description>
+      </field>
+      <field name="DisA1"
+              start="4" bits="1"  mode="rw"  purpose="config"  format="bitmask" >
+        <description>Discharge analog power for chip 1.</description>
+      </field>
+      <field name="EnaD1"
+              start="3" bits="1"  mode="rw"  purpose="config"  format="bitmask" >
+        <description>Enable digital power for chip 1.</description>
+      </field>
+      <field name="DisD1"
+              start="2" bits="1"  mode="rw"  purpose="config"  format="bitmask" >
+        <description>Discharge digital power for chip 1.</description>
+      </field>
+      <field name="SensorEn1"
+              start="1" bits="1"  mode="rw"  purpose="config"  format="bitmask" >
+        <description>Enable sensor 1.</description>
+      </field>
+      <field name="JtagEn1"
+              start="0" bits="1"  mode="rw"  purpose="config"  format="bitmask" >
+        <description>Enable JTAG for sensor 1.</description>
+      </field>
+    </register>
+
+
+    <register  name="ADC_conf" address="0002" purpose="config" mode="rw" >
+      <description></description>
+      <field name="CycleRef" start="0" bits="1" format="bitmask" >
+      </field>
+      <field name="CyclePower" start="1" bits="1" format="bitmask" >
+      </field>
+      <field name="StreamSelected" start="2" bits="1" format="bitmask" >
+      </field>
+      <field name="ADC_sel" start="3" bits="1" format="bitmask" >
+      </field>
+      <field name="MuxAddr0" start="4" bits="1" format="bitmask" >
+      </field>
+      <field name="MuxAddr1" start="5" bits="1" format="bitmask" >
+      </field>
+      <field name="ZeroCalib" start="6" bits="1" format="bitmask" >
+      </field>
+      <field name="ADC0_chan0" start="8" bits="1" format="bitmask" >
+      </field>
+      <field name="ADC0_chan1" start="9" bits="1" format="bitmask" >
+      </field>
+      <field name="ADC0_chan2" start="10" bits="1" format="bitmask" >
+      </field>
+      <field name="ADC1_chan0" start="12" bits="1" format="bitmask" >
+      </field>
+      <field name="ADC1_chan1" start="13" bits="1" format="bitmask" >
+      </field>
+      <field name="ADC1_chan2" start="14" bits="1" format="bitmask" >
+      </field>
+    </register>
+
+    <register  name="ADC_read" address="0003" purpose="config" mode="r" >
+      <description></description>
+      <field name="ADC_read" start="0" bits="16" format="bitmask" >
+      </field>
+    </register>
+
+    <register  name="DacCurLimA0" address="0004" purpose="config" mode="rw" >
+      <description></description>
+      <field name="DacCurLimA0" start="0" bits="16" format="bitmask" >
+      </field>
+    </register>
+
+    <register  name="DacCurLimD0" address="0005" purpose="config" mode="rw" >
+      <description></description>
+      <field name="DacCurLimD0" start="0" bits="16" format="bitmask" >
+      </field>
+    </register>
+
+    <register  name="DacVClp0" address="0006" purpose="config" mode="rw" >
+      <description></description>
+      <field name="DacVClp0" start="0" bits="16" format="bitmask" >
+      </field>
+    </register>
+
+    <register  name="DacCurLimA1" address="0007" purpose="config" mode="rw" >
+      <description></description>
+      <field name="DacCurLimA1" start="0" bits="16" format="bitmask" >
+      </field>
+    </register>
+
+    <register  name="DacCurLimD1" address="0008" purpose="config" mode="rw" >
+      <description></description>
+      <field name="DacCurLimD1" start="0" bits="16" format="bitmask" >
+      </field>
+    </register>
+
+    <register  name="DacVClp1" address="0009" purpose="config" mode="rw" >
+      <description></description>
+      <field name="DacVClp1" start="0" bits="16" format="bitmask" >
+      </field>
+    </register>
+
+    <register  name="SpiDebugConf" address="0010" purpose="config" mode="rw" >
+      <description></description>
+      <field name="spiSpeed" start="8" bits="4" format="bitmask" >
+      </field>
+      <field name="16bit_8bit" start="5" bits="1" format="bitmask" >
+      </field>
+      <field name="DebugMode" start="4" bits="1" format="bitmask" >
+      </field>
+      <field name="SpiNo_1" start="1" bits="1" format="bitmask" >
+      </field>
+      <field name="SpiNo_0" start="0" bits="1" format="bitmask" >
+      </field>
+    </register>
+
+    <register  name="SpiDebugCs" address="0011" purpose="config" mode="rw" >
+      <description></description>
+      <field name="SpiDebugCs" start="0" bits="16" format="bitmask" >
+      </field>
+    </register>
+
+    <register  name="SpiDebugWordIn" address="0012" purpose="config" mode="rw" >
+      <description></description>
+      <field name="SpiDebugWordIn" start="0" bits="16" format="bitmask" >
+      </field>
     </register>
+
+    <register  name="SpiDebugWordOut" address="0013" purpose="config" mode="r" >
+      <description></description>
+      <field name="SpiDebugWordOut" start="0" bits="16" format="bitmask" >
+      </field>
+    </register>
+
+    <register  name="OvCurStatus" address="0014" purpose="config" mode="r" >
+      <description></description>
+      <field name="OvCurStatus" start="0" bits="16" format="bitmask" >
+      </field>
+    </register>
+
+    <register  name="MiscConf" address="0015" purpose="config" mode="rw" >
+      <description></description>
+      <field name="MiscConf" start="0" bits="16" format="bitmask" >
+      </field>
+    </register>
+
+
   </group>
   
-  
-  
-  
 
 </TrbNetEntity>