-- VHDL netlist generated by SCUBA Diamond_2.0_Production (151)
-- Module Version: 5.4
---/usr/local/opt/lattice_diamond/diamond/2.0/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 256 -width 9 -depth 256 -rdata_width 36 -regout -pe -1 -pf -1 -e
+--/usr/local/opt/lattice_diamond/diamond/2.0/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 256 -width 9 -depth 256 -rdata_width 36 -regout -no_enable -pe 0 -pf -1 -e
--- Sat Nov 24 15:58:10 2012
+-- Sun Mar 24 00:15:23 2013
library IEEE;
use IEEE.std_logic_1164.all;
use ecp3.components.all;
-- synopsys translate_on
-entity fifo_dc_9to36 is
+entity fifo_dc_9to36_dyn is
port (
Data: in std_logic_vector(8 downto 0);
WrClock: in std_logic;
RdEn: in std_logic;
Reset: in std_logic;
RPReset: in std_logic;
+ AmEmptyThresh: in std_logic_vector(5 downto 0);
Q: out std_logic_vector(35 downto 0);
Empty: out std_logic;
- Full: out std_logic);
-end fifo_dc_9to36;
+ Full: out std_logic;
+ AlmostEmpty: out std_logic);
+end fifo_dc_9to36_dyn;
-architecture Structure of fifo_dc_9to36 is
+architecture Structure of fifo_dc_9to36_dyn is
-- internal signal declarations
signal invout_1: std_logic;
signal wcount_r1: std_logic;
signal wcount_r0: std_logic;
signal w_g2b_xor_cluster_1: std_logic;
+ signal rcnt_reg_5_inv: std_logic;
signal w_gdata_0: std_logic;
signal w_gdata_1: std_logic;
signal w_gdata_2: std_logic;
signal r_gcount_w5: std_logic;
signal r_gcount_w26: std_logic;
signal r_gcount_w6: std_logic;
+ signal rcnt_reg_6: std_logic;
signal empty_i: std_logic;
- signal rRst: std_logic;
signal full_i: std_logic;
+ signal rRst: std_logic;
signal iwcount_0: std_logic;
signal iwcount_1: std_logic;
signal w_gctr_ci: std_logic;
signal co4: std_logic;
signal wcount_8: std_logic;
signal co3: std_logic;
- signal scuba_vhi: std_logic;
signal ircount_0: std_logic;
signal ircount_1: std_logic;
signal r_gctr_ci: std_logic;
signal co3_1: std_logic;
signal rcount_6: std_logic;
signal co2_1: std_logic;
- signal rden_i: std_logic;
+ signal rcnt_sub_0: std_logic;
+ signal scuba_vhi: std_logic;
+ signal rcnt_sub_1: std_logic;
+ signal rcnt_sub_2: std_logic;
+ signal co0_2: std_logic;
+ signal rcnt_sub_3: std_logic;
+ signal rcnt_sub_4: std_logic;
+ signal co1_2: std_logic;
+ signal rcnt_sub_5: std_logic;
+ signal rcnt_sub_6: std_logic;
+ signal co2_2: std_logic;
+ signal rcnt_sub_msb: std_logic;
+ signal co3_2d: std_logic;
+ signal co3_2: std_logic;
signal cmp_ci: std_logic;
signal wcount_r2: std_logic;
signal wcount_r3: std_logic;
signal rcount_0: std_logic;
signal rcount_1: std_logic;
- signal co0_2: std_logic;
+ signal co0_3: std_logic;
signal wcount_r4: std_logic;
signal w_g2b_xor_cluster_0: std_logic;
signal rcount_2: std_logic;
signal rcount_3: std_logic;
- signal co1_2: std_logic;
+ signal co1_3: std_logic;
signal wcount_r6: std_logic;
signal wcount_r7: std_logic;
signal rcount_4: std_logic;
signal rcount_5: std_logic;
- signal co2_2: std_logic;
+ signal co2_3: std_logic;
signal empty_cmp_clr: std_logic;
signal empty_cmp_set: std_logic;
signal empty_d: std_logic;
signal cmp_ci_1: std_logic;
signal wcount_0: std_logic;
signal wcount_1: std_logic;
- signal co0_3: std_logic;
+ signal co0_4: std_logic;
signal rcount_w0: std_logic;
signal rcount_w1: std_logic;
signal wcount_2: std_logic;
signal wcount_3: std_logic;
- signal co1_3: std_logic;
+ signal co1_4: std_logic;
signal rcount_w2: std_logic;
signal r_g2b_xor_cluster_0: std_logic;
signal wcount_4: std_logic;
signal wcount_5: std_logic;
- signal co2_3: std_logic;
+ signal co2_4: std_logic;
signal rcount_w4: std_logic;
signal rcount_w5: std_logic;
signal wcount_6: std_logic;
signal wcount_7: std_logic;
- signal co3_2: std_logic;
+ signal co3_3: std_logic;
signal full_cmp_clr: std_logic;
signal full_cmp_set: std_logic;
signal full_d: std_logic;
signal full_d_c: std_logic;
+ signal rden_i: std_logic;
+ signal cmp_ci_2: std_logic;
+ signal rcnt_reg_0: std_logic;
+ signal rcnt_reg_1: std_logic;
+ signal co0_5: std_logic;
+ signal rcnt_reg_2: std_logic;
+ signal rcnt_reg_3: std_logic;
+ signal co1_5: std_logic;
+ signal rcnt_reg_4: std_logic;
+ signal rcnt_reg_5: std_logic;
+ signal co2_5: std_logic;
+ signal ae_clrsig: std_logic;
+ signal ae_setsig: std_logic;
+ signal ae_d: std_logic;
+ signal ae_d_c: std_logic;
signal scuba_vlo: std_logic;
-- local component declarations
B1: in std_logic; CI: in std_logic; COUT: out std_logic;
S0: out std_logic; S1: out std_logic);
end component;
+ component FSUB2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; BI: in std_logic; BOUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
component FD1P3BX
port (D: in std_logic; SP: in std_logic; CK: in std_logic;
PD: in std_logic; Q: out std_logic);
attribute MEM_INIT_FILE : string;
attribute RESETMODE : string;
attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_2 : label is "fifo_dc_9to36.lpc";
+ attribute MEM_LPC_FILE of pdp_ram_0_0_2 : label is "fifo_dc_9to36_dyn.lpc";
attribute MEM_INIT_FILE of pdp_ram_0_0_2 : label is "";
attribute RESETMODE of pdp_ram_0_0_2 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_1_1 : label is "fifo_dc_9to36.lpc";
+ attribute MEM_LPC_FILE of pdp_ram_0_1_1 : label is "fifo_dc_9to36_dyn.lpc";
attribute MEM_INIT_FILE of pdp_ram_0_1_1 : label is "";
attribute RESETMODE of pdp_ram_0_1_1 : label is "SYNC";
- attribute MEM_LPC_FILE of pdp_ram_0_2_0 : label is "fifo_dc_9to36.lpc";
+ attribute MEM_LPC_FILE of pdp_ram_0_2_0 : label is "fifo_dc_9to36_dyn.lpc";
attribute MEM_INIT_FILE of pdp_ram_0_2_0 : label is "";
attribute RESETMODE of pdp_ram_0_2_0 : label is "SYNC";
+ attribute GSR of FF_89 : label is "ENABLED";
+ attribute GSR of FF_88 : label is "ENABLED";
+ attribute GSR of FF_87 : label is "ENABLED";
+ attribute GSR of FF_86 : label is "ENABLED";
+ attribute GSR of FF_85 : label is "ENABLED";
+ attribute GSR of FF_84 : label is "ENABLED";
+ attribute GSR of FF_83 : label is "ENABLED";
+ attribute GSR of FF_82 : label is "ENABLED";
attribute GSR of FF_81 : label is "ENABLED";
attribute GSR of FF_80 : label is "ENABLED";
attribute GSR of FF_79 : label is "ENABLED";
begin
-- component instantiation statements
- AND2_t16: AND2
+ AND2_t19: AND2
port map (A=>WrEn, B=>invout_1, Z=>wren_i);
- INV_1: INV
+ INV_2: INV
port map (A=>full_i, Z=>invout_1);
- AND2_t15: AND2
+ AND2_t18: AND2
port map (A=>RdEn, B=>invout_0, Z=>rden_i);
- INV_0: INV
+ INV_1: INV
port map (A=>empty_i, Z=>invout_0);
- OR2_t14: OR2
+ OR2_t17: OR2
port map (A=>Reset, B=>RPReset, Z=>rRst);
- XOR2_t13: XOR2
+ XOR2_t16: XOR2
port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
- XOR2_t12: XOR2
+ XOR2_t15: XOR2
port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
- XOR2_t11: XOR2
+ XOR2_t14: XOR2
port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
- XOR2_t10: XOR2
+ XOR2_t13: XOR2
port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
- XOR2_t9: XOR2
+ XOR2_t12: XOR2
port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
- XOR2_t8: XOR2
+ XOR2_t11: XOR2
port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
- XOR2_t7: XOR2
+ XOR2_t10: XOR2
port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
- XOR2_t6: XOR2
+ XOR2_t9: XOR2
port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
- XOR2_t5: XOR2
+ XOR2_t8: XOR2
port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
- XOR2_t4: XOR2
+ XOR2_t7: XOR2
port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
- XOR2_t3: XOR2
+ XOR2_t6: XOR2
port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
- XOR2_t2: XOR2
+ XOR2_t5: XOR2
port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
- XOR2_t1: XOR2
+ XOR2_t4: XOR2
port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
- XOR2_t0: XOR2
+ XOR2_t3: XOR2
port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
LUT4_18: ROM16X1A
port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
AD1=>r_gcount_w22, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w0);
+ XOR2_t2: XOR2
+ port map (A=>w_gcount_r28, B=>rcount_6, Z=>rcnt_sub_msb);
+
LUT4_3: ROM16X1A
generic map (initval=> X"0410")
port map (AD3=>rptr_6, AD2=>rcount_6, AD1=>w_gcount_r28,
port map (AD3=>wptr_8, AD2=>wcount_8, AD1=>r_gcount_w26,
AD0=>scuba_vlo, DO0=>full_cmp_clr);
+ INV_0: INV
+ port map (A=>rcnt_reg_5, Z=>rcnt_reg_5_inv);
+
+ AND2_t1: AND2
+ port map (A=>rcnt_reg_6, B=>rcnt_reg_5_inv, Z=>ae_clrsig);
+
+ AND2_t0: AND2
+ port map (A=>rcnt_reg_6, B=>rcnt_reg_5, Z=>ae_setsig);
+
pdp_ram_0_0_2: DP16KC
generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>rptr_0, ADB5=>rptr_1,
ADB6=>rptr_2, ADB7=>rptr_3, ADB8=>rptr_4, ADB9=>rptr_5,
ADB10=>scuba_vlo, ADB11=>scuba_vlo, ADB12=>scuba_vlo,
- ADB13=>scuba_vlo, CEB=>rden_i, CLKB=>RdClock, OCEB=>RdEn,
- WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2),
- DOB3=>Q(3), DOB4=>Q(9), DOB5=>Q(10), DOB6=>Q(11),
- DOB7=>Q(12), DOB8=>open, DOB9=>Q(18), DOB10=>Q(19),
- DOB11=>Q(20), DOB12=>Q(21), DOB13=>Q(27), DOB14=>Q(28),
- DOB15=>Q(29), DOB16=>Q(30), DOB17=>open);
+ ADB13=>scuba_vlo, CEB=>rden_i, CLKB=>RdClock,
+ OCEB=>scuba_vhi, WEB=>scuba_vlo, CSB0=>scuba_vlo,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0),
+ DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>Q(9), DOB5=>Q(10),
+ DOB6=>Q(11), DOB7=>Q(12), DOB8=>open, DOB9=>Q(18),
+ DOB10=>Q(19), DOB11=>Q(20), DOB12=>Q(21), DOB13=>Q(27),
+ DOB14=>Q(28), DOB15=>Q(29), DOB16=>Q(30), DOB17=>open);
pdp_ram_0_1_1: DP16KC
generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>rptr_0, ADB5=>rptr_1,
ADB6=>rptr_2, ADB7=>rptr_3, ADB8=>rptr_4, ADB9=>rptr_5,
ADB10=>scuba_vlo, ADB11=>scuba_vlo, ADB12=>scuba_vlo,
- ADB13=>scuba_vlo, CEB=>rden_i, CLKB=>RdClock, OCEB=>RdEn,
- WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>Q(4), DOB1=>Q(5), DOB2=>Q(6),
- DOB3=>Q(7), DOB4=>Q(13), DOB5=>Q(14), DOB6=>Q(15),
- DOB7=>Q(16), DOB8=>open, DOB9=>Q(22), DOB10=>Q(23),
- DOB11=>Q(24), DOB12=>Q(25), DOB13=>Q(31), DOB14=>Q(32),
- DOB15=>Q(33), DOB16=>Q(34), DOB17=>open);
+ ADB13=>scuba_vlo, CEB=>rden_i, CLKB=>RdClock,
+ OCEB=>scuba_vhi, WEB=>scuba_vlo, CSB0=>scuba_vlo,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(4),
+ DOB1=>Q(5), DOB2=>Q(6), DOB3=>Q(7), DOB4=>Q(13), DOB5=>Q(14),
+ DOB6=>Q(15), DOB7=>Q(16), DOB8=>open, DOB9=>Q(22),
+ DOB10=>Q(23), DOB11=>Q(24), DOB12=>Q(25), DOB13=>Q(31),
+ DOB14=>Q(32), DOB15=>Q(33), DOB16=>Q(34), DOB17=>open);
pdp_ram_0_2_0: DP16KC
generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>rptr_0, ADB5=>rptr_1,
ADB6=>rptr_2, ADB7=>rptr_3, ADB8=>rptr_4, ADB9=>rptr_5,
ADB10=>scuba_vlo, ADB11=>scuba_vlo, ADB12=>scuba_vlo,
- ADB13=>scuba_vlo, CEB=>rden_i, CLKB=>RdClock, OCEB=>RdEn,
- WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>Q(8), DOB1=>open, DOB2=>open,
- DOB3=>open, DOB4=>Q(17), DOB5=>open, DOB6=>open, DOB7=>open,
- DOB8=>open, DOB9=>Q(26), DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>Q(35), DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
- FF_81: FD1P3BX
+ ADB13=>scuba_vlo, CEB=>rden_i, CLKB=>RdClock,
+ OCEB=>scuba_vhi, WEB=>scuba_vlo, CSB0=>scuba_vlo,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(8),
+ DOB1=>open, DOB2=>open, DOB3=>open, DOB4=>Q(17), DOB5=>open,
+ DOB6=>open, DOB7=>open, DOB8=>open, DOB9=>Q(26), DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>Q(35), DOB14=>open,
+ DOB15=>open, DOB16=>open, DOB17=>open);
+
+ FF_89: FD1P3BX
port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
Q=>wcount_0);
- FF_80: FD1P3DX
+ FF_88: FD1P3DX
port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wcount_1);
- FF_79: FD1P3DX
+ FF_87: FD1P3DX
port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wcount_2);
- FF_78: FD1P3DX
+ FF_86: FD1P3DX
port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wcount_3);
- FF_77: FD1P3DX
+ FF_85: FD1P3DX
port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wcount_4);
- FF_76: FD1P3DX
+ FF_84: FD1P3DX
port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wcount_5);
- FF_75: FD1P3DX
+ FF_83: FD1P3DX
port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wcount_6);
- FF_74: FD1P3DX
+ FF_82: FD1P3DX
port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wcount_7);
- FF_73: FD1P3DX
+ FF_81: FD1P3DX
port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wcount_8);
- FF_72: FD1P3DX
+ FF_80: FD1P3DX
port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>w_gcount_0);
- FF_71: FD1P3DX
+ FF_79: FD1P3DX
port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>w_gcount_1);
- FF_70: FD1P3DX
+ FF_78: FD1P3DX
port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>w_gcount_2);
- FF_69: FD1P3DX
+ FF_77: FD1P3DX
port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>w_gcount_3);
- FF_68: FD1P3DX
+ FF_76: FD1P3DX
port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>w_gcount_4);
- FF_67: FD1P3DX
+ FF_75: FD1P3DX
port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>w_gcount_5);
- FF_66: FD1P3DX
+ FF_74: FD1P3DX
port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>w_gcount_6);
- FF_65: FD1P3DX
+ FF_73: FD1P3DX
port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>w_gcount_7);
- FF_64: FD1P3DX
+ FF_72: FD1P3DX
port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>w_gcount_8);
- FF_63: FD1P3DX
+ FF_71: FD1P3DX
port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wptr_0);
- FF_62: FD1P3DX
+ FF_70: FD1P3DX
port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wptr_1);
- FF_61: FD1P3DX
+ FF_69: FD1P3DX
port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wptr_2);
- FF_60: FD1P3DX
+ FF_68: FD1P3DX
port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wptr_3);
- FF_59: FD1P3DX
+ FF_67: FD1P3DX
port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wptr_4);
- FF_58: FD1P3DX
+ FF_66: FD1P3DX
port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wptr_5);
- FF_57: FD1P3DX
+ FF_65: FD1P3DX
port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wptr_6);
- FF_56: FD1P3DX
+ FF_64: FD1P3DX
port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wptr_7);
- FF_55: FD1P3DX
+ FF_63: FD1P3DX
port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
Q=>wptr_8);
- FF_54: FD1P3BX
+ FF_62: FD1P3BX
port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
Q=>rcount_0);
- FF_53: FD1P3DX
+ FF_61: FD1P3DX
port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rcount_1);
- FF_52: FD1P3DX
+ FF_60: FD1P3DX
port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rcount_2);
- FF_51: FD1P3DX
+ FF_59: FD1P3DX
port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rcount_3);
- FF_50: FD1P3DX
+ FF_58: FD1P3DX
port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rcount_4);
- FF_49: FD1P3DX
+ FF_57: FD1P3DX
port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rcount_5);
- FF_48: FD1P3DX
+ FF_56: FD1P3DX
port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rcount_6);
- FF_47: FD1P3DX
+ FF_55: FD1P3DX
port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>r_gcount_0);
- FF_46: FD1P3DX
+ FF_54: FD1P3DX
port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>r_gcount_1);
- FF_45: FD1P3DX
+ FF_53: FD1P3DX
port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>r_gcount_2);
- FF_44: FD1P3DX
+ FF_52: FD1P3DX
port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>r_gcount_3);
- FF_43: FD1P3DX
+ FF_51: FD1P3DX
port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>r_gcount_4);
- FF_42: FD1P3DX
+ FF_50: FD1P3DX
port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>r_gcount_5);
- FF_41: FD1P3DX
+ FF_49: FD1P3DX
port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>r_gcount_6);
- FF_40: FD1P3DX
+ FF_48: FD1P3DX
port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rptr_0);
- FF_39: FD1P3DX
+ FF_47: FD1P3DX
port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rptr_1);
- FF_38: FD1P3DX
+ FF_46: FD1P3DX
port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rptr_2);
- FF_37: FD1P3DX
+ FF_45: FD1P3DX
port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rptr_3);
- FF_36: FD1P3DX
+ FF_44: FD1P3DX
port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rptr_4);
- FF_35: FD1P3DX
+ FF_43: FD1P3DX
port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rptr_5);
- FF_34: FD1P3DX
+ FF_42: FD1P3DX
port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
Q=>rptr_6);
- FF_33: FD1S3DX
+ FF_41: FD1S3DX
port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
- FF_32: FD1S3DX
+ FF_40: FD1S3DX
port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
- FF_31: FD1S3DX
+ FF_39: FD1S3DX
port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
- FF_30: FD1S3DX
+ FF_38: FD1S3DX
port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
- FF_29: FD1S3DX
+ FF_37: FD1S3DX
port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
- FF_28: FD1S3DX
+ FF_36: FD1S3DX
port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
- FF_27: FD1S3DX
+ FF_35: FD1S3DX
port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
- FF_26: FD1S3DX
+ FF_34: FD1S3DX
port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
- FF_25: FD1S3DX
+ FF_33: FD1S3DX
port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
- FF_24: FD1S3DX
+ FF_32: FD1S3DX
port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
- FF_23: FD1S3DX
+ FF_31: FD1S3DX
port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
- FF_22: FD1S3DX
+ FF_30: FD1S3DX
port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
- FF_21: FD1S3DX
+ FF_29: FD1S3DX
port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
- FF_20: FD1S3DX
+ FF_28: FD1S3DX
port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
- FF_19: FD1S3DX
+ FF_27: FD1S3DX
port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
- FF_18: FD1S3DX
+ FF_26: FD1S3DX
port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
- FF_17: FD1S3DX
+ FF_25: FD1S3DX
port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
Q=>w_gcount_r20);
- FF_16: FD1S3DX
+ FF_24: FD1S3DX
port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
Q=>w_gcount_r21);
- FF_15: FD1S3DX
+ FF_23: FD1S3DX
port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
Q=>w_gcount_r22);
- FF_14: FD1S3DX
+ FF_22: FD1S3DX
port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
Q=>w_gcount_r23);
- FF_13: FD1S3DX
+ FF_21: FD1S3DX
port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
Q=>w_gcount_r24);
- FF_12: FD1S3DX
+ FF_20: FD1S3DX
port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
Q=>w_gcount_r25);
- FF_11: FD1S3DX
+ FF_19: FD1S3DX
port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
Q=>w_gcount_r26);
- FF_10: FD1S3DX
+ FF_18: FD1S3DX
port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
Q=>w_gcount_r27);
- FF_9: FD1S3DX
+ FF_17: FD1S3DX
port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
Q=>w_gcount_r28);
- FF_8: FD1S3DX
+ FF_16: FD1S3DX
port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
- FF_7: FD1S3DX
+ FF_15: FD1S3DX
port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
- FF_6: FD1S3DX
+ FF_14: FD1S3DX
port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
- FF_5: FD1S3DX
+ FF_13: FD1S3DX
port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
- FF_4: FD1S3DX
+ FF_12: FD1S3DX
port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
- FF_3: FD1S3DX
+ FF_11: FD1S3DX
port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
- FF_2: FD1S3DX
+ FF_10: FD1S3DX
port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
- FF_1: FD1S3BX
+ FF_9: FD1S3DX
+ port map (D=>rcnt_sub_0, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_0);
+
+ FF_8: FD1S3DX
+ port map (D=>rcnt_sub_1, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_1);
+
+ FF_7: FD1S3DX
+ port map (D=>rcnt_sub_2, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_2);
+
+ FF_6: FD1S3DX
+ port map (D=>rcnt_sub_3, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_3);
+
+ FF_5: FD1S3DX
+ port map (D=>rcnt_sub_4, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_4);
+
+ FF_4: FD1S3DX
+ port map (D=>rcnt_sub_5, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_5);
+
+ FF_3: FD1S3DX
+ port map (D=>rcnt_sub_6, CK=>RdClock, CD=>rRst, Q=>rcnt_reg_6);
+
+ FF_2: FD1S3BX
port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
- FF_0: FD1S3DX
+ FF_1: FD1S3DX
port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+ FF_0: FD1S3BX
+ port map (D=>ae_d, CK=>RdClock, PD=>rRst, Q=>AlmostEmpty);
+
w_gctr_cia: FADD2B
port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
port map (CI=>co3, PC0=>wcount_8, PC1=>scuba_vlo, CO=>co4,
NC0=>iwcount_8, NC1=>open);
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
r_gctr_cia: FADD2B
port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
port map (CI=>co2_1, PC0=>rcount_6, PC1=>scuba_vlo, CO=>co3_1,
NC0=>ircount_6, NC1=>open);
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ rcnt_0: FSUB2B
+ port map (A0=>scuba_vhi, A1=>wcount_r2, B0=>scuba_vlo,
+ B1=>rcount_0, BI=>scuba_vlo, BOUT=>co0_2, S0=>open,
+ S1=>rcnt_sub_0);
+
+ rcnt_1: FSUB2B
+ port map (A0=>wcount_r3, A1=>wcount_r4, B0=>rcount_1,
+ B1=>rcount_2, BI=>co0_2, BOUT=>co1_2, S0=>rcnt_sub_1,
+ S1=>rcnt_sub_2);
+
+ rcnt_2: FSUB2B
+ port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r6, B0=>rcount_3,
+ B1=>rcount_4, BI=>co1_2, BOUT=>co2_2, S0=>rcnt_sub_3,
+ S1=>rcnt_sub_4);
+
+ rcnt_3: FSUB2B
+ port map (A0=>wcount_r7, A1=>rcnt_sub_msb, B0=>rcount_5,
+ B1=>scuba_vlo, BI=>co2_2, BOUT=>co3_2, S0=>rcnt_sub_5,
+ S1=>rcnt_sub_6);
+
+ rcntd: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co3_2, COUT=>open, S0=>co3_2d, S1=>open);
+
empty_cmp_ci_a: FADD2B
port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
empty_cmp_0: AGEB2
port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r2,
- B1=>wcount_r3, CI=>cmp_ci, GE=>co0_2);
+ B1=>wcount_r3, CI=>cmp_ci, GE=>co0_3);
empty_cmp_1: AGEB2
port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r4,
- B1=>w_g2b_xor_cluster_0, CI=>co0_2, GE=>co1_2);
+ B1=>w_g2b_xor_cluster_0, CI=>co0_3, GE=>co1_3);
empty_cmp_2: AGEB2
port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r6,
- B1=>wcount_r7, CI=>co1_2, GE=>co2_2);
+ B1=>wcount_r7, CI=>co1_3, GE=>co2_3);
empty_cmp_3: AGEB2
port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
- B1=>scuba_vlo, CI=>co2_2, GE=>empty_d_c);
+ B1=>scuba_vlo, CI=>co2_3, GE=>empty_d_c);
a0: FADD2B
port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
full_cmp_0: AGEB2
port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>cmp_ci_1, GE=>co0_3);
+ B1=>scuba_vlo, CI=>cmp_ci_1, GE=>co0_4);
full_cmp_1: AGEB2
port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w0,
- B1=>rcount_w1, CI=>co0_3, GE=>co1_3);
+ B1=>rcount_w1, CI=>co0_4, GE=>co1_4);
full_cmp_2: AGEB2
port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w2,
- B1=>r_g2b_xor_cluster_0, CI=>co1_3, GE=>co2_3);
+ B1=>r_g2b_xor_cluster_0, CI=>co1_4, GE=>co2_4);
full_cmp_3: AGEB2
port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co2_3, GE=>co3_2);
+ B1=>rcount_w5, CI=>co2_4, GE=>co3_3);
full_cmp_4: AGEB2
port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr,
- B1=>scuba_vlo, CI=>co3_2, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
+ B1=>scuba_vlo, CI=>co3_3, GE=>full_d_c);
a1: FADD2B
port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
S1=>open);
+ ae_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
+ CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open);
+
+ ae_cmp_0: AGEB2
+ port map (A0=>AmEmptyThresh(0), A1=>AmEmptyThresh(1),
+ B0=>rcnt_reg_0, B1=>rcnt_reg_1, CI=>cmp_ci_2, GE=>co0_5);
+
+ ae_cmp_1: AGEB2
+ port map (A0=>AmEmptyThresh(2), A1=>AmEmptyThresh(3),
+ B0=>rcnt_reg_2, B1=>rcnt_reg_3, CI=>co0_5, GE=>co1_5);
+
+ ae_cmp_2: AGEB2
+ port map (A0=>AmEmptyThresh(4), A1=>AmEmptyThresh(5),
+ B0=>rcnt_reg_4, B1=>rcnt_reg_5, CI=>co1_5, GE=>co2_5);
+
+ ae_cmp_3: AGEB2
+ port map (A0=>ae_setsig, A1=>scuba_vlo, B0=>ae_clrsig,
+ B1=>scuba_vlo, CI=>co2_5, GE=>ae_d_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a2: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>ae_d_c, COUT=>open, S0=>ae_d, S1=>open);
+
Empty <= empty_i;
Full <= full_i;
end Structure;
-- synopsys translate_off
library ecp3;
-configuration Structure_CON of fifo_dc_9to36 is
+configuration Structure_CON of fifo_dc_9to36_dyn is
for Structure
for all:AGEB2 use entity ecp3.AGEB2(V); end for;
for all:AND2 use entity ecp3.AND2(V); end for;
for all:CU2 use entity ecp3.CU2(V); end for;
for all:FADD2B use entity ecp3.FADD2B(V); end for;
+ for all:FSUB2B use entity ecp3.FSUB2B(V); end for;
for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
jspc29 / trb3.git / commitdiff