add input for automatic settings from flash to hub base

diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd
index ded5c7ddf1a33eeb5204501d1e9edf76b8889968..ef5519d73476e06cc41a135e29c624b94e9fa888 100644 (file)
--- a/trb_net16_hub_base.vhd
+++ b/trb_net16_hub_base.vhd
@@ -106,6 +106,10 @@ entity trb_net16_hub_base is
     TIMER_TICKS_OUT              : out std_logic_vector(1 downto 0);
     HUB_LED_OUT                  : out std_logic_vector (MII_NUMBER-1 downto 0);
     UNIQUE_ID_OUT                : out std_logic_vector (63 downto 0);
+    --Data port - external master (e.g. Flash or Debug)
+    BUS_MASTER_IN                : out CTRLBUS_TX;
+    BUS_MASTER_OUT               : in  CTRLBUS_RX := (data => (others => '0'), addr => (others => '0'), write => '0', read => '0', timeout => '0');
+    BUS_MASTER_ACTIVE            : in  std_logic := '0';
     --Fixed status and control ports
     HUB_STAT_CHANNEL             : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
     HUB_STAT_GEN                 : out std_logic_vector (31 downto 0);
@@ -264,6 +268,11 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is
   signal DAT_UNKNOWN_ADDR_IN     : std_logic := '0';
   signal DAT_TIMEOUT_OUT         : std_logic;
 
+  signal handlerbus_data_in  : std_logic_vector(31 downto 0);
+  signal handlerbus_write    : std_logic;
+  signal handlerbus_read     : std_logic;
+  signal handlerbus_addr_in  : std_logic_vector(15 downto 0);  
+  
   signal STAT_TIMEOUT            : std_logic_vector(4*32-1 downto 0);
   signal last_STAT_TIMEOUT       : std_logic_vector(4*32-1 downto 0);
 
@@ -1128,7 +1137,16 @@ end generate;
       DAT_WRITE_ACK_IN    => DAT_WRITE_ACK_IN
       );
 
-
+     
+  handlerbus_addr_in <= DAT_ADDR_OUT             when BUS_MASTER_ACTIVE = '0' else BUS_MASTER_OUT.addr;
+  handlerbus_data_in <= DAT_DATA_OUT             when BUS_MASTER_ACTIVE = '0' else BUS_MASTER_OUT.data;
+  handlerbus_write   <= DAT_WRITE_ENABLE_OUT     when BUS_MASTER_ACTIVE = '0' else BUS_MASTER_OUT.write;
+  handlerbus_read    <= DAT_READ_ENABLE_OUT      when BUS_MASTER_ACTIVE = '0' else BUS_MASTER_OUT.read;
+  BUS_MASTER_IN.ack     <= DAT_DATAREADY_IN or DAT_WRITE_ACK_IN;
+  BUS_MASTER_IN.nack    <= DAT_NO_MORE_DATA_IN;
+  BUS_MASTER_IN.unknown <= DAT_UNKNOWN_ADDR_IN;
+  
+  
 --Fucking Modelsim wants it like this...
 THE_BUS_HANDLER : trb_net16_regio_bus_handler
   generic map(
@@ -1141,11 +1159,11 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler
     CLK                          => CLK,
     RESET                        => reset_i,
 
-    DAT_ADDR_IN                  => DAT_ADDR_OUT,
-    DAT_DATA_IN                  => DAT_DATA_OUT,
+    DAT_ADDR_IN                  => handlerbus_addr_in,
+    DAT_DATA_IN                  => handlerbus_data_in,
     DAT_DATA_OUT                 => DAT_DATA_IN,
-    DAT_READ_ENABLE_IN           => DAT_READ_ENABLE_OUT,
-    DAT_WRITE_ENABLE_IN          => DAT_WRITE_ENABLE_OUT,
+    DAT_READ_ENABLE_IN           => handlerbus_read,
+    DAT_WRITE_ENABLE_IN          => handlerbus_write,
     DAT_TIMEOUT_IN               => DAT_TIMEOUT_OUT,
     DAT_DATAREADY_OUT            => DAT_DATAREADY_IN,
     DAT_WRITE_ACK_OUT            => DAT_WRITE_ACK_IN,

diff --git a/trb_net16_hub_func.vhd b/trb_net16_hub_func.vhd
index ac82c277a7a4614516a31d042523070f3fc7eaaf..fe8ffd57eced3c11be2980e97a72a1174c19e015 100644 (file)
--- a/trb_net16_hub_func.vhd
+++ b/trb_net16_hub_func.vhd
@@ -179,6 +179,10 @@ package trb_net16_hub_func is
     MY_ADDRESS_OUT   : out std_logic_vector (15 downto 0);
     HUB_LED_OUT      : out std_logic_vector (MII_NUMBER-1 downto 0);
     UNIQUE_ID_OUT                : out std_logic_vector (63 downto 0);
+    --Data port - external master (e.g. Flash or Debug)
+    BUS_MASTER_IN                : out CTRLBUS_TX;
+    BUS_MASTER_OUT               : in  CTRLBUS_RX := (data => (others => '0'), addr => (others => '0'), write => '0', read => '0', timeout => '0');
+    BUS_MASTER_ACTIVE            : in  std_logic := '0';    
     --Fixed status and control ports
     HUB_STAT_CHANNEL      : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
     HUB_STAT_GEN          : out std_logic_vector (31 downto 0);