DBG(3 downto 0) <= dl_rx_frame_avail;
DBG(7 downto 4) <= dl_rx_frame_req;
DBG(11 downto 8) <= dl_rx_frame_ack;
- DBG(19 downto 12) <= ul_rx_data(7 downto 0);
+ DBG(15 downto 12) <= ul_rx_data(3 downto 0);
+ DBG(19 downto 16) <= dl_rx_data(0)(3 downto 0);
DBG(20) <= ul_rx_frame_avail;
DBG(21) <= ul_rx_frame_req;
DBG(22) <= ul_rx_frame_ack;
DBG(23) <= dl_rx_data(0)(9);
- DBG(31 downto 24) <= dl_rx_data(0)(7 downto 0);
+ DBG(31 downto 24) <= (others => '0');
DBG(32) <= dl_rx_data(0)(8);
DBG(33) <= clk_sys;
---------------------------------------------------------------------------
GBE : entity work.gbe_wrapper_fifo
generic map(
- DO_SIMULATION => 0,
- INCLUDE_DEBUG => 0,
- USE_INTERNAL_TRBNET_DUMMY => 0,
- USE_EXTERNAL_TRBNET_DUMMY => 0,
- RX_PATH_ENABLE => 1,
- FIXED_SIZE_MODE => 1,
- INCREMENTAL_MODE => 1,
- FIXED_SIZE => 100,
- FIXED_DELAY_MODE => 1,
- UP_DOWN_MODE => 0,
- UP_DOWN_LIMIT => 100,
- FIXED_DELAY => 100,
-
LINK_HAS_READOUT => '0',
LINK_HAS_SLOWCTRL => '1',
LINK_HAS_DHCP => '1',
LINK_HAS_FWD => '0'
)
port map(
- CLK_SYS_IN => clk_sys,
CLK_125_IN => clk_sys,
RESET => reset_i,
GSR_N => reset_n_i,