$feat .= ", single Fifo" if $d->{$addr}&0x1000;
$feat .= ", indiv. Fifos" unless $d->{$addr}&0x1000;
}
- for($inclHigh->{$addr}>>16&0xF) {
- when(1) {$feat .="\nTrigger Module: simple or";}
- when(2) {$feat .="\nTrigger Module: edge detect";}
+
+ if(($inclHigh->{$addr}>>16&0xF) == 1 || ($inclHigh->{$addr}>>16&0xF) == 2) {
+ for($inclHigh->{$addr}>>16&0xF) {
+ when(1) {$feat .="\nTrigger Module: simple or";}
+ when(2) {$feat .="\nTrigger Module: edge detect";}
+ }
+ my $d = trb_register_read($addr,0xcf27);
+ $feat .= sprintf(", %i inputs, %i outputs",($d->{$addr}&0x3F),($d->{$addr}>>8&0xF));
}
for($inclHigh->{$addr}>>20&0xF) {
when(0) {$feat .="\nClock: on-board 200 MHz";}
<description>Inverts individual inputs for trigger generation.</description>
<field name="TriggerInvert" start="0" bits="32" format="bitmask" />
</register>
+ <register name="TriggerCoincidence1" address="0025" mode="rw" >
+ <description>Enable input to be used in coincidence logic. First group of signals or'ed. At least one of the inputs to each group must fire within 40 ns to get a coincidence.</description>
+ <field name="TriggerCoincidence1" start="0" bits="32" format="bitmask" />
+ </register>
+ <register name="TriggerCoincidence2" address="0026" mode="rw" >
+ <description>Enable input to be used in coincidence logic. Second group of signals or'ed. At least one of the inputs to each group must fire within 40 ns to get a coincidence.</description>
+ <field name="TriggerCoincidence2" start="0" bits="32" format="bitmask" />
+ </register>
+ <register name="TriggerConfig" address="0027" mode="r" >
+ <description>Information about configuration.</description>
+ <field name="TriggerInputs" start="0" bits="6" format="unsigned" noflag="true">
+ <description>Number of inputs to the trigger logic</description>
+ </field>
+ <field name="TriggerOutputs" start="8" bits="4" format="unsigned" noflag="true">
+ <description>Number of outputs of the trigger logic</description>
+ </field>
+ </register>
</group>
</TrbNetEntity>
-
-