Updatine ADC AddOn with debug bus

diff --git a/adcaddon/par.p2t b/adcaddon/par.p2t
index e13de7d3bc0ff44031b14779d63570f31cfb8825..90214e9859de82127d5898f8ad23cc42560f494e 100644 (file)
--- a/adcaddon/par.p2t
+++ b/adcaddon/par.p2t
@@ -1,21 +1,9 @@
 -w
 -i 15
 -l 5
--n 1
 -y
 -s 12
--t 25
+-t 32
 -c 1
 -e 2
-#-g guidefile.ncd
-#-m nodelist.txt
-# -w
-# -i 6
-# -l 5
-# -n 1
-# -t 1
-# -s 1
-# -c 0
-# -e 0
-#
 -exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1

diff --git a/adcaddon/trb3_periph_adc_constraints.lpf b/adcaddon/trb3_periph_adc_constraints.lpf
index dd0786bb34fbadf88dfe0444461cb41e9e54fcb8..c54389be3c5dd8e7160b295a3644912038cb1e79 100644 (file)
--- a/adcaddon/trb3_periph_adc_constraints.lpf
+++ b/adcaddon/trb3_periph_adc_constraints.lpf
@@ -47,5 +47,8 @@ INPUT_SETUP ALLPORTS 1.5 ns HOLD 1.5 ns CLKPORT ADC_DCO_12;
 #USE PRIMARY NET "CLK_GPLL_RIGHT_c";
 #USE PRIMARY NET "CLK_PCLK_LEFT_c";
 
-USE PRIMARY NET "CLK_CORE_PCLK";
-USE PRIMARY NET "CLK_EXT_PCLK";
\ No newline at end of file
+USE PRIMARY NET "CLK_CORE_PCLK_c";
+USE PRIMARY NET "CLK_EXT_PCLK";
+
+# USE PRIMARY2EDGE NET gen_reallogic.THE_ADC/THE_ADC_RIGHT/clk_adcfast_i ;
+# USE PRIMARY2EDGE NET gen_reallogic.THE_ADC/THE_ADC_LEFT/clk_adcfast_i;
\ No newline at end of file

diff --git a/adcaddon/trb3sc_adc.prj b/adcaddon/trb3sc_adc.prj
index 5d27da07e101eebce7d6a483c99753d2b232038f..68d405a262ffa9a255372a048544b1ccc583200f 100644 (file)
--- a/adcaddon/trb3sc_adc.prj
+++ b/adcaddon/trb3sc_adc.prj
@@ -110,7 +110,7 @@ add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
-add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd"
 add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd"
 
 #SlowControl files

diff --git a/adcaddon/trb3sc_adc.vhd b/adcaddon/trb3sc_adc.vhd
index 1b4e31936ddeccf9161d63111f65709bcb8eb91e..15602f2706e400f4f4f65da477fe6fd4a6f1c983 100644 (file)
--- a/adcaddon/trb3sc_adc.vhd
+++ b/adcaddon/trb3sc_adc.vhd
@@ -144,7 +144,7 @@ architecture trb3sc_adc_arch of trb3sc_adc is
   signal readout_rx        : READOUT_RX;
   signal readout_tx        : readout_tx_array_t(0 to 11);
 
-  signal ctrlbus_rx, bussci_rx, bustools_rx, bustc_rx, busadc_rx, bus_master_out, handlerbus_rx  : CTRLBUS_RX;
+  signal ctrlbus_rx, bussci_rx, bustools_rx, bustc_rx, busadc_rx, bus_master_out  : CTRLBUS_RX;
   signal ctrlbus_tx, bussci_tx, bustools_tx, bustc_tx, busadc_tx, bus_master_in   : CTRLBUS_TX;
   
   signal common_stat_reg   : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
@@ -222,8 +222,6 @@ THE_CLOCK_RESET :  entity work.clock_reset_handler
       TX_DLM_WORD => open,
 
       --SFP Connection
-      SD_REFCLK_P_IN => '0',
-      SD_REFCLK_N_IN => '0',
       SD_PRSNT_N_IN  => sfp_prsnt_i,
       SD_LOS_IN      => sfp_los_i,
       SD_TXDIS_OUT   => sfp_txdis_i,
@@ -282,7 +280,9 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record
     REGIO_COMMON_CTRL_REG_OUT    => common_ctrl_reg,  --0x20
     BUS_RX                       => ctrlbus_rx,
     BUS_TX                       => ctrlbus_tx,
-
+    BUS_MASTER_IN                => bus_master_in,
+    BUS_MASTER_OUT               => bus_master_out,
+    BUS_MASTER_ACTIVE            => bus_master_active,   
     ONEWIRE_INOUT                => TEMPSENS,
     --Timing registers
     TIMERS_OUT                   => timer
@@ -357,8 +357,6 @@ end generate;
 -- Bus Handler
 ---------------------------------------------------------------------------
 
-  handlerbus_rx <= ctrlbus_rx when bus_master_active = '0' else bus_master_out;
-
   THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
     generic map(
       PORT_NUMBER      => 4,
@@ -370,7 +368,7 @@ end generate;
       CLK   => clk_sys,
       RESET => reset_i,
 
-      REGIO_RX  => handlerbus_rx,
+      REGIO_RX  => ctrlbus_rx,
       REGIO_TX  => ctrlbus_tx,
       
       BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED
@@ -421,7 +419,7 @@ end generate;
       BUS_RX     => bustools_rx,
       BUS_TX     => bustools_tx,
       --Control master for default settings
-      BUS_MASTER_IN  => ctrlbus_tx,
+      BUS_MASTER_IN  => bus_master_in,
       BUS_MASTER_OUT => bus_master_out,
       BUS_MASTER_ACTIVE => bus_master_active,      
       DEBUG_OUT  => open