TABs removed

diff --git a/special/trb_net_reset_handler.vhd b/special/trb_net_reset_handler.vhd
index fcb852457604f1daa3b2fe65a82638e393b52e71..694a102a8b0ef2b6ab663fe79323e87a89ab49cd 100644 (file)
--- a/special/trb_net_reset_handler.vhd
+++ b/special/trb_net_reset_handler.vhd
@@ -5,22 +5,21 @@ use ieee.std_logic_unsigned.all;
 \r
 library work;\r
 \r
-\r
 entity trb_net_reset_handler is\r
-generic(\r
-       RESET_DELAY     : std_logic_vector(15 downto 0) := x"1fff"\r
-);\r
+  generic(\r
+    RESET_DELAY     : std_logic_vector(15 downto 0) := x"1fff"\r
+  );\r
 port(\r
-       CLEAR_IN        : in    std_logic; -- reset input (high active, async)\r
-       CLEAR_N_IN      : in    std_logic; -- reset input (low active, async)\r
-       CLK_IN          : in    std_logic; -- raw master clock, NOT from PLL/DLL!\r
-       SYSCLK_IN       : in    std_logic; -- PLL/DLL remastered clock\r
-       PLL_LOCKED_IN   : in    std_logic; -- master PLL lock signal (async)\r
-       RESET_IN        : in    std_logic; -- general reset signal (SYSCLK)\r
-       TRB_RESET_IN    : in    std_logic; -- TRBnet reset signal (SYSCLK)\r
-       CLEAR_OUT       : out   std_logic; -- async reset out, USE WITH CARE!\r
-       RESET_OUT       : out   std_logic; -- synchronous reset out (SYSCLK)\r
-       DEBUG_OUT       : out   std_logic_vector(15 downto 0)\r
+  CLEAR_IN        : in    std_logic; -- reset input (high active, async)\r
+  CLEAR_N_IN      : in    std_logic; -- reset input (low active, async)\r
+  CLK_IN          : in    std_logic; -- raw master clock, NOT from PLL/DLL!\r
+  SYSCLK_IN       : in    std_logic; -- PLL/DLL remastered clock\r
+  PLL_LOCKED_IN   : in    std_logic; -- master PLL lock signal (async)\r
+  RESET_IN        : in    std_logic; -- general reset signal (SYSCLK)\r
+  TRB_RESET_IN    : in    std_logic; -- TRBnet reset signal (SYSCLK)\r
+  CLEAR_OUT       : out   std_logic; -- async reset out, USE WITH CARE!\r
+  RESET_OUT       : out   std_logic; -- synchronous reset out (SYSCLK)\r
+  DEBUG_OUT       : out   std_logic_vector(15 downto 0)\r
 );\r
 end;\r
 \r
@@ -70,10 +69,10 @@ comb_async_rst_n <= not clear_in and clear_n_in and pll_locked_in;
 ----------------------------------------------------------------\r
 THE_ASYNC_SAMPLER_PROC: process( clk_in )\r
 begin\r
-       if( rising_edge(clk_in) ) then\r
-               async_sampler(7 downto 0) <= async_sampler(6 downto 0) & comb_async_rst_n;\r
-               async_pulse               <= comb_async_pulse;\r
-       end if;\r
+  if( rising_edge(clk_in) ) then\r
+    async_sampler(7 downto 0) <= async_sampler(6 downto 0) & comb_async_rst_n;\r
+    async_pulse               <= comb_async_pulse;\r
+  end if;\r
 end process THE_ASYNC_SAMPLER_PROC;\r
 \r
 -- first two registers are clock domain transfer registers!\r
@@ -84,19 +83,19 @@ comb_async_pulse <= '1' when ( async_sampler(7 downto 2) = b"0000_00" ) else '0'
 ----------------------------------------------------------------\r
 THE_SYNC_PROC: process( sysclk_in )\r
 begin\r
-       if( rising_edge(sysclk_in) ) then\r
-               reset_buffer     <= RESET_IN;      -- not really needed, but relaxes timing\r
-               trb_reset_buffer <= TRB_RESET_IN;  -- not really needed, but relaxes timing\r
-               final_reset      <= final_reset(0) & reset;\r
-       end if;\r
+  if( rising_edge(sysclk_in) ) then\r
+    reset_buffer     <= RESET_IN;      -- not really needed, but relaxes timing\r
+    trb_reset_buffer <= TRB_RESET_IN;  -- not really needed, but relaxes timing\r
+    final_reset      <= final_reset(0) & reset;\r
+  end if;\r
 end process THE_SYNC_PROC;\r
 \r
 THE_CROSSING_PROC: process( clk_in )\r
 begin\r
-       if( rising_edge(clk_in) ) then\r
-               reset_pulse      <= reset_pulse(0)     & reset_buffer;\r
-               trb_reset_pulse  <= trb_reset_pulse(0) & trb_reset_buffer;\r
-       end if;\r
+  if( rising_edge(clk_in) ) then\r
+    reset_pulse      <= reset_pulse(0)     & reset_buffer;\r
+    trb_reset_pulse  <= trb_reset_pulse(0) & trb_reset_buffer;\r
+  end if;\r
 end process THE_CROSSING_PROC;\r
 \r
 ----------------------------------------------------------------\r
@@ -104,19 +103,19 @@ end process THE_CROSSING_PROC;
 ----------------------------------------------------------------\r
 THE_GLOBAL_RESET_PROC: process( clk_in )\r
 begin\r
-       if( rising_edge(clk_in) ) then\r
-               if( (async_pulse = '1') or (reset_pulse(1) = '1') or (trb_reset_pulse(1) = '1') ) then\r
-                       reset_cnt <= (others => '0');\r
-                       reset     <= '1';\r
-               else\r
-                       reset_cnt <= reset_cnt + 1;\r
-                       reset     <= '1';\r
-                       if( reset_cnt = RESET_DELAY ) then\r
-                               reset     <= '0';\r
-                               reset_cnt <= RESET_DELAY;\r
-                       end if;\r
-               end if;\r
-       end if;\r
+  if( rising_edge(clk_in) ) then\r
+    if( (async_pulse = '1') or (reset_pulse(1) = '1') or (trb_reset_pulse(1) = '1') ) then\r
+      reset_cnt <= (others => '0');\r
+      reset     <= '1';\r
+    else\r
+      reset_cnt <= reset_cnt + 1;\r
+      reset     <= '1';\r
+      if( reset_cnt = RESET_DELAY ) then\r
+        reset     <= '0';\r
+        reset_cnt <= RESET_DELAY;\r
+      end if;\r
+    end if;\r
+  end if;\r
 end process THE_GLOBAL_RESET_PROC;\r
 \r
 ----------------------------------------------------------------\r