*** empty log message ***

diff --git a/lattice/scm/lattice_scm_fifo_18x16_tmpl.vhd b/lattice/scm/lattice_scm_fifo_18x16_tmpl.vhd
new file mode 100644 (file)
index 0000000..c06882b
--- /dev/null
+++ b/lattice/scm/lattice_scm_fifo_18x16_tmpl.vhd
@@ -0,0 +1,18 @@
+-- VHDL module instantiation generated by SCUBA ispLever_v70_Prod_Build (55)
+-- Module  Version: 4.2
+-- Fri Feb  8 13:39:45 2008
+
+-- parameterized module component declaration
+component lattice_scm_fifo_18x16
+    port (Data: in  std_logic_vector(17 downto 0); 
+        WrClock: in  std_logic; RdClock: in  std_logic; 
+        WrEn: in  std_logic; RdEn: in  std_logic; Reset: in  std_logic; 
+        RPReset: in  std_logic; Q: out  std_logic_vector(17 downto 0); 
+        Empty: out  std_logic; Full: out  std_logic);
+end component;
+
+-- parameterized module component instance
+__ : lattice_scm_fifo_18x16
+    port map (Data(17 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, 
+        RdEn=>__, Reset=>__, RPReset=>__, Q(17 downto 0)=>__, Empty=>__, 
+        Full=>__);

diff --git a/lattice/scm/lattice_scm_fifo_18x1k_tmpl.vhd b/lattice/scm/lattice_scm_fifo_18x1k_tmpl.vhd
new file mode 100644 (file)
index 0000000..ab8b412
--- /dev/null
+++ b/lattice/scm/lattice_scm_fifo_18x1k_tmpl.vhd
@@ -0,0 +1,19 @@
+-- VHDL module instantiation generated by SCUBA ispLever_v70_Prod_Build (55)
+-- Module  Version: 4.2
+-- Fri Feb  8 13:39:06 2008
+
+-- parameterized module component declaration
+component lattice_scm_fifo_18x1k
+    port (Data: in  std_logic_vector(17 downto 0); 
+        WrClock: in  std_logic; RdClock: in  std_logic; 
+        WrEn: in  std_logic; RdEn: in  std_logic; Reset: in  std_logic; 
+        RPReset: in  std_logic; Q: out  std_logic_vector(17 downto 0); 
+        Empty: out  std_logic; Full: out  std_logic; 
+        AlmostEmpty: out  std_logic; AlmostFull: out  std_logic);
+end component;
+
+-- parameterized module component instance
+__ : lattice_scm_fifo_18x1k
+    port map (Data(17 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, 
+        RdEn=>__, Reset=>__, RPReset=>__, Q(17 downto 0)=>__, Empty=>__, 
+        Full=>__, AlmostEmpty=>__, AlmostFull=>__);

diff --git a/lattice/scm/lattice_scm_fifo_18x32_tmpl.vhd b/lattice/scm/lattice_scm_fifo_18x32_tmpl.vhd
new file mode 100644 (file)
index 0000000..95f6500
--- /dev/null
+++ b/lattice/scm/lattice_scm_fifo_18x32_tmpl.vhd
@@ -0,0 +1,18 @@
+-- VHDL module instantiation generated by SCUBA ispLever_v70_Prod_Build (55)
+-- Module  Version: 4.2
+-- Fri Feb  8 13:40:11 2008
+
+-- parameterized module component declaration
+component lattice_scm_fifo_18x32
+    port (Data: in  std_logic_vector(17 downto 0); 
+        WrClock: in  std_logic; RdClock: in  std_logic; 
+        WrEn: in  std_logic; RdEn: in  std_logic; Reset: in  std_logic; 
+        RPReset: in  std_logic; Q: out  std_logic_vector(17 downto 0); 
+        Empty: out  std_logic; Full: out  std_logic);
+end component;
+
+-- parameterized module component instance
+__ : lattice_scm_fifo_18x32
+    port map (Data(17 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, 
+        RdEn=>__, Reset=>__, RPReset=>__, Q(17 downto 0)=>__, Empty=>__, 
+        Full=>__);

diff --git a/lattice/scm/lattice_scm_fifo_18x64_tmpl.vhd b/lattice/scm/lattice_scm_fifo_18x64_tmpl.vhd
new file mode 100644 (file)
index 0000000..623b547
--- /dev/null
+++ b/lattice/scm/lattice_scm_fifo_18x64_tmpl.vhd
@@ -0,0 +1,18 @@
+-- VHDL module instantiation generated by SCUBA ispLever_v70_Prod_Build (55)
+-- Module  Version: 4.2
+-- Fri Feb  8 13:40:40 2008
+
+-- parameterized module component declaration
+component lattice_scm_fifo_18x64
+    port (Data: in  std_logic_vector(17 downto 0); 
+        WrClock: in  std_logic; RdClock: in  std_logic; 
+        WrEn: in  std_logic; RdEn: in  std_logic; Reset: in  std_logic; 
+        RPReset: in  std_logic; Q: out  std_logic_vector(17 downto 0); 
+        Empty: out  std_logic; Full: out  std_logic);
+end component;
+
+-- parameterized module component instance
+__ : lattice_scm_fifo_18x64
+    port map (Data(17 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, 
+        RdEn=>__, Reset=>__, RPReset=>__, Q(17 downto 0)=>__, Empty=>__, 
+        Full=>__);