-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41)
-- Module Version: 4.7
---/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 16384 -width 36 -depth 16384 -regout -no_enable -pe -1 -pf 0 -fill -e
+--/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 16384 -width 36 -depth 16384 -regout -no_enable -pe -1 -pf 0 -fill -e
-- Wed Mar 31 11:45:33 2010
entity fifo_36x16k_oreg is
port (
- Data: in std_logic_vector(35 downto 0);
- Clock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- AmFullThresh: in std_logic_vector(13 downto 0);
- Q: out std_logic_vector(35 downto 0);
- WCNT: out std_logic_vector(14 downto 0);
- Empty: out std_logic;
- Full: out std_logic;
+ Data: in std_logic_vector(35 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ AmFullThresh: in std_logic_vector(13 downto 0);
+ Q: out std_logic_vector(35 downto 0);
+ WCNT: out std_logic_vector(14 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
AlmostFull: out std_logic);
end fifo_36x16k_oreg;
-- local component declarations
component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
B1: in std_logic; CI: in std_logic; GE: out std_logic);
end component;
component ALEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
B1: in std_logic; CI: in std_logic; LE: out std_logic);
end component;
component AND2
port (A: in std_logic; B: in std_logic; Z: out std_logic);
end component;
component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
end component;
component CB2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CON: in std_logic; CO: out std_logic; NC0: out std_logic;
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CON: in std_logic; CO: out std_logic; NC0: out std_logic;
NC1: out std_logic);
end component;
component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
S0: out std_logic; S1: out std_logic);
end component;
component FSUB2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; BI: in std_logic; BOUT: out std_logic;
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; BI: in std_logic; BOUT: out std_logic;
S0: out std_logic; S1: out std_logic);
end component;
component FD1P3BX
-- synopsys translate_off
generic (GSR : in String);
-- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
PD: in std_logic; Q: out std_logic);
end component;
component FD1P3DX
-- synopsys translate_off
generic (GSR : in String);
-- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
CD: in std_logic; Q: out std_logic);
end component;
component FD1S3BX
-- synopsys translate_off
generic (GSR : in String);
-- synopsys translate_on
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
Q: out std_logic);
end component;
component FD1S3DX
-- synopsys translate_off
generic (GSR : in String);
-- synopsys translate_on
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
Q: out std_logic);
end component;
component INV
port (A: in std_logic; Z: out std_logic);
end component;
component MUX81
- port (D0: in std_logic; D1: in std_logic; D2: in std_logic;
- D3: in std_logic; D4: in std_logic; D5: in std_logic;
- D6: in std_logic; D7: in std_logic; SD1: in std_logic;
+ port (D0: in std_logic; D1: in std_logic; D2: in std_logic;
+ D3: in std_logic; D4: in std_logic; D5: in std_logic;
+ D6: in std_logic; D7: in std_logic; SD1: in std_logic;
SD2: in std_logic; SD3: in std_logic; Z: out std_logic);
end component;
component ROM16X1
-- synopsys translate_off
generic (initval : in String);
-- synopsys translate_on
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
AD0: in std_logic; DO0: out std_logic);
end component;
component VHI
end component;
component DP16KB
-- synopsys translate_off
- generic (GSR : in String; WRITEMODE_B : in String;
- CSDECODE_B : in std_logic_vector(2 downto 0);
- CSDECODE_A : in std_logic_vector(2 downto 0);
- WRITEMODE_A : in String; RESETMODE : in String;
- REGMODE_B : in String; REGMODE_A : in String;
+ generic (GSR : in String; WRITEMODE_B : in String;
+ CSDECODE_B : in std_logic_vector(2 downto 0);
+ CSDECODE_A : in std_logic_vector(2 downto 0);
+ WRITEMODE_A : in String; RESETMODE : in String;
+ REGMODE_B : in String; REGMODE_A : in String;
DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
-- synopsys translate_on
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
- CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
- CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
+ port (DIA0: in std_logic; DIA1: in std_logic;
+ DIA2: in std_logic; DIA3: in std_logic;
+ DIA4: in std_logic; DIA5: in std_logic;
+ DIA6: in std_logic; DIA7: in std_logic;
+ DIA8: in std_logic; DIA9: in std_logic;
+ DIA10: in std_logic; DIA11: in std_logic;
+ DIA12: in std_logic; DIA13: in std_logic;
+ DIA14: in std_logic; DIA15: in std_logic;
+ DIA16: in std_logic; DIA17: in std_logic;
+ ADA0: in std_logic; ADA1: in std_logic;
+ ADA2: in std_logic; ADA3: in std_logic;
+ ADA4: in std_logic; ADA5: in std_logic;
+ ADA6: in std_logic; ADA7: in std_logic;
+ ADA8: in std_logic; ADA9: in std_logic;
+ ADA10: in std_logic; ADA11: in std_logic;
+ ADA12: in std_logic; ADA13: in std_logic;
+ CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
+ CSA0: in std_logic; CSA1: in std_logic;
+ CSA2: in std_logic; RSTA: in std_logic;
+ DIB0: in std_logic; DIB1: in std_logic;
+ DIB2: in std_logic; DIB3: in std_logic;
+ DIB4: in std_logic; DIB5: in std_logic;
+ DIB6: in std_logic; DIB7: in std_logic;
+ DIB8: in std_logic; DIB9: in std_logic;
+ DIB10: in std_logic; DIB11: in std_logic;
+ DIB12: in std_logic; DIB13: in std_logic;
+ DIB14: in std_logic; DIB15: in std_logic;
+ DIB16: in std_logic; DIB17: in std_logic;
+ ADB0: in std_logic; ADB1: in std_logic;
+ ADB2: in std_logic; ADB3: in std_logic;
+ ADB4: in std_logic; ADB5: in std_logic;
+ ADB6: in std_logic; ADB7: in std_logic;
+ ADB8: in std_logic; ADB9: in std_logic;
+ ADB10: in std_logic; ADB11: in std_logic;
+ ADB12: in std_logic; ADB13: in std_logic;
+ CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
+ CSB0: in std_logic; CSB1: in std_logic;
+ CSB2: in std_logic; RSTB: in std_logic;
+ DOA0: out std_logic; DOA1: out std_logic;
+ DOA2: out std_logic; DOA3: out std_logic;
+ DOA4: out std_logic; DOA5: out std_logic;
+ DOA6: out std_logic; DOA7: out std_logic;
+ DOA8: out std_logic; DOA9: out std_logic;
+ DOA10: out std_logic; DOA11: out std_logic;
+ DOA12: out std_logic; DOA13: out std_logic;
+ DOA14: out std_logic; DOA15: out std_logic;
+ DOA16: out std_logic; DOA17: out std_logic;
+ DOB0: out std_logic; DOB1: out std_logic;
+ DOB2: out std_logic; DOB3: out std_logic;
+ DOB4: out std_logic; DOB5: out std_logic;
+ DOB6: out std_logic; DOB7: out std_logic;
+ DOB8: out std_logic; DOB9: out std_logic;
+ DOB10: out std_logic; DOB11: out std_logic;
+ DOB12: out std_logic; DOB13: out std_logic;
+ DOB14: out std_logic; DOB15: out std_logic;
DOB16: out std_logic; DOB17: out std_logic);
end component;
- attribute initval : string;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute CSDECODE_B : string;
- attribute CSDECODE_A : string;
- attribute WRITEMODE_B : string;
- attribute WRITEMODE_A : string;
- attribute RESETMODE : string;
- attribute REGMODE_B : string;
- attribute REGMODE_A : string;
- attribute DATA_WIDTH_B : string;
- attribute DATA_WIDTH_A : string;
- attribute GSR : string;
+ attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_B : string;
+ attribute CSDECODE_A : string;
+ attribute WRITEMODE_B : string;
+ attribute WRITEMODE_A : string;
+ attribute RESETMODE : string;
+ attribute REGMODE_B : string;
+ attribute REGMODE_A : string;
+ attribute DATA_WIDTH_B : string;
+ attribute DATA_WIDTH_A : string;
+ attribute GSR : string;
attribute initval of LUT4_17 : label is "0x3232";
attribute initval of LUT4_16 : label is "0x3232";
attribute initval of LUT4_15 : label is "0xfffe";
-- synopsys translate_off
generic map (initval=> "0x3232")
-- synopsys translate_on
- port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
+ port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
AD0=>empty_i, DO0=>empty_d);
LUT4_16: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x3232")
-- synopsys translate_on
- port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
+ port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
AD0=>full_i, DO0=>full_d);
LUT4_15: ROM16X1
-- synopsys translate_off
generic map (initval=> "0xfffe")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
+ port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
AD0=>scuba_vlo, DO0=>rden_cr0);
LUT4_14: ROM16X1
-- synopsys translate_off
generic map (initval=> "0xfffe")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
+ port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
AD0=>scuba_vlo, DO0=>rden_cr0_1);
LUT4_13: ROM16X1
-- synopsys translate_off
generic map (initval=> "0xfffe")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
+ port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
AD0=>scuba_vlo, DO0=>rden_cr0_2);
LUT4_12: ROM16X1
-- synopsys translate_off
generic map (initval=> "0xfffe")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
+ port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
AD0=>scuba_vlo, DO0=>rden_cr0_3);
AND2_t17: AND2
-- synopsys translate_off
generic map (initval=> "0xfffe")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
+ port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
AD0=>scuba_vlo, DO0=>rden_cr0_8);
LUT4_10: ROM16X1
-- synopsys translate_off
generic map (initval=> "0xfffe")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
+ port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
AD0=>scuba_vlo, DO0=>rden_cr0_9);
LUT4_9: ROM16X1
-- synopsys translate_off
generic map (initval=> "0xfffe")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
+ port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
AD0=>scuba_vlo, DO0=>rden_cr0_10);
LUT4_8: ROM16X1
-- synopsys translate_off
generic map (initval=> "0xfffe")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
+ port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
AD0=>scuba_vlo, DO0=>rden_cr0_11);
AND2_t13: AND2
-- synopsys translate_off
generic map (initval=> "0xfffe")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
+ port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
AD0=>scuba_vlo, DO0=>rden_cr0_16);
LUT4_6: ROM16X1
-- synopsys translate_off
generic map (initval=> "0xfffe")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
+ port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
AD0=>scuba_vlo, DO0=>rden_cr0_17);
LUT4_5: ROM16X1
-- synopsys translate_off
generic map (initval=> "0xfffe")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
+ port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
AD0=>scuba_vlo, DO0=>rden_cr0_18);
LUT4_4: ROM16X1
-- synopsys translate_off
generic map (initval=> "0xfffe")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
+ port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
AD0=>scuba_vlo, DO0=>rden_cr0_19);
AND2_t9: AND2
-- synopsys translate_off
generic map (initval=> "0xfffe")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
+ port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
AD0=>scuba_vlo, DO0=>rden_cr0_24);
LUT4_2: ROM16X1
-- synopsys translate_off
generic map (initval=> "0xfffe")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
+ port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
AD0=>scuba_vlo, DO0=>rden_cr0_25);
LUT4_1: ROM16X1
-- synopsys translate_off
generic map (initval=> "0xfffe")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
+ port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
AD0=>scuba_vlo, DO0=>rden_cr0_26);
LUT4_0: ROM16X1
-- synopsys translate_off
generic map (initval=> "0xfffe")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
+ port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
AD0=>scuba_vlo, DO0=>rden_cr0_27);
AND2_t5: AND2
pdp_ram_0_0_31: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
- CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>rden_cr0, CSB1=>rptr_12,
- CSB2=>rptr_13, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1,
- DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4,
- DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7,
- DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>rden_cr0, CSB1=>rptr_12,
+ CSB2=>rptr_13, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1,
+ DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4,
+ DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7,
+ DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
DOB16=>open, DOB17=>open);
pdp_ram_0_1_30: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
- DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
- DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
- CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>rden_cr0_1, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_0_9, DOB1=>mdout1_0_10, DOB2=>mdout1_0_11,
- DOB3=>mdout1_0_12, DOB4=>mdout1_0_13, DOB5=>mdout1_0_14,
- DOB6=>mdout1_0_15, DOB7=>mdout1_0_16, DOB8=>mdout1_0_17,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
+ DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
+ DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rden_cr0_1, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_0_9, DOB1=>mdout1_0_10, DOB2=>mdout1_0_11,
+ DOB3=>mdout1_0_12, DOB4=>mdout1_0_13, DOB5=>mdout1_0_14,
+ DOB6=>mdout1_0_15, DOB7=>mdout1_0_16, DOB8=>mdout1_0_17,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_0_2_29: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
- DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
- DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
- CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>rden_cr0_2, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_0_18, DOB1=>mdout1_0_19, DOB2=>mdout1_0_20,
- DOB3=>mdout1_0_21, DOB4=>mdout1_0_22, DOB5=>mdout1_0_23,
- DOB6=>mdout1_0_24, DOB7=>mdout1_0_25, DOB8=>mdout1_0_26,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
+ DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
+ DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rden_cr0_2, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_0_18, DOB1=>mdout1_0_19, DOB2=>mdout1_0_20,
+ DOB3=>mdout1_0_21, DOB4=>mdout1_0_22, DOB5=>mdout1_0_23,
+ DOB6=>mdout1_0_24, DOB7=>mdout1_0_25, DOB8=>mdout1_0_26,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_0_3_28: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
- DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
- DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
- CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>rden_cr0_3, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_0_27, DOB1=>mdout1_0_28, DOB2=>mdout1_0_29,
- DOB3=>mdout1_0_30, DOB4=>mdout1_0_31, DOB5=>mdout1_0_32,
- DOB6=>mdout1_0_33, DOB7=>mdout1_0_34, DOB8=>mdout1_0_35,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
+ DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
+ DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rden_cr0_3, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_0_27, DOB1=>mdout1_0_28, DOB2=>mdout1_0_29,
+ DOB3=>mdout1_0_30, DOB4=>mdout1_0_31, DOB5=>mdout1_0_32,
+ DOB6=>mdout1_0_33, DOB7=>mdout1_0_34, DOB8=>mdout1_0_35,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_1_0_27: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
- CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>rden_cr0_4, CSB1=>rptr_12,
- CSB2=>rptr_13, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1,
- DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4,
- DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7,
- DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>rden_cr0_4, CSB1=>rptr_12,
+ CSB2=>rptr_13, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1,
+ DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4,
+ DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7,
+ DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
DOB16=>open, DOB17=>open);
pdp_ram_1_1_26: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
- DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
- DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
- CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>rden_cr0_5, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_1_9, DOB1=>mdout1_1_10, DOB2=>mdout1_1_11,
- DOB3=>mdout1_1_12, DOB4=>mdout1_1_13, DOB5=>mdout1_1_14,
- DOB6=>mdout1_1_15, DOB7=>mdout1_1_16, DOB8=>mdout1_1_17,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
+ DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
+ DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rden_cr0_5, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_1_9, DOB1=>mdout1_1_10, DOB2=>mdout1_1_11,
+ DOB3=>mdout1_1_12, DOB4=>mdout1_1_13, DOB5=>mdout1_1_14,
+ DOB6=>mdout1_1_15, DOB7=>mdout1_1_16, DOB8=>mdout1_1_17,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_1_2_25: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
- DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
- DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
- CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>rden_cr0_6, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_1_18, DOB1=>mdout1_1_19, DOB2=>mdout1_1_20,
- DOB3=>mdout1_1_21, DOB4=>mdout1_1_22, DOB5=>mdout1_1_23,
- DOB6=>mdout1_1_24, DOB7=>mdout1_1_25, DOB8=>mdout1_1_26,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
+ DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
+ DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rden_cr0_6, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_1_18, DOB1=>mdout1_1_19, DOB2=>mdout1_1_20,
+ DOB3=>mdout1_1_21, DOB4=>mdout1_1_22, DOB5=>mdout1_1_23,
+ DOB6=>mdout1_1_24, DOB7=>mdout1_1_25, DOB8=>mdout1_1_26,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_1_3_24: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
- DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
- DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
- CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>rden_cr0_7, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_1_27, DOB1=>mdout1_1_28, DOB2=>mdout1_1_29,
- DOB3=>mdout1_1_30, DOB4=>mdout1_1_31, DOB5=>mdout1_1_32,
- DOB6=>mdout1_1_33, DOB7=>mdout1_1_34, DOB8=>mdout1_1_35,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
+ DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
+ DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rden_cr0_7, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_1_27, DOB1=>mdout1_1_28, DOB2=>mdout1_1_29,
+ DOB3=>mdout1_1_30, DOB4=>mdout1_1_31, DOB5=>mdout1_1_32,
+ DOB6=>mdout1_1_33, DOB7=>mdout1_1_34, DOB8=>mdout1_1_35,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_2_0_23: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
- CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>rden_cr0_8, CSB1=>rptr_12,
- CSB2=>rptr_13, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0, DOB1=>mdout1_2_1,
- DOB2=>mdout1_2_2, DOB3=>mdout1_2_3, DOB4=>mdout1_2_4,
- DOB5=>mdout1_2_5, DOB6=>mdout1_2_6, DOB7=>mdout1_2_7,
- DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>rden_cr0_8, CSB1=>rptr_12,
+ CSB2=>rptr_13, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0, DOB1=>mdout1_2_1,
+ DOB2=>mdout1_2_2, DOB3=>mdout1_2_3, DOB4=>mdout1_2_4,
+ DOB5=>mdout1_2_5, DOB6=>mdout1_2_6, DOB7=>mdout1_2_7,
+ DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
DOB16=>open, DOB17=>open);
pdp_ram_2_1_22: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
- DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
- DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
- CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>rden_cr0_9, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_2_9, DOB1=>mdout1_2_10, DOB2=>mdout1_2_11,
- DOB3=>mdout1_2_12, DOB4=>mdout1_2_13, DOB5=>mdout1_2_14,
- DOB6=>mdout1_2_15, DOB7=>mdout1_2_16, DOB8=>mdout1_2_17,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
+ DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
+ DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rden_cr0_9, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_2_9, DOB1=>mdout1_2_10, DOB2=>mdout1_2_11,
+ DOB3=>mdout1_2_12, DOB4=>mdout1_2_13, DOB5=>mdout1_2_14,
+ DOB6=>mdout1_2_15, DOB7=>mdout1_2_16, DOB8=>mdout1_2_17,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_2_2_21: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
- DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
- DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
- CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>rden_cr0_10, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_2_18, DOB1=>mdout1_2_19, DOB2=>mdout1_2_20,
- DOB3=>mdout1_2_21, DOB4=>mdout1_2_22, DOB5=>mdout1_2_23,
- DOB6=>mdout1_2_24, DOB7=>mdout1_2_25, DOB8=>mdout1_2_26,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
+ DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
+ DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rden_cr0_10, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_2_18, DOB1=>mdout1_2_19, DOB2=>mdout1_2_20,
+ DOB3=>mdout1_2_21, DOB4=>mdout1_2_22, DOB5=>mdout1_2_23,
+ DOB6=>mdout1_2_24, DOB7=>mdout1_2_25, DOB8=>mdout1_2_26,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_2_3_20: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
- DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
- DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
- CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>rden_cr0_11, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_2_27, DOB1=>mdout1_2_28, DOB2=>mdout1_2_29,
- DOB3=>mdout1_2_30, DOB4=>mdout1_2_31, DOB5=>mdout1_2_32,
- DOB6=>mdout1_2_33, DOB7=>mdout1_2_34, DOB8=>mdout1_2_35,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
+ DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
+ DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rden_cr0_11, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_2_27, DOB1=>mdout1_2_28, DOB2=>mdout1_2_29,
+ DOB3=>mdout1_2_30, DOB4=>mdout1_2_31, DOB5=>mdout1_2_32,
+ DOB6=>mdout1_2_33, DOB7=>mdout1_2_34, DOB8=>mdout1_2_35,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_3_0_19: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
- CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>rden_cr0_12,
- CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0,
- DOB1=>mdout1_3_1, DOB2=>mdout1_3_2, DOB3=>mdout1_3_3,
- DOB4=>mdout1_3_4, DOB5=>mdout1_3_5, DOB6=>mdout1_3_6,
- DOB7=>mdout1_3_7, DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>rden_cr0_12,
+ CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0,
+ DOB1=>mdout1_3_1, DOB2=>mdout1_3_2, DOB3=>mdout1_3_3,
+ DOB4=>mdout1_3_4, DOB5=>mdout1_3_5, DOB6=>mdout1_3_6,
+ DOB7=>mdout1_3_7, DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_3_1_18: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
- DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
- DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
- CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>rden_cr0_13, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_3_9, DOB1=>mdout1_3_10, DOB2=>mdout1_3_11,
- DOB3=>mdout1_3_12, DOB4=>mdout1_3_13, DOB5=>mdout1_3_14,
- DOB6=>mdout1_3_15, DOB7=>mdout1_3_16, DOB8=>mdout1_3_17,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
+ DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
+ DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rden_cr0_13, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_3_9, DOB1=>mdout1_3_10, DOB2=>mdout1_3_11,
+ DOB3=>mdout1_3_12, DOB4=>mdout1_3_13, DOB5=>mdout1_3_14,
+ DOB6=>mdout1_3_15, DOB7=>mdout1_3_16, DOB8=>mdout1_3_17,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_3_2_17: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
- DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
- DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
- CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>rden_cr0_14, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_3_18, DOB1=>mdout1_3_19, DOB2=>mdout1_3_20,
- DOB3=>mdout1_3_21, DOB4=>mdout1_3_22, DOB5=>mdout1_3_23,
- DOB6=>mdout1_3_24, DOB7=>mdout1_3_25, DOB8=>mdout1_3_26,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
+ DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
+ DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rden_cr0_14, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_3_18, DOB1=>mdout1_3_19, DOB2=>mdout1_3_20,
+ DOB3=>mdout1_3_21, DOB4=>mdout1_3_22, DOB5=>mdout1_3_23,
+ DOB6=>mdout1_3_24, DOB7=>mdout1_3_25, DOB8=>mdout1_3_26,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_3_3_16: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
- DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
- DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
- CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>rden_cr0_15, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_3_27, DOB1=>mdout1_3_28, DOB2=>mdout1_3_29,
- DOB3=>mdout1_3_30, DOB4=>mdout1_3_31, DOB5=>mdout1_3_32,
- DOB6=>mdout1_3_33, DOB7=>mdout1_3_34, DOB8=>mdout1_3_35,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
+ DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
+ DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rden_cr0_15, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_3_27, DOB1=>mdout1_3_28, DOB2=>mdout1_3_29,
+ DOB3=>mdout1_3_30, DOB4=>mdout1_3_31, DOB5=>mdout1_3_32,
+ DOB6=>mdout1_3_33, DOB7=>mdout1_3_34, DOB8=>mdout1_3_35,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_4_0_15: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "100", CSDECODE_A=> "100", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "100", CSDECODE_A=> "100", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
- CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>rden_cr0_16,
- CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_4_0,
- DOB1=>mdout1_4_1, DOB2=>mdout1_4_2, DOB3=>mdout1_4_3,
- DOB4=>mdout1_4_4, DOB5=>mdout1_4_5, DOB6=>mdout1_4_6,
- DOB7=>mdout1_4_7, DOB8=>mdout1_4_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>rden_cr0_16,
+ CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_4_0,
+ DOB1=>mdout1_4_1, DOB2=>mdout1_4_2, DOB3=>mdout1_4_3,
+ DOB4=>mdout1_4_4, DOB5=>mdout1_4_5, DOB6=>mdout1_4_6,
+ DOB7=>mdout1_4_7, DOB8=>mdout1_4_8, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_4_1_14: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "100", CSDECODE_A=> "100", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "100", CSDECODE_A=> "100", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
- DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
- DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
- CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>rden_cr0_17, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_4_9, DOB1=>mdout1_4_10, DOB2=>mdout1_4_11,
- DOB3=>mdout1_4_12, DOB4=>mdout1_4_13, DOB5=>mdout1_4_14,
- DOB6=>mdout1_4_15, DOB7=>mdout1_4_16, DOB8=>mdout1_4_17,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
+ DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
+ DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rden_cr0_17, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_4_9, DOB1=>mdout1_4_10, DOB2=>mdout1_4_11,
+ DOB3=>mdout1_4_12, DOB4=>mdout1_4_13, DOB5=>mdout1_4_14,
+ DOB6=>mdout1_4_15, DOB7=>mdout1_4_16, DOB8=>mdout1_4_17,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_4_2_13: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "100", CSDECODE_A=> "100", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "100", CSDECODE_A=> "100", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
- DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
- DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
- CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>rden_cr0_18, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_4_18, DOB1=>mdout1_4_19, DOB2=>mdout1_4_20,
- DOB3=>mdout1_4_21, DOB4=>mdout1_4_22, DOB5=>mdout1_4_23,
- DOB6=>mdout1_4_24, DOB7=>mdout1_4_25, DOB8=>mdout1_4_26,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
+ DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
+ DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rden_cr0_18, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_4_18, DOB1=>mdout1_4_19, DOB2=>mdout1_4_20,
+ DOB3=>mdout1_4_21, DOB4=>mdout1_4_22, DOB5=>mdout1_4_23,
+ DOB6=>mdout1_4_24, DOB7=>mdout1_4_25, DOB8=>mdout1_4_26,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_4_3_12: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "100", CSDECODE_A=> "100", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "100", CSDECODE_A=> "100", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
- DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
- DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
- CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>rden_cr0_19, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_4_27, DOB1=>mdout1_4_28, DOB2=>mdout1_4_29,
- DOB3=>mdout1_4_30, DOB4=>mdout1_4_31, DOB5=>mdout1_4_32,
- DOB6=>mdout1_4_33, DOB7=>mdout1_4_34, DOB8=>mdout1_4_35,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
+ DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
+ DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rden_cr0_19, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_4_27, DOB1=>mdout1_4_28, DOB2=>mdout1_4_29,
+ DOB3=>mdout1_4_30, DOB4=>mdout1_4_31, DOB5=>mdout1_4_32,
+ DOB6=>mdout1_4_33, DOB7=>mdout1_4_34, DOB8=>mdout1_4_35,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_5_0_11: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "101", CSDECODE_A=> "101", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "101", CSDECODE_A=> "101", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
- CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>rden_cr0_20,
- CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_5_0,
- DOB1=>mdout1_5_1, DOB2=>mdout1_5_2, DOB3=>mdout1_5_3,
- DOB4=>mdout1_5_4, DOB5=>mdout1_5_5, DOB6=>mdout1_5_6,
- DOB7=>mdout1_5_7, DOB8=>mdout1_5_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>rden_cr0_20,
+ CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_5_0,
+ DOB1=>mdout1_5_1, DOB2=>mdout1_5_2, DOB3=>mdout1_5_3,
+ DOB4=>mdout1_5_4, DOB5=>mdout1_5_5, DOB6=>mdout1_5_6,
+ DOB7=>mdout1_5_7, DOB8=>mdout1_5_8, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_5_1_10: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "101", CSDECODE_A=> "101", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "101", CSDECODE_A=> "101", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
- DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
- DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
- CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>rden_cr0_21, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_5_9, DOB1=>mdout1_5_10, DOB2=>mdout1_5_11,
- DOB3=>mdout1_5_12, DOB4=>mdout1_5_13, DOB5=>mdout1_5_14,
- DOB6=>mdout1_5_15, DOB7=>mdout1_5_16, DOB8=>mdout1_5_17,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
+ DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
+ DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rden_cr0_21, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_5_9, DOB1=>mdout1_5_10, DOB2=>mdout1_5_11,
+ DOB3=>mdout1_5_12, DOB4=>mdout1_5_13, DOB5=>mdout1_5_14,
+ DOB6=>mdout1_5_15, DOB7=>mdout1_5_16, DOB8=>mdout1_5_17,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_5_2_9: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "101", CSDECODE_A=> "101", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "101", CSDECODE_A=> "101", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
- DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
- DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
- CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>rden_cr0_22, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_5_18, DOB1=>mdout1_5_19, DOB2=>mdout1_5_20,
- DOB3=>mdout1_5_21, DOB4=>mdout1_5_22, DOB5=>mdout1_5_23,
- DOB6=>mdout1_5_24, DOB7=>mdout1_5_25, DOB8=>mdout1_5_26,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
+ DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
+ DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rden_cr0_22, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_5_18, DOB1=>mdout1_5_19, DOB2=>mdout1_5_20,
+ DOB3=>mdout1_5_21, DOB4=>mdout1_5_22, DOB5=>mdout1_5_23,
+ DOB6=>mdout1_5_24, DOB7=>mdout1_5_25, DOB8=>mdout1_5_26,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_5_3_8: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "101", CSDECODE_A=> "101", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "101", CSDECODE_A=> "101", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
- DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
- DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
- CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>rden_cr0_23, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_5_27, DOB1=>mdout1_5_28, DOB2=>mdout1_5_29,
- DOB3=>mdout1_5_30, DOB4=>mdout1_5_31, DOB5=>mdout1_5_32,
- DOB6=>mdout1_5_33, DOB7=>mdout1_5_34, DOB8=>mdout1_5_35,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
+ DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
+ DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rden_cr0_23, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_5_27, DOB1=>mdout1_5_28, DOB2=>mdout1_5_29,
+ DOB3=>mdout1_5_30, DOB4=>mdout1_5_31, DOB5=>mdout1_5_32,
+ DOB6=>mdout1_5_33, DOB7=>mdout1_5_34, DOB8=>mdout1_5_35,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_6_0_7: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "110", CSDECODE_A=> "110", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "110", CSDECODE_A=> "110", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
- CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>rden_cr0_24,
- CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_6_0,
- DOB1=>mdout1_6_1, DOB2=>mdout1_6_2, DOB3=>mdout1_6_3,
- DOB4=>mdout1_6_4, DOB5=>mdout1_6_5, DOB6=>mdout1_6_6,
- DOB7=>mdout1_6_7, DOB8=>mdout1_6_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>rden_cr0_24,
+ CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_6_0,
+ DOB1=>mdout1_6_1, DOB2=>mdout1_6_2, DOB3=>mdout1_6_3,
+ DOB4=>mdout1_6_4, DOB5=>mdout1_6_5, DOB6=>mdout1_6_6,
+ DOB7=>mdout1_6_7, DOB8=>mdout1_6_8, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_6_1_6: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "110", CSDECODE_A=> "110", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "110", CSDECODE_A=> "110", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
- DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
- DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
- CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>rden_cr0_25, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_6_9, DOB1=>mdout1_6_10, DOB2=>mdout1_6_11,
- DOB3=>mdout1_6_12, DOB4=>mdout1_6_13, DOB5=>mdout1_6_14,
- DOB6=>mdout1_6_15, DOB7=>mdout1_6_16, DOB8=>mdout1_6_17,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
+ DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
+ DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rden_cr0_25, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_6_9, DOB1=>mdout1_6_10, DOB2=>mdout1_6_11,
+ DOB3=>mdout1_6_12, DOB4=>mdout1_6_13, DOB5=>mdout1_6_14,
+ DOB6=>mdout1_6_15, DOB7=>mdout1_6_16, DOB8=>mdout1_6_17,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_6_2_5: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "110", CSDECODE_A=> "110", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "110", CSDECODE_A=> "110", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
- DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
- DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
- CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>rden_cr0_26, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_6_18, DOB1=>mdout1_6_19, DOB2=>mdout1_6_20,
- DOB3=>mdout1_6_21, DOB4=>mdout1_6_22, DOB5=>mdout1_6_23,
- DOB6=>mdout1_6_24, DOB7=>mdout1_6_25, DOB8=>mdout1_6_26,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
+ DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
+ DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rden_cr0_26, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_6_18, DOB1=>mdout1_6_19, DOB2=>mdout1_6_20,
+ DOB3=>mdout1_6_21, DOB4=>mdout1_6_22, DOB5=>mdout1_6_23,
+ DOB6=>mdout1_6_24, DOB7=>mdout1_6_25, DOB8=>mdout1_6_26,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_6_3_4: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "110", CSDECODE_A=> "110", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "110", CSDECODE_A=> "110", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
- DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
- DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
- CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>rden_cr0_27, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_6_27, DOB1=>mdout1_6_28, DOB2=>mdout1_6_29,
- DOB3=>mdout1_6_30, DOB4=>mdout1_6_31, DOB5=>mdout1_6_32,
- DOB6=>mdout1_6_33, DOB7=>mdout1_6_34, DOB8=>mdout1_6_35,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
+ DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
+ DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rden_cr0_27, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_6_27, DOB1=>mdout1_6_28, DOB2=>mdout1_6_29,
+ DOB3=>mdout1_6_30, DOB4=>mdout1_6_31, DOB5=>mdout1_6_32,
+ DOB6=>mdout1_6_33, DOB7=>mdout1_6_34, DOB8=>mdout1_6_35,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_7_0_3: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "111", CSDECODE_A=> "111", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "111", CSDECODE_A=> "111", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
- CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>rden_cr0_28,
- CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_7_0,
- DOB1=>mdout1_7_1, DOB2=>mdout1_7_2, DOB3=>mdout1_7_3,
- DOB4=>mdout1_7_4, DOB5=>mdout1_7_5, DOB6=>mdout1_7_6,
- DOB7=>mdout1_7_7, DOB8=>mdout1_7_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>wptr_13, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>rden_cr0_28,
+ CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_7_0,
+ DOB1=>mdout1_7_1, DOB2=>mdout1_7_2, DOB3=>mdout1_7_3,
+ DOB4=>mdout1_7_4, DOB5=>mdout1_7_5, DOB6=>mdout1_7_6,
+ DOB7=>mdout1_7_7, DOB8=>mdout1_7_8, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_7_1_2: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "111", CSDECODE_A=> "111", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "111", CSDECODE_A=> "111", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
- DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
- DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
- CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>rden_cr0_29, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_7_9, DOB1=>mdout1_7_10, DOB2=>mdout1_7_11,
- DOB3=>mdout1_7_12, DOB4=>mdout1_7_13, DOB5=>mdout1_7_14,
- DOB6=>mdout1_7_15, DOB7=>mdout1_7_16, DOB8=>mdout1_7_17,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
+ DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
+ DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rden_cr0_29, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_7_9, DOB1=>mdout1_7_10, DOB2=>mdout1_7_11,
+ DOB3=>mdout1_7_12, DOB4=>mdout1_7_13, DOB5=>mdout1_7_14,
+ DOB6=>mdout1_7_15, DOB7=>mdout1_7_16, DOB8=>mdout1_7_17,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_7_2_1: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "111", CSDECODE_A=> "111", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "111", CSDECODE_A=> "111", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
- DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
- DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
- CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>rden_cr0_30, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_7_18, DOB1=>mdout1_7_19, DOB2=>mdout1_7_20,
- DOB3=>mdout1_7_21, DOB4=>mdout1_7_22, DOB5=>mdout1_7_23,
- DOB6=>mdout1_7_24, DOB7=>mdout1_7_25, DOB8=>mdout1_7_26,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
+ DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
+ DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rden_cr0_30, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_7_18, DOB1=>mdout1_7_19, DOB2=>mdout1_7_20,
+ DOB3=>mdout1_7_21, DOB4=>mdout1_7_22, DOB5=>mdout1_7_23,
+ DOB6=>mdout1_7_24, DOB7=>mdout1_7_25, DOB8=>mdout1_7_26,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_7_3_0: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "111", CSDECODE_A=> "111", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "111", CSDECODE_A=> "111", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
- DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
- DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
- CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>rden_cr0_31, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_7_27, DOB1=>mdout1_7_28, DOB2=>mdout1_7_29,
- DOB3=>mdout1_7_30, DOB4=>mdout1_7_31, DOB5=>mdout1_7_32,
- DOB6=>mdout1_7_33, DOB7=>mdout1_7_34, DOB8=>mdout1_7_35,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
+ DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
+ DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>wptr_13, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rden_cr0_31, CSB1=>rptr_12, CSB2=>rptr_13, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_7_27, DOB1=>mdout1_7_28, DOB2=>mdout1_7_29,
+ DOB3=>mdout1_7_30, DOB4=>mdout1_7_31, DOB5=>mdout1_7_32,
+ DOB6=>mdout1_7_33, DOB7=>mdout1_7_34, DOB8=>mdout1_7_35,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
FF_98: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_0);
FF_97: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_1);
FF_96: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_2);
FF_95: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_3);
FF_94: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_4);
FF_93: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_5);
FF_92: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_6);
FF_91: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_7);
FF_90: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_8);
FF_89: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_9);
FF_88: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_10);
FF_87: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_11);
FF_86: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_12, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_12, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_12);
FF_85: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_13, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_13, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_13);
FF_84: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_14, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_14, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_14);
FF_83: FD1S3BX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset,
+ port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset,
Q=>wcount_0);
FF_80: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_1);
FF_79: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_2);
FF_78: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_3);
FF_77: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_4);
FF_76: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_5);
FF_75: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_6);
FF_74: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_7);
FF_73: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_8);
FF_72: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_9);
FF_71: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_10);
FF_70: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_11);
FF_69: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_12, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_12, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_12);
FF_68: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_13, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_13, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_13);
FF_67: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_14, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_14, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_14);
FF_66: FD1P3BX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset,
+ port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset,
Q=>rcount_0);
FF_65: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_1);
FF_64: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_2);
FF_63: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_3);
FF_62: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_4);
FF_61: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_5);
FF_60: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_6);
FF_59: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_7);
FF_58: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_8);
FF_57: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_9);
FF_56: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_10);
FF_55: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_11);
FF_54: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_12, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_12, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_12);
FF_53: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_13, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_13, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_13);
FF_52: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_14, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_14, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_14);
FF_51: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_0);
FF_50: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_1);
FF_49: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_2);
FF_48: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_3);
FF_47: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_4);
FF_46: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_5);
FF_45: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_6);
FF_44: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_7);
FF_43: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_8);
FF_42: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_9);
FF_41: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_10);
FF_40: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_11, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_11, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_11);
FF_39: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_12, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_12, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_12);
FF_38: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_13, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_13, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_13);
FF_37: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_14, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_14, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_14);
FF_36: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_0);
FF_35: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_1);
FF_34: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_2);
FF_33: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_3);
FF_32: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_4);
FF_31: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_5);
FF_30: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_6);
FF_29: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_7);
FF_28: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_8);
FF_27: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_9);
FF_26: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_10);
FF_25: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_11, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_11, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_11);
FF_24: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_12, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_12, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_12);
FF_23: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_13, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_13, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_13);
FF_22: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_14, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_14, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_14);
FF_21: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rptr_11, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ port map (D=>rptr_11, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
Q=>rptr_11_ff);
FF_20: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rptr_12, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ port map (D=>rptr_12, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
Q=>rptr_12_ff);
FF_19: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rptr_13, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ port map (D=>rptr_13, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
Q=>rptr_13_ff);
+-- FF_18: FD1P3DX
+-- -- synopsys translate_off
+-- generic map (GSR=> "ENABLED")
+-- -- synopsys translate_on
+-- port map (D=>rptr_11_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+-- Q=>rptr_11_ff2);
+--
+-- FF_17: FD1P3DX
+-- -- synopsys translate_off
+-- generic map (GSR=> "ENABLED")
+-- -- synopsys translate_on
+-- port map (D=>rptr_12_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+-- Q=>rptr_12_ff2);
+--
+-- FF_16: FD1P3DX
+-- -- synopsys translate_off
+-- generic map (GSR=> "ENABLED")
+-- -- synopsys translate_on
+-- port map (D=>rptr_13_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+-- Q=>rptr_13_ff2);
+
FF_18: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rptr_11_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ port map (D=>rptr_11_ff, SP=>'1', CK=>Clock, CD=>scuba_vlo,
Q=>rptr_11_ff2);
FF_17: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rptr_12_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ port map (D=>rptr_12_ff, SP=>'1', CK=>Clock, CD=>scuba_vlo,
Q=>rptr_12_ff2);
FF_16: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rptr_13_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ port map (D=>rptr_13_ff, SP=>'1', CK=>Clock, CD=>scuba_vlo,
Q=>rptr_13_ff2);
FF_15: FD1S3DX
port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull);
bdcnt_bctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con,
+ port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con,
CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open);
bdcnt_bctr_0: CB2
- port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1,
+ port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1,
CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1);
bdcnt_bctr_1: CB2
- port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con,
+ port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con,
CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3);
bdcnt_bctr_2: CB2
- port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con,
+ port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con,
CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5);
bdcnt_bctr_3: CB2
- port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con,
+ port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con,
CO=>co3, NC0=>ifcount_6, NC1=>ifcount_7);
bdcnt_bctr_4: CB2
- port map (CI=>co3, PC0=>fcount_8, PC1=>fcount_9, CON=>cnt_con,
+ port map (CI=>co3, PC0=>fcount_8, PC1=>fcount_9, CON=>cnt_con,
CO=>co4, NC0=>ifcount_8, NC1=>ifcount_9);
bdcnt_bctr_5: CB2
- port map (CI=>co4, PC0=>fcount_10, PC1=>fcount_11, CON=>cnt_con,
+ port map (CI=>co4, PC0=>fcount_10, PC1=>fcount_11, CON=>cnt_con,
CO=>co5, NC0=>ifcount_10, NC1=>ifcount_11);
bdcnt_bctr_6: CB2
- port map (CI=>co5, PC0=>fcount_12, PC1=>fcount_13, CON=>cnt_con,
+ port map (CI=>co5, PC0=>fcount_12, PC1=>fcount_13, CON=>cnt_con,
CO=>co6, NC0=>ifcount_12, NC1=>ifcount_13);
bdcnt_bctr_7: CB2
- port map (CI=>co6, PC0=>fcount_14, PC1=>scuba_vlo, CON=>cnt_con,
+ port map (CI=>co6, PC0=>fcount_14, PC1=>scuba_vlo, CON=>cnt_con,
CO=>co7, NC0=>ifcount_14, NC1=>open);
e_cmp_ci_a: FADD2B
- port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open,
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open,
S1=>open);
e_cmp_0: ALEB2
- port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo,
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo,
CI=>cmp_ci, LE=>co0_1);
e_cmp_1: ALEB2
- port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo,
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo,
B1=>scuba_vlo, CI=>co0_1, LE=>co1_1);
e_cmp_2: ALEB2
- port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo,
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo,
B1=>scuba_vlo, CI=>co1_1, LE=>co2_1);
e_cmp_3: ALEB2
- port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo,
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo,
B1=>scuba_vlo, CI=>co2_1, LE=>co3_1);
e_cmp_4: ALEB2
- port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo,
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo,
B1=>scuba_vlo, CI=>co3_1, LE=>co4_1);
e_cmp_5: ALEB2
- port map (A0=>fcount_10, A1=>fcount_11, B0=>scuba_vlo,
+ port map (A0=>fcount_10, A1=>fcount_11, B0=>scuba_vlo,
B1=>scuba_vlo, CI=>co4_1, LE=>co5_1);
e_cmp_6: ALEB2
- port map (A0=>fcount_12, A1=>fcount_13, B0=>scuba_vlo,
+ port map (A0=>fcount_12, A1=>fcount_13, B0=>scuba_vlo,
B1=>scuba_vlo, CI=>co5_1, LE=>co6_1);
e_cmp_7: ALEB2
- port map (A0=>fcount_14, A1=>scuba_vlo, B0=>scuba_vlo,
+ port map (A0=>fcount_14, A1=>scuba_vlo, B0=>scuba_vlo,
B1=>scuba_vlo, CI=>co6_1, LE=>cmp_le_1_c);
a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1,
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1,
S1=>open);
g_cmp_ci_a: FADD2B
- port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open,
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open,
S1=>open);
g_cmp_0: AGEB2
- port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i,
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i,
CI=>cmp_ci_1, GE=>co0_2);
g_cmp_1: AGEB2
- port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i,
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i,
CI=>co0_2, GE=>co1_2);
g_cmp_2: AGEB2
- port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i,
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i,
CI=>co1_2, GE=>co2_2);
g_cmp_3: AGEB2
- port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i,
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i,
CI=>co2_2, GE=>co3_2);
g_cmp_4: AGEB2
- port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i,
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i,
CI=>co3_2, GE=>co4_2);
g_cmp_5: AGEB2
- port map (A0=>fcount_10, A1=>fcount_11, B0=>wren_i, B1=>wren_i,
+ port map (A0=>fcount_10, A1=>fcount_11, B0=>wren_i, B1=>wren_i,
CI=>co4_2, GE=>co5_2);
g_cmp_6: AGEB2
- port map (A0=>fcount_12, A1=>fcount_13, B0=>wren_i, B1=>wren_i,
+ port map (A0=>fcount_12, A1=>fcount_13, B0=>wren_i, B1=>wren_i,
CI=>co5_2, GE=>co6_2);
g_cmp_7: AGEB2
- port map (A0=>fcount_14, A1=>scuba_vlo, B0=>wren_i_inv,
+ port map (A0=>fcount_14, A1=>scuba_vlo, B0=>wren_i_inv,
B1=>scuba_vlo, CI=>co6_2, GE=>cmp_ge_d1_c);
a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1,
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1,
S1=>open);
w_ctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open,
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open,
S1=>open);
w_ctr_0: CU2
- port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3,
+ port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3,
NC0=>iwcount_0, NC1=>iwcount_1);
w_ctr_1: CU2
- port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3,
+ port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3,
NC0=>iwcount_2, NC1=>iwcount_3);
w_ctr_2: CU2
- port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3,
+ port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3,
NC0=>iwcount_4, NC1=>iwcount_5);
w_ctr_3: CU2
- port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3,
+ port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3,
NC0=>iwcount_6, NC1=>iwcount_7);
w_ctr_4: CU2
- port map (CI=>co3_3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4_3,
+ port map (CI=>co3_3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4_3,
NC0=>iwcount_8, NC1=>iwcount_9);
w_ctr_5: CU2
- port map (CI=>co4_3, PC0=>wcount_10, PC1=>wcount_11, CO=>co5_3,
+ port map (CI=>co4_3, PC0=>wcount_10, PC1=>wcount_11, CO=>co5_3,
NC0=>iwcount_10, NC1=>iwcount_11);
w_ctr_6: CU2
- port map (CI=>co5_3, PC0=>wcount_12, PC1=>wcount_13, CO=>co6_3,
+ port map (CI=>co5_3, PC0=>wcount_12, PC1=>wcount_13, CO=>co6_3,
NC0=>iwcount_12, NC1=>iwcount_13);
w_ctr_7: CU2
- port map (CI=>co6_3, PC0=>wcount_14, PC1=>scuba_vlo, CO=>co7_1,
+ port map (CI=>co6_3, PC0=>wcount_14, PC1=>scuba_vlo, CO=>co7_1,
NC0=>iwcount_14, NC1=>open);
scuba_vhi_inst: VHI
port map (Z=>scuba_vhi);
r_ctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open,
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open,
S1=>open);
r_ctr_0: CU2
- port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4,
+ port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4,
NC0=>ircount_0, NC1=>ircount_1);
r_ctr_1: CU2
- port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4,
+ port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4,
NC0=>ircount_2, NC1=>ircount_3);
r_ctr_2: CU2
- port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4,
+ port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4,
NC0=>ircount_4, NC1=>ircount_5);
r_ctr_3: CU2
- port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4,
+ port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4,
NC0=>ircount_6, NC1=>ircount_7);
r_ctr_4: CU2
- port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_4,
+ port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_4,
NC0=>ircount_8, NC1=>ircount_9);
r_ctr_5: CU2
- port map (CI=>co4_4, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_4,
+ port map (CI=>co4_4, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_4,
NC0=>ircount_10, NC1=>ircount_11);
r_ctr_6: CU2
- port map (CI=>co5_4, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_4,
+ port map (CI=>co5_4, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_4,
NC0=>ircount_12, NC1=>ircount_13);
r_ctr_7: CU2
- port map (CI=>co6_4, PC0=>rcount_14, PC1=>scuba_vlo, CO=>co7_2,
+ port map (CI=>co6_4, PC0=>rcount_14, PC1=>scuba_vlo, CO=>co7_2,
NC0=>ircount_14, NC1=>open);
mux_35: MUX81
- port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0,
- D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0,
- D6=>mdout1_6_0, D7=>mdout1_7_0, SD1=>rptr_11_ff2,
+ port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0,
+ D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0,
+ D6=>mdout1_6_0, D7=>mdout1_7_0, SD1=>rptr_11_ff2,
SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(0));
mux_34: MUX81
- port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1,
- D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1,
- D6=>mdout1_6_1, D7=>mdout1_7_1, SD1=>rptr_11_ff2,
+ port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1,
+ D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1,
+ D6=>mdout1_6_1, D7=>mdout1_7_1, SD1=>rptr_11_ff2,
SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(1));
mux_33: MUX81
- port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2,
- D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2,
- D6=>mdout1_6_2, D7=>mdout1_7_2, SD1=>rptr_11_ff2,
+ port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2,
+ D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2,
+ D6=>mdout1_6_2, D7=>mdout1_7_2, SD1=>rptr_11_ff2,
SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(2));
mux_32: MUX81
- port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3,
- D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3,
- D6=>mdout1_6_3, D7=>mdout1_7_3, SD1=>rptr_11_ff2,
+ port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3,
+ D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3,
+ D6=>mdout1_6_3, D7=>mdout1_7_3, SD1=>rptr_11_ff2,
SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(3));
mux_31: MUX81
- port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4,
- D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4,
- D6=>mdout1_6_4, D7=>mdout1_7_4, SD1=>rptr_11_ff2,
+ port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4,
+ D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4,
+ D6=>mdout1_6_4, D7=>mdout1_7_4, SD1=>rptr_11_ff2,
SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(4));
mux_30: MUX81
- port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5,
- D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5,
- D6=>mdout1_6_5, D7=>mdout1_7_5, SD1=>rptr_11_ff2,
+ port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5,
+ D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5,
+ D6=>mdout1_6_5, D7=>mdout1_7_5, SD1=>rptr_11_ff2,
SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(5));
mux_29: MUX81
- port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6,
- D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6,
- D6=>mdout1_6_6, D7=>mdout1_7_6, SD1=>rptr_11_ff2,
+ port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6,
+ D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6,
+ D6=>mdout1_6_6, D7=>mdout1_7_6, SD1=>rptr_11_ff2,
SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(6));
mux_28: MUX81
- port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7,
- D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7,
- D6=>mdout1_6_7, D7=>mdout1_7_7, SD1=>rptr_11_ff2,
+ port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7,
+ D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7,
+ D6=>mdout1_6_7, D7=>mdout1_7_7, SD1=>rptr_11_ff2,
SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(7));
mux_27: MUX81
- port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8,
- D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8,
- D6=>mdout1_6_8, D7=>mdout1_7_8, SD1=>rptr_11_ff2,
+ port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8,
+ D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8,
+ D6=>mdout1_6_8, D7=>mdout1_7_8, SD1=>rptr_11_ff2,
SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(8));
mux_26: MUX81
- port map (D0=>mdout1_0_9, D1=>mdout1_1_9, D2=>mdout1_2_9,
- D3=>mdout1_3_9, D4=>mdout1_4_9, D5=>mdout1_5_9,
- D6=>mdout1_6_9, D7=>mdout1_7_9, SD1=>rptr_11_ff2,
+ port map (D0=>mdout1_0_9, D1=>mdout1_1_9, D2=>mdout1_2_9,
+ D3=>mdout1_3_9, D4=>mdout1_4_9, D5=>mdout1_5_9,
+ D6=>mdout1_6_9, D7=>mdout1_7_9, SD1=>rptr_11_ff2,
SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(9));
mux_25: MUX81
- port map (D0=>mdout1_0_10, D1=>mdout1_1_10, D2=>mdout1_2_10,
- D3=>mdout1_3_10, D4=>mdout1_4_10, D5=>mdout1_5_10,
- D6=>mdout1_6_10, D7=>mdout1_7_10, SD1=>rptr_11_ff2,
+ port map (D0=>mdout1_0_10, D1=>mdout1_1_10, D2=>mdout1_2_10,
+ D3=>mdout1_3_10, D4=>mdout1_4_10, D5=>mdout1_5_10,
+ D6=>mdout1_6_10, D7=>mdout1_7_10, SD1=>rptr_11_ff2,
SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(10));
mux_24: MUX81
- port map (D0=>mdout1_0_11, D1=>mdout1_1_11, D2=>mdout1_2_11,
- D3=>mdout1_3_11, D4=>mdout1_4_11, D5=>mdout1_5_11,
- D6=>mdout1_6_11, D7=>mdout1_7_11, SD1=>rptr_11_ff2,
+ port map (D0=>mdout1_0_11, D1=>mdout1_1_11, D2=>mdout1_2_11,
+ D3=>mdout1_3_11, D4=>mdout1_4_11, D5=>mdout1_5_11,
+ D6=>mdout1_6_11, D7=>mdout1_7_11, SD1=>rptr_11_ff2,
SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(11));
mux_23: MUX81
- port map (D0=>mdout1_0_12, D1=>mdout1_1_12, D2=>mdout1_2_12,
- D3=>mdout1_3_12, D4=>mdout1_4_12, D5=>mdout1_5_12,
- D6=>mdout1_6_12, D7=>mdout1_7_12, SD1=>rptr_11_ff2,
+ port map (D0=>mdout1_0_12, D1=>mdout1_1_12, D2=>mdout1_2_12,
+ D3=>mdout1_3_12, D4=>mdout1_4_12, D5=>mdout1_5_12,
+ D6=>mdout1_6_12, D7=>mdout1_7_12, SD1=>rptr_11_ff2,
SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(12));
mux_22: MUX81
- port map (D0=>mdout1_0_13, D1=>mdout1_1_13, D2=>mdout1_2_13,
- D3=>mdout1_3_13, D4=>mdout1_4_13, D5=>mdout1_5_13,
- D6=>mdout1_6_13, D7=>mdout1_7_13, SD1=>rptr_11_ff2,
+ port map (D0=>mdout1_0_13, D1=>mdout1_1_13, D2=>mdout1_2_13,
+ D3=>mdout1_3_13, D4=>mdout1_4_13, D5=>mdout1_5_13,
+ D6=>mdout1_6_13, D7=>mdout1_7_13, SD1=>rptr_11_ff2,
SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(13));
mux_21: MUX81
- port map (D0=>mdout1_0_14, D1=>mdout1_1_14, D2=>mdout1_2_14,
- D3=>mdout1_3_14, D4=>mdout1_4_14, D5=>mdout1_5_14,
- D6=>mdout1_6_14, D7=>mdout1_7_14, SD1=>rptr_11_ff2,
+ port map (D0=>mdout1_0_14, D1=>mdout1_1_14, D2=>mdout1_2_14,
+ D3=>mdout1_3_14, D4=>mdout1_4_14, D5=>mdout1_5_14,
+ D6=>mdout1_6_14, D7=>mdout1_7_14, SD1=>rptr_11_ff2,
SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(14));
mux_20: MUX81
- port map (D0=>mdout1_0_15, D1=>mdout1_1_15, D2=>mdout1_2_15,
- D3=>mdout1_3_15, D4=>mdout1_4_15, D5=>mdout1_5_15,
- D6=>mdout1_6_15, D7=>mdout1_7_15, SD1=>rptr_11_ff2,
+ port map (D0=>mdout1_0_15, D1=>mdout1_1_15, D2=>mdout1_2_15,
+ D3=>mdout1_3_15, D4=>mdout1_4_15, D5=>mdout1_5_15,
+ D6=>mdout1_6_15, D7=>mdout1_7_15, SD1=>rptr_11_ff2,
SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(15));
mux_19: MUX81
- port map (D0=>mdout1_0_16, D1=>mdout1_1_16, D2=>mdout1_2_16,
- D3=>mdout1_3_16, D4=>mdout1_4_16, D5=>mdout1_5_16,
- D6=>mdout1_6_16, D7=>mdout1_7_16, SD1=>rptr_11_ff2,
+ port map (D0=>mdout1_0_16, D1=>mdout1_1_16, D2=>mdout1_2_16,
+ D3=>mdout1_3_16, D4=>mdout1_4_16, D5=>mdout1_5_16,
+ D6=>mdout1_6_16, D7=>mdout1_7_16, SD1=>rptr_11_ff2,
SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(16));
mux_18: MUX81
- port map (D0=>mdout1_0_17, D1=>mdout1_1_17, D2=>mdout1_2_17,
- D3=>mdout1_3_17, D4=>mdout1_4_17, D5=>mdout1_5_17,
- D6=>mdout1_6_17, D7=>mdout1_7_17, SD1=>rptr_11_ff2,
+ port map (D0=>mdout1_0_17, D1=>mdout1_1_17, D2=>mdout1_2_17,
+ D3=>mdout1_3_17, D4=>mdout1_4_17, D5=>mdout1_5_17,
+ D6=>mdout1_6_17, D7=>mdout1_7_17, SD1=>rptr_11_ff2,
SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(17));
mux_17: MUX81
- port map (D0=>mdout1_0_18, D1=>mdout1_1_18, D2=>mdout1_2_18,
- D3=>mdout1_3_18, D4=>mdout1_4_18, D5=>mdout1_5_18,
- D6=>mdout1_6_18, D7=>mdout1_7_18, SD1=>rptr_11_ff2,
+ port map (D0=>mdout1_0_18, D1=>mdout1_1_18, D2=>mdout1_2_18,
+ D3=>mdout1_3_18, D4=>mdout1_4_18, D5=>mdout1_5_18,
+ D6=>mdout1_6_18, D7=>mdout1_7_18, SD1=>rptr_11_ff2,
SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(18));
mux_16: MUX81
- port map (D0=>mdout1_0_19, D1=>mdout1_1_19, D2=>mdout1_2_19,
- D3=>mdout1_3_19, D4=>mdout1_4_19, D5=>mdout1_5_19,
- D6=>mdout1_6_19, D7=>mdout1_7_19, SD1=>rptr_11_ff2,
+ port map (D0=>mdout1_0_19, D1=>mdout1_1_19, D2=>mdout1_2_19,
+ D3=>mdout1_3_19, D4=>mdout1_4_19, D5=>mdout1_5_19,
+ D6=>mdout1_6_19, D7=>mdout1_7_19, SD1=>rptr_11_ff2,
SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(19));
mux_15: MUX81
- port map (D0=>mdout1_0_20, D1=>mdout1_1_20, D2=>mdout1_2_20,
- D3=>mdout1_3_20, D4=>mdout1_4_20, D5=>mdout1_5_20,
- D6=>mdout1_6_20, D7=>mdout1_7_20, SD1=>rptr_11_ff2,
+ port map (D0=>mdout1_0_20, D1=>mdout1_1_20, D2=>mdout1_2_20,
+ D3=>mdout1_3_20, D4=>mdout1_4_20, D5=>mdout1_5_20,
+ D6=>mdout1_6_20, D7=>mdout1_7_20, SD1=>rptr_11_ff2,
SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(20));
mux_14: MUX81
- port map (D0=>mdout1_0_21, D1=>mdout1_1_21, D2=>mdout1_2_21,
- D3=>mdout1_3_21, D4=>mdout1_4_21, D5=>mdout1_5_21,
- D6=>mdout1_6_21, D7=>mdout1_7_21, SD1=>rptr_11_ff2,
+ port map (D0=>mdout1_0_21, D1=>mdout1_1_21, D2=>mdout1_2_21,
+ D3=>mdout1_3_21, D4=>mdout1_4_21, D5=>mdout1_5_21,
+ D6=>mdout1_6_21, D7=>mdout1_7_21, SD1=>rptr_11_ff2,
SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(21));
mux_13: MUX81
- port map (D0=>mdout1_0_22, D1=>mdout1_1_22, D2=>mdout1_2_22,
- D3=>mdout1_3_22, D4=>mdout1_4_22, D5=>mdout1_5_22,
- D6=>mdout1_6_22, D7=>mdout1_7_22, SD1=>rptr_11_ff2,
+ port map (D0=>mdout1_0_22, D1=>mdout1_1_22, D2=>mdout1_2_22,
+ D3=>mdout1_3_22, D4=>mdout1_4_22, D5=>mdout1_5_22,
+ D6=>mdout1_6_22, D7=>mdout1_7_22, SD1=>rptr_11_ff2,
SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(22));
mux_12: MUX81
- port map (D0=>mdout1_0_23, D1=>mdout1_1_23, D2=>mdout1_2_23,
- D3=>mdout1_3_23, D4=>mdout1_4_23, D5=>mdout1_5_23,
- D6=>mdout1_6_23, D7=>mdout1_7_23, SD1=>rptr_11_ff2,
+ port map (D0=>mdout1_0_23, D1=>mdout1_1_23, D2=>mdout1_2_23,
+ D3=>mdout1_3_23, D4=>mdout1_4_23, D5=>mdout1_5_23,
+ D6=>mdout1_6_23, D7=>mdout1_7_23, SD1=>rptr_11_ff2,
SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(23));
mux_11: MUX81
- port map (D0=>mdout1_0_24, D1=>mdout1_1_24, D2=>mdout1_2_24,
- D3=>mdout1_3_24, D4=>mdout1_4_24, D5=>mdout1_5_24,
- D6=>mdout1_6_24, D7=>mdout1_7_24, SD1=>rptr_11_ff2,
+ port map (D0=>mdout1_0_24, D1=>mdout1_1_24, D2=>mdout1_2_24,
+ D3=>mdout1_3_24, D4=>mdout1_4_24, D5=>mdout1_5_24,
+ D6=>mdout1_6_24, D7=>mdout1_7_24, SD1=>rptr_11_ff2,
SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(24));
mux_10: MUX81
- port map (D0=>mdout1_0_25, D1=>mdout1_1_25, D2=>mdout1_2_25,
- D3=>mdout1_3_25, D4=>mdout1_4_25, D5=>mdout1_5_25,
- D6=>mdout1_6_25, D7=>mdout1_7_25, SD1=>rptr_11_ff2,
+ port map (D0=>mdout1_0_25, D1=>mdout1_1_25, D2=>mdout1_2_25,
+ D3=>mdout1_3_25, D4=>mdout1_4_25, D5=>mdout1_5_25,
+ D6=>mdout1_6_25, D7=>mdout1_7_25, SD1=>rptr_11_ff2,
SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(25));
mux_9: MUX81
- port map (D0=>mdout1_0_26, D1=>mdout1_1_26, D2=>mdout1_2_26,
- D3=>mdout1_3_26, D4=>mdout1_4_26, D5=>mdout1_5_26,
- D6=>mdout1_6_26, D7=>mdout1_7_26, SD1=>rptr_11_ff2,
+ port map (D0=>mdout1_0_26, D1=>mdout1_1_26, D2=>mdout1_2_26,
+ D3=>mdout1_3_26, D4=>mdout1_4_26, D5=>mdout1_5_26,
+ D6=>mdout1_6_26, D7=>mdout1_7_26, SD1=>rptr_11_ff2,
SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(26));
mux_8: MUX81
- port map (D0=>mdout1_0_27, D1=>mdout1_1_27, D2=>mdout1_2_27,
- D3=>mdout1_3_27, D4=>mdout1_4_27, D5=>mdout1_5_27,
- D6=>mdout1_6_27, D7=>mdout1_7_27, SD1=>rptr_11_ff2,
+ port map (D0=>mdout1_0_27, D1=>mdout1_1_27, D2=>mdout1_2_27,
+ D3=>mdout1_3_27, D4=>mdout1_4_27, D5=>mdout1_5_27,
+ D6=>mdout1_6_27, D7=>mdout1_7_27, SD1=>rptr_11_ff2,
SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(27));
mux_7: MUX81
- port map (D0=>mdout1_0_28, D1=>mdout1_1_28, D2=>mdout1_2_28,
- D3=>mdout1_3_28, D4=>mdout1_4_28, D5=>mdout1_5_28,
- D6=>mdout1_6_28, D7=>mdout1_7_28, SD1=>rptr_11_ff2,
+ port map (D0=>mdout1_0_28, D1=>mdout1_1_28, D2=>mdout1_2_28,
+ D3=>mdout1_3_28, D4=>mdout1_4_28, D5=>mdout1_5_28,
+ D6=>mdout1_6_28, D7=>mdout1_7_28, SD1=>rptr_11_ff2,
SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(28));
mux_6: MUX81
- port map (D0=>mdout1_0_29, D1=>mdout1_1_29, D2=>mdout1_2_29,
- D3=>mdout1_3_29, D4=>mdout1_4_29, D5=>mdout1_5_29,
- D6=>mdout1_6_29, D7=>mdout1_7_29, SD1=>rptr_11_ff2,
+ port map (D0=>mdout1_0_29, D1=>mdout1_1_29, D2=>mdout1_2_29,
+ D3=>mdout1_3_29, D4=>mdout1_4_29, D5=>mdout1_5_29,
+ D6=>mdout1_6_29, D7=>mdout1_7_29, SD1=>rptr_11_ff2,
SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(29));
mux_5: MUX81
- port map (D0=>mdout1_0_30, D1=>mdout1_1_30, D2=>mdout1_2_30,
- D3=>mdout1_3_30, D4=>mdout1_4_30, D5=>mdout1_5_30,
- D6=>mdout1_6_30, D7=>mdout1_7_30, SD1=>rptr_11_ff2,
+ port map (D0=>mdout1_0_30, D1=>mdout1_1_30, D2=>mdout1_2_30,
+ D3=>mdout1_3_30, D4=>mdout1_4_30, D5=>mdout1_5_30,
+ D6=>mdout1_6_30, D7=>mdout1_7_30, SD1=>rptr_11_ff2,
SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(30));
mux_4: MUX81
- port map (D0=>mdout1_0_31, D1=>mdout1_1_31, D2=>mdout1_2_31,
- D3=>mdout1_3_31, D4=>mdout1_4_31, D5=>mdout1_5_31,
- D6=>mdout1_6_31, D7=>mdout1_7_31, SD1=>rptr_11_ff2,
+ port map (D0=>mdout1_0_31, D1=>mdout1_1_31, D2=>mdout1_2_31,
+ D3=>mdout1_3_31, D4=>mdout1_4_31, D5=>mdout1_5_31,
+ D6=>mdout1_6_31, D7=>mdout1_7_31, SD1=>rptr_11_ff2,
SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(31));
mux_3: MUX81
- port map (D0=>mdout1_0_32, D1=>mdout1_1_32, D2=>mdout1_2_32,
- D3=>mdout1_3_32, D4=>mdout1_4_32, D5=>mdout1_5_32,
- D6=>mdout1_6_32, D7=>mdout1_7_32, SD1=>rptr_11_ff2,
+ port map (D0=>mdout1_0_32, D1=>mdout1_1_32, D2=>mdout1_2_32,
+ D3=>mdout1_3_32, D4=>mdout1_4_32, D5=>mdout1_5_32,
+ D6=>mdout1_6_32, D7=>mdout1_7_32, SD1=>rptr_11_ff2,
SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(32));
mux_2: MUX81
- port map (D0=>mdout1_0_33, D1=>mdout1_1_33, D2=>mdout1_2_33,
- D3=>mdout1_3_33, D4=>mdout1_4_33, D5=>mdout1_5_33,
- D6=>mdout1_6_33, D7=>mdout1_7_33, SD1=>rptr_11_ff2,
+ port map (D0=>mdout1_0_33, D1=>mdout1_1_33, D2=>mdout1_2_33,
+ D3=>mdout1_3_33, D4=>mdout1_4_33, D5=>mdout1_5_33,
+ D6=>mdout1_6_33, D7=>mdout1_7_33, SD1=>rptr_11_ff2,
SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(33));
mux_1: MUX81
- port map (D0=>mdout1_0_34, D1=>mdout1_1_34, D2=>mdout1_2_34,
- D3=>mdout1_3_34, D4=>mdout1_4_34, D5=>mdout1_5_34,
- D6=>mdout1_6_34, D7=>mdout1_7_34, SD1=>rptr_11_ff2,
+ port map (D0=>mdout1_0_34, D1=>mdout1_1_34, D2=>mdout1_2_34,
+ D3=>mdout1_3_34, D4=>mdout1_4_34, D5=>mdout1_5_34,
+ D6=>mdout1_6_34, D7=>mdout1_7_34, SD1=>rptr_11_ff2,
SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(34));
mux_0: MUX81
- port map (D0=>mdout1_0_35, D1=>mdout1_1_35, D2=>mdout1_2_35,
- D3=>mdout1_3_35, D4=>mdout1_4_35, D5=>mdout1_5_35,
- D6=>mdout1_6_35, D7=>mdout1_7_35, SD1=>rptr_11_ff2,
+ port map (D0=>mdout1_0_35, D1=>mdout1_1_35, D2=>mdout1_2_35,
+ D3=>mdout1_3_35, D4=>mdout1_4_35, D5=>mdout1_5_35,
+ D6=>mdout1_6_35, D7=>mdout1_7_35, SD1=>rptr_11_ff2,
SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(35));
wcnt_0: FSUB2B
- port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0,
+ port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0,
BI=>scuba_vlo, BOUT=>co0_5, S0=>open, S1=>wcnt_sub_0);
wcnt_1: FSUB2B
- port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2,
+ port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2,
BI=>co0_5, BOUT=>co1_5, S0=>wcnt_sub_1, S1=>wcnt_sub_2);
wcnt_2: FSUB2B
- port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4,
+ port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4,
BI=>co1_5, BOUT=>co2_5, S0=>wcnt_sub_3, S1=>wcnt_sub_4);
wcnt_3: FSUB2B
- port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6,
+ port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6,
BI=>co2_5, BOUT=>co3_5, S0=>wcnt_sub_5, S1=>wcnt_sub_6);
wcnt_4: FSUB2B
- port map (A0=>wcount_7, A1=>wcount_8, B0=>rptr_7, B1=>rptr_8,
+ port map (A0=>wcount_7, A1=>wcount_8, B0=>rptr_7, B1=>rptr_8,
BI=>co3_5, BOUT=>co4_5, S0=>wcnt_sub_7, S1=>wcnt_sub_8);
wcnt_5: FSUB2B
- port map (A0=>wcount_9, A1=>wcount_10, B0=>rptr_9, B1=>rptr_10,
+ port map (A0=>wcount_9, A1=>wcount_10, B0=>rptr_9, B1=>rptr_10,
BI=>co4_5, BOUT=>co5_5, S0=>wcnt_sub_9, S1=>wcnt_sub_10);
wcnt_6: FSUB2B
- port map (A0=>wcount_11, A1=>wcount_12, B0=>rptr_11, B1=>rptr_12,
+ port map (A0=>wcount_11, A1=>wcount_12, B0=>rptr_11, B1=>rptr_12,
BI=>co5_5, BOUT=>co6_5, S0=>wcnt_sub_11, S1=>wcnt_sub_12);
wcnt_7: FSUB2B
- port map (A0=>wcount_13, A1=>wcnt_sub_msb, B0=>rptr_13,
- B1=>scuba_vlo, BI=>co6_5, BOUT=>co7_3, S0=>wcnt_sub_13,
+ port map (A0=>wcount_13, A1=>wcnt_sub_msb, B0=>rptr_13,
+ B1=>scuba_vlo, BI=>co6_5, BOUT=>co7_3, S0=>wcnt_sub_13,
S1=>wcnt_sub_14);
wcntd: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
B1=>scuba_vlo, CI=>co7_3, COUT=>open, S0=>co7_3d, S1=>open);
af_set_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
+ port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open);
af_set_cmp_0: AGEB2
- port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0),
+ port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0),
B1=>AmFullThresh(1), CI=>cmp_ci_2, GE=>co0_6);
af_set_cmp_1: AGEB2
- port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2),
+ port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2),
B1=>AmFullThresh(3), CI=>co0_6, GE=>co1_6);
af_set_cmp_2: AGEB2
- port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4),
+ port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4),
B1=>AmFullThresh(5), CI=>co1_6, GE=>co2_6);
af_set_cmp_3: AGEB2
- port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6),
+ port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6),
B1=>AmFullThresh(7), CI=>co2_6, GE=>co3_6);
af_set_cmp_4: AGEB2
- port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8),
+ port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8),
B1=>AmFullThresh(9), CI=>co3_6, GE=>co4_6);
af_set_cmp_5: AGEB2
- port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10),
+ port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10),
B1=>AmFullThresh(11), CI=>co4_6, GE=>co5_6);
af_set_cmp_6: AGEB2
- port map (A0=>wcnt_reg_12, A1=>wcnt_reg_13, B0=>AmFullThresh(12),
+ port map (A0=>wcnt_reg_12, A1=>wcnt_reg_13, B0=>AmFullThresh(12),
B1=>AmFullThresh(13), CI=>co5_6, GE=>co6_6);
af_set_cmp_7: AGEB2
- port map (A0=>wcnt_reg_14, A1=>scuba_vlo, B0=>scuba_vlo,
+ port map (A0=>wcnt_reg_14, A1=>scuba_vlo, B0=>scuba_vlo,
B1=>scuba_vlo, CI=>co6_6, GE=>af_set_c);
scuba_vlo_inst: VLO
port map (Z=>scuba_vlo);
a2: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set,
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set,
S1=>open);
WCNT(0) <= fcount_0;
-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41)
-- Module Version: 4.7
---/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 32768 -width 36 -depth 32768 -regout -no_enable -pe -1 -pf 0 -fill -e
+--/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 32768 -width 36 -depth 32768 -regout -no_enable -pe -1 -pf 0 -fill -e
-- Wed Mar 31 11:46:41 2010
entity fifo_36x32k_oreg is
port (
- Data: in std_logic_vector(35 downto 0);
- Clock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- AmFullThresh: in std_logic_vector(14 downto 0);
- Q: out std_logic_vector(35 downto 0);
- WCNT: out std_logic_vector(15 downto 0);
- Empty: out std_logic;
- Full: out std_logic;
+ Data: in std_logic_vector(35 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ AmFullThresh: in std_logic_vector(14 downto 0);
+ Q: out std_logic_vector(35 downto 0);
+ WCNT: out std_logic_vector(15 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
AlmostFull: out std_logic);
end fifo_36x32k_oreg;
-- local component declarations
component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
B1: in std_logic; CI: in std_logic; GE: out std_logic);
end component;
component ALEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
B1: in std_logic; CI: in std_logic; LE: out std_logic);
end component;
component AND2
port (A: in std_logic; B: in std_logic; Z: out std_logic);
end component;
component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
end component;
component CB2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CON: in std_logic; CO: out std_logic; NC0: out std_logic;
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CON: in std_logic; CO: out std_logic; NC0: out std_logic;
NC1: out std_logic);
end component;
component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
S0: out std_logic; S1: out std_logic);
end component;
component FSUB2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; BI: in std_logic; BOUT: out std_logic;
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; BI: in std_logic; BOUT: out std_logic;
S0: out std_logic; S1: out std_logic);
end component;
component FD1P3BX
-- synopsys translate_off
generic (GSR : in String);
-- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
PD: in std_logic; Q: out std_logic);
end component;
component FD1P3DX
-- synopsys translate_off
generic (GSR : in String);
-- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
CD: in std_logic; Q: out std_logic);
end component;
component FD1S3BX
-- synopsys translate_off
generic (GSR : in String);
-- synopsys translate_on
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
Q: out std_logic);
end component;
component FD1S3DX
-- synopsys translate_off
generic (GSR : in String);
-- synopsys translate_on
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
Q: out std_logic);
end component;
component INV
port (A: in std_logic; Z: out std_logic);
end component;
component MUX161
- port (D0: in std_logic; D1: in std_logic; D2: in std_logic;
- D3: in std_logic; D4: in std_logic; D5: in std_logic;
- D6: in std_logic; D7: in std_logic; D8: in std_logic;
- D9: in std_logic; D10: in std_logic; D11: in std_logic;
- D12: in std_logic; D13: in std_logic; D14: in std_logic;
- D15: in std_logic; SD1: in std_logic; SD2: in std_logic;
+ port (D0: in std_logic; D1: in std_logic; D2: in std_logic;
+ D3: in std_logic; D4: in std_logic; D5: in std_logic;
+ D6: in std_logic; D7: in std_logic; D8: in std_logic;
+ D9: in std_logic; D10: in std_logic; D11: in std_logic;
+ D12: in std_logic; D13: in std_logic; D14: in std_logic;
+ D15: in std_logic; SD1: in std_logic; SD2: in std_logic;
SD3: in std_logic; SD4: in std_logic; Z: out std_logic);
end component;
component ROM16X1
-- synopsys translate_off
generic (initval : in String);
-- synopsys translate_on
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
AD0: in std_logic; DO0: out std_logic);
end component;
component VHI
end component;
component DP16KB
-- synopsys translate_off
- generic (GSR : in String; WRITEMODE_B : in String;
- CSDECODE_B : in std_logic_vector(2 downto 0);
- CSDECODE_A : in std_logic_vector(2 downto 0);
- WRITEMODE_A : in String; RESETMODE : in String;
- REGMODE_B : in String; REGMODE_A : in String;
+ generic (GSR : in String; WRITEMODE_B : in String;
+ CSDECODE_B : in std_logic_vector(2 downto 0);
+ CSDECODE_A : in std_logic_vector(2 downto 0);
+ WRITEMODE_A : in String; RESETMODE : in String;
+ REGMODE_B : in String; REGMODE_A : in String;
DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
-- synopsys translate_on
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
- CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
- CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
+ port (DIA0: in std_logic; DIA1: in std_logic;
+ DIA2: in std_logic; DIA3: in std_logic;
+ DIA4: in std_logic; DIA5: in std_logic;
+ DIA6: in std_logic; DIA7: in std_logic;
+ DIA8: in std_logic; DIA9: in std_logic;
+ DIA10: in std_logic; DIA11: in std_logic;
+ DIA12: in std_logic; DIA13: in std_logic;
+ DIA14: in std_logic; DIA15: in std_logic;
+ DIA16: in std_logic; DIA17: in std_logic;
+ ADA0: in std_logic; ADA1: in std_logic;
+ ADA2: in std_logic; ADA3: in std_logic;
+ ADA4: in std_logic; ADA5: in std_logic;
+ ADA6: in std_logic; ADA7: in std_logic;
+ ADA8: in std_logic; ADA9: in std_logic;
+ ADA10: in std_logic; ADA11: in std_logic;
+ ADA12: in std_logic; ADA13: in std_logic;
+ CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
+ CSA0: in std_logic; CSA1: in std_logic;
+ CSA2: in std_logic; RSTA: in std_logic;
+ DIB0: in std_logic; DIB1: in std_logic;
+ DIB2: in std_logic; DIB3: in std_logic;
+ DIB4: in std_logic; DIB5: in std_logic;
+ DIB6: in std_logic; DIB7: in std_logic;
+ DIB8: in std_logic; DIB9: in std_logic;
+ DIB10: in std_logic; DIB11: in std_logic;
+ DIB12: in std_logic; DIB13: in std_logic;
+ DIB14: in std_logic; DIB15: in std_logic;
+ DIB16: in std_logic; DIB17: in std_logic;
+ ADB0: in std_logic; ADB1: in std_logic;
+ ADB2: in std_logic; ADB3: in std_logic;
+ ADB4: in std_logic; ADB5: in std_logic;
+ ADB6: in std_logic; ADB7: in std_logic;
+ ADB8: in std_logic; ADB9: in std_logic;
+ ADB10: in std_logic; ADB11: in std_logic;
+ ADB12: in std_logic; ADB13: in std_logic;
+ CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
+ CSB0: in std_logic; CSB1: in std_logic;
+ CSB2: in std_logic; RSTB: in std_logic;
+ DOA0: out std_logic; DOA1: out std_logic;
+ DOA2: out std_logic; DOA3: out std_logic;
+ DOA4: out std_logic; DOA5: out std_logic;
+ DOA6: out std_logic; DOA7: out std_logic;
+ DOA8: out std_logic; DOA9: out std_logic;
+ DOA10: out std_logic; DOA11: out std_logic;
+ DOA12: out std_logic; DOA13: out std_logic;
+ DOA14: out std_logic; DOA15: out std_logic;
+ DOA16: out std_logic; DOA17: out std_logic;
+ DOB0: out std_logic; DOB1: out std_logic;
+ DOB2: out std_logic; DOB3: out std_logic;
+ DOB4: out std_logic; DOB5: out std_logic;
+ DOB6: out std_logic; DOB7: out std_logic;
+ DOB8: out std_logic; DOB9: out std_logic;
+ DOB10: out std_logic; DOB11: out std_logic;
+ DOB12: out std_logic; DOB13: out std_logic;
+ DOB14: out std_logic; DOB15: out std_logic;
DOB16: out std_logic; DOB17: out std_logic);
end component;
- attribute initval : string;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute CSDECODE_B : string;
- attribute CSDECODE_A : string;
- attribute WRITEMODE_B : string;
- attribute WRITEMODE_A : string;
- attribute RESETMODE : string;
- attribute REGMODE_B : string;
- attribute REGMODE_A : string;
- attribute DATA_WIDTH_B : string;
- attribute DATA_WIDTH_A : string;
- attribute GSR : string;
+ attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_B : string;
+ attribute CSDECODE_A : string;
+ attribute WRITEMODE_B : string;
+ attribute WRITEMODE_A : string;
+ attribute RESETMODE : string;
+ attribute REGMODE_B : string;
+ attribute REGMODE_A : string;
+ attribute DATA_WIDTH_B : string;
+ attribute DATA_WIDTH_A : string;
+ attribute GSR : string;
attribute initval of LUT4_129 : label is "0x3232";
attribute initval of LUT4_128 : label is "0x3232";
attribute initval of LUT4_127 : label is "0x8000";
-- synopsys translate_off
generic map (initval=> "0x3232")
-- synopsys translate_on
- port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
+ port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
AD0=>empty_i, DO0=>empty_d);
LUT4_128: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x3232")
-- synopsys translate_on
- port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
+ port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
AD0=>full_i, DO0=>full_d);
INV_9: INV
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
AD0=>wptr_14_inv, DO0=>dec0_p00);
INV_5: INV
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
AD0=>rptr_14_inv, DO0=>dec1_r10);
LUT4_125: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
AD0=>wptr_14_inv, DO0=>dec2_p00);
LUT4_124: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
AD0=>rptr_14_inv, DO0=>dec3_r10);
LUT4_123: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
AD0=>wptr_14_inv, DO0=>dec4_p00);
LUT4_122: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
AD0=>rptr_14_inv, DO0=>dec5_r10);
LUT4_121: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
AD0=>wptr_14_inv, DO0=>dec6_p00);
LUT4_120: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
AD0=>rptr_14_inv, DO0=>dec7_r10);
LUT4_119: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
AD0=>wptr_14_inv, DO0=>dec8_p01);
LUT4_118: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
AD0=>rptr_14_inv, DO0=>dec9_r11);
LUT4_117: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
AD0=>wptr_14_inv, DO0=>dec10_p01);
LUT4_116: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
AD0=>rptr_14_inv, DO0=>dec11_r11);
LUT4_115: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
AD0=>wptr_14_inv, DO0=>dec12_p01);
LUT4_114: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
AD0=>rptr_14_inv, DO0=>dec13_r11);
LUT4_113: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
AD0=>wptr_14_inv, DO0=>dec14_p01);
LUT4_112: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
AD0=>rptr_14_inv, DO0=>dec15_r11);
LUT4_111: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
AD0=>wptr_14_inv, DO0=>dec16_p02);
LUT4_110: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
AD0=>rptr_14_inv, DO0=>dec17_r12);
LUT4_109: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
AD0=>wptr_14_inv, DO0=>dec18_p02);
LUT4_108: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
AD0=>rptr_14_inv, DO0=>dec19_r12);
LUT4_107: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
AD0=>wptr_14_inv, DO0=>dec20_p02);
LUT4_106: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
AD0=>rptr_14_inv, DO0=>dec21_r12);
LUT4_105: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
AD0=>wptr_14_inv, DO0=>dec22_p02);
LUT4_104: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
AD0=>rptr_14_inv, DO0=>dec23_r12);
LUT4_103: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
AD0=>wptr_14_inv, DO0=>dec24_p03);
LUT4_102: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
AD0=>rptr_14_inv, DO0=>dec25_r13);
LUT4_101: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
AD0=>wptr_14_inv, DO0=>dec26_p03);
LUT4_100: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
AD0=>rptr_14_inv, DO0=>dec27_r13);
LUT4_99: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
AD0=>wptr_14_inv, DO0=>dec28_p03);
LUT4_98: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
AD0=>rptr_14_inv, DO0=>dec29_r13);
LUT4_97: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
AD0=>wptr_14_inv, DO0=>dec30_p03);
LUT4_96: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
AD0=>rptr_14_inv, DO0=>dec31_r13);
LUT4_95: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
AD0=>wptr_14_inv, DO0=>dec32_p04);
LUT4_94: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
AD0=>rptr_14_inv, DO0=>dec33_r14);
LUT4_93: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
AD0=>wptr_14_inv, DO0=>dec34_p04);
LUT4_92: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
AD0=>rptr_14_inv, DO0=>dec35_r14);
LUT4_91: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
AD0=>wptr_14_inv, DO0=>dec36_p04);
LUT4_90: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
AD0=>rptr_14_inv, DO0=>dec37_r14);
LUT4_89: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
AD0=>wptr_14_inv, DO0=>dec38_p04);
LUT4_88: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
AD0=>rptr_14_inv, DO0=>dec39_r14);
LUT4_87: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
AD0=>wptr_14_inv, DO0=>dec40_p05);
LUT4_86: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
AD0=>rptr_14_inv, DO0=>dec41_r15);
LUT4_85: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
AD0=>wptr_14_inv, DO0=>dec42_p05);
LUT4_84: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
AD0=>rptr_14_inv, DO0=>dec43_r15);
LUT4_83: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
AD0=>wptr_14_inv, DO0=>dec44_p05);
LUT4_82: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
AD0=>rptr_14_inv, DO0=>dec45_r15);
LUT4_81: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
AD0=>wptr_14_inv, DO0=>dec46_p05);
LUT4_80: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
AD0=>rptr_14_inv, DO0=>dec47_r15);
LUT4_79: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
AD0=>wptr_14_inv, DO0=>dec48_p06);
LUT4_78: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
AD0=>rptr_14_inv, DO0=>dec49_r16);
LUT4_77: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
AD0=>wptr_14_inv, DO0=>dec50_p06);
LUT4_76: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
AD0=>rptr_14_inv, DO0=>dec51_r16);
LUT4_75: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
AD0=>wptr_14_inv, DO0=>dec52_p06);
LUT4_74: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
AD0=>rptr_14_inv, DO0=>dec53_r16);
LUT4_73: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
AD0=>wptr_14_inv, DO0=>dec54_p06);
LUT4_72: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
AD0=>rptr_14_inv, DO0=>dec55_r16);
LUT4_71: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13,
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13,
AD0=>wptr_14_inv, DO0=>dec56_p07);
LUT4_70: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13,
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13,
AD0=>rptr_14_inv, DO0=>dec57_r17);
LUT4_69: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13,
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13,
AD0=>wptr_14_inv, DO0=>dec58_p07);
LUT4_68: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13,
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13,
AD0=>rptr_14_inv, DO0=>dec59_r17);
LUT4_67: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13,
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13,
AD0=>wptr_14_inv, DO0=>dec60_p07);
LUT4_66: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13,
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13,
AD0=>rptr_14_inv, DO0=>dec61_r17);
LUT4_65: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13,
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13,
AD0=>wptr_14_inv, DO0=>dec62_p07);
LUT4_64: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13,
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13,
AD0=>rptr_14_inv, DO0=>dec63_r17);
LUT4_63: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
AD0=>wptr_14, DO0=>dec64_p08);
LUT4_62: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
AD0=>rptr_14, DO0=>dec65_r18);
LUT4_61: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
AD0=>wptr_14, DO0=>dec66_p08);
LUT4_60: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
AD0=>rptr_14, DO0=>dec67_r18);
LUT4_59: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
AD0=>wptr_14, DO0=>dec68_p08);
LUT4_58: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
AD0=>rptr_14, DO0=>dec69_r18);
LUT4_57: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
AD0=>wptr_14, DO0=>dec70_p08);
LUT4_56: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
AD0=>rptr_14, DO0=>dec71_r18);
LUT4_55: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
AD0=>wptr_14, DO0=>dec72_p09);
LUT4_54: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
AD0=>rptr_14, DO0=>dec73_r19);
LUT4_53: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
AD0=>wptr_14, DO0=>dec74_p09);
LUT4_52: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
AD0=>rptr_14, DO0=>dec75_r19);
LUT4_51: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
AD0=>wptr_14, DO0=>dec76_p09);
LUT4_50: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
AD0=>rptr_14, DO0=>dec77_r19);
LUT4_49: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
AD0=>wptr_14, DO0=>dec78_p09);
LUT4_48: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
AD0=>rptr_14, DO0=>dec79_r19);
LUT4_47: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
AD0=>wptr_14, DO0=>dec80_p010);
LUT4_46: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
AD0=>rptr_14, DO0=>dec81_r110);
LUT4_45: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
AD0=>wptr_14, DO0=>dec82_p010);
LUT4_44: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
AD0=>rptr_14, DO0=>dec83_r110);
LUT4_43: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
AD0=>wptr_14, DO0=>dec84_p010);
LUT4_42: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
AD0=>rptr_14, DO0=>dec85_r110);
LUT4_41: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
AD0=>wptr_14, DO0=>dec86_p010);
LUT4_40: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
AD0=>rptr_14, DO0=>dec87_r110);
LUT4_39: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
AD0=>wptr_14, DO0=>dec88_p011);
LUT4_38: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
AD0=>rptr_14, DO0=>dec89_r111);
LUT4_37: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
AD0=>wptr_14, DO0=>dec90_p011);
LUT4_36: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
AD0=>rptr_14, DO0=>dec91_r111);
LUT4_35: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
AD0=>wptr_14, DO0=>dec92_p011);
LUT4_34: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
AD0=>rptr_14, DO0=>dec93_r111);
LUT4_33: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
AD0=>wptr_14, DO0=>dec94_p011);
LUT4_32: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
AD0=>rptr_14, DO0=>dec95_r111);
LUT4_31: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
AD0=>wptr_14, DO0=>dec96_p012);
LUT4_30: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
AD0=>rptr_14, DO0=>dec97_r112);
LUT4_29: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
AD0=>wptr_14, DO0=>dec98_p012);
LUT4_28: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
AD0=>rptr_14, DO0=>dec99_r112);
LUT4_27: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
AD0=>wptr_14, DO0=>dec100_p012);
LUT4_26: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
AD0=>rptr_14, DO0=>dec101_r112);
LUT4_25: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
AD0=>wptr_14, DO0=>dec102_p012);
LUT4_24: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
AD0=>rptr_14, DO0=>dec103_r112);
LUT4_23: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
AD0=>wptr_14, DO0=>dec104_p013);
LUT4_22: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
AD0=>rptr_14, DO0=>dec105_r113);
LUT4_21: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
AD0=>wptr_14, DO0=>dec106_p013);
LUT4_20: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
AD0=>rptr_14, DO0=>dec107_r113);
LUT4_19: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
AD0=>wptr_14, DO0=>dec108_p013);
LUT4_18: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
AD0=>rptr_14, DO0=>dec109_r113);
LUT4_17: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
AD0=>wptr_14, DO0=>dec110_p013);
LUT4_16: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
AD0=>rptr_14, DO0=>dec111_r113);
LUT4_15: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
AD0=>wptr_14, DO0=>dec112_p014);
LUT4_14: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
AD0=>rptr_14, DO0=>dec113_r114);
LUT4_13: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
AD0=>wptr_14, DO0=>dec114_p014);
LUT4_12: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
AD0=>rptr_14, DO0=>dec115_r114);
LUT4_11: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
AD0=>wptr_14, DO0=>dec116_p014);
LUT4_10: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
AD0=>rptr_14, DO0=>dec117_r114);
LUT4_9: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
AD0=>wptr_14, DO0=>dec118_p014);
LUT4_8: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
AD0=>rptr_14, DO0=>dec119_r114);
LUT4_7: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14,
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14,
DO0=>dec120_p015);
LUT4_6: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14,
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14,
DO0=>dec121_r115);
LUT4_5: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14,
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14,
DO0=>dec122_p015);
LUT4_4: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14,
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14,
DO0=>dec123_r115);
LUT4_3: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14,
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14,
DO0=>dec124_p015);
LUT4_2: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14,
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14,
DO0=>dec125_r115);
LUT4_1: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14,
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14,
DO0=>dec126_p015);
LUT4_0: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x8000")
-- synopsys translate_on
- port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14,
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14,
DO0=>dec127_r115);
AND2_t1: AND2
pdp_ram_0_0_63: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
- CSA0=>dec0_p00, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec1_r10,
- CSB1=>rden_i, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0,
- DOB1=>mdout1_0_1, DOB2=>mdout1_0_2, DOB3=>mdout1_0_3,
- DOB4=>mdout1_0_4, DOB5=>mdout1_0_5, DOB6=>mdout1_0_6,
- DOB7=>mdout1_0_7, DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA0=>dec0_p00, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec1_r10,
+ CSB1=>rden_i, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0,
+ DOB1=>mdout1_0_1, DOB2=>mdout1_0_2, DOB3=>mdout1_0_3,
+ DOB4=>mdout1_0_4, DOB5=>mdout1_0_5, DOB6=>mdout1_0_6,
+ DOB7=>mdout1_0_7, DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_0_1_62: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
- DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
- DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec2_p00, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>dec3_r10, CSB1=>rden_i, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_0_9, DOB1=>mdout1_0_10, DOB2=>mdout1_0_11,
- DOB3=>mdout1_0_12, DOB4=>mdout1_0_13, DOB5=>mdout1_0_14,
- DOB6=>mdout1_0_15, DOB7=>mdout1_0_16, DOB8=>mdout1_0_17,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
+ DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
+ DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec2_p00, CSA1=>scuba_vlo,
+ CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
+ ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
+ ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
+ ADB13=>rptr_10, CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>dec3_r10, CSB1=>rden_i, CSB2=>scuba_vlo, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_0_9, DOB1=>mdout1_0_10, DOB2=>mdout1_0_11,
+ DOB3=>mdout1_0_12, DOB4=>mdout1_0_13, DOB5=>mdout1_0_14,
+ DOB6=>mdout1_0_15, DOB7=>mdout1_0_16, DOB8=>mdout1_0_17,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_0_2_61: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
- DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
- DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec4_p00, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>dec5_r10, CSB1=>rden_i, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_0_18, DOB1=>mdout1_0_19, DOB2=>mdout1_0_20,
- DOB3=>mdout1_0_21, DOB4=>mdout1_0_22, DOB5=>mdout1_0_23,
- DOB6=>mdout1_0_24, DOB7=>mdout1_0_25, DOB8=>mdout1_0_26,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
+ DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
+ DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec4_p00, CSA1=>scuba_vlo,
+ CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
+ ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
+ ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
+ ADB13=>rptr_10, CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>dec5_r10, CSB1=>rden_i, CSB2=>scuba_vlo, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_0_18, DOB1=>mdout1_0_19, DOB2=>mdout1_0_20,
+ DOB3=>mdout1_0_21, DOB4=>mdout1_0_22, DOB5=>mdout1_0_23,
+ DOB6=>mdout1_0_24, DOB7=>mdout1_0_25, DOB8=>mdout1_0_26,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_0_3_60: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
- DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
- DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec6_p00, CSA1=>scuba_vlo,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>dec7_r10, CSB1=>rden_i, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_0_27, DOB1=>mdout1_0_28, DOB2=>mdout1_0_29,
- DOB3=>mdout1_0_30, DOB4=>mdout1_0_31, DOB5=>mdout1_0_32,
- DOB6=>mdout1_0_33, DOB7=>mdout1_0_34, DOB8=>mdout1_0_35,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
+ DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
+ DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec6_p00, CSA1=>scuba_vlo,
+ CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
+ ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
+ ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
+ ADB13=>rptr_10, CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>dec7_r10, CSB1=>rden_i, CSB2=>scuba_vlo, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_0_27, DOB1=>mdout1_0_28, DOB2=>mdout1_0_29,
+ DOB3=>mdout1_0_30, DOB4=>mdout1_0_31, DOB5=>mdout1_0_32,
+ DOB6=>mdout1_0_33, DOB7=>mdout1_0_34, DOB8=>mdout1_0_35,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_1_0_59: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
- CSA0=>dec8_p01, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec9_r11,
- CSB1=>rden_i, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0,
- DOB1=>mdout1_1_1, DOB2=>mdout1_1_2, DOB3=>mdout1_1_3,
- DOB4=>mdout1_1_4, DOB5=>mdout1_1_5, DOB6=>mdout1_1_6,
- DOB7=>mdout1_1_7, DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA0=>dec8_p01, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec9_r11,
+ CSB1=>rden_i, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0,
+ DOB1=>mdout1_1_1, DOB2=>mdout1_1_2, DOB3=>mdout1_1_3,
+ DOB4=>mdout1_1_4, DOB5=>mdout1_1_5, DOB6=>mdout1_1_6,
+ DOB7=>mdout1_1_7, DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_1_1_58: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
- DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
- DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec10_p01,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec11_r11, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_9,
- DOB1=>mdout1_1_10, DOB2=>mdout1_1_11, DOB3=>mdout1_1_12,
- DOB4=>mdout1_1_13, DOB5=>mdout1_1_14, DOB6=>mdout1_1_15,
- DOB7=>mdout1_1_16, DOB8=>mdout1_1_17, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
+ DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
+ DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec10_p01,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec11_r11, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_1_9,
+ DOB1=>mdout1_1_10, DOB2=>mdout1_1_11, DOB3=>mdout1_1_12,
+ DOB4=>mdout1_1_13, DOB5=>mdout1_1_14, DOB6=>mdout1_1_15,
+ DOB7=>mdout1_1_16, DOB8=>mdout1_1_17, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_1_2_57: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
- DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
- DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec12_p01,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec13_r11, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_18,
- DOB1=>mdout1_1_19, DOB2=>mdout1_1_20, DOB3=>mdout1_1_21,
- DOB4=>mdout1_1_22, DOB5=>mdout1_1_23, DOB6=>mdout1_1_24,
- DOB7=>mdout1_1_25, DOB8=>mdout1_1_26, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
+ DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
+ DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec12_p01,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec13_r11, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_1_18,
+ DOB1=>mdout1_1_19, DOB2=>mdout1_1_20, DOB3=>mdout1_1_21,
+ DOB4=>mdout1_1_22, DOB5=>mdout1_1_23, DOB6=>mdout1_1_24,
+ DOB7=>mdout1_1_25, DOB8=>mdout1_1_26, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_1_3_56: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
- DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
- DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec14_p01,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec15_r11, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_27,
- DOB1=>mdout1_1_28, DOB2=>mdout1_1_29, DOB3=>mdout1_1_30,
- DOB4=>mdout1_1_31, DOB5=>mdout1_1_32, DOB6=>mdout1_1_33,
- DOB7=>mdout1_1_34, DOB8=>mdout1_1_35, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
+ DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
+ DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec14_p01,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec15_r11, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_1_27,
+ DOB1=>mdout1_1_28, DOB2=>mdout1_1_29, DOB3=>mdout1_1_30,
+ DOB4=>mdout1_1_31, DOB5=>mdout1_1_32, DOB6=>mdout1_1_33,
+ DOB7=>mdout1_1_34, DOB8=>mdout1_1_35, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_2_0_55: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
- CSA0=>dec16_p02, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec17_r12,
- CSB1=>rden_i, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0,
- DOB1=>mdout1_2_1, DOB2=>mdout1_2_2, DOB3=>mdout1_2_3,
- DOB4=>mdout1_2_4, DOB5=>mdout1_2_5, DOB6=>mdout1_2_6,
- DOB7=>mdout1_2_7, DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA0=>dec16_p02, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec17_r12,
+ CSB1=>rden_i, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0,
+ DOB1=>mdout1_2_1, DOB2=>mdout1_2_2, DOB3=>mdout1_2_3,
+ DOB4=>mdout1_2_4, DOB5=>mdout1_2_5, DOB6=>mdout1_2_6,
+ DOB7=>mdout1_2_7, DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_2_1_54: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
- DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
- DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec18_p02,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec19_r12, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_9,
- DOB1=>mdout1_2_10, DOB2=>mdout1_2_11, DOB3=>mdout1_2_12,
- DOB4=>mdout1_2_13, DOB5=>mdout1_2_14, DOB6=>mdout1_2_15,
- DOB7=>mdout1_2_16, DOB8=>mdout1_2_17, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
+ DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
+ DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec18_p02,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec19_r12, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_2_9,
+ DOB1=>mdout1_2_10, DOB2=>mdout1_2_11, DOB3=>mdout1_2_12,
+ DOB4=>mdout1_2_13, DOB5=>mdout1_2_14, DOB6=>mdout1_2_15,
+ DOB7=>mdout1_2_16, DOB8=>mdout1_2_17, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_2_2_53: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
- DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
- DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec20_p02,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec21_r12, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_18,
- DOB1=>mdout1_2_19, DOB2=>mdout1_2_20, DOB3=>mdout1_2_21,
- DOB4=>mdout1_2_22, DOB5=>mdout1_2_23, DOB6=>mdout1_2_24,
- DOB7=>mdout1_2_25, DOB8=>mdout1_2_26, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
+ DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
+ DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec20_p02,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec21_r12, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_2_18,
+ DOB1=>mdout1_2_19, DOB2=>mdout1_2_20, DOB3=>mdout1_2_21,
+ DOB4=>mdout1_2_22, DOB5=>mdout1_2_23, DOB6=>mdout1_2_24,
+ DOB7=>mdout1_2_25, DOB8=>mdout1_2_26, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_2_3_52: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
- DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
- DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec22_p02,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec23_r12, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_27,
- DOB1=>mdout1_2_28, DOB2=>mdout1_2_29, DOB3=>mdout1_2_30,
- DOB4=>mdout1_2_31, DOB5=>mdout1_2_32, DOB6=>mdout1_2_33,
- DOB7=>mdout1_2_34, DOB8=>mdout1_2_35, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
+ DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
+ DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec22_p02,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec23_r12, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_2_27,
+ DOB1=>mdout1_2_28, DOB2=>mdout1_2_29, DOB3=>mdout1_2_30,
+ DOB4=>mdout1_2_31, DOB5=>mdout1_2_32, DOB6=>mdout1_2_33,
+ DOB7=>mdout1_2_34, DOB8=>mdout1_2_35, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_3_0_51: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
- CSA0=>dec24_p03, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec25_r13,
- CSB1=>rden_i, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0,
- DOB1=>mdout1_3_1, DOB2=>mdout1_3_2, DOB3=>mdout1_3_3,
- DOB4=>mdout1_3_4, DOB5=>mdout1_3_5, DOB6=>mdout1_3_6,
- DOB7=>mdout1_3_7, DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA0=>dec24_p03, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec25_r13,
+ CSB1=>rden_i, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0,
+ DOB1=>mdout1_3_1, DOB2=>mdout1_3_2, DOB3=>mdout1_3_3,
+ DOB4=>mdout1_3_4, DOB5=>mdout1_3_5, DOB6=>mdout1_3_6,
+ DOB7=>mdout1_3_7, DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_3_1_50: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
- DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
- DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec26_p03,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec27_r13, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_9,
- DOB1=>mdout1_3_10, DOB2=>mdout1_3_11, DOB3=>mdout1_3_12,
- DOB4=>mdout1_3_13, DOB5=>mdout1_3_14, DOB6=>mdout1_3_15,
- DOB7=>mdout1_3_16, DOB8=>mdout1_3_17, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
+ DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
+ DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec26_p03,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec27_r13, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_3_9,
+ DOB1=>mdout1_3_10, DOB2=>mdout1_3_11, DOB3=>mdout1_3_12,
+ DOB4=>mdout1_3_13, DOB5=>mdout1_3_14, DOB6=>mdout1_3_15,
+ DOB7=>mdout1_3_16, DOB8=>mdout1_3_17, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_3_2_49: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
- DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
- DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec28_p03,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec29_r13, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_18,
- DOB1=>mdout1_3_19, DOB2=>mdout1_3_20, DOB3=>mdout1_3_21,
- DOB4=>mdout1_3_22, DOB5=>mdout1_3_23, DOB6=>mdout1_3_24,
- DOB7=>mdout1_3_25, DOB8=>mdout1_3_26, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
+ DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
+ DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec28_p03,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec29_r13, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_3_18,
+ DOB1=>mdout1_3_19, DOB2=>mdout1_3_20, DOB3=>mdout1_3_21,
+ DOB4=>mdout1_3_22, DOB5=>mdout1_3_23, DOB6=>mdout1_3_24,
+ DOB7=>mdout1_3_25, DOB8=>mdout1_3_26, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_3_3_48: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
- DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
- DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec30_p03,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec31_r13, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_27,
- DOB1=>mdout1_3_28, DOB2=>mdout1_3_29, DOB3=>mdout1_3_30,
- DOB4=>mdout1_3_31, DOB5=>mdout1_3_32, DOB6=>mdout1_3_33,
- DOB7=>mdout1_3_34, DOB8=>mdout1_3_35, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
+ DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
+ DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec30_p03,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec31_r13, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_3_27,
+ DOB1=>mdout1_3_28, DOB2=>mdout1_3_29, DOB3=>mdout1_3_30,
+ DOB4=>mdout1_3_31, DOB5=>mdout1_3_32, DOB6=>mdout1_3_33,
+ DOB7=>mdout1_3_34, DOB8=>mdout1_3_35, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_4_0_47: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
- CSA0=>dec32_p04, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec33_r14,
- CSB1=>rden_i, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_4_0,
- DOB1=>mdout1_4_1, DOB2=>mdout1_4_2, DOB3=>mdout1_4_3,
- DOB4=>mdout1_4_4, DOB5=>mdout1_4_5, DOB6=>mdout1_4_6,
- DOB7=>mdout1_4_7, DOB8=>mdout1_4_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA0=>dec32_p04, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec33_r14,
+ CSB1=>rden_i, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_4_0,
+ DOB1=>mdout1_4_1, DOB2=>mdout1_4_2, DOB3=>mdout1_4_3,
+ DOB4=>mdout1_4_4, DOB5=>mdout1_4_5, DOB6=>mdout1_4_6,
+ DOB7=>mdout1_4_7, DOB8=>mdout1_4_8, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_4_1_46: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
- DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
- DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec34_p04,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec35_r14, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_4_9,
- DOB1=>mdout1_4_10, DOB2=>mdout1_4_11, DOB3=>mdout1_4_12,
- DOB4=>mdout1_4_13, DOB5=>mdout1_4_14, DOB6=>mdout1_4_15,
- DOB7=>mdout1_4_16, DOB8=>mdout1_4_17, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
+ DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
+ DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec34_p04,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec35_r14, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_4_9,
+ DOB1=>mdout1_4_10, DOB2=>mdout1_4_11, DOB3=>mdout1_4_12,
+ DOB4=>mdout1_4_13, DOB5=>mdout1_4_14, DOB6=>mdout1_4_15,
+ DOB7=>mdout1_4_16, DOB8=>mdout1_4_17, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_4_2_45: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
- DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
- DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec36_p04,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec37_r14, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_4_18,
- DOB1=>mdout1_4_19, DOB2=>mdout1_4_20, DOB3=>mdout1_4_21,
- DOB4=>mdout1_4_22, DOB5=>mdout1_4_23, DOB6=>mdout1_4_24,
- DOB7=>mdout1_4_25, DOB8=>mdout1_4_26, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
+ DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
+ DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec36_p04,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec37_r14, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_4_18,
+ DOB1=>mdout1_4_19, DOB2=>mdout1_4_20, DOB3=>mdout1_4_21,
+ DOB4=>mdout1_4_22, DOB5=>mdout1_4_23, DOB6=>mdout1_4_24,
+ DOB7=>mdout1_4_25, DOB8=>mdout1_4_26, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_4_3_44: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
- DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
- DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec38_p04,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec39_r14, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_4_27,
- DOB1=>mdout1_4_28, DOB2=>mdout1_4_29, DOB3=>mdout1_4_30,
- DOB4=>mdout1_4_31, DOB5=>mdout1_4_32, DOB6=>mdout1_4_33,
- DOB7=>mdout1_4_34, DOB8=>mdout1_4_35, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
+ DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
+ DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec38_p04,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec39_r14, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_4_27,
+ DOB1=>mdout1_4_28, DOB2=>mdout1_4_29, DOB3=>mdout1_4_30,
+ DOB4=>mdout1_4_31, DOB5=>mdout1_4_32, DOB6=>mdout1_4_33,
+ DOB7=>mdout1_4_34, DOB8=>mdout1_4_35, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_5_0_43: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
- CSA0=>dec40_p05, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec41_r15,
- CSB1=>rden_i, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_5_0,
- DOB1=>mdout1_5_1, DOB2=>mdout1_5_2, DOB3=>mdout1_5_3,
- DOB4=>mdout1_5_4, DOB5=>mdout1_5_5, DOB6=>mdout1_5_6,
- DOB7=>mdout1_5_7, DOB8=>mdout1_5_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA0=>dec40_p05, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec41_r15,
+ CSB1=>rden_i, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_5_0,
+ DOB1=>mdout1_5_1, DOB2=>mdout1_5_2, DOB3=>mdout1_5_3,
+ DOB4=>mdout1_5_4, DOB5=>mdout1_5_5, DOB6=>mdout1_5_6,
+ DOB7=>mdout1_5_7, DOB8=>mdout1_5_8, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_5_1_42: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
- DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
- DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec42_p05,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec43_r15, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_5_9,
- DOB1=>mdout1_5_10, DOB2=>mdout1_5_11, DOB3=>mdout1_5_12,
- DOB4=>mdout1_5_13, DOB5=>mdout1_5_14, DOB6=>mdout1_5_15,
- DOB7=>mdout1_5_16, DOB8=>mdout1_5_17, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
+ DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
+ DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec42_p05,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec43_r15, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_5_9,
+ DOB1=>mdout1_5_10, DOB2=>mdout1_5_11, DOB3=>mdout1_5_12,
+ DOB4=>mdout1_5_13, DOB5=>mdout1_5_14, DOB6=>mdout1_5_15,
+ DOB7=>mdout1_5_16, DOB8=>mdout1_5_17, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_5_2_41: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
- DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
- DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec44_p05,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec45_r15, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_5_18,
- DOB1=>mdout1_5_19, DOB2=>mdout1_5_20, DOB3=>mdout1_5_21,
- DOB4=>mdout1_5_22, DOB5=>mdout1_5_23, DOB6=>mdout1_5_24,
- DOB7=>mdout1_5_25, DOB8=>mdout1_5_26, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
+ DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
+ DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec44_p05,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec45_r15, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_5_18,
+ DOB1=>mdout1_5_19, DOB2=>mdout1_5_20, DOB3=>mdout1_5_21,
+ DOB4=>mdout1_5_22, DOB5=>mdout1_5_23, DOB6=>mdout1_5_24,
+ DOB7=>mdout1_5_25, DOB8=>mdout1_5_26, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_5_3_40: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
- DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
- DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec46_p05,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec47_r15, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_5_27,
- DOB1=>mdout1_5_28, DOB2=>mdout1_5_29, DOB3=>mdout1_5_30,
- DOB4=>mdout1_5_31, DOB5=>mdout1_5_32, DOB6=>mdout1_5_33,
- DOB7=>mdout1_5_34, DOB8=>mdout1_5_35, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
+ DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
+ DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec46_p05,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec47_r15, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_5_27,
+ DOB1=>mdout1_5_28, DOB2=>mdout1_5_29, DOB3=>mdout1_5_30,
+ DOB4=>mdout1_5_31, DOB5=>mdout1_5_32, DOB6=>mdout1_5_33,
+ DOB7=>mdout1_5_34, DOB8=>mdout1_5_35, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_6_0_39: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
- CSA0=>dec48_p06, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec49_r16,
- CSB1=>rden_i, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_6_0,
- DOB1=>mdout1_6_1, DOB2=>mdout1_6_2, DOB3=>mdout1_6_3,
- DOB4=>mdout1_6_4, DOB5=>mdout1_6_5, DOB6=>mdout1_6_6,
- DOB7=>mdout1_6_7, DOB8=>mdout1_6_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA0=>dec48_p06, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec49_r16,
+ CSB1=>rden_i, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_6_0,
+ DOB1=>mdout1_6_1, DOB2=>mdout1_6_2, DOB3=>mdout1_6_3,
+ DOB4=>mdout1_6_4, DOB5=>mdout1_6_5, DOB6=>mdout1_6_6,
+ DOB7=>mdout1_6_7, DOB8=>mdout1_6_8, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_6_1_38: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
- DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
- DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec50_p06,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec51_r16, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_6_9,
- DOB1=>mdout1_6_10, DOB2=>mdout1_6_11, DOB3=>mdout1_6_12,
- DOB4=>mdout1_6_13, DOB5=>mdout1_6_14, DOB6=>mdout1_6_15,
- DOB7=>mdout1_6_16, DOB8=>mdout1_6_17, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
+ DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
+ DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec50_p06,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec51_r16, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_6_9,
+ DOB1=>mdout1_6_10, DOB2=>mdout1_6_11, DOB3=>mdout1_6_12,
+ DOB4=>mdout1_6_13, DOB5=>mdout1_6_14, DOB6=>mdout1_6_15,
+ DOB7=>mdout1_6_16, DOB8=>mdout1_6_17, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_6_2_37: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
- DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
- DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec52_p06,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec53_r16, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_6_18,
- DOB1=>mdout1_6_19, DOB2=>mdout1_6_20, DOB3=>mdout1_6_21,
- DOB4=>mdout1_6_22, DOB5=>mdout1_6_23, DOB6=>mdout1_6_24,
- DOB7=>mdout1_6_25, DOB8=>mdout1_6_26, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
+ DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
+ DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec52_p06,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec53_r16, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_6_18,
+ DOB1=>mdout1_6_19, DOB2=>mdout1_6_20, DOB3=>mdout1_6_21,
+ DOB4=>mdout1_6_22, DOB5=>mdout1_6_23, DOB6=>mdout1_6_24,
+ DOB7=>mdout1_6_25, DOB8=>mdout1_6_26, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_6_3_36: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
- DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
- DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec54_p06,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec55_r16, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_6_27,
- DOB1=>mdout1_6_28, DOB2=>mdout1_6_29, DOB3=>mdout1_6_30,
- DOB4=>mdout1_6_31, DOB5=>mdout1_6_32, DOB6=>mdout1_6_33,
- DOB7=>mdout1_6_34, DOB8=>mdout1_6_35, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
+ DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
+ DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec54_p06,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec55_r16, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_6_27,
+ DOB1=>mdout1_6_28, DOB2=>mdout1_6_29, DOB3=>mdout1_6_30,
+ DOB4=>mdout1_6_31, DOB5=>mdout1_6_32, DOB6=>mdout1_6_33,
+ DOB7=>mdout1_6_34, DOB8=>mdout1_6_35, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_7_0_35: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
- CSA0=>dec56_p07, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec57_r17,
- CSB1=>rden_i, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_7_0,
- DOB1=>mdout1_7_1, DOB2=>mdout1_7_2, DOB3=>mdout1_7_3,
- DOB4=>mdout1_7_4, DOB5=>mdout1_7_5, DOB6=>mdout1_7_6,
- DOB7=>mdout1_7_7, DOB8=>mdout1_7_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA0=>dec56_p07, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec57_r17,
+ CSB1=>rden_i, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_7_0,
+ DOB1=>mdout1_7_1, DOB2=>mdout1_7_2, DOB3=>mdout1_7_3,
+ DOB4=>mdout1_7_4, DOB5=>mdout1_7_5, DOB6=>mdout1_7_6,
+ DOB7=>mdout1_7_7, DOB8=>mdout1_7_8, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_7_1_34: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
- DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
- DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec58_p07,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec59_r17, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_7_9,
- DOB1=>mdout1_7_10, DOB2=>mdout1_7_11, DOB3=>mdout1_7_12,
- DOB4=>mdout1_7_13, DOB5=>mdout1_7_14, DOB6=>mdout1_7_15,
- DOB7=>mdout1_7_16, DOB8=>mdout1_7_17, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
+ DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
+ DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec58_p07,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec59_r17, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_7_9,
+ DOB1=>mdout1_7_10, DOB2=>mdout1_7_11, DOB3=>mdout1_7_12,
+ DOB4=>mdout1_7_13, DOB5=>mdout1_7_14, DOB6=>mdout1_7_15,
+ DOB7=>mdout1_7_16, DOB8=>mdout1_7_17, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_7_2_33: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
- DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
- DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec60_p07,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec61_r17, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_7_18,
- DOB1=>mdout1_7_19, DOB2=>mdout1_7_20, DOB3=>mdout1_7_21,
- DOB4=>mdout1_7_22, DOB5=>mdout1_7_23, DOB6=>mdout1_7_24,
- DOB7=>mdout1_7_25, DOB8=>mdout1_7_26, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
+ DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
+ DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec60_p07,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec61_r17, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_7_18,
+ DOB1=>mdout1_7_19, DOB2=>mdout1_7_20, DOB3=>mdout1_7_21,
+ DOB4=>mdout1_7_22, DOB5=>mdout1_7_23, DOB6=>mdout1_7_24,
+ DOB7=>mdout1_7_25, DOB8=>mdout1_7_26, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_7_3_32: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
- DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
- DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec62_p07,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec63_r17, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_7_27,
- DOB1=>mdout1_7_28, DOB2=>mdout1_7_29, DOB3=>mdout1_7_30,
- DOB4=>mdout1_7_31, DOB5=>mdout1_7_32, DOB6=>mdout1_7_33,
- DOB7=>mdout1_7_34, DOB8=>mdout1_7_35, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
+ DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
+ DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec62_p07,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec63_r17, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_7_27,
+ DOB1=>mdout1_7_28, DOB2=>mdout1_7_29, DOB3=>mdout1_7_30,
+ DOB4=>mdout1_7_31, DOB5=>mdout1_7_32, DOB6=>mdout1_7_33,
+ DOB7=>mdout1_7_34, DOB8=>mdout1_7_35, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_8_0_31: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
- CSA0=>dec64_p08, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec65_r18,
- CSB1=>rden_i, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_8_0,
- DOB1=>mdout1_8_1, DOB2=>mdout1_8_2, DOB3=>mdout1_8_3,
- DOB4=>mdout1_8_4, DOB5=>mdout1_8_5, DOB6=>mdout1_8_6,
- DOB7=>mdout1_8_7, DOB8=>mdout1_8_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA0=>dec64_p08, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec65_r18,
+ CSB1=>rden_i, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_8_0,
+ DOB1=>mdout1_8_1, DOB2=>mdout1_8_2, DOB3=>mdout1_8_3,
+ DOB4=>mdout1_8_4, DOB5=>mdout1_8_5, DOB6=>mdout1_8_6,
+ DOB7=>mdout1_8_7, DOB8=>mdout1_8_8, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_8_1_30: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
- DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
- DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec66_p08,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec67_r18, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_8_9,
- DOB1=>mdout1_8_10, DOB2=>mdout1_8_11, DOB3=>mdout1_8_12,
- DOB4=>mdout1_8_13, DOB5=>mdout1_8_14, DOB6=>mdout1_8_15,
- DOB7=>mdout1_8_16, DOB8=>mdout1_8_17, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
+ DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
+ DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec66_p08,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec67_r18, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_8_9,
+ DOB1=>mdout1_8_10, DOB2=>mdout1_8_11, DOB3=>mdout1_8_12,
+ DOB4=>mdout1_8_13, DOB5=>mdout1_8_14, DOB6=>mdout1_8_15,
+ DOB7=>mdout1_8_16, DOB8=>mdout1_8_17, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_8_2_29: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
- DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
- DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec68_p08,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec69_r18, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_8_18,
- DOB1=>mdout1_8_19, DOB2=>mdout1_8_20, DOB3=>mdout1_8_21,
- DOB4=>mdout1_8_22, DOB5=>mdout1_8_23, DOB6=>mdout1_8_24,
- DOB7=>mdout1_8_25, DOB8=>mdout1_8_26, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
+ DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
+ DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec68_p08,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec69_r18, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_8_18,
+ DOB1=>mdout1_8_19, DOB2=>mdout1_8_20, DOB3=>mdout1_8_21,
+ DOB4=>mdout1_8_22, DOB5=>mdout1_8_23, DOB6=>mdout1_8_24,
+ DOB7=>mdout1_8_25, DOB8=>mdout1_8_26, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_8_3_28: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
- DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
- DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec70_p08,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec71_r18, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_8_27,
- DOB1=>mdout1_8_28, DOB2=>mdout1_8_29, DOB3=>mdout1_8_30,
- DOB4=>mdout1_8_31, DOB5=>mdout1_8_32, DOB6=>mdout1_8_33,
- DOB7=>mdout1_8_34, DOB8=>mdout1_8_35, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
+ DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
+ DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec70_p08,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec71_r18, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_8_27,
+ DOB1=>mdout1_8_28, DOB2=>mdout1_8_29, DOB3=>mdout1_8_30,
+ DOB4=>mdout1_8_31, DOB5=>mdout1_8_32, DOB6=>mdout1_8_33,
+ DOB7=>mdout1_8_34, DOB8=>mdout1_8_35, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_9_0_27: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
- CSA0=>dec72_p09, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec73_r19,
- CSB1=>rden_i, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
- DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
- DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
- DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
- DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_9_0,
- DOB1=>mdout1_9_1, DOB2=>mdout1_9_2, DOB3=>mdout1_9_3,
- DOB4=>mdout1_9_4, DOB5=>mdout1_9_5, DOB6=>mdout1_9_6,
- DOB7=>mdout1_9_7, DOB8=>mdout1_9_8, DOB9=>open, DOB10=>open,
- DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA0=>dec72_p09, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec73_r19,
+ CSB1=>rden_i, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>mdout1_9_0,
+ DOB1=>mdout1_9_1, DOB2=>mdout1_9_2, DOB3=>mdout1_9_3,
+ DOB4=>mdout1_9_4, DOB5=>mdout1_9_5, DOB6=>mdout1_9_6,
+ DOB7=>mdout1_9_7, DOB8=>mdout1_9_8, DOB9=>open, DOB10=>open,
+ DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open,
DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_9_1_26: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
- DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
- DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec74_p09,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec75_r19, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_9_9,
- DOB1=>mdout1_9_10, DOB2=>mdout1_9_11, DOB3=>mdout1_9_12,
- DOB4=>mdout1_9_13, DOB5=>mdout1_9_14, DOB6=>mdout1_9_15,
- DOB7=>mdout1_9_16, DOB8=>mdout1_9_17, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
+ DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
+ DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec74_p09,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec75_r19, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_9_9,
+ DOB1=>mdout1_9_10, DOB2=>mdout1_9_11, DOB3=>mdout1_9_12,
+ DOB4=>mdout1_9_13, DOB5=>mdout1_9_14, DOB6=>mdout1_9_15,
+ DOB7=>mdout1_9_16, DOB8=>mdout1_9_17, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_9_2_25: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
- DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
- DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec76_p09,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec77_r19, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_9_18,
- DOB1=>mdout1_9_19, DOB2=>mdout1_9_20, DOB3=>mdout1_9_21,
- DOB4=>mdout1_9_22, DOB5=>mdout1_9_23, DOB6=>mdout1_9_24,
- DOB7=>mdout1_9_25, DOB8=>mdout1_9_26, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
+ DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
+ DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec76_p09,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec77_r19, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_9_18,
+ DOB1=>mdout1_9_19, DOB2=>mdout1_9_20, DOB3=>mdout1_9_21,
+ DOB4=>mdout1_9_22, DOB5=>mdout1_9_23, DOB6=>mdout1_9_24,
+ DOB7=>mdout1_9_25, DOB8=>mdout1_9_26, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_9_3_24: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
- DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
- DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec78_p09,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec79_r19, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_9_27,
- DOB1=>mdout1_9_28, DOB2=>mdout1_9_29, DOB3=>mdout1_9_30,
- DOB4=>mdout1_9_31, DOB5=>mdout1_9_32, DOB6=>mdout1_9_33,
- DOB7=>mdout1_9_34, DOB8=>mdout1_9_35, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
+ DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
+ DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec78_p09,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec79_r19, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_9_27,
+ DOB1=>mdout1_9_28, DOB2=>mdout1_9_29, DOB3=>mdout1_9_30,
+ DOB4=>mdout1_9_31, DOB5=>mdout1_9_32, DOB6=>mdout1_9_33,
+ DOB7=>mdout1_9_34, DOB8=>mdout1_9_35, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_10_0_23: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
- CSA0=>dec80_p010, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>dec81_r110, CSB1=>rden_i, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_10_0, DOB1=>mdout1_10_1, DOB2=>mdout1_10_2,
- DOB3=>mdout1_10_3, DOB4=>mdout1_10_4, DOB5=>mdout1_10_5,
- DOB6=>mdout1_10_6, DOB7=>mdout1_10_7, DOB8=>mdout1_10_8,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA0=>dec80_p010, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>dec81_r110, CSB1=>rden_i, CSB2=>scuba_vlo, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_10_0, DOB1=>mdout1_10_1, DOB2=>mdout1_10_2,
+ DOB3=>mdout1_10_3, DOB4=>mdout1_10_4, DOB5=>mdout1_10_5,
+ DOB6=>mdout1_10_6, DOB7=>mdout1_10_7, DOB8=>mdout1_10_8,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_10_1_22: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
- DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
- DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec82_p010,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec83_r110, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_10_9,
- DOB1=>mdout1_10_10, DOB2=>mdout1_10_11, DOB3=>mdout1_10_12,
- DOB4=>mdout1_10_13, DOB5=>mdout1_10_14, DOB6=>mdout1_10_15,
- DOB7=>mdout1_10_16, DOB8=>mdout1_10_17, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
+ DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
+ DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec82_p010,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec83_r110, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_10_9,
+ DOB1=>mdout1_10_10, DOB2=>mdout1_10_11, DOB3=>mdout1_10_12,
+ DOB4=>mdout1_10_13, DOB5=>mdout1_10_14, DOB6=>mdout1_10_15,
+ DOB7=>mdout1_10_16, DOB8=>mdout1_10_17, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_10_2_21: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
- DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
- DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec84_p010,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec85_r110, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_10_18,
- DOB1=>mdout1_10_19, DOB2=>mdout1_10_20, DOB3=>mdout1_10_21,
- DOB4=>mdout1_10_22, DOB5=>mdout1_10_23, DOB6=>mdout1_10_24,
- DOB7=>mdout1_10_25, DOB8=>mdout1_10_26, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
+ DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
+ DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec84_p010,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec85_r110, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_10_18,
+ DOB1=>mdout1_10_19, DOB2=>mdout1_10_20, DOB3=>mdout1_10_21,
+ DOB4=>mdout1_10_22, DOB5=>mdout1_10_23, DOB6=>mdout1_10_24,
+ DOB7=>mdout1_10_25, DOB8=>mdout1_10_26, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_10_3_20: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
- DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
- DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec86_p010,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec87_r110, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_10_27,
- DOB1=>mdout1_10_28, DOB2=>mdout1_10_29, DOB3=>mdout1_10_30,
- DOB4=>mdout1_10_31, DOB5=>mdout1_10_32, DOB6=>mdout1_10_33,
- DOB7=>mdout1_10_34, DOB8=>mdout1_10_35, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
+ DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
+ DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec86_p010,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec87_r110, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_10_27,
+ DOB1=>mdout1_10_28, DOB2=>mdout1_10_29, DOB3=>mdout1_10_30,
+ DOB4=>mdout1_10_31, DOB5=>mdout1_10_32, DOB6=>mdout1_10_33,
+ DOB7=>mdout1_10_34, DOB8=>mdout1_10_35, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_11_0_19: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
- CSA0=>dec88_p011, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>dec89_r111, CSB1=>rden_i, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_11_0, DOB1=>mdout1_11_1, DOB2=>mdout1_11_2,
- DOB3=>mdout1_11_3, DOB4=>mdout1_11_4, DOB5=>mdout1_11_5,
- DOB6=>mdout1_11_6, DOB7=>mdout1_11_7, DOB8=>mdout1_11_8,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA0=>dec88_p011, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>dec89_r111, CSB1=>rden_i, CSB2=>scuba_vlo, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_11_0, DOB1=>mdout1_11_1, DOB2=>mdout1_11_2,
+ DOB3=>mdout1_11_3, DOB4=>mdout1_11_4, DOB5=>mdout1_11_5,
+ DOB6=>mdout1_11_6, DOB7=>mdout1_11_7, DOB8=>mdout1_11_8,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_11_1_18: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
- DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
- DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec90_p011,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec91_r111, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_11_9,
- DOB1=>mdout1_11_10, DOB2=>mdout1_11_11, DOB3=>mdout1_11_12,
- DOB4=>mdout1_11_13, DOB5=>mdout1_11_14, DOB6=>mdout1_11_15,
- DOB7=>mdout1_11_16, DOB8=>mdout1_11_17, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
+ DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
+ DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec90_p011,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec91_r111, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_11_9,
+ DOB1=>mdout1_11_10, DOB2=>mdout1_11_11, DOB3=>mdout1_11_12,
+ DOB4=>mdout1_11_13, DOB5=>mdout1_11_14, DOB6=>mdout1_11_15,
+ DOB7=>mdout1_11_16, DOB8=>mdout1_11_17, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_11_2_17: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
- DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
- DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec92_p011,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec93_r111, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_11_18,
- DOB1=>mdout1_11_19, DOB2=>mdout1_11_20, DOB3=>mdout1_11_21,
- DOB4=>mdout1_11_22, DOB5=>mdout1_11_23, DOB6=>mdout1_11_24,
- DOB7=>mdout1_11_25, DOB8=>mdout1_11_26, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
+ DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
+ DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec92_p011,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec93_r111, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_11_18,
+ DOB1=>mdout1_11_19, DOB2=>mdout1_11_20, DOB3=>mdout1_11_21,
+ DOB4=>mdout1_11_22, DOB5=>mdout1_11_23, DOB6=>mdout1_11_24,
+ DOB7=>mdout1_11_25, DOB8=>mdout1_11_26, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_11_3_16: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
- DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
- DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec94_p011,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec95_r111, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_11_27,
- DOB1=>mdout1_11_28, DOB2=>mdout1_11_29, DOB3=>mdout1_11_30,
- DOB4=>mdout1_11_31, DOB5=>mdout1_11_32, DOB6=>mdout1_11_33,
- DOB7=>mdout1_11_34, DOB8=>mdout1_11_35, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
+ DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
+ DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec94_p011,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec95_r111, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_11_27,
+ DOB1=>mdout1_11_28, DOB2=>mdout1_11_29, DOB3=>mdout1_11_30,
+ DOB4=>mdout1_11_31, DOB5=>mdout1_11_32, DOB6=>mdout1_11_33,
+ DOB7=>mdout1_11_34, DOB8=>mdout1_11_35, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_12_0_15: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
- CSA0=>dec96_p012, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>dec97_r112, CSB1=>rden_i, CSB2=>scuba_vlo, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_12_0, DOB1=>mdout1_12_1, DOB2=>mdout1_12_2,
- DOB3=>mdout1_12_3, DOB4=>mdout1_12_4, DOB5=>mdout1_12_5,
- DOB6=>mdout1_12_6, DOB7=>mdout1_12_7, DOB8=>mdout1_12_8,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA0=>dec96_p012, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>dec97_r112, CSB1=>rden_i, CSB2=>scuba_vlo, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_12_0, DOB1=>mdout1_12_1, DOB2=>mdout1_12_2,
+ DOB3=>mdout1_12_3, DOB4=>mdout1_12_4, DOB5=>mdout1_12_5,
+ DOB6=>mdout1_12_6, DOB7=>mdout1_12_7, DOB8=>mdout1_12_8,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_12_1_14: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
- DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
- DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec98_p012,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec99_r112, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_12_9,
- DOB1=>mdout1_12_10, DOB2=>mdout1_12_11, DOB3=>mdout1_12_12,
- DOB4=>mdout1_12_13, DOB5=>mdout1_12_14, DOB6=>mdout1_12_15,
- DOB7=>mdout1_12_16, DOB8=>mdout1_12_17, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
+ DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
+ DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec98_p012,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec99_r112, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_12_9,
+ DOB1=>mdout1_12_10, DOB2=>mdout1_12_11, DOB3=>mdout1_12_12,
+ DOB4=>mdout1_12_13, DOB5=>mdout1_12_14, DOB6=>mdout1_12_15,
+ DOB7=>mdout1_12_16, DOB8=>mdout1_12_17, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_12_2_13: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
- DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
- DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec100_p012,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec101_r112, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_12_18,
- DOB1=>mdout1_12_19, DOB2=>mdout1_12_20, DOB3=>mdout1_12_21,
- DOB4=>mdout1_12_22, DOB5=>mdout1_12_23, DOB6=>mdout1_12_24,
- DOB7=>mdout1_12_25, DOB8=>mdout1_12_26, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
+ DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
+ DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec100_p012,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec101_r112, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_12_18,
+ DOB1=>mdout1_12_19, DOB2=>mdout1_12_20, DOB3=>mdout1_12_21,
+ DOB4=>mdout1_12_22, DOB5=>mdout1_12_23, DOB6=>mdout1_12_24,
+ DOB7=>mdout1_12_25, DOB8=>mdout1_12_26, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_12_3_12: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
- DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
- DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec102_p012,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec103_r112, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_12_27,
- DOB1=>mdout1_12_28, DOB2=>mdout1_12_29, DOB3=>mdout1_12_30,
- DOB4=>mdout1_12_31, DOB5=>mdout1_12_32, DOB6=>mdout1_12_33,
- DOB7=>mdout1_12_34, DOB8=>mdout1_12_35, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
+ DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
+ DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec102_p012,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec103_r112, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_12_27,
+ DOB1=>mdout1_12_28, DOB2=>mdout1_12_29, DOB3=>mdout1_12_30,
+ DOB4=>mdout1_12_31, DOB5=>mdout1_12_32, DOB6=>mdout1_12_33,
+ DOB7=>mdout1_12_34, DOB8=>mdout1_12_35, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_13_0_11: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
- CSA0=>dec104_p013, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>dec105_r113, CSB1=>rden_i, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_13_0, DOB1=>mdout1_13_1,
- DOB2=>mdout1_13_2, DOB3=>mdout1_13_3, DOB4=>mdout1_13_4,
- DOB5=>mdout1_13_5, DOB6=>mdout1_13_6, DOB7=>mdout1_13_7,
- DOB8=>mdout1_13_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA0=>dec104_p013, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>dec105_r113, CSB1=>rden_i, CSB2=>scuba_vlo,
+ RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
+ DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
+ DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
+ DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
+ DOA17=>open, DOB0=>mdout1_13_0, DOB1=>mdout1_13_1,
+ DOB2=>mdout1_13_2, DOB3=>mdout1_13_3, DOB4=>mdout1_13_4,
+ DOB5=>mdout1_13_5, DOB6=>mdout1_13_6, DOB7=>mdout1_13_7,
+ DOB8=>mdout1_13_8, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
DOB16=>open, DOB17=>open);
pdp_ram_13_1_10: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
- DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
- DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec106_p013,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec107_r113, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_13_9,
- DOB1=>mdout1_13_10, DOB2=>mdout1_13_11, DOB3=>mdout1_13_12,
- DOB4=>mdout1_13_13, DOB5=>mdout1_13_14, DOB6=>mdout1_13_15,
- DOB7=>mdout1_13_16, DOB8=>mdout1_13_17, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
+ DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
+ DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec106_p013,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec107_r113, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_13_9,
+ DOB1=>mdout1_13_10, DOB2=>mdout1_13_11, DOB3=>mdout1_13_12,
+ DOB4=>mdout1_13_13, DOB5=>mdout1_13_14, DOB6=>mdout1_13_15,
+ DOB7=>mdout1_13_16, DOB8=>mdout1_13_17, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_13_2_9: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
- DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
- DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec108_p013,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec109_r113, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_13_18,
- DOB1=>mdout1_13_19, DOB2=>mdout1_13_20, DOB3=>mdout1_13_21,
- DOB4=>mdout1_13_22, DOB5=>mdout1_13_23, DOB6=>mdout1_13_24,
- DOB7=>mdout1_13_25, DOB8=>mdout1_13_26, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
+ DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
+ DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec108_p013,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec109_r113, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_13_18,
+ DOB1=>mdout1_13_19, DOB2=>mdout1_13_20, DOB3=>mdout1_13_21,
+ DOB4=>mdout1_13_22, DOB5=>mdout1_13_23, DOB6=>mdout1_13_24,
+ DOB7=>mdout1_13_25, DOB8=>mdout1_13_26, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_13_3_8: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
- DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
- DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec110_p013,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec111_r113, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_13_27,
- DOB1=>mdout1_13_28, DOB2=>mdout1_13_29, DOB3=>mdout1_13_30,
- DOB4=>mdout1_13_31, DOB5=>mdout1_13_32, DOB6=>mdout1_13_33,
- DOB7=>mdout1_13_34, DOB8=>mdout1_13_35, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
+ DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
+ DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec110_p013,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec111_r113, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_13_27,
+ DOB1=>mdout1_13_28, DOB2=>mdout1_13_29, DOB3=>mdout1_13_30,
+ DOB4=>mdout1_13_31, DOB5=>mdout1_13_32, DOB6=>mdout1_13_33,
+ DOB7=>mdout1_13_34, DOB8=>mdout1_13_35, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_14_0_7: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
- CSA0=>dec112_p014, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>dec113_r114, CSB1=>rden_i, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_14_0, DOB1=>mdout1_14_1,
- DOB2=>mdout1_14_2, DOB3=>mdout1_14_3, DOB4=>mdout1_14_4,
- DOB5=>mdout1_14_5, DOB6=>mdout1_14_6, DOB7=>mdout1_14_7,
- DOB8=>mdout1_14_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA0=>dec112_p014, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>dec113_r114, CSB1=>rden_i, CSB2=>scuba_vlo,
+ RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
+ DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
+ DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
+ DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
+ DOA17=>open, DOB0=>mdout1_14_0, DOB1=>mdout1_14_1,
+ DOB2=>mdout1_14_2, DOB3=>mdout1_14_3, DOB4=>mdout1_14_4,
+ DOB5=>mdout1_14_5, DOB6=>mdout1_14_6, DOB7=>mdout1_14_7,
+ DOB8=>mdout1_14_8, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
DOB16=>open, DOB17=>open);
pdp_ram_14_1_6: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
- DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
- DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec114_p014,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec115_r114, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_14_9,
- DOB1=>mdout1_14_10, DOB2=>mdout1_14_11, DOB3=>mdout1_14_12,
- DOB4=>mdout1_14_13, DOB5=>mdout1_14_14, DOB6=>mdout1_14_15,
- DOB7=>mdout1_14_16, DOB8=>mdout1_14_17, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
+ DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
+ DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec114_p014,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec115_r114, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_14_9,
+ DOB1=>mdout1_14_10, DOB2=>mdout1_14_11, DOB3=>mdout1_14_12,
+ DOB4=>mdout1_14_13, DOB5=>mdout1_14_14, DOB6=>mdout1_14_15,
+ DOB7=>mdout1_14_16, DOB8=>mdout1_14_17, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_14_2_5: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
- DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
- DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec116_p014,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec117_r114, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_14_18,
- DOB1=>mdout1_14_19, DOB2=>mdout1_14_20, DOB3=>mdout1_14_21,
- DOB4=>mdout1_14_22, DOB5=>mdout1_14_23, DOB6=>mdout1_14_24,
- DOB7=>mdout1_14_25, DOB8=>mdout1_14_26, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
+ DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
+ DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec116_p014,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec117_r114, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_14_18,
+ DOB1=>mdout1_14_19, DOB2=>mdout1_14_20, DOB3=>mdout1_14_21,
+ DOB4=>mdout1_14_22, DOB5=>mdout1_14_23, DOB6=>mdout1_14_24,
+ DOB7=>mdout1_14_25, DOB8=>mdout1_14_26, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_14_3_4: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
- DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
- DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec118_p014,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec119_r114, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_14_27,
- DOB1=>mdout1_14_28, DOB2=>mdout1_14_29, DOB3=>mdout1_14_30,
- DOB4=>mdout1_14_31, DOB5=>mdout1_14_32, DOB6=>mdout1_14_33,
- DOB7=>mdout1_14_34, DOB8=>mdout1_14_35, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
+ DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
+ DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec118_p014,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec119_r114, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_14_27,
+ DOB1=>mdout1_14_28, DOB2=>mdout1_14_29, DOB3=>mdout1_14_30,
+ DOB4=>mdout1_14_31, DOB5=>mdout1_14_32, DOB6=>mdout1_14_33,
+ DOB7=>mdout1_14_34, DOB8=>mdout1_14_35, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_15_0_3: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
- CSA0=>dec120_p015, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
- ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
- ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
- CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>dec121_r115, CSB1=>rden_i, CSB2=>scuba_vlo,
- RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
- DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
- DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
- DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
- DOA17=>open, DOB0=>mdout1_15_0, DOB1=>mdout1_15_1,
- DOB2=>mdout1_15_2, DOB3=>mdout1_15_3, DOB4=>mdout1_15_4,
- DOB5=>mdout1_15_5, DOB6=>mdout1_15_6, DOB7=>mdout1_15_7,
- DOB8=>mdout1_15_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA0=>dec120_p015, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2,
+ ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6,
+ ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10,
+ CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>dec121_r115, CSB1=>rden_i, CSB2=>scuba_vlo,
+ RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
+ DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
+ DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
+ DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
+ DOA17=>open, DOB0=>mdout1_15_0, DOB1=>mdout1_15_1,
+ DOB2=>mdout1_15_2, DOB3=>mdout1_15_3, DOB4=>mdout1_15_4,
+ DOB5=>mdout1_15_5, DOB6=>mdout1_15_6, DOB7=>mdout1_15_7,
+ DOB8=>mdout1_15_8, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
DOB16=>open, DOB17=>open);
pdp_ram_15_1_2: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
- DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
- DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec122_p015,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec123_r115, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_15_9,
- DOB1=>mdout1_15_10, DOB2=>mdout1_15_11, DOB3=>mdout1_15_12,
- DOB4=>mdout1_15_13, DOB5=>mdout1_15_14, DOB6=>mdout1_15_15,
- DOB7=>mdout1_15_16, DOB8=>mdout1_15_17, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
+ DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
+ DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec122_p015,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec123_r115, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_15_9,
+ DOB1=>mdout1_15_10, DOB2=>mdout1_15_11, DOB3=>mdout1_15_12,
+ DOB4=>mdout1_15_13, DOB5=>mdout1_15_14, DOB6=>mdout1_15_15,
+ DOB7=>mdout1_15_16, DOB8=>mdout1_15_17, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_15_2_1: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
- DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
- DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec124_p015,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec125_r115, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_15_18,
- DOB1=>mdout1_15_19, DOB2=>mdout1_15_20, DOB3=>mdout1_15_21,
- DOB4=>mdout1_15_22, DOB5=>mdout1_15_23, DOB6=>mdout1_15_24,
- DOB7=>mdout1_15_25, DOB8=>mdout1_15_26, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
+ DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
+ DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec124_p015,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec125_r115, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_15_18,
+ DOB1=>mdout1_15_19, DOB2=>mdout1_15_20, DOB3=>mdout1_15_21,
+ DOB4=>mdout1_15_22, DOB5=>mdout1_15_23, DOB6=>mdout1_15_24,
+ DOB7=>mdout1_15_25, DOB8=>mdout1_15_26, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
pdp_ram_15_3_0: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
- DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
- DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec126_p015,
- CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec127_r115, CSB1=>rden_i,
- CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_15_27,
- DOB1=>mdout1_15_28, DOB2=>mdout1_15_29, DOB3=>mdout1_15_30,
- DOB4=>mdout1_15_31, DOB5=>mdout1_15_32, DOB6=>mdout1_15_33,
- DOB7=>mdout1_15_34, DOB8=>mdout1_15_35, DOB9=>open,
- DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
+ port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
+ DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
+ DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>dec126_p015,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>dec127_r115, CSB1=>rden_i,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_15_27,
+ DOB1=>mdout1_15_28, DOB2=>mdout1_15_29, DOB3=>mdout1_15_30,
+ DOB4=>mdout1_15_31, DOB5=>mdout1_15_32, DOB6=>mdout1_15_33,
+ DOB7=>mdout1_15_34, DOB8=>mdout1_15_35, DOB9=>open,
+ DOB10=>open, DOB11=>open, DOB12=>open, DOB13=>open,
DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open);
FF_106: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_0);
FF_105: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_1);
FF_104: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_2);
FF_103: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_3);
FF_102: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_4);
FF_101: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_5);
FF_100: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_6);
FF_99: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_7);
FF_98: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_8);
FF_97: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_9);
FF_96: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_10);
FF_95: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_11);
FF_94: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_12, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_12, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_12);
FF_93: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_13, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_13, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_13);
FF_92: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_14, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_14, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_14);
FF_91: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_15, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_15, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_15);
FF_90: FD1S3BX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset,
+ port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset,
Q=>wcount_0);
FF_87: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_1);
FF_86: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_2);
FF_85: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_3);
FF_84: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_4);
FF_83: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_5);
FF_82: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_6);
FF_81: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_7);
FF_80: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_8);
FF_79: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_9);
FF_78: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_10);
FF_77: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_11);
FF_76: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_12, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_12, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_12);
FF_75: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_13, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_13, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_13);
FF_74: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_14, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_14, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_14);
FF_73: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_15, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_15, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_15);
FF_72: FD1P3BX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset,
+ port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset,
Q=>rcount_0);
FF_71: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_1);
FF_70: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_2);
FF_69: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_3);
FF_68: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_4);
FF_67: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_5);
FF_66: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_6);
FF_65: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_7);
FF_64: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_8);
FF_63: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_9);
FF_62: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_10);
FF_61: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_11);
FF_60: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_12, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_12, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_12);
FF_59: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_13, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_13, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_13);
FF_58: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_14, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_14, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_14);
FF_57: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_15, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_15, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_15);
FF_56: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_0);
FF_55: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_1);
FF_54: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_2);
FF_53: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_3);
FF_52: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_4);
FF_51: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_5);
FF_50: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_6);
FF_49: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_7);
FF_48: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_8);
FF_47: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_9);
FF_46: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_10);
FF_45: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_11, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_11, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_11);
FF_44: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_12, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_12, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_12);
FF_43: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_13, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_13, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_13);
FF_42: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_14, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_14, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_14);
FF_41: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_15, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_15, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_15);
FF_40: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_0);
FF_39: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_1);
FF_38: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_2);
FF_37: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_3);
FF_36: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_4);
FF_35: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_5);
FF_34: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_6);
FF_33: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_7);
FF_32: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_8);
FF_31: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_9);
FF_30: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_10);
FF_29: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_11, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_11, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_11);
FF_28: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_12, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_12, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_12);
FF_27: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_13, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_13, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_13);
FF_26: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_14, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_14, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_14);
FF_25: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_15, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_15, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_15);
FF_24: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rptr_11, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ port map (D=>rptr_11, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
Q=>rptr_11_ff);
FF_23: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rptr_12, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ port map (D=>rptr_12, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
Q=>rptr_12_ff);
FF_22: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rptr_13, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ port map (D=>rptr_13, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
Q=>rptr_13_ff);
FF_21: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rptr_14, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ port map (D=>rptr_14, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
Q=>rptr_14_ff);
+--changed SP from rden_i to '1'
FF_20: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rptr_11_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ port map (D=>rptr_11_ff, SP=>'1', CK=>Clock, CD=>scuba_vlo,
Q=>rptr_11_ff2);
FF_19: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rptr_12_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ port map (D=>rptr_12_ff, SP=>'1', CK=>Clock, CD=>scuba_vlo,
Q=>rptr_12_ff2);
FF_18: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rptr_13_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ port map (D=>rptr_13_ff, SP=>'1', CK=>Clock, CD=>scuba_vlo,
Q=>rptr_13_ff2);
FF_17: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rptr_14_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ port map (D=>rptr_14_ff, SP=>'1', CK=>Clock, CD=>scuba_vlo,
Q=>rptr_14_ff2);
+
+
FF_16: FD1S3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull);
bdcnt_bctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con,
+ port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con,
CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open);
bdcnt_bctr_0: CB2
- port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1,
+ port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1,
CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1);
bdcnt_bctr_1: CB2
- port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con,
+ port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con,
CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3);
bdcnt_bctr_2: CB2
- port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con,
+ port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con,
CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5);
bdcnt_bctr_3: CB2
- port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con,
+ port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con,
CO=>co3, NC0=>ifcount_6, NC1=>ifcount_7);
bdcnt_bctr_4: CB2
- port map (CI=>co3, PC0=>fcount_8, PC1=>fcount_9, CON=>cnt_con,
+ port map (CI=>co3, PC0=>fcount_8, PC1=>fcount_9, CON=>cnt_con,
CO=>co4, NC0=>ifcount_8, NC1=>ifcount_9);
bdcnt_bctr_5: CB2
- port map (CI=>co4, PC0=>fcount_10, PC1=>fcount_11, CON=>cnt_con,
+ port map (CI=>co4, PC0=>fcount_10, PC1=>fcount_11, CON=>cnt_con,
CO=>co5, NC0=>ifcount_10, NC1=>ifcount_11);
bdcnt_bctr_6: CB2
- port map (CI=>co5, PC0=>fcount_12, PC1=>fcount_13, CON=>cnt_con,
+ port map (CI=>co5, PC0=>fcount_12, PC1=>fcount_13, CON=>cnt_con,
CO=>co6, NC0=>ifcount_12, NC1=>ifcount_13);
bdcnt_bctr_7: CB2
- port map (CI=>co6, PC0=>fcount_14, PC1=>fcount_15, CON=>cnt_con,
+ port map (CI=>co6, PC0=>fcount_14, PC1=>fcount_15, CON=>cnt_con,
CO=>co7, NC0=>ifcount_14, NC1=>ifcount_15);
e_cmp_ci_a: FADD2B
- port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open,
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open,
S1=>open);
e_cmp_0: ALEB2
- port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo,
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo,
CI=>cmp_ci, LE=>co0_1);
e_cmp_1: ALEB2
- port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo,
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo,
B1=>scuba_vlo, CI=>co0_1, LE=>co1_1);
e_cmp_2: ALEB2
- port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo,
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo,
B1=>scuba_vlo, CI=>co1_1, LE=>co2_1);
e_cmp_3: ALEB2
- port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo,
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo,
B1=>scuba_vlo, CI=>co2_1, LE=>co3_1);
e_cmp_4: ALEB2
- port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo,
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo,
B1=>scuba_vlo, CI=>co3_1, LE=>co4_1);
e_cmp_5: ALEB2
- port map (A0=>fcount_10, A1=>fcount_11, B0=>scuba_vlo,
+ port map (A0=>fcount_10, A1=>fcount_11, B0=>scuba_vlo,
B1=>scuba_vlo, CI=>co4_1, LE=>co5_1);
e_cmp_6: ALEB2
- port map (A0=>fcount_12, A1=>fcount_13, B0=>scuba_vlo,
+ port map (A0=>fcount_12, A1=>fcount_13, B0=>scuba_vlo,
B1=>scuba_vlo, CI=>co5_1, LE=>co6_1);
e_cmp_7: ALEB2
- port map (A0=>fcount_14, A1=>fcount_15, B0=>scuba_vlo,
+ port map (A0=>fcount_14, A1=>fcount_15, B0=>scuba_vlo,
B1=>scuba_vlo, CI=>co6_1, LE=>cmp_le_1_c);
a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1,
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1,
S1=>open);
g_cmp_ci_a: FADD2B
- port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open,
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open,
S1=>open);
g_cmp_0: AGEB2
- port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i,
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i,
CI=>cmp_ci_1, GE=>co0_2);
g_cmp_1: AGEB2
- port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i,
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i,
CI=>co0_2, GE=>co1_2);
g_cmp_2: AGEB2
- port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i,
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i,
CI=>co1_2, GE=>co2_2);
g_cmp_3: AGEB2
- port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i,
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i,
CI=>co2_2, GE=>co3_2);
g_cmp_4: AGEB2
- port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i,
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i,
CI=>co3_2, GE=>co4_2);
g_cmp_5: AGEB2
- port map (A0=>fcount_10, A1=>fcount_11, B0=>wren_i, B1=>wren_i,
+ port map (A0=>fcount_10, A1=>fcount_11, B0=>wren_i, B1=>wren_i,
CI=>co4_2, GE=>co5_2);
g_cmp_6: AGEB2
- port map (A0=>fcount_12, A1=>fcount_13, B0=>wren_i, B1=>wren_i,
+ port map (A0=>fcount_12, A1=>fcount_13, B0=>wren_i, B1=>wren_i,
CI=>co5_2, GE=>co6_2);
g_cmp_7: AGEB2
- port map (A0=>fcount_14, A1=>fcount_15, B0=>wren_i,
+ port map (A0=>fcount_14, A1=>fcount_15, B0=>wren_i,
B1=>wren_i_inv, CI=>co6_2, GE=>cmp_ge_d1_c);
a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1,
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1,
S1=>open);
w_ctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open,
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open,
S1=>open);
w_ctr_0: CU2
- port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3,
+ port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3,
NC0=>iwcount_0, NC1=>iwcount_1);
w_ctr_1: CU2
- port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3,
+ port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3,
NC0=>iwcount_2, NC1=>iwcount_3);
w_ctr_2: CU2
- port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3,
+ port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3,
NC0=>iwcount_4, NC1=>iwcount_5);
w_ctr_3: CU2
- port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3,
+ port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3,
NC0=>iwcount_6, NC1=>iwcount_7);
w_ctr_4: CU2
- port map (CI=>co3_3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4_3,
+ port map (CI=>co3_3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4_3,
NC0=>iwcount_8, NC1=>iwcount_9);
w_ctr_5: CU2
- port map (CI=>co4_3, PC0=>wcount_10, PC1=>wcount_11, CO=>co5_3,
+ port map (CI=>co4_3, PC0=>wcount_10, PC1=>wcount_11, CO=>co5_3,
NC0=>iwcount_10, NC1=>iwcount_11);
w_ctr_6: CU2
- port map (CI=>co5_3, PC0=>wcount_12, PC1=>wcount_13, CO=>co6_3,
+ port map (CI=>co5_3, PC0=>wcount_12, PC1=>wcount_13, CO=>co6_3,
NC0=>iwcount_12, NC1=>iwcount_13);
w_ctr_7: CU2
- port map (CI=>co6_3, PC0=>wcount_14, PC1=>wcount_15, CO=>co7_1,
+ port map (CI=>co6_3, PC0=>wcount_14, PC1=>wcount_15, CO=>co7_1,
NC0=>iwcount_14, NC1=>iwcount_15);
scuba_vhi_inst: VHI
port map (Z=>scuba_vhi);
r_ctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open,
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open,
S1=>open);
r_ctr_0: CU2
- port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4,
+ port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4,
NC0=>ircount_0, NC1=>ircount_1);
r_ctr_1: CU2
- port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4,
+ port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4,
NC0=>ircount_2, NC1=>ircount_3);
r_ctr_2: CU2
- port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4,
+ port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4,
NC0=>ircount_4, NC1=>ircount_5);
r_ctr_3: CU2
- port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4,
+ port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4,
NC0=>ircount_6, NC1=>ircount_7);
r_ctr_4: CU2
- port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_4,
+ port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_4,
NC0=>ircount_8, NC1=>ircount_9);
r_ctr_5: CU2
- port map (CI=>co4_4, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_4,
+ port map (CI=>co4_4, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_4,
NC0=>ircount_10, NC1=>ircount_11);
r_ctr_6: CU2
- port map (CI=>co5_4, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_4,
+ port map (CI=>co5_4, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_4,
NC0=>ircount_12, NC1=>ircount_13);
r_ctr_7: CU2
- port map (CI=>co6_4, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_2,
+ port map (CI=>co6_4, PC0=>rcount_14, PC1=>rcount_15, CO=>co7_2,
NC0=>ircount_14, NC1=>ircount_15);
mux_35: MUX161
- port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0,
- D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0,
- D6=>mdout1_6_0, D7=>mdout1_7_0, D8=>mdout1_8_0,
- D9=>mdout1_9_0, D10=>mdout1_10_0, D11=>mdout1_11_0,
- D12=>mdout1_12_0, D13=>mdout1_13_0, D14=>mdout1_14_0,
- D15=>mdout1_15_0, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0,
+ D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0,
+ D6=>mdout1_6_0, D7=>mdout1_7_0, D8=>mdout1_8_0,
+ D9=>mdout1_9_0, D10=>mdout1_10_0, D11=>mdout1_11_0,
+ D12=>mdout1_12_0, D13=>mdout1_13_0, D14=>mdout1_14_0,
+ D15=>mdout1_15_0, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(0));
mux_34: MUX161
- port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1,
- D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1,
- D6=>mdout1_6_1, D7=>mdout1_7_1, D8=>mdout1_8_1,
- D9=>mdout1_9_1, D10=>mdout1_10_1, D11=>mdout1_11_1,
- D12=>mdout1_12_1, D13=>mdout1_13_1, D14=>mdout1_14_1,
- D15=>mdout1_15_1, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1,
+ D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1,
+ D6=>mdout1_6_1, D7=>mdout1_7_1, D8=>mdout1_8_1,
+ D9=>mdout1_9_1, D10=>mdout1_10_1, D11=>mdout1_11_1,
+ D12=>mdout1_12_1, D13=>mdout1_13_1, D14=>mdout1_14_1,
+ D15=>mdout1_15_1, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(1));
mux_33: MUX161
- port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2,
- D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2,
- D6=>mdout1_6_2, D7=>mdout1_7_2, D8=>mdout1_8_2,
- D9=>mdout1_9_2, D10=>mdout1_10_2, D11=>mdout1_11_2,
- D12=>mdout1_12_2, D13=>mdout1_13_2, D14=>mdout1_14_2,
- D15=>mdout1_15_2, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2,
+ D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2,
+ D6=>mdout1_6_2, D7=>mdout1_7_2, D8=>mdout1_8_2,
+ D9=>mdout1_9_2, D10=>mdout1_10_2, D11=>mdout1_11_2,
+ D12=>mdout1_12_2, D13=>mdout1_13_2, D14=>mdout1_14_2,
+ D15=>mdout1_15_2, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(2));
mux_32: MUX161
- port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3,
- D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3,
- D6=>mdout1_6_3, D7=>mdout1_7_3, D8=>mdout1_8_3,
- D9=>mdout1_9_3, D10=>mdout1_10_3, D11=>mdout1_11_3,
- D12=>mdout1_12_3, D13=>mdout1_13_3, D14=>mdout1_14_3,
- D15=>mdout1_15_3, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3,
+ D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3,
+ D6=>mdout1_6_3, D7=>mdout1_7_3, D8=>mdout1_8_3,
+ D9=>mdout1_9_3, D10=>mdout1_10_3, D11=>mdout1_11_3,
+ D12=>mdout1_12_3, D13=>mdout1_13_3, D14=>mdout1_14_3,
+ D15=>mdout1_15_3, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(3));
mux_31: MUX161
- port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4,
- D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4,
- D6=>mdout1_6_4, D7=>mdout1_7_4, D8=>mdout1_8_4,
- D9=>mdout1_9_4, D10=>mdout1_10_4, D11=>mdout1_11_4,
- D12=>mdout1_12_4, D13=>mdout1_13_4, D14=>mdout1_14_4,
- D15=>mdout1_15_4, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4,
+ D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4,
+ D6=>mdout1_6_4, D7=>mdout1_7_4, D8=>mdout1_8_4,
+ D9=>mdout1_9_4, D10=>mdout1_10_4, D11=>mdout1_11_4,
+ D12=>mdout1_12_4, D13=>mdout1_13_4, D14=>mdout1_14_4,
+ D15=>mdout1_15_4, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(4));
mux_30: MUX161
- port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5,
- D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5,
- D6=>mdout1_6_5, D7=>mdout1_7_5, D8=>mdout1_8_5,
- D9=>mdout1_9_5, D10=>mdout1_10_5, D11=>mdout1_11_5,
- D12=>mdout1_12_5, D13=>mdout1_13_5, D14=>mdout1_14_5,
- D15=>mdout1_15_5, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5,
+ D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5,
+ D6=>mdout1_6_5, D7=>mdout1_7_5, D8=>mdout1_8_5,
+ D9=>mdout1_9_5, D10=>mdout1_10_5, D11=>mdout1_11_5,
+ D12=>mdout1_12_5, D13=>mdout1_13_5, D14=>mdout1_14_5,
+ D15=>mdout1_15_5, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(5));
mux_29: MUX161
- port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6,
- D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6,
- D6=>mdout1_6_6, D7=>mdout1_7_6, D8=>mdout1_8_6,
- D9=>mdout1_9_6, D10=>mdout1_10_6, D11=>mdout1_11_6,
- D12=>mdout1_12_6, D13=>mdout1_13_6, D14=>mdout1_14_6,
- D15=>mdout1_15_6, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6,
+ D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6,
+ D6=>mdout1_6_6, D7=>mdout1_7_6, D8=>mdout1_8_6,
+ D9=>mdout1_9_6, D10=>mdout1_10_6, D11=>mdout1_11_6,
+ D12=>mdout1_12_6, D13=>mdout1_13_6, D14=>mdout1_14_6,
+ D15=>mdout1_15_6, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(6));
mux_28: MUX161
- port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7,
- D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7,
- D6=>mdout1_6_7, D7=>mdout1_7_7, D8=>mdout1_8_7,
- D9=>mdout1_9_7, D10=>mdout1_10_7, D11=>mdout1_11_7,
- D12=>mdout1_12_7, D13=>mdout1_13_7, D14=>mdout1_14_7,
- D15=>mdout1_15_7, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7,
+ D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7,
+ D6=>mdout1_6_7, D7=>mdout1_7_7, D8=>mdout1_8_7,
+ D9=>mdout1_9_7, D10=>mdout1_10_7, D11=>mdout1_11_7,
+ D12=>mdout1_12_7, D13=>mdout1_13_7, D14=>mdout1_14_7,
+ D15=>mdout1_15_7, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(7));
mux_27: MUX161
- port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8,
- D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8,
- D6=>mdout1_6_8, D7=>mdout1_7_8, D8=>mdout1_8_8,
- D9=>mdout1_9_8, D10=>mdout1_10_8, D11=>mdout1_11_8,
- D12=>mdout1_12_8, D13=>mdout1_13_8, D14=>mdout1_14_8,
- D15=>mdout1_15_8, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8,
+ D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8,
+ D6=>mdout1_6_8, D7=>mdout1_7_8, D8=>mdout1_8_8,
+ D9=>mdout1_9_8, D10=>mdout1_10_8, D11=>mdout1_11_8,
+ D12=>mdout1_12_8, D13=>mdout1_13_8, D14=>mdout1_14_8,
+ D15=>mdout1_15_8, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(8));
mux_26: MUX161
- port map (D0=>mdout1_0_9, D1=>mdout1_1_9, D2=>mdout1_2_9,
- D3=>mdout1_3_9, D4=>mdout1_4_9, D5=>mdout1_5_9,
- D6=>mdout1_6_9, D7=>mdout1_7_9, D8=>mdout1_8_9,
- D9=>mdout1_9_9, D10=>mdout1_10_9, D11=>mdout1_11_9,
- D12=>mdout1_12_9, D13=>mdout1_13_9, D14=>mdout1_14_9,
- D15=>mdout1_15_9, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_9, D1=>mdout1_1_9, D2=>mdout1_2_9,
+ D3=>mdout1_3_9, D4=>mdout1_4_9, D5=>mdout1_5_9,
+ D6=>mdout1_6_9, D7=>mdout1_7_9, D8=>mdout1_8_9,
+ D9=>mdout1_9_9, D10=>mdout1_10_9, D11=>mdout1_11_9,
+ D12=>mdout1_12_9, D13=>mdout1_13_9, D14=>mdout1_14_9,
+ D15=>mdout1_15_9, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(9));
mux_25: MUX161
- port map (D0=>mdout1_0_10, D1=>mdout1_1_10, D2=>mdout1_2_10,
- D3=>mdout1_3_10, D4=>mdout1_4_10, D5=>mdout1_5_10,
- D6=>mdout1_6_10, D7=>mdout1_7_10, D8=>mdout1_8_10,
- D9=>mdout1_9_10, D10=>mdout1_10_10, D11=>mdout1_11_10,
- D12=>mdout1_12_10, D13=>mdout1_13_10, D14=>mdout1_14_10,
- D15=>mdout1_15_10, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_10, D1=>mdout1_1_10, D2=>mdout1_2_10,
+ D3=>mdout1_3_10, D4=>mdout1_4_10, D5=>mdout1_5_10,
+ D6=>mdout1_6_10, D7=>mdout1_7_10, D8=>mdout1_8_10,
+ D9=>mdout1_9_10, D10=>mdout1_10_10, D11=>mdout1_11_10,
+ D12=>mdout1_12_10, D13=>mdout1_13_10, D14=>mdout1_14_10,
+ D15=>mdout1_15_10, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(10));
mux_24: MUX161
- port map (D0=>mdout1_0_11, D1=>mdout1_1_11, D2=>mdout1_2_11,
- D3=>mdout1_3_11, D4=>mdout1_4_11, D5=>mdout1_5_11,
- D6=>mdout1_6_11, D7=>mdout1_7_11, D8=>mdout1_8_11,
- D9=>mdout1_9_11, D10=>mdout1_10_11, D11=>mdout1_11_11,
- D12=>mdout1_12_11, D13=>mdout1_13_11, D14=>mdout1_14_11,
- D15=>mdout1_15_11, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_11, D1=>mdout1_1_11, D2=>mdout1_2_11,
+ D3=>mdout1_3_11, D4=>mdout1_4_11, D5=>mdout1_5_11,
+ D6=>mdout1_6_11, D7=>mdout1_7_11, D8=>mdout1_8_11,
+ D9=>mdout1_9_11, D10=>mdout1_10_11, D11=>mdout1_11_11,
+ D12=>mdout1_12_11, D13=>mdout1_13_11, D14=>mdout1_14_11,
+ D15=>mdout1_15_11, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(11));
mux_23: MUX161
- port map (D0=>mdout1_0_12, D1=>mdout1_1_12, D2=>mdout1_2_12,
- D3=>mdout1_3_12, D4=>mdout1_4_12, D5=>mdout1_5_12,
- D6=>mdout1_6_12, D7=>mdout1_7_12, D8=>mdout1_8_12,
- D9=>mdout1_9_12, D10=>mdout1_10_12, D11=>mdout1_11_12,
- D12=>mdout1_12_12, D13=>mdout1_13_12, D14=>mdout1_14_12,
- D15=>mdout1_15_12, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_12, D1=>mdout1_1_12, D2=>mdout1_2_12,
+ D3=>mdout1_3_12, D4=>mdout1_4_12, D5=>mdout1_5_12,
+ D6=>mdout1_6_12, D7=>mdout1_7_12, D8=>mdout1_8_12,
+ D9=>mdout1_9_12, D10=>mdout1_10_12, D11=>mdout1_11_12,
+ D12=>mdout1_12_12, D13=>mdout1_13_12, D14=>mdout1_14_12,
+ D15=>mdout1_15_12, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(12));
mux_22: MUX161
- port map (D0=>mdout1_0_13, D1=>mdout1_1_13, D2=>mdout1_2_13,
- D3=>mdout1_3_13, D4=>mdout1_4_13, D5=>mdout1_5_13,
- D6=>mdout1_6_13, D7=>mdout1_7_13, D8=>mdout1_8_13,
- D9=>mdout1_9_13, D10=>mdout1_10_13, D11=>mdout1_11_13,
- D12=>mdout1_12_13, D13=>mdout1_13_13, D14=>mdout1_14_13,
- D15=>mdout1_15_13, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_13, D1=>mdout1_1_13, D2=>mdout1_2_13,
+ D3=>mdout1_3_13, D4=>mdout1_4_13, D5=>mdout1_5_13,
+ D6=>mdout1_6_13, D7=>mdout1_7_13, D8=>mdout1_8_13,
+ D9=>mdout1_9_13, D10=>mdout1_10_13, D11=>mdout1_11_13,
+ D12=>mdout1_12_13, D13=>mdout1_13_13, D14=>mdout1_14_13,
+ D15=>mdout1_15_13, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(13));
mux_21: MUX161
- port map (D0=>mdout1_0_14, D1=>mdout1_1_14, D2=>mdout1_2_14,
- D3=>mdout1_3_14, D4=>mdout1_4_14, D5=>mdout1_5_14,
- D6=>mdout1_6_14, D7=>mdout1_7_14, D8=>mdout1_8_14,
- D9=>mdout1_9_14, D10=>mdout1_10_14, D11=>mdout1_11_14,
- D12=>mdout1_12_14, D13=>mdout1_13_14, D14=>mdout1_14_14,
- D15=>mdout1_15_14, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_14, D1=>mdout1_1_14, D2=>mdout1_2_14,
+ D3=>mdout1_3_14, D4=>mdout1_4_14, D5=>mdout1_5_14,
+ D6=>mdout1_6_14, D7=>mdout1_7_14, D8=>mdout1_8_14,
+ D9=>mdout1_9_14, D10=>mdout1_10_14, D11=>mdout1_11_14,
+ D12=>mdout1_12_14, D13=>mdout1_13_14, D14=>mdout1_14_14,
+ D15=>mdout1_15_14, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(14));
mux_20: MUX161
- port map (D0=>mdout1_0_15, D1=>mdout1_1_15, D2=>mdout1_2_15,
- D3=>mdout1_3_15, D4=>mdout1_4_15, D5=>mdout1_5_15,
- D6=>mdout1_6_15, D7=>mdout1_7_15, D8=>mdout1_8_15,
- D9=>mdout1_9_15, D10=>mdout1_10_15, D11=>mdout1_11_15,
- D12=>mdout1_12_15, D13=>mdout1_13_15, D14=>mdout1_14_15,
- D15=>mdout1_15_15, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_15, D1=>mdout1_1_15, D2=>mdout1_2_15,
+ D3=>mdout1_3_15, D4=>mdout1_4_15, D5=>mdout1_5_15,
+ D6=>mdout1_6_15, D7=>mdout1_7_15, D8=>mdout1_8_15,
+ D9=>mdout1_9_15, D10=>mdout1_10_15, D11=>mdout1_11_15,
+ D12=>mdout1_12_15, D13=>mdout1_13_15, D14=>mdout1_14_15,
+ D15=>mdout1_15_15, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(15));
mux_19: MUX161
- port map (D0=>mdout1_0_16, D1=>mdout1_1_16, D2=>mdout1_2_16,
- D3=>mdout1_3_16, D4=>mdout1_4_16, D5=>mdout1_5_16,
- D6=>mdout1_6_16, D7=>mdout1_7_16, D8=>mdout1_8_16,
- D9=>mdout1_9_16, D10=>mdout1_10_16, D11=>mdout1_11_16,
- D12=>mdout1_12_16, D13=>mdout1_13_16, D14=>mdout1_14_16,
- D15=>mdout1_15_16, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_16, D1=>mdout1_1_16, D2=>mdout1_2_16,
+ D3=>mdout1_3_16, D4=>mdout1_4_16, D5=>mdout1_5_16,
+ D6=>mdout1_6_16, D7=>mdout1_7_16, D8=>mdout1_8_16,
+ D9=>mdout1_9_16, D10=>mdout1_10_16, D11=>mdout1_11_16,
+ D12=>mdout1_12_16, D13=>mdout1_13_16, D14=>mdout1_14_16,
+ D15=>mdout1_15_16, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(16));
mux_18: MUX161
- port map (D0=>mdout1_0_17, D1=>mdout1_1_17, D2=>mdout1_2_17,
- D3=>mdout1_3_17, D4=>mdout1_4_17, D5=>mdout1_5_17,
- D6=>mdout1_6_17, D7=>mdout1_7_17, D8=>mdout1_8_17,
- D9=>mdout1_9_17, D10=>mdout1_10_17, D11=>mdout1_11_17,
- D12=>mdout1_12_17, D13=>mdout1_13_17, D14=>mdout1_14_17,
- D15=>mdout1_15_17, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_17, D1=>mdout1_1_17, D2=>mdout1_2_17,
+ D3=>mdout1_3_17, D4=>mdout1_4_17, D5=>mdout1_5_17,
+ D6=>mdout1_6_17, D7=>mdout1_7_17, D8=>mdout1_8_17,
+ D9=>mdout1_9_17, D10=>mdout1_10_17, D11=>mdout1_11_17,
+ D12=>mdout1_12_17, D13=>mdout1_13_17, D14=>mdout1_14_17,
+ D15=>mdout1_15_17, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(17));
mux_17: MUX161
- port map (D0=>mdout1_0_18, D1=>mdout1_1_18, D2=>mdout1_2_18,
- D3=>mdout1_3_18, D4=>mdout1_4_18, D5=>mdout1_5_18,
- D6=>mdout1_6_18, D7=>mdout1_7_18, D8=>mdout1_8_18,
- D9=>mdout1_9_18, D10=>mdout1_10_18, D11=>mdout1_11_18,
- D12=>mdout1_12_18, D13=>mdout1_13_18, D14=>mdout1_14_18,
- D15=>mdout1_15_18, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_18, D1=>mdout1_1_18, D2=>mdout1_2_18,
+ D3=>mdout1_3_18, D4=>mdout1_4_18, D5=>mdout1_5_18,
+ D6=>mdout1_6_18, D7=>mdout1_7_18, D8=>mdout1_8_18,
+ D9=>mdout1_9_18, D10=>mdout1_10_18, D11=>mdout1_11_18,
+ D12=>mdout1_12_18, D13=>mdout1_13_18, D14=>mdout1_14_18,
+ D15=>mdout1_15_18, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(18));
mux_16: MUX161
- port map (D0=>mdout1_0_19, D1=>mdout1_1_19, D2=>mdout1_2_19,
- D3=>mdout1_3_19, D4=>mdout1_4_19, D5=>mdout1_5_19,
- D6=>mdout1_6_19, D7=>mdout1_7_19, D8=>mdout1_8_19,
- D9=>mdout1_9_19, D10=>mdout1_10_19, D11=>mdout1_11_19,
- D12=>mdout1_12_19, D13=>mdout1_13_19, D14=>mdout1_14_19,
- D15=>mdout1_15_19, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_19, D1=>mdout1_1_19, D2=>mdout1_2_19,
+ D3=>mdout1_3_19, D4=>mdout1_4_19, D5=>mdout1_5_19,
+ D6=>mdout1_6_19, D7=>mdout1_7_19, D8=>mdout1_8_19,
+ D9=>mdout1_9_19, D10=>mdout1_10_19, D11=>mdout1_11_19,
+ D12=>mdout1_12_19, D13=>mdout1_13_19, D14=>mdout1_14_19,
+ D15=>mdout1_15_19, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(19));
mux_15: MUX161
- port map (D0=>mdout1_0_20, D1=>mdout1_1_20, D2=>mdout1_2_20,
- D3=>mdout1_3_20, D4=>mdout1_4_20, D5=>mdout1_5_20,
- D6=>mdout1_6_20, D7=>mdout1_7_20, D8=>mdout1_8_20,
- D9=>mdout1_9_20, D10=>mdout1_10_20, D11=>mdout1_11_20,
- D12=>mdout1_12_20, D13=>mdout1_13_20, D14=>mdout1_14_20,
- D15=>mdout1_15_20, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_20, D1=>mdout1_1_20, D2=>mdout1_2_20,
+ D3=>mdout1_3_20, D4=>mdout1_4_20, D5=>mdout1_5_20,
+ D6=>mdout1_6_20, D7=>mdout1_7_20, D8=>mdout1_8_20,
+ D9=>mdout1_9_20, D10=>mdout1_10_20, D11=>mdout1_11_20,
+ D12=>mdout1_12_20, D13=>mdout1_13_20, D14=>mdout1_14_20,
+ D15=>mdout1_15_20, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(20));
mux_14: MUX161
- port map (D0=>mdout1_0_21, D1=>mdout1_1_21, D2=>mdout1_2_21,
- D3=>mdout1_3_21, D4=>mdout1_4_21, D5=>mdout1_5_21,
- D6=>mdout1_6_21, D7=>mdout1_7_21, D8=>mdout1_8_21,
- D9=>mdout1_9_21, D10=>mdout1_10_21, D11=>mdout1_11_21,
- D12=>mdout1_12_21, D13=>mdout1_13_21, D14=>mdout1_14_21,
- D15=>mdout1_15_21, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_21, D1=>mdout1_1_21, D2=>mdout1_2_21,
+ D3=>mdout1_3_21, D4=>mdout1_4_21, D5=>mdout1_5_21,
+ D6=>mdout1_6_21, D7=>mdout1_7_21, D8=>mdout1_8_21,
+ D9=>mdout1_9_21, D10=>mdout1_10_21, D11=>mdout1_11_21,
+ D12=>mdout1_12_21, D13=>mdout1_13_21, D14=>mdout1_14_21,
+ D15=>mdout1_15_21, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(21));
mux_13: MUX161
- port map (D0=>mdout1_0_22, D1=>mdout1_1_22, D2=>mdout1_2_22,
- D3=>mdout1_3_22, D4=>mdout1_4_22, D5=>mdout1_5_22,
- D6=>mdout1_6_22, D7=>mdout1_7_22, D8=>mdout1_8_22,
- D9=>mdout1_9_22, D10=>mdout1_10_22, D11=>mdout1_11_22,
- D12=>mdout1_12_22, D13=>mdout1_13_22, D14=>mdout1_14_22,
- D15=>mdout1_15_22, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_22, D1=>mdout1_1_22, D2=>mdout1_2_22,
+ D3=>mdout1_3_22, D4=>mdout1_4_22, D5=>mdout1_5_22,
+ D6=>mdout1_6_22, D7=>mdout1_7_22, D8=>mdout1_8_22,
+ D9=>mdout1_9_22, D10=>mdout1_10_22, D11=>mdout1_11_22,
+ D12=>mdout1_12_22, D13=>mdout1_13_22, D14=>mdout1_14_22,
+ D15=>mdout1_15_22, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(22));
mux_12: MUX161
- port map (D0=>mdout1_0_23, D1=>mdout1_1_23, D2=>mdout1_2_23,
- D3=>mdout1_3_23, D4=>mdout1_4_23, D5=>mdout1_5_23,
- D6=>mdout1_6_23, D7=>mdout1_7_23, D8=>mdout1_8_23,
- D9=>mdout1_9_23, D10=>mdout1_10_23, D11=>mdout1_11_23,
- D12=>mdout1_12_23, D13=>mdout1_13_23, D14=>mdout1_14_23,
- D15=>mdout1_15_23, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_23, D1=>mdout1_1_23, D2=>mdout1_2_23,
+ D3=>mdout1_3_23, D4=>mdout1_4_23, D5=>mdout1_5_23,
+ D6=>mdout1_6_23, D7=>mdout1_7_23, D8=>mdout1_8_23,
+ D9=>mdout1_9_23, D10=>mdout1_10_23, D11=>mdout1_11_23,
+ D12=>mdout1_12_23, D13=>mdout1_13_23, D14=>mdout1_14_23,
+ D15=>mdout1_15_23, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(23));
mux_11: MUX161
- port map (D0=>mdout1_0_24, D1=>mdout1_1_24, D2=>mdout1_2_24,
- D3=>mdout1_3_24, D4=>mdout1_4_24, D5=>mdout1_5_24,
- D6=>mdout1_6_24, D7=>mdout1_7_24, D8=>mdout1_8_24,
- D9=>mdout1_9_24, D10=>mdout1_10_24, D11=>mdout1_11_24,
- D12=>mdout1_12_24, D13=>mdout1_13_24, D14=>mdout1_14_24,
- D15=>mdout1_15_24, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_24, D1=>mdout1_1_24, D2=>mdout1_2_24,
+ D3=>mdout1_3_24, D4=>mdout1_4_24, D5=>mdout1_5_24,
+ D6=>mdout1_6_24, D7=>mdout1_7_24, D8=>mdout1_8_24,
+ D9=>mdout1_9_24, D10=>mdout1_10_24, D11=>mdout1_11_24,
+ D12=>mdout1_12_24, D13=>mdout1_13_24, D14=>mdout1_14_24,
+ D15=>mdout1_15_24, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(24));
mux_10: MUX161
- port map (D0=>mdout1_0_25, D1=>mdout1_1_25, D2=>mdout1_2_25,
- D3=>mdout1_3_25, D4=>mdout1_4_25, D5=>mdout1_5_25,
- D6=>mdout1_6_25, D7=>mdout1_7_25, D8=>mdout1_8_25,
- D9=>mdout1_9_25, D10=>mdout1_10_25, D11=>mdout1_11_25,
- D12=>mdout1_12_25, D13=>mdout1_13_25, D14=>mdout1_14_25,
- D15=>mdout1_15_25, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_25, D1=>mdout1_1_25, D2=>mdout1_2_25,
+ D3=>mdout1_3_25, D4=>mdout1_4_25, D5=>mdout1_5_25,
+ D6=>mdout1_6_25, D7=>mdout1_7_25, D8=>mdout1_8_25,
+ D9=>mdout1_9_25, D10=>mdout1_10_25, D11=>mdout1_11_25,
+ D12=>mdout1_12_25, D13=>mdout1_13_25, D14=>mdout1_14_25,
+ D15=>mdout1_15_25, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(25));
mux_9: MUX161
- port map (D0=>mdout1_0_26, D1=>mdout1_1_26, D2=>mdout1_2_26,
- D3=>mdout1_3_26, D4=>mdout1_4_26, D5=>mdout1_5_26,
- D6=>mdout1_6_26, D7=>mdout1_7_26, D8=>mdout1_8_26,
- D9=>mdout1_9_26, D10=>mdout1_10_26, D11=>mdout1_11_26,
- D12=>mdout1_12_26, D13=>mdout1_13_26, D14=>mdout1_14_26,
- D15=>mdout1_15_26, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_26, D1=>mdout1_1_26, D2=>mdout1_2_26,
+ D3=>mdout1_3_26, D4=>mdout1_4_26, D5=>mdout1_5_26,
+ D6=>mdout1_6_26, D7=>mdout1_7_26, D8=>mdout1_8_26,
+ D9=>mdout1_9_26, D10=>mdout1_10_26, D11=>mdout1_11_26,
+ D12=>mdout1_12_26, D13=>mdout1_13_26, D14=>mdout1_14_26,
+ D15=>mdout1_15_26, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(26));
mux_8: MUX161
- port map (D0=>mdout1_0_27, D1=>mdout1_1_27, D2=>mdout1_2_27,
- D3=>mdout1_3_27, D4=>mdout1_4_27, D5=>mdout1_5_27,
- D6=>mdout1_6_27, D7=>mdout1_7_27, D8=>mdout1_8_27,
- D9=>mdout1_9_27, D10=>mdout1_10_27, D11=>mdout1_11_27,
- D12=>mdout1_12_27, D13=>mdout1_13_27, D14=>mdout1_14_27,
- D15=>mdout1_15_27, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_27, D1=>mdout1_1_27, D2=>mdout1_2_27,
+ D3=>mdout1_3_27, D4=>mdout1_4_27, D5=>mdout1_5_27,
+ D6=>mdout1_6_27, D7=>mdout1_7_27, D8=>mdout1_8_27,
+ D9=>mdout1_9_27, D10=>mdout1_10_27, D11=>mdout1_11_27,
+ D12=>mdout1_12_27, D13=>mdout1_13_27, D14=>mdout1_14_27,
+ D15=>mdout1_15_27, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(27));
mux_7: MUX161
- port map (D0=>mdout1_0_28, D1=>mdout1_1_28, D2=>mdout1_2_28,
- D3=>mdout1_3_28, D4=>mdout1_4_28, D5=>mdout1_5_28,
- D6=>mdout1_6_28, D7=>mdout1_7_28, D8=>mdout1_8_28,
- D9=>mdout1_9_28, D10=>mdout1_10_28, D11=>mdout1_11_28,
- D12=>mdout1_12_28, D13=>mdout1_13_28, D14=>mdout1_14_28,
- D15=>mdout1_15_28, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_28, D1=>mdout1_1_28, D2=>mdout1_2_28,
+ D3=>mdout1_3_28, D4=>mdout1_4_28, D5=>mdout1_5_28,
+ D6=>mdout1_6_28, D7=>mdout1_7_28, D8=>mdout1_8_28,
+ D9=>mdout1_9_28, D10=>mdout1_10_28, D11=>mdout1_11_28,
+ D12=>mdout1_12_28, D13=>mdout1_13_28, D14=>mdout1_14_28,
+ D15=>mdout1_15_28, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(28));
mux_6: MUX161
- port map (D0=>mdout1_0_29, D1=>mdout1_1_29, D2=>mdout1_2_29,
- D3=>mdout1_3_29, D4=>mdout1_4_29, D5=>mdout1_5_29,
- D6=>mdout1_6_29, D7=>mdout1_7_29, D8=>mdout1_8_29,
- D9=>mdout1_9_29, D10=>mdout1_10_29, D11=>mdout1_11_29,
- D12=>mdout1_12_29, D13=>mdout1_13_29, D14=>mdout1_14_29,
- D15=>mdout1_15_29, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_29, D1=>mdout1_1_29, D2=>mdout1_2_29,
+ D3=>mdout1_3_29, D4=>mdout1_4_29, D5=>mdout1_5_29,
+ D6=>mdout1_6_29, D7=>mdout1_7_29, D8=>mdout1_8_29,
+ D9=>mdout1_9_29, D10=>mdout1_10_29, D11=>mdout1_11_29,
+ D12=>mdout1_12_29, D13=>mdout1_13_29, D14=>mdout1_14_29,
+ D15=>mdout1_15_29, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(29));
mux_5: MUX161
- port map (D0=>mdout1_0_30, D1=>mdout1_1_30, D2=>mdout1_2_30,
- D3=>mdout1_3_30, D4=>mdout1_4_30, D5=>mdout1_5_30,
- D6=>mdout1_6_30, D7=>mdout1_7_30, D8=>mdout1_8_30,
- D9=>mdout1_9_30, D10=>mdout1_10_30, D11=>mdout1_11_30,
- D12=>mdout1_12_30, D13=>mdout1_13_30, D14=>mdout1_14_30,
- D15=>mdout1_15_30, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_30, D1=>mdout1_1_30, D2=>mdout1_2_30,
+ D3=>mdout1_3_30, D4=>mdout1_4_30, D5=>mdout1_5_30,
+ D6=>mdout1_6_30, D7=>mdout1_7_30, D8=>mdout1_8_30,
+ D9=>mdout1_9_30, D10=>mdout1_10_30, D11=>mdout1_11_30,
+ D12=>mdout1_12_30, D13=>mdout1_13_30, D14=>mdout1_14_30,
+ D15=>mdout1_15_30, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(30));
mux_4: MUX161
- port map (D0=>mdout1_0_31, D1=>mdout1_1_31, D2=>mdout1_2_31,
- D3=>mdout1_3_31, D4=>mdout1_4_31, D5=>mdout1_5_31,
- D6=>mdout1_6_31, D7=>mdout1_7_31, D8=>mdout1_8_31,
- D9=>mdout1_9_31, D10=>mdout1_10_31, D11=>mdout1_11_31,
- D12=>mdout1_12_31, D13=>mdout1_13_31, D14=>mdout1_14_31,
- D15=>mdout1_15_31, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_31, D1=>mdout1_1_31, D2=>mdout1_2_31,
+ D3=>mdout1_3_31, D4=>mdout1_4_31, D5=>mdout1_5_31,
+ D6=>mdout1_6_31, D7=>mdout1_7_31, D8=>mdout1_8_31,
+ D9=>mdout1_9_31, D10=>mdout1_10_31, D11=>mdout1_11_31,
+ D12=>mdout1_12_31, D13=>mdout1_13_31, D14=>mdout1_14_31,
+ D15=>mdout1_15_31, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(31));
mux_3: MUX161
- port map (D0=>mdout1_0_32, D1=>mdout1_1_32, D2=>mdout1_2_32,
- D3=>mdout1_3_32, D4=>mdout1_4_32, D5=>mdout1_5_32,
- D6=>mdout1_6_32, D7=>mdout1_7_32, D8=>mdout1_8_32,
- D9=>mdout1_9_32, D10=>mdout1_10_32, D11=>mdout1_11_32,
- D12=>mdout1_12_32, D13=>mdout1_13_32, D14=>mdout1_14_32,
- D15=>mdout1_15_32, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_32, D1=>mdout1_1_32, D2=>mdout1_2_32,
+ D3=>mdout1_3_32, D4=>mdout1_4_32, D5=>mdout1_5_32,
+ D6=>mdout1_6_32, D7=>mdout1_7_32, D8=>mdout1_8_32,
+ D9=>mdout1_9_32, D10=>mdout1_10_32, D11=>mdout1_11_32,
+ D12=>mdout1_12_32, D13=>mdout1_13_32, D14=>mdout1_14_32,
+ D15=>mdout1_15_32, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(32));
mux_2: MUX161
- port map (D0=>mdout1_0_33, D1=>mdout1_1_33, D2=>mdout1_2_33,
- D3=>mdout1_3_33, D4=>mdout1_4_33, D5=>mdout1_5_33,
- D6=>mdout1_6_33, D7=>mdout1_7_33, D8=>mdout1_8_33,
- D9=>mdout1_9_33, D10=>mdout1_10_33, D11=>mdout1_11_33,
- D12=>mdout1_12_33, D13=>mdout1_13_33, D14=>mdout1_14_33,
- D15=>mdout1_15_33, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_33, D1=>mdout1_1_33, D2=>mdout1_2_33,
+ D3=>mdout1_3_33, D4=>mdout1_4_33, D5=>mdout1_5_33,
+ D6=>mdout1_6_33, D7=>mdout1_7_33, D8=>mdout1_8_33,
+ D9=>mdout1_9_33, D10=>mdout1_10_33, D11=>mdout1_11_33,
+ D12=>mdout1_12_33, D13=>mdout1_13_33, D14=>mdout1_14_33,
+ D15=>mdout1_15_33, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(33));
mux_1: MUX161
- port map (D0=>mdout1_0_34, D1=>mdout1_1_34, D2=>mdout1_2_34,
- D3=>mdout1_3_34, D4=>mdout1_4_34, D5=>mdout1_5_34,
- D6=>mdout1_6_34, D7=>mdout1_7_34, D8=>mdout1_8_34,
- D9=>mdout1_9_34, D10=>mdout1_10_34, D11=>mdout1_11_34,
- D12=>mdout1_12_34, D13=>mdout1_13_34, D14=>mdout1_14_34,
- D15=>mdout1_15_34, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_34, D1=>mdout1_1_34, D2=>mdout1_2_34,
+ D3=>mdout1_3_34, D4=>mdout1_4_34, D5=>mdout1_5_34,
+ D6=>mdout1_6_34, D7=>mdout1_7_34, D8=>mdout1_8_34,
+ D9=>mdout1_9_34, D10=>mdout1_10_34, D11=>mdout1_11_34,
+ D12=>mdout1_12_34, D13=>mdout1_13_34, D14=>mdout1_14_34,
+ D15=>mdout1_15_34, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(34));
mux_0: MUX161
- port map (D0=>mdout1_0_35, D1=>mdout1_1_35, D2=>mdout1_2_35,
- D3=>mdout1_3_35, D4=>mdout1_4_35, D5=>mdout1_5_35,
- D6=>mdout1_6_35, D7=>mdout1_7_35, D8=>mdout1_8_35,
- D9=>mdout1_9_35, D10=>mdout1_10_35, D11=>mdout1_11_35,
- D12=>mdout1_12_35, D13=>mdout1_13_35, D14=>mdout1_14_35,
- D15=>mdout1_15_35, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_35, D1=>mdout1_1_35, D2=>mdout1_2_35,
+ D3=>mdout1_3_35, D4=>mdout1_4_35, D5=>mdout1_5_35,
+ D6=>mdout1_6_35, D7=>mdout1_7_35, D8=>mdout1_8_35,
+ D9=>mdout1_9_35, D10=>mdout1_10_35, D11=>mdout1_11_35,
+ D12=>mdout1_12_35, D13=>mdout1_13_35, D14=>mdout1_14_35,
+ D15=>mdout1_15_35, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(35));
wcnt_0: FSUB2B
- port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0,
+ port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0,
BI=>scuba_vlo, BOUT=>co0_5, S0=>open, S1=>wcnt_sub_0);
wcnt_1: FSUB2B
- port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2,
+ port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2,
BI=>co0_5, BOUT=>co1_5, S0=>wcnt_sub_1, S1=>wcnt_sub_2);
wcnt_2: FSUB2B
- port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4,
+ port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4,
BI=>co1_5, BOUT=>co2_5, S0=>wcnt_sub_3, S1=>wcnt_sub_4);
wcnt_3: FSUB2B
- port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6,
+ port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6,
BI=>co2_5, BOUT=>co3_5, S0=>wcnt_sub_5, S1=>wcnt_sub_6);
wcnt_4: FSUB2B
- port map (A0=>wcount_7, A1=>wcount_8, B0=>rptr_7, B1=>rptr_8,
+ port map (A0=>wcount_7, A1=>wcount_8, B0=>rptr_7, B1=>rptr_8,
BI=>co3_5, BOUT=>co4_5, S0=>wcnt_sub_7, S1=>wcnt_sub_8);
wcnt_5: FSUB2B
- port map (A0=>wcount_9, A1=>wcount_10, B0=>rptr_9, B1=>rptr_10,
+ port map (A0=>wcount_9, A1=>wcount_10, B0=>rptr_9, B1=>rptr_10,
BI=>co4_5, BOUT=>co5_5, S0=>wcnt_sub_9, S1=>wcnt_sub_10);
wcnt_6: FSUB2B
- port map (A0=>wcount_11, A1=>wcount_12, B0=>rptr_11, B1=>rptr_12,
+ port map (A0=>wcount_11, A1=>wcount_12, B0=>rptr_11, B1=>rptr_12,
BI=>co5_5, BOUT=>co6_5, S0=>wcnt_sub_11, S1=>wcnt_sub_12);
wcnt_7: FSUB2B
- port map (A0=>wcount_13, A1=>wcount_14, B0=>rptr_13, B1=>rptr_14,
+ port map (A0=>wcount_13, A1=>wcount_14, B0=>rptr_13, B1=>rptr_14,
BI=>co6_5, BOUT=>co7_3, S0=>wcnt_sub_13, S1=>wcnt_sub_14);
wcnt_8: FSUB2B
- port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, BI=>co7_3, BOUT=>open, S0=>wcnt_sub_15,
+ port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, BI=>co7_3, BOUT=>open, S0=>wcnt_sub_15,
S1=>open);
af_set_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
+ port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open);
af_set_cmp_0: AGEB2
- port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0),
+ port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0),
B1=>AmFullThresh(1), CI=>cmp_ci_2, GE=>co0_6);
af_set_cmp_1: AGEB2
- port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2),
+ port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2),
B1=>AmFullThresh(3), CI=>co0_6, GE=>co1_6);
af_set_cmp_2: AGEB2
- port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4),
+ port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4),
B1=>AmFullThresh(5), CI=>co1_6, GE=>co2_6);
af_set_cmp_3: AGEB2
- port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6),
+ port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6),
B1=>AmFullThresh(7), CI=>co2_6, GE=>co3_6);
af_set_cmp_4: AGEB2
- port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8),
+ port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8),
B1=>AmFullThresh(9), CI=>co3_6, GE=>co4_6);
af_set_cmp_5: AGEB2
- port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10),
+ port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10),
B1=>AmFullThresh(11), CI=>co4_6, GE=>co5_6);
af_set_cmp_6: AGEB2
- port map (A0=>wcnt_reg_12, A1=>wcnt_reg_13, B0=>AmFullThresh(12),
+ port map (A0=>wcnt_reg_12, A1=>wcnt_reg_13, B0=>AmFullThresh(12),
B1=>AmFullThresh(13), CI=>co5_6, GE=>co6_6);
af_set_cmp_7: AGEB2
- port map (A0=>wcnt_reg_14, A1=>wcnt_reg_15, B0=>AmFullThresh(14),
+ port map (A0=>wcnt_reg_14, A1=>wcnt_reg_15, B0=>AmFullThresh(14),
B1=>scuba_vlo, CI=>co6_6, GE=>af_set_c);
scuba_vlo_inst: VLO
port map (Z=>scuba_vlo);
a2: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set,
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set,
S1=>open);
WCNT(0) <= fcount_0;
--- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41)
--- Module Version: 4.7
---/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 8192 -width 36 -depth 8192 -regout -no_enable -pe -1 -pf 0 -fill -e
+-- VHDL netlist generated by SCUBA ispLever_v8.1_PROD_Build (20)
+-- Module Version: 4.8
+--/d/sugar/lattice/ispLEVER8.1/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 8192 -width 36 -depth 8192 -regout -no_enable -pe -1 -pf 0 -fill -e
--- Wed Mar 31 11:25:15 2010
+-- Fri Jul 30 15:11:59 2010
library IEEE;
use IEEE.std_logic_1164.all;
entity fifo_36x8k_oreg is
port (
- Data: in std_logic_vector(35 downto 0);
- Clock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- AmFullThresh: in std_logic_vector(12 downto 0);
- Q: out std_logic_vector(35 downto 0);
- WCNT: out std_logic_vector(13 downto 0);
- Empty: out std_logic;
- Full: out std_logic;
+ Data: in std_logic_vector(35 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ AmFullThresh: in std_logic_vector(12 downto 0);
+ Q: out std_logic_vector(35 downto 0);
+ WCNT: out std_logic_vector(13 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
AlmostFull: out std_logic);
end fifo_36x8k_oreg;
-- local component declarations
component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
B1: in std_logic; CI: in std_logic; GE: out std_logic);
end component;
component ALEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
B1: in std_logic; CI: in std_logic; LE: out std_logic);
end component;
component AND2
port (A: in std_logic; B: in std_logic; Z: out std_logic);
end component;
component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
end component;
component CB2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CON: in std_logic; CO: out std_logic; NC0: out std_logic;
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CON: in std_logic; CO: out std_logic; NC0: out std_logic;
NC1: out std_logic);
end component;
component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
S0: out std_logic; S1: out std_logic);
end component;
component FSUB2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; BI: in std_logic; BOUT: out std_logic;
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; BI: in std_logic; BOUT: out std_logic;
S0: out std_logic; S1: out std_logic);
end component;
component FD1P3BX
-- synopsys translate_off
generic (GSR : in String);
-- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
PD: in std_logic; Q: out std_logic);
end component;
component FD1P3DX
-- synopsys translate_off
generic (GSR : in String);
-- synopsys translate_on
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
CD: in std_logic; Q: out std_logic);
end component;
component FD1S3BX
-- synopsys translate_off
generic (GSR : in String);
-- synopsys translate_on
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
Q: out std_logic);
end component;
component FD1S3DX
-- synopsys translate_off
generic (GSR : in String);
-- synopsys translate_on
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
Q: out std_logic);
end component;
component INV
port (A: in std_logic; Z: out std_logic);
end component;
component MUX41
- port (D0: in std_logic; D1: in std_logic; D2: in std_logic;
- D3: in std_logic; SD1: in std_logic; SD2: in std_logic;
+ port (D0: in std_logic; D1: in std_logic; D2: in std_logic;
+ D3: in std_logic; SD1: in std_logic; SD2: in std_logic;
Z: out std_logic);
end component;
component ROM16X1
-- synopsys translate_off
generic (initval : in String);
-- synopsys translate_on
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
AD0: in std_logic; DO0: out std_logic);
end component;
component VHI
end component;
component DP16KB
-- synopsys translate_off
- generic (GSR : in String; WRITEMODE_B : in String;
- CSDECODE_B : in std_logic_vector(2 downto 0);
- CSDECODE_A : in std_logic_vector(2 downto 0);
- WRITEMODE_A : in String; RESETMODE : in String;
- REGMODE_B : in String; REGMODE_A : in String;
+ generic (GSR : in String; WRITEMODE_B : in String;
+ CSDECODE_B : in std_logic_vector(2 downto 0);
+ CSDECODE_A : in std_logic_vector(2 downto 0);
+ WRITEMODE_A : in String; RESETMODE : in String;
+ REGMODE_B : in String; REGMODE_A : in String;
DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
-- synopsys translate_on
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
- CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
- CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
+ port (DIA0: in std_logic; DIA1: in std_logic;
+ DIA2: in std_logic; DIA3: in std_logic;
+ DIA4: in std_logic; DIA5: in std_logic;
+ DIA6: in std_logic; DIA7: in std_logic;
+ DIA8: in std_logic; DIA9: in std_logic;
+ DIA10: in std_logic; DIA11: in std_logic;
+ DIA12: in std_logic; DIA13: in std_logic;
+ DIA14: in std_logic; DIA15: in std_logic;
+ DIA16: in std_logic; DIA17: in std_logic;
+ ADA0: in std_logic; ADA1: in std_logic;
+ ADA2: in std_logic; ADA3: in std_logic;
+ ADA4: in std_logic; ADA5: in std_logic;
+ ADA6: in std_logic; ADA7: in std_logic;
+ ADA8: in std_logic; ADA9: in std_logic;
+ ADA10: in std_logic; ADA11: in std_logic;
+ ADA12: in std_logic; ADA13: in std_logic;
+ CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
+ CSA0: in std_logic; CSA1: in std_logic;
+ CSA2: in std_logic; RSTA: in std_logic;
+ DIB0: in std_logic; DIB1: in std_logic;
+ DIB2: in std_logic; DIB3: in std_logic;
+ DIB4: in std_logic; DIB5: in std_logic;
+ DIB6: in std_logic; DIB7: in std_logic;
+ DIB8: in std_logic; DIB9: in std_logic;
+ DIB10: in std_logic; DIB11: in std_logic;
+ DIB12: in std_logic; DIB13: in std_logic;
+ DIB14: in std_logic; DIB15: in std_logic;
+ DIB16: in std_logic; DIB17: in std_logic;
+ ADB0: in std_logic; ADB1: in std_logic;
+ ADB2: in std_logic; ADB3: in std_logic;
+ ADB4: in std_logic; ADB5: in std_logic;
+ ADB6: in std_logic; ADB7: in std_logic;
+ ADB8: in std_logic; ADB9: in std_logic;
+ ADB10: in std_logic; ADB11: in std_logic;
+ ADB12: in std_logic; ADB13: in std_logic;
+ CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
+ CSB0: in std_logic; CSB1: in std_logic;
+ CSB2: in std_logic; RSTB: in std_logic;
+ DOA0: out std_logic; DOA1: out std_logic;
+ DOA2: out std_logic; DOA3: out std_logic;
+ DOA4: out std_logic; DOA5: out std_logic;
+ DOA6: out std_logic; DOA7: out std_logic;
+ DOA8: out std_logic; DOA9: out std_logic;
+ DOA10: out std_logic; DOA11: out std_logic;
+ DOA12: out std_logic; DOA13: out std_logic;
+ DOA14: out std_logic; DOA15: out std_logic;
+ DOA16: out std_logic; DOA17: out std_logic;
+ DOB0: out std_logic; DOB1: out std_logic;
+ DOB2: out std_logic; DOB3: out std_logic;
+ DOB4: out std_logic; DOB5: out std_logic;
+ DOB6: out std_logic; DOB7: out std_logic;
+ DOB8: out std_logic; DOB9: out std_logic;
+ DOB10: out std_logic; DOB11: out std_logic;
+ DOB12: out std_logic; DOB13: out std_logic;
+ DOB14: out std_logic; DOB15: out std_logic;
DOB16: out std_logic; DOB17: out std_logic);
end component;
- attribute initval : string;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute CSDECODE_B : string;
- attribute CSDECODE_A : string;
- attribute WRITEMODE_B : string;
- attribute WRITEMODE_A : string;
- attribute RESETMODE : string;
- attribute REGMODE_B : string;
- attribute REGMODE_A : string;
- attribute DATA_WIDTH_B : string;
- attribute DATA_WIDTH_A : string;
- attribute GSR : string;
+ attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_B : string;
+ attribute CSDECODE_A : string;
+ attribute WRITEMODE_B : string;
+ attribute WRITEMODE_A : string;
+ attribute RESETMODE : string;
+ attribute REGMODE_B : string;
+ attribute REGMODE_A : string;
+ attribute DATA_WIDTH_B : string;
+ attribute DATA_WIDTH_A : string;
+ attribute GSR : string;
attribute initval of LUT4_1 : label is "0x3232";
attribute initval of LUT4_0 : label is "0x3232";
attribute MEM_LPC_FILE of pdp_ram_0_0_15 : label is "fifo_36x8k_oreg.lpc";
-- synopsys translate_off
generic map (initval=> "0x3232")
-- synopsys translate_on
- port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
+ port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
AD0=>empty_i, DO0=>empty_d);
LUT4_0: ROM16X1
-- synopsys translate_off
generic map (initval=> "0x3232")
-- synopsys translate_on
- port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
+ port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
AD0=>full_i, DO0=>full_d);
AND2_t1: AND2
pdp_ram_0_0_15: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "100", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "100", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
- CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12,
- CSB2=>rden_i, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1,
- DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4,
- DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7,
- DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12,
+ CSB2=>rden_i, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1,
+ DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4,
+ DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7,
+ DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
DOB16=>open, DOB17=>open);
pdp_ram_0_1_14: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "100", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "100", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
- DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
- DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rden_i, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_0_9, DOB1=>mdout1_0_10, DOB2=>mdout1_0_11,
- DOB3=>mdout1_0_12, DOB4=>mdout1_0_13, DOB5=>mdout1_0_14,
- DOB6=>mdout1_0_15, DOB7=>mdout1_0_16, DOB8=>mdout1_0_17,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
+ DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
+ DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
+ ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
+ ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
+ ADB13=>rptr_10, CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rden_i, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_0_9, DOB1=>mdout1_0_10, DOB2=>mdout1_0_11,
+ DOB3=>mdout1_0_12, DOB4=>mdout1_0_13, DOB5=>mdout1_0_14,
+ DOB6=>mdout1_0_15, DOB7=>mdout1_0_16, DOB8=>mdout1_0_17,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_0_2_13: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "100", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "100", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
- DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
- DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rden_i, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_0_18, DOB1=>mdout1_0_19, DOB2=>mdout1_0_20,
- DOB3=>mdout1_0_21, DOB4=>mdout1_0_22, DOB5=>mdout1_0_23,
- DOB6=>mdout1_0_24, DOB7=>mdout1_0_25, DOB8=>mdout1_0_26,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
+ DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
+ DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
+ ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
+ ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
+ ADB13=>rptr_10, CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rden_i, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_0_18, DOB1=>mdout1_0_19, DOB2=>mdout1_0_20,
+ DOB3=>mdout1_0_21, DOB4=>mdout1_0_22, DOB5=>mdout1_0_23,
+ DOB6=>mdout1_0_24, DOB7=>mdout1_0_25, DOB8=>mdout1_0_26,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_0_3_12: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "100", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "100", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
- DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
- DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rden_i, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_0_27, DOB1=>mdout1_0_28, DOB2=>mdout1_0_29,
- DOB3=>mdout1_0_30, DOB4=>mdout1_0_31, DOB5=>mdout1_0_32,
- DOB6=>mdout1_0_33, DOB7=>mdout1_0_34, DOB8=>mdout1_0_35,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
+ DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
+ DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
+ ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
+ ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
+ ADB13=>rptr_10, CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rden_i, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_0_27, DOB1=>mdout1_0_28, DOB2=>mdout1_0_29,
+ DOB3=>mdout1_0_30, DOB4=>mdout1_0_31, DOB5=>mdout1_0_32,
+ DOB6=>mdout1_0_33, DOB7=>mdout1_0_34, DOB8=>mdout1_0_35,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_1_0_11: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "101", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "101", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
- CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12,
- CSB2=>rden_i, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1,
- DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4,
- DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7,
- DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12,
+ CSB2=>rden_i, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1,
+ DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4,
+ DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7,
+ DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
DOB16=>open, DOB17=>open);
pdp_ram_1_1_10: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "101", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "101", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
- DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
- DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rden_i, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_1_9, DOB1=>mdout1_1_10, DOB2=>mdout1_1_11,
- DOB3=>mdout1_1_12, DOB4=>mdout1_1_13, DOB5=>mdout1_1_14,
- DOB6=>mdout1_1_15, DOB7=>mdout1_1_16, DOB8=>mdout1_1_17,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
+ DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
+ DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
+ ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
+ ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
+ ADB13=>rptr_10, CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rden_i, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_1_9, DOB1=>mdout1_1_10, DOB2=>mdout1_1_11,
+ DOB3=>mdout1_1_12, DOB4=>mdout1_1_13, DOB5=>mdout1_1_14,
+ DOB6=>mdout1_1_15, DOB7=>mdout1_1_16, DOB8=>mdout1_1_17,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_1_2_9: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "101", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "101", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
- DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
- DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rden_i, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_1_18, DOB1=>mdout1_1_19, DOB2=>mdout1_1_20,
- DOB3=>mdout1_1_21, DOB4=>mdout1_1_22, DOB5=>mdout1_1_23,
- DOB6=>mdout1_1_24, DOB7=>mdout1_1_25, DOB8=>mdout1_1_26,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
+ DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
+ DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
+ ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
+ ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
+ ADB13=>rptr_10, CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rden_i, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_1_18, DOB1=>mdout1_1_19, DOB2=>mdout1_1_20,
+ DOB3=>mdout1_1_21, DOB4=>mdout1_1_22, DOB5=>mdout1_1_23,
+ DOB6=>mdout1_1_24, DOB7=>mdout1_1_25, DOB8=>mdout1_1_26,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_1_3_8: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "101", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "101", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
- DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
- DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rden_i, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_1_27, DOB1=>mdout1_1_28, DOB2=>mdout1_1_29,
- DOB3=>mdout1_1_30, DOB4=>mdout1_1_31, DOB5=>mdout1_1_32,
- DOB6=>mdout1_1_33, DOB7=>mdout1_1_34, DOB8=>mdout1_1_35,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
+ DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
+ DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
+ ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
+ ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
+ ADB13=>rptr_10, CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rden_i, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_1_27, DOB1=>mdout1_1_28, DOB2=>mdout1_1_29,
+ DOB3=>mdout1_1_30, DOB4=>mdout1_1_31, DOB5=>mdout1_1_32,
+ DOB6=>mdout1_1_33, DOB7=>mdout1_1_34, DOB8=>mdout1_1_35,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_2_0_7: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "110", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "110", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
- CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12,
- CSB2=>rden_i, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0, DOB1=>mdout1_2_1,
- DOB2=>mdout1_2_2, DOB3=>mdout1_2_3, DOB4=>mdout1_2_4,
- DOB5=>mdout1_2_5, DOB6=>mdout1_2_6, DOB7=>mdout1_2_7,
- DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12,
+ CSB2=>rden_i, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0, DOB1=>mdout1_2_1,
+ DOB2=>mdout1_2_2, DOB3=>mdout1_2_3, DOB4=>mdout1_2_4,
+ DOB5=>mdout1_2_5, DOB6=>mdout1_2_6, DOB7=>mdout1_2_7,
+ DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
DOB16=>open, DOB17=>open);
pdp_ram_2_1_6: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "110", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "110", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
- DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
- DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rden_i, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_2_9, DOB1=>mdout1_2_10, DOB2=>mdout1_2_11,
- DOB3=>mdout1_2_12, DOB4=>mdout1_2_13, DOB5=>mdout1_2_14,
- DOB6=>mdout1_2_15, DOB7=>mdout1_2_16, DOB8=>mdout1_2_17,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
+ DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
+ DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
+ ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
+ ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
+ ADB13=>rptr_10, CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rden_i, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_2_9, DOB1=>mdout1_2_10, DOB2=>mdout1_2_11,
+ DOB3=>mdout1_2_12, DOB4=>mdout1_2_13, DOB5=>mdout1_2_14,
+ DOB6=>mdout1_2_15, DOB7=>mdout1_2_16, DOB8=>mdout1_2_17,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_2_2_5: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "110", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "110", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
- DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
- DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rden_i, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_2_18, DOB1=>mdout1_2_19, DOB2=>mdout1_2_20,
- DOB3=>mdout1_2_21, DOB4=>mdout1_2_22, DOB5=>mdout1_2_23,
- DOB6=>mdout1_2_24, DOB7=>mdout1_2_25, DOB8=>mdout1_2_26,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
+ DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
+ DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
+ ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
+ ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
+ ADB13=>rptr_10, CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rden_i, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_2_18, DOB1=>mdout1_2_19, DOB2=>mdout1_2_20,
+ DOB3=>mdout1_2_21, DOB4=>mdout1_2_22, DOB5=>mdout1_2_23,
+ DOB6=>mdout1_2_24, DOB7=>mdout1_2_25, DOB8=>mdout1_2_26,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_2_3_4: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "110", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "110", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
- DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
- DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rden_i, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_2_27, DOB1=>mdout1_2_28, DOB2=>mdout1_2_29,
- DOB3=>mdout1_2_30, DOB4=>mdout1_2_31, DOB5=>mdout1_2_32,
- DOB6=>mdout1_2_33, DOB7=>mdout1_2_34, DOB8=>mdout1_2_35,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
+ DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
+ DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
+ ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
+ ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
+ ADB13=>rptr_10, CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rden_i, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_2_27, DOB1=>mdout1_2_28, DOB2=>mdout1_2_29,
+ DOB3=>mdout1_2_30, DOB4=>mdout1_2_31, DOB5=>mdout1_2_32,
+ DOB6=>mdout1_2_33, DOB7=>mdout1_2_34, DOB8=>mdout1_2_35,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_3_0_3: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "111", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "111", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
- DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
- DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
- DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
- DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
- DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
- ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
- ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
- ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
- ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
- CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>scuba_vlo, RSTA=>Reset,
- DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
- DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
- DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
- DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
- DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
- DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
- ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
- ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
- ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
- ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
- CLKB=>Clock, WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12,
- CSB2=>rden_i, RSTB=>Reset, DOA0=>open, DOA1=>open,
- DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0, DOB1=>mdout1_3_1,
- DOB2=>mdout1_3_2, DOB3=>mdout1_3_3, DOB4=>mdout1_3_4,
- DOB5=>mdout1_3_5, DOB6=>mdout1_3_6, DOB7=>mdout1_3_7,
- DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>scuba_vhi,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12,
+ CSB2=>rden_i, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0, DOB1=>mdout1_3_1,
+ DOB2=>mdout1_3_2, DOB3=>mdout1_3_3, DOB4=>mdout1_3_4,
+ DOB5=>mdout1_3_5, DOB6=>mdout1_3_6, DOB7=>mdout1_3_7,
+ DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
DOB16=>open, DOB17=>open);
pdp_ram_3_1_2: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "111", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "111", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
- DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
- DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rden_i, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_3_9, DOB1=>mdout1_3_10, DOB2=>mdout1_3_11,
- DOB3=>mdout1_3_12, DOB4=>mdout1_3_13, DOB5=>mdout1_3_14,
- DOB6=>mdout1_3_15, DOB7=>mdout1_3_16, DOB8=>mdout1_3_17,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
+ DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
+ DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
+ ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
+ ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
+ ADB13=>rptr_10, CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rden_i, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_3_9, DOB1=>mdout1_3_10, DOB2=>mdout1_3_11,
+ DOB3=>mdout1_3_12, DOB4=>mdout1_3_13, DOB5=>mdout1_3_14,
+ DOB6=>mdout1_3_15, DOB7=>mdout1_3_16, DOB8=>mdout1_3_17,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_3_2_1: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "111", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "111", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
- DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
- DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rden_i, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_3_18, DOB1=>mdout1_3_19, DOB2=>mdout1_3_20,
- DOB3=>mdout1_3_21, DOB4=>mdout1_3_22, DOB5=>mdout1_3_23,
- DOB6=>mdout1_3_24, DOB7=>mdout1_3_25, DOB8=>mdout1_3_26,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
+ DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
+ DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
+ ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
+ ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
+ ADB13=>rptr_10, CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rden_i, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_3_18, DOB1=>mdout1_3_19, DOB2=>mdout1_3_20,
+ DOB3=>mdout1_3_21, DOB4=>mdout1_3_22, DOB5=>mdout1_3_23,
+ DOB6=>mdout1_3_24, DOB7=>mdout1_3_25, DOB8=>mdout1_3_26,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
pdp_ram_3_3_0: DP16KB
-- synopsys translate_off
- generic map (CSDECODE_B=> "111", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
- REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
+ generic map (CSDECODE_B=> "111", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9,
DATA_WIDTH_A=> 9)
-- synopsys translate_on
- port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
- DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
- DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
- ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
- ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
- CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
- CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
- DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
- DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
- DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
- DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
- DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
- DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
- ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
- ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
- ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
- ADB13=>rptr_10, CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
- CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rden_i, RSTB=>Reset,
- DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
- DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
- DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
- DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
- DOB0=>mdout1_3_27, DOB1=>mdout1_3_28, DOB2=>mdout1_3_29,
- DOB3=>mdout1_3_30, DOB4=>mdout1_3_31, DOB5=>mdout1_3_32,
- DOB6=>mdout1_3_33, DOB7=>mdout1_3_34, DOB8=>mdout1_3_35,
- DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
- DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
+ DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
+ DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
+ ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
+ ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
+ ADB13=>rptr_10, CEB=>scuba_vhi, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>rden_i, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_3_27, DOB1=>mdout1_3_28, DOB2=>mdout1_3_29,
+ DOB3=>mdout1_3_30, DOB4=>mdout1_3_31, DOB5=>mdout1_3_32,
+ DOB6=>mdout1_3_33, DOB7=>mdout1_3_34, DOB8=>mdout1_3_35,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
FF_90: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_0);
FF_89: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_1);
FF_88: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_2);
FF_87: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_3);
FF_86: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_4);
FF_85: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_5);
FF_84: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_6);
FF_83: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_7);
FF_82: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_8);
FF_81: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_9);
FF_80: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_10);
FF_79: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_11);
FF_78: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_12, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_12, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_12);
FF_77: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ifcount_13, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ port map (D=>ifcount_13, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_13);
FF_76: FD1S3BX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset,
+ port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset,
Q=>wcount_0);
FF_73: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_1);
FF_72: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_2);
FF_71: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_3);
FF_70: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_4);
FF_69: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_5);
FF_68: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_6);
FF_67: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_7);
FF_66: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_8);
FF_65: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_9);
FF_64: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_10);
FF_63: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_11);
FF_62: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_12, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_12, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_12);
FF_61: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>iwcount_13, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>iwcount_13, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_13);
FF_60: FD1P3BX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset,
+ port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset,
Q=>rcount_0);
FF_59: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_1);
FF_58: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_2);
FF_57: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_3);
FF_56: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_4);
FF_55: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_5);
FF_54: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_6);
FF_53: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_7);
FF_52: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_8);
FF_51: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_9);
FF_50: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_10);
FF_49: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_11);
FF_48: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_12, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_12, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_12);
FF_47: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>ircount_13, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>ircount_13, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_13);
FF_46: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_0);
FF_45: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_1);
FF_44: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_2);
FF_43: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_3);
FF_42: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_4);
FF_41: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_5);
FF_40: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_6);
FF_39: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_7);
FF_38: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_8);
FF_37: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_9);
FF_36: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_10);
FF_35: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_11, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_11, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_11);
FF_34: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_12, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_12, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_12);
FF_33: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>wcount_13, SP=>wren_i, CK=>Clock, CD=>Reset,
+ port map (D=>wcount_13, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wptr_13);
FF_32: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_0);
FF_31: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_1);
FF_30: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_2);
FF_29: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_3);
FF_28: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_4);
FF_27: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_5);
FF_26: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_6);
FF_25: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_7);
FF_24: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_8);
FF_23: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_9);
FF_22: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_10);
FF_21: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_11, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_11, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_11);
FF_20: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_12, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_12, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_12);
FF_19: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rcount_13, SP=>rden_i, CK=>Clock, CD=>Reset,
+ port map (D=>rcount_13, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rptr_13);
FF_18: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rptr_11, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ port map (D=>rptr_11, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
Q=>rptr_11_ff);
FF_17: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rptr_12, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ port map (D=>rptr_12, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
Q=>rptr_12_ff);
+-- FF_16: FD1P3DX
+-- -- synopsys translate_off
+-- generic map (GSR=> "ENABLED")
+-- -- synopsys translate_on
+-- port map (D=>rptr_11_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+-- Q=>rptr_11_ff2);
+--
+-- FF_15: FD1P3DX
+-- -- synopsys translate_off
+-- generic map (GSR=> "ENABLED")
+-- -- synopsys translate_on
+-- port map (D=>rptr_12_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+-- Q=>rptr_12_ff2);
FF_16: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rptr_11_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ port map (D=>rptr_11_ff, SP=>'1', CK=>Clock, CD=>scuba_vlo,
Q=>rptr_11_ff2);
FF_15: FD1P3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
-- synopsys translate_on
- port map (D=>rptr_12_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ port map (D=>rptr_12_ff, SP=>'1', CK=>Clock, CD=>scuba_vlo,
Q=>rptr_12_ff2);
+
FF_14: FD1S3DX
-- synopsys translate_off
generic map (GSR=> "ENABLED")
port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull);
bdcnt_bctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con,
+ port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con,
CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open);
bdcnt_bctr_0: CB2
- port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1,
+ port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1,
CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1);
bdcnt_bctr_1: CB2
- port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con,
+ port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con,
CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3);
bdcnt_bctr_2: CB2
- port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con,
+ port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con,
CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5);
bdcnt_bctr_3: CB2
- port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con,
+ port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con,
CO=>co3, NC0=>ifcount_6, NC1=>ifcount_7);
bdcnt_bctr_4: CB2
- port map (CI=>co3, PC0=>fcount_8, PC1=>fcount_9, CON=>cnt_con,
+ port map (CI=>co3, PC0=>fcount_8, PC1=>fcount_9, CON=>cnt_con,
CO=>co4, NC0=>ifcount_8, NC1=>ifcount_9);
bdcnt_bctr_5: CB2
- port map (CI=>co4, PC0=>fcount_10, PC1=>fcount_11, CON=>cnt_con,
+ port map (CI=>co4, PC0=>fcount_10, PC1=>fcount_11, CON=>cnt_con,
CO=>co5, NC0=>ifcount_10, NC1=>ifcount_11);
bdcnt_bctr_6: CB2
- port map (CI=>co5, PC0=>fcount_12, PC1=>fcount_13, CON=>cnt_con,
+ port map (CI=>co5, PC0=>fcount_12, PC1=>fcount_13, CON=>cnt_con,
CO=>co6, NC0=>ifcount_12, NC1=>ifcount_13);
e_cmp_ci_a: FADD2B
- port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open,
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open,
S1=>open);
e_cmp_0: ALEB2
- port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo,
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo,
CI=>cmp_ci, LE=>co0_1);
e_cmp_1: ALEB2
- port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo,
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo,
B1=>scuba_vlo, CI=>co0_1, LE=>co1_1);
e_cmp_2: ALEB2
- port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo,
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo,
B1=>scuba_vlo, CI=>co1_1, LE=>co2_1);
e_cmp_3: ALEB2
- port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo,
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo,
B1=>scuba_vlo, CI=>co2_1, LE=>co3_1);
e_cmp_4: ALEB2
- port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo,
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo,
B1=>scuba_vlo, CI=>co3_1, LE=>co4_1);
e_cmp_5: ALEB2
- port map (A0=>fcount_10, A1=>fcount_11, B0=>scuba_vlo,
+ port map (A0=>fcount_10, A1=>fcount_11, B0=>scuba_vlo,
B1=>scuba_vlo, CI=>co4_1, LE=>co5_1);
e_cmp_6: ALEB2
- port map (A0=>fcount_12, A1=>fcount_13, B0=>scuba_vlo,
+ port map (A0=>fcount_12, A1=>fcount_13, B0=>scuba_vlo,
B1=>scuba_vlo, CI=>co5_1, LE=>cmp_le_1_c);
a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1,
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1,
S1=>open);
g_cmp_ci_a: FADD2B
- port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open,
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open,
S1=>open);
g_cmp_0: AGEB2
- port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i,
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i,
CI=>cmp_ci_1, GE=>co0_2);
g_cmp_1: AGEB2
- port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i,
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i,
CI=>co0_2, GE=>co1_2);
g_cmp_2: AGEB2
- port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i,
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i,
CI=>co1_2, GE=>co2_2);
g_cmp_3: AGEB2
- port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i,
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i,
CI=>co2_2, GE=>co3_2);
g_cmp_4: AGEB2
- port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i,
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i,
CI=>co3_2, GE=>co4_2);
g_cmp_5: AGEB2
- port map (A0=>fcount_10, A1=>fcount_11, B0=>wren_i, B1=>wren_i,
+ port map (A0=>fcount_10, A1=>fcount_11, B0=>wren_i, B1=>wren_i,
CI=>co4_2, GE=>co5_2);
g_cmp_6: AGEB2
- port map (A0=>fcount_12, A1=>fcount_13, B0=>wren_i,
+ port map (A0=>fcount_12, A1=>fcount_13, B0=>wren_i,
B1=>wren_i_inv, CI=>co5_2, GE=>cmp_ge_d1_c);
a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1,
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1,
S1=>open);
w_ctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open,
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open,
S1=>open);
w_ctr_0: CU2
- port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3,
+ port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3,
NC0=>iwcount_0, NC1=>iwcount_1);
w_ctr_1: CU2
- port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3,
+ port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3,
NC0=>iwcount_2, NC1=>iwcount_3);
w_ctr_2: CU2
- port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3,
+ port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3,
NC0=>iwcount_4, NC1=>iwcount_5);
w_ctr_3: CU2
- port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3,
+ port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3,
NC0=>iwcount_6, NC1=>iwcount_7);
w_ctr_4: CU2
- port map (CI=>co3_3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4_3,
+ port map (CI=>co3_3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4_3,
NC0=>iwcount_8, NC1=>iwcount_9);
w_ctr_5: CU2
- port map (CI=>co4_3, PC0=>wcount_10, PC1=>wcount_11, CO=>co5_3,
+ port map (CI=>co4_3, PC0=>wcount_10, PC1=>wcount_11, CO=>co5_3,
NC0=>iwcount_10, NC1=>iwcount_11);
w_ctr_6: CU2
- port map (CI=>co5_3, PC0=>wcount_12, PC1=>wcount_13, CO=>co6_1,
+ port map (CI=>co5_3, PC0=>wcount_12, PC1=>wcount_13, CO=>co6_1,
NC0=>iwcount_12, NC1=>iwcount_13);
scuba_vhi_inst: VHI
port map (Z=>scuba_vhi);
r_ctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open,
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open,
S1=>open);
r_ctr_0: CU2
- port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4,
+ port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4,
NC0=>ircount_0, NC1=>ircount_1);
r_ctr_1: CU2
- port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4,
+ port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4,
NC0=>ircount_2, NC1=>ircount_3);
r_ctr_2: CU2
- port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4,
+ port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4,
NC0=>ircount_4, NC1=>ircount_5);
r_ctr_3: CU2
- port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4,
+ port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4,
NC0=>ircount_6, NC1=>ircount_7);
r_ctr_4: CU2
- port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_4,
+ port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_4,
NC0=>ircount_8, NC1=>ircount_9);
r_ctr_5: CU2
- port map (CI=>co4_4, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_4,
+ port map (CI=>co4_4, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_4,
NC0=>ircount_10, NC1=>ircount_11);
r_ctr_6: CU2
- port map (CI=>co5_4, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_2,
+ port map (CI=>co5_4, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_2,
NC0=>ircount_12, NC1=>ircount_13);
mux_35: MUX41
- port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0,
+ port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0,
D3=>mdout1_3_0, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(0));
mux_34: MUX41
- port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1,
+ port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1,
D3=>mdout1_3_1, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(1));
mux_33: MUX41
- port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2,
+ port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2,
D3=>mdout1_3_2, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(2));
mux_32: MUX41
- port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3,
+ port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3,
D3=>mdout1_3_3, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(3));
mux_31: MUX41
- port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4,
+ port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4,
D3=>mdout1_3_4, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(4));
mux_30: MUX41
- port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5,
+ port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5,
D3=>mdout1_3_5, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(5));
mux_29: MUX41
- port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6,
+ port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6,
D3=>mdout1_3_6, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(6));
mux_28: MUX41
- port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7,
+ port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7,
D3=>mdout1_3_7, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(7));
mux_27: MUX41
- port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8,
+ port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8,
D3=>mdout1_3_8, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(8));
mux_26: MUX41
- port map (D0=>mdout1_0_9, D1=>mdout1_1_9, D2=>mdout1_2_9,
+ port map (D0=>mdout1_0_9, D1=>mdout1_1_9, D2=>mdout1_2_9,
D3=>mdout1_3_9, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(9));
mux_25: MUX41
- port map (D0=>mdout1_0_10, D1=>mdout1_1_10, D2=>mdout1_2_10,
- D3=>mdout1_3_10, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_10, D1=>mdout1_1_10, D2=>mdout1_2_10,
+ D3=>mdout1_3_10, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
Z=>Q(10));
mux_24: MUX41
- port map (D0=>mdout1_0_11, D1=>mdout1_1_11, D2=>mdout1_2_11,
- D3=>mdout1_3_11, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_11, D1=>mdout1_1_11, D2=>mdout1_2_11,
+ D3=>mdout1_3_11, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
Z=>Q(11));
mux_23: MUX41
- port map (D0=>mdout1_0_12, D1=>mdout1_1_12, D2=>mdout1_2_12,
- D3=>mdout1_3_12, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_12, D1=>mdout1_1_12, D2=>mdout1_2_12,
+ D3=>mdout1_3_12, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
Z=>Q(12));
mux_22: MUX41
- port map (D0=>mdout1_0_13, D1=>mdout1_1_13, D2=>mdout1_2_13,
- D3=>mdout1_3_13, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_13, D1=>mdout1_1_13, D2=>mdout1_2_13,
+ D3=>mdout1_3_13, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
Z=>Q(13));
mux_21: MUX41
- port map (D0=>mdout1_0_14, D1=>mdout1_1_14, D2=>mdout1_2_14,
- D3=>mdout1_3_14, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_14, D1=>mdout1_1_14, D2=>mdout1_2_14,
+ D3=>mdout1_3_14, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
Z=>Q(14));
mux_20: MUX41
- port map (D0=>mdout1_0_15, D1=>mdout1_1_15, D2=>mdout1_2_15,
- D3=>mdout1_3_15, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_15, D1=>mdout1_1_15, D2=>mdout1_2_15,
+ D3=>mdout1_3_15, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
Z=>Q(15));
mux_19: MUX41
- port map (D0=>mdout1_0_16, D1=>mdout1_1_16, D2=>mdout1_2_16,
- D3=>mdout1_3_16, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_16, D1=>mdout1_1_16, D2=>mdout1_2_16,
+ D3=>mdout1_3_16, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
Z=>Q(16));
mux_18: MUX41
- port map (D0=>mdout1_0_17, D1=>mdout1_1_17, D2=>mdout1_2_17,
- D3=>mdout1_3_17, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_17, D1=>mdout1_1_17, D2=>mdout1_2_17,
+ D3=>mdout1_3_17, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
Z=>Q(17));
mux_17: MUX41
- port map (D0=>mdout1_0_18, D1=>mdout1_1_18, D2=>mdout1_2_18,
- D3=>mdout1_3_18, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_18, D1=>mdout1_1_18, D2=>mdout1_2_18,
+ D3=>mdout1_3_18, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
Z=>Q(18));
mux_16: MUX41
- port map (D0=>mdout1_0_19, D1=>mdout1_1_19, D2=>mdout1_2_19,
- D3=>mdout1_3_19, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_19, D1=>mdout1_1_19, D2=>mdout1_2_19,
+ D3=>mdout1_3_19, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
Z=>Q(19));
mux_15: MUX41
- port map (D0=>mdout1_0_20, D1=>mdout1_1_20, D2=>mdout1_2_20,
- D3=>mdout1_3_20, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_20, D1=>mdout1_1_20, D2=>mdout1_2_20,
+ D3=>mdout1_3_20, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
Z=>Q(20));
mux_14: MUX41
- port map (D0=>mdout1_0_21, D1=>mdout1_1_21, D2=>mdout1_2_21,
- D3=>mdout1_3_21, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_21, D1=>mdout1_1_21, D2=>mdout1_2_21,
+ D3=>mdout1_3_21, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
Z=>Q(21));
mux_13: MUX41
- port map (D0=>mdout1_0_22, D1=>mdout1_1_22, D2=>mdout1_2_22,
- D3=>mdout1_3_22, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_22, D1=>mdout1_1_22, D2=>mdout1_2_22,
+ D3=>mdout1_3_22, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
Z=>Q(22));
mux_12: MUX41
- port map (D0=>mdout1_0_23, D1=>mdout1_1_23, D2=>mdout1_2_23,
- D3=>mdout1_3_23, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_23, D1=>mdout1_1_23, D2=>mdout1_2_23,
+ D3=>mdout1_3_23, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
Z=>Q(23));
mux_11: MUX41
- port map (D0=>mdout1_0_24, D1=>mdout1_1_24, D2=>mdout1_2_24,
- D3=>mdout1_3_24, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_24, D1=>mdout1_1_24, D2=>mdout1_2_24,
+ D3=>mdout1_3_24, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
Z=>Q(24));
mux_10: MUX41
- port map (D0=>mdout1_0_25, D1=>mdout1_1_25, D2=>mdout1_2_25,
- D3=>mdout1_3_25, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_25, D1=>mdout1_1_25, D2=>mdout1_2_25,
+ D3=>mdout1_3_25, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
Z=>Q(25));
mux_9: MUX41
- port map (D0=>mdout1_0_26, D1=>mdout1_1_26, D2=>mdout1_2_26,
- D3=>mdout1_3_26, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_26, D1=>mdout1_1_26, D2=>mdout1_2_26,
+ D3=>mdout1_3_26, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
Z=>Q(26));
mux_8: MUX41
- port map (D0=>mdout1_0_27, D1=>mdout1_1_27, D2=>mdout1_2_27,
- D3=>mdout1_3_27, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_27, D1=>mdout1_1_27, D2=>mdout1_2_27,
+ D3=>mdout1_3_27, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
Z=>Q(27));
mux_7: MUX41
- port map (D0=>mdout1_0_28, D1=>mdout1_1_28, D2=>mdout1_2_28,
- D3=>mdout1_3_28, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_28, D1=>mdout1_1_28, D2=>mdout1_2_28,
+ D3=>mdout1_3_28, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
Z=>Q(28));
mux_6: MUX41
- port map (D0=>mdout1_0_29, D1=>mdout1_1_29, D2=>mdout1_2_29,
- D3=>mdout1_3_29, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_29, D1=>mdout1_1_29, D2=>mdout1_2_29,
+ D3=>mdout1_3_29, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
Z=>Q(29));
mux_5: MUX41
- port map (D0=>mdout1_0_30, D1=>mdout1_1_30, D2=>mdout1_2_30,
- D3=>mdout1_3_30, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_30, D1=>mdout1_1_30, D2=>mdout1_2_30,
+ D3=>mdout1_3_30, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
Z=>Q(30));
mux_4: MUX41
- port map (D0=>mdout1_0_31, D1=>mdout1_1_31, D2=>mdout1_2_31,
- D3=>mdout1_3_31, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_31, D1=>mdout1_1_31, D2=>mdout1_2_31,
+ D3=>mdout1_3_31, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
Z=>Q(31));
mux_3: MUX41
- port map (D0=>mdout1_0_32, D1=>mdout1_1_32, D2=>mdout1_2_32,
- D3=>mdout1_3_32, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_32, D1=>mdout1_1_32, D2=>mdout1_2_32,
+ D3=>mdout1_3_32, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
Z=>Q(32));
mux_2: MUX41
- port map (D0=>mdout1_0_33, D1=>mdout1_1_33, D2=>mdout1_2_33,
- D3=>mdout1_3_33, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_33, D1=>mdout1_1_33, D2=>mdout1_2_33,
+ D3=>mdout1_3_33, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
Z=>Q(33));
mux_1: MUX41
- port map (D0=>mdout1_0_34, D1=>mdout1_1_34, D2=>mdout1_2_34,
- D3=>mdout1_3_34, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_34, D1=>mdout1_1_34, D2=>mdout1_2_34,
+ D3=>mdout1_3_34, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
Z=>Q(34));
mux_0: MUX41
- port map (D0=>mdout1_0_35, D1=>mdout1_1_35, D2=>mdout1_2_35,
- D3=>mdout1_3_35, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ port map (D0=>mdout1_0_35, D1=>mdout1_1_35, D2=>mdout1_2_35,
+ D3=>mdout1_3_35, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
Z=>Q(35));
wcnt_0: FSUB2B
- port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0,
+ port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0,
BI=>scuba_vlo, BOUT=>co0_5, S0=>open, S1=>wcnt_sub_0);
wcnt_1: FSUB2B
- port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2,
+ port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2,
BI=>co0_5, BOUT=>co1_5, S0=>wcnt_sub_1, S1=>wcnt_sub_2);
wcnt_2: FSUB2B
- port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4,
+ port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4,
BI=>co1_5, BOUT=>co2_5, S0=>wcnt_sub_3, S1=>wcnt_sub_4);
wcnt_3: FSUB2B
- port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6,
+ port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6,
BI=>co2_5, BOUT=>co3_5, S0=>wcnt_sub_5, S1=>wcnt_sub_6);
wcnt_4: FSUB2B
- port map (A0=>wcount_7, A1=>wcount_8, B0=>rptr_7, B1=>rptr_8,
+ port map (A0=>wcount_7, A1=>wcount_8, B0=>rptr_7, B1=>rptr_8,
BI=>co3_5, BOUT=>co4_5, S0=>wcnt_sub_7, S1=>wcnt_sub_8);
wcnt_5: FSUB2B
- port map (A0=>wcount_9, A1=>wcount_10, B0=>rptr_9, B1=>rptr_10,
+ port map (A0=>wcount_9, A1=>wcount_10, B0=>rptr_9, B1=>rptr_10,
BI=>co4_5, BOUT=>co5_5, S0=>wcnt_sub_9, S1=>wcnt_sub_10);
wcnt_6: FSUB2B
- port map (A0=>wcount_11, A1=>wcount_12, B0=>rptr_11, B1=>rptr_12,
+ port map (A0=>wcount_11, A1=>wcount_12, B0=>rptr_11, B1=>rptr_12,
BI=>co5_5, BOUT=>co6_3, S0=>wcnt_sub_11, S1=>wcnt_sub_12);
wcnt_7: FSUB2B
- port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, BI=>co6_3, BOUT=>open, S0=>wcnt_sub_13,
+ port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, BI=>co6_3, BOUT=>open, S0=>wcnt_sub_13,
S1=>open);
af_set_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
+ port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open);
af_set_cmp_0: AGEB2
- port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0),
+ port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0),
B1=>AmFullThresh(1), CI=>cmp_ci_2, GE=>co0_6);
af_set_cmp_1: AGEB2
- port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2),
+ port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2),
B1=>AmFullThresh(3), CI=>co0_6, GE=>co1_6);
af_set_cmp_2: AGEB2
- port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4),
+ port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4),
B1=>AmFullThresh(5), CI=>co1_6, GE=>co2_6);
af_set_cmp_3: AGEB2
- port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6),
+ port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6),
B1=>AmFullThresh(7), CI=>co2_6, GE=>co3_6);
af_set_cmp_4: AGEB2
- port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8),
+ port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8),
B1=>AmFullThresh(9), CI=>co3_6, GE=>co4_6);
af_set_cmp_5: AGEB2
- port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10),
+ port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10),
B1=>AmFullThresh(11), CI=>co4_6, GE=>co5_6);
af_set_cmp_6: AGEB2
- port map (A0=>wcnt_reg_12, A1=>wcnt_reg_13, B0=>AmFullThresh(12),
+ port map (A0=>wcnt_reg_12, A1=>wcnt_reg_13, B0=>AmFullThresh(12),
B1=>scuba_vlo, CI=>co5_6, GE=>af_set_c);
scuba_vlo_inst: VLO
port map (Z=>scuba_vlo);
a2: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set,
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set,
S1=>open);
WCNT(0) <= fcount_0;
jspc29 / trbnet.git / commitdiff