added multiple outputs to uart module

diff --git a/special/uart.vhd b/special/uart.vhd
index 9f86e9d58c107c90aff80e032c70e8748c247fa1..db69331fd6dca3e3bed86a6f50947cb5d3f08c2b 100644 (file)
--- a/special/uart.vhd
+++ b/special/uart.vhd
@@ -11,11 +11,14 @@ use machxo2.all;
 
 
 entity uart is
+  generic(
+    OUTPUTS : integer := 1
+    );
   port(
     CLK     : in  std_logic;
     RESET   : in  std_logic;
-    UART_RX : in  std_logic;
-    UART_TX : out std_logic;
+    UART_RX : in  std_logic_vector(0 to OUTPUTS-1);
+    UART_TX : out std_logic_vector(0 to OUTPUTS-1);
     
     DATA_OUT  : out std_logic_vector(31 downto 0);
     DATA_IN   : in  std_logic_vector(31 downto 0);
@@ -36,6 +39,9 @@ signal rx_data   : std_logic_vector(7 downto 0);
 signal rx_ready  : std_logic;
 signal tx_send   : std_logic;
 signal tx_ready  : std_logic;
+signal out_sel   : integer range 0 to 15 := 0;
+signal uart_sel_rx : std_logic;
+signal uart_sel_tx : std_logic;
 
 signal clk_div   : integer := 100000000/57600;
 
@@ -60,7 +66,7 @@ THE_RX : entity work.uart_rec
     CLK_DIV      => clk_div,
     CLK          => CLK,
     RST          => RESET,
-    RX           => UART_RX,
+    RX           => uart_sel_rx,
     DATA_OUT     => rx_data,
     DATA_WAITING => rx_ready
     );
@@ -73,7 +79,7 @@ THE_TX : entity work.uart_trans
     DATA_IN      => tx_fifo_out(7 downto 0),
     SEND         => tx_send,
     READY        => tx_ready,
-    TX           => UART_TX
+    TX           => uart_sel_tx
     );
 
     
@@ -125,6 +131,9 @@ PROC_REGS : process begin
     elsif ADDR_IN(3 downto 0) = x"1" then
       clk_div  <= to_integer(unsigned(DATA_IN));
       ACK_OUT  <= '1';
+    elsif ADDR_IN(3 downto 0) = x"2" then
+      out_sel  <= to_integer(unsigned(DATA_IN(3 downto 0)));
+      ACK_OUT  <= '1';
     else
       UNKWN_OUT     <= '1';
     end if;
@@ -136,6 +145,9 @@ PROC_REGS : process begin
     elsif ADDR_IN(3 downto 0) = x"1" then
       DATA_OUT <= std_logic_vector(to_unsigned(clk_div,32));
       ACK_OUT  <= '1';
+    elsif ADDR_IN(3 downto 0) = x"2" then
+      DATA_OUT(3 downto 0) <= std_logic_vector(to_unsigned(out_sel,4));
+      ACK_OUT  <= '1';
     else
       UNKWN_OUT <= '1';
     end if;
@@ -156,7 +168,13 @@ PROC_SEND : process begin
   end if;
   
 end process;
-    
+  
+proc_io : process begin
+  wait until rising_edge(CLK);
+  UART_TX <= (others => '1');
+  UART_TX(out_sel) <= uart_sel_tx;
+  uart_sel_rx <= UART_RX(out_sel);
+end process;
 
     
 end architecture;