*** empty log message ***

diff --git a/delaygbe.png b/delaygbe.png
new file mode 100644 (file)
index 0000000..46bc607
Binary files /dev/null and b/delaygbe.png differ

diff --git a/gbe.tex b/gbe.tex
index 50f68d127b9772767f0738e50647465540b8fa08..7c838589461a2ba6edd58e8b03c9a98078030bee 100644 (file)
--- a/gbe.tex
+++ b/gbe.tex
@@ -3,17 +3,19 @@
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 The configuration memory of the GbE interface consists of two parts. Registers 0x8300 to 0x83FF are used to configure the behaviour the SubEventBuilder and the packing of data into UDP packets. The registers implemented are listed in table \ref{GbEConfigRegisters}.
 
-The second part is located at addresses 0x8200 to 0x82F0. Each block of 16 addresses describes the addresses and ports used to send data to one of the Eventbuilders (see table \ref{GbEEBSettings}. Which entry in the memory is used, is selected by the lower 4 bits of the IPU readout information as shown in table \ref{IPUInformationBits}.
+The second part is located at addresses 0x8100 to 0x81F0. Each block of 16 addresses describes the addresses and ports used to send data to one of the Eventbuilders (see table \ref{GbEEBSettings}. Which entry in the memory is used, is selected by the lower 4 bits of the IPU readout information as shown in table \ref{IPUInformationBits}.
+
+Register 0x8309 is used to insert an additional delay between sending two UDP frames. Figure \ref{fig:gbedelay} shows the relationship between this setting and the achievable data rate.
 
 The GbE interface itself has a control and a status register, available at addresses 0xc020 and 0xc021 respectively:
 \begin{description}
- \item[0xc020: Control Register] PHY control register. Each of the bits has to be reset manually after use
+ \item[0x8020: Control Register] PHY control register. Each of the bits has to be reset manually after use
   \begin{description}
    \item[Bit 0]Restart Autonegotiation
    \item[Bit 1]PHY mode (must be 0)
    \item[Bit 3]PHY reset
   \end{description}
- \item[0xc021: Status Register] GbE link status register (detailed explanation: t.b.d.)
+ \item[0x8021: Status Register] GbE link status register (detailed explanation: t.b.d.)
   \begin{description}
    \item[Bit 15..0] Link partner page
    \item[Bit 16] Link partner page received (strobe signal)
@@ -23,7 +25,12 @@ The GbE interface itself has a control and a status register, available at addre
   \end{description}
 \end{description}
 
- 
+\begin{figure}
+       \centering
+               \includegraphics[width=12cm]{delaygbe.png}
+       \caption[Delay on GbE Interface]{Additional delay can be inserted between sending two UDP packets to reduce the total bandwidth. With no delay, 400 MBit/s (50 MByte/s) can be reached.}
+       \label{fig:gbedelay}
+\end{figure}
 
 \begin{table}[hbtp]
 \begin{center}
@@ -40,6 +47,7 @@ The GbE interface itself has a control and a status register, available at addre
 0x8306 & UseTrbNet        & Forward data over TrbNet (default: 0) \\
 0x8307 & MultiEventQueue  & Enable packing several events into one event queue (default: 0) \\
 0x8308 & TriggerCounter   & The internal, 24bit trigger counter used for the SubEventHeader (default: 0) \\
+0x8309 & DelayCounter     & Microseconds delay between sending two UDP packets \\
 0x83FF & ResetDefault     & When written to 0xFFFFFFFF: all values are reset to default \\
 \hline
 \end{tabularx}
@@ -54,15 +62,15 @@ The GbE interface itself has a control and a status register, available at addre
 \hline
 \textbf{Address} & \textbf{Name} & \textbf{Description} \\
 \hline\hline
-0x82S0 & DestMacLsb  & Lower 32 bits of the destination MAC address  \\
-0x82S1 & DestMacMsb  & Bit 15..0: Higher 16 bit of the destinatioon MAC, Bit 31..16: reserved\\
-0x82S2 & DestIP      & Destination IP \\
-0x82S3 & DestUdpPort & Bit 15..0: Destination UDP port, Bit 31..16: reserved \\
-0x82S4 & SrcMacLsb   & Lower 32 bits of the source MAC address \\
-0x82S5 & SrcMacMsb   & Bit 15..0: Higher 16 bit of the source MAC, Bit 31..16: reserved \\
-0x82S6 & SrcIP       & Source IP address \\
-0x82S7 & SrcUdpPort  & Bit 15..0: Source UDP port, Bit 31..16: reserved \\
-0x82S8 & MtuSize     & Bit 15..0: MTU size, Bit 31..16: reserved \\
+0x81S0 & DestMacLsb  & Lower 32 bits of the destination MAC address  \\
+0x81S1 & DestMacMsb  & Bit 15..0: Higher 16 bit of the destinatioon MAC, Bit 31..16: reserved\\
+0x81S2 & DestIP      & Destination IP \\
+0x81S3 & DestUdpPort & Bit 15..0: Destination UDP port, Bit 31..16: reserved \\
+0x81S4 & SrcMacLsb   & Lower 32 bits of the source MAC address \\
+0x81S5 & SrcMacMsb   & Bit 15..0: Higher 16 bit of the source MAC, Bit 31..16: reserved \\
+0x81S6 & SrcIP       & Source IP address \\
+0x81S7 & SrcUdpPort  & Bit 15..0: Source UDP port, Bit 31..16: reserved \\
+0x81S8 & MtuSize     & Bit 15..0: MTU size, Bit 31..16: reserved \\
 \hline
 \end{tabularx}
 \caption{Memory map for GbE Ethernet settings. The third digit is the EventBuilder number, allowing to stor 16 different settings that are selected by the IPU request information word.}

diff --git a/networkaddresses.tex b/networkaddresses.tex
index 42ae5831489925181a67b53067f74db9f5fc8b61..c34ba1b97ee0c2b5801c96fac67b178f1f10fde4 100755 (executable)
--- a/networkaddresses.tex
+++ b/networkaddresses.tex
@@ -1,4 +1,4 @@
-The documentation of network addresses can be found in the wiki: 
+The documentation of network addresses can be found in the wiki:
 \url{http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/NetworkAddresses}
 
 \subsection{Addressing scheme}
@@ -29,6 +29,7 @@ On boards with two or more FPGAs each FPGA gets its own address. The FPGA provid
 8400 - 84FF & RPC Hubs & Hubs for RPC, last digit: sector divided by 3 \\
 8500 - 85FF & Shower Hub & \\
 8600 - 86FF & TOF Hub & \\
+8700 - 87FF & Forward Wall Hub & \\
 F000 - FEFF & Test Setups & \\
 FF00 - FFFF & Broadcasts &
 \end{tabularx}
@@ -70,7 +71,7 @@ If the bitmask configuration of an endpoint contains two unset bits it will answ
 
 \subsection{SubEventIDs}
 \label{subeventids}
-The subevent ids are assigned based on the trbnet addresses of the board forming the subevent. The range in which TRBs are located is restricted due to demands of the unpacking software. 
+The subevent ids are assigned based on the trbnet addresses of the board forming the subevent. The range in which TRBs are located is restricted due to demands of the unpacking software.
 
 In summary, the only boards that send subevents are the Hubs, MDC Concentrators and Shower AddOns as well as the CTS. This sums up to 59 individual SubEvents.
 
@@ -85,10 +86,11 @@ Start/Veto & 4000 - 43FF & 1  & \\
 Forw. Wall & 4400 - 47FF & 3  & last digit is the segment of FW \\
 RPC        & 4800 - 4BFF & 24 & 3rd digit is the sector, last digit normal(0) or additional(1) TRB \\
 TOF        & 4C00 - 4FFF & 9  & 3rd digit is normal(0) or additional(1) TRB, last digit is the sector \\
+Start/Veto & 8000 - 80FF & 1 & Start / Veto / Forward Wall readout via GbE \\
 RICH       & 8300 - 83FF & 3  & last digit is the sector divided by 2 \\
 RPC *)     & 8400 - 84FF & 2  & RPC readout via GbE \\
 TOF *)     & 8600 - 86FF & 1  & TOF readout via GbE \\
-Wall/Start/Veto & 8000 - 80FF & 1 & Start / Veto / Forward Wall readout via GbE \\
+Wall *)    & 8700 - 87FF & 1  & Forward Wall readout via GbE \\
 \end{tabularx}
 \caption{Reserved SubEvent IDs Ranges. The star marks possible future setups which are not implemented now but might come later. In that case, data from several TRB (only from one subsystem) will be merged into one SubEvent. The id of each TRB is still available inside the data stream.}
 \label{subeventidtable}

diff --git a/slowcontrol.tex b/slowcontrol.tex
index 4d302cc8cd2b2ec891e2a74b433cf1b03e58d3ca..4aa0ea449a72a0cc39619faa9cb008f7a68a1869 100755 (executable)
--- a/slowcontrol.tex
+++ b/slowcontrol.tex
@@ -255,7 +255,7 @@ E000 - FFFF & Debugging & Memories and Registers for Debugging \\
 The first common status register is described in table \ref{CommonStatReg0}. It is used for error flags and readback of the boards temperature. The second status register is used to read the LVL1 trigger number of the last timing trigger (Bits 15 - 0) and the number of the event last read on the IPU channel (Bits 31 - 16).
 
 
-The first common control register consists of strobe signals for dummy timing triggers and reset signals as shown in table \ref{CommonCtrlReg0}. The second common control register is used to set the current LVL1 trigger number (Bits 15 - 0) and the number of received timing triggers (Bits 31-16).
+The first common control register consists of strobe signals for dummy timing triggers and reset signals as shown in table \ref{CommonCtrlReg0}. N.B. before a complete reset or reboot is executed, a delay of about 3~us has to be included to allow the endpoint to send back a correct answer. The second common control register is used to set the current LVL1 trigger number (Bits 15 - 0) and the number of received timing triggers (Bits 31-16).
 
 \begin{table}
 \begin{center}