LOCATE COMP "TEST_LINE_14" SITE "H10";
LOCATE COMP "TEST_LINE_15" SITE "H11";
DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
-#IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12;
-IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN;
+IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN SLEWRATE=FAST;
#################################################################
# Connection to AddOn
<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="ram_dp_128x32" module="RAM_DP" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 12 13 22:59:17.398" version="6.1" type="Module" synthesis="" source_format="VHDL">
+<DiamondModule name="ram_dp_128x32" module="RAM_DP" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 12 15 15:23:00.769" version="6.1" type="Module" synthesis="" source_format="VHDL">
<Package>
- <File name="" type="mem" modified="2013 12 13 22:59:17.000"/>
- <File name="ram_dp_128x32.lpc" type="lpc" modified="2013 12 13 22:59:16.000"/>
- <File name="ram_dp_128x32.vhd" type="top_level_vhdl" modified="2013 12 13 22:59:16.000"/>
- <File name="ram_dp_128x32_tmpl.vhd" type="template_vhdl" modified="2013 12 13 22:59:16.000"/>
- <File name="tb_ram_dp_128x32_tmpl.vhd" type="testbench_vhdl" modified="2013 12 13 22:59:16.000"/>
+ <File name="" type="mem" modified="2013 12 15 15:23:00.000"/>
+ <File name="ram_dp_128x32.lpc" type="lpc" modified="2013 12 15 15:22:59.000"/>
+ <File name="ram_dp_128x32.vhd" type="top_level_vhdl" modified="2013 12 15 15:22:59.000"/>
+ <File name="ram_dp_128x32_tmpl.vhd" type="template_vhdl" modified="2013 12 15 15:22:59.000"/>
+ <File name="tb_ram_dp_128x32_tmpl.vhd" type="testbench_vhdl" modified="2013 12 15 15:22:59.000"/>
</Package>
</DiamondModule>
ModuleName=ram_dp_128x32
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=12/13/2013
-Time=22:59:16
+Date=12/15/2013
+Time=15:22:59
[Parameters]
Verilog=0
ByteSize=9
adPipeline=0
inPipeline=0
-outPipeline=0
+outPipeline=1
MOR=0
InData=Registered
AdControl=Registered
-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
-- Module Version: 6.1
---/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 10 -rp 0011 -rdata_width 32 -data_width 32 -num_rows 128 -cascade -1 -e
+--/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 10 -rp 0011 -rdata_width 32 -data_width 32 -num_rows 128 -outdata REGISTERED -cascade -1 -e
--- Fri Dec 13 22:59:16 2013
+-- Sun Dec 15 15:22:59 2013
library IEEE;
use IEEE.std_logic_1164.all;
ram_dp_128x32_0_0_0: PDPW16KC
generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
+ REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
ERROR_ADC0_OUT <= error_adc0_o;
ERROR_ADC1_OUT <= error_adc1_o;
-end architecture;
+end Behavioral;
end entity;
-architecture Gray_Decoder of Gray_Decoder is
+architecture Behavioral of Gray_Decoder is
signal binary_o : std_logic_vector(WIDTH - 1 downto 0);
-- Output
BINARY_OUT <= binary_o;
-end Gray_Decoder;
+end Behavioral;
CLK_IN : in std_logic;
RESET_IN : in std_logic;
+
+ NUM_AVERAGES_IN : in unsigned(2 downto 0);
+ AVERAGE_ENABLE_IN : in std_logic;
CHANNEL_ID_IN : in std_logic_vector(BUS_WIDTH - 1 downto 0);
CHANNEL_DATA_IN : in std_logic_vector(DATA_WIDTH - 1 downto 0);
CHANNEL_ADD_IN : in std_logic;
CHANNEL_WRITE_IN : in std_logic;
CHANNEL_WRITE_BUSY_OUT : out std_logic;
-
+
CHANNEL_ID_READ_IN : in std_logic_vector(BUS_WIDTH - 1 downto 0);
CHANNEL_READ_IN : in std_logic;
CHANNEL_DATA_OUT : out std_logic_vector(DATA_WIDTH - 1 downto 0);
-- Hist Fill/Ctr Handler
type H_STATES is (H_IDLE,
+ H_WRITEADD_CHANNEL,
H_WRITE_CHANNEL
);
signal H_STATE, H_NEXT_STATE : H_STATES;
signal data_hist_m_x : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal read_data_hist : std_logic_vector(DATA_WIDTH - 1 downto 0);
+ signal read_data_ctr_hist : unsigned(7 downto 0);
signal read_address_hist : std_logic_vector(BUS_WIDTH - 1 downto 0);
signal read_enable_hist : std_logic;
- signal write_address_hist : std_logic_vector(BUS_WIDTH - 1 downto 0);
signal write_data_hist : std_logic_vector(DATA_WIDTH - 1 downto 0);
+ signal write_data_ctr_hist : unsigned(7 downto 0);
+ signal write_address_hist : std_logic_vector(BUS_WIDTH - 1 downto 0);
signal write_enable_hist : std_logic;
signal write_address : std_logic_vector(BUS_WIDTH - 1 downto 0);
DEBUG_OUT(5) <= CHANNEL_READ_IN;
DEBUG_OUT(6) <= read_enable_hist;
DEBUG_OUT(7) <= channel_data_valid_o;
- DEBUG_OUT(15 downto 8) <= channel_data_o(7 downto 0);
+-- DEBUG_OUT(15 downto 8) <= channel_data_o(7 downto 0);
+ DEBUG_OUT(14 downto 8) <= CHANNEL_ID_IN;
+ DEBUG_OUT(15) <= '0';
-----------------------------------------------------------------------------
- ram_dp_128x32_hist: ram_dp_128x32
+ ram_dp_128x40_hist: ram_dp_128x40
port map (
- WrAddress => write_address_hist,
- RdAddress => read_address_hist,
- Data => write_data_hist,
- WE => not RESET_IN,
- RdClock => CLK_IN,
- RdClockEn => read_enable_hist,
- Reset => RESET_IN,
- WrClock => CLK_IN,
- WrClockEn => write_enable_hist,
- Q => read_data_hist
+ WrAddress => write_address_hist,
+ RdAddress => read_address_hist,
+ Data(31 downto 0) => write_data_hist,
+ Data(39 downto 32) => write_data_ctr_hist,
+ WE => not RESET_IN,
+ RdClock => CLK_IN,
+ RdClockEn => read_enable_hist,
+ Reset => RESET_IN,
+ WrClock => CLK_IN,
+ WrClockEn => write_enable_hist,
+ Q(31 downto 0) => read_data_hist,
+ Q(39 downto 32) => read_data_ctr_hist
);
ram_dp_128x32_result: ram_dp_128x32
read_address <= CHANNEL_ID_READ_IN;
channel_data_valid_o_f <= CHANNEL_READ_IN when rising_edge(CLK_IN);
channel_data_valid_o <= channel_data_valid_o_f when rising_edge(CLK_IN);
- channel_data_o <= read_data when rising_edge(CLK_IN);
+ channel_data_o <= read_data;
PROC_HIST_HANDLER_TRANSFER: process(CLK_IN)
begin
case H_STATE is
when H_IDLE =>
- write_address_hist <= (others => '0');
- write_data_hist <= (others => '0');
- write_enable_hist <= '0';
- write_address <= (others => '0');
- write_data <= (others => '0');
- write_enable <= '0';
+ write_address_hist <= (others => '0');
+ write_data_hist <= (others => '0');
+ write_data_ctr_hist <= (others => '0');
+ write_enable_hist <= '0';
+ write_address <= (others => '0');
+ write_data <= (others => '0');
+ write_enable <= '0';
if (CHANNEL_ADD_IN = '1') then
read_address_hist <= CHANNEL_ID_IN;
address_hist_m_x <= CHANNEL_ID_IN;
data_hist_m_x <= CHANNEL_DATA_IN;
channel_write_busy_o <= '1';
+ H_NEXT_STATE <= H_WRITEADD_CHANNEL;
+ elsif (CHANNEL_WRITE_IN = '1') then
+ read_address_hist <= (others => '0');
+ read_enable_hist <= '0';
+ address_hist_m_x <= CHANNEL_ID_IN;
+ data_hist_m_x <= CHANNEL_DATA_IN;
+ channel_write_busy_o <= '1';
H_NEXT_STATE <= H_WRITE_CHANNEL;
else
read_address_hist <= (others => '0');
H_NEXT_STATE <= H_IDLE;
end if;
+ when H_WRITEADD_CHANNEL =>
+ if (AVERAGE_ENABLE_IN = '0') then
+ new_data := std_logic_vector(unsigned(read_data_hist) +
+ unsigned(data_hist_m));
+ write_data_ctr_hist <= read_data_ctr_hist + 1;
+
+ write_address <= address_hist_m;
+ write_data <= new_data;
+ write_enable <= '1';
+ elsif ((read_data_ctr_hist srl to_integer(NUM_AVERAGES_IN)) > 0)
+ then
+ new_data := std_logic_vector(unsigned(data_hist_m));
+ write_data_ctr_hist <= x"01";
+
+ write_address <= address_hist_m;
+ write_data <= new_data;
+ write_enable <= '1';
+ else
+ new_data := std_logic_vector(unsigned(read_data_hist) +
+ unsigned(data_hist_m));
+ write_data_ctr_hist <= read_data_ctr_hist + 1;
+
+ write_address <= (others => '0');
+ write_data <= (others => '0');
+ write_enable <= '0';
+ end if;
+
+ read_address_hist <= (others => '0');
+ read_enable_hist <= '0';
+ write_address_hist <= address_hist_m;
+ write_data_hist <= new_data;
+ write_enable_hist <= '1';
+ channel_write_busy_o <= '1';
+ H_NEXT_STATE <= H_IDLE;
+
when H_WRITE_CHANNEL =>
- new_data :=
- std_logic_vector(unsigned(read_data_hist) + unsigned(data_hist_m));
+ new_data := unsigned(data_hist_m);
read_address_hist <= (others => '0');
read_enable_hist <= '0';
write_address_hist <= address_hist_m;
write_data_hist <= new_data;
+ write_data_ctr_hist <= (others => '0');
write_enable_hist <= '1';
write_address <= address_hist_m;
write_enable <= '1';
channel_write_busy_o <= '1';
H_NEXT_STATE <= H_IDLE;
+
end case;
end process PROC_HIST_HANDLER;
RESET_HISTS_IN : in std_logic;
- CHANNEL_STAT_FILL_IN : in std_logic;
+ CHANNEL_FILL_IN : in std_logic;
CHANNEL_ID_IN : in std_logic_vector(6 downto 0);
CHANNEL_ADC_IN : in std_logic_vector(11 downto 0);
+ CHANNEL_PILEUP_IN : in std_logic;
+ CHANNEL_OVERFLOW_IN : in std_logic;
-- Slave bus
SLV_READ_IN : in std_logic;
end entity;
-architecture nx_histograms of nx_histograms is
+architecture Behavioral of nx_histograms is
--- Histograms
- signal hist_write_busy : std_logic;
- signal hist_read_busy : std_logic;
+ -- Hit Histogram
+ signal hit_num_averages : unsigned(2 downto 0);
+ signal hit_average_enable : std_logic;
+ signal hit_write_busy : std_logic;
+ signal hit_read_busy : std_logic;
- signal hist_write_id : std_logic_vector(6 downto 0);
- signal hist_write_data : std_logic_vector(31 downto 0);
- signal hist_write : std_logic;
- signal hist_add : std_logic;
+ signal hit_write_id : std_logic_vector(6 downto 0);
+ signal hit_write_data : std_logic_vector(31 downto 0);
+ signal hit_write : std_logic;
+ signal hit_add : std_logic;
- signal hist_read_id : std_logic_vector(6 downto 0);
- signal hist_read : std_logic;
- signal hist_read_data : std_logic_vector(31 downto 0);
- signal hist_read_data_valid : std_logic;
+ signal hit_read_id : std_logic_vector(6 downto 0);
+ signal hit_read : std_logic;
+ signal hit_read_data : std_logic_vector(31 downto 0);
+ signal hit_read_data_valid : std_logic;
- signal write_ctr : unsigned(11 downto 0);
+ -- PileUp Histogram
+ signal pileup_num_averages : unsigned(2 downto 0);
+ signal pileup_average_enable : std_logic;
+ signal pileup_write_busy : std_logic;
+ signal pileup_read_busy : std_logic;
+
+ signal pileup_write_id : std_logic_vector(6 downto 0);
+ signal pileup_write_data : std_logic_vector(31 downto 0);
+ signal pileup_write : std_logic;
+ signal pileup_add : std_logic;
+
+ signal pileup_read_id : std_logic_vector(6 downto 0);
+ signal pileup_read : std_logic;
+ signal pileup_read_data : std_logic_vector(31 downto 0);
+ signal pileup_read_data_valid : std_logic;
+
+ -- OverFlow Histogram
+ signal ovfl_num_averages : unsigned(2 downto 0);
+ signal ovfl_average_enable : std_logic;
+ signal ovfl_write_busy : std_logic;
+ signal ovfl_read_busy : std_logic;
+
+ signal ovfl_write_id : std_logic_vector(6 downto 0);
+ signal ovfl_write_data : std_logic_vector(31 downto 0);
+ signal ovfl_write : std_logic;
+ signal ovfl_add : std_logic;
+
+ signal ovfl_read_id : std_logic_vector(6 downto 0);
+ signal ovfl_read : std_logic;
+ signal ovfl_read_data : std_logic_vector(31 downto 0);
+ signal ovfl_read_data_valid : std_logic;
+
+ -- ADC Value Histogram
+ signal adc_num_averages : unsigned(2 downto 0);
+ signal adc_average_enable : std_logic;
+ signal adc_write_busy : std_logic;
+ signal adc_read_busy : std_logic;
+ signal adc_write_id : std_logic_vector(6 downto 0);
+ signal adc_write_data : std_logic_vector(31 downto 0);
+ signal adc_write : std_logic;
+ signal adc_add : std_logic;
+
+ signal adc_read_id : std_logic_vector(6 downto 0);
+ signal adc_read : std_logic;
+ signal adc_read_data : std_logic_vector(31 downto 0);
+ signal adc_read_data_valid : std_logic;
+
-- Slave Bus
signal slv_data_out_o : std_logic_vector(31 downto 0);
signal slv_no_more_data_o : std_logic;
signal slv_unknown_addr_o : std_logic;
signal slv_ack_o : std_logic;
- signal reset_hists_r : std_logic;
begin
---------------------------------------------------------------------------
- nx_histogram_1: nx_histogram
- generic map (
- BUS_WIDTH => 7,
- DATA_WIDTH => 32
- )
+
+ -- DEBUG_OUT(0) <= SLV_READ_IN;
+ -- DEBUG_OUT(15 downto 1) <= SLV_ADDR_IN(14 downto 0);
+
+ -----------------------------------------------------------------------------
+
+ nx_histogram_hits: nx_histogram
port map (
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
- CHANNEL_ID_IN => hist_write_id,
- CHANNEL_DATA_IN => hist_write_data,
- CHANNEL_ADD_IN => hist_add,
- CHANNEL_WRITE_IN => hist_write,
- CHANNEL_WRITE_BUSY_OUT => hist_write_busy,
+ NUM_AVERAGES_IN => hit_num_averages,
+ AVERAGE_ENABLE_IN => hit_average_enable,
+ CHANNEL_ID_IN => hit_write_id,
+ CHANNEL_DATA_IN => hit_write_data,
+ CHANNEL_ADD_IN => hit_add,
+ CHANNEL_WRITE_IN => hit_write,
+ CHANNEL_WRITE_BUSY_OUT => hit_write_busy,
- CHANNEL_ID_READ_IN => hist_read_id,
- CHANNEL_READ_IN => hist_read,
- CHANNEL_DATA_OUT => hist_read_data,
- CHANNEL_DATA_VALID_OUT => hist_read_data_valid,
- CHANNEL_READ_BUSY_OUT => hist_read_busy,
+ CHANNEL_ID_READ_IN => hit_read_id,
+ CHANNEL_READ_IN => hit_read,
+ CHANNEL_DATA_OUT => hit_read_data,
+ CHANNEL_DATA_VALID_OUT => hit_read_data_valid,
+ CHANNEL_READ_BUSY_OUT => hit_read_busy,
- DEBUG_OUT => DEBUG_OUT
+ DEBUG_OUT => open
);
+ nx_histogram_adc: nx_histogram
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+
+ NUM_AVERAGES_IN => adc_num_averages,
+ AVERAGE_ENABLE_IN => adc_average_enable,
+ CHANNEL_ID_IN => adc_write_id,
+ CHANNEL_DATA_IN => adc_write_data,
+ CHANNEL_ADD_IN => adc_add,
+ CHANNEL_WRITE_IN => adc_write,
+ CHANNEL_WRITE_BUSY_OUT => adc_write_busy,
+
+ CHANNEL_ID_READ_IN => adc_read_id,
+ CHANNEL_READ_IN => adc_read,
+ CHANNEL_DATA_OUT => adc_read_data,
+ CHANNEL_DATA_VALID_OUT => adc_read_data_valid,
+ CHANNEL_READ_BUSY_OUT => adc_read_busy,
+
+ DEBUG_OUT => open
+ );
+
+ nx_histogram_pileup: nx_histogram
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+
+ NUM_AVERAGES_IN => pileup_num_averages,
+ AVERAGE_ENABLE_IN => pileup_average_enable,
+ CHANNEL_ID_IN => pileup_write_id,
+ CHANNEL_DATA_IN => pileup_write_data,
+ CHANNEL_ADD_IN => pileup_add,
+ CHANNEL_WRITE_IN => pileup_write,
+ CHANNEL_WRITE_BUSY_OUT => pileup_write_busy,
+
+ CHANNEL_ID_READ_IN => pileup_read_id,
+ CHANNEL_READ_IN => pileup_read,
+ CHANNEL_DATA_OUT => pileup_read_data,
+ CHANNEL_DATA_VALID_OUT => pileup_read_data_valid,
+ CHANNEL_READ_BUSY_OUT => pileup_read_busy,
+
+ DEBUG_OUT => DEBUG_OUT --open
+ );
+
+ nx_histogram_ovfl: nx_histogram
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+
+ NUM_AVERAGES_IN => ovfl_num_averages,
+ AVERAGE_ENABLE_IN => ovfl_average_enable,
+ CHANNEL_ID_IN => ovfl_write_id,
+ CHANNEL_DATA_IN => ovfl_write_data,
+ CHANNEL_ADD_IN => ovfl_add,
+ CHANNEL_WRITE_IN => ovfl_write,
+ CHANNEL_WRITE_BUSY_OUT => ovfl_write_busy,
+
+ CHANNEL_ID_READ_IN => ovfl_read_id,
+ CHANNEL_READ_IN => ovfl_read,
+ CHANNEL_DATA_OUT => ovfl_read_data,
+ CHANNEL_DATA_VALID_OUT => ovfl_read_data_valid,
+ CHANNEL_READ_BUSY_OUT => ovfl_read_busy,
+
+ DEBUG_OUT => open
+ );
+
-----------------------------------------------------------------------------
-- Fill Histograms
-----------------------------------------------------------------------------
begin
if (rising_edge(CLK_IN)) then
if (RESET_IN = '1') then
- hist_write_id <= CHANNEL_ID_IN;
- hist_write_data <= (others => '0');
- hist_write <= '0';
- hist_add <= '0';
- write_ctr <= (others => '0');
+ hit_write_id <= (others => '0');
+ hit_write_data <= (others => '0');
+ hit_write <= '0';
+ hit_add <= '0';
+
+ adc_write_id <= (others => '0');
+ adc_write_data <= (others => '0');
+ adc_write <= '0';
+ adc_add <= '0';
+
+ pileup_write_id <= (others => '0');
+ pileup_write_data <= (others => '0');
+ pileup_write <= '0';
+ pileup_add <= '0';
+
+ ovfl_write_id <= (others => '0');
+ ovfl_write_data <= (others => '0');
+ ovfl_write <= '0';
+ ovfl_add <= '0';
else
- hist_write_id <= (others => '0');
- hist_write_data <= (others => '0');
- hist_write <= '0';
- hist_add <= '0';
-
- if (CHANNEL_STAT_FILL_IN = '1' and hist_write_busy = '0') then
- hist_write_id <= CHANNEL_ID_IN;
- hist_write_data(11 downto 0) <= x"001"; --CHANNEL_ADC_IN;
- hist_write_data(31 downto 12) <= (others => '0');
- hist_add <= '1';
-
- write_ctr <= write_ctr + 1;
+ hit_write_id <= (others => '0');
+ hit_write_data <= (others => '0');
+ hit_write <= '0';
+ hit_add <= '0';
+
+ adc_write_id <= (others => '0');
+ adc_write_data <= (others => '0');
+ adc_write <= '0';
+ adc_add <= '0';
+
+ pileup_write_id <= (others => '0');
+ pileup_write_data <= (others => '0');
+ pileup_write <= '0';
+ pileup_add <= '0';
+
+ ovfl_write_id <= (others => '0');
+ ovfl_write_data <= (others => '0');
+ ovfl_write <= '0';
+ ovfl_add <= '0';
+
+ if (CHANNEL_FILL_IN = '1' and hit_write_busy = '0') then
+ hit_write_id <= CHANNEL_ID_IN;
+ hit_write_data <= x"0000_0001";
+ hit_add <= '1';
+
+ adc_write_id <= CHANNEL_ID_IN;
+ adc_write_data(11 downto 0) <= CHANNEL_ADC_IN;
+ adc_write_data(31 downto 12) <= (others => '0');
+ adc_add <= '1';
+
+ if (CHANNEL_PILEUP_IN = '1') then
+ pileup_write_id <= CHANNEL_ID_IN;
+ pileup_write_data <= x"0000_0001";
+ pileup_add <= '1';
+ end if;
+
+ if (CHANNEL_OVERFLOW_IN = '1') then
+ ovfl_write_id <= CHANNEL_ID_IN;
+ ovfl_write_data <= x"0000_0001";
+ ovfl_add <= '1';
+ end if;
+
end if;
end if;
end if;
end process PROC_FILL_HISTOGRAMS;
-
+
---------------------------------------------------------------------------
-- TRBNet Slave Bus
---------------------------------------------------------------------------
begin
if( rising_edge(CLK_IN) ) then
if( RESET_IN = '1' ) then
- slv_data_out_o <= (others => '0');
- slv_no_more_data_o <= '0';
- slv_unknown_addr_o <= '0';
- slv_ack_o <= '0';
+ slv_data_out_o <= (others => '0');
+ slv_no_more_data_o <= '0';
+ slv_unknown_addr_o <= '0';
+ slv_ack_o <= '0';
+
+ hit_read_id <= (others => '0');
+ hit_read <= '0';
+ hit_num_averages <= "000";
+ hit_average_enable <= '0';
- hist_read_id <= (others => '0');
- hist_read <= '0';
+ adc_read_id <= (others => '0');
+ adc_read <= '0';
+ adc_num_averages <= "001";
+ adc_average_enable <= '1';
+
+ pileup_read_id <= (others => '0');
+ pileup_read <= '0';
+ pileup_num_averages <= "000";
+ pileup_average_enable <= '0';
+
+ ovfl_read_id <= (others => '0');
+ ovfl_read <= '0';
+ ovfl_num_averages <= "000";
+ ovfl_average_enable <= '0';
else
- slv_data_out_o <= (others => '0');
- slv_unknown_addr_o <= '0';
- slv_no_more_data_o <= '0';
+ slv_data_out_o <= (others => '0');
+ slv_unknown_addr_o <= '0';
+ slv_no_more_data_o <= '0';
- hist_read_id <= (others => '0');
- hist_read <= '0';
+ hit_read_id <= (others => '0');
+ hit_read <= '0';
+ adc_read_id <= (others => '0');
+ adc_read <= '0';
+ pileup_read_id <= (others => '0');
+ pileup_read <= '0';
+ ovfl_read_id <= (others => '0');
+ ovfl_read <= '0';
- if (hist_read_busy = '1') then
- if (hist_read_data_valid = '1') then
- slv_data_out_o <= hist_read_data;
- slv_ack_o <= '1';
+ if (hit_read_busy = '1' or
+ adc_read_busy = '1' or
+ pileup_read_busy = '1' or
+ ovfl_read_busy = '1' ) then
+ if (hit_read_data_valid = '1') then
+ slv_data_out_o <= hit_read_data;
+ slv_ack_o <= '1';
+ elsif (adc_read_data_valid = '1') then
+ slv_data_out_o <= adc_read_data;
+ slv_ack_o <= '1';
+ elsif (pileup_read_data_valid = '1') then
+ slv_data_out_o <= pileup_read_data;
+ slv_ack_o <= '1';
+ elsif (ovfl_read_data_valid = '1') then
+ slv_data_out_o <= ovfl_read_data;
+ slv_ack_o <= '1';
else
- slv_ack_o <= '0';
+ slv_ack_o <= '0';
end if;
elsif (SLV_READ_IN = '1') then
if (unsigned(SLV_ADDR_IN) >= x"0000" and
unsigned(SLV_ADDR_IN) <= x"007f") then
- hist_read_id <= SLV_ADDR_IN(6 downto 0);
- hist_read <= '1';
- slv_ack_o <= '0';
+ hit_read_id <= SLV_ADDR_IN(6 downto 0);
+ hit_read <= '1';
+ slv_ack_o <= '0';
+ elsif (unsigned(SLV_ADDR_IN) >= x"0100" and
+ unsigned(SLV_ADDR_IN) <= x"017f") then
+ adc_read_id <= SLV_ADDR_IN(6 downto 0);
+ adc_read <= '1';
+ slv_ack_o <= '0';
+ elsif (unsigned(SLV_ADDR_IN) >= x"0200" and
+ unsigned(SLV_ADDR_IN) <= x"027f") then
+ pileup_read_id <= SLV_ADDR_IN(6 downto 0);
+ pileup_read <= '1';
+ slv_ack_o <= '0';
+ elsif (unsigned(SLV_ADDR_IN) >= x"0300" and
+ unsigned(SLV_ADDR_IN) <= x"037f") then
+ ovfl_read_id <= SLV_ADDR_IN(6 downto 0);
+ ovfl_read <= '1';
+ slv_ack_o <= '0';
else
- slv_unknown_addr_o <= '1';
- slv_ack_o <= '0';
+ case SLV_ADDR_IN is
+ when x"0080" =>
+ slv_data_out_o(2 downto 0) <=
+ std_logic_vector(hit_num_averages);
+ slv_data_out_o(31 downto 3) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"0081" =>
+ slv_data_out_o(0) <= hit_average_enable;
+ slv_data_out_o(31 downto 1) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"0180" =>
+ slv_data_out_o(2 downto 0) <=
+ std_logic_vector(adc_num_averages);
+ slv_data_out_o(31 downto 3) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"0181" =>
+ slv_data_out_o(0) <= adc_average_enable;
+ slv_data_out_o(31 downto 1) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"0280" =>
+ slv_data_out_o(2 downto 0) <=
+ std_logic_vector(pileup_num_averages);
+ slv_data_out_o(31 downto 3) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"0281" =>
+ slv_data_out_o(0) <= pileup_average_enable;
+ slv_data_out_o(31 downto 1) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"0380" =>
+ slv_data_out_o(2 downto 0) <=
+ std_logic_vector(ovfl_num_averages);
+ slv_data_out_o(31 downto 3) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"0381" =>
+ slv_data_out_o(0) <= ovfl_average_enable;
+ slv_data_out_o(31 downto 1) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when others =>
+ slv_unknown_addr_o <= '1';
+ slv_ack_o <= '0';
+
+ end case;
end if;
elsif (SLV_WRITE_IN = '1') then
case SLV_ADDR_IN is
+ when x"0080" =>
+ hit_num_averages <= SLV_DATA_IN(2 downto 0);
+ slv_ack_o <= '1';
+
+ when x"0081" =>
+ hit_average_enable <= SLV_DATA_IN(0);
+ slv_ack_o <= '1';
+
+ when x"0180" =>
+ adc_num_averages <= SLV_DATA_IN(2 downto 0);
+ slv_ack_o <= '1';
+
+ when x"0181" =>
+ adc_average_enable <= SLV_DATA_IN(0);
+ slv_ack_o <= '1';
+
+ when x"0280" =>
+ pileup_num_averages <= SLV_DATA_IN(2 downto 0);
+ slv_ack_o <= '1';
+
+ when x"0281" =>
+ pileup_average_enable <= SLV_DATA_IN(0);
+ slv_ack_o <= '1';
+
+ when x"0380" =>
+ ovfl_num_averages <= SLV_DATA_IN(2 downto 0);
+ slv_ack_o <= '1';
+ when x"0381" =>
+ ovfl_average_enable <= SLV_DATA_IN(0);
+ slv_ack_o <= '1';
+
when others =>
- slv_unknown_addr_o <= '1';
- slv_ack_o <= '0';
+ slv_unknown_addr_o <= '1';
+ slv_ack_o <= '0';
end case;
else
- slv_ack_o <= '0';
+ slv_ack_o <= '0';
end if;
end if;
end if;
SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;
SLV_ACK_OUT <= slv_ack_o;
-end nx_histograms;
+end Behavioral;
BOARD_ID : std_logic_vector(15 downto 0) := x"ffff"
);
port (
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
-
- -- Inputs
- DATA_CLK_IN : in std_logic;
- TIMESTAMP_IN : in std_logic_vector(13 downto 0);
- CHANNEL_IN : in std_logic_vector(6 downto 0);
- TIMESTAMP_STATUS_IN : in std_logic_vector(2 downto 0); -- 2: parity
- ADC_DATA_IN : in std_logic_vector(11 downto 0); -- 1: pileup
- NX_TOKEN_RETURN_IN : in std_logic; -- 0: ovfl
- NX_NOMORE_DATA_IN : in std_logic;
-
- TRIGGER_IN : in std_logic;
- TRIGGER_BUSY_IN : in std_logic;
- FAST_CLEAR_IN : in std_logic;
- TRIGGER_BUSY_OUT : out std_logic;
- TIMESTAMP_FPGA_IN : in unsigned(11 downto 0);
- DATA_FIFO_DELAY_OUT : out std_logic_vector(7 downto 0);
-
- -- Event Buffer I/O
- DATA_OUT : out std_logic_vector(31 downto 0);
- DATA_CLK_OUT : out std_logic;
- NOMORE_DATA_OUT : out std_logic;
- EVT_BUFFER_CLEAR_OUT : out std_logic;
- EVT_BUFFER_FULL_IN : in std_logic;
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+
+ -- Inputs
+ DATA_CLK_IN : in std_logic;
+ TIMESTAMP_IN : in std_logic_vector(13 downto 0);
+ CHANNEL_IN : in std_logic_vector(6 downto 0);
+ TIMESTAMP_STATUS_IN : in std_logic_vector(2 downto 0); -- 2: parity
+ ADC_DATA_IN : in std_logic_vector(11 downto 0); -- 1: pileup
+ NX_TOKEN_RETURN_IN : in std_logic; -- 0: ovfl
+ NX_NOMORE_DATA_IN : in std_logic;
+
+ TRIGGER_IN : in std_logic;
+ TRIGGER_BUSY_IN : in std_logic;
+ FAST_CLEAR_IN : in std_logic;
+ TRIGGER_BUSY_OUT : out std_logic;
+ TIMESTAMP_FPGA_IN : in unsigned(11 downto 0);
+ DATA_FIFO_DELAY_OUT : out std_logic_vector(7 downto 0);
+
+ -- Event Buffer I/O
+ DATA_OUT : out std_logic_vector(31 downto 0);
+ DATA_CLK_OUT : out std_logic;
+ NOMORE_DATA_OUT : out std_logic;
+ EVT_BUFFER_CLEAR_OUT : out std_logic;
+ EVT_BUFFER_FULL_IN : in std_logic;
-- Histogram
- HISTOGRAM_FILL_OUT : out std_logic;
- HISTOGRAM_BIN_OUT : out std_logic_vector(6 downto 0);
- HISTOGRAM_ADC_OUT : out std_logic_vector(11 downto 0);
+ HISTOGRAM_FILL_OUT : out std_logic;
+ HISTOGRAM_BIN_OUT : out std_logic_vector(6 downto 0);
+ HISTOGRAM_ADC_OUT : out std_logic_vector(11 downto 0);
+ HISTOGRAM_PILEUP_OUT : out std_logic;
+ HISTOGRAM_OVERFLOW_OUT : out std_logic;
-- Slave bus
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_ADDR_IN : in std_logic_vector(15 downto 0);
- SLV_ACK_OUT : out std_logic;
- SLV_NO_MORE_DATA_OUT : out std_logic;
- SLV_UNKNOWN_ADDR_OUT : out std_logic;
-
- DEBUG_OUT : out std_logic_vector(15 downto 0)
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_ADDR_IN : in std_logic_vector(15 downto 0);
+ SLV_ACK_OUT : out std_logic;
+ SLV_NO_MORE_DATA_OUT : out std_logic;
+ SLV_UNKNOWN_ADDR_OUT : out std_logic;
+
+ DEBUG_OUT : out std_logic_vector(15 downto 0)
);
end entity;
signal histogram_fill_o : std_logic;
signal histogram_bin_o : std_logic_vector(6 downto 0);
signal histogram_adc_o : std_logic_vector(11 downto 0);
+ signal histogram_pileup_o : std_logic;
+ signal histogram_ovfl_o : std_logic;
-- Data FIFO Delay
signal data_fifo_delay_o : unsigned(7 downto 0);
histogram_fill_o <= '0';
histogram_bin_o <= (others => '0');
histogram_adc_o <= (others => '0');
+ histogram_pileup_o <= '0';
+ histogram_ovfl_o <= '0';
-----------------------------------------------------------------------
-- Calculate Thresholds and values for FIFO Delay
-- Fill Histogram
histogram_fill_o <= '1';
histogram_bin_o <= CHANNEL_IN;
- histogram_adc_o <= ADC_DATA_IN;
+ histogram_adc_o <= ADC_DATA_IN;
+ histogram_pileup_o <= TIMESTAMP_STATUS_IN(1);
+ histogram_ovfl_o <= TIMESTAMP_STATUS_IN(0);
+
end if;
end if;
end if;
data_clk_o <= d_data_clk_o or t_data_clk_o;
data_o <= d_data_o or t_data_o;
- TRIGGER_BUSY_OUT <= trigger_busy_o;
- DATA_OUT <= data_o or t_data_o;
- DATA_CLK_OUT <= data_clk_o;
- NOMORE_DATA_OUT <= nomore_data_o;
- DATA_FIFO_DELAY_OUT <= std_logic_vector(data_fifo_delay_o);
- EVT_BUFFER_CLEAR_OUT <= evt_buffer_clear_o;
+ TRIGGER_BUSY_OUT <= trigger_busy_o;
+ DATA_OUT <= data_o or t_data_o;
+ DATA_CLK_OUT <= data_clk_o;
+ NOMORE_DATA_OUT <= nomore_data_o;
+ DATA_FIFO_DELAY_OUT <= std_logic_vector(data_fifo_delay_o);
+ EVT_BUFFER_CLEAR_OUT <= evt_buffer_clear_o;
- HISTOGRAM_FILL_OUT <= histogram_fill_o;
- HISTOGRAM_BIN_OUT <= histogram_bin_o;
- HISTOGRAM_ADC_OUT <= histogram_adc_o;
+ HISTOGRAM_FILL_OUT <= histogram_fill_o;
+ HISTOGRAM_BIN_OUT <= histogram_bin_o;
+ HISTOGRAM_ADC_OUT <= histogram_adc_o;
+ HISTOGRAM_PILEUP_OUT <= histogram_pileup_o;
+ HISTOGRAM_OVERFLOW_OUT <= histogram_ovfl_o;
-- Slave
- SLV_DATA_OUT <= slv_data_out_o;
- SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o;
- SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;
- SLV_ACK_OUT <= slv_ack_o;
+ SLV_DATA_OUT <= slv_data_out_o;
+ SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o;
+ SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;
+ SLV_ACK_OUT <= slv_ack_o;
end Behavioral;
BOARD_ID : std_logic_vector(15 downto 0)
);
port (
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
- DATA_CLK_IN : in std_logic;
- TIMESTAMP_IN : in std_logic_vector(13 downto 0);
- CHANNEL_IN : in std_logic_vector(6 downto 0);
- TIMESTAMP_STATUS_IN : in std_logic_vector(2 downto 0);
- ADC_DATA_IN : in std_logic_vector(11 downto 0);
- NX_TOKEN_RETURN_IN : in std_logic;
- NX_NOMORE_DATA_IN : in std_logic;
- TRIGGER_IN : in std_logic;
- TRIGGER_BUSY_IN : in std_logic;
- FAST_CLEAR_IN : in std_logic;
- TRIGGER_BUSY_OUT : out std_logic;
- TIMESTAMP_FPGA_IN : in unsigned(11 downto 0);
- DATA_FIFO_DELAY_OUT : out std_logic_vector(7 downto 0);
- DATA_OUT : out std_logic_vector(31 downto 0);
- DATA_CLK_OUT : out std_logic;
- NOMORE_DATA_OUT : out std_logic;
- EVT_BUFFER_CLEAR_OUT : out std_logic;
- EVT_BUFFER_FULL_IN : in std_logic;
- HISTOGRAM_FILL_OUT : out std_logic;
- HISTOGRAM_BIN_OUT : out std_logic_vector(6 downto 0);
- HISTOGRAM_ADC_OUT : out std_logic_vector(11 downto 0);
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_ADDR_IN : in std_logic_vector(15 downto 0);
- SLV_ACK_OUT : out std_logic;
- SLV_NO_MORE_DATA_OUT : out std_logic;
- SLV_UNKNOWN_ADDR_OUT : out std_logic;
- DEBUG_OUT : out std_logic_vector(15 downto 0)
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ DATA_CLK_IN : in std_logic;
+ TIMESTAMP_IN : in std_logic_vector(13 downto 0);
+ CHANNEL_IN : in std_logic_vector(6 downto 0);
+ TIMESTAMP_STATUS_IN : in std_logic_vector(2 downto 0);
+ ADC_DATA_IN : in std_logic_vector(11 downto 0);
+ NX_TOKEN_RETURN_IN : in std_logic;
+ NX_NOMORE_DATA_IN : in std_logic;
+ TRIGGER_IN : in std_logic;
+ TRIGGER_BUSY_IN : in std_logic;
+ FAST_CLEAR_IN : in std_logic;
+ TRIGGER_BUSY_OUT : out std_logic;
+ TIMESTAMP_FPGA_IN : in unsigned(11 downto 0);
+ DATA_FIFO_DELAY_OUT : out std_logic_vector(7 downto 0);
+ DATA_OUT : out std_logic_vector(31 downto 0);
+ DATA_CLK_OUT : out std_logic;
+ NOMORE_DATA_OUT : out std_logic;
+ EVT_BUFFER_CLEAR_OUT : out std_logic;
+ EVT_BUFFER_FULL_IN : in std_logic;
+ HISTOGRAM_FILL_OUT : out std_logic;
+ HISTOGRAM_BIN_OUT : out std_logic_vector(6 downto 0);
+ HISTOGRAM_ADC_OUT : out std_logic_vector(11 downto 0);
+ HISTOGRAM_PILEUP_OUT : out std_logic;
+ HISTOGRAM_OVERFLOW_OUT : out std_logic;
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_ADDR_IN : in std_logic_vector(15 downto 0);
+ SLV_ACK_OUT : out std_logic;
+ SLV_NO_MORE_DATA_OUT : out std_logic;
+ SLV_UNKNOWN_ADDR_OUT : out std_logic;
+ DEBUG_OUT : out std_logic_vector(15 downto 0)
);
end component;
port (
CLK_IN : in std_logic;
RESET_IN : in std_logic;
+ NUM_AVERAGES_IN : in unsigned(2 downto 0);
+ AVERAGE_ENABLE_IN : in std_logic;
CHANNEL_ID_IN : in std_logic_vector(BUS_WIDTH - 1 downto 0);
CHANNEL_DATA_IN : in std_logic_vector(DATA_WIDTH - 1 downto 0);
CHANNEL_ADD_IN : in std_logic;
CLK_IN : in std_logic;
RESET_IN : in std_logic;
RESET_HISTS_IN : in std_logic;
- CHANNEL_STAT_FILL_IN : in std_logic;
+ CHANNEL_FILL_IN : in std_logic;
CHANNEL_ID_IN : in std_logic_vector(6 downto 0);
CHANNEL_ADC_IN : in std_logic_vector(11 downto 0);
+ CHANNEL_PILEUP_IN : in std_logic;
+ CHANNEL_OVERFLOW_IN : in std_logic;
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
SLV_DATA_OUT : out std_logic_vector(31 downto 0);
);
end component;
+component ram_dp_128x40
+ port (
+ WrAddress : in std_logic_vector(6 downto 0);
+ RdAddress : in std_logic_vector(6 downto 0);
+ Data : in std_logic_vector(39 downto 0);
+ WE : in std_logic;
+ RdClock : in std_logic;
+ RdClockEn : in std_logic;
+ Reset : in std_logic;
+ WrClock : in std_logic;
+ WrClockEn : in std_logic;
+ Q : out std_logic_vector(39 downto 0)
+ );
+end component;
+
component ram_dp_128x32
port (
WrAddress : in std_logic_vector(6 downto 0);
signal trigger_validate_busy : std_logic;
signal validate_nomore_data : std_logic;
- signal trigger_validate_fill : std_logic;
- signal trigger_validate_bin : std_logic_vector(6 downto 0);
- signal trigger_validate_adc : std_logic_vector(11 downto 0);
+ signal trigger_validate_fill : std_logic;
+ signal trigger_validate_bin : std_logic_vector(6 downto 0);
+ signal trigger_validate_adc : std_logic_vector(11 downto 0);
+ signal trigger_validate_pileup : std_logic;
+ signal trigger_validate_ovfl : std_logic;
-- Event Buffer
signal trigger_evt_busy : std_logic;
7 => 4, -- Trigger Handler
8 => 5, -- Trigger Validate
9 => 9, -- NX Setup
- 10 => 9, -- NX Histograms
+ 10 => 10, -- NX Histograms
11 => 0, -- Debug Handler
12 => 2, -- Data Delay
others => 0
BOARD_ID => BOARD_ID
)
port map (
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
-
- DATA_CLK_IN => data_valid,
- TIMESTAMP_IN => timestamp,
- CHANNEL_IN => timestamp_channel_id,
- TIMESTAMP_STATUS_IN => timestamp_status,
- ADC_DATA_IN => adc_data,
- NX_TOKEN_RETURN_IN => nx_token_return,
- NX_NOMORE_DATA_IN => nx_nomore_data,
-
- TRIGGER_IN => trigger,
- TRIGGER_BUSY_IN => trigger_busy,
- FAST_CLEAR_IN => fast_clear,
- TRIGGER_BUSY_OUT => trigger_validate_busy,
- TIMESTAMP_FPGA_IN => timestamp_hold,
- DATA_FIFO_DELAY_OUT => new_data_fifo_delay,
-
- DATA_OUT => trigger_data,
- DATA_CLK_OUT => trigger_data_clk,
- NOMORE_DATA_OUT => validate_nomore_data,
- EVT_BUFFER_CLEAR_OUT => event_buffer_clear,
- EVT_BUFFER_FULL_IN => evt_buffer_full,
-
- HISTOGRAM_FILL_OUT => trigger_validate_fill,
- HISTOGRAM_BIN_OUT => trigger_validate_bin,
- HISTOGRAM_ADC_OUT => trigger_validate_adc,
-
- SLV_READ_IN => slv_read(8),
- SLV_WRITE_IN => slv_write(8),
- SLV_DATA_OUT => slv_data_rd(8*32+31 downto 8*32),
- SLV_DATA_IN => slv_data_wr(8*32+31 downto 8*32),
- SLV_ADDR_IN => slv_addr(8*16+15 downto 8*16),
- SLV_ACK_OUT => slv_ack(8),
- SLV_NO_MORE_DATA_OUT => slv_no_more_data(8),
- SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(8),
-
- DEBUG_OUT => debug_line(10)
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+
+ DATA_CLK_IN => data_valid,
+ TIMESTAMP_IN => timestamp,
+ CHANNEL_IN => timestamp_channel_id,
+ TIMESTAMP_STATUS_IN => timestamp_status,
+ ADC_DATA_IN => adc_data,
+ NX_TOKEN_RETURN_IN => nx_token_return,
+ NX_NOMORE_DATA_IN => nx_nomore_data,
+
+ TRIGGER_IN => trigger,
+ TRIGGER_BUSY_IN => trigger_busy,
+ FAST_CLEAR_IN => fast_clear,
+ TRIGGER_BUSY_OUT => trigger_validate_busy,
+ TIMESTAMP_FPGA_IN => timestamp_hold,
+ DATA_FIFO_DELAY_OUT => new_data_fifo_delay,
+
+ DATA_OUT => trigger_data,
+ DATA_CLK_OUT => trigger_data_clk,
+ NOMORE_DATA_OUT => validate_nomore_data,
+ EVT_BUFFER_CLEAR_OUT => event_buffer_clear,
+ EVT_BUFFER_FULL_IN => evt_buffer_full,
+
+ HISTOGRAM_FILL_OUT => trigger_validate_fill,
+ HISTOGRAM_BIN_OUT => trigger_validate_bin,
+ HISTOGRAM_ADC_OUT => trigger_validate_adc,
+ HISTOGRAM_PILEUP_OUT => trigger_validate_pileup,
+ HISTOGRAM_OVERFLOW_OUT => trigger_validate_ovfl,
+
+ SLV_READ_IN => slv_read(8),
+ SLV_WRITE_IN => slv_write(8),
+ SLV_DATA_OUT => slv_data_rd(8*32+31 downto 8*32),
+ SLV_DATA_IN => slv_data_wr(8*32+31 downto 8*32),
+ SLV_ADDR_IN => slv_addr(8*16+15 downto 8*16),
+ SLV_ACK_OUT => slv_ack(8),
+ SLV_NO_MORE_DATA_OUT => slv_no_more_data(8),
+ SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(8),
+
+ DEBUG_OUT => debug_line(10)
);
-------------------------------------------------------------------------------
RESET_IN => RESET_IN,
RESET_HISTS_IN => '0',
- CHANNEL_STAT_FILL_IN => trigger_validate_fill,
+ CHANNEL_FILL_IN => trigger_validate_fill,
CHANNEL_ID_IN => trigger_validate_bin,
CHANNEL_ADC_IN => trigger_validate_adc,
+ CHANNEL_PILEUP_IN => trigger_validate_pileup,
+ CHANNEL_OVERFLOW_IN => trigger_validate_ovfl,
SLV_READ_IN => slv_read(10),
SLV_WRITE_IN => slv_write(10),
0x8418 : r EVT_BUFFER_FULL_IN
0x8419 : r Wait for Data time (ns)
0x841a : r Nxyter CVT (ns)
+0x841b : r Minimum validation Time
+0x841c : r Out of Window Counter last Event Low
+0x841d : r Window Hit Counter last Event
+0x841e : r Out of Window Counter last Event High
+0x841f : r Data Rate being written to Event Buffer (Hz)
-- Event Data Buffer
0x8600 : r read FIFO buffer
add_file -vhdl -lib "work" "cores/fifo_ts_32to32_dc.vhd"
add_file -vhdl -lib "work" "cores/fifo_44_data_delay.vhd"
add_file -vhdl -lib "work" "cores/fifo_32_data.vhd"
+add_file -vhdl -lib "work" "cores/ram_dp_128x40.vhd"
add_file -vhdl -lib "work" "cores/ram_dp_128x32.vhd"
add_file -vhdl -lib "work" "cores/ram_fifo_delay_256x44.vhd"
add_file -vhdl -lib "work" "cores/adc_ddr_generic.vhd"
jspc29 / trb3.git / commitdiff