-In the data stream of the DAQ system, the TDC data starts with the TDC network header "0xXXXXc0XX", "0xc0XX" indicating the address of the TDC in the system. The bits 4\textendash7 indicates the number of the TRB3 board in the system starting from 0 (This must be set up in the \textit{addresses\_trb3.db} file). The least significant 4 bits indicate the TDC number on the TRB3 board. It can alter between 1\textendash4. The number of words sent by the TDC is marked in the upper 16 bits, e.g., "0x0006c0XX" means, the next 6 words are from the TDC with the address XX. After the TDC header, the data is sent. 4 different kinds of words are sent by the TDCs; header, time data, debug and reserved.
+In the data stream of the DAQ system, the TDC data starts with the TDC network
+header, for example "0xXXXXc0XX", "0xc0XX" indicating the address of the TDC
+in the system. The bits 4\textendash7 indicates the number of the TRB3 board
+in the system starting from 0 (This must be set up in the
+\textit{addresses\_trb3.db} file). The least significant 4 bits indicate the
+TDC number on the TRB3 board. It can alter between 1\textendash4. The number
+of words sent by the TDC is marked in the upper 16 bits, e.g., "0x0006c0XX"
+means, the next 6 words are from the TDC with the address XX. After the TDC
+header, the data is sent. 4 different kinds of words are sent by the TDCs;
+header, time data, debug and reserved.
\subsubsection{TDC HEADER}
error bits \> 16 bits \> Error might occur will be marked here \\
\end{tabbing}
-Any word starting with the bits "001" indicates a header word from the TDC in the system. The TDC is defined with the previous word in the data stream \textendash\ TDC network header, e.g., "0xXXXXc023": 3rd TDC of the 2nd TRB3 board in the system.
+Any word starting with the bits "001" indicates a header word from the TDC in
+the system. The TDC is defined with the previous word in the data stream
+\textendash\ TDC network header.
-The trigger random code \textendash\ 8 bits \textendash\ is generated by the trbnet for each trigger in order to distinguish the trigger. It is repeated in the TDC HEADER, so data \& trigger matching can be tested.
+The trigger random code \textendash\ 8 bits \textendash\ is generated by the
+trbnet for each trigger in order to distinguish the trigger. It is repeated in
+the TDC HEADER, so data \& trigger matching can be tested.
-The error bits are used to indicate any error might occurred in the TDC since the last trigger. The error bits coded in the header is given in Table \ref{tab:tdcHeaderErrorBits}.
+The error bits are used to indicate any error might occurred in the TDC since
+the last trigger. The error bits coded in the header is given in Table
+\ref{tab:tdcHeaderErrorBits}.
\begin{table}[ht]
\centering
coarse time \> 11 bits \> The coarse time value of the measurement – 5~ns granularity\\
\end{tabbing}
-Any word starting with the bit "1" indicates a time data word from the TDC in the system.
+Any word starting with the bit "1" indicates a time data word from the TDC in
+the system.
-7 bits are reserved for indicating the channel number in the TDC (max. 63). The first channel \textendash\ channel "000000" \textendash\ is used to measure the reference time. All TDCs in the system measure the same reference time in this channel, so that they can be all synchronised.
+7 bits are reserved for indicating the channel number in the TDC. The first
+channel \textendash\ channel "0000000" \textendash\ is used to measure the
+reference time. All TDCs in the system measure the same reference time in this
+channel, so that they can be all synchronised.
+
+Three time informations are generated for each event detected by each
+channel; epoch wocounter, coarse counter and fine counter. The epoch counter
+word is explained in \ref{sec:tdcEpoch}. The coarse time information has the
+granularity of 5~ns (period of the system clock). The range of the coarse time
+is 10,24~us. The fine time has the range of 5~ns but doesn't have a fixed
+granularity. The fine time information has to be calibrated using the
+statistic collected by the individual channel (for details see
+\ref{sec:tdcFineTime}).
-Two time informations are generated for each event detected by each channel. The coarse time information has the granularity of 5~ns (period of the system clock). The range of the coarse time is 10,24~us. The fine time has the range of 5~ns but doesn't have a fixed granularity. The fine time information has to be calibrated using the statistic collected by the individual channel (for details see \ref{sec:tdcFineTime}).
\subsubsection{DEBUG}
\label{sec:tdcDebug}
The debug mode can be enabled via slow control register bit:
\begin{verbatim}
- 0xc0 - bit 4
+ 0xc800 - bit 4
\end{verbatim}
-The data format of the \textbf{\textit{debug}} word is shown in Table~\ref{tab:tdcDebugWord}:
+The data format of the \textbf{\textit{debug}} word is shown in
+Table~\ref{tab:tdcDebugWord}:
\begin{table}[h]
\centering
\end{center}
\end{table}
-The debug words sent with DAQ can be accessed also via slow control registers (see Table \ref{tab:tdcStatusReg1} and Table \ref{tab:tdcStatusReg2}).
+The debug words sent with DAQ can be accessed also via slow control registers
+(see Table \ref{tab:tdcStatusReg1} and Table \ref{tab:tdcStatusReg2}).
\newpage
\subsubsection{EPOCH Counter}
-As the global coarse counter has the time limit of $\sim$10~us, an overflow counter (EPOCH counter) is implemented in order to increase the measurement range. The data format of the \textbf{\textit{EPOCH Counter}} word is shown below:
+\label{sec:tdcEpoch}
+As the global coarse counter has the time limit of $\sim$10~us, an overflow
+counter (EPOCH counter) is implemented in order to increase the measurement
+range. The data format of the \textbf{\textit{EPOCH Counter}} word is shown
+below:
\begin{table}[h]
\centering
\label{tab:tdcEpochCounte}
\end{table}
-The EPOCH counter is designed with 28 bits increasing the total measurement range up to $\sim$45,8~min. For each channel an individual EPOCH counter is implemented and they are incremented, when the coarse counter wraps around. The value of the EPOCH counter is kept in a register before it is written in the channel memory. It is only written in the memory, if a time measurement takes place after the last increment of the EPOCH counter. The EPOCH counter word is written in the memory only once per channel for each increment, thus saving bandwidth. In order to be on the safe side and not overflow the EPOCH counter, the readout trigger frequency can be set minimum to 24~Hz.
+The EPOCH counter is designed with 28 bits increasing the total measurement
+range up to $\sim$45,8~min. For each channel an individual EPOCH counter is
+implemented and they are incremented, when the coarse counter wraps
+around. The value of the EPOCH counter is kept in a register before it is
+written in the channel memory. It is only written in the memory, if a time
+measurement takes place after the last increment of the EPOCH counter. The
+EPOCH counter word is written in the memory only once per channel for each
+increment, thus saving bandwidth. In order to be on the safe side and not
+overflow the EPOCH counter, the readout trigger frequency can be set minimum
+to 24~Hz.
\subsubsection{RESERVED}
-\subsubsection{Trigger Window}
+\subsubsection{Trigger Window and Trigger Mode}
\label{sec:tdcTrigWin}
-In order to reduce the data load on the DAQ a feature called trigger window is implemented. With this feature the user can define the interested time interval and filter the hits occurred in this time interval. An illustration of the trigger window feature is shown in Figure \ref{fig:tdcTrigWin}. The trigger window is relative to the rising edge of the reference time at the \textit{TRIGGER\_INP1} (see Figure \ref{fig:trb3}) with the granularity of 5~ns. The \textit{Pre-Trigger Window} and \textit{Post-Trigger Window} widths can be set via slow control (Table \ref{tab:tdcControlReg}).
+In order to reduce the data load on the DAQ a feature called trigger window is
+implemented. With this feature the user can define the interested time
+interval and filter the hits occurred in this time interval. An illustration
+of the trigger window feature is shown in Figure \ref{fig:tdcTrigWin}. The
+trigger window is relative to the rising edge of the reference time at the
+\textit{TRIGGER\_INP1} (see Figure \ref{fig:trb3}) with the granularity of
+5~ns. The \textit{Pre-Trigger Window} and \textit{Post-Trigger Window} widths
+can be set via slow control (Table \ref{tab:tdcControlReg}).
\begin{figure}[htp]
\centering
\includegraphics[width=0.8\textwidth]{figures/tdcTrigWinWF.png}
\caption{An illustration of trigger window relative to the reference time.}
\label{fig:tdcTrigWin}
-\end{figure}
\ No newline at end of file
+\end{figure}
+
+Trigger mode is controled by register 0xc800 bit 12. If it is set to triggered
+mode ('1'), the epoch and coarse counters are reset after each trigger
+window. If this bit is set to triggerless mode ('0'), the epoch and coarse
+counters are never reset, unless there is a system wide reset. They will run
+until they have an overflow.
-A set of control registers are assigned in order to access the basic controls, edit the features and debug information of the TDC. A detailed explanation of the control registers are given in Table \ref{tab:tdcControlReg}.
+A set of control registers are assigned in order to access the basic controls,
+edit the features and debug information of the TDC. A detailed explanation of
+the control registers are given in Table \ref{tab:tdcControlReg}.
\begin{table}[htbp]
\begin{center}
\multirow{13}{*}{0xc800} & \multirow{13}{*}{Basic controls} & 3-0 & Enables different signals to the HPLA* output for debugging with logic analyser (For more details see Table \ref{tab:tdcControlRegBasicLA}).\\
& & 4 & Enables the \textit{Debug Mode}. Different statistics and debug words are sent after every trigger (see \ref{sec:tdcDebug}).\\
& & 7-5 & reserved.\\
- & & 8 & Resets the internal counters.\\
+ & & 8 & Resets the internal counters (active high).\\
& & 11-9 & reserved.\\
& & 12 & Used to select the trigger mode. 0 - with trigger mode; 1 - trigger-less mode (For more details see \ref{sec:tdcTrigWin}).\\
& & 31-13 & reserved.\\
\hline
0xc803 & Channel enable 2 & 31-0 & Enable signals for the channels 33-64.\\
\hline
- \multirow{3}{*}{0xc804} & \multirow{3}{*}{Channel hit scaler control} & 7-0 & Defines the channel number of the scaler register (Status register 0xc111).\\
- & & 31-8 & reserved.\\
- \hline
+% \multirow{3}{*}{0xc804} & \multirow{3}{*}{Channel hit scaler control} & 7-0 & Defines the channel number of the scaler register (Status register 0xc111).\\
+% & & 31-8 & reserved.\\
+% \hline
\end{tabularx}
\caption{The control registers of the TDC. Note that these registers
have been moved from 0xc0\ldots0xc4 at the beginning of 2013.}
\end{center}
\end{table}
-The status registers of the TDC are explained in Table \ref{tab:tdcStatusReg1} and Table \ref{tab:tdcStatusReg2}.
+The status registers of the TDC are explained in Table \ref{tab:tdcStatusReg1}
+and Table \ref{tab:tdcStatusReg2}.
\newpage
\subsubsection{Hit Scaler Registers}
-In order to automatise the threshold level settings the number of hits detected by each channel can be reached via slow control as well as the current LVDS input level state. The bit mask for these registers is x"c0". The very least 8~bits are used for the channel number, e.g. \verb|trbcmd r 0xc001| would give the hits detected by channel 1. In the same register the MSB shows the logic level of the output of the input LVDS buffers. This bit is useful for the designs, which use the LVDS buffers as discriminators, e.g. cbmrich and padiwa projects. The data format of the register is shown below:
+In order to automatise the threshold level settings the number of hits
+detected by each channel can be reached via slow control as well as the
+current LVDS input level state. These register can be read from the bus
+address x"c0xx". The very least 8~bits are used for the channel number,
+e.g. \verb|trbcmd r 0xc001| would give the hits detected by channel 1. In the
+same register the MSB shows the logic level of the output of the input LVDS
+buffers. This bit is useful for the designs, which use the LVDS buffers as
+discriminators, e.g. cbmrich and padiwa projects. The data format of the
+register is shown below:
+
\begin{table}[ht]
\centering
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