still testing

diff --git a/media_interfaces/sync/rx_control.vhd b/media_interfaces/sync/rx_control.vhd
index 1881bb1b1c14936d48b35ebaeecd72052cf3856d..1898854e87810cc09f90dfd36bbf51f1b8be58a5 100644 (file)
--- a/media_interfaces/sync/rx_control.vhd
+++ b/media_interfaces/sync/rx_control.vhd
@@ -95,14 +95,18 @@ signal got_pulse_bad       : std_logic := '0';
 signal pulse_good_100      : std_logic;
 signal pulse_bad_100       : std_logic;
 signal waiting_for_retr    : std_logic := '0';
-signal good_pos_counter    : unsigned(7 downto 0) := (others => '0');
+signal good_pos_counter    : std_logic_vector(7 downto 0) := (others => '0');
 signal num_pakets          : unsigned(3 downto 0) := (others => '0');
 
 signal use_crc             : std_logic := '0';
 signal load_use_crc        : std_logic := '0';
+signal disable_crc         : std_logic := '0';
 
 signal num_crc          : unsigned(3 downto 0) := (others => '0');
-signal num_pak          : unsigned(3 downto 0) := (others => '0');
+signal num_pak          : unsigned(7 downto 0) := (others => '0');
+signal resub_mode : std_logic := '0';
+signal last_good_pos_counter    : std_logic_vector(7 downto 0) := (others => '0');
+signal last_send_link_reset_i  : std_logic;
 
 
 begin
@@ -127,15 +131,22 @@ last_ct_fifo_empty <= ct_fifo_empty when rising_edge(CLK_100);
 
 process begin
   wait until rising_edge(CLK_100);
+  
   if pulse_good_100 = '1' then
     got_pulse_good <= '1';
-    good_pos_counter <= good_pos_counter+5;
-  elsif ct_fifo_empty = '1' then
-    got_pulse_good <= '0';
-    if load_use_crc = '1' then
-      use_crc <= '1';
-    else
-      use_crc <= '0';
+    good_pos_counter <= std_logic_vector(unsigned(good_pos_counter)+5);
+  else
+    if buf_rx_write_out = '1' and use_crc = '0' then
+      --fake pointer increase
+      good_pos_counter <= std_logic_vector(unsigned(good_pos_counter)+1);
+    end if;
+    if ct_fifo_empty = '1' then
+      got_pulse_good <= '0';
+      if load_use_crc = '1' then
+        use_crc <= '1';
+      else
+        use_crc <= '0';
+      end if;
     end if;
   end if;
   if pulse_bad_100 = '1' then
@@ -143,22 +154,35 @@ process begin
     got_pulse_good <= '0';
   elsif ct_fifo_empty = '1' then
     got_pulse_bad <= '0';
-  end if;  
+  end if;
+
   if RX_ALLOW_IN = '0' then
     rx_packet_num <= "100";
-    good_pos_counter <= (others => '0');
+    --good_pos_counter <= (others => '0');
   elsif buf_rx_write_out = '1' then
     if rx_packet_num = "100" then
       rx_packet_num <= "000";
+      --if use_crc = '0' then
+        --good_pos_counter <= std_logic_vector(unsigned(good_pos_counter)+5);
+      --end if;
     else
       rx_packet_num <= std_logic_vector(unsigned(rx_packet_num)+1);
     end if;  
   end if;
-  if send_link_reset_i = '1' then
+
+  if send_link_reset_i = '1' --and last_send_link_reset_i = '0'
+                             --and last_good_pos_counter /= x"00"
+                             then
+    if last_good_pos_counter /= x"00" then
+      num_pak(7 downto 0) <= last_good_pos_counter;
+    end if;
     good_pos_counter <= (others => '0');
   end if;
 end process;
 
+last_good_pos_counter <= good_pos_counter when rising_edge(CLK_100) and resub_mode = '1';
+last_send_link_reset_i <= send_link_reset_i when rising_edge(CLK_100);
+
 ----------------------------------------------------------------------
 -- Clock Domain Transfer
 ----------------------------------------------------------------------
@@ -266,6 +290,9 @@ PROC_RX_FSM : process begin
       rx_state_bits         <= x"4";
       crc_en                <= '1';
       if reg_rx_k_in = '0' then
+        --if resub_mode = '1' then
+          --num_pak <= num_pak+1;
+        --end if;
         next_sop            <= '0';
         rx_data(15 downto 8)<= reg_rx_data_in;
         rx_data(16)         <= next_sop;
@@ -283,17 +310,20 @@ PROC_RX_FSM : process begin
         load_use_crc <= '1';
         pulse_good   <= '1';
       else  
-        if (crc_q = reg_rx_data_in and waiting_for_retr = '0') --- and num_pakets = 5)
-                                                               and force_crc_error = '0' then -- CRC match
+        if ((crc_q = reg_rx_data_in and waiting_for_retr = '0') --- and num_pakets = 5)
+                                                               and force_crc_error = '0') or disable_crc = '1' then -- CRC match
           pulse_good       <= '1';
         else
+          if force_crc_error = '1' then
+            disable_crc <= '1';
+          end if;
           --pulse_good       <= '1';
           pulse_bad        <= '1';
           if waiting_for_retr = '0' then
             if crc_q /= reg_rx_data_in then
               num_crc <= num_crc+1;
-            else
-              num_pak <= num_pak+1;
+            --else
+              --num_pak <= num_pak+1;
             end if;
             req_retr_i       <= '1';
             waiting_for_retr <= '1';
@@ -309,6 +339,8 @@ PROC_RX_FSM : process begin
       waiting_for_retr      <= '0';
       crc_reset             <= '1';
       num_pakets <= (others => '0');
+      --num_pak <= (others => '0');
+      resub_mode <= '1';
       num_crc <= num_crc+1; --BUGBUG
       --load_use_crc          <= '0';
       
@@ -330,6 +362,7 @@ PROC_RX_FSM : process begin
       crc_reset             <= '1';
       waiting_for_retr      <= '0';
       num_pakets <= (others => '0');
+      resub_mode <= '0';
       if reg_rx_k_in = '1' and reg_rx_data_in = K_RST then
         send_link_reset_i   <= '1';
         make_reset_i        <= '0';
@@ -413,7 +446,7 @@ PULSE_BAD_SYNC : pulse_sync
 
 
 --REQUEST_POSITION_OUT   <= x"00";  --TODO: check incoming data
-REQUEST_POSITION_OUT   <= std_logic_vector(good_pos_counter);
+REQUEST_POSITION_OUT   <= good_pos_counter;
 
 SEND_LINK_RESET_OUT    <= send_link_reset_i when rising_edge(CLK_200);
 MAKE_RESET_OUT         <= make_reset_i when rising_edge(CLK_200);
@@ -440,16 +473,18 @@ DEBUG_OUT(6)            <= ct_fifo_empty;
 DEBUG_OUT(7)            <= ct_fifo_write;
 DEBUG_OUT(15 downto 8)  <= rx_data(7 downto 0);
 
-DEBUG_OUT(16)           <= reg_rx_k_in;
-DEBUG_OUT(17)           <= make_reset_i;
-DEBUG_OUT(18)           <= send_link_reset_i;
-DEBUG_OUT(19)           <= '1' when rx_state_bits = x"f" else '0';
+--DEBUG_OUT(16)           <= reg_rx_k_in;
+--DEBUG_OUT(17)           <= make_reset_i;
+--DEBUG_OUT(18)           <= send_link_reset_i;
+--DEBUG_OUT(19)           <= '1' when rx_state_bits = x"f" else '0';
+
+--DEBUG_OUT(20)           <= use_crc;
 
-DEBUG_OUT(20)           <= use_crc;
+--DEBUG_OUT(23 downto 21) <= (others => '0');
+--DEBUG_OUT(27 downto 24) <= num_crc;
+DEBUG_OUT(23 downto 16) <= last_good_pos_counter;
+DEBUG_OUT(31 downto 24) <= num_pak;
 
-DEBUG_OUT(23 downto 21) <= (others => '0');
-DEBUG_OUT(27 downto 24) <= num_crc;
-DEBUG_OUT(31 downto 28) <= num_pak;
 
 -- DEBUG_OUT(23 downto 16) <= rx_data(7 downto 0);
 -- DEBUG_OUT(31 downto 24) <= ct_fifo_data_out(7 downto 0);

diff --git a/media_interfaces/sync/tx_control.vhd b/media_interfaces/sync/tx_control.vhd
index 69ed56c6b5cddfc5a68c738abaed69df2817a0bb..e0251a04625ad0fbb16db15d86e3ee553294b98c 100644 (file)
--- a/media_interfaces/sync/tx_control.vhd
+++ b/media_interfaces/sync/tx_control.vhd
@@ -112,6 +112,9 @@ architecture arch of tx_control is
   signal toggle_idle             : std_logic := '0';
 
   signal send_chksum_counter : std_logic_vector(7 downto 0) := x"00";
+
+  signal num_pak          : unsigned(15 downto 0) := (others => '0');
+  signal resub_mode : std_logic := '0';
   
 begin
 
@@ -189,16 +192,21 @@ begin
 --         ram_read_addr <= (others => '0');
 --       els
       if rising_edge(CLK_200) then
-        if tx_allow_qtx = '0' then
+        if tx_allow_qtx = '0' or send_link_reset_qtx = '1'
+        then
+          num_pak(15 downto 8) <= (others => '0');
+            if ram_read_addr /= x"00" then
+              num_pak(7 downto 0) <= ram_read_addr;
+            end if;
           ram_read_addr <= (others => '0');
+          --ram_read_addr2 <= (others => '0');
         elsif load_read_pointer_i = '1' then
-          --BUGBUG
-          ram_read_addr1 <= ram_read_addr;
           ram_read_addr <= unsigned(restart_position_i);
-          ram_read_addr2 <= ram_read_addr;
+          ram_read_addr2 <= unsigned(restart_position_i);
+          ram_read_addr1 <= ram_read_addr;
         elsif ram_read = '1' then
           ram_read_addr <= ram_read_addr + to_unsigned(1,1);
-        end if;
+        end if;          
       end if;
     end process;
 
@@ -209,7 +217,8 @@ begin
 --         ram_write_addr <= (others => '0');
 --       els
       if rising_edge(CLK_200) then
-        if tx_allow_qtx = '0' then
+        if tx_allow_qtx = '0' or send_link_reset_qtx = '1'
+                            then
           ram_write_addr <= (others => '0');
         elsif ram_write = '1' then
           ram_write_addr <= ram_write_addr + to_unsigned(1,1);
@@ -285,6 +294,9 @@ begin
 
           when SEND_DATA_H =>
             TX_DATA_OUT        <= ram_dout(15 downto 8);
+            --if resub_mode = '1' then
+              --num_pak <= num_pak+1;
+            --end if;
 
           when SEND_CHKSUM_L =>
             send_chksum_counter <= std_logic_vector(unsigned(send_chksum_counter) + 1);
@@ -306,6 +318,8 @@ begin
             --TX_DATA_OUT        <= std_logic_vector(ram_read_addr);
             TX_DATA_OUT        <= x"FF";   --
             current_state      <= SEND_DATA_L;   ---
+            --num_pak <= (others => '0');
+            resub_mode <= '1';
 
           when SEND_REQUEST_L =>
             TX_DATA_OUT        <= K_REQ;
@@ -328,6 +342,7 @@ begin
           when SEND_RESET =>
             TX_DATA_OUT        <= K_RST;
             TX_K_OUT           <= '1';
+            resub_mode <= '0';
             if send_link_reset_qtx = '0' then
               current_state    <= SEND_IDLE_L;
             end if;
@@ -540,8 +555,10 @@ begin
 --  DEBUG_OUT(23 downto 16) <= tx_data_200(7 downto 0);
 --  DEBUG_OUT(31 downto 24) <= ram_dout(7 downto 0);
 --  DEBUG_OUT(31 downto 24) <= send_chksum_counter;
-  DEBUG_OUT(23 downto 16) <= ram_read_addr1;
-  DEBUG_OUT(31 downto 24) <= ram_read_addr2;
+
+--  DEBUG_OUT(23 downto 16) <= ram_read_addr1 when rising_edge(CLK_100);
+--  DEBUG_OUT(31 downto 24) <= ram_read_addr2 when rising_edge(CLK_100);
+DEBUG_OUT(31 downto 16) <= num_pak when rising_edge(CLK_100);
     
   process(CLK_100)
     begin