signal trigger_busy_mupix_data_int : std_logic;
-- synced signals from board interface
- signal timestamp_from_mupix_sync : std_logic_vector(7 downto 0);
- signal rowaddr_from_mupix_sync : std_logic_vector(5 downto 0);
- signal coladdr_from_mupix_sync : std_logic_vector(5 downto 0);
- signal priout_from_mupix_sync : std_logic;
+ signal mupixcontrol_i : MupixReadoutCtrl;
+ signal mupixreadout_i : MupixReadoutData;
+ signal mupixreadout_sync_i : MupixReadoutData;
signal sout_c_from_mupix_sync : std_logic;
signal sout_d_from_mupix_sync : std_logic;
signal hbus_from_mupix_sync : std_logic;
signal szintilator_sync : std_logic;
signal mupix_ctrl_i : MupixSlowControl;
+
begin -- Behavioral
STAT_DEBUG => open
);
-
+ mupixreadout_i.priout <= priout_from_mupix;
+ mupixreadout_i.hit_col <= coladdr_from_mupix;
+ mupixreadout_i.hit_row <= rowaddr_from_mupix;
+ mupixreadout_i.hit_time <= timestamp_from_mupix;
+
board_interface_1: entity work.board_interface
port map (
clk_in => clk,
fast_clk_in => fast_clk,
- timestamp_from_mupix => timestamp_from_mupix,
- rowaddr_from_mupix => rowaddr_from_mupix,
- coladdr_from_mupix => coladdr_from_mupix,
- priout_from_mupix => priout_from_mupix,
+ mupixreadout => mupixreadout_i,
sout_c_from_mupix => sout_c_from_mupix,
sout_d_from_mupix => sout_d_from_mupix,
hbus_from_mupix => hbus_from_mupix,
fpga_aux_from_board => fpga_aux_from_board,
- timestamp_from_mupix_sync => timestamp_from_mupix_sync,
- rowaddr_from_mupix_sync => rowaddr_from_mupix_sync,
- coladdr_from_mupix_sync => coladdr_from_mupix_sync,
- priout_from_mupix_sync => priout_from_mupix_sync,
+ mupixreadout_sync => mupixreadout_sync_i,
sout_c_from_mupix_sync => sout_c_from_mupix_sync,
sout_d_from_mupix_sync => sout_d_from_mupix_sync,
hbus_from_mupix_sync => hbus_from_mupix_sync,
SLV_NO_MORE_DATA_OUT => slv_no_more_data(7),
SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(7));
+ ldpix_to_mupix <= mupixcontrol_i.ldpix;
+ ldcol_to_mupix <= mupixcontrol_i.ldcol;
+ rdcol_to_mupix <= mupixcontrol_i.rdcol;
+ pulldown_to_mupix <= mupixcontrol_i.pulldown;
+ timestamp_to_mupix <= mupixcontrol_i.timestamps;
+
--Mupix 3 Chip Interface
mupix_interface_1 : mupix_interface
port map (
rst => Reset,
clk => clk,
- ldpix => ldpix_to_mupix,
- ldcol => ldcol_to_mupix,
- rdcol => rdcol_to_mupix,
- pulldown => pulldown_to_mupix,
- timestamps => timestamp_to_mupix,
- priout => priout_from_mupix_sync,
- hit_col => coladdr_from_mupix_sync,
- hit_row => rowaddr_from_mupix_sync,
- hit_time => timestamp_from_mupix_sync,
+ mupixcontrol => mupixcontrol_i,
+ mupixreadout => mupixreadout_sync_i,
memdata => memdata,
memwren => memwren,
trigger_ext => valid_trigger_int,
use ieee.std_logic_1164.all;
use work.mupix_components.all;
+use work.StdTypes.all;
entity board_interface is
port(
clk_in : in std_logic;
fast_clk_in : in std_logic;
-- signals from mupix
- timestamp_from_mupix : in std_logic_vector(7 downto 0);
- rowaddr_from_mupix : in std_logic_vector(5 downto 0);
- coladdr_from_mupix : in std_logic_vector(5 downto 0);
- priout_from_mupix : in std_logic;
+ mupixreadout : in MupixReadoutData;
sout_c_from_mupix : in std_logic;
sout_d_from_mupix : in std_logic;
hbus_from_mupix : in std_logic;
fpga_aux_from_board : in std_logic_vector(5 downto 0);
--synced (and inverted) signals
- timestamp_from_mupix_sync : out std_logic_vector(7 downto 0);
- rowaddr_from_mupix_sync : out std_logic_vector(5 downto 0);
- coladdr_from_mupix_sync : out std_logic_vector(5 downto 0);
- priout_from_mupix_sync : out std_logic;
+ mupixreadout_sync : out MupixReadoutData;
sout_c_from_mupix_sync : out std_logic;
sout_d_from_mupix_sync : out std_logic;
hbus_from_mupix_sync : out std_logic;
wait until rising_edge(clk_in);
fpga_aux_from_board_sync <= fpga_aux_from_board;
if invert_signals_int = '1' then
- timestamp_from_mupix_sync <= not timestamp_from_mupix;
- rowaddr_from_mupix_sync <= not rowaddr_from_mupix;
- coladdr_from_mupix_sync <= not coladdr_from_mupix;
- sout_c_from_mupix_sync <= not sout_c_from_mupix;
- sout_d_from_mupix_sync <= not sout_d_from_mupix;
- priout_from_mupix_sync <= priout_from_mupix; --is inverted on the chip
+ mupixreadout_sync.hit_time <= not mupixreadout.hit_time;
+ mupixreadout_sync.hit_row <= not mupixreadout.hit_row;
+ mupixreadout_sync.hit_col <= not mupixreadout.hit_col;
+ mupixreadout_sync.priout <= mupixreadout.priout; --is inverted on the chip
+ sout_c_from_mupix_sync <= not sout_c_from_mupix;
+ sout_d_from_mupix_sync <= not sout_d_from_mupix;
else
- timestamp_from_mupix_sync <= timestamp_from_mupix;
- rowaddr_from_mupix_sync <= rowaddr_from_mupix;
- coladdr_from_mupix_sync <= coladdr_from_mupix;
- sout_c_from_mupix_sync <= sout_c_from_mupix;
- sout_d_from_mupix_sync <= sout_d_from_mupix;
- priout_from_mupix_sync <= not priout_from_mupix; --is inverted on the chip
+ mupixreadout_sync.hit_time <= mupixreadout.hit_time;
+ mupixreadout_sync.hit_row <= mupixreadout.hit_row;
+ mupixreadout_sync.hit_col <= mupixreadout.hit_col;
+ mupixreadout_sync.priout <= not mupixreadout.priout; --is inverted on the chip
+ sout_c_from_mupix_sync <= sout_c_from_mupix;
+ sout_d_from_mupix_sync <= sout_d_from_mupix;
end if;
end process;
use ieee.numeric_std.all;
use work.mupix_components.all;
+use work.StdTypes.all;
+
entity mupix_interface is
port (
rst : in std_logic;
clk : in std_logic;
-- MUPIX IF
- ldpix : out std_logic;
- ldcol : out std_logic;
- rdcol : out std_logic;
- pulldown : out std_logic;
- timestamps : out std_logic_vector(7 downto 0);
- priout : in std_logic;
- hit_col : in std_logic_vector(5 downto 0);
- hit_row : in std_logic_vector(5 downto 0);
- hit_time : in std_logic_vector(7 downto 0);
-
+ mupixcontrol : out MupixReadoutCtrl;
+ mupixreadout : in MupixReadoutData;
+
-- MEMORY IF
memdata : out std_logic_vector(31 downto 0);
memwren : out std_logic;
process(rst, clk)
begin
- if(clk'event and clk = '1') then
+ if rising_edge(clk) then
if(rst = '1') then
triggering <= '0';
continousread <= '0';
endofevent <= '0';
else
testoutro <= (others => '0');
- testoutro(31) <= priout;
+ testoutro(31) <= mupixreadout.priout;
memwren <= '0';
memdata <= (others => '0');
endofevent <= '0';
rd_col_reg <= '0';
case state is
when pause =>
- pausecounter <= pausecounter +1;
+ pausecounter <= pausecounter + 1;
if(std_logic_vector(pausecounter) = pauseregister) then
state <= waiting;
pausecounter <= (others => '0');
delcounter <= delcounter - 1;
state <= loadcol;
if(delcounter = "00000000") then
- if priout = '1' then
+ if mupixreadout.priout = '1' then
state <= readcol;
rd_col_reg <= '1';
delcounter <= unsigned(delaycounters1(31 downto 24));
end if;
--sample priout
if (std_logic_vector(delcounter) = delaycounters2(23 downto 16)) then
- priout_reg <= priout;
+ priout_reg <= mupixreadout.priout;
end if;
--write hit information
if(std_logic_vector(delcounter) = delaycounters2(31 downto 24)) then
- memdata <= x"F0F" & hit_col & hit_row & hit_time;
+ memdata <= x"F0F" & mupixreadout.hit_col & mupixreadout.hit_row & mupixreadout.hit_time;
memwren <= '1';
- if(ignorehitflag = '1' and (hit_col = "000000" and hit_row = "000000")) then
- memwren <= '0';
- end if;
hitcounter <= hitcounter + 1;
state <= readcol;
elsif(delcounter = "00000000") then
endofevent <= '1';
state <= pause;
else
- if (priout = '1' or (delaycounters2(23 downto 16) /= "00000000" and priout_reg = '1')) then
+ if ( mupixreadout.priout = '1' or (delaycounters2(23 downto 16) /= "00000000" and priout_reg = '1')) then
state <= readcol;
rd_col_reg <= '1';
delcounter <= unsigned(delaycounters1(31 downto 24));
process(rst, clk)
begin
if(rst = '1') then
- timestamps <= (others => '0');
+ mupixcontrol.timestamps <= (others => '0');
elsif(clk'event and clk = '1') then
if(timestampcontrolbits(8) = '1') then
- timestamps <= graycount;
+ mupixcontrol.timestamps <= graycount;
else
- timestamps <= timestampcontrolbits(7 downto 0);
+ mupixcontrol.timestamps <= timestampcontrolbits(7 downto 0);
end if;
end if;
end process;
ro_busy <= ro_busy_int;
- ldpix <= ld_pix_reg;
- pulldown <= pulldown_reg;
- ldcol <= ld_col_reg;
- rdcol <= rd_col_reg;
+ mupixcontrol.ldpix <= ld_pix_reg;
+ mupixcontrol.pulldown <= pulldown_reg;
+ mupixcontrol.ldcol <= ld_col_reg;
+ mupixcontrol.rdcol <= rd_col_reg;
end RTL;
port (
rst : in std_logic;
clk : in std_logic;
- ldpix : out std_logic;
- ldcol : out std_logic;
- rdcol : out std_logic;
- pulldown : out std_logic;
- timestamps : out std_logic_vector(7 downto 0);
- priout : in std_logic;
- hit_col : in std_logic_vector(5 downto 0);
- hit_row : in std_logic_vector(5 downto 0);
- hit_time : in std_logic_vector(7 downto 0);
+ mupixcontrol : out MupixReadoutCtrl;
+ mupixreadout : in MupixReadoutData;
memdata : out std_logic_vector(31 downto 0);
memwren : out std_logic;
endofevent : out std_logic;
port (
clk_in : in std_logic;
fast_clk_in : in std_logic;
- timestamp_from_mupix : in std_logic_vector(7 downto 0);
- rowaddr_from_mupix : in std_logic_vector(5 downto 0);
- coladdr_from_mupix : in std_logic_vector(5 downto 0);
- priout_from_mupix : in std_logic;
+ mupixreadout : in MupixReadoutData;
sout_c_from_mupix : in std_logic;
sout_d_from_mupix : in std_logic;
hbus_from_mupix : in std_logic;
fpga_aux_from_board : in std_logic_vector(5 downto 0);
- timestamp_from_mupix_sync : out std_logic_vector(7 downto 0);
- rowaddr_from_mupix_sync : out std_logic_vector(5 downto 0);
- coladdr_from_mupix_sync : out std_logic_vector(5 downto 0);
- priout_from_mupix_sync : out std_logic;
+ mupixreadout_sync : out MupixReadoutData;
sout_c_from_mupix_sync : out std_logic;
sout_d_from_mupix_sync : out std_logic;
hbus_form_mupix_sync : out std_logic;
jspc29 / trb3.git / commitdiff