my $n = $q->param('n') || 10;
my $delay = $q->param('delay') || 5 ; #ms
my $verbose = $q->param('verbose') || 0;
+my $unit = $q->param('unit') || 0;
print header('text/plain') if $isHttpReq;
print_usage() unless ( defined($channel) && defined($chip) && defined($FPGA));
my $self = $xmldb->channelParm($chip,$channel);
+
+if ($unit) {
+ print $self->{unit};
+ exit;
+}
+
+
$self->{FPGA} = any2dec($FPGA);
trb_init_ports() or die trb_strerror();
sub getVal{
my $read = trb_register_read($self->{FPGA},$self->{address});
- my $value = ($read->{$self->{FPGA}} & 0xFFFF ) * $self->{scale};
+ my $value = ($read->{$self->{FPGA}} & 0xFFFF ) * $self->{scale} + $self->{scaleoffset};
return $value;
}
# read min and max
my $read = trb_register_read($self->{FPGA},$self->{address}+0x30);
my $minmax = ($read->{$self->{FPGA}} ) ;
- my $min = ($minmax & 0x0000FFFF) * $self->{scale}; # lower 16 bit
- my $max = ($minmax >> 16 ) * $self->{scale}; # upper 16 bit
+ my $min = ($minmax & 0x0000FFFF) * $self->{scale} + $self->{scaleoffset}; # lower 16 bit
+ my $max = ($minmax >> 16 ) * $self->{scale} + $self->{scaleoffset}; # upper 16 bit
return ($min, $max);
}
if left out, will use DAQOPSERVER ENV variable
verbose = <0|1> if verbose=1 then script will print all sampled values
as well as the channel unit and other debug data
+ unit = <0|1> if unit=1 then only the selected channel unit is
+ printed
available ADC channels:
Options:
-h, --help brief help message
-v, --verbose detailed debugging info about ongoing actions
- -c, --config specifies the input config xml file
+ -c, --config specifies the input config xml file
+ (including path if necessary!)
=back
# sample random number for debug
# HPlot::PlotAdd($self->{requestString},rand());
my $read = trb_register_read($self->{FPGA},$self->{address});
- my $value = ($read->{$self->{FPGA}} & 0xFFFF ) * $self->{scale};
+ my $value = ($read->{$self->{FPGA}} & 0xFFFF ) * $self->{scale} + $self->{scaleoffset};
# read min and max
my $read = trb_register_read($self->{FPGA},$self->{address}+0x30);
my $minmax = ($read->{$self->{FPGA}} ) ;
- my $min = ($minmax & 0x0000FFFF) * $self->{scale}; # lower 16 bit
- my $max = ($minmax >> 16 ) * $self->{scale}; # upper 16 bit
+ my $min = ($minmax & 0x0000FFFF) * $self->{scale} + $self->{scaleoffset}; # lower 16 bit
+ my $max = ($minmax >> 16 ) * $self->{scale} + $self->{scaleoffset}; # upper 16 bit
# print $value."\n" if $myverbose;
HPlot::PlotAdd($self->{requestString},$value,0);
HPlot::PlotAdd($self->{requestString},$min,1);
my $xmlfile = $configFile;
my $newValue;
$newValue = $_[2];
- my $base = $_[3];
+ my $base = $_[3] || "";
my $xmltree = $configTree;