precision of the TDC is increased with the Wave Union Launcher method. In\r
order to overcome the minimum pulse width limitation a semi-asynchronous pulse\r
stretcher is implemented which has been verified to allow a measurement of a\r
-pulse width $<500~ps$. The TDC has the typical precision of $7.2~ps$ RMS\r
-($14~ps$ RMS on the worst channel) on a single channel. Also the 264 Channel\r
-TDC Platform - TDC Readout Board, TRB3 - applying the described TDC is\r
-presented in the paper.\r
+pulse width $<500~ps$. The TDC has a typical precision of $7.2~ps$ RMS\r
+($14~ps$ RMS on the worst channel) on a single channel. Additionally, the 264\r
+Channel TDC Platform, TDC Readout Board (TRB3), is presented in the paper\r
+applying the described TDC.\r
\end{abstract}\r
\r
% IEEEtran.cls defaults to using nonbold math in the Abstract.\r
\section{Introduction}\r
One of the application areas, where Time to Digital Converters (TDCs) are\r
widely used, is in particle physics experiments. These experiments constantly\r
-demand higher rates and more precise time measurements, therefore the compelling\r
+demand higher rates and more precise time measurements, therefore compelling\r
constant development on the TDCs. Among many TDC architectures FPGA based TDCs\r
-gained more and moree importance in recent years, due to their high\r
-performance, higher flexibility to adapt to special neeeds of the\r
+gained more and more importance in recent years, due to their high\r
+performance, higher flexibility to adapt to the special needs of the\r
application and reduced development time compared to ASIC TDCs.\r
\r
The review of the time interval measurement methods is given and discussed in\r
-detail in \cite{kalisz_review}. Many TDC designs based on delay lines are\r
-implemented in the recent years and precisions between $5~ps$ and $60~ps$ are\r
-achieved\cite{tdl1, tdl2, tdl3, tdl4}.\r
+detail in \cite{kalisz_review}. Many TDC designs based on delay lines have\r
+been implemented in recent years and precisions between $5~ps$ and $60~ps$\r
+have been achieved\cite{tdl1, tdl2, tdl3, tdl4}.\r
\r
\section{TDC Architecture}\r
\r
The TDC architecture is based on the interpolation method, as a long\r
measurement range with high precision is needed. In order to achieve a high\r
-precision a fine time interpolator based on tapped delay line method (TDL)\r
-with a wave union launcher \cite{wu_wul} is used. \replaced[id=MT]{The coarse counter\r
- ($5~ns$ period) and an epoch counter ($10~us$ period) complete the time\r
- measurement with a total range up to seconds.}{For the long measurement\r
- range a double interpolation of coarse counter and an epoch counter is\r
- applied.} All these time information are written to a ring buffer as\r
-illustrated in \autoref{fig:tdc_arch}.\r
+precision a fine time interpolator based on the tapped delay line method (TDL)\r
+with a wave union launcher \cite{wu_wul} is used. The coarse counter ($5~ns$\r
+period) and the epoch counter ($\sim10~us$ period) complete the time\r
+measurement with a total range up to $\sim45$ minutes. All these time\r
+measurements are written to a ring buffer as illustrated in\r
+\autoref{fig:tdc_arch}.\r
\r
\begin{figure}[!t]\r
\centering\r
\r
\subsection{Fine Time Interpolator}\r
\r
-For the fine time a interpolator TDL method is implemented \autoref{fig:tdl},\r
-as the architectures of the modern FPGAs are well suited for the method. This\r
-method \replaced[id=MT]{utilizes}{applies} the intrinsic delays of the delay\r
+For the fine time interpolator the TDL method is implemented\r
+(\autoref{fig:tdl}), as the architectures of the modern FPGAs are well suited\r
+for this method. This method utilises the intrinsic delays of the delay\r
elements for time measurements. While the start signal propagates through the\r
delay elements along the delay line, the rising edge of the stop signal, which\r
has a minimal skew (in theory $0~s$), samples the state of the delay\r
-line. With the location of the start signal and the intrinsic delay of a\r
-single delay element the time between the start and the stop signals can be\r
-calculated. As the intrinsic delay of the delay elements effects the bin width\r
-of the fine time interpolator, the shorter the intrinsic delay is, the higher\r
-the precision will be. Therefore we \replaced[id=MT]{make use of}{apply} the\r
-carry chain lines in the FPGA, which are dedicated for fast arithmetic\r
-operations and have logic elements with very small intrinsic delays.\r
+line. With the location of the start signal on the delay line and the\r
+intrinsic delay of a single delay element the time between the start and the\r
+stop signals can be calculated. The intrinsic delays of the delay elements\r
+affect the bin width of the fine time interpolator. The shorter the intrinsic\r
+delay, the higher the precision. Therefore we make use of the carry chain\r
+lines in the FPGA, which are dedicated for fast arithmetic operations and have\r
+logic elements with very small intrinsic delays.\r
\r
\begin{figure}[!t]\r
\centering\r
clock inputs of the flip-flops. This skewness should be minimal in order to\r
keep the fine time interpolator bins at a similar width and reduce the\r
non-linearity. Hence the reason we use the clock signal as the stop signal,\r
-for the reason that, it is distributed over the clock\r
-\replaced[id=MT]{distribution network}{lines}, which are engineered by the\r
-FPGA developers to keep the clock skewness at minimum.\r
+for the reason that, it is distributed over the clock distribution network,\r
+which is engineered by the FPGA developers to keep the clock skewness at a\r
+minimum.\r
\r
\r
\subsection{Coarse Time Interpolator}\r
\r
-The coarse time interpolator \replaced{consists of}{employs} a coarse counter\r
-and an epoch counter, which are \deleted{respectively} 11-bits and 28-bits\r
-long\added{, respectively}. The coarse counter is triggered by the system\r
+The coarse time interpolator consists of a coarse counter\r
+and an epoch counter, which are 11-bits and 28-bits\r
+long respectively. The coarse counter is triggered by the system\r
clock, whereas the epoch counter is driven by the coarse counter overflow and\r
together they increase the measurement range up to $\sim45~minutes$. The\r
coarse counter information is written to the ring buffer for each hit signal,\r
-however in order to decrease the \replaced[id=MT]{transported amount of\r
- data}{the excessive bits in the data stream} the epoch counter information\r
-is recorded \replaced{only}{, if and only} if the coarse counter overflow occurs.\r
+however in order to decrease the transported amount of data the epoch counter\r
+information is recorded only if the coarse counter overflow occurs.\r
\r
Using the Nutt method \cite{nutt} the total time information of a hit signal\r
and the time interval between two hit signals on different channels\r
-(\autoref{fig:hitTime}) is calculated as in \autoref{eq:tDiff}. Please note\r
+(\autoref{fig:hitTime}) is calculated as in \autoref{eq:tDiff}. Note\r
that the fine time interpolator is a backward counter.\r
\r
\begin{equation}\r
Induced by the non-ideal topology of the FPGA architecture and non-uniform\r
parasitic reactances \cite{pelka_nonlinearity} the intrinsic delays along the\r
carry chain are not uniform. This non-uniformity dramatically decreases the\r
-sensitivity of the TDL, if the TDL is latched, while the hit signal is\r
-propagating through an ultra wide bin (UWB). Suggested by \cite{wu_wul}, the\r
+sensitivity of the TDL, if the TDL is latched, while the hit signal propagates\r
+through an ultra wide bin (UWB). Suggested by \cite{wu_wul}, the\r
sensitivity of the TDL can be increased by applying the Wave Union Launcher\r
(WUL) method. Using the two transition WUL the maximum bin width is decreased\r
-to $35~ps$ from $45~ps$ \added[id=MT]{What about the mean bin\r
- width?}(\autoref{fig:bin_wid}). The effect of the WUL on the time precision\r
-is shown in \autoref{sec:results}.\r
+to $35~ps$ from $45~ps$, whereas the average bin width is reduced to\r
+$\sim10~ps$ from $\sim20~ps$ (\autoref{fig:bin_wid}). The effect of the WUL on\r
+the time precision is shown in \autoref{sec:results}.\r
\r
\begin{figure*}[!t]\r
\centerline{\subfloat[Traditional TDL method.]{\includegraphics[width=2.5in]{bin_wid_sing}%\r
\label{fig:bin_wid}\r
\end{figure*}\r
\r
-In order to \replaced{inject}{induce} two transitions into the TDL the hit\r
+In order to induce two transitions into the TDL the hit\r
signal is split in the FPGA. The delay lines between the split and the TDL\r
-must have \deleted{the} similar delays. Otherwise, either the first transition\r
-might overtake the second one and destroy the transition pattern in the TDL or\r
-the second transition might take off much earlier than the first one and\r
-\added[id=MT]{generate an} over flow \added{of} the TDL for some hits. At this\r
+must have similar delays. Otherwise, either the first transition\r
+may overtake the second one and destroy the transition pattern in the TDL or\r
+the second transition may take off much earlier than the first one and\r
+generate an over flow of the TDL for some hits. At this\r
point very careful placement and routing in the FPGA comes into the equation.\r
\r
\subsection{Semi-asynchronous Stretcher for Minimum Pulse Width Limitation}\r
\r
Some detectors used in particle physics experiments - e.g. Microchannel Plate\r
-(MCP) Detectors used for \replaced{single photon}{electron} detection - can\r
+(MCP) Detectors used for single photon detection - can\r
generate pulses as short as $1~ns$. These short signals cannot be measured by\r
the traditional TDL based TDCs. In the traditional TDL based TDC concept the\r
state of the start signal has to be preserved until the rising edge of the\r
guarantee this condition the width of the hit signal must be longer than the\r
period of the clock.\r
\r
-In our work a semi-asynchronous pulse stretcher is designed to extend the\r
+In our work, a semi-asynchronous pulse stretcher is designed to extend the\r
length of the hit signals more than one clock period. The demonstration of the\r
stretcher is shown in \autoref{fig:stretcher}. The short pulse from the\r
detector is connected to the clock input of the D-flipflop and with the rising\r
random hit signals (not correlated with the clock) over the measurement\r
interval of the fine time interpolator (\textit{$P$}) (in our case $5~ns$) are\r
used to generate a histogram. Knowing the number of the hits in each bin\r
-(\textit{$H_n$}) it is possible to calculate the bin width\r
+(\textit{$H_n$}) it is possible to calculate each bin width\r
(\textit{$BW_n$})\cite{wu_wul}:\r
\r
\begin{equation}\r
\label{sec:results}\r
\r
Several tests were carried out in order to determine the quality and the\r
-limitations of the TDC designed. Some of these tests are the precision, mean,\r
-minimum pulse width, dead time, calibration and temperature test.\r
+limitations of the TDC designed. These tests include the precision, mean,\r
+minimum pulse width, dead time, calibration and temperature tests.\r
\r
-In order to test the precision \deleted{quality} of the TDC a LVDS pulse from\r
-a pulse generator was split using an LVDS splitter ($max9153$ $1~ps$ random\r
-jitter\cite{max}) and fed to two different channels of the TDC through a\r
+In order to test the precision of the TDC a LVDS pulse from\r
+a pulse generator was split using a LVDS splitter ($max9153$ $1~ps$ random\r
+jitter\cite{max}) and fed to two different channels of the TDC through\r
coaxial cables. At least $300\thinspace000$ measurements were collected at\r
stable environmental conditions for the offline calibration stage. The time\r
interval between the rising edges of the signals was calculated as explained\r
-in \autoref{eq:tDiff} for the set of data and filled into a histogram. The\r
+in \autoref{eq:tDiff} for a set of data and entered into a histogram. The\r
time precision was measured by calculating the root mean square (RMS) of the\r
-peak without \added{applying} any \replaced[id=MT]{cuts}{curve fittings}.\r
-\r
-\replaced[id=MT]{This is well known and should be ommited}{\r
-Please note that the RMS values in the time difference histograms are the\r
-errors of the two channels and one should divide the value with $\sqrt{2}$ in\r
-order to find the time precision of a single channel.}\r
+peak without applying any curve fittings.\r
\r
The precision measurements were repeated for the designs with and without the\r
WUL and the results are given in \autoref{fig:precision}. The time\r
\label{fig:precision}\r
\end{figure*}\r
\r
-The measured mean time of the TDC is also tested. For this test, as due to the\r
+The measured mean time of the TDC is also tested. For this test, due to the\r
unknown delays of the hit signals on the PCB and in the FPGA, the change in the\r
mean time was measured. The change in the mean time was created by extending the\r
-cable length of one of the hit signals by certain amount. In other words one\r
-of the hits signals is shifted by a known amount of time relative to the other\r
+cable length of one of the hit signals by a certain amount. In other words, one\r
+of the hit signals is shifted by a known amount of time relative to the other\r
one. Sets of measurements for $3~cm$, $6~cm$ and $9~cm$ were done and the results are\r
shown in \autoref{fig:mean} with the original length.\r
\r
stretcher concept and to find out the minimum pulse width, which can be\r
measured. The pulses were generated by setting a high threshold level of the\r
NB4N316M discriminator at the output of the LeCroy 9212 Pulse Generator. The\r
-shortest pulse, that could be generated with this setup has a pulse width of\r
+shortest pulse that could be generated with this setup had a pulse width of\r
$\sim500~ps$. In order to measure the width of the short pulse the pulse was\r
-sent to the FPGA, internally split and fed to two channels, one of which has\r
-an inverter at the input. In other words the rising and falling edges of the\r
-pulse are measured on two channels. The difference between these two channels\r
-is filled in a histogram after calibration.\r
+sent to the FPGA, internally split and fed to two channels, one of which had\r
+an inverter at the input. In other words, the rising and falling edges of the\r
+pulse were measured on two channels. The difference between these two channels\r
+was recorded in a histogram after calibration.\r
\r
In \autoref{fig:shortpulse} it can be seen, that the mean of the peak is at\r
$519~ps$, which gives the width of the pulse. Also the measured error is not\r
readout of the TDC was triggered using a Tektronix Arbitrary Waveform Generator\r
(AWG7122C). The time interval between the leading edges of the two pulses were\r
adjusted with the AWG during the measurements and the number of hits per event\r
-was analysed. For the time gaps, dead time, $15~ns<t_{dt}$ both of the hits are\r
-detected by the TDC. If the time gap is selected as $10~ns<t_{dt}\le15~ns$,\r
-for some events the second hit is not detected. For time gaps $t_{dt}\le10~ns$\r
-only the first hit is detected. In simulations the dead time is calculated as\r
+was analysed. For the time gaps, dead time, $15~ns<t_{dt}$ both of the hits were\r
+detected by the TDC. If the time gap was selected as $10~ns<t_{dt}\le15~ns$,\r
+for some events the second hit was not detected. For time gaps $t_{dt}\le10~ns$\r
+only the first hit was detected. In simulations the dead time was calculated as\r
3 clock cycles ($15~ns$), however due to imperfections in the clock period and\r
-the slight skew in the clock line, the dead time is measured as\r
+the slight skew in the clock line, the dead time was measured as\r
$15~ns<t_{dt}$. This dead time is equal to $<66.7~MHz$ of maximum hit rate in\r
-burst of 64 hits.\r
+a burst of 64 hits.\r
\r
The effect of the number of hits used for calibration is also\r
-investigated. The same set of data collected at constant temperature is\r
-analysed with different calibration tables generated with different number of\r
+investigated. The same set of data collected at constant temperature was\r
+analysed with different calibration tables generated with a different number of\r
hits from the same data set. As it can be seen in the \autoref{fig:rms_vs_hit}\r
with the increasing number of hits used, the fine time histogram starts to fill\r
out and the time precision decreases rapidly. The calculated precision starts\r
\label{fig:rms_vs_hit}\r
\end{figure}\r
\r
-The increasing temperature change have negative effects on the intrinsic\r
+The increasing temperature change has negative effects on the intrinsic\r
delays of the delay elements on the carry chain line. With the rising\r
temperature the amount of current flowing through the transistors decreases and\r
therefore, the required time to charge/discharge the output load increases. The\r
increasing delay of each delay element changes the bin widths. Moreover, the\r
-calibration table generated at certain temperature is no longer valid for\r
+calibration table generated at a certain temperature is no longer valid for\r
other temperatures. \autoref{fig:rms_vs_temp} shows the change in the time\r
precision with the increasing temperature. As long as the calibration table is\r
updated for the temperature value, the time precision stays stable. Otherwise,\r
\section{TDC Readout Board - TRB3}\r
\r
Using the above mentioned research an FPGA based TDC Platform with 264\r
-channels \replaced{was}{is}developed to be used in various particle\r
+channels was developed to be used in various particle\r
physics experiments and medical imaging - TRB3\cite{traxler_trb3}. The\r
platform consists of 5 Lattice ECP3 FPGAs each consisting of $150~K$ logic\r
elements. The 4 peripheral FPGAs are used as TDCs each containing 65\r
-channels. First channel of each TDC digitises the arrival time of the common\r
+channels. The first channel of each TDC digitises the arrival time of the common\r
trigger signal. This way all TDC data can be synchronised, if a bigger system,\r
which contains more than one TRB3, is used. The central FPGA is used for data\r
concentration, data transfer over either GbE or optical links, slow-control\r
channel has a maximum of $66.7~MHz$ burst hit rate and the maximum readout\r
trigger rate of the system is $700~kHz$. Thanks to the standard GbE protocol\r
implemented in the central FPGA, power supply and an Ethernet cable is the\r
-only necessary equipment for data taking.\r
+only necessary equipment for data capturing.\r
\r
-For this platform various front-end electronics (FEE) \replaced{were}{are}\r
+For this platform various front-end electronics (FEE) were\r
developed and are being developed for Time-of-Flight (ToF),\r
Time-over-Threshold (ToT) and charge measurements. One low cost FEE developed\r
for the ToF and ToT measurements of a MCP detector for the PANDA experiment\r
$0.2\%$ charge precision.\r
\r
\r
-\added[id=MT]{Precision vs. Resolution: Nothing to be discussed in a paper,\r
- this is a discussion with the referees, I think. But the information at the\r
- end, that the FPGA-TDC would have a resolution of 35ps, and a precision of\r
- <10ps is intersesting. Sill I would not put it in to avoid confusion.}\r
-\section{Precision vs Resolution}\r
-\label{sec:pre_vs_res}\r
-In most of the literature about the TDCs, which are based on statistical\r
-approach, the word ``\textit{resolution}'' is used to determine the measurement\r
-quality of the TDCs. This terminology comes from the flash ADCs, as the TDL\r
-based TDCs are also called ``\textit{Flash TDCs}''. However, as the authors of\r
-this paper, we believe, the correct word for the figure of merit for quality\r
-should be ``\textit{precision}'' for the TDCs, which are based on statistical\r
-approach.\r
-\r
-\r
-``The property of the set of measurements of being very reproducible\r
-or of an estimate of having small random error of estimation.'' is given as\r
-the definition of precision in the web site of the \textit{Organisation for\r
- Economic Co-operation and Development}\cite{precision}. The explanation continues\r
-as ``Precision is a quality associated with a class of measurements and refers\r
-to the way in which repeated observations conform to themselves.''. As you can\r
-see, the precision is defined as the error of the repeated observations,\r
-which is exactly what the TDC does: measures the same time interval\r
-repeatedly. Then we calculate the RMS of these repeated measurements in order\r
-to define the quality of the measurements.\r
-\r
-The word ``resolution'' can be used for the converters, which are highly\r
-linear ($INL<1 LSB$), such as flash ADCs. For flash ADCs the resolution is\r
-defined as ``the smallest voltage, which can be translated by the\r
-ADC''\cite{resolution}. So the smallest change in the input of the ADC, which\r
-guarantees a change in the output gives the resolution. If we translate this\r
-to the TDC, the smallest time interval, which guarantees a time change in the\r
-output is the largest bin in the fine time histogram, which is $35~ps$ in our\r
-case.\r
+% \added[id=MT]{Precision vs. Resolution: Nothing to be discussed in a paper,\r
+% this is a discussion with the referees, I think. But the information at the\r
+% end, that the FPGA-TDC would have a resolution of 35ps, and a precision of\r
+% <10ps is intersesting. Sill I would not put it in to avoid confusion.}\r
+% \section{Precision vs Resolution}\r
+% \label{sec:pre_vs_res}\r
+% In most of the literature about the TDCs, which are based on statistical\r
+% approach, the word ``\textit{resolution}'' is used to determine the measurement\r
+% quality of the TDCs. This terminology comes from the flash ADCs, as the TDL\r
+% based TDCs are also called ``\textit{Flash TDCs}''. However, as the authors of\r
+% this paper, we believe, the correct word for the figure of merit for quality\r
+% should be ``\textit{precision}'' for the TDCs, which are based on statistical\r
+% approach.\r
+\r
+\r
+% ``The property of the set of measurements of being very reproducible\r
+% or of an estimate of having small random error of estimation.'' is given as\r
+% the definition of precision in the web site of the \textit{Organisation for\r
+% Economic Co-operation and Development}\cite{precision}. The explanation continues\r
+% as ``Precision is a quality associated with a class of measurements and refers\r
+% to the way in which repeated observations conform to themselves.''. As you can\r
+% see, the precision is defined as the error of the repeated observations,\r
+% which is exactly what the TDC does: measures the same time interval\r
+% repeatedly. Then we calculate the RMS of these repeated measurements in order\r
+% to define the quality of the measurements.\r
+\r
+% The word ``resolution'' can be used for the converters, which are highly\r
+% linear ($INL<1 LSB$), such as flash ADCs. For flash ADCs the resolution is\r
+% defined as ``the smallest voltage, which can be translated by the\r
+% ADC''\cite{resolution}. So the smallest change in the input of the ADC, which\r
+% guarantees a change in the output gives the resolution. If we translate this\r
+% to the TDC, the smallest time interval, which guarantees a time change in the\r
+% output is the largest bin in the fine time histogram, which is $35~ps$ in our\r
+% case.\r
\r
\r
\section{Conclusion}\r
In this paper the architecture of a 65 channel TDC implemented in a single\r
FPGA is discussed in detail and the test results displaying some of the\r
quality measurements are presented. The TDC has a maximum precision of\r
-$7.2~ps$ RMS and $<14~ps$ RMS on all channels. \added[id=MT]{The last sentence is\r
- unclear to me.} The solution for the short pulse limitation of the\r
-conventional TDCs and the non-linearity correction is analysed. Moreover, a\r
-264 channel TDC platform - TRB3 - based on the FPGA TDC design is\r
-disclosed. At last the terminology for the statistical approach based TDCs is\r
-argued in \autoref{sec:pre_vs_res}, ``\textit{Precision vs Resolution}''.\r
+$7.2~ps$ RMS and $<14~ps$ RMS on all channels. The solution for the short\r
+pulse limitation of the conventional TDCs and the non-linearity correction is\r
+analysed. Moreover, a 264 channel TDC platform - TRB3 - based on the FPGA TDC\r
+design is elaborated.\r
+% At last the terminology for the statistical approach based TDCs is\r
+% argued in \autoref{sec:pre_vs_res}, ``\textit{Precision vs Resolution}''.\r
\r
\r
\r
jspc29 / publication.git / commitdiff