NET ADO_TTL<29> LOC ="M11"| IOSTANDARD = "LVTTL";
NET ADO_TTL<30> LOC ="N11"| IOSTANDARD = "LVTTL";
NET ADO_TTL<31> LOC ="N12"| IOSTANDARD = "LVTTL";
- NET ADO_TTL_OUT<0> LOC ="P12"| IOSTANDARD = "LVTTL";
- NET ADO_TTL_OUT<1> LOC ="R12"| IOSTANDARD = "LVTTL";
- NET ADO_TTL_OUT<2> LOC ="R13"| IOSTANDARD = "LVTTL";
- NET ADO_TTL_OUT<3> LOC ="R14"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<32> LOC ="P12"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<33> LOC ="R12"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<34> LOC ="R13"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<35> LOC ="R14"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<36> LOC ="T12"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<37> LOC ="T13"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<38> LOC ="T14"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<39> LOC ="T6"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<40> LOC ="T5"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<41> LOC ="T4"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<42> LOC ="R6"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<43> LOC ="R5"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<44> LOC ="R4"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<45> LOC ="P5"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<46> LOC ="E7"| IOSTANDARD = "LVTTL";
+# NET ADO_TTL_OUT<0> LOC ="P12"| IOSTANDARD = "LVTTL";
+# NET ADO_TTL_OUT<1> LOC ="R12"| IOSTANDARD = "LVTTL";
+# NET ADO_TTL_OUT<2> LOC ="R13"| IOSTANDARD = "LVTTL";
+# NET ADO_TTL_OUT<3> LOC ="R14"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<32> LOC ="P12"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<33> LOC ="R12"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<34> LOC ="R13"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<35> LOC ="R14"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<36> LOC ="T12"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<37> LOC ="T13"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<38> LOC ="T14"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<39> LOC ="T6"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<40> LOC ="T5"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<41> LOC ="T4"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<42> LOC ="R6"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<43> LOC ="R5"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<44> LOC ="R4"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<45> LOC ="P5"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<46> LOC ="E7"| IOSTANDARD = "LVTTL";
NET A_R LOC ="A6"| IOSTANDARD = "TTL";
NET A_RB LOC ="D8";
NET A_RD<0> LOC ="B7"| IOSTANDARD = "TTL";
port(
-- -- # NET +<3> LOC = E8;
-- ADDON_RESET :in std_logic;
- ADO_TTL : inout std_logic_vector(34 downto 0);
+ ADO_TTL : inout std_logic_vector(46 downto 0);
ADO_TTL_OUT : out std_logic_vector(3 downto 0);
-- ------------------------------------------------------------------------------
-- -- LVL1
-- ------------------------------------------------------------------------------
-- -- LVL1
-- ------------------------------------------------------------------------------
--- ADO_TTL(4) <= B_R;
- B_RB <= '0';-- ADO_TTL(0) or A_RB;
--- ADO_TTL(8 downto 5) <= B_RD;
- B_RE <= '0';--ADO_TTL(1);
--- ADO_TTL(9) <= B_RS;
+ ADO_TTL(0) <= B_R;
+ ADO_TTL(1) <= B_RS;
+ ADO_TTL(5 downto 2) <= B_RD;
+ B_RE <= '0';--ADO_TTL(6);
+ ADO_TTL(6) <= 'Z';
+ B_RB <= ADO_TTL(7) or A_RB;
+ ADO_TTL(7) <= 'Z';
-- ------------------------------------------------------------------------------
-- -- LVL2
-- ------------------------------------------------------------------------------
- ADO_TTL(10) <= B_T;
- B_TB <= ADO_TTL(8);-- or A_TB;
- ADO_TTL(14 downto 11) <= B_TD;
- B_TE <= ADO_TTL(9);
- ADO_TTL(15) <= B_TS;
+ ADO_TTL(8) <= B_T;
+ ADO_TTL(9) <= B_TS;
+ ADO_TTL(13 downto 10) <= B_TD;
+ B_TE <= '0';--ADO_TTL(9);
+ ADO_TTL(14) <= 'Z';
+ B_TB <= ADO_TTL(15) or A_TB;
+ ADO_TTL(15) <= 'Z';
-- -----------------------------------------------------------------------------
-- -- Hades bus direction
-- -----------------------------------------------------------------------------
B_TB_D_DIR <= '0';
B_TB_E2_DIR <= '1';
B_TB_E1_DIR <= '1';
- ADO_TTL(9 downto 8) <= (others => 'Z');
--- ADO_TTL(3 downto 0) <= (others => 'Z');
-------------------------------------------------------------------------------
-- to next trb dtu data
-------------------------------------------------------------------------------
--- A_R <= B_R;
--- -- A_RB; --BUSY FROM NEXT TRB
--- A_RD <= B_RD;
--- -- A_RE ;--ERROR FROM NEXT TRB
--- A_RS <= B_RS;
--- ------------------------------------------------------------------------------
--- -- LVL2
--- ------------------------------------------------------------------------------
--- A_T <= B_T;
--- -- A_TB ; --BUSY FROM NEXT TRB
--- A_TD <= B_TD;
--- -- A_TE ; --ERROR FROM NEXT TRB
--- A_TS <= B_TS;
--- -----------------------------------------------------------------------------
--- -- Hades bus direction
--- -----------------------------------------------------------------------------
--- A_TB_B2_DIR <= '0';
--- A_TB_B1_DIR <= '0';
--- A_TB_D_DIR <= '1';
--- A_TB_E2_DIR <= '0';
--- A_TB_E1_DIR <= '0';
+ --LVL1
+ A_R <= B_R;
+ A_RD <= B_RD;
+ A_RS <= B_RS;
+ -- LVL2
+ A_T <= B_T;
+ A_TD <= B_TD;
+ A_TS <= B_TS;
+ -----------------------------------------------------------------------------
+ -- Hades bus direction
+ -----------------------------------------------------------------------------
+ A_TB_B2_DIR <= '0';
+ A_TB_B1_DIR <= '0';
+ A_TB_D_DIR <= '1';
+ A_TB_E2_DIR <= '0';
+ A_TB_E1_DIR <= '0';
----------------------------------------------------------------------------
-- scalers
-- Vulom interface
-------------------------------------------------------------------------------
- ADO_TTL(4) <= 'Z';
--- ADO_TTL(3 downto 0) <= DIFF_IN(0 to 3);
- ADO_TTL(1) <= DIFF_IN(0);
- ADO_TTL(2) <= DIFF_IN(1);
- ADO_TTL(3) <= DIFF_IN(2);
--- ADO_TTL(3) <= DIFF_IN(3);
--- ADO_TTL(15 downto 12) <= DIFF_IN(3 downto 0);
- busy <= ADO_TTL(4);
- ADO_TTL_OUT(0) <= '0';--busy;--ADO_TTL(4);
+ ADO_TTL(46) <= DIFF_IN(0);
+ ADO_TTL(41) <= DIFF_IN(1);
+ ADO_TTL(42) <= DIFF_IN(2);
+ ADO_TTL(32) <= '0';--busy;--ADO_TTL(4);
+ ADO_TTL(33) <= 'Z';--ADO_TTL(43); --RETRANSMIT
+ ADO_TTL(34) <= 'Z';--ADO_TTL(44); --ACK
+ ADO_TTL(35) <= '0';--busy;--ADO_TTL(4);
- ADO_TTL_OUT(1) <= ADO_TTL(6); --RETRANSMIT
- ADO_TTL_OUT(2) <= ADO_TTL(5); --ACK
- ADO_TTL_OUT(3) <= '0';--busy;--ADO_TTL(4);
end gp_add_on;
signal lvl2_fifo_data_out : std_logic_vector(11 downto 0);
signal lvl2_fifo_we_in : std_logic;
signal fifo_counter: std_logic_vector(3 downto 0);
-
+signal lvl1_fast_busy : std_logic:='0';
+signal lvl2_fast_busy : std_logic:='0';
type send_lvl2_trigger is (IDLE, SEND_TRIGGER, WAIT_FOR_ACK);
signal current_state_send_lvl2_trigger, next_state_send_lvl2_trigger : send_lvl2_trigger;
end if;
end if;
end process LVL1_SAVE_CODE_AND_TAG;
+ MAKE_FAST_LVL1_BUSY: process (CLK, RESET)
+ begin -- process MAKE_FAST_LVL1_BUSY
+ if rising_edge(CLK) then
+ if RESET = '1' or LVL1_BUSY = '1' or lvl1_code_i = x"d" then -- asynchronous reset (active low)
+ lvl1_fast_busy <= '0';
+ elsif lvl1_trigger_bus_pulse = '1' then
+ lvl1_fast_busy <= '1';
+ end if;
+ end if;
+ end process MAKE_FAST_LVL1_BUSY;
LVL1_CODE <= lvl1_code_i;
LVL1_TAG <= lvl1_tag_i;
lvl1_trb_trigg_enable <= lvl1_trigger_counter(0) and lvl1_trigger_counter(1); --
pulse => lvl1_trigger_i );
LVL1_TRIGGER <= lvl1_trigger_i;
- LVL1_BUSY_BUS <= LVL1_BUSY;-- or lvl1_error_bus_i;
+ LVL1_BUSY_BUS <= LVL1_BUSY or lvl1_fast_busy;-- or lvl1_error_bus_i;
LVL1_COUNT_TRIGGERS: process (CLK, RESET, lvl1_trigger_bus_pulse_synch)
begin
if rising_edge(CLK) then
end if;
end if;
end process LVL2_SAVE_CODE_AND_TAG;
-
+MAKE_FAST_LVL2_BUSY: process (CLK, RESET)
+ begin -- process MAKE_FAST_LVL2_BUSY
+ if rising_edge(CLK) then
+ if RESET = '1' or LVL2_BUSY = '1' then -- asynchronous reset (active low)
+ lvl2_fast_busy <= '0';
+ elsif lvl2_trigger_bus_pulse = '1' then
+ lvl2_fast_busy <= '1';
+ end if;
+ end if;
+ end process MAKE_FAST_LVL2_BUSY;
lvl2_fifo_data_in <= lvl2_code_i & lvl2_tag_i;
LVL2_CODE <= lvl2_fifo_data_out(11 downto 8);
LVL2_TAG <= lvl2_fifo_data_out(7 downto 0);
lvl2_fifo_full <= '0' when fifo_counter < x"e" else '1';
lvl2_fifo_not_empty <= '1' when fifo_counter > x"0" else '0';
-- LVL2_BUSY_BUS <= LVL2_BUSY or lvl2_fifo_full;
- LVL2_BUSY_BUS <= lvl2_fifo_full;-- or lvl2_error_bus_i;
+ LVL2_BUSY_BUS <= lvl2_fifo_full or lvl2_fast_busy or LVL2_BUSY;-- or lvl2_error_bus_i;
SEND_LVL2_TRIGGER_FSM : process (CLK,RESET)
begin
if rising_edge(CLK) then
end process SEND_LVL2_TRIGGER_FSM;
SEND_LVL2_TRIGGER_PROC: process (lvl2_fifo_not_empty,LVL2_TRB_ACK,CLK,LVL2_BUSY)
- begin
+ begin
+ lvl2_trigger_i <= '0';
case current_state_send_lvl2_trigger is
+
when IDLE =>
lvl2_trigger_i <= '0';
if lvl2_fifo_not_empty = '1' and LVL2_BUSY = '0' then
next_state_send_lvl2_trigger <= WAIT_FOR_ACK;
end if;
when others =>
+ lvl2_trigger_i <= '0';
next_state_send_lvl2_trigger <= IDLE;
end case;
end process SEND_LVL2_TRIGGER_PROC;
end if;
end process LVL2_CHECK_TAG;
LVL2_ERROR_BUS <= '0';--lvl2_error_bus_i;
- DTU_DEBUG_00 <= x"00" & "00" & lvl2_fifo_address_out& lvl2_fifo_address_in & fifo_counter & lvl2_fifo_full & lvl2_trigger_i & lvl2_triggers_counter;
+ DTU_DEBUG_00 <= lvl2_fifo_data_out(7 downto 0) & lvl2_fifo_address_out& lvl2_fifo_address_in & fifo_counter & lvl2_fifo_full & "00" & lvl2_trigger_i & lvl2_triggers_counter;
end dtu_interface;
-------------------------------------------------------------------------------
-- reset
-------------------------------------------------------------------------------
- MAKE_EXTERNAL_RESET: process (CLK)
- begin
- if rising_edge(CLK) then
- if ETRAX_DATA_BUS_C(17) ='0' or ETRAX_DATA_BUS_C(16)='0' or ETRAX_DATA_BUS_B(17)= '0' then
- external_reset_counter <= (others => '0');
- elsif ETRAX_DATA_BUS_C(17) ='1' and ETRAX_DATA_BUS_C(16)='1' and ETRAX_DATA_BUS_B(17)= '1' then
- external_reset_counter <= external_reset_counter + 1;
- end if;
- end if;
- end process MAKE_EXTERNAL_RESET;
+-- MAKE_EXTERNAL_RESET: process (CLK)
+-- begin
+-- if rising_edge(CLK) then
+-- if ETRAX_DATA_BUS_C(17) ='0' or ETRAX_DATA_BUS_C(16)='0' or ETRAX_DATA_BUS_B(17)= '0' then
+-- external_reset_counter <= (others => '0');
+-- elsif ETRAX_DATA_BUS_C(17) ='1' and ETRAX_DATA_BUS_C(16)='1' and ETRAX_DATA_BUS_B(17)= '1' then
+-- external_reset_counter <= external_reset_counter + 1;
+-- end if;
+-- end if;
+-- end process MAKE_EXTERNAL_RESET;
MAKE_START_RESET: process (CLK)
begin
ETRAX_READY_PULSE : edge_to_pulse
port map (
clock => CLK,
- en_clk => DATA_VALID,--'1',
+ en_clk => '1', --DATA_VALID
signal_in => ETRAX_DATA_BUS_B(17),
pulse => etrax_is_ready_to_read_i);
- MAKE_PULSES: process (CLK, internal_reset_i)
- begin
- if rising_edge(CLK) then
- if internal_reset_i = '1' then
- counter_for_pulses <= "000";
- else
- counter_for_pulses <= counter_for_pulses + 1;
- end if;
- end if;
- end process make_pulses;
+ MAKE_PULSES: process (CLK, internal_reset_i)
+ begin
+ if rising_edge(CLK) then
+ if internal_reset_i = '1' then
+ counter_for_pulses <= "000";
+ else
+ counter_for_pulses <= counter_for_pulses + 1;
+ end if;
+ end if;
+ end process make_pulses;
LVL2_NOT_VALID_READY_PULSE : edge_to_pulse
port map (
clock => CLK,
end process ENABLE_TRIGG_TOETRAX;
-- ETRAX_DATA_BUS_B(16) <= not CLK when en_trigg_to_etrax = '1' else '0';
not_etrax_busy <= not ETRAX_DATA_BUS_B(17);
- ETRAX_NOT_BUSY_PULSER : edge_to_pulse
- port map (
- clock => CLK,
- en_clk => '1',
- signal_in => not_etrax_busy,
- pulse => etrax_busy_end_pulse);
+-- ETRAX_NOT_BUSY_PULSER : edge_to_pulse
+-- port map (
+-- clock => CLK,
+-- en_clk => '1',
+-- signal_in => not_etrax_busy,
+-- pulse => etrax_busy_end_pulse);
- COUNT_SENT_WORDS: process (CLK, RESET,ETRAX_DATA_BUS_B,busy_dma_counter,etrax_is_ready_to_read_i,ETRAX_DATA_BUS_B(17))
- begin -- process COUNT_SENT_WORDS
- if rising_edge(CLK) then
- if internal_reset_i = '1' or etrax_busy_end_pulse = '1' then -- asynchronous reset (active low)
- busy_dma_counter <= x"0";
+-- COUNT_SENT_WORDS: process (CLK, RESET,ETRAX_DATA_BUS_B,busy_dma_counter,etrax_is_ready_to_read_i,ETRAX_DATA_BUS_B(17))
+-- begin -- process COUNT_SENT_WORDS
+-- if rising_edge(CLK) then
+-- if internal_reset_i = '1' or etrax_busy_end_pulse = '1' then -- asynchronous reset (active low)
+-- busy_dma_counter <= x"0";
- elsif etrax_is_ready_to_read_i = '1' and busy_dma_counter < x"a" then
- busy_dma_counter <= busy_dma_counter + 1;
+-- elsif etrax_is_ready_to_read_i = '1' and busy_dma_counter < x"a" then
+-- busy_dma_counter <= busy_dma_counter + 1;
- end if;
- end if;
- end process COUNT_SENT_WORDS;
- busy_dma <= '1' when busy_dma_counter= x"a" else '0';
+-- end if;
+-- end if;
+-- end process COUNT_SENT_WORDS;
+-- busy_dma <= '1' when busy_dma_counter= x"a" else '0';
ETRAX_DATA_BUS_B(16) <= DATA_VALID and (not LVL2_VALID);
-------------------------------------------------------------------------------
-- tdc jtag programming
SFP_INP_P : in std_logic_vector(15 downto 0);
SFP_OUT_N : out std_logic_vector(15 downto 0);
SFP_OUT_P : out std_logic_vector(15 downto 0);
- OPT_DATA_IN : in std_logic_vector(31 downto 0);
- OPT_DATA_OUT : out std_logic_vector(31 downto 0);
- OPT_DATA_VALID_IN : in std_logic_vector(1 downto 0);
- OPT_DATA_VALID_OUT : out std_logic_vector(1 downto 0));
+ OPT_DATA_IN : in std_logic_vector(63 downto 0);
+ OPT_DATA_OUT : out std_logic_vector(63 downto 0);
+ OPT_DATA_VALID_IN : in std_logic_vector(2 downto 0);
+ OPT_DATA_VALID_OUT : out std_logic_vector(2 downto 0));
end component;
component trb_v2b_fpga
port (
C_TRIGGERB : out std_logic;
D_TRIGGER : out std_logic;
D_TRIGGERB : out std_logic;
- FS_PB : out std_logic_vector (17 downto 0);
+ FS_PB : inout std_logic_vector (17 downto 0);
FS_PC : inout std_logic_vector (17 downto 0);
ETRAX_IRQ : out std_logic;
A_SCK : out std_logic;
D_TEST1B : out std_logic;
D_TEST2 : out std_logic;
D_TEST2B : out std_logic;
- DSPADDR : out std_logic_vector (31 downto 0);
- DSPDAT : inout std_logic_vector (31 downto 0);
- DSP_ACK : in std_logic;
- DSP_BM : inout std_logic;
- DSP_BMS : out std_logic;
- DSP_BOFF : out std_logic;
- DSP_BRST : inout std_logic;
- DSP_HBG : in std_logic;
- DSP_HBR : out std_logic;
- DSP_IRQ : out std_logic_vector (3 downto 0);
- DSP_RD : out std_logic;
- DSP_RESET : out std_logic;
- DSP_RESET_OUT : in std_logic;
- DSP_WRH : out std_logic;
- DSP_WRL : out std_logic;
- VSD_A : out std_logic_vector (12 downto 0);
- VSD_BA : out std_logic_vector (1 downto 0);
- VSD_CAS : out std_logic;
- VSD_CKE : out std_logic;
- VSD_CLOCK : out std_logic;
- VSD_CSEH : out std_logic;
- VSD_CSEL : out std_logic;
- VSD_D : inout std_logic_vector (31 downto 0);
- VSD_DQML : out std_logic_vector (3 downto 0);
- VSD_RAS : out std_logic;
- VSD_WE : out std_logic;
+-- DSPADDR : out std_logic_vector (31 downto 0);
+-- DSPDAT : inout std_logic_vector (31 downto 0);
+-- DSP_ACK : in std_logic;
+-- DSP_BM : inout std_logic;
+-- DSP_BMS : out std_logic;
+-- DSP_BOFF : out std_logic;
+-- DSP_BRST : inout std_logic;
+-- DSP_HBG : in std_logic;
+-- DSP_HBR : out std_logic;
+-- DSP_IRQ : out std_logic_vector (3 downto 0);
+-- DSP_RD : out std_logic;
+-- DSP_RESET : out std_logic;
+-- DSP_RESET_OUT : in std_logic;
+-- DSP_WRH : out std_logic;
+-- DSP_WRL : out std_logic;
+-- VSD_A : out std_logic_vector (12 downto 0);
+-- VSD_BA : out std_logic_vector (1 downto 0);
+-- VSD_CAS : out std_logic;
+-- VSD_CKE : out std_logic;
+-- VSD_CLOCK : out std_logic;
+-- VSD_CSEH : out std_logic;
+-- VSD_CSEL : out std_logic;
+-- VSD_D : inout std_logic_vector (31 downto 0);
+-- VSD_DQML : out std_logic_vector (3 downto 0);
+-- VSD_RAS : out std_logic;
+-- VSD_WE : out std_logic;
TLK_CLK : in std_logic;
TLK_ENABLE : out std_logic;
TLK_LCKREFN : out std_logic;
SFP_LOS : in std_logic;
SFP_TX_DIS : out std_logic;
SFP_TX_FAULT : in std_logic;
+ ADDON_TO_TRB_CLKINN : in std_logic;
+ ADDON_TO_TRB_CLKINP : in std_logic;
ADO_LV : in std_logic_vector(51 downto 0);
ADO_TTL : inout std_logic_vector(46 downto 0);
VIRT_TCK : out std_logic;
DGOOD : out std_logic;
DINT : out std_logic;
DWAIT : out std_logic;
- FS_PB : out std_logic_vector (17 downto 0);
+ FS_PB : inout std_logic_vector (17 downto 0);
FS_PC : inout std_logic_vector (17 downto 0);
ETRAX_IRQ : out std_logic;
DSPADDR : out std_logic_vector (31 downto 0);
SFP_LOS : in std_logic;
SFP_TX_DIS : out std_logic;
SFP_TX_FAULT : in std_logic;
- ADO_CLK1 : in std_logic;
- ADO_CLK2 : in std_logic;
+-- ADO_CLK1 : in std_logic;
+ ADO_CLK : in std_logic;
ADO_LV : in std_logic_vector(51 downto 0);
- ADO_TTL : inout std_logic_vector(46 downto 2));
- end component;
+ ADO_TTL : inout std_logic_vector(45 downto 0));
+ end component;
+ --hub
signal LVDS_CLK_200P_i : std_logic;
- signal ADO_TTL_i : std_logic_vector(46 downto 2);
+ signal ADO_TTL_i : std_logic_vector(45 downto 0);
signal DBAD_i : std_logic;
signal DGOOD_i : std_logic;
signal DINT_i : std_logic;
signal SFP_INP_P_i : std_logic_vector(15 downto 0);
signal SFP_OUT_N_i : std_logic_vector(15 downto 0);
signal SFP_OUT_P_i : std_logic_vector(15 downto 0);
- signal OPT_DATA_IN_i : std_logic_vector(31 downto 0);
- signal OPT_DATA_OUT_i : std_logic_vector(31 downto 0);
- signal OPT_DATA_VALID_IN_i : std_logic_vector(1 downto 0);
- signal OPT_DATA_VALID_OUT_i : std_logic_vector(1 downto 0);
-
+ signal OPT_DATA_IN_i : std_logic_vector(63 downto 0);
+ signal OPT_DATA_OUT_i : std_logic_vector(63 downto 0);
+ signal OPT_DATA_VALID_IN_i : std_logic_vector(2 downto 0);
+ signal OPT_DATA_VALID_OUT_i : std_logic_vector(2 downto 0);
+ --trb_0
signal VIRT_CLK_i : std_logic;
signal VIRT_CLKB_i : std_logic;
- signal RESET_VIRT_i : std_logic;
+ signal RESET_VIRT_0 : std_logic;
- signal A_RESERVED_i : std_logic;
- signal A_TEMP_i : std_logic;
- signal B_RESERVED_i : std_logic;
- signal B_TEMP_i : std_logic;
- signal C_RESERVED_i : std_logic;
- signal C_TEMP_i : std_logic;
- signal D_RESERVED_i : std_logic;
- signal D_TEMP_i : std_logic;
- signal VIR_TRIG_i : std_logic;
- signal VIR_TRIGB_i : std_logic;
- signal A_TDC_ERROR_i : std_logic;
- signal B_TDC_ERROR_i : std_logic;
- signal C_TDC_ERROR_i : std_logic;
- signal D_TDC_ERROR_i : std_logic;
- signal A_TDC_POWERUP_i : std_logic;
- signal B_TDC_POWERUP_i : std_logic;
- signal C_TDC_POWERUP_i : std_logic;
- signal D_TDC_POWERUP_i : std_logic;
- signal TOKEN_IN_i : std_logic;
- signal TOKEN_OUT_i : std_logic;
- signal C_TOKEN_OUT_TTL_i : std_logic;
- signal GET_DATA_i : std_logic;
- signal A_DATA_READY_i : std_logic;
- signal B_DATA_READY_i : std_logic;
- signal C_DATA_READY_i : std_logic;
- signal D_DATA_READY_i : std_logic;
+ signal A_RESERVED_0 : std_logic;
+ signal A_TEMP_0 : std_logic;
+ signal B_RESERVED_0 : std_logic;
+ signal B_TEMP_0 : std_logic;
+ signal C_RESERVED_0 : std_logic;
+ signal C_TEMP_0 : std_logic;
+ signal D_RESERVED_0 : std_logic;
+ signal D_TEMP_0 : std_logic;
+ signal VIR_TRIG_0 : std_logic;
+ signal VIR_TRIGB_0 : std_logic;
+ signal A_TDC_ERROR_0 : std_logic;
+ signal B_TDC_ERROR_0 : std_logic;
+ signal C_TDC_ERROR_0 : std_logic;
+ signal D_TDC_ERROR_0 : std_logic;
+ signal A_TDC_POWERUP_0 : std_logic;
+ signal B_TDC_POWERUP_0 : std_logic;
+ signal C_TDC_POWERUP_0 : std_logic;
+ signal D_TDC_POWERUP_0 : std_logic;
+ signal TOKEN_IN_0 : std_logic;
+ signal TOKEN_OUT_0 : std_logic;
+ signal C_TOKEN_OUT_TTL_0 : std_logic;
+ signal GET_DATA_0 : std_logic;
+ signal A_DATA_READY_0 : std_logic;
+ signal B_DATA_READY_0 : std_logic;
+ signal C_DATA_READY_0 : std_logic;
+ signal D_DATA_READY_0 : std_logic;
signal REF_TDC_CLK_i : std_logic;
signal REF_TDC_CLKB_i : std_logic;
- signal A_TDC_BU_RESET_i : std_logic;
- signal A_TDC_BU_RESETB_i : std_logic;
- signal A_TDC_EV_RESET_i : std_logic;
- signal A_TDC_EV_RESETB_i : std_logic;
- signal B_TDC_BU_RESET_i : std_logic;
- signal B_TDC_BU_RESETB_i : std_logic;
- signal B_TDC_EV_RESET_i : std_logic;
- signal B_TDC_EV_RESETB_i : std_logic;
- signal C_TDC_BU_RESET_i : std_logic;
- signal C_TDC_BU_RESETB_i : std_logic;
- signal C_TDC_EV_RESET_i : std_logic;
- signal C_TDC_EV_RESETB_i : std_logic;
- signal D_TDC_BU_RESET_i : std_logic;
- signal D_TDC_BU_RESETB_i : std_logic;
- signal D_TDC_EV_RESET_i : std_logic;
- signal D_TDC_EV_RESETB_i : std_logic;
- signal TDC_OUT_i : std_logic_vector (31 downto 0);
- signal TDC_RESET_i : std_logic;
- signal A_TRIGGER_i : std_logic;
- signal A_TRIGGERB_i : std_logic;
- signal B_TRIGGER_i : std_logic;
- signal B_TRIGGERB_i : std_logic;
- signal C_TRIGGER_i : std_logic;
- signal C_TRIGGERB_i : std_logic;
- signal D_TRIGGER_i : std_logic;
- signal D_TRIGGERB_i : std_logic;
- signal FS_PB_i : std_logic_vector (17 downto 0);
- signal FS_PC_i : std_logic_vector (17 downto 0);
- signal ETRAX_IRQ_i : std_logic;
- signal A_SCK_i : std_logic;
- signal A_SCKB_i : std_logic;
- signal A_SDI_i : std_logic;
- signal A_SDIB_i : std_logic;
- signal A_SDO_i : std_logic;
- signal A_SDOB_i : std_logic;
- signal A_CSB_i : std_logic;
- signal A_CS_i : std_logic;
- signal B_SCK_i : std_logic;
- signal B_SCKB_i : std_logic;
- signal B_SDI_i : std_logic;
- signal B_SDIB_i : std_logic;
- signal B_SDO_i : std_logic;
- signal B_SDOB_i : std_logic;
- signal B_CSB_i : std_logic;
- signal B_CS_i : std_logic;
- signal C_SCK_i : std_logic;
- signal C_SCKB_i : std_logic;
- signal C_SDI_i : std_logic;
- signal C_SDIB_i : std_logic;
- signal C_SDO_i : std_logic;
- signal C_SDOB_i : std_logic;
- signal C_CSB_i : std_logic;
- signal C_CS_i : std_logic;
- signal D_SCK_i : std_logic;
- signal D_SCKB_i : std_logic;
- signal D_SDI_i : std_logic;
- signal D_SDIB_i : std_logic;
- signal D_SDO_i : std_logic;
- signal D_SDOB_i : std_logic;
- signal D_CSB_i : std_logic;
- signal D_CS_i : std_logic;
- signal A_TEST1_i : std_logic;
- signal A_TEST1B_i : std_logic;
- signal A_TEST2_i : std_logic;
- signal A_TEST2B_i : std_logic;
- signal B_TEST1_i : std_logic;
- signal B_TEST1B_i : std_logic;
- signal B_TEST2_i : std_logic;
- signal B_TEST2B_i : std_logic;
- signal C_TEST1_i : std_logic;
- signal C_TEST1B_i : std_logic;
- signal C_TEST2_i : std_logic;
- signal C_TEST2B_i : std_logic;
- signal D_TEST1_i : std_logic;
- signal D_TEST1B_i : std_logic;
- signal D_TEST2_i : std_logic;
- signal D_TEST2B_i : std_logic;
- signal DSPADDR_i : std_logic_vector (31 downto 0);
- signal DSPDAT_i : std_logic_vector (31 downto 0);
- signal DSP_ACK_i : std_logic;
- signal DSP_BM_i : std_logic;
- signal DSP_BMS_i : std_logic;
- signal DSP_BOFF_i : std_logic;
- signal DSP_BRST_i : std_logic;
- signal DSP_HBG_i : std_logic;
- signal DSP_HBR_i : std_logic;
- signal DSP_IRQ_i : std_logic_vector (3 downto 0);
- signal DSP_RD_i : std_logic;
- signal DSP_RESET_i : std_logic;
- signal DSP_RESET_OUT_i : std_logic;
- signal DSP_WRH_i : std_logic;
- signal DSP_WRL_i : std_logic;
- signal VSD_A_i : std_logic_vector (12 downto 0);
- signal VSD_BA_i : std_logic_vector (1 downto 0);
- signal VSD_CAS_i : std_logic;
- signal VSD_CKE_i : std_logic;
- signal VSD_CLOCK_i : std_logic;
- signal VSD_CSEH_i : std_logic;
- signal VSD_CSEL_i : std_logic;
- signal VSD_D_i : std_logic_vector (31 downto 0);
- signal VSD_DQML_i : std_logic_vector (3 downto 0);
- signal VSD_RAS_i : std_logic;
- signal VSD_WE_i : std_logic;
+ signal A_TDC_BU_RESET_0 : std_logic;
+ signal A_TDC_BU_RESETB_0 : std_logic;
+ signal A_TDC_EV_RESET_0 : std_logic;
+ signal A_TDC_EV_RESETB_0 : std_logic;
+ signal B_TDC_BU_RESET_0 : std_logic;
+ signal B_TDC_BU_RESETB_0 : std_logic;
+ signal B_TDC_EV_RESET_0 : std_logic;
+ signal B_TDC_EV_RESETB_0 : std_logic;
+ signal C_TDC_BU_RESET_0 : std_logic;
+ signal C_TDC_BU_RESETB_0 : std_logic;
+ signal C_TDC_EV_RESET_0 : std_logic;
+ signal C_TDC_EV_RESETB_0 : std_logic;
+ signal D_TDC_BU_RESET_0 : std_logic;
+ signal D_TDC_BU_RESETB_0 : std_logic;
+ signal D_TDC_EV_RESET_0 : std_logic;
+ signal D_TDC_EV_RESETB_0 : std_logic;
+ signal TDC_OUT_0 : std_logic_vector (31 downto 0);
+ signal TDC_RESET_0 : std_logic;
+ signal A_TRIGGER_0 : std_logic;
+ signal A_TRIGGERB_0 : std_logic;
+ signal B_TRIGGER_0 : std_logic;
+ signal B_TRIGGERB_0 : std_logic;
+ signal C_TRIGGER_0 : std_logic;
+ signal C_TRIGGERB_0 : std_logic;
+ signal D_TRIGGER_0 : std_logic;
+ signal D_TRIGGERB_0 : std_logic;
+ signal FS_PB_0 : std_logic_vector (17 downto 0);
+ signal FS_PC_0 : std_logic_vector (17 downto 0);
+ signal ETRAX_IRQ_0 : std_logic;
+ signal A_SCK_0 : std_logic;
+ signal A_SCKB_0 : std_logic;
+ signal A_SDI_0 : std_logic;
+ signal A_SDIB_0 : std_logic;
+ signal A_SDO_0 : std_logic;
+ signal A_SDOB_0 : std_logic;
+ signal A_CSB_0 : std_logic;
+ signal A_CS_0 : std_logic;
+ signal B_SCK_0 : std_logic;
+ signal B_SCKB_0 : std_logic;
+ signal B_SDI_0 : std_logic;
+ signal B_SDIB_0 : std_logic;
+ signal B_SDO_0 : std_logic;
+ signal B_SDOB_0 : std_logic;
+ signal B_CSB_0 : std_logic;
+ signal B_CS_0 : std_logic;
+ signal C_SCK_0 : std_logic;
+ signal C_SCKB_0 : std_logic;
+ signal C_SDI_0 : std_logic;
+ signal C_SDIB_0 : std_logic;
+ signal C_SDO_0 : std_logic;
+ signal C_SDOB_0 : std_logic;
+ signal C_CSB_0 : std_logic;
+ signal C_CS_0 : std_logic;
+ signal D_SCK_0 : std_logic;
+ signal D_SCKB_0 : std_logic;
+ signal D_SDI_0 : std_logic;
+ signal D_SDIB_0 : std_logic;
+ signal D_SDO_0 : std_logic;
+ signal D_SDOB_0 : std_logic;
+ signal D_CSB_0 : std_logic;
+ signal D_CS_0 : std_logic;
+ signal A_TEST1_0 : std_logic;
+ signal A_TEST1B_0 : std_logic;
+ signal A_TEST2_0 : std_logic;
+ signal A_TEST2B_0 : std_logic;
+ signal B_TEST1_0 : std_logic;
+ signal B_TEST1B_0 : std_logic;
+ signal B_TEST2_0 : std_logic;
+ signal B_TEST2B_0 : std_logic;
+ signal C_TEST1_0 : std_logic;
+ signal C_TEST1B_0 : std_logic;
+ signal C_TEST2_0 : std_logic;
+ signal C_TEST2B_0 : std_logic;
+ signal D_TEST1_0 : std_logic;
+ signal D_TEST1B_0 : std_logic;
+ signal D_TEST2_0 : std_logic;
+ signal D_TEST2B_0 : std_logic;
+-- signal DSPADDR_0 : std_logic_vector (31 downto 0);
+-- signal DSPDAT_0 : std_logic_vector (31 downto 0);
+-- signal DSP_ACK_0 : std_logic;
+-- signal DSP_BM_0 : std_logic;
+-- signal DSP_BMS_0 : std_logic;
+-- signal DSP_BOFF_0 : std_logic;
+-- signal DSP_BRST_0 : std_logic;
+-- signal DSP_HBG_0 : std_logic;
+-- signal DSP_HBR_0 : std_logic;
+-- signal DSP_IRQ_0 : std_logic_vector (3 downto 0);
+-- signal DSP_RD_0 : std_logic;
+-- signal DSP_RESET_0 : std_logic;
+-- signal DSP_RESET_OUT_0 : std_logic;
+-- signal DSP_WRH_0 : std_logic;
+-- signal DSP_WRL_0 : std_logic;
+-- signal VSD_A_0 : std_logic_vector (12 downto 0);
+-- signal VSD_BA_0 : std_logic_vector (1 downto 0);
+-- signal VSD_CAS_0 : std_logic;
+-- signal VSD_CKE_0 : std_logic;
+-- signal VSD_CLOCK_0 : std_logic;
+-- signal VSD_CSEH_0 : std_logic;
+-- signal VSD_CSEL_0 : std_logic;
+-- signal VSD_D_0 : std_logic_vector (31 downto 0);
+-- signal VSD_DQML_0 : std_logic_vector (3 downto 0);
+-- signal VSD_RAS_0 : std_logic;
+-- signal VSD_WE_0 : std_logic;
signal TLK_CLK_i : std_logic;
- signal TLK_ENABLE_i : std_logic;
- signal TLK_LCKREFN_i : std_logic;
- signal TLK_LOOPEN_i : std_logic;
- signal TLK_PRBSEN_i : std_logic;
- signal TLK_RXD_i : std_logic_vector (15 downto 0);
+ signal TLK_ENABLE_0 : std_logic;
+ signal TLK_LCKREFN_0 : std_logic;
+ signal TLK_LOOPEN_0 : std_logic;
+ signal TLK_PRBSEN_0 : std_logic;
+ signal TLK_RXD_0 : std_logic_vector (15 downto 0);
signal TLK_RX_CLK_i : std_logic;
- signal TLK_RX_DV_i : std_logic;
- signal TLK_RX_ER_i : std_logic;
- signal TLK_TXD_i : std_logic_vector (15 downto 0);
- signal TLK_TX_EN_i : std_logic;
- signal TLK_TX_ER_i : std_logic;
- signal SFP_LOS_i : std_logic;
- signal SFP_TX_DIS_i : std_logic;
- signal SFP_TX_FAULT_i : std_logic;
- signal ADO_LV_i : std_logic_vector(51 downto 0);
+ signal TLK_RX_DV_0 : std_logic;
+ signal TLK_RX_ER_0 : std_logic;
+ signal TLK_TXD_0 : std_logic_vector (15 downto 0);
+ signal TLK_TX_EN_0 : std_logic;
+ signal TLK_TX_ER_0 : std_logic;
+ signal SFP_LOS_0 : std_logic;
+ signal SFP_TX_DIS_0 : std_logic;
+ signal SFP_TX_FAULT_0 : std_logic;
+ signal ADO_LV_0 : std_logic_vector(51 downto 0);
+ signal ADDON_TO_TRB_CLKINP_i : std_logic;
+ signal ADDON_TO_TRB_CLKINN_i : std_logic;
+ signal VIRT_TCK_0 : std_logic;
+ signal VIRT_TDI_0 : std_logic;
+ signal VIRT_TDO_0 : std_logic;
+ signal VIRT_TMS_0 : std_logic;
+ signal VIRT_TRST_0 : std_logic;
+ --trb_1
+ signal RESET_VIRT_1 : std_logic;
+
+ signal A_RESERVED_1 : std_logic;
+ signal A_TEMP_1 : std_logic;
+ signal B_RESERVED_1 : std_logic;
+ signal B_TEMP_1 : std_logic;
+ signal C_RESERVED_1 : std_logic;
+ signal C_TEMP_1 : std_logic;
+ signal D_RESERVED_1 : std_logic;
+ signal D_TEMP_1 : std_logic;
+ signal VIR_TRIG_1 : std_logic;
+ signal VIR_TRIGB_1 : std_logic;
+ signal A_TDC_ERROR_1 : std_logic;
+ signal B_TDC_ERROR_1 : std_logic;
+ signal C_TDC_ERROR_1 : std_logic;
+ signal D_TDC_ERROR_1 : std_logic;
+ signal A_TDC_POWERUP_1 : std_logic;
+ signal B_TDC_POWERUP_1 : std_logic;
+ signal C_TDC_POWERUP_1 : std_logic;
+ signal D_TDC_POWERUP_1 : std_logic;
+ signal TOKEN_IN_1 : std_logic;
+ signal TOKEN_OUT_1 : std_logic;
+ signal C_TOKEN_OUT_TTL_1 : std_logic;
+ signal GET_DATA_1 : std_logic;
+ signal A_DATA_READY_1 : std_logic;
+ signal B_DATA_READY_1 : std_logic;
+ signal C_DATA_READY_1 : std_logic;
+ signal D_DATA_READY_1 : std_logic;
+-- signal REF_TDC_CLK_i : std_logic;
+-- signal REF_TDC_CLKB_i : std_logic;
+ signal A_TDC_BU_RESET_1 : std_logic;
+ signal A_TDC_BU_RESETB_1 : std_logic;
+ signal A_TDC_EV_RESET_1 : std_logic;
+ signal A_TDC_EV_RESETB_1 : std_logic;
+ signal B_TDC_BU_RESET_1 : std_logic;
+ signal B_TDC_BU_RESETB_1 : std_logic;
+ signal B_TDC_EV_RESET_1 : std_logic;
+ signal B_TDC_EV_RESETB_1 : std_logic;
+ signal C_TDC_BU_RESET_1 : std_logic;
+ signal C_TDC_BU_RESETB_1 : std_logic;
+ signal C_TDC_EV_RESET_1 : std_logic;
+ signal C_TDC_EV_RESETB_1 : std_logic;
+ signal D_TDC_BU_RESET_1 : std_logic;
+ signal D_TDC_BU_RESETB_1 : std_logic;
+ signal D_TDC_EV_RESET_1 : std_logic;
+ signal D_TDC_EV_RESETB_1 : std_logic;
+ signal TDC_OUT_1 : std_logic_vector (31 downto 0);
+ signal TDC_RESET_1 : std_logic;
+ signal A_TRIGGER_1 : std_logic;
+ signal A_TRIGGERB_1 : std_logic;
+ signal B_TRIGGER_1 : std_logic;
+ signal B_TRIGGERB_1 : std_logic;
+ signal C_TRIGGER_1 : std_logic;
+ signal C_TRIGGERB_1 : std_logic;
+ signal D_TRIGGER_1 : std_logic;
+ signal D_TRIGGERB_1 : std_logic;
+ signal FS_PB_1 : std_logic_vector (17 downto 0);
+ signal FS_PC_1 : std_logic_vector (17 downto 0);
+ signal ETRAX_IRQ_1 : std_logic;
+ signal A_SCK_1 : std_logic;
+ signal A_SCKB_1 : std_logic;
+ signal A_SDI_1 : std_logic;
+ signal A_SDIB_1 : std_logic;
+ signal A_SDO_1 : std_logic;
+ signal A_SDOB_1 : std_logic;
+ signal A_CSB_1 : std_logic;
+ signal A_CS_1 : std_logic;
+ signal B_SCK_1 : std_logic;
+ signal B_SCKB_1 : std_logic;
+ signal B_SDI_1 : std_logic;
+ signal B_SDIB_1 : std_logic;
+ signal B_SDO_1 : std_logic;
+ signal B_SDOB_1 : std_logic;
+ signal B_CSB_1 : std_logic;
+ signal B_CS_1 : std_logic;
+ signal C_SCK_1 : std_logic;
+ signal C_SCKB_1 : std_logic;
+ signal C_SDI_1 : std_logic;
+ signal C_SDIB_1 : std_logic;
+ signal C_SDO_1 : std_logic;
+ signal C_SDOB_1 : std_logic;
+ signal C_CSB_1 : std_logic;
+ signal C_CS_1 : std_logic;
+ signal D_SCK_1 : std_logic;
+ signal D_SCKB_1 : std_logic;
+ signal D_SDI_1 : std_logic;
+ signal D_SDIB_1 : std_logic;
+ signal D_SDO_1 : std_logic;
+ signal D_SDOB_1 : std_logic;
+ signal D_CSB_1 : std_logic;
+ signal D_CS_1 : std_logic;
+ signal A_TEST1_1 : std_logic;
+ signal A_TEST1B_1 : std_logic;
+ signal A_TEST2_1 : std_logic;
+ signal A_TEST2B_1 : std_logic;
+ signal B_TEST1_1 : std_logic;
+ signal B_TEST1B_1 : std_logic;
+ signal B_TEST2_1 : std_logic;
+ signal B_TEST2B_1 : std_logic;
+ signal C_TEST1_1 : std_logic;
+ signal C_TEST1B_1 : std_logic;
+ signal C_TEST2_1 : std_logic;
+ signal C_TEST2B_1 : std_logic;
+ signal D_TEST1_1 : std_logic;
+ signal D_TEST1B_1 : std_logic;
+ signal D_TEST2_1 : std_logic;
+ signal D_TEST2B_1 : std_logic;
+-- signal DSPADDR_1 : std_logic_vector (31 downto 0);
+-- signal DSPDAT_1 : std_logic_vector (31 downto 0);
+-- signal DSP_ACK_1 : std_logic;
+-- signal DSP_BM_1 : std_logic;
+-- signal DSP_BMS_1 : std_logic;
+-- signal DSP_BOFF_1 : std_logic;
+-- signal DSP_BRST_1 : std_logic;
+-- signal DSP_HBG_1 : std_logic;
+-- signal DSP_HBR_1 : std_logic;
+-- signal DSP_IRQ_1 : std_logic_vector (3 downto 0);
+-- signal DSP_RD_1 : std_logic;
+-- signal DSP_RESET_1 : std_logic;
+-- signal DSP_RESET_OUT_1 : std_logic;
+-- signal DSP_WRH_1 : std_logic;
+-- signal DSP_WRL_1 : std_logic;
+-- signal VSD_A_1 : std_logic_vector (12 downto 0);
+-- signal VSD_BA_1 : std_logic_vector (1 downto 0);
+-- signal VSD_CAS_1 : std_logic;
+-- signal VSD_CKE_1 : std_logic;
+-- signal VSD_CLOCK_1 : std_logic;
+-- signal VSD_CSEH_1 : std_logic;
+-- signal VSD_CSEL_1 : std_logic;
+-- signal VSD_D_1 : std_logic_vector (31 downto 0);
+-- signal VSD_DQML_1 : std_logic_vector (3 downto 0);
+-- signal VSD_RAS_1 : std_logic;
+-- signal VSD_WE_1 : std_logic;
+-- signal TLK_CLK_1 : std_logic;
+ signal TLK_ENABLE_1 : std_logic;
+ signal TLK_LCKREFN_1 : std_logic;
+ signal TLK_LOOPEN_1 : std_logic;
+ signal TLK_PRBSEN_1 : std_logic;
+ signal TLK_RXD_1 : std_logic_vector (15 downto 0);
+-- signal TLK_RX_CLK_1 : std_logic;
+ signal TLK_RX_DV_1 : std_logic;
+ signal TLK_RX_ER_1 : std_logic;
+ signal TLK_TXD_1 : std_logic_vector (15 downto 0);
+ signal TLK_TX_EN_1 : std_logic;
+ signal TLK_TX_ER_1 : std_logic;
+ signal SFP_LOS_1 : std_logic;
+ signal SFP_TX_DIS_1 : std_logic;
+ signal SFP_TX_FAULT_1 : std_logic;
+ signal ADO_LV_1 : std_logic_vector(51 downto 0);
+ signal ADDON_TO_TRB_CLKINP_1 : std_logic;
+ signal ADDON_TO_TRB_CLKINN_1 : std_logic;
+ signal VIRT_TCK_1 : std_logic;
+ signal VIRT_TDI_1 : std_logic;
+ signal VIRT_TDO_1 : std_logic;
+ signal VIRT_TMS_1 : std_logic;
+ signal VIRT_TRST_1 : std_logic;
- signal VIRT_TCK_i : std_logic;
- signal VIRT_TDI_i : std_logic;
- signal VIRT_TDO_i : std_logic;
- signal VIRT_TMS_i : std_logic;
- signal VIRT_TRST_i : std_logic;
-
+ --cts
signal FS_PB_CTS_i : std_logic_vector (17 downto 0);
signal FS_PC_CTS_i : std_logic_vector (17 downto 0);
signal TLK_CLK_CTS_i : std_logic;
signal ADO_CLK1_i : std_logic;
signal ADO_CLK2_i : std_logic;
signal ADO_LV_CTS_i : std_logic_vector(51 downto 0);
- signal ADO_TTL_CTS_i : std_logic_vector(46 downto 2);
+ signal ADO_TTL_CTS_i : std_logic_vector(45 downto 0);
+ --local
signal vulom_lvl1_tag : std_logic_vector(15 downto 0);
signal test_synch_00 : std_logic;
+ signal dtu_clk : std_logic;
+ signal dtu_lvl2_tag : std_logic_vector(7 downto 0);
+ signal lvl2_trig : std_logic;
+ signal tdc_data_i : std_logic_vector(31 downto 0):=(others => '0');
+
begin
HUB_INST: hub
port map (
OPT_DATA_OUT => OPT_DATA_OUT_i,
OPT_DATA_VALID_IN => OPT_DATA_VALID_IN_i,
OPT_DATA_VALID_OUT => OPT_DATA_VALID_OUT_i);
- TRB_INST: trb_v2b_fpga
+ TRB_INST_0: trb_v2b_fpga
port map (
VIRT_CLK => VIRT_CLK_i,
VIRT_CLKB => VIRT_CLKB_i,
DGOOD => DGOOD_i,
DINT => DINT_i,
DWAIT => DWAIT_i,
- A_RESERVED => A_RESERVED_i,
- A_TEMP => A_TEMP_i,
- B_RESERVED => B_RESERVED_i,
- B_TEMP => B_TEMP_i,
- C_RESERVED => C_RESERVED_i,
- C_TEMP => C_TEMP_i,
- D_RESERVED => D_RESERVED_i,
- D_TEMP => D_TEMP_i,
- VIR_TRIG => VIR_TRIG_i,
- VIR_TRIGB => VIR_TRIGB_i,
- A_TDC_ERROR => A_TDC_ERROR_i,
- B_TDC_ERROR => B_TDC_ERROR_i,
- C_TDC_ERROR => C_TDC_ERROR_i,
- D_TDC_ERROR => D_TDC_ERROR_i,
- A_TDC_POWERUP => A_TDC_POWERUP_i,
- B_TDC_POWERUP => B_TDC_POWERUP_i,
- C_TDC_POWERUP => C_TDC_POWERUP_i,
- D_TDC_POWERUP => D_TDC_POWERUP_i,
- TOKEN_IN => TOKEN_IN_i,
- TOKEN_OUT => TOKEN_OUT_i,
- C_TOKEN_OUT_TTL => C_TOKEN_OUT_TTL_i,
- GET_DATA => GET_DATA_i,
- A_DATA_READY => A_DATA_READY_i,
- B_DATA_READY => B_DATA_READY_i,
- C_DATA_READY => C_DATA_READY_i,
- D_DATA_READY => D_DATA_READY_i,
+ A_RESERVED => A_RESERVED_0,
+ A_TEMP => A_TEMP_0,
+ B_RESERVED => B_RESERVED_0,
+ B_TEMP => B_TEMP_0,
+ C_RESERVED => C_RESERVED_0,
+ C_TEMP => C_TEMP_0,
+ D_RESERVED => D_RESERVED_0,
+ D_TEMP => D_TEMP_0,
+ VIR_TRIG => VIR_TRIG_0,
+ VIR_TRIGB => VIR_TRIGB_0,
+ A_TDC_ERROR => A_TDC_ERROR_0,
+ B_TDC_ERROR => B_TDC_ERROR_0,
+ C_TDC_ERROR => C_TDC_ERROR_0,
+ D_TDC_ERROR => D_TDC_ERROR_0,
+ A_TDC_POWERUP => A_TDC_POWERUP_0,
+ B_TDC_POWERUP => B_TDC_POWERUP_0,
+ C_TDC_POWERUP => C_TDC_POWERUP_0,
+ D_TDC_POWERUP => D_TDC_POWERUP_0,
+ TOKEN_IN => TOKEN_IN_0,
+ TOKEN_OUT => TOKEN_OUT_0,
+ C_TOKEN_OUT_TTL => C_TOKEN_OUT_TTL_0,
+ GET_DATA => GET_DATA_0,
+ A_DATA_READY => A_DATA_READY_0,
+ B_DATA_READY => B_DATA_READY_0,
+ C_DATA_READY => C_DATA_READY_0,
+ D_DATA_READY => D_DATA_READY_0,
REF_TDC_CLK => REF_TDC_CLK_i,
REF_TDC_CLKB => REF_TDC_CLKB_i,
- A_TDC_BU_RESET => A_TDC_BU_RESET_i,
- A_TDC_BU_RESETB => A_TDC_BU_RESETB_i,
- A_TDC_EV_RESET => A_TDC_EV_RESET_i,
- A_TDC_EV_RESETB => A_TDC_EV_RESETB_i,
- B_TDC_BU_RESET => B_TDC_BU_RESET_i,
- B_TDC_BU_RESETB => B_TDC_BU_RESETB_i,
- B_TDC_EV_RESET => B_TDC_EV_RESET_i,
- B_TDC_EV_RESETB => B_TDC_EV_RESETB_i,
- C_TDC_BU_RESET => C_TDC_BU_RESET_i,
- C_TDC_BU_RESETB => C_TDC_BU_RESETB_i,
- C_TDC_EV_RESET => C_TDC_EV_RESET_i,
- C_TDC_EV_RESETB => C_TDC_EV_RESETB_i,
- D_TDC_BU_RESET => D_TDC_BU_RESET_i,
- D_TDC_BU_RESETB => D_TDC_BU_RESETB_i,
- D_TDC_EV_RESET => D_TDC_EV_RESET_i,
- D_TDC_EV_RESETB => D_TDC_EV_RESETB_i,
- TDC_OUT => TDC_OUT_i,
- TDC_RESET => TDC_RESET_i,
- A_TRIGGER => A_TRIGGER_i,
- A_TRIGGERB => A_TRIGGERB_i,
- B_TRIGGER => B_TRIGGER_i,
- B_TRIGGERB => B_TRIGGERB_i,
- C_TRIGGER => C_TRIGGER_i,
- C_TRIGGERB => C_TRIGGERB_i,
- D_TRIGGER => D_TRIGGER_i,
- D_TRIGGERB => D_TRIGGERB_i,
- FS_PB => FS_PB_i,
- FS_PC => FS_PC_i,
- ETRAX_IRQ => ETRAX_IRQ_i,
- A_SCK => A_SCK_i,
- A_SCKB => A_SCKB_i,
- A_SDI => A_SDI_i,
- A_SDIB => A_SDIB_i,
- A_SDO => A_SDO_i,
- A_SDOB => A_SDOB_i,
- A_CSB => A_CSB_i,
- A_CS => A_CS_i,
- B_SCK => B_SCK_i,
- B_SCKB => B_SCKB_i,
- B_SDI => B_SDI_i,
- B_SDIB => B_SDIB_i,
- B_SDO => B_SDO_i,
- B_SDOB => B_SDOB_i,
- B_CSB => B_CSB_i,
- B_CS => B_CS_i,
- C_SCK => C_SCK_i,
- C_SCKB => C_SCKB_i,
- C_SDI => C_SDI_i,
- C_SDIB => C_SDIB_i,
- C_SDO => C_SDO_i,
- C_SDOB => C_SDOB_i,
- C_CSB => C_CSB_i,
- C_CS => C_CS_i,
- D_SCK => D_SCK_i,
- D_SCKB => D_SCKB_i,
- D_SDI => D_SDI_i,
- D_SDIB => D_SDIB_i,
- D_SDO => D_SDO_i,
- D_SDOB => D_SDOB_i,
- D_CSB => D_CSB_i,
- D_CS => D_CS_i,
- A_TEST1 => A_TEST1_i,
- A_TEST1B => A_TEST1B_i,
- A_TEST2 => A_TEST2_i,
- A_TEST2B => A_TEST2B_i,
- B_TEST1 => B_TEST1_i,
- B_TEST1B => B_TEST1B_i,
- B_TEST2 => B_TEST2_i,
- B_TEST2B => B_TEST2B_i,
- C_TEST1 => C_TEST1_i,
- C_TEST1B => C_TEST1B_i,
- C_TEST2 => C_TEST2_i,
- C_TEST2B => C_TEST2B_i,
- D_TEST1 => D_TEST1_i,
- D_TEST1B => D_TEST1B_i,
- D_TEST2 => D_TEST2_i,
- D_TEST2B => D_TEST2B_i,
- DSPADDR => DSPADDR_i,
- DSPDAT => DSPDAT_i,
- DSP_ACK => DSP_ACK_i,
- DSP_BM => DSP_BM_i,
- DSP_BMS => DSP_BMS_i,
- DSP_BOFF => DSP_BOFF_i,
- DSP_BRST => DSP_BRST_i,
- DSP_HBG => DSP_HBG_i,
- DSP_HBR => DSP_HBR_i,
- DSP_IRQ => DSP_IRQ_i,
- DSP_RD => DSP_RD_i,
- DSP_RESET => DSP_RESET_i,
- DSP_RESET_OUT => DSP_RESET_OUT_i,
- DSP_WRH => DSP_WRH_i,
- DSP_WRL => DSP_WRL_i,
- VSD_A => VSD_A_i,
- VSD_BA => VSD_BA_i,
- VSD_CAS => VSD_CAS_i,
- VSD_CKE => VSD_CKE_i,
- VSD_CLOCK => VSD_CLOCK_i,
- VSD_CSEH => VSD_CSEH_i,
- VSD_CSEL => VSD_CSEL_i,
- VSD_D => VSD_D_i,
- VSD_DQML => VSD_DQML_i,
- VSD_RAS => VSD_RAS_i,
- VSD_WE => VSD_WE_i,
+ A_TDC_BU_RESET => A_TDC_BU_RESET_0,
+ A_TDC_BU_RESETB => A_TDC_BU_RESETB_0,
+ A_TDC_EV_RESET => A_TDC_EV_RESET_0,
+ A_TDC_EV_RESETB => A_TDC_EV_RESETB_0,
+ B_TDC_BU_RESET => B_TDC_BU_RESET_0,
+ B_TDC_BU_RESETB => B_TDC_BU_RESETB_0,
+ B_TDC_EV_RESET => B_TDC_EV_RESET_0,
+ B_TDC_EV_RESETB => B_TDC_EV_RESETB_0,
+ C_TDC_BU_RESET => C_TDC_BU_RESET_0,
+ C_TDC_BU_RESETB => C_TDC_BU_RESETB_0,
+ C_TDC_EV_RESET => C_TDC_EV_RESET_0,
+ C_TDC_EV_RESETB => C_TDC_EV_RESETB_0,
+ D_TDC_BU_RESET => D_TDC_BU_RESET_0,
+ D_TDC_BU_RESETB => D_TDC_BU_RESETB_0,
+ D_TDC_EV_RESET => D_TDC_EV_RESET_0,
+ D_TDC_EV_RESETB => D_TDC_EV_RESETB_0,
+ TDC_OUT => TDC_OUT_0,
+ TDC_RESET => TDC_RESET_0,
+ A_TRIGGER => A_TRIGGER_0,
+ A_TRIGGERB => A_TRIGGERB_0,
+ B_TRIGGER => B_TRIGGER_0,
+ B_TRIGGERB => B_TRIGGERB_0,
+ C_TRIGGER => C_TRIGGER_0,
+ C_TRIGGERB => C_TRIGGERB_0,
+ D_TRIGGER => D_TRIGGER_0,
+ D_TRIGGERB => D_TRIGGERB_0,
+ FS_PB => FS_PB_0,
+ FS_PC => FS_PC_0,
+ ETRAX_IRQ => ETRAX_IRQ_0,
+ A_SCK => A_SCK_0,
+ A_SCKB => A_SCKB_0,
+ A_SDI => A_SDI_0,
+ A_SDIB => A_SDIB_0,
+ A_SDO => A_SDO_0,
+ A_SDOB => A_SDOB_0,
+ A_CSB => A_CSB_0,
+ A_CS => A_CS_0,
+ B_SCK => B_SCK_0,
+ B_SCKB => B_SCKB_0,
+ B_SDI => B_SDI_0,
+ B_SDIB => B_SDIB_0,
+ B_SDO => B_SDO_0,
+ B_SDOB => B_SDOB_0,
+ B_CSB => B_CSB_0,
+ B_CS => B_CS_0,
+ C_SCK => C_SCK_0,
+ C_SCKB => C_SCKB_0,
+ C_SDI => C_SDI_0,
+ C_SDIB => C_SDIB_0,
+ C_SDO => C_SDO_0,
+ C_SDOB => C_SDOB_0,
+ C_CSB => C_CSB_0,
+ C_CS => C_CS_0,
+ D_SCK => D_SCK_0,
+ D_SCKB => D_SCKB_0,
+ D_SDI => D_SDI_0,
+ D_SDIB => D_SDIB_0,
+ D_SDO => D_SDO_0,
+ D_SDOB => D_SDOB_0,
+ D_CSB => D_CSB_0,
+ D_CS => D_CS_0,
+ A_TEST1 => A_TEST1_0,
+ A_TEST1B => A_TEST1B_0,
+ A_TEST2 => A_TEST2_0,
+ A_TEST2B => A_TEST2B_0,
+ B_TEST1 => B_TEST1_0,
+ B_TEST1B => B_TEST1B_0,
+ B_TEST2 => B_TEST2_0,
+ B_TEST2B => B_TEST2B_0,
+ C_TEST1 => C_TEST1_0,
+ C_TEST1B => C_TEST1B_0,
+ C_TEST2 => C_TEST2_0,
+ C_TEST2B => C_TEST2B_0,
+ D_TEST1 => D_TEST1_0,
+ D_TEST1B => D_TEST1B_0,
+ D_TEST2 => D_TEST2_0,
+ D_TEST2B => D_TEST2B_0,
+-- DSPADDR => DSPADDR_0,
+-- DSPDAT => DSPDAT_0,
+-- DSP_ACK => DSP_ACK_0,
+-- DSP_BM => DSP_BM_0,
+-- DSP_BMS => DSP_BMS_0,
+-- DSP_BOFF => DSP_BOFF_0,
+-- DSP_BRST => DSP_BRST_0,
+-- DSP_HBG => DSP_HBG_0,
+-- DSP_HBR => DSP_HBR_0,
+-- DSP_IRQ => DSP_IRQ_0,
+-- DSP_RD => DSP_RD_0,
+-- DSP_RESET => DSP_RESET_0,
+-- DSP_RESET_OUT => DSP_RESET_OUT_0,
+-- DSP_WRH => DSP_WRH_0,
+-- DSP_WRL => DSP_WRL_0,
+-- VSD_A => VSD_A_0,
+-- VSD_BA => VSD_BA_0,
+-- VSD_CAS => VSD_CAS_0,
+-- VSD_CKE => VSD_CKE_0,
+-- VSD_CLOCK => VSD_CLOCK_0,
+-- VSD_CSEH => VSD_CSEH_0,
+-- VSD_CSEL => VSD_CSEL_0,
+-- VSD_D => VSD_D_0,
+-- VSD_DQML => VSD_DQML_0,
+-- VSD_RAS => VSD_RAS_0,
+-- VSD_WE => VSD_WE_0,
TLK_CLK => TLK_CLK_i,
- TLK_ENABLE => TLK_ENABLE_i,
- TLK_LCKREFN => TLK_LCKREFN_i,
- TLK_LOOPEN => TLK_LOOPEN_i,
- TLK_PRBSEN => TLK_PRBSEN_i,
+ TLK_ENABLE => TLK_ENABLE_0,
+ TLK_LCKREFN => TLK_LCKREFN_0,
+ TLK_LOOPEN => TLK_LOOPEN_0,
+ TLK_PRBSEN => TLK_PRBSEN_0,
TLK_RXD => OPT_DATA_OUT_i(31 downto 16), --TLK_RXD_i,
TLK_RX_CLK => TLK_RX_CLK_i,
TLK_RX_DV => OPT_DATA_VALID_OUT_i(1),--TLK_RX_DV_i,
TLK_RX_ER => '0',--TLK_RX_ER_i,
TLK_TXD => OPT_DATA_IN_i(31 downto 16),-- TLK_TXD_i,
TLK_TX_EN => OPT_DATA_VALID_IN_i(1),--TLK_TX_EN_i,
- TLK_TX_ER => TLK_TX_ER_i,
- SFP_LOS => SFP_LOS_i,
- SFP_TX_DIS => SFP_TX_DIS_i,
- SFP_TX_FAULT => SFP_TX_FAULT_i,
- ADO_LV => ADO_LV_i,
- ADO_TTL => open,--ADO_TTL_i,
- VIRT_TCK => VIRT_TCK_i,
- VIRT_TDI => VIRT_TDI_i,
- VIRT_TDO => VIRT_TDO_i,
- VIRT_TMS => VIRT_TMS_i,
- VIRT_TRST => VIRT_TRST_i);
+ TLK_TX_ER => TLK_TX_ER_0,
+ SFP_LOS => SFP_LOS_0,
+ SFP_TX_DIS => SFP_TX_DIS_0,
+ SFP_TX_FAULT => SFP_TX_FAULT_0,
+ ADDON_TO_TRB_CLKINN => ADDON_TO_TRB_CLKINN_i,
+ ADDON_TO_TRB_CLKINP => ADDON_TO_TRB_CLKINP_i,
+ ADO_LV => ADO_LV_0,
+ ADO_TTL => open,--ADO_TTL_0,
+ VIRT_TCK => VIRT_TCK_0,
+ VIRT_TDI => VIRT_TDI_0,
+ VIRT_TDO => VIRT_TDO_0,
+ VIRT_TMS => VIRT_TMS_0,
+ VIRT_TRST => VIRT_TRST_0);
+ TRB_INST_1: trb_v2b_fpga
+ port map (
+ VIRT_CLK => VIRT_CLK_i,
+ VIRT_CLKB => VIRT_CLKB_i,
+ RESET_VIRT => '0',
+ DBAD => DBAD_i,
+ DGOOD => DGOOD_i,
+ DINT => DINT_i,
+ DWAIT => DWAIT_i,
+ A_RESERVED => A_RESERVED_1,
+ A_TEMP => A_TEMP_1,
+ B_RESERVED => B_RESERVED_1,
+ B_TEMP => B_TEMP_1,
+ C_RESERVED => C_RESERVED_1,
+ C_TEMP => C_TEMP_1,
+ D_RESERVED => D_RESERVED_1,
+ D_TEMP => D_TEMP_1,
+ VIR_TRIG => VIR_TRIG_1,
+ VIR_TRIGB => VIR_TRIGB_1,
+ A_TDC_ERROR => A_TDC_ERROR_1,
+ B_TDC_ERROR => B_TDC_ERROR_1,
+ C_TDC_ERROR => C_TDC_ERROR_1,
+ D_TDC_ERROR => D_TDC_ERROR_1,
+ A_TDC_POWERUP => A_TDC_POWERUP_1,
+ B_TDC_POWERUP => B_TDC_POWERUP_1,
+ C_TDC_POWERUP => C_TDC_POWERUP_1,
+ D_TDC_POWERUP => D_TDC_POWERUP_1,
+ TOKEN_IN => TOKEN_IN_1,
+ TOKEN_OUT => TOKEN_OUT_1,
+ C_TOKEN_OUT_TTL => C_TOKEN_OUT_TTL_1,
+ GET_DATA => GET_DATA_1,
+ A_DATA_READY => A_DATA_READY_1,
+ B_DATA_READY => B_DATA_READY_1,
+ C_DATA_READY => C_DATA_READY_1,
+ D_DATA_READY => D_DATA_READY_1,
+ REF_TDC_CLK => REF_TDC_CLK_i,
+ REF_TDC_CLKB => REF_TDC_CLKB_i,
+ A_TDC_BU_RESET => A_TDC_BU_RESET_1,
+ A_TDC_BU_RESETB => A_TDC_BU_RESETB_1,
+ A_TDC_EV_RESET => A_TDC_EV_RESET_1,
+ A_TDC_EV_RESETB => A_TDC_EV_RESETB_1,
+ B_TDC_BU_RESET => B_TDC_BU_RESET_1,
+ B_TDC_BU_RESETB => B_TDC_BU_RESETB_1,
+ B_TDC_EV_RESET => B_TDC_EV_RESET_1,
+ B_TDC_EV_RESETB => B_TDC_EV_RESETB_1,
+ C_TDC_BU_RESET => C_TDC_BU_RESET_1,
+ C_TDC_BU_RESETB => C_TDC_BU_RESETB_1,
+ C_TDC_EV_RESET => C_TDC_EV_RESET_1,
+ C_TDC_EV_RESETB => C_TDC_EV_RESETB_1,
+ D_TDC_BU_RESET => D_TDC_BU_RESET_1,
+ D_TDC_BU_RESETB => D_TDC_BU_RESETB_1,
+ D_TDC_EV_RESET => D_TDC_EV_RESET_1,
+ D_TDC_EV_RESETB => D_TDC_EV_RESETB_1,
+ TDC_OUT => TDC_OUT_1,
+ TDC_RESET => TDC_RESET_1,
+ A_TRIGGER => A_TRIGGER_1,
+ A_TRIGGERB => A_TRIGGERB_1,
+ B_TRIGGER => B_TRIGGER_1,
+ B_TRIGGERB => B_TRIGGERB_1,
+ C_TRIGGER => C_TRIGGER_1,
+ C_TRIGGERB => C_TRIGGERB_1,
+ D_TRIGGER => D_TRIGGER_1,
+ D_TRIGGERB => D_TRIGGERB_1,
+ FS_PB => FS_PB_1,
+ FS_PC => FS_PC_1,
+ ETRAX_IRQ => ETRAX_IRQ_1,
+ A_SCK => A_SCK_1,
+ A_SCKB => A_SCKB_1,
+ A_SDI => A_SDI_1,
+ A_SDIB => A_SDIB_1,
+ A_SDO => A_SDO_1,
+ A_SDOB => A_SDOB_1,
+ A_CSB => A_CSB_1,
+ A_CS => A_CS_1,
+ B_SCK => B_SCK_1,
+ B_SCKB => B_SCKB_1,
+ B_SDI => B_SDI_1,
+ B_SDIB => B_SDIB_1,
+ B_SDO => B_SDO_1,
+ B_SDOB => B_SDOB_1,
+ B_CSB => B_CSB_1,
+ B_CS => B_CS_1,
+ C_SCK => C_SCK_1,
+ C_SCKB => C_SCKB_1,
+ C_SDI => C_SDI_1,
+ C_SDIB => C_SDIB_1,
+ C_SDO => C_SDO_1,
+ C_SDOB => C_SDOB_1,
+ C_CSB => C_CSB_1,
+ C_CS => C_CS_1,
+ D_SCK => D_SCK_1,
+ D_SCKB => D_SCKB_1,
+ D_SDI => D_SDI_1,
+ D_SDIB => D_SDIB_1,
+ D_SDO => D_SDO_1,
+ D_SDOB => D_SDOB_1,
+ D_CSB => D_CSB_1,
+ D_CS => D_CS_1,
+ A_TEST1 => A_TEST1_1,
+ A_TEST1B => A_TEST1B_1,
+ A_TEST2 => A_TEST2_1,
+ A_TEST2B => A_TEST2B_1,
+ B_TEST1 => B_TEST1_1,
+ B_TEST1B => B_TEST1B_1,
+ B_TEST2 => B_TEST2_1,
+ B_TEST2B => B_TEST2B_1,
+ C_TEST1 => C_TEST1_1,
+ C_TEST1B => C_TEST1B_1,
+ C_TEST2 => C_TEST2_1,
+ C_TEST2B => C_TEST2B_1,
+ D_TEST1 => D_TEST1_1,
+ D_TEST1B => D_TEST1B_1,
+ D_TEST2 => D_TEST2_1,
+ D_TEST2B => D_TEST2B_1,
+-- DSPADDR => DSPADDR_1,
+-- DSPDAT => DSPDAT_1,
+-- DSP_ACK => DSP_ACK_1,
+-- DSP_BM => DSP_BM_1,
+-- DSP_BMS => DSP_BMS_1,
+-- DSP_BOFF => DSP_BOFF_1,
+-- DSP_BRST => DSP_BRST_1,
+-- DSP_HBG => DSP_HBG_1,
+-- DSP_HBR => DSP_HBR_1,
+-- DSP_IRQ => DSP_IRQ_1,
+-- DSP_RD => DSP_RD_1,
+-- DSP_RESET => DSP_RESET_1,
+-- DSP_RESET_OUT => DSP_RESET_OUT_1,
+-- DSP_WRH => DSP_WRH_1,
+-- DSP_WRL => DSP_WRL_1,
+-- VSD_A => VSD_A_1,
+-- VSD_BA => VSD_BA_1,
+-- VSD_CAS => VSD_CAS_1,
+-- VSD_CKE => VSD_CKE_1,
+-- VSD_CLOCK => VSD_CLOCK_1,
+-- VSD_CSEH => VSD_CSEH_1,
+-- VSD_CSEL => VSD_CSEL_1,
+-- VSD_D => VSD_D_1,
+-- VSD_DQML => VSD_DQML_1,
+-- VSD_RAS => VSD_RAS_1,
+-- VSD_WE => VSD_WE_1,
+ TLK_CLK => TLK_CLK_i,
+ TLK_ENABLE => TLK_ENABLE_1,
+ TLK_LCKREFN => TLK_LCKREFN_1,
+ TLK_LOOPEN => TLK_LOOPEN_1,
+ TLK_PRBSEN => TLK_PRBSEN_1,
+ TLK_RXD => OPT_DATA_OUT_i(47 downto 32), --TLK_RXD_i,
+ TLK_RX_CLK => TLK_RX_CLK_i,
+ TLK_RX_DV => OPT_DATA_VALID_OUT_i(2),--TLK_RX_DV_i,
+ TLK_RX_ER => '0',--TLK_RX_ER_i,
+ TLK_TXD => OPT_DATA_IN_i(47 downto 32),-- TLK_TXD_i,
+ TLK_TX_EN => OPT_DATA_VALID_IN_i(2),--TLK_TX_EN_i,
+ TLK_TX_ER => TLK_TX_ER_1,
+ SFP_LOS => SFP_LOS_1,
+ SFP_TX_DIS => SFP_TX_DIS_1,
+ SFP_TX_FAULT => SFP_TX_FAULT_1,
+ ADDON_TO_TRB_CLKINN => ADDON_TO_TRB_CLKINN_i,
+ ADDON_TO_TRB_CLKINP => ADDON_TO_TRB_CLKINP_i,
+ ADO_LV => ADO_LV_1,
+ ADO_TTL => open,--ADO_TTL_1,
+ VIRT_TCK => VIRT_TCK_1,
+ VIRT_TDI => VIRT_TDI_1,
+ VIRT_TDO => VIRT_TDO_1,
+ VIRT_TMS => VIRT_TMS_1,
+ VIRT_TRST => VIRT_TRST_1);
+
CTS_INST: cts
port map (
VIRT_CLK => VIRT_CLK_i,
TLK_RXD => OPT_DATA_OUT_i(15 downto 0),--TLK_RXD_i,
TLK_RX_CLK => TLK_RX_CLK_i,
TLK_RX_DV => OPT_DATA_VALID_OUT_i(0),--TLK_RX_DV_i,
- TLK_RX_ER => TLK_RX_ER_i,
+ TLK_RX_ER => TLK_RX_ER_CTS_i,
TLK_TXD => OPT_DATA_IN_i(15 downto 0),--TLK_TXD_i,
TLK_TX_EN => OPT_DATA_VALID_IN_i(0),--TLK_TX_EN_i,
TLK_TX_ER => open,--TLK_TX_ER_i,
- SFP_LOS => SFP_LOS_i,
+ SFP_LOS => SFP_LOS_CTS_i,
SFP_TX_DIS => open,--SFP_TX_DIS_i,
SFP_TX_FAULT => '0',--SFP_TX_FAULT_i,
- ADO_CLK1 => ADO_CLK1_i,
- ADO_CLK2 => ADO_CLK2_i,
+-- ADO_CLK => ADO_CLK1_i,
+ ADO_CLK => ADO_CLK2_i,
ADO_LV => (others => '0'),--ADO_LV_i,
ADO_TTL => ADO_TTL_i);
-----------------------------------------------------------------------------
- -- --------------------------------------------------------------------------
- -- CTS
+ -- clocks
-----------------------------------------------------------------------------
+ clock_tlk_clk : process
+ begin
+ TLK_CLK_i <= '0';
+ wait for 5 ns;
+ TLK_CLK_i <= '1';
+ wait for 5 ns;
+ end process;
+ clock_tlk_rx_clk : process
+ begin
+ TLK_RX_CLK_i <= '0';
+ wait for 5 ns;
+ TLK_RX_CLK_i <= '1';
+ wait for 5 ns;
+ end process;
+ clock_gclk : process
+ begin
+ VIRT_CLK_i <= '0';
+ VIRT_CLKB_i <= '1';
+ wait for 5 ns;
+ VIRT_CLK_i <= '1';
+ VIRT_CLKB_i <= '0';
+ wait for 5 ns;
+ end process;
+ clock_hub_clk : process
+ begin
+ LVDS_CLK_200P_i<= '0';
+ wait for 5 ns;
+ LVDS_CLK_200P_i <= '1';
+ wait for 5 ns;
+ end process;
+ clock_tdcclk : process
+ begin
+ wait for 12 ns;
+ loop
+ REF_TDC_CLK_i <= '0';
+ REF_TDC_CLKB_i <= '1';
+ wait for 12.5 ns;
+ REF_TDC_CLK_i <= '1';
+ REF_TDC_CLKB_i <= '0';
+ wait for 12.5 ns;
+ end loop;
+ end process;
+ ----------------------------------------------------------------------------
+ -- CTS
-----------------------------------------------------------------------------
+
-----------------------------------------------------------------------------
-- vulom to cts
-----------------------------------------------------------------------------
-
ADO_TTL_i(4) <= 'Z';
VULOM_SENDS_TRIGGER: process
variable i,y : integer;
begin
vulom_lvl1_tag <= (others => '0');
+ ADO_CLK2_i <= '0';
+ ADO_TTL_i(3 downto 2) <= "00";
wait for 310 ns;
loop
y := 0;
- ADO_TTL_i(3 downto 2) <= "01";
+ wait on VIRT_CLK_i until ADO_TTL_i(7) = '0';
+ ADO_TTL_i(42 downto 41) <= "01";
+ ADO_CLK2_i <= '1';
+ wait for 10 ns;
+ ADO_CLK2_i <= '0';
+ wait for 10 ns;
+ ADO_TTL_i(42 downto 41) <= "10";
+ ADO_CLK2_i <= '1';
+ wait for 10 ns;
+ ADO_CLK2_i <= '0';
+ wait for 10 ns;
+ ADO_TTL_i(42 downto 41) <= "01";
+ ADO_CLK2_i <= '1';
+ wait for 10 ns;
+ ADO_CLK2_i <= '0';
+ wait for 10 ns;
+ ADO_TTL_i(42 downto 41) <= "10";
+ ADO_CLK2_i <= '1';
+ wait for 10 ns;
+ ADO_CLK2_i <= '0';
+ wait for 10 ns;
+ ADO_TTL_i(42 downto 41) <= "10";
ADO_CLK2_i <= '1';
wait for 10 ns;
ADO_CLK2_i <= '0';
wait for 10 ns;
for i in 0 to 159 loop
- ADO_TTL_i(3 downto 2) <= vulom_lvl1_tag (((y mod 15)+1) downto (y mod 15));
+ ADO_TTL_i(42 downto 41) <= vulom_lvl1_tag (((y mod 15)+1) downto (y mod 15));
ADO_CLK2_i <= '1';
wait for 10 ns;
ADO_CLK2_i <= '0';
wait for 10 ns;
y := y + 2;
end loop; -- 40ns;
- wait on VIRT_CLK_i until ADO_TTL_i(4) = '0';
+ wait on VIRT_CLK_i until ADO_TTL_i(34) = '1';
+ wait on VIRT_CLK_i until ADO_TTL_i(34) = '0';
vulom_lvl1_tag <= vulom_lvl1_tag + 1;
end loop;
end process VULOM_SENDS_TRIGGER;
- clock_gclk : process
- begin
- VIRT_CLK_i <= '0';
- VIRT_CLKB_i <= '1';
- wait for 5 ns;
- VIRT_CLKB_i <= '0';
- VIRT_CLK_i <= '1';
- wait for 5 ns;
- end process;
- clock_tlk_clk : process
- begin
- TLK_CLK_i <= '0';
- wait for 5 ns;
- TLK_CLK_i <= '1';
- wait for 5 ns;
- end process;
- clock_tlk_rx_clk : process
+-------------------------------------------------------------------------------
+-- DTU only lvl2
+------------------------------------------------------------------------------
+ clock_dtu : process
begin
- TLK_RX_CLK_i <= '0';
- wait for 5 ns;
- TLK_RX_CLK_i <= '1';
- wait for 5 ns;
+ wait for 34 ns;
+ loop
+ dtu_clk <= '0';
+ wait for 50 ns;
+ dtu_clk <= '1';
+ wait for 50 ns;
+ end loop;
end process;
- etrax_interface : process
+ ADO_TTL_i(34) <= 'Z';
+ ADO_TTL_i(7) <= 'Z';
+ LVL2_COUNT : process
begin
-
- --reading DSP(dev number 1)
- wait for 10 ns;
- RESET_VIRT_i <= '0';
-
- wait for 10 ns;
- FS_PC_CTS_i(16) <= '1';
- FS_PC_CTS_i(17) <= '1';
- RESET_VIRT_i <= '1';
- wait for 10 ns;
-
- wait for 30 ns;
- FS_PC_CTS_i(15 downto 0) <= x"0000";
- FS_PC_CTS_i(16) <= '0';
- FS_PC_CTS_i(17) <= '0';
- wait on VIRT_CLK_i until FS_PB_CTS_i(16) = '0';
- wait for 20 ns;
- FS_PC_CTS_i(16) <= '1';
- wait for 20 ns;
- FS_PC_CTS_i(15) <= '1'; --read mode(1)
- FS_PC_CTS_i(14 downto 8) <= (others => '0');
- FS_PC_CTS_i(7 downto 0) <= x"00"; --device
- FS_PC_CTS_i(16) <= '0';
- FS_PC_CTS_i(17) <= '0';
- wait for 20 ns;
- FS_PC_CTS_i(15 downto 0) <= x"0000"; --address upper part
- FS_PC_CTS_i(16) <= '1';
- FS_PC_CTS_i(17) <= '0';
- wait for 20 ns;
- FS_PC_CTS_i(16) <= '0';
- wait for 20 ns;
- FS_PC_CTS_i(16) <= '1';
- FS_PC_CTS_i(15 downto 0) <= x"0025"; --adrees lower part
- FS_PC_CTS_i(16) <= '1';
- FS_PC_CTS_i(17) <= '0';
- wait for 20 ns;
- FS_PC_CTS_i(16) <= '0';
- wait on VIRT_CLK_i until FS_PB_CTS_i(16) = '1';
- FS_PC_CTS_i(16) <= '1';
- wait for 20 ns;
- FS_PC_CTS_i(16) <= '0';
- wait on VIRT_CLK_i until FS_PB_CTS_i(16) = '0';
- FS_PC_CTS_i(16) <= '1';
- wait for 20 ns;
- FS_PC_CTS_i(16) <= '0';
- wait on VIRT_CLK_i until FS_PB_CTS_i(16) = '1';
- FS_PC_CTS_i(16) <= '1';
- wait for 20 ns;
- FS_PC_CTS_i(16) <= '0';
- --writing DSP
- wait for 20 ns;
- FS_PC_CTS_i(16) <= '1';
- wait for 20 ns;
- FS_PC_CTS_i(15) <= '0'; --write mode
- FS_PC_CTS_i(14 downto 8) <= (others => '0');
- FS_PC_CTS_i(7 downto 0) <= x"00"; --device
- FS_PC_CTS_i(16) <= '0';
- FS_PC_CTS_i(17) <= '0';
- wait for 20 ns;
- FS_PC_CTS_i(15 downto 0) <= x"0000"; --address upper part
- FS_PC_CTS_i(16) <= '1';
- FS_PC_CTS_i(17) <= '0';
- wait for 20 ns;
- FS_PC_CTS_i(16) <= '0';
- wait for 20 ns;
- FS_PC_CTS_i(16) <= '1';
- FS_PC_CTS_i(15 downto 0) <= x"0000"; --adrees lower part
- FS_PC_CTS_i(16) <= '1';
- FS_PC_CTS_i(17) <= '0';
- wait for 20 ns;
- FS_PC_CTS_i(16) <= '0';
- wait for 20 ns;
- FS_PC_CTS_i(15 downto 0) <= x"0000"; --data upper part
- FS_PC_CTS_i(16) <= '1';
- FS_PC_CTS_i(17) <= '0';
- wait for 20 ns;
- FS_PC_CTS_i(16) <= '0';
- wait for 20 ns;
- FS_PC_CTS_i(15 downto 0) <= x"0080"; --data lower part - 1 switch on
- --internal generation of trigger
- FS_PC_CTS_i(16) <= '1';
- FS_PC_CTS_i(17) <= '0';
- wait for 20 ns;
- FS_PC_CTS_i(16) <= '0';
- wait for 20 ns;
- FS_PC_CTS_i(16) <= '1';
- wait for 20 ns;
- FS_PC_CTS_i(16) <= '0';
--- wait on VIRT_CLK_i until FS_PB_CTS_i(16)= '1';
+ wait for 100 ns;
+ dtu_lvl2_tag <= x"00";
+ wait on dtu_clk until ADO_TTL_i(8) = '0';
loop
- wait on VIRT_CLK_i until FS_PB_CTS_i(16) = '1';
- FS_PC_CTS_i(17) <= '1';
- wait for 100 ns;
- FS_PC_CTS_i(17) <= '0';
- wait for 100 ns;
+ wait on dtu_clk until lvl2_trig = '1';
+ wait for 500 ns;
+ dtu_lvl2_tag <= dtu_lvl2_tag +1;
+ wait on dtu_clk until ADO_TTL_i(8) = '0';
end loop;
- wait; -- will wait forever
- end process;
-
--------------------------------------------------------------------------------
--- trb
--------------------------------------------------------------------------------
- etrax_intf : process
+ end process LVL2_COUNT;
+-- ADO_TTL_i(9) <= lvl2_trig;
+ DTU_EMULATION_LVL2 : process
begin
-
- --reading DSP(dev number 1)
- wait for 10 ns;
- RESET_VIRT_i <= '0';
-
- wait for 10 ns;
- FS_PC_i(16) <= '1';
- FS_PC_i(17) <= '1';
- RESET_VIRT_i <= '1';
- wait for 10 ns;
-
+ ADO_TTL_i(9) <= '0';
+ ADO_TTL_i(13 downto 10) <= x"1";
+ lvl2_trig <= '0';
+ wait for 4000 ns;
+ loop
+ for number_of_normal_triggers in 0 to 9 loop
+ ADO_TTL_i(9) <= '0';
+ wait on VIRT_CLK_i until ADO_TTL_i(7) = '1'; --after lvl1
+ -- -- wait on dtu_clk until dtu_lvl1_tag > dtu_lvl2_tag + 1;
+-- wait on VIRT_CLK_i until ADO_TTL_i(7) = '0'; --after lvl1
+ wait for 3000 ns;
+ wait on VIRT_CLK_i until ADO_TTL_i(15) = '0';
+-- wait for 6000 ns;
+ ADO_TTL_i(13 downto 10) <= x"1";
+ ADO_TTL_i(8) <= '1';
+ wait for 100 ns;
+ ADO_TTL_i(8) <= '0';
+ ADO_TTL_i(13 downto 10) <= dtu_lvl2_tag(3 downto 0);
+ lvl2_trig <= '1';
+ wait for 100 ns;
+ ADO_TTL_i(9) <= '1';
+ lvl2_trig <= '0';
+ wait for 100 ns;
+ ADO_TTL_i(9) <= '0';
+ ADO_TTL_i(13 downto 10) <= dtu_lvl2_tag(7 downto 4);
+ wait for 100 ns;
+ ADO_TTL_i(9) <= '1';
+ wait for 100 ns;
+ ADO_TTL_i(9) <= '0';
+ wait for 100 ns;
+ ADO_TTL_i(9) <= '1';
+ wait for 100 ns;
+ ADO_TTL_i(9) <= '0';
+ end loop; -- number_of_normal_triggers
+ ADO_TTL_i(9) <= '0';
+ wait on VIRT_CLK_i until ADO_TTL_i(7) = '1'; --after lvl1
+ -- -- wait on dtu_clk until dtu_lvl1_tag > dtu_lvl2_tag + 1;
+-- wait on VIRT_CLK_i until ADO_TTL_i(7) = '0'; --after lvl1
+ wait for 3000 ns;
+ wait on VIRT_CLK_i until ADO_TTL_i(15) = '0';
+-- wait for 6000 ns;
+ ADO_TTL_i(13 downto 10) <= x"9";
+ ADO_TTL_i(8) <= '1';
+ wait for 100 ns;
+ ADO_TTL_i(8) <= '0';
+ lvl2_trig <= '1';
+ ADO_TTL_i(13 downto 10) <= dtu_lvl2_tag(3 downto 0);
+ wait for 100 ns;
+ lvl2_trig <= '0';
+ wait for 100 ns;
+ ADO_TTL_i(9) <= '1';
+ wait for 100 ns;
+ ADO_TTL_i(9) <= '0';
+ ADO_TTL_i(13 downto 10) <= dtu_lvl2_tag(7 downto 4);
+ wait for 100 ns;
+ ADO_TTL_i(9) <= '1';
+ wait for 100 ns;
+ ADO_TTL_i(9) <= '0';
+ wait for 100 ns;
+ ADO_TTL_i(9) <= '1';
+ wait for 100 ns;
+ ADO_TTL_i(9) <= '0';
+ end loop;
+ end process DTU_EMULATION_LVL2;
+
+ -----------------------------------------------------------------------------
+ -- etrax trb_0
+ -----------------------------------------------------------------------------
+ ETRAX_BUSY_0: process
+ variable etrax_busy_time : integer :=0;
+ begin -- process ETRAX_BUSY
+ FS_PB_0(17) <= '0';
+ wait on VIRT_CLK_i until FS_PB_0(16) ='1';
+ wait for 30 ns;
+ FS_PB_0(17) <= '1';
+ wait for 80 ns;
+ wait for ((etrax_busy_time mod 7 )*5+20)*ns;
+ etrax_busy_time := etrax_busy_time*3/2 +1;
+ end process ETRAX_BUSY_0;
+ -----------------------------------------------------------------------------
+ -- etrax trb_1
+ -----------------------------------------------------------------------------
+ ETRAX_BUSY_1: process
+ variable etrax_busy_time : integer :=0;
+ begin -- process ETRAX_BUSY
+ FS_PB_1(17) <= '0';
+ wait on VIRT_CLK_i until FS_PB_1(16) ='1';
wait for 30 ns;
- -- FS_PC_i(16) <= '0';
- -- FS_PC_i(17) <= '0';
- -- wait for 10 ns;
- FS_PC_i(15 downto 0) <= x"0000";
- FS_PC_i(16) <= '0';
- FS_PC_i(17) <= '0';
- wait on VIRT_CLK_i until FS_PB_i(16) = '0';
- wait for 20 ns;
- FS_PC_i(16) <= '1';
- wait for 20 ns;
- FS_PC_i(15) <= '1'; --read mode(1)
- FS_PC_i(14 downto 8) <= (others => '0');
- FS_PC_i(7 downto 0) <= x"00"; --device
- FS_PC_i(16) <= '0';
- FS_PC_i(17) <= '0';
- wait for 20 ns;
- FS_PC_i(15 downto 0) <= x"0000"; --address upper part
- FS_PC_i(16) <= '1';
- FS_PC_i(17) <= '0';
- wait for 20 ns;
- FS_PC_i(16) <= '0';
- wait for 20 ns;
- FS_PC_i(16) <= '1';
- FS_PC_i(15 downto 0) <= x"0025"; --adrees lower part
- FS_PC_i(16) <= '1';
- FS_PC_i(17) <= '0';
- wait for 20 ns;
- FS_PC_i(16) <= '0';
- wait on VIRT_CLK_i until FS_PB_i(16) = '1';
- FS_PC_i(16) <= '1';
- wait for 20 ns;
- FS_PC_i(16) <= '0';
- wait on VIRT_CLK_i until FS_PB_i(16) = '0';
- FS_PC_i(16) <= '1';
- wait for 20 ns;
- FS_PC_i(16) <= '0';
- wait on VIRT_CLK_i until FS_PB_i(16) = '1';
- FS_PC_i(16) <= '1';
- wait for 20 ns;
- FS_PC_i(16) <= '0';
- --writing DSP
- wait for 20 ns;
- FS_PC_i(16) <= '1';
- test_synch_00 <= '1';
- wait for 20 ns;
- FS_PC_i(15) <= '0'; --write mode
- FS_PC_i(14 downto 8) <= (others => '0');
- FS_PC_i(7 downto 0) <= x"00"; --device
- FS_PC_i(16) <= '0';
- FS_PC_i(17) <= '0';
- wait for 20 ns;
- FS_PC_i(15 downto 0) <= x"0000"; --address upper part
- FS_PC_i(16) <= '1';
- FS_PC_i(17) <= '0';
- wait for 20 ns;
- FS_PC_i(16) <= '0';
- wait for 20 ns;
- FS_PC_i(16) <= '1';
- FS_PC_i(15 downto 0) <= x"0006"; --adrees lower part
- FS_PC_i(16) <= '1';
- FS_PC_i(17) <= '0';
- wait for 20 ns;
- FS_PC_i(16) <= '0';
- wait for 20 ns;
- FS_PC_i(15 downto 0) <= x"0004"; --data upper part
- FS_PC_i(16) <= '1';
- FS_PC_i(17) <= '0';
- wait for 20 ns;
- FS_PC_i(16) <= '0';
- wait for 20 ns;
- FS_PC_i(15 downto 0) <= x"0000"; --data lower part - 1 switch on
- --internal generation of trigger
- FS_PC_i(16) <= '1';
- FS_PC_i(17) <= '0';
- wait for 20 ns;
- FS_PC_i(16) <= '0';
- wait for 20 ns;
- test_synch_00 <= '0';
- FS_PC_i(16) <= '1';
- wait for 20 ns;
- FS_PC_i(16) <= '0';
- FS_PC_i(15 downto 0) <= (others => 'Z');
--- wait on VIRT_CLK until FS_PB_i(16)= '1';
+ FS_PB_1(17) <= '1';
+ wait for 80 ns;
+ wait for ((etrax_busy_time mod 9 )*5+20)*ns;
+ etrax_busy_time := etrax_busy_time*3/2 +1;
+ end process ETRAX_BUSY_1;
+-- etrax_intf_trb0 : PROCESS
+-- BEGIN
+-- loop
+-- wait on VIRT_CLK_i until FS_PB_0(16) = '1';
+-- wait for 50 ns;
+-- FS_PB_0(17) <= '1';
+-- wait for 50 ns;
+-- FS_PB_0(17) <= '0';
+-- wait for 50 ns;
+-- end loop;
+-- wait; -- will wait forever
+-- end process;
+ -----------------------------------------------------------------------------
+ -- etrax cts
+ -----------------------------------------------------------------------------
+ etrax_intf_cts : PROCESS
+ BEGIN
loop
- wait on VIRT_CLK_i until FS_PB_i(16) = '1';
- FS_PC_i(17) <= '1';
+ wait on VIRT_CLK_i until FS_PB_CTS_i(16) = '1';
+ wait for 50 ns;
+ FS_PB_CTS_i(17) <= '1';
wait for 50 ns;
- FS_PC_i(17) <= '0';
+ FS_PB_CTS_i(17) <= '0';
wait for 50 ns;
end loop;
-
- wait; -- will wait forever
+ wait; -- will wait forever
end process;
+ -----------------------------------------------------------------------
+ -- TDC_trb_0
+ -----------------------------------------------------------------------
+ TDC_OUT_0 <= tdc_data_i;--x"00000000";--tdc_data_i;
+ TDC_DATA_CHANGE_0: process(REF_TDC_CLK_i, RESET_VIRT_0)
+ begin
+ if rising_edge(REF_TDC_CLK_i) then
+ if RESET_VIRT_0 = '1' then
+ tdc_data_i <= x"00000000";
+ else
+ tdc_data_i <= tdc_data_i + 1;
+ end if;
+ end if;
+ end process TDC_DATA_CHANGE_0;
+
+
+ trigger_lvl1_0 : process
+ variable valid_time : integer :=0;
+ begin
+-- ADO_TTL(7) <= '0';
+ A_DATA_READY_0 <= '0';
+ B_DATA_READY_0 <= '0';
+ C_DATA_READY_0 <= '0';
+ D_DATA_READY_0 <= '0';
+ TOKEN_IN_0 <= '0';
+ -- A_TEMP <= '0';
+-- wait for 50 ns;
+-- A_TEMP <= '1';
+-- wait for 10 ns;
+-- A_TEMP <= '0';
+-- wait for 10 ns;
+ wait on REF_TDC_CLK_i until TOKEN_OUT_0 = '1';
+ wait on REF_TDC_CLK_i until TOKEN_OUT_0 = '0';
+ wait for 10 ns;
+-- ADO_TTL(7) <= '0';
+ A_DATA_READY_0 <= '1';
+-- wait for 50 ns;
+ wait for ((valid_time mod 3)*50*3+2*25)*ns;
+ A_DATA_READY_0 <= '0';
+ B_DATA_READY_0 <= '1';
+-- wait for 50 ns;
+ wait for ((valid_time mod 5 )*50*2+2*25)*ns;
+ B_DATA_READY_0 <= '0';
+ C_DATA_READY_0 <= '1';
+-- wait for 50 ns;
+ wait for ((valid_time mod 7 )*50+2*25)*ns;
+-- ADO_TTL(7) <= '0';
+ C_DATA_READY_0 <= '0';
+ D_DATA_READY_0 <= '1';
+ --wait for 50 ns;
+ wait for ((valid_time mod 9 )*50+2*25)*ns;
+ D_DATA_READY_0 <= '0';
+ wait for 0 ns;
+-- ADO_TTL(6) <= '1';
+ TOKEN_IN_0 <= '1';
+ wait for 25 ns;
+-- ADO_TTL(6) <= '0';
+ TOKEN_IN_0 <= '0';
+ -- wait on REF_TDC_CLK until DBAD = '0';
+ valid_time := valid_time*3/2 +1;
+ end process;
-----------------------------------------------------------------------
- -- TDC
+ -- TDC_trb_1
-----------------------------------------------------------------------
- clock_tdcclk : process
- begin
- wait for 12 ns;
- loop
- REF_TDC_CLK_i <= '0';
- REF_TDC_CLKB_i <= '1';
- wait for 12.5 ns;
- REF_TDC_CLK_i <= '1';
- REF_TDC_CLKB_i <= '0';
- wait for 12.5 ns;
- end loop;
- end process;
- trigger_lvl1 : process
- begin
--- ADO_TTL(7) <= '0';
- A_DATA_READY_i <= '0';
- B_DATA_READY_i <= '0';
- C_DATA_READY_i <= '0';
- D_DATA_READY_i <= '0';
- TOKEN_IN_i <= '0';
- TDC_OUT_i <= x"bedebabe";
--- A_TEMP <= '0';
--- wait for 50 ns;
--- A_TEMP <= '1';
--- wait for 10 ns;
--- A_TEMP <= '0';
--- wait for 10 ns;
- wait on REF_TDC_CLK_i until TOKEN_OUT_i = '1';
- wait on REF_TDC_CLK_i until TOKEN_OUT_i = '0';
- wait for 10 ns;
--- ADO_TTL(7) <= '0';
- A_DATA_READY_i <= '1';
- wait for 50 ns;
- A_DATA_READY_i <= '0';
- B_DATA_READY_i <= '1';
- wait for 50 ns;
- B_DATA_READY_i <= '0';
- C_DATA_READY_i <= '1';
- wait for 50 ns;
--- ADO_TTL(7) <= '0';
- C_DATA_READY_i <= '0';
- D_DATA_READY_i <= '1';
- wait for 50 ns;
- D_DATA_READY_i <= '0';
- wait for 0 ns;
--- ADO_TTL(6) <= '1';
- TOKEN_IN_i <= '1';
- wait for 25 ns;
--- ADO_TTL(6) <= '0';
- TOKEN_IN_i <= '0';
+ TDC_OUT_1 <= tdc_data_i;--x"00000000";--tdc_data_i;
+
+-- TDC_DATA_CHANGE: process(REF_TDC_CLK_i, RESET_VIRT_1)
+-- begin
+-- if rising_edge(REF_TDC_CLK_i) then
+-- if RESET_VIRT_1 = '1' then
+-- tdc_data_i <= x"00000000";
+-- else
+-- tdc_data_i <= tdc_data_i + 1;
+-- end if;
+-- end if;
+-- end process TDC_DATA_CHANGE;
+
+
+ trigger_lvl1_1 : process
+ variable valid_time : integer :=0;
+ begin
+-- ADO_TTL(7) <= '0';
+ A_DATA_READY_1 <= '0';
+ B_DATA_READY_1 <= '0';
+ C_DATA_READY_1 <= '0';
+ D_DATA_READY_1 <= '0';
+ TOKEN_IN_1 <= '0';
+ -- A_TEMP <= '0';
+-- wait for 50 ns;
+-- A_TEMP <= '1';
+-- wait for 10 ns;
+-- A_TEMP <= '0';
+-- wait for 10 ns;
+ wait on REF_TDC_CLK_i until TOKEN_OUT_1 = '1';
+ wait on REF_TDC_CLK_i until TOKEN_OUT_1 = '0';
+ wait for 10 ns;
+-- ADO_TTL(7) <= '0';
+ A_DATA_READY_1 <= '1';
+-- wait for 50 ns;
+ wait for ((valid_time mod 11)*50*3+2*25)*ns;
+ A_DATA_READY_1 <= '0';
+ B_DATA_READY_1 <= '1';
+-- wait for 50 ns;
+ wait for ((valid_time mod 3 )*50*2+2*25)*ns;
+ B_DATA_READY_1 <= '0';
+ C_DATA_READY_1 <= '1';
+-- wait for 50 ns;
+ wait for ((valid_time mod 5 )*50+2*25)*ns;
+-- ADO_TTL(7) <= '0';
+ C_DATA_READY_1 <= '0';
+ D_DATA_READY_1 <= '1';
+ --wait for 50 ns;
+ wait for ((valid_time mod 7 )*50+2*25)*ns;
+ D_DATA_READY_1 <= '0';
+ wait for 0 ns;
+-- ADO_TTL(6) <= '1';
+ TOKEN_IN_1 <= '1';
+ wait for 25 ns;
+-- ADO_TTL(6) <= '0';
+ TOKEN_IN_1 <= '0';
-- wait on REF_TDC_CLK until DBAD = '0';
- end process;
--- trigger_lvl2 : process
--- begin
--- B_TEMP <= '0';
--- C_TEMP <= '0';
--- wait until DBAD = '1';
--- wait until DBAD = '0';
--- wait for 30 ns;
--- wait on VIRT_CLK until DGOOD = '0';
--- B_TEMP <= '0';
--- C_TEMP <= '1';
--- wait for 30 ns;
--- end process;
+ valid_time := valid_time*3/2 +1;
+ end process;
+
+
end system;
TDC_READOUT_COMPLETED : out std_logic;
LVL1_TAG : in std_logic_vector(7 downto 0);
LVL1_CODE : in std_logic_vector(3 downto 0);
+ LVL2_TAG : in std_logic_vector(7 downto 0);
HOW_MANY_ADD_DATA : in std_logic_vector(7 downto 0);
COUNTER_a : in std_logic_vector(31 downto 0);
COUNTER_b : in std_logic_vector(31 downto 0);
TDC_START : out std_logic;
TRIGGER_WITHOUT_HADES : in std_logic;
TRIGGER_WITH_GEN_EN : in std_logic;
- TRIGGER_WITH_GEN : in std_logic
+ TRIGGER_WITH_GEN : in std_logic;
+ FIFO_RESET_ERR : out std_logic
);
end tdc_interface;
architecture tdc_interface of tdc_interface is
signal delay_qout : std_logic_vector(7 downto 0);
signal lvl1_trigger_pulse_start : std_logic;
signal lvl1_trigger_pulse_delay : std_logic;
+ signal fifo_reset_err_i : std_logic;
type DELAY_FSM_TRIGG is
(IDLE ,DELAY_1,DELAY_2);
signal delay_fsm_currentstate, delay_fsm_nextstate: DELAY_FSM_TRIGG;
(IDLE, SEND_LVL1_TRIGG_1, SEND_LVL1_TRIGG_2, SEND_LVL1_TRIGG_3, SEND_LVL1_TRIGG_4, WAIT_FOR_TOKEN, SAVE_ADD_DATA_1, SAVE_ADD_DATA_2, SAVE_ADD_DATA_3, SAVE_ADD_DATA_4, SEND_LVL2_TRIGG);
signal LVL1_START_fsm_currentstate, LVL1_START_fsm_nextstate : LVL1_START_FSM;
type LVL2_START_FSM is
- (IDLE, READOUT_WORD1, READOUT_WORD2 ,SAVE_EVENT_SIZE ,SEND_DATA1);
+ (IDLE, READOUT_WORD1, READOUT_WORD2 ,READOUT_WORD3 ,SAVE_EVENT_SIZE ,SEND_DATA1);
signal LVL2_START_fsm_currentstate, LVL2_START_fsm_nextstate : LVL2_START_FSM;
signal lvl1_busy_i : std_logic;
signal lvl1_busy_ff : std_logic;
signal tdc_ready_d_i : std_logic;
signal lvl1_fifo_rd_en_empty_pulse : std_logic;
signal lvl1_fifo_empty_not : std_logic;
+ signal lvl1_fifo_busy_counter : std_logic_vector(31 downto 0);
begin
READ_ADRESS_END_UP <= lvl2_busy_end_pulse; --here
TDC_REGISTER : process (CLK, RESET)
TDC_REGISTER_00(1) <= B_TDC_ERROR;
TDC_REGISTER_00(2) <= C_TDC_ERROR;
TDC_REGISTER_00(3) <= D_TDC_ERROR;
- TDC_REGISTER_00(13 downto 4) <= lvl1_buffer_counter(9 downto 0);
+ TDC_REGISTER_00(13 downto 4) <= lvl1_fifo_counter(9 downto 0);
TDC_REGISTER_00(14) <= lvl1_busy_i;
- TDC_REGISTER_00(15) <= lvl1_or_lvl2_is_busy;--lvl1_memory_busy_i;
+ TDC_REGISTER_00(15) <= lvl1_memory_busy_i;--lvl1_or_lvl2_is_busy;--lvl1_memory_busy_i;
TDC_REGISTER_00(30) <= lvl1_fifo_wr_en;
TDC_REGISTER_00(31) <= lvl2_busy_i;
- TDC_REGISTER_00(29 downto 16) <= lvl1_fifo_counter(13 downto 0);
+ TDC_REGISTER_00(29 downto 16) <= lvl1_fifo_busy_counter(13 downto 0);
TDC_REGISTER_01(26 downto 0) <= lvl2_debug & trigger_register_00_i(5 downto 2) & "00" & trigger_register_00_i(1 downto 0)& words_in_event(15 downto 0);
TDC_REGISTER_01(31 downto 27) <= (others => '0');
- TDC_REGISTER_02(31 downto 0) <= lvl1_buffer_out;--lvl1_fifo_out;
+ TDC_REGISTER_02(31 downto 0) <= LVL2_TAG & lvl1_buffer_out(23 downto 0);--lvl1_fifo_out;
-- TDC_REGISTER_03(31 downto 0) <= lvl1_fifo_out;
TDC_REGISTER_03(31 downto 0) <= x"0"& LVL1_CODE & LVL1_TAG & x"0" & lvl1_code_i & lvl1_tag_minus1;
TDC_REGISTER_04(31 downto 0) <= test_counter_3 & test_counter_2 & test_counter_1 & test_counter_0;
din => TDC_DATA_IN,
rd_clk => CLK,
rd_en => lvl1_buffer_rd_en,
- rst => RESET,
+ rst => RESET ,
wr_clk => TDC_CLK,
wr_en => lvl1_buffer_wr_en,
almost_empty => open,--almost_empty_i,
end process LVL2_START;
START_LVL2_FSM: process (LVL2_TRIGGER,LVL2_START_fsm_currentstate, LVL1_START_fsm_currentstate, how_many_words_in_event, lvl1_fifo_out, etrax_is_ready_to_read, lvl1_fifo_rd_en_empty_pulse)
begin
+ lvl2_busy_i <= '1';
lvl2_debug (2 downto 0) <= "000";
lvl1_fifo_rd_en_fsm <= '0';
tdc_data_valid_i_fsm <= '0';
LVL2_START_fsm_nextstate <= IDLE;
case (LVL2_START_fsm_currentstate) is
when IDLE =>
+ lvl2_busy_i <= '0';
lvl2_debug (2 downto 0) <= "001";
- lvl1_fifo_rd_en_fsm <= lvl1_fifo_rd_en_empty_pulse;--'0';
+ lvl1_fifo_rd_en_fsm <= '0';--lvl1_fifo_rd_en_empty_pulse;--'0';
tdc_data_valid_i_fsm <= '0';
-- if LVL1_START_fsm_currentstate = SEND_LVL2_TRIGG then
if LVL2_TRIGGER = '1' or (TRIGGER_WITH_GEN_EN ='1' and LVL1_START_fsm_currentstate = SEND_LVL2_TRIGG ) then
- LVL2_START_fsm_nextstate <= SAVE_EVENT_SIZE;--READOUT_WORD1;
+ LVL2_START_fsm_nextstate <= READOUT_WORD1;--SAVE_EVENT_SIZE;
else
LVL2_START_fsm_nextstate <= IDLE;
end if;
- when READOUT_WORD1 =>
- lvl2_debug (2 downto 0) <= "010";
- lvl1_fifo_rd_en_fsm <= '1';
- tdc_data_valid_i_fsm <= '0';
- LVL2_START_fsm_nextstate <= READOUT_WORD2;
- when READOUT_WORD2 =>
- lvl2_debug (2 downto 0) <= "011";
- lvl1_fifo_rd_en_fsm <= '0';
- tdc_data_valid_i_fsm <= '0';
- LVL2_START_fsm_nextstate <= SAVE_EVENT_SIZE;
+ when READOUT_WORD1 =>
+ lvl2_busy_i <= '1';
+ lvl2_debug (2 downto 0) <= "010";
+ lvl1_fifo_rd_en_fsm <= '0';
+ tdc_data_valid_i_fsm <= '0';
+ if lvl1_fifo_out(15 downto 0)= x"0000" or lvl1_fifo_out(31 downto 28) = x"3" then
+ LVL2_START_fsm_nextstate <= READOUT_WORD2;
+ else
+ LVL2_START_fsm_nextstate <= SAVE_EVENT_SIZE;
+ end if;
+ when READOUT_WORD2 =>
+ lvl2_busy_i <= '1';
+ lvl2_debug (2 downto 0) <= "011";
+ lvl1_fifo_rd_en_fsm <= '1';
+ tdc_data_valid_i_fsm <= '0';
+ LVL2_START_fsm_nextstate <= READOUT_WORD3;
+ when READOUT_WORD3 =>
+ lvl2_busy_i <= '1';
+ lvl2_debug (2 downto 0) <= "011";
+ lvl1_fifo_rd_en_fsm <= '0';
+ tdc_data_valid_i_fsm <= '0';
+ LVL2_START_fsm_nextstate <= SAVE_EVENT_SIZE;
when SAVE_EVENT_SIZE =>
+ lvl2_busy_i <= '1';
lvl2_debug (2 downto 0) <= "100";
lvl1_fifo_rd_en_fsm <= '0';
tdc_data_valid_i_fsm <= '0';
LVL2_START_fsm_nextstate <= SEND_DATA1;
when SEND_DATA1 =>
+ lvl2_busy_i <= '1';
lvl2_debug (2 downto 0) <= "101";
lvl1_fifo_rd_en_fsm <= ETRAX_IS_READY_TO_READ;
tdc_data_valid_i_fsm <= '1';
else
LVL2_START_fsm_nextstate <= SEND_DATA1;
end if;
+ when others =>
+ lvl2_busy_i <= '1';
+ LVL2_START_fsm_nextstate <= IDLE;
end case;
end process START_LVL2_FSM;
COUNT_DOWN_READOUT: process (CLK, RESET,how_many_words_in_event)
en_clk => '1',
signal_in => not_tdc_data_valid_i,
pulse => lvl2_busy_end_pulse);
- LVL2_BUSY_SET: process (CLK, RESET)
- begin
- if rising_edge(CLK) then
- if RESET = '1' or lvl2_busy_end_pulse = '1'then
- lvl2_busy_i <= '0';
- elsif LVL2_START_fsm_currentstate /= IDLE then
- lvl2_busy_i <= '1';
- end if;
- end if;
- end process LVL2_BUSY_SET;
+-- LVL2_BUSY_SET: process (CLK, RESET)
+-- begin
+-- if rising_edge(CLK) then
+-- if RESET = '1' or lvl2_busy_end_pulse = '1'then
+-- lvl2_busy_i <= '0';
+-- elsif LVL2_START_fsm_currentstate /= IDLE then
+-- lvl2_busy_i <= '1';
+-- end if;
+-- end if;
+-- end process LVL2_BUSY_SET;
LVL2_BUSY_START_PULSER : edge_to_pulse
port map (
clock => CLK,
en_clk => '1',
signal_in => lvl2_busy_i,
pulse => lvl2_busy_start_pulse);
- lvl1_memory_busy_i <= '1' when lvl1_fifo_counter(13) = '1' else '0';
+
--set
--to
--max
CLR => RESET,
QOUT => test_counter_3
);
+ SET_BUFFER_BUSY: process (CLK, RESET)
+ begin -- process SET_BUFFER_BUSY
+ if rising_edge(CLK) then
+ if RESET = '1' or (test_counter_3 = test_counter_1 and lvl1_memory_busy_i = '1') then --or test_counter_3 = test_counter_1 then -- asynchronous reset (active low)
+ lvl1_fifo_busy_counter <= (others => '0');
+ elsif lvl1_fifo_rd_en = '1' and lvl1_fifo_wr_en = '0' and lvl1_fifo_busy_counter > 0 then
+ lvl1_fifo_busy_counter <= lvl1_fifo_busy_counter -1;
+ elsif lvl1_fifo_rd_en = '0' and lvl1_fifo_wr_en = '1' then
+ lvl1_fifo_busy_counter <= lvl1_fifo_busy_counter +1;
+ elsif lvl1_fifo_rd_en = '1' and lvl1_fifo_wr_en = '1' then
+ lvl1_fifo_busy_counter <= lvl1_fifo_busy_counter;
+ else
+ lvl1_fifo_busy_counter <= lvl1_fifo_busy_counter;
+ end if;
+ end if;
+ end process SET_BUFFER_BUSY;
+ fifo_reset_err_i <= '1' when test_counter_3 = test_counter_1 and lvl1_memory_busy_i = '1' else '0';
+ -- lvl1_memory_busy_i <= '1' when lvl1_fifo_counter(13) = '1' else '0';
+ lvl1_memory_busy_i <= '1' when lvl1_fifo_busy_counter(13) = '1' and lvl1_fifo_busy_counter(12) = '1'else '0';
REGITERING_SIGNALS: process (CLK, RESET)
begin
if rising_edge(CLK) then -- rising clock edge
NOTE "CREATOR" "Xilinx iMPACT Software";
-NOTE "DATE" "2008/07/17";
+NOTE "DATE" "2008/08/11";
NOTE "STAPL_VERSION" "JESD71";
NOTE "ALG_VERSION" "1";
NOTE "DEVICE" "UNSPECIFIED";
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-@pW_VCg@@2x@ju_@Am@dYy@dG@V9s@F2_@Xe@@7y@tX@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@f106000
-0_0ecHBC0G0040000K40000830300m400008102Y00XG0W880G240e020C018JQGYW6C030G
-0010GG9039EO0G90000030O003Um05080HFO00blAT2F3HFO0O90WS7u100yF0
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@r100O00008IzhPZo0020G0000GX00000C0W
+0040000m80000010a001H0WG80G4408120K0106WGZnCOGI3C43G280G008K2auW100K2000
+0W1060W00000W10K0WHFO000KULr9yHFO00WbWS7_10
;
' // Loading device with a `jstart` instruction.
IRSCAN 10, $03cc
IF D <= 2500 THEN CALL ADJUST_SMALL_DELAY;
ENDPROC;
-CRC E36B;
+CRC 03E2;
# NET ADO_LV<59> LOC ="AP26";
# NET ADO_LV<60> LOC ="AJ27";
# NET ADO_LV<61> LOC ="AH27";
-# NET ADO_TTL<0> LOC ="AL11"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<1> LOC ="AL10"| IOSTANDARD = "LVTTL";
- NET ADO_CLK1 LOC ="AL11"| IOSTANDARD = "LVTTL";
- NET ADO_CLK2 LOC ="AL10"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<0> LOC ="AL11"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<1> LOC ="AL10"| IOSTANDARD = "LVTTL";
+
NET ADO_TTL<2> LOC ="AE11"| IOSTANDARD = "LVTTL";
NET ADO_TTL<3> LOC ="AF11"| IOSTANDARD = "LVTTL";
NET ADO_TTL<4> LOC ="AM12"| IOSTANDARD = "LVTTL";
NET ADO_TTL<43> LOC ="C28"| IOSTANDARD = "LVTTL";
NET ADO_TTL<44> LOC ="L26"| IOSTANDARD = "LVTTL";
NET ADO_TTL<45> LOC ="B32"| IOSTANDARD = "LVTTL";
- NET ADO_TTL<46> LOC ="B33"| IOSTANDARD = "LVTTL";
+ # NET ADO_TTL<46> LOC ="B33"| IOSTANDARD = "LVTTL";
+ # NET ADO_CLK1 LOC ="AL11"| IOSTANDARD = "LVTTL";
+ # NET ADO_CLK2 LOC ="AL10"| IOSTANDARD = "LVTTL";
+ NET ADO_CLK LOC ="B33"| IOSTANDARD = "LVTTL";
# NET A_CS1B LOC ="P9"| IOSTANDARD = "LVTTL";
# NET A_CS<1> LOC ="P10"| IOSTANDARD = "LVTTL";
# NET A_DATA_READY LOC ="B12"| IOSTANDARD = "LVTTL";
# OFFSET=IN 2.5 ns BEFORE "REF_TDC_CLK" HIGH;
NET "VIRT_CLK" TNM_NET =VIRT_CLK;
TIMESPEC TS_VIRT_CLK =PERIOD "VIRT_CLK" 9 ns;
-
-NET "ADO_CLK2" TNM_NET =ADO_CLK2;
-TIMESPEC TS_ADO_CLK2 =PERIOD "ADO_CLK2" 16 ns;
+ NET "TLK_CLK" TNM_NET =TLK_CLK;
+# TIMESPEC TS_TLK_CLK =PERIOD "TLK_CLK" 9 ns;
+ NET "TLK_RX_CLK" TNM_NET =TLK_RX_CLK;
+# TIMESPEC TS_TLK_RX_CLK =PERIOD "TLK_RX_CLK" 9 ns;
+
+
+NET "ADO_CLK" TNM_NET =ADO_CLK;
+TIMESPEC TS_ADO_CLK =PERIOD "ADO_CLK" 16 ns;
#NET "REF_TDC_CLK" TNM_NET = REF_TDC_CLK;
#TIMESPEC TS_REF_TDC_CLK = PERIOD "REF_TDC_CLK" 10 ns;
-------------------------------------------------------------------------
-- ADDON_TO_TRB_CLKINN : in std_logic;
-- ADDON_TO_TRB_CLKINP : in std_logic;
- ADO_CLK1 : in std_logic;
- ADO_CLK2 : in std_logic;
+-- ADO_CLK1 : in std_logic;
+-- ADO_CLK2 : in std_logic;
+ ADO_CLK : in std_logic;
ADO_LV : in std_logic_vector(51 downto 0); --lvds signal
- ADO_TTL : inout std_logic_vector(46 downto 2)
+ ADO_TTL : inout std_logic_vector(45 downto 0)
);
end cts;
architecture cts of cts is
LVL1_BUSY : out std_logic;
LVL2_START : in std_logic;
LVL2_CODE : in std_logic;
- LVL2_TRB_ACK : out std_logic;
+ LVL2_TRB_BUSY : out std_logic;
CTS_ETRAX_REGISTER_00 : out std_logic_vector(31 downto 0);
CTS_ETRAX_REGISTER_01 : out std_logic_vector(31 downto 0);
CTS_ETRAX_REGISTER_02 : out std_logic_vector(31 downto 0);
CTS_ETRAX_REGISTER_03 : out std_logic_vector(31 downto 0);
- CTS_ETRAX_REGISTER_04 : out std_logic_vector(31 downto 0));
+ CTS_ETRAX_REGISTER_04 : out std_logic_vector(31 downto 0);
+ CTS_ETRAX_REGISTER_05 : out std_logic_vector(31 downto 0));
end component;
component simpleupcounter_32bit
port (
signal lvl1_busy_i : std_logic;
signal data_valid_i : std_logic;
signal data_out_i : std_logic_vector(31 downto 0);
+ signal lvl1_vulom_busy : std_logic;
--ctu
signal dtu_debug_00_i : std_logic_vector(31 downto 0);
signal lvl2_trigger_i : std_logic;
signal current_state_send_lvl1_and_lvl2_trigg, next_state_send_lvl1_and_lvl2_trigg : send_lvl1_and_lvl2_trigg;
signal not_lvl2_busy_i : std_logic;
signal lvl1_cts_busy : std_logic;
+ signal lvl1_ack : std_logic;
+ signal not_lvl1_cts_busy : std_logic;
+ signal lvl1_cts_busy_end : std_logic;
signal lvl1_system_busy : std_logic;
+ signal not_lvl1_system_busy : std_logic;
+ signal lvl1_system_busy_end : std_logic;
+ signal lvl1_trb_ack_cts_saved : std_logic;
+ signal lvl1_trb_ack_system_saved : std_logic;
+ signal lvl1_trb_ack_i : std_logic;
+ signal lvl1_trb_ack_system : std_logic;
+ signal lvl1_trb_ack_cts : std_logic;
+ signal not_lvl1_busy_i : std_logic;
+
+ signal lvl2_system_busy : std_logic;
+ signal not_lvl2_system_busy : std_logic;
+ signal lvl2_system_busy_end : std_logic;
+ signal lvl2_cts_busy : std_logic;
+ signal not_lvl2_cts_busy : std_logic;
+ signal lvl2_cts_busy_end : std_logic;
+
+
signal lvl2_trb_ack_cts : std_logic;
signal lvl2_trb_ack_system : std_logic;
signal lvl2_trb_ack_cts_saved : std_logic;
signal lvl2_trb_ack_system_saved : std_logic;
+ signal opt_synch_stat_counter : std_logic_vector(31 downto 0);
+ signal opt_synch_stat : std_logic;
+ signal all_lvl2_finished : std_logic;
begin
------------------------------------------------------------------------------
-- LVDS signals
port map(
CE => '1',
CLR => '0',
- I => ADO_CLK2,
+ I => ADO_CLK,
O => ADDON_CLK2
);
-- ADD_LVDS
CLK => CLK,
DATA_CLK => ADDON_CLK2,
RESET => external_reset_i,
- DATA_IN => ADO_TTL(3 downto 2), --lvds_add_on_data (3 downto 0),
- BUSY => open, --lvds_add_on_data (4),
- ACK_TO_VULOM => ADO_TTL(5),
- ERR_TO_VULOM => ADO_TTL(6),
+ DATA_IN => ADO_TTL(42 downto 41), --lvds_add_on_data (3 downto 0),
+ BUSY => lvl1_vulom_busy,--open, --lvds_add_on_data (4),
+ ACK_TO_VULOM => open,--ADO_TTL(34),
+ ERR_TO_VULOM => ADO_TTL(33),
API_DATA => open,
- API_RUN_OUT => lvl1_busy_i,--apl_run_out_i,
+ API_RUN_OUT => lvl1_busy_i, --lvl1_cts_busy or lvl1_system_busy,--apl_run_out_i,
API_SHORT_TRANSFER => open,
API_DTYPE => lvl1_trigger_code_i,
API_SEND => apl_send_in_i,
EVENT_REGISTER_0b => counter_b_i,
EVENT_REGISTER_0c => counter_c_i,
START_READOUT => start_readout_i,
- LVL1_TRANSFER_BUSY => lvl1_busy_i
+ LVL1_TRANSFER_BUSY => lvl1_cts_busy --lvl1_cts_busy or lvl1_system_busy
);
--- ADO_TTL(3 downto 2) <= (others => 'Z');
+ ADO_TTL(42 downto 40) <= (others => 'Z');
+ ADO_TTL(34) <= '1';
+-- ADO_TTL(44) <= '0';
+-- ADO_TTL(32) <= '0';
+-- ADO_TTL(35) <= '0';
-- ADO_TTL(4) <= lvl1_busy_i;
-- ADO_TTL(15 downto 8) <= vulom_int_reg_00(7 downto 0);
--------------------------------------------------------------------------
-- dtu interface
--------------------------------------------------------------------------
+ DTU_INT: dtu_interface
+ port map (
+ CLK => CLK,
+ RESET => external_reset_i,
+ LVL1_TRIGGER_BUS => ADO_TTL(0),
+ LVL1_DATA_TRIGGER_BUS => ADO_TTL(1),
+ LVL1_DATA_BUS => ADO_TTL(5 downto 2),
+ LVL1_ERROR_BUS => open,
+ LVL1_BUSY_BUS => ADO_TTL(7),
+ LVL1_TRIGGER => lvl1_trigger_i,
+ LVL1_CODE => lvl1_trigger_code_i,
+ LVL1_TAG => lvl1_trigger_tag_i,
+ LVL1_BUSY => lvl1_busy_i,--'0',
+ LVL2_TRIGGER_BUS => ADO_TTL(8),
+ LVL2_DATA_TRIGGER_BUS => ADO_TTL(9),
+ LVL2_DATA_BUS => ADO_TTL(13 downto 10),
+ LVL2_ERROR_BUS => open,
+ LVL2_BUSY_BUS => ADO_TTL(15),
+ LVL2_TRIGGER => lvl2_trigger_i,
+ LVL2_CODE => lvl2_trigger_code_i,
+ LVL2_TAG => lvl2_trigger_tag_i,
+ LVL2_BUSY => lvl2_busy_i,
+ LVL2_TRB_ACK => lvl2_trb_ack_i,--lvl2_trb_ack_i,
+ DTU_DEBUG_00 => dtu_debug_00_i);
+ -- ADO_TTL(7) <= lvl1_busy_i;
+ ADO_TTL(5 downto 0) <= (others => 'Z');
+ ADO_TTL(13 downto 8) <= (others => 'Z');
+ ADO_TTL(34) <= '1';
+ ADO_TTL(33) <= '0';
-- DTU_INT: dtu_interface
-- port map (
-- CLK => CLK,
-- ADO_TTL(15 downto 4) <= (others => 'Z');
-- ADO_TTL(2) <= '0';
-- ADO_TTL(3) <= '0';
-SAVE_LVL2_ACK_SYSTEM: process (CLK, external_reset_i, lvl2_trb_ack_system, lvl2_trb_ack_i)
-begin -- process SAVE_LVL2_ACK_SYSTEM
- if rising_edge(CLK) then
- if external_reset_i = '1' or lvl2_trb_ack_i = '1' then -- asynchronous reset (active low)
- lvl2_trb_ack_system_saved <= '0';
- elsif lvl2_trb_ack_system = '1' then
- lvl2_trb_ack_system_saved <= '1';
- end if;
- end if;
-end process SAVE_LVL2_ACK_SYSTEM;
-SAVE_LVL2_ACK_CTS : process (CLK, external_reset_i, lvl2_trb_ack_cts, lvl2_trb_ack_i)
-begin -- process SAVE_LVL2_ACK_SYSTEM
- if rising_edge(CLK) then
- if external_reset_i = '1' or lvl2_trb_ack_i = '1' then -- asynchronous reset (active low)
- lvl2_trb_ack_cts_saved <= '0';
- elsif lvl2_trb_ack_cts = '1' then
- lvl2_trb_ack_cts_saved <= '1';
- end if;
- end if;
-end process SAVE_LVL2_ACK_CTS ;
-SET_LVL2_ACK: process (CLK, external_reset_i,lvl2_trb_ack_cts_saved,lvl2_trb_ack_system_saved, lvl2_trb_ack_i)
-begin
- if rising_edge(CLK) then
- if external_reset_i = '1' or lvl2_trb_ack_i = '1' then
- lvl2_trb_ack_i <= '0';
- elsif lvl2_trb_ack_cts_saved='1' and lvl2_trb_ack_system_saved ='1' then
- lvl2_trb_ack_i <= '1';
-
- end if;
- end if;
-end process SET_LVL2_ACK;
+ -- lvl1 busy
+ --system
+ not_lvl1_system_busy <= not lvl1_system_busy;
+ ACK_SYSTEM_LVL1_BUSY_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => not_lvl1_system_busy,
+ pulse => lvl1_system_busy_end);
+ SAVE_LVL1_ACK_SYSTEM: process (CLK, external_reset_i, lvl1_trb_ack_system, lvl1_trb_ack_i)
+ begin -- process SAVE_LVL1_ACK_SYSTEM
+ if rising_edge(CLK) then
+ if external_reset_i = '1' or lvl1_trb_ack_i = '1' then -- asynchronous reset (active low)
+ lvl1_trb_ack_system_saved <= '0';
+ elsif lvl1_system_busy_end = '1' then
+ lvl1_trb_ack_system_saved <= '1';
+ end if;
+ end if;
+ end process SAVE_LVL1_ACK_SYSTEM;
+ --cts
+ not_lvl1_cts_busy <= not lvl1_cts_busy;
+ ACK_CTS_LVL1_BUSY_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => not_lvl1_cts_busy,
+ pulse => lvl1_cts_busy_end);
+ SAVE_LVL1_ACK_CTS : process (CLK, external_reset_i, lvl1_trb_ack_cts, lvl1_trb_ack_i)
+ begin -- process SAVE_LVL1_ACK_SYSTEM
+ if rising_edge(CLK) then
+ if external_reset_i = '1' or lvl1_trb_ack_i = '1' then -- asynchronous reset (active low)
+ lvl1_trb_ack_cts_saved <= '0';
+ elsif lvl1_cts_busy_end = '1' then
+ lvl1_trb_ack_cts_saved <= '1';
+ end if;
+ end if;
+ end process SAVE_LVL1_ACK_CTS ;
+-- lvl1_busy_i <= lvl1_trb_ack_cts_saved; --or (lvl1_trb_ack_system_saved);
+-- not_lvl1_busy_i <= not lvl1_busy_i;
+ lvl1_ack <= lvl1_trb_ack_cts_saved and lvl1_trb_ack_system_saved; --or lvl1_trb_ack_system_saved
+ ACK_LVL1_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => lvl1_ack,
+ pulse => lvl1_trb_ack_i);
+ SEND_LVL1_BUSY: process (CLK, external_reset_i)
+ begin
+ if rising_edge(CLK) then
+ if external_reset_i = '1' or lvl1_trb_ack_i = '1' then -- asynchronous reset (active low)
+ lvl1_busy_i <= '0';
+ elsif apl_send_in_i = '1' then
+ lvl1_busy_i <= '1';
+ end if;
+ end if;
+ end process SEND_LVL1_BUSY;
+ -- lvl2 busy
+ --system
+ not_lvl2_system_busy <= not lvl2_system_busy;
+ ACK_SYSTEM_LVL2_BUSY_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => not_lvl2_system_busy,
+ pulse => lvl2_system_busy_end);
+ SAVE_LVL2_ACK_SYSTEM: process (CLK, external_reset_i, lvl2_trb_ack_system, lvl2_trb_ack_i)
+ begin -- process SAVE_LVL2_ACK_SYSTEM
+ if rising_edge(CLK) then
+ if external_reset_i = '1' or lvl2_trb_ack_i = '1' then -- asynchronous reset (active low)
+ lvl2_trb_ack_system_saved <= '0';
+ elsif lvl2_system_busy_end = '1' then
+ lvl2_trb_ack_system_saved <= '1';
+ end if;
+ end if;
+ end process SAVE_LVL2_ACK_SYSTEM;
+ --cts
+ not_lvl2_cts_busy <= not lvl2_cts_busy;
+ ACK_CTS_LVL2_BUSY_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => not_lvl2_cts_busy,
+ pulse => lvl2_cts_busy_end);
+
+ SAVE_LVL2_ACK_CTS : process (CLK, external_reset_i, lvl2_trb_ack_cts, lvl2_trb_ack_i)
+ begin -- process SAVE_LVL2_ACK_SYSTEM
+ if rising_edge(CLK) then
+ if external_reset_i = '1' or lvl2_trb_ack_i = '1' then -- asynchronous reset (active low)
+ lvl2_trb_ack_cts_saved <= '0';
+ elsif lvl2_cts_busy_end = '1' then
+ lvl2_trb_ack_cts_saved <= '1';
+ end if;
+ end if;
+ end process SAVE_LVL2_ACK_CTS ;
+ -- lvl2_busy_i <= lvl2_trb_ack_cts_saved; --or (lvl2_trb_ack_system_saved);
+ not_lvl2_busy_i <= lvl2_trb_ack_cts_saved and lvl2_trb_ack_system_saved; --or (lvl2_trb_ack_system_saved);;
+ ACK_LVL2_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => not_lvl2_busy_i,
+ pulse => lvl2_trb_ack_i);
+ SEND_LVL2_BUSY: process (CLK, external_reset_i)
+ begin
+ if rising_edge(CLK) then
+ if external_reset_i = '1' or lvl2_trb_ack_i = '1' then -- asynchronous reset (active low)
+ lvl2_busy_i <= '0';
+ elsif lvl2_trigger_i = '1' then
+ lvl2_busy_i <= '1';
+ end if;
+ end if;
+ end process SEND_LVL2_BUSY;
+-- SET_LVL2_ACK: process (CLK, external_reset_i,lvl2_trb_ack_cts_saved,lvl2_trb_ack_system_saved, lvl2_trb_ack_i)
+-- begin
+-- if rising_edge(CLK) then
+-- if external_reset_i = '1' or lvl2_trb_ack_i = '1' then
+-- lvl2_trb_ack_i <= '0';
+-- elsif lvl2_trb_ack_cts_saved ='1' then -- and lvl2_trb_ack_system_saved ='1' then
+-- lvl2_trb_ack_i <= '1';
+-- end if;
+-- end if;
+-- end process SET_LVL2_ACK;
DTU_INT: dtu_interface
port map (
CLK => CLK,
RESET => external_reset_i,
- LVL1_TRIGGER_BUS => '0',
- LVL1_DATA_TRIGGER_BUS => '0',
- LVL1_DATA_BUS => x"0",
+ LVL1_TRIGGER_BUS => ADO_TTL(0),
+ LVL1_DATA_TRIGGER_BUS => ADO_TTL(1),
+ LVL1_DATA_BUS => ADO_TTL(5 downto 2),
LVL1_ERROR_BUS => open,
- LVL1_BUSY_BUS => open,
+ LVL1_BUSY_BUS => ADO_TTL(7),
LVL1_TRIGGER => open,
LVL1_CODE => open,
LVL1_TAG => open,
- LVL1_BUSY => '0',
- LVL2_TRIGGER_BUS => ADO_TTL(10),
- LVL2_DATA_TRIGGER_BUS => ADO_TTL(15),
- LVL2_DATA_BUS => ADO_TTL(14 downto 11),
- LVL2_ERROR_BUS => ADO_TTL(9),
- LVL2_BUSY_BUS => ADO_TTL(8),
+ LVL1_BUSY => lvl1_busy_i,--'0',
+ LVL2_TRIGGER_BUS => ADO_TTL(8),
+ LVL2_DATA_TRIGGER_BUS => ADO_TTL(9),
+ LVL2_DATA_BUS => ADO_TTL(13 downto 10),
+ LVL2_ERROR_BUS => open,
+ LVL2_BUSY_BUS => ADO_TTL(15),
LVL2_TRIGGER => lvl2_trigger_i,
LVL2_CODE => lvl2_code_i,
LVL2_TAG => lvl2_tag_i,
LVL2_BUSY => lvl2_busy_i,
- LVL2_TRB_ACK => lvl2_trb_ack_i,
+ LVL2_TRB_ACK => lvl2_trb_ack_i,--lvl2_trb_ack_i,
DTU_DEBUG_00 => dtu_debug_00_i);
- ADO_TTL(15 downto 10) <= (others => 'Z');
+ -- ADO_TTL(7) <= lvl1_busy_i;
+ ADO_TTL(5 downto 0) <= (others => 'Z');
+ ADO_TTL(13 downto 8) <= (others => 'Z');
+-- ADO_TTL(7) <= lvl1_busy_i;--'0';
+-- ADO_TTL(1) <= '0';
--------------------------------------------------------------------------
-- no api
--------------------------------------------------------------------------
SAVE_LVL1_TRIGGER: process (tlk_rx_clk_r, external_reset_i, apl_send_in_i)
begin -- process SAVE_LVL1_TRIGGER
if rising_edge(tlk_rx_clk_r) then
- if external_reset_i = '1' or current_state_send_lvl1_and_lvl2_trigg = LVL1_B then
+ if external_reset_i = '1' or current_state_send_lvl1_and_lvl2_trigg = LVL1_A then
lvl1_trigger_saved <= '0';
elsif apl_send_in_i ='1' then
lvl1_trigger_saved <= '1';
SAVE_LVL2_TRIGGER: process (tlk_rx_clk_r, external_reset_i,lvl2_trigger_i)
begin -- process SAVE_LVL1_TRIGGER
if rising_edge(tlk_rx_clk_r) then
- if external_reset_i = '1' or current_state_send_lvl1_and_lvl2_trigg = LVL2_B then
+ if external_reset_i = '1' or current_state_send_lvl1_and_lvl2_trigg = LVL2_A then
lvl2_trigger_saved <= '0';
elsif lvl2_trigger_i ='1' then
lvl2_trigger_saved <= '1';
SEND_LVL1_AND_LVL2_TRIGG_CLK : process (tlk_clk_r,external_reset_i)
begin
if rising_edge(tlk_clk_r) then
- if external_reset_i= '1' then
+ if external_reset_i= '1' or opt_synch_stat = '0' then
current_state_send_lvl1_and_lvl2_trigg <= IDLE;
else
current_state_send_lvl1_and_lvl2_trigg <= next_state_send_lvl1_and_lvl2_trigg;
case current_state_send_lvl1_and_lvl2_trigg is
when IDLE =>
TLK_TX_EN <= '0';
- TLK_TXD <= x"1000";
+ TLK_TXD <= x"0000";
if lvl1_trigger_saved = '1' then
next_state_send_lvl1_and_lvl2_trigg <= LVL1_A;
elsif lvl1_trigger_saved = '1' and lvl2_trigger_saved = '1' then
next_state_send_lvl1_and_lvl2_trigg <= LVL1_C;
when LVL1_C =>
TLK_TX_EN <= '1';
- TLK_TXD <= x"1" & lvl1_trigger_code_i & vulom_int_reg_00(15 downto 8);
+ TLK_TXD <= x"0" & lvl1_trigger_code_i & vulom_int_reg_00(15 downto 8);
next_state_send_lvl1_and_lvl2_trigg <= IDLE;
when LVL2_A =>
TLK_TX_EN <= '1';
next_state_send_lvl1_and_lvl2_trigg <= LVL2_C;
when LVL2_C =>
TLK_TX_EN <= '1';
- TLK_TXD <= x"2" & lvl2_code_i & lvl2_trigger_tag_i;
+ TLK_TXD <= x"0" & lvl2_code_i & lvl2_trigger_tag_i;
next_state_send_lvl1_and_lvl2_trigg <= IDLE;
when others =>
TLK_TX_EN <= '0';
next_state_send_lvl1_and_lvl2_trigg <= IDLE;
end case;
end process SEND_LVL1_AND_LVL2_TRIGG_FSM;
- CHECK_LVL1_BUSY: process (tlk_rx_clk_r, external_reset_i)
+ SYSTEM_LVL1_BUSY: process (tlk_rx_clk_r, external_reset_i)
begin
if rising_edge(tlk_rx_clk_r) then
if external_reset_i = '1' or (TLK_RX_DV = '1' and TLK_RXD(15 downto 12) = x"1") then
lvl1_system_busy <= '1';
end if;
end if;
- end process CHECK_LVL1_BUSY;
- lvl1_busy_i <= lvl1_system_busy or lvl1_cts_busy;
- CHECK_LVL2_BUSY: process (tlk_rx_clk_r, external_reset_i)
+ end process SYSTEM_LVL1_BUSY;
+ SYSTEM_LVL2_BUSY: process (tlk_rx_clk_r, external_reset_i)
begin
if rising_edge(tlk_rx_clk_r) then
if external_reset_i = '1' or (TLK_RX_DV = '1' and TLK_RXD(15 downto 12) = x"2") then
- lvl2_busy_i <= '0';
+ lvl2_system_busy <= '0';
elsif lvl2_trigger_saved = '1' then
- lvl2_busy_i <= '1';
+ lvl2_system_busy <= '1';
end if;
end if;
- end process CHECK_LVL2_BUSY;
- not_lvl2_busy_i <= not lvl2_busy_i;
- ACK_LVL2_PULSER : edge_to_pulse
- port map (
- clock => CLK,
- en_clk => '1',
- signal_in => not_lvl2_busy_i,
- pulse => lvl2_trb_ack_system);
+ end process SYSTEM_LVL2_BUSY;
+
+ CHECK_OPT_SYNCH: process (tlk_rx_clk_r, external_reset_i)
+ begin
+ if rising_edge(tlk_rx_clk_r) then
+ if external_reset_i = '1' or TLK_RX_ER = '1' then
+ opt_synch_stat_counter <= x"00000000";
+ elsif (TLK_RX_ER = '0' and TLK_RX_DV = '0') and opt_synch_stat_counter(27) = '0' then
+ opt_synch_stat_counter <= opt_synch_stat_counter + 1;
+ end if;
+ end if;
+ end process CHECK_OPT_SYNCH;
+ opt_synch_stat <= '1';--opt_synch_stat_counter(27);--'1';--opt_synch_stat_counter(27);--sim
+
--------------------------------------------------------------------------
-- event from cts to etrax
--------------------------------------------------------------------------
LVL1_BUSY => lvl1_cts_busy,--lvl1_busy_i,
LVL2_START => lvl2_trigger_i,
LVL2_CODE => '0',--lvl2_trigger_code_i(3),
- LVL2_TRB_ACK => lvl2_trb_ack_cts,
+ LVL2_TRB_BUSY => lvl2_cts_busy, --end pulse
CTS_ETRAX_REGISTER_00 => cts_etrax_register_00_i,
CTS_ETRAX_REGISTER_01 => cts_etrax_register_01_i,
CTS_ETRAX_REGISTER_02 => cts_etrax_register_02_i,
CTS_ETRAX_REGISTER_03 => cts_etrax_register_03_i,
- CTS_ETRAX_REGISTER_04 => cts_etrax_register_04_i);
+ CTS_ETRAX_REGISTER_04 => cts_etrax_register_04_i,
+ CTS_ETRAX_REGISTER_05 => cts_etrax_register_05_i);
-- ADO_TTL(15 downto 11) <= TLK_TXD_i (4 downto 0);
FPGA_REGISTER_08 => fpga_register_08_i,
FPGA_REGISTER_09 => fpga_register_09_i,
FPGA_REGISTER_0a => fpga_register_0a_i,
- FPGA_REGISTER_0b => x"00000000",--fpga_register_0b_i,
- FPGA_REGISTER_0c => x"00000000",--fpga_register_0c_i,
+ FPGA_REGISTER_0b => fpga_register_0b_i,
+ FPGA_REGISTER_0c => fpga_register_0c_i,
FPGA_REGISTER_0d => x"00000000",--fpga_register_0d_i,
FPGA_REGISTER_0e => fpga_register_0e_i,--fpga_register_0d_i,
EXTERNAL_RESET => external_reset,
LVL2_VALID => lvl2_code_i(3)--lvl2_trigger_code_i(3)
);
fpga_register_01_i <= vulom_int_reg_00;
- fpga_register_02_i <= '0' & "000" & "00"& TLK_RX_DV & TLK_RX_ER & TLK_RXD & x"00";--
+ fpga_register_02_i <= opt_synch_stat & "000" & "00" & TLK_RX_DV & TLK_RX_ER & TLK_RXD & x"00";--
--apl_seqnr_out_i;
fpga_register_03_i <= cts_etrax_register_00_i;-- x"bacd0000";--med_data_out_i_saved(31 downto 0);
fpga_register_04_i <= cts_etrax_register_01_i;--x"00001234";--med_data_out_i_saved(63 downto 32);
- fpga_register_05_i <= cts_etrax_register_02_i;
+ fpga_register_05_i <= cts_etrax_register_02_i;--cts_etrax_register_02_i;
fpga_register_09_i <= cts_etrax_register_03_i;
fpga_register_0a_i <= cts_etrax_register_04_i;
+ fpga_register_0b_i <= x"80000"& "00" & lvl2_busy_i &lvl2_trb_ack_cts_saved & lvl2_trb_ack_system_saved & lvl1_trb_ack_cts_saved & lvl1_trb_ack_system_saved & lvl1_system_busy_end & lvl1_cts_busy_end & lvl1_cts_busy & lvl1_system_busy & lvl1_busy_i ;
+-- fpga_register_0c_i <= cts_etrax_register_05_i;
-- ADO_TTL(5)<= vulom_int_reg_00(0);
-- ADO_TTL(6) <= vulom_int_reg_00(1);--K_RX_ER;
-- ADO_TTL(7) <= ADDON_CLK1;--vulom_int_reg_00(2);
#add_file options
+add_file -vhdl -lib work "~/trbnet/optical_link/simpleupcounter_8bit.vhd"
add_file -vhdl -lib work "~/trbnet/trb_net16_med_tlk"
add_file -vhdl -lib work "~/trbnet/trb_net_rom_16x8.vhd"
add_file -vhdl -lib work "~/trbnet/trb_net_onewire.vhd"
add_file -vhdl -lib work "up_down_counter_10bit.vhd"
add_file -vhdl -lib work "simpleupcounter_10bit.vhd"
add_file -vhdl -lib work "link_converter.vhd"
-add_file -vhdl -lib work "cts_etrax_interface.vhd"
+#add_file -vhdl -lib work "cts_etrax_interface.vhd"
add_file -vhdl -lib work "trbv2_tlk_api_fifo.vhd"
add_file -vhdl -lib work "trbv2_tlk_api.vhd"
+add_file -vhdl -lib work "fpga_to_etrax_data_flow.vhd"
#add_file -constraint "cts_syn.sdc"
LVL1_BUSY : out std_logic;
LVL2_START : in std_logic;
LVL2_CODE : in std_logic;
- LVL2_TRB_ACK : out std_logic;
+ LVL2_TRB_BUSY : out std_logic;
CTS_ETRAX_REGISTER_00 : out std_logic_vector(31 downto 0);
CTS_ETRAX_REGISTER_01 : out std_logic_vector(31 downto 0);
CTS_ETRAX_REGISTER_02 : out std_logic_vector(31 downto 0);
CTS_ETRAX_REGISTER_03 : out std_logic_vector(31 downto 0);
- CTS_ETRAX_REGISTER_04 : out std_logic_vector(31 downto 0)
+ CTS_ETRAX_REGISTER_04 : out std_logic_vector(31 downto 0);
+ CTS_ETRAX_REGISTER_05 : out std_logic_vector(31 downto 0)
);
end fpga_to_etrax_data_flow;
architecture fpga_to_etrax_data_flow of fpga_to_etrax_data_flow is
I: in std_ulogic
);
end component;
- component up_counter_8bit
+ component simpleupcounter_8bit
port (
QOUT : out std_logic_vector(7 downto 0);
UP : in std_logic;
signal tdc_data_valid_i_fsm : std_logic;
signal lvl2_finished : std_logic;
signal lvl2_finished_pulse : std_logic;
-
+ signal not_lvl1_busy : std_logic;
begin
CTS_ETRAX_REGISTER_00(3) <= '0';
CTS_ETRAX_REGISTER_00(13 downto 4) <= (others => '0');
CTS_ETRAX_REGISTER_00(14) <= lvl1_busy_i;
- CTS_ETRAX_REGISTER_00(15) <= lvl1_or_lvl2_is_busy;--lvl1_memory_busy_i;
+ CTS_ETRAX_REGISTER_00(15) <= lvl1_memory_busy_i;
CTS_ETRAX_REGISTER_00(30) <= lvl1_fifo_wr_en;
CTS_ETRAX_REGISTER_00(31) <= lvl2_busy_i;
CTS_ETRAX_REGISTER_00(29 downto 16) <= lvl1_fifo_counter;
end if;
end if;
end process LVL2_BUSY_SET;
- LVL2_TRB_ACK <= lvl2_busy_end_pulse;
+ LVL2_TRB_BUSY <= lvl2_busy_i;-- lvl2_busy_end_pulse;
LVL2_BUSY_START_PULSER : edge_to_pulse
port map (
clock => CLK,
en_clk => '1',
signal_in => lvl2_busy_i,
pulse => lvl2_busy_start_pulse);
- lvl1_memory_busy_i <= '1' when lvl1_fifo_counter > "00001111111111" else '0';
+ lvl1_memory_busy_i <= '0';--'1' when lvl1_fifo_counter > "00001111111111" else '0';
--set
--to
--max
-----------------------------------------------------------------------------
-- end writing to fifo when TDC_LVL1_BUSY and read all data and send finish signal
-----------------------------------------------------------------------------
--- TEST_COUNTER_a : up_counter_8bit
--- port map (
--- CLK => CLK,
--- UP => tdc_start_i,
--- CLR => RESET,
--- QOUT => test_counter_0
--- );
--- TEST_COUNTER_b : up_counter_8bit
--- port map (
--- CLK => CLK,
--- UP => RECEIVED_TDC_TOKEN,
--- CLR => RESET,
--- QOUT => test_counter_1
--- );
- TEST_COUNTER_c : up_counter_8bit
+ TEST_COUNTER_a : simpleupcounter_8bit
+ port map (
+ CLK => CLK,
+ UP => lvl1_busy_i,
+ CLR => RESET,
+ QOUT => test_counter_0
+ );
+ not_lvl1_busy <= lvl1_busy_i;
+ TEST_COUNTER_b : simpleupcounter_8bit
+ port map (
+ CLK => CLK,
+ UP => not_lvl1_busy,
+ CLR => RESET,
+ QOUT => test_counter_1
+ );
+ TEST_COUNTER_c : simpleupcounter_8bit
port map (
CLK => CLK,
UP => lvl2_busy_start_pulse,--lvl2_trigger_pulse,
CLR => RESET,
QOUT => test_counter_2
);
- TEST_COUNTER_d : up_counter_8bit
+ TEST_COUNTER_d : simpleupcounter_8bit
port map (
CLK => CLK,
UP => lvl2_busy_end_pulse,
CLR => RESET,
QOUT => test_counter_3
);
+ CTS_ETRAX_REGISTER_05 <= test_counter_3 & test_counter_2 & test_counter_1 & test_counter_0;
REGITERING_SIGNALS: process (CLK, RESET)
begin
if rising_edge(CLK) then -- rising clock edge
end case;
end process VULOM_TO_API_FSM;
--- BUSY <=(busy_i or LVL1_TRANSFER_BUSY);6e1b17
- BUSY <= ack;
+ BUSY <=busy_i;-- or LVL1_TRANSFER_BUSY);6e1b17
+-- BUSY <= ack;
VULOM_INT_REG(3 downto 0) <= vulom_interface_debug(3 downto 0);
VULOM_INT_REG(7 downto 4) <= vulom_interface_debug(7 downto 4);
VULOM_INT_REG(15 downto 8) <= trigger_tag(7 downto 0);
NOTE "CREATOR" "Xilinx iMPACT Software";
-NOTE "DATE" "2008/07/19";
+NOTE "DATE" "2008/08/24";
NOTE "STAPL_VERSION" "JESD71";
NOTE "ALG_VERSION" "1";
NOTE "DEVICE" "UNSPECIFIED";
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;
' // Loading device with a `jstart` instruction.
IRSCAN 10, $03cc
IF D <= 2500 THEN CALL ADJUST_SMALL_DELAY;
ENDPROC;
-CRC A7B0;
+CRC 5083;
# NET +<1> LOC = AE28;
# NET +<2> LOC ="L2| IOSTANDARD = "LVTTL";
# NET +<3> LOC ="AJ18| IOSTANDARD = "LVTTL";
- # NET ADDON_TO_TRB_CLKINN LOC ="G16| IOSTANDARD = "LVTTL";
- # NET ADDON_TO_TRB_CLKINP LOC ="G17| IOSTANDARD = "LVTTL";
+ NET ADDON_TO_TRB_CLKINN LOC ="G16";
+ NET ADDON_TO_TRB_CLKINP LOC ="G17";
+ NET "ADDON_TO_TRB_CLKINP" TNM_NET = ADDON_TO_TRB_CLKINP;
+# TIMESPEC TS_ADDON_TO_TRB_CLKINP =PERIOD "ADDON_TO_TRB_CLKINP" 9 ns; #mdc
NET ADO_LV<0> LOC ="AC9";
NET ADO_LV<1> LOC ="AC8";
NET ADO_LV<2> LOC ="AG3";
NET ADO_TTL<13> LOC ="AP12"| IOSTANDARD = "LVTTL";
NET ADO_TTL<14> LOC ="AP9"| IOSTANDARD = "LVTTL";
NET ADO_TTL<15> LOC ="AN9"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<16> LOC ="AH12"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<17> LOC ="AG11"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<18> LOC ="AN7"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<19> LOC ="AM7"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<20> LOC ="AN10"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<21> LOC ="AM10"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<22> LOC ="AF10"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<23> LOC ="AE9"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<24> LOC ="AJ12"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<25> LOC ="L33"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<26> LOC ="L34"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<27> LOC ="M32"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<28> LOC ="M33"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<29> LOC ="D5"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<30> LOC ="G7"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<31> LOC ="G6"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<32> LOC ="E14"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<33> LOC ="D14"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<34> LOC ="AL20"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<35> LOC ="AJ15"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<36> LOC ="AJ14"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<37> LOC ="AG20"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<38> LOC ="AH20"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<39> LOC ="AG15"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<40> LOC ="AH14"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<41> LOC ="AL16"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<42> LOC ="AK16"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<43> LOC ="C28"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<44> LOC ="L26"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<45> LOC ="B32"| IOSTANDARD = "LVTTL";
-# NET ADO_TTL<46> LOC ="B33"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<16> LOC ="AH12"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<17> LOC ="AG11"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<18> LOC ="AN7"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<19> LOC ="AM7"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<20> LOC ="AN10"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<21> LOC ="AM10"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<22> LOC ="AF10"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<23> LOC ="AE9"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<24> LOC ="AJ12"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<25> LOC ="L33"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<26> LOC ="L34"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<27> LOC ="M32"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<28> LOC ="M33"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<29> LOC ="D5"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<30> LOC ="G7"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<31> LOC ="G6"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<32> LOC ="E14"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<33> LOC ="D14"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<34> LOC ="AL20"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<35> LOC ="AJ15"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<36> LOC ="AJ14"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<37> LOC ="AG20"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<38> LOC ="AH20"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<39> LOC ="AG15"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<40> LOC ="AH14"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<41> LOC ="AL16"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<42> LOC ="AK16"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<43> LOC ="C28"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<44> LOC ="L26"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<45> LOC ="B32"| IOSTANDARD = "LVTTL";
+ NET ADO_TTL<46> LOC ="B33"| IOSTANDARD = "LVTTL";
NET A_CSB LOC ="P9";
NET A_CS LOC ="P10";
NET A_DATA_READY LOC ="B12"| IOSTANDARD = "LVTTL"| SLEW = FAST;
NET TDC_RESET LOC ="C5"| IOSTANDARD = "LVTTL";
NET TLK_CLK LOC ="AG16"| IOSTANDARD = "LVTTL";
NET "TLK_CLK" TNM_NET =TLK_CLK;
- TIMESPEC TS_TLK_CLK =PERIOD "TLK_CLK" 9 ns;
+ # TIMESPEC TS_TLK_CLK =PERIOD "TLK_CLK" 9 ns;
NET TLK_ENABLE LOC ="R24"| IOSTANDARD = "LVTTL";
NET TLK_LCKREFN LOC ="L28"| IOSTANDARD = "LVTTL";
NET TLK_LOOPEN LOC ="R19"| IOSTANDARD = "LVTTL";
NET TLK_RXD<15> LOC ="G33"| IOSTANDARD = "LVTTL";
NET TLK_RX_CLK LOC ="AF18"| IOSTANDARD = "LVTTL";
NET "TLK_RX_CLK" TNM_NET =TLK_RX_CLK;
- TIMESPEC TS_TLK_RX_CLK =PERIOD "TLK_RX_CLK" 9 ns;
+ # TIMESPEC TS_TLK_RX_CLK =PERIOD "TLK_RX_CLK" 9 ns;
NET TLK_RX_DV LOC ="M30"| IOSTANDARD = "LVTTL";
NET TLK_RX_ER LOC ="P20"| IOSTANDARD = "LVTTL";
NET TLK_TXD<0> LOC ="H27"| IOSTANDARD = "LVTTL";
NET VIRT_TDO LOC ="N30"| IOSTANDARD = "LVTTL";
NET VIRT_TMS LOC ="J34"| IOSTANDARD = "LVTTL";
NET VIRT_TRST LOC ="N29"| IOSTANDARD = "LVTTL";
-# NET VIR_TRIG LOC ="E3";
-# NET VIR_TRIGB LOC ="E2";
+ NET VIR_TRIG LOC ="E3";
+ NET VIR_TRIGB LOC ="E2";
# NET VSD_A<0> LOC ="F23"| IOSTANDARD = "LVTTL";
# NET VSD_A<1> LOC ="E23"| IOSTANDARD = "LVTTL";
# NET VSD_A<2> LOC ="D26"| IOSTANDARD = "LVTTL";
NET "VIRT_CLK" TNM_NET =VIRT_CLK;
TIMESPEC TS_VIRT_CLK =PERIOD "VIRT_CLK" 9 ns;
NET "REF_TDC_CLK" TNM_NET = REF_TDC_CLK;
-# TIMESPEC TS_REF_TDC_CLK = PERIOD "REF_TDC_CLK" 23 ns;
+ TIMESPEC TS_REF_TDC_CLK = PERIOD "REF_TDC_CLK" 23 ns;
NET "A_DATA_READY" TNM = TDC_NET_GROUP ;
NET "B_DATA_READY" TNM = TDC_NET_GROUP ;
TDC_READOUT_COMPLETED : out std_logic;
LVL1_TAG : in std_logic_vector(7 downto 0);
LVL1_CODE : in std_logic_vector(3 downto 0);
+ LVL2_TAG : in std_logic_vector(7 downto 0);
HOW_MANY_ADD_DATA : in std_logic_vector(7 downto 0);
COUNTER_a : in std_logic_vector(31 downto 0);
COUNTER_b : in std_logic_vector(31 downto 0);
TDC_START : out std_logic;
TRIGGER_WITHOUT_HADES : in std_logic;
TRIGGER_WITH_GEN_EN : in std_logic;
- TRIGGER_WITH_GEN : in std_logic
+ TRIGGER_WITH_GEN : in std_logic;
+ FIFO_RESET_ERR : out std_logic
);
end component;
component etrax_interfacev2
signal tdc_control_register_i : std_logic_vector(7 downto 0);
signal delay_trigger_i : std_logic_vector(7 downto 0);
signal trb_ack_lvl1_i : std_logic;
+ signal lvl2_trb_ack_i : std_logic;
signal trb_ack_lvl2_i : std_logic;
signal etrax_data_bus_i : std_logic_vector(35 downto 0);
signal etrax_bus_busy_i : std_logic; --should go to busy logic !?
signal busy_register_01_i : std_logic_vector(31 downto 0);
signal trigger_register_00_i : std_logic_vector(31 downto 0);
signal lvl2_trigger_code_i : std_logic_vector(3 downto 0):=x"0";
+ signal lvl2_trigger_tag_i : std_logic_vector(7 downto 0):=x"00";
signal trb_ack_lvl1_long_i : std_logic;
signal trb_ack_lvl2_long_i : std_logic;
signal lvl1_counter_ack : std_logic_vector(7 downto 0);
signal hub_test : std_logic_vector(7 downto 0);
signal tlk_tx_en_i : std_logic;
signal lvl1_trb_ack_i : std_logic;
- signal lvl2_trb_ack_i : std_logic;
signal lvl1_trb_ack_synch : std_logic;
signal lvl2_trb_ack_synch : std_logic;
signal opt_synch_stat : std_logic;
signal ado_ttl0_i : std_logic;
signal ado_ttl0_more : std_logic;
signal addon_clk : std_logic;
+ --no api
+ type send_lvl1_and_lvl2_trigg is (IDLE, LVL1_A, LVL1_B, LVL1_C, LVL2_A, LVL2_B, LVL2_C);
+ signal current_state_send_lvl1_and_lvl2_trigg, next_state_send_lvl1_and_lvl2_trigg : send_lvl1_and_lvl2_trigg;
+-- signal not_lvl2_busy_i : std_logic;
+ signal lvl1_cts_busy : std_logic;
+ signal lvl1_system_busy : std_logic;
+ signal lvl2_trb_ack_cts : std_logic;
+ signal lvl2_trb_ack_system : std_logic;
+ signal lvl2_trb_ack_cts_saved : std_logic;
+ signal lvl2_trb_ack_system_saved : std_logic;
+ signal lvl1_trigger_saved : std_logic;
+ signal lvl2_trigger_saved : std_logic;
+ signal dtu_debug_00_i : std_logic_vector(31 downto 0);
+ signal fifo_reset_err_i : std_logic;
+ --signal opt_synch_stat_counter : std_logic_vector(31 downto 0);
+ --signal opt_synch_stat : std_logic;
begin
-------------------------------------------------------------------------------
-- test
-- tdc interface without trbnet
-----------------------------------------------------------------------------
--opt
- TLK_TX_ER <= '0';
- SFP_TX_DIS <= fpga_register_06_i(15);
- TLK_LOOPEN <= '0';
- TLK_LCKREFN <= '1';
- TLK_ENABLE <= '1';
- TLK_PRBSEN <= '0';
- TLK_RX_CLK_BUFR: BUFR
- port map(
- CE => '1',
- CLR => '0',
- I => TLK_RX_CLK,
- O => tlk_rx_clk_r
- );
- TLK_CLK_BUFR: BUFR
- port map(
- CE => '1',
- CLR => '0',
- I => TLK_CLK,
- O => tlk_clk_r
- );
- not_lvl2_busy_i <= not lvl2_busy_i;
- ACK_LVL2_PULSER : edge_to_pulse
- port map (
- clock => tlk_rx_clk_r,
- en_clk => '1',
- signal_in => not_lvl2_busy_i,
- pulse => lvl2_trb_ack_i);
- not_lvl1_busy_i <= not lvl1_busy_i;
- ACK_LVL1_PULSER : edge_to_pulse
- port map (
- clock => tlk_rx_clk_r,
- en_clk => '1',
- signal_in => not_lvl1_busy_i,
- pulse => lvl1_trb_ack_i);
- SYNCH_ACK: process (tlk_clk_r, external_reset_i)
- begin -- process SYNCH_ACK
- if rising_edge(tlk_clk_r) then
- if external_reset_i = '1' then -- asynchronous reset (active low)
- lvl1_trb_ack_synch <= '0';
- lvl2_trb_ack_synch <= '0';
- else
- lvl1_trb_ack_synch <= lvl1_trb_ack_i;
- lvl2_trb_ack_synch <= lvl2_trb_ack_i;
- end if;
- end if;
- end process SYNCH_ACK;
- SEND_LVL1_LVL2_ACK: process (tlk_clk_r, external_reset_i)
- begin
- if rising_edge(tlk_clk_r) then
- if external_reset_i = '1' and opt_synch_stat = '0' then -- asynchronous reset (active low)
- TLK_TX_EN <= '0';
- TLK_TXD <= x"0000";
- elsif lvl1_trb_ack_i = '1' then
- TLK_TX_EN <= '1';
- TLK_TXD <= x"1000";
- elsif lvl2_trb_ack_i = '1' then
- TLK_TX_EN <= '1';
- TLK_TXD <= x"2000";
- elsif lvl1_trb_ack_i = '1' and lvl2_trb_ack_i ='1' then
- TLK_TX_EN <= '1';
- TLK_TXD <= x"1000";
- elsif lvl1_trb_ack_synch = '1' and lvl2_trb_ack_synch ='1' then
- TLK_TX_EN <= '1';
- TLK_TXD <= x"2000";
- else
- TLK_TX_EN <= '0';
- TLK_TXD <= x"0000";
- end if;
- end if;
- end process SEND_LVL1_LVL2_ACK;
- SAVE_LVL1_LVL2_TRIGG: process (tlk_rx_clk_r, external_reset_i, TLK_RX_DV, TLK_RXD(15 downto 12), TLK_RX_ER)
- begin
- if falling_edge(tlk_rx_clk_r) then
- if external_reset_i = '1' or opt_synch_stat = '0' then -- asynchronous reset (active low)
- lvl1_trigger_code_i <= x"0";
- lvl1_trigger_tag_i <= x"00";
- lvl2_trigger_code_i <= x"0";
- lvl1_trigger_i <= '0';
- lvl2_trigger_i <= '0';
- elsif TLK_RX_DV = '1' and TLK_RX_ER = '0' and TLK_RXD(15 downto 12)= x"1" then
- lvl1_trigger_code_i <= TLK_RXD(11 downto 8);
- lvl1_trigger_tag_i <= TLK_RXD(7 downto 0);
- lvl2_trigger_code_i <= lvl2_trigger_code_i;
- lvl1_trigger_i <= '1';
- lvl2_trigger_i <= '0';
- elsif TLK_RX_DV = '1' and TLK_RX_ER = '0' and TLK_RXD(15 downto 12)= x"2" then
- lvl1_trigger_code_i <= lvl1_trigger_code_i;
- lvl1_trigger_tag_i <= lvl1_trigger_tag_i;
- lvl2_trigger_code_i <= TLK_RXD(11 downto 8);
- lvl1_trigger_i <= '0';
- lvl2_trigger_i <= '1';
- else
- lvl1_trigger_code_i <= lvl1_trigger_code_i;
- lvl1_trigger_tag_i <= lvl1_trigger_tag_i;
- lvl2_trigger_code_i <= lvl2_trigger_code_i;
- lvl1_trigger_i <= '0';
- lvl2_trigger_i <= '0';
- end if;
- end if;
- end process SAVE_LVL1_LVL2_TRIGG;
- CHECK_OPT_SYNCH: process (tlk_rx_clk_r, external_reset_i)
- begin
- if rising_edge(tlk_rx_clk_r) then
- if external_reset_i = '1' or TLK_RX_ER = '1' then
- opt_synch_stat_counter <= x"00000000";
- elsif (TLK_RX_ER = '0' and TLK_RX_DV = '0') and opt_synch_stat_counter(27) = '0' then
- opt_synch_stat_counter <= opt_synch_stat_counter + 1;
- end if;
- end if;
- end process CHECK_OPT_SYNCH;
- opt_synch_stat <= '1';--opt_synch_stat_counter(27);sim
+-- TLK_TX_ER <= '0';
+-- SFP_TX_DIS <= fpga_register_06_i(15);
+-- TLK_LOOPEN <= '0';
+-- TLK_LCKREFN <= '1';
+-- TLK_ENABLE <= '1';
+-- TLK_PRBSEN <= '0';
+-- TLK_RX_CLK_BUFR: BUFR
+-- port map(
+-- CE => '1',
+-- CLR => '0',
+-- I => TLK_RX_CLK,
+-- O => tlk_rx_clk_r
+-- );
+-- TLK_CLK_BUFR: BUFR
+-- port map(
+-- CE => '1',
+-- CLR => '0',
+-- I => TLK_CLK,
+-- O => tlk_clk_r
+-- );
+
+-- not_lvl2_busy_i <= not lvl2_busy_i;
+-- ACK_LVL2_PULSER : edge_to_pulse
+-- port map (
+-- clock => tlk_rx_clk_r,
+-- en_clk => '1',
+-- signal_in => not_lvl2_busy_i,
+-- pulse => lvl2_trb_ack_i);
+-- not_lvl1_busy_i <= not lvl1_busy_i;
+-- ACK_LVL1_PULSER : edge_to_pulse
+-- port map (
+-- clock => tlk_rx_clk_r,
+-- en_clk => '1',
+-- signal_in => not_lvl1_busy_i,
+-- pulse => lvl1_trb_ack_i);
+-- SAVE_LVL1_TRIGGER: process (tlk_rx_clk_r, external_reset_i, apl_send_in_i)
+-- begin -- process SAVE_LVL1_TRIGGER
+-- if rising_edge(tlk_rx_clk_r) then
+-- if external_reset_i = '1' or current_state_send_lvl1_and_lvl2_trigg = LVL1_B then
+-- lvl1_trigger_saved <= '0';
+-- elsif lvl1_trb_ack_i ='1' then
+-- lvl1_trigger_saved <= '1';
+-- end if;
+-- end if;
+-- end process SAVE_LVL1_TRIGGER;
+-- SAVE_LVL2_TRIGGER: process (tlk_rx_clk_r, external_reset_i,lvl2_trigger_i)
+-- begin -- process SAVE_LVL1_TRIGGER
+-- if rising_edge(tlk_rx_clk_r) then
+-- if external_reset_i = '1' or current_state_send_lvl1_and_lvl2_trigg = LVL2_B then
+-- lvl2_trigger_saved <= '0';
+-- elsif lvl2_trb_ack_i ='1' then
+-- lvl2_trigger_saved <= '1';
+-- end if;
+-- end if;
+-- end process SAVE_LVL2_TRIGGER;
+-- SEND_LVL1_AND_LVL2_TRIGG_CLK : process (tlk_clk_r,external_reset_i)
+-- begin
+-- if rising_edge(tlk_clk_r) then
+-- if external_reset_i= '1' or opt_synch_stat = '0' then
+-- current_state_send_lvl1_and_lvl2_trigg <= IDLE;
+-- else
+-- current_state_send_lvl1_and_lvl2_trigg <= next_state_send_lvl1_and_lvl2_trigg;
+-- end if;
+-- end if;
+-- end process SEND_LVL1_AND_LVL2_TRIGG_CLK;
+-- SEND_LVL1_AND_LVL2_TRIGG_FSM: process (tlk_clk_r,lvl1_trigger_saved, lvl2_trigger_saved)
+-- begin -- process SEND_LVL1_AND_LVL2_TRIGG_FSM
+-- case current_state_send_lvl1_and_lvl2_trigg is
+-- when IDLE =>
+-- TLK_TX_EN <= '0';
+-- TLK_TXD <= x"0000";
+-- if lvl1_trigger_saved = '1' then
+-- next_state_send_lvl1_and_lvl2_trigg <= LVL1_A;
+-- elsif lvl1_trigger_saved = '1' and lvl2_trigger_saved = '1' then
+-- next_state_send_lvl1_and_lvl2_trigg <= LVL1_A;
+-- elsif lvl2_trigger_saved = '1' then
+-- next_state_send_lvl1_and_lvl2_trigg <= LVL2_A;
+-- else
+-- next_state_send_lvl1_and_lvl2_trigg <= IDLE;
+-- end if;
+-- when LVL1_A =>
+-- TLK_TX_EN <= '1';
+-- TLK_TXD <= x"1000";-- & lvl1_trigger_code_i & vulom_int_reg_00(15 downto 8);
+-- next_state_send_lvl1_and_lvl2_trigg <= LVL1_B;
+-- when LVL1_B =>
+-- TLK_TX_EN <= '1';
+-- TLK_TXD <= x"1000";-- & lvl1_trigger_code_i & vulom_int_reg_00(15 downto 8);
+-- next_state_send_lvl1_and_lvl2_trigg <= LVL1_C;
+-- when LVL1_C =>
+-- TLK_TX_EN <= '1';
+-- TLK_TXD <= x"0000";-- & lvl1_trigger_code_i & vulom_int_reg_00(15 downto 8);
+-- next_state_send_lvl1_and_lvl2_trigg <= IDLE;
+-- when LVL2_A =>
+-- TLK_TX_EN <= '1';
+-- TLK_TXD <= x"2000";-- & lvl2_code_i & lvl2_trigger_tag_i;
+-- next_state_send_lvl1_and_lvl2_trigg <= LVL2_B;
+-- when LVL2_B =>
+-- TLK_TX_EN <= '1';
+-- TLK_TXD <= x"2000";-- & lvl2_code_i & lvl2_trigger_tag_i;
+-- next_state_send_lvl1_and_lvl2_trigg <= LVL2_C;
+-- when LVL2_C =>
+-- TLK_TX_EN <= '1';
+-- TLK_TXD <= x"0000";-- & lvl2_code_i & lvl2_trigger_tag_i;
+-- next_state_send_lvl1_and_lvl2_trigg <= IDLE;
+-- when others =>
+-- TLK_TX_EN <= '0';
+-- TLK_TXD <= x"1000";
+-- next_state_send_lvl1_and_lvl2_trigg <= IDLE;
+-- end case;
+-- end process SEND_LVL1_AND_LVL2_TRIGG_FSM;
+
+
+-- SAVE_LVL1_LVL2_TRIGG: process (tlk_rx_clk_r, external_reset_i, TLK_RX_DV, TLK_RXD(15 downto 12), TLK_RX_ER)
+-- begin
+-- if falling_edge(tlk_rx_clk_r) then
+-- if external_reset_i = '1' or opt_synch_stat = '0' then -- asynchronous reset (active low)
+-- lvl1_trigger_code_i <= x"0";
+-- lvl1_trigger_tag_i <= x"00";
+-- lvl2_trigger_code_i <= x"0";
+-- lvl1_trigger_i <= '0';
+-- lvl2_trigger_i <= '0';
+-- elsif TLK_RX_DV = '1' and TLK_RX_ER = '0' and TLK_RXD(15 downto 12)= x"1" then
+-- lvl1_trigger_code_i <= TLK_RXD(11 downto 8);
+-- lvl1_trigger_tag_i <= TLK_RXD(7 downto 0);
+-- lvl2_trigger_code_i <= lvl2_trigger_code_i;
+-- lvl1_trigger_i <= '1';
+-- lvl2_trigger_i <= '0';
+-- elsif TLK_RX_DV = '1' and TLK_RX_ER = '0' and TLK_RXD(15 downto 12)= x"2" then
+-- lvl1_trigger_code_i <= lvl1_trigger_code_i;
+-- lvl1_trigger_tag_i <= lvl1_trigger_tag_i;
+-- lvl2_trigger_code_i <= TLK_RXD(11 downto 8);
+-- lvl1_trigger_i <= '0';
+-- lvl2_trigger_i <= '1';
+-- else
+-- lvl1_trigger_code_i <= lvl1_trigger_code_i;
+-- lvl1_trigger_tag_i <= lvl1_trigger_tag_i;
+-- lvl2_trigger_code_i <= lvl2_trigger_code_i;
+-- lvl1_trigger_i <= '0';
+-- lvl2_trigger_i <= '0';
+-- end if;
+-- end if;
+-- end process SAVE_LVL1_LVL2_TRIGG;
+-- CHECK_OPT_SYNCH: process (tlk_rx_clk_r, external_reset_i)
+-- begin
+-- if rising_edge(tlk_rx_clk_r) then
+-- if external_reset_i = '1' or TLK_RX_ER = '1' then
+-- opt_synch_stat_counter <= x"00000000";
+-- elsif (TLK_RX_ER = '0' and TLK_RX_DV = '0') and opt_synch_stat_counter(27) = '0' then
+-- opt_synch_stat_counter <= opt_synch_stat_counter + 1;
+-- end if;
+-- end if;
+-- end process CHECK_OPT_SYNCH;
+-- opt_synch_stat <= '1';--opt_synch_stat_counter(27);--'1';--opt_synch_stat_counter(27);--sim
--end opt
TDC_READOUT_COMPLETED => tdc_readout_completed_i,
LVL1_TAG => lvl1_trigger_tag_i, --apl_seqnr_out_i, --tdc_tag_i,
LVL1_CODE => lvl1_trigger_code_i, --apl_data_out_i(3 downto 0), --tdc_code_i,
+ LVL2_TAG => lvl2_trigger_tag_i, --apl_seqnr_out_i, --tdc_tag_i,
HOW_MANY_ADD_DATA => fpga_register_06_i(23 downto 16), --how_many_add_data_i,
COUNTER_a => scaler_counter(0)(31 downto 0),--timing_counter(31 downto 0),--test_counter_1, --scaler_counter_0, --x"12311231",
COUNTER_b => scaler_counter(0)(63 downto 32),--timing_counter(63 downto 32),--scaler_counter(0), --x"12321232",
TDC_REGISTER_05 => fpga_register_0e_i,
BUNCH_RESET => bunch_reset_i,
EVENT_RESET => event_reset_i,
- READ_ADRESS_END_UP => trb_ack_lvl2_i,
+ READ_ADRESS_END_UP => lvl2_trb_ack_i,--trb_ack_lvl2_i,
DELAY_TRIGGER => x"00", --fpga_register_06_i(31 downto 24),
TDC_START => trigger_to_tdc_i,
TRIGGER_WITHOUT_HADES => fpga_register_06_i(7),
TRIGGER_WITH_GEN_EN => fpga_register_06_i(8),
- TRIGGER_WITH_GEN => not_hades_trigger --trigger_for_test_signal or generator_trigger
+ TRIGGER_WITH_GEN => not_hades_trigger, --trigger_for_test_signal or generator_trigger
+ FIFO_RESET_ERR => fifo_reset_err_i
);
--ADO_TTL(42 downto 35) <= tdc_register_01_i(26 downto 19);
-- not_hades_trigger <= rx_dv_pulse;--trigger_for_test_signal or generator_trigger_1 or generator_trigger_2;
-- en_clk => '1',
-- signal_in => ADO_TTL(0),
-- pulse => generator_trigger_1);
- EXT_TRIGGER_1 : edge_to_pulse
- port map (
- clock => CLK,
- en_clk => '1',
- signal_in => fast_ref_trigger,
- pulse => fast_ref_trigger_pulse);
--- generator_trigger_2 <= '0';
- ADO_TTL(0) <= 'Z';
+-- EXT_TRIGGER_1 : edge_to_pulse
+-- port map (
+-- clock => CLK,
+-- en_clk => '1',
+-- signal_in => fast_ref_trigger,
+-- pulse => fast_ref_trigger_pulse);
+-- -- generator_trigger_2 <= '0';
+-- ADO_TTL(0) <= 'Z';
-------------------------------------------------------------------------------
-- tdc to api
-------------------------------------------------------------------------------
-- I => ADDON_TO_TRB_CLKINP,
-- IB => ADDON_TO_TRB_CLKINN -- Diff_n clock buffer input (connect to top-level port)
-- );
--- ADO_TTL(6) <= 'L';
--- ADO_TTL(5) <= 'L';
+
-- EXT_TRIGGER_NORM : edge_to_pulse
-- port map (
EXTERNAL_RESET => external_reset,
LVL2_VALID => lvl2_trigger_code_i(3)
);
- fpga_register_01_i <= x"0" & "00" & lvds_add_on_data(25 downto 0);--tdc_register_00_i;
+ fpga_register_01_i <= tdc_register_00_i;--x"0" & "00" & lvds_add_on_data(25 downto 0);--tdc_register_00_i;
fpga_register_02_i <= tdc_register_01_i;--tdc_data_valid_i & write_lvl1_busy_i & lvl2_busy_fast & lvl2_busy_i & tdc_lvl2_busy_i & tdc_lvl1_busy_i & lvl1_busy_i & trigger_register_00_i(11 downto 0) & sdram_register_00_i(5 downto 0) & dsp_register_00_i(2 downto 0);
fpga_register_03_i <= tdc_register_02_i;--busy_register_01_i;
fpga_register_04_i <= tdc_register_03_i;
fpga_register_05_i <= tdc_register_04_i;
-- fpga_register_09_i <= x"000" & "00" & TLK_RX_ER & TLK_RX_DV & TLK_RXD;--tlk_register_00_i;
- fpga_register_0a_i <= tlk_register_01_i;
- fpga_register_0b_i <= "00" & rx_dv_pulse & opt_busy & lvl1_trigger_code_i & lvl1_trigger_tag_i & x"00" & lvl1_trigger_tag_i;
+ fpga_register_0a_i <= tdc_data_out_i;--tlk_register_01_i;
+ fpga_register_0b_i <= FS_PB(17)&lvl2_trigger_code_i(3)& tdc_data_valid_i& opt_busy & lvl1_trigger_code_i & lvl1_trigger_tag_i & x"00" & lvl1_trigger_tag_i;
-- fpga_register_0b_i <= saved_txd & x"00" & apl_seqnr_out_i;
fpga_register_0c_i <= opt_synch_stat & "0" & TLK_RX_DV & TLK_RX_ER & x"000"& TLK_RXD;
-- fpga_register_0c_i <= med_data_in_i_saved(63 downto 32);--stat_reply_buffer_i;
--- fpga_register_0d_i <= med_data_in_i_saved(31 downto 0);--stat_init_buffer_i;
+ fpga_register_0d_i <= dtu_debug_00_i;--med_data_in_i_saved(31 downto 0);--stat_init_buffer_i;
SYNCH_RESET: process (CLK)
begin -- process SYNCH_RESET
if rising_edge(CLK) then -- rising clock edge
- external_reset_i <= external_reset;
+ external_reset_i <= external_reset;-- or fifo_reset_err_i;
end if;
end process SYNCH_RESET;
fpga_register_10_i <= x"0000"& external_mode_i;
-
+ ADO_TTL(14) <= FS_PB(17);
+ ADO_TTL(6) <= lvl2_trigger_code_i(3);--lvl1_busy_i;
-------------------------------------------------------------------------------
-- tlk
-------------------------------------------------------------------------------
-- ADO_TTL(15 downto 4) <= (others => 'Z');
-- ADO_TTL(2) <= '0';
-- ADO_TTL(3) <= '0';
+ DTU_INT: dtu_interface
+ port map (
+ CLK => CLK,
+ RESET => external_reset_i,
+ LVL1_TRIGGER_BUS => ADO_TTL(0),
+ LVL1_DATA_TRIGGER_BUS => ADO_TTL(1),
+ LVL1_DATA_BUS => ADO_TTL(5 downto 2),
+ LVL1_ERROR_BUS => open,
+ LVL1_BUSY_BUS => ADO_TTL(7),
+ LVL1_TRIGGER => lvl1_trigger_i,
+ LVL1_CODE => lvl1_trigger_code_i,
+ LVL1_TAG => lvl1_trigger_tag_i,
+ LVL1_BUSY => lvl1_busy_i,--'0',
+ LVL2_TRIGGER_BUS => ADO_TTL(8),
+ LVL2_DATA_TRIGGER_BUS => ADO_TTL(9),
+ LVL2_DATA_BUS => ADO_TTL(13 downto 10),
+ LVL2_ERROR_BUS => open,
+ LVL2_BUSY_BUS => ADO_TTL(15),
+ LVL2_TRIGGER => lvl2_trigger_i,
+ LVL2_CODE => lvl2_trigger_code_i,
+ LVL2_TAG => lvl2_trigger_tag_i,
+ LVL2_BUSY => lvl2_busy_i,
+ LVL2_TRB_ACK => lvl2_trb_ack_i,--lvl2_trb_ack_i,
+ DTU_DEBUG_00 => dtu_debug_00_i);
+ -- ADO_TTL(7) <= lvl1_busy_i;
+ ADO_TTL(5 downto 0) <= (others => 'Z');
+ ADO_TTL(13 downto 8) <= (others => 'Z');
+ ADO_TTL(34) <= '1';
+ ADO_TTL(33) <= '0';
-------------------------------------------------------------------------------
-- ctu
-------------------------------------------------------------------------------
C_TEMP : in std_logic;
D_RESERVED : in std_logic;
D_TEMP : in std_logic;
--- VIR_TRIG : in std_logic;
--- VIR_TRIGB : in std_logic;
+ VIR_TRIG : in std_logic;
+ VIR_TRIGB : in std_logic;
A_TDC_ERROR : in std_logic;
B_TDC_ERROR : in std_logic;
C_TDC_ERROR : in std_logic;
SFP_TX_DIS : out std_logic;
SFP_TX_FAULT : in std_logic;
ADO_LV : in std_logic_vector(51 downto 0);
--- ADO_TTL : inout std_logic_vector(46 downto 0);
- ADO_TTL : inout std_logic_vector(15 downto 0);
+ ADDON_TO_TRB_CLKINN : in std_logic;
+ ADDON_TO_TRB_CLKINP : in std_logic;
+ ADO_TTL : inout std_logic_vector(46 downto 0);
+-- ADO_TTL : inout std_logic_vector(15 downto 0);
VIRT_TCK : out std_logic;
VIRT_TDI : out std_logic;
VIRT_TDO : in std_logic;
signal SFP_TX_DIS : std_logic;
signal SFP_TX_FAULT : std_logic;
signal ADO_LV : std_logic_vector(51 downto 0);
--- signal ADO_TTL : std_logic_vector(46 downto 0);
- signal ADO_TTL : std_logic_vector(15 downto 0);
+ signal ADO_TTL : std_logic_vector(46 downto 0);
+-- signal ADO_TTL : std_logic_vector(15 downto 0);
signal VIRT_TCK : std_logic;
signal VIRT_TDI : std_logic;
signal VIRT_TDO : std_logic;
signal VIRT_TMS : std_logic;
signal VIRT_TRST : std_logic;
-
+ signal ADDON_TO_TRB_CLKINN : std_logic;
+ signal ADDON_TO_TRB_CLKINP : std_logic;
signal test_synch_00 : std_logic;
signal dtu_clk : std_logic;
C_TEMP => C_TEMP,
D_RESERVED => D_RESERVED,
D_TEMP => D_TEMP,
--- VIR_TRIG => VIR_TRIG,
--- VIR_TRIGB => VIR_TRIGB,
+ VIR_TRIG => VIR_TRIG,
+ VIR_TRIGB => VIR_TRIGB,
A_TDC_ERROR => A_TDC_ERROR,
B_TDC_ERROR => B_TDC_ERROR,
C_TDC_ERROR => C_TDC_ERROR,
SFP_TX_FAULT => SFP_TX_FAULT,
ADO_LV => ADO_LV,
ADO_TTL => ADO_TTL,
+ ADDON_TO_TRB_CLKINN => ADDON_TO_TRB_CLKINN,
+ ADDON_TO_TRB_CLKINP => ADDON_TO_TRB_CLKINP,
VIRT_TCK => VIRT_TCK,
VIRT_TDI => VIRT_TDI,
VIRT_TDO => VIRT_TDO,
---------------------------------------------------------------------------
rw_mode <= x"0000";
address <= x"00000006";
- data <= x"00000106";
+ data <= x"00000000";
FS_PC(17) <= '0';
FS_PC(16) <= '0';
wait for 1000 ns;
-----------------------------------------------------------------------
-- DTU
-----------------------------------------------------------------------
--- clock_dtu : process
--- begin
--- wait for 34 ns;
+ clock_dtu : process
+ begin
+ wait for 34 ns;
--- loop
--- dtu_clk <= '0';
--- wait for 50 ns;
--- dtu_clk <= '1';
--- wait for 50 ns;
--- end loop;
--- end process;
--- ADO_TTL(4) <= lvl1_trig;
--- ADO_TTL(10) <= lvl2_trig;
-
--- -- LVL1_TAG_COUNTER: process (dtu_clk,RESET_VIRT,lvl1_trig)
--- -- begin
--- -- if rising_edge(dtu_clk) then
--- -- if RESET_VIRT = '0' then
--- -- dtu_lvl1_tag <= x"00";
--- -- elsif ADO_TTL(17) = '1' then
--- -- dtu_lvl1_tag <= dtu_lvl1_tag +1;
--- -- end if;
--- -- end if;
--- -- end process LVL1_TAG_COUNTER;
--- LVL1_COUNT:process
--- begin
--- wait for 100 ns;
--- dtu_lvl1_tag <= x"00";
--- wait on dtu_clk until ADO_TTL(0) = '0';
--- wait on dtu_clk until lvl1_trig = '1';
--- wait for 500 ns;
--- dtu_lvl1_tag <= dtu_lvl1_tag +1;
--- loop
--- wait on dtu_clk until ADO_TTL(0) = '1';
--- -- wait for 1000 ns;
--- dtu_lvl1_tag <= dtu_lvl1_tag +1;
--- wait on dtu_clk until ADO_TTL(0) = '0';
--- end loop;
--- end process LVL1_COUNT;
--- LVL2_COUNT:process
--- begin
--- wait for 100 ns;
--- dtu_lvl2_tag <= x"00";
--- wait on dtu_clk until ADO_TTL(2) = '0';
--- loop
--- -- wait on dtu_clk until ADO_TTL(2) = '1';
--- wait on dtu_clk until lvl2_trig = '1';
--- -- wait for 1000 ns;
--- wait for 500 ns;
--- dtu_lvl2_tag <= dtu_lvl2_tag +1;
--- wait on dtu_clk until ADO_TTL(2) = '0';
--- end loop;
--- end process LVL2_COUNT;
+ loop
+ dtu_clk <= '0';
+ wait for 50 ns;
+ dtu_clk <= '1';
+ wait for 50 ns;
+ end loop;
+ end process;
+ ADO_TTL(0) <= lvl1_trig;
+ ADO_TTL(8) <= lvl2_trig;
+ ADO_TTL(7) <= 'Z';
+ ADO_TTL(15) <= 'Z';
+ -- LVL1_TAG_COUNTER: process (dtu_clk,RESET_VIRT,lvl1_trig)
+ -- begin
+ -- if rising_edge(dtu_clk) then
+ -- if RESET_VIRT = '0' then
+ -- dtu_lvl1_tag <= x"00";
+ -- elsif ADO_TTL(17) = '1' then
+ -- dtu_lvl1_tag <= dtu_lvl1_tag +1;
+ -- end if;
+ -- end if;
+ -- end process LVL1_TAG_COUNTER;
+ LVL1_COUNT:process
+ begin
+ wait for 100 ns;
+ dtu_lvl1_tag <= x"00";
+ wait on dtu_clk until ADO_TTL(0) = '0';
+ wait on dtu_clk until lvl1_trig = '1';
+ wait for 500 ns;
+ dtu_lvl1_tag <= dtu_lvl1_tag +1;
+ loop
+ wait on dtu_clk until ADO_TTL(0) = '1';
+ -- wait for 1000 ns;
+ dtu_lvl1_tag <= dtu_lvl1_tag +1;
+ wait on dtu_clk until ADO_TTL(0) = '0';
+ end loop;
+ end process LVL1_COUNT;
+ LVL2_COUNT:process
+ begin
+ wait for 100 ns;
+ dtu_lvl2_tag <= x"00";
+ wait on dtu_clk until ADO_TTL(2) = '0';
+ loop
+ -- wait on dtu_clk until ADO_TTL(2) = '1';
+ wait on dtu_clk until lvl2_trig = '1';
+ -- wait for 1000 ns;
+ wait for 500 ns;
+ dtu_lvl2_tag <= dtu_lvl2_tag +1;
+ wait on dtu_clk until ADO_TTL(2) = '0';
+ end loop;
+ end process LVL2_COUNT;
--- -- LVL2_TAG_COUNTER: process (dtu_clk,RESET_VIRT,lvl2_trig)
--- -- begin
--- -- if rising_edge(dtu_clk) then
--- -- if RESET_VIRT = '0' then
--- -- dtu_lvl2_tag <= x"00";
--- -- elsif lvl2_trig = '1' then
--- -- dtu_lvl2_tag <= dtu_lvl2_tag +1;
--- -- end if;
--- -- end if;
--- -- end process LVL2_TAG_COUNTER;
--- -- ADO_TTL(20 downto 17) <= (others => 'Z');
+ -- LVL2_TAG_COUNTER: process (dtu_clk,RESET_VIRT,lvl2_trig)
+ -- begin
+ -- if rising_edge(dtu_clk) then
+ -- if RESET_VIRT = '0' then
+ -- dtu_lvl2_tag <= x"00";
+ -- elsif lvl2_trig = '1' then
+ -- dtu_lvl2_tag <= dtu_lvl2_tag +1;
+ -- end if;
+ -- end if;
+ -- end process LVL2_TAG_COUNTER;
+ -- ADO_TTL(20 downto 17) <= (others => 'Z');
--- ADO_TTL(4) <= lvl1_trig;
--- DTU_EMULATION_LVL1: process
--- begin
--- ADO_TTL(9) <= '0';
--- lvl1_trig <= '0';
--- wait for 1000 ns;
--- wait on dtu_clk until ADO_TTL(0) = '0' and dtu_clk = '1'; --busylvl1
--- lvl1_trig <= '1';
--- ADO_TTL(8 downto 5) <= x"d";
--- wait for 100 ns;
--- lvl1_trig <= '0';
--- wait for 100 ns;
--- ADO_TTL(9) <= '1';
--- ADO_TTL(8 downto 5) <= dtu_lvl1_tag(3 downto 0);
--- wait for 100 ns;
--- ADO_TTL(9) <= '0';
--- wait for 100 ns;
--- ADO_TTL(9) <= '1';
--- ADO_TTL(8 downto 5) <= dtu_lvl1_tag(7 downto 4);
--- loop
--- wait for 100 ns;
--- ADO_TTL(9) <= '0';
--- wait for 100 ns;
--- ADO_TTL(9) <= '1';
--- wait for 100 ns;
--- ADO_TTL(9) <= '0';
--- wait on dtu_clk until ADO_TTL(0) = '0' and dtu_clk = '1'; --busylvl1
--- wait for 300 ns;
--- lvl1_trig <= '1';
--- ADO_TTL(8 downto 5) <= x"1";
--- wait for 100 ns;
--- lvl1_trig <= '0';
--- wait for 100 ns;
--- ADO_TTL(9) <= '1';
--- ADO_TTL(8 downto 5) <= dtu_lvl1_tag(3 downto 0);
--- wait for 100 ns;
--- ADO_TTL(9) <= '0';
--- wait for 100 ns;
--- ADO_TTL(9) <= '1';
--- ADO_TTL(8 downto 5) <= dtu_lvl1_tag(7 downto 4);
--- end loop;
--- end process DTU_EMULATION_LVL1;
+ ADO_TTL(4) <= lvl1_trig;
+ DTU_EMULATION_LVL1: process
+ variable lvl1_randomize : integer := 100;
+ begin
+ ADO_TTL(1) <= '0';
+ lvl1_trig <= '0';
+ wait for 1000 ns;
+ wait on dtu_clk until ADO_TTL(7) = '0' and dtu_clk = '1'; --busylvl1
+ lvl1_trig <= '1';
+ ADO_TTL(5 downto 2) <= x"d";
+ wait for 100 ns;
+ lvl1_trig <= '0';
+ wait for 100 ns;
+ ADO_TTL(1) <= '1';
+ ADO_TTL(5 downto 2) <= dtu_lvl1_tag(3 downto 0);
+ wait for 100 ns;
+ ADO_TTL(1) <= '0';
+ wait for 100 ns;
+ ADO_TTL(1) <= '1';
+ ADO_TTL(5 downto 2) <= dtu_lvl1_tag(7 downto 4);
+ loop
+ wait for 100 ns;
+ ADO_TTL(1) <= '0';
+ wait for 100 ns;
+ ADO_TTL(1) <= '1';
+ wait for 100 ns;
+ ADO_TTL(1) <= '0';
+ wait on dtu_clk until ADO_TTL(7) = '0' and dtu_clk = '1'; --busylvl1
+ lvl1_randomize := lvl1_randomize * 3/2 + 10;
+-- wait for (lvl1_randomize )*ns;
+ lvl1_trig <= '1';
+ ADO_TTL(5 downto 2) <= x"1";
+ wait for 100 ns;
+ lvl1_trig <= '0';
+ wait for 100 ns;
+ ADO_TTL(1) <= '1';
+ ADO_TTL(5 downto 2) <= dtu_lvl1_tag(3 downto 0);
+ wait for 100 ns;
+ ADO_TTL(1) <= '0';
+ wait for 100 ns;
+ ADO_TTL(1) <= '1';
+ ADO_TTL(5 downto 2) <= dtu_lvl1_tag(7 downto 4);
+ end loop;
+ end process DTU_EMULATION_LVL1;
-- ADO_TTL(10) <= lvl2_trig;
--- DTU_EMULATION_LVL2:process
--- begin
--- ADO_TTL(15) <= '0';
--- lvl2_trig <= '0';
--- wait for 26000 ns;
--- loop
--- ADO_TTL(15) <= '0';
--- wait on dtu_clk until ADO_TTL(2) = '0'and dtu_clk = '1'; --busylvl2
--- -- wait on dtu_clk until dtu_lvl1_tag > dtu_lvl2_tag + 1;
--- wait on dtu_clk until dtu_lvl1_tag - dtu_lvl2_tag > x"01";
+ DTU_EMULATION_LVL2:process
+ begin
+ -- ADO_TTL(15) <= '0';
+ lvl2_trig <= '0';
+ wait for 26000 ns;
+ loop
+ ADO_TTL(9) <= '0';
+ wait on dtu_clk until ADO_TTL(15) = '0'and dtu_clk = '1'; --busylvl2
+ -- wait on dtu_clk until dtu_lvl1_tag > dtu_lvl2_tag + 1;
+ wait on dtu_clk until dtu_lvl1_tag - dtu_lvl2_tag > x"01";
-- wait for 300 ns;
--- lvl2_trig <= '1';
--- ADO_TTL(14 downto 11) <= x"1";
--- wait for 100 ns;
--- lvl2_trig <= '0';
--- wait for 100 ns;
--- ADO_TTL(15) <= '1';
--- ADO_TTL(14 downto 11) <= dtu_lvl2_tag(3 downto 0);
--- wait for 100 ns;
--- ADO_TTL(15) <= '0';
--- wait for 100 ns;
--- ADO_TTL(15) <= '1';
--- ADO_TTL(14 downto 11) <= dtu_lvl2_tag(7 downto 4);
--- wait for 100 ns;
--- ADO_TTL(15) <= '0';
--- wait for 100 ns;
--- ADO_TTL(15) <= '1';
--- wait for 100 ns;
--- ADO_TTL(15) <= '0';
+ lvl2_trig <= '1';
+ ADO_TTL(13 downto 10) <= x"1";
+ wait for 100 ns;
+ lvl2_trig <= '0';
+ wait for 100 ns;
+ ADO_TTL(9) <= '1';
+ ADO_TTL(13 downto 10) <= dtu_lvl2_tag(3 downto 0);
+ wait for 100 ns;
+ ADO_TTL(9) <= '0';
+ wait for 100 ns;
+ ADO_TTL(9) <= '1';
+ ADO_TTL(13 downto 10) <= dtu_lvl2_tag(7 downto 4);
+ wait for 100 ns;
+ ADO_TTL(9) <= '0';
+ wait for 100 ns;
+ ADO_TTL(9) <= '1';
+ wait for 100 ns;
+ ADO_TTL(9) <= '0';
--- wait on dtu_clk until ADO_TTL(2) = '0'and dtu_clk = '1';
--- wait on dtu_clk until dtu_lvl1_tag - dtu_lvl2_tag > x"01";
--- wait for 100 ns;
--- lvl2_trig <= '1';
--- ADO_TTL(14 downto 11) <= x"9";
--- wait for 100 ns;
--- lvl2_trig <= '0';
--- wait for 100 ns;
--- ADO_TTL(15) <= '1';
--- ADO_TTL(14 downto 11) <= dtu_lvl2_tag(3 downto 0);
--- wait for 100 ns;
--- ADO_TTL(15) <= '0';
--- wait for 100 ns;
--- ADO_TTL(15) <= '1';
--- ADO_TTL(14 downto 11) <= dtu_lvl2_tag(7 downto 4);
--- wait for 100 ns;
--- ADO_TTL(15) <= '0';
--- wait for 100 ns;
--- ADO_TTL(15) <= '1';
--- wait for 100 ns;
--- ADO_TTL(15) <= '0';
--- end loop;
--- end process DTU_EMULATION_LVL2;
+ wait on dtu_clk until ADO_TTL(15) = '0'and dtu_clk = '1';
+ wait on dtu_clk until dtu_lvl1_tag - dtu_lvl2_tag > x"01";
+ -- wait for 100 ns;
+ lvl2_trig <= '1';
+ ADO_TTL(13 downto 10) <= x"9";
+ wait for 100 ns;
+ lvl2_trig <= '0';
+ wait for 100 ns;
+ ADO_TTL(9) <= '1';
+ ADO_TTL(13 downto 10) <= dtu_lvl2_tag(3 downto 0);
+ wait for 100 ns;
+ ADO_TTL(9) <= '0';
+ wait for 100 ns;
+ ADO_TTL(9) <= '1';
+ ADO_TTL(13 downto 10) <= dtu_lvl2_tag(7 downto 4);
+ wait for 100 ns;
+ ADO_TTL(9) <= '0';
+ wait for 100 ns;
+ ADO_TTL(9) <= '1';
+ wait for 100 ns;
+ ADO_TTL(9) <= '0';
+ end loop;
+ end process DTU_EMULATION_LVL2;
-------------------------------------------------------------------------------
-- if external trigger
-------------------------------------------------------------------------------
- send_external_trigger: process
- begin
- loop
- ADO_TTL(0) <= '0';
- wait for 10 ns;
- ADO_TTL(0) <= '1';
- wait for 10 ns;
- end loop;
- end process send_external_trigger;
+-- send_external_trigger: process
+-- begin
+-- loop
+-- ADO_TTL(0) <= '0';
+-- wait for 10 ns;
+-- ADO_TTL(0) <= '1';
+-- wait for 10 ns;
+-- end loop;
+-- end process send_external_trigger;
-- ETRAX_RESPONSE: process
-- begin
-- FS_PC(16) <= '0';
jspc29 / trbv2.git / commitdiff