add cores for trb5sc GBE project, mentioned in .prj file

diff --git a/gbe/cores/GbePcsExtrefclk/GbePcsExtrefclk.sbx b/gbe/cores/GbePcsExtrefclk/GbePcsExtrefclk.sbx
new file mode 100644 (file)
index 0000000..314e0e1
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/GbePcsExtrefclk.sbx
@@ -0,0 +1,2432 @@
+<!DOCTYPE GbePcsExtrefclk>
+<lattice:project>
+    <spirit:component>
+        <spirit:vendor>LATTICE</spirit:vendor>
+        <spirit:library>LOCAL</spirit:library>
+        <spirit:name>GbePcsExtrefclk</spirit:name>
+        <spirit:version>1.0</spirit:version>
+        <spirit:fileSets>
+            <spirit:fileset>
+                <spirit:name>Diamond_Synthesis</spirit:name>
+                <spirit:group>synthesis</spirit:group>
+                <spirit:file>
+                    <spirit:name>./GbePcsExtrefclk.vhd</spirit:name>
+                    <spirit:fileType>vhdlSource</spirit:fileType>
+                </spirit:file>
+            </spirit:fileset>
+            <spirit:fileset>
+                <spirit:name>Diamond_Simulation</spirit:name>
+                <spirit:group>simulation</spirit:group>
+                <spirit:file>
+                    <spirit:name>./GbePcsExtrefclk.vhd</spirit:name>
+                    <spirit:fileType>vhdlSource</spirit:fileType>
+                </spirit:file>
+            </spirit:fileset>
+        </spirit:fileSets>
+        <spirit:componentGenerators/>
+        <spirit:model>
+            <spirit:views/>
+            <spirit:ports>
+                <spirit:port>
+                    <spirit:name>extref_refclkn</spirit:name>
+                    <spirit:displayName>extref_refclkn</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">extref.refclkn</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>extref_refclkp</spirit:name>
+                    <spirit:displayName>extref_refclkp</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">extref.refclkp</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_ctc_del_s</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_ctc_del_s</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.ctc_del_s</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_ctc_ins_s</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_ctc_ins_s</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.ctc_ins_s</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_ctc_orun_s</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_ctc_orun_s</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.ctc_orun_s</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_ctc_urun_s</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_ctc_urun_s</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.ctc_urun_s</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_cyawstn</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_cyawstn</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.cyawstn</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_hdinn</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_hdinn</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.hdinn</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_hdinp</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_hdinp</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.hdinp</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_hdoutn</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_hdoutn</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.hdoutn</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_hdoutp</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_hdoutp</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.hdoutp</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_lsm_status_s</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_lsm_status_s</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.lsm_status_s</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_pll_lol</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_pll_lol</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.pll_lol</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_rsl_disable</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_rsl_disable</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.rsl_disable</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_rsl_rst</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_rsl_rst</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.rsl_rst</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_rsl_rx_rdy</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_rsl_rx_rdy</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.rsl_rx_rdy</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_rsl_tx_rdy</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_rsl_tx_rdy</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.rsl_tx_rdy</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_rst_dual_c</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_rst_dual_c</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.rst_dual_c</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_rx_cdr_lol_s</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_rx_cdr_lol_s</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.rx_cdr_lol_s</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_rx_los_low_s</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_rx_los_low_s</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.rx_los_low_s</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_rx_pcs_rst_c</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_rx_pcs_rst_c</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.rx_pcs_rst_c</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_rx_pwrup_c</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_rx_pwrup_c</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.rx_pwrup_c</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_rx_serdes_rst_c</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_rx_serdes_rst_c</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.rx_serdes_rst_c</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_sci_en</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_sci_en</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.sci_en</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_sci_en_dual</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_sci_en_dual</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.sci_en_dual</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_sci_int</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_sci_int</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.sci_int</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_sci_rd</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_sci_rd</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.sci_rd</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_sci_sel</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_sci_sel</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.sci_sel</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_sci_sel_dual</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_sci_sel_dual</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.sci_sel_dual</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_sci_wrn</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_sci_wrn</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.sci_wrn</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_serdes_pdb</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_serdes_pdb</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.serdes_pdb</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_serdes_rst_dual_c</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_serdes_rst_dual_c</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.serdes_rst_dual_c</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_signal_detect_c</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_signal_detect_c</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.signal_detect_c</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_tx_pclk</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_tx_pclk</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.tx_pclk</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_tx_pcs_rst_c</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_tx_pcs_rst_c</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.tx_pcs_rst_c</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_tx_pwrup_c</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_tx_pwrup_c</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.tx_pwrup_c</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_tx_serdes_rst_c</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_tx_serdes_rst_c</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.tx_serdes_rst_c</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_txi_clk</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_txi_clk</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.txi_clk</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_rx_cv_err</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_rx_cv_err</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                        <spirit:vector>
+                            <spirit:left>0</spirit:left>
+                            <spirit:right>0</spirit:right>
+                        </spirit:vector>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.rx_cv_err</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_rx_disp_err</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_rx_disp_err</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                        <spirit:vector>
+                            <spirit:left>0</spirit:left>
+                            <spirit:right>0</spirit:right>
+                        </spirit:vector>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.rx_disp_err</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_rx_k</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_rx_k</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                        <spirit:vector>
+                            <spirit:left>0</spirit:left>
+                            <spirit:right>0</spirit:right>
+                        </spirit:vector>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.rx_k</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_rxdata</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_rxdata</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                        <spirit:vector>
+                            <spirit:left>7</spirit:left>
+                            <spirit:right>0</spirit:right>
+                        </spirit:vector>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.rxdata</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_sci_addr</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_sci_addr</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                        <spirit:vector>
+                            <spirit:left>5</spirit:left>
+                            <spirit:right>0</spirit:right>
+                        </spirit:vector>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.sci_addr</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_sci_rddata</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_sci_rddata</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                        <spirit:vector>
+                            <spirit:left>7</spirit:left>
+                            <spirit:right>0</spirit:right>
+                        </spirit:vector>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.sci_rddata</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_sci_wrdata</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_sci_wrdata</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                        <spirit:vector>
+                            <spirit:left>7</spirit:left>
+                            <spirit:right>0</spirit:right>
+                        </spirit:vector>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.sci_wrdata</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_tx_disp_correct</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_tx_disp_correct</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                        <spirit:vector>
+                            <spirit:left>0</spirit:left>
+                            <spirit:right>0</spirit:right>
+                        </spirit:vector>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.tx_disp_correct</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_tx_k</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_tx_k</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                        <spirit:vector>
+                            <spirit:left>0</spirit:left>
+                            <spirit:right>0</spirit:right>
+                        </spirit:vector>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.tx_k</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_txdata</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_txdata</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                        <spirit:vector>
+                            <spirit:left>7</spirit:left>
+                            <spirit:right>0</spirit:right>
+                        </spirit:vector>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.txdata</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_xmit</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_xmit</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                        <spirit:vector>
+                            <spirit:left>0</spirit:left>
+                            <spirit:right>0</spirit:right>
+                        </spirit:vector>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.xmit</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+            </spirit:ports>
+        </spirit:model>
+        <spirit:vendorExtensions>
+            <lattice:device>LFE5UM-85F-8BG756C</lattice:device>
+            <lattice:synthesis>synplify</lattice:synthesis>
+            <lattice:date>2019-05-13.09:04:13 AM</lattice:date>
+            <lattice:modified>2019-05-13.10:35:48 AM</lattice:modified>
+            <lattice:diamond>3.10.3.144</lattice:diamond>
+            <lattice:language>VHDL</lattice:language>
+            <lattice:attributes>
+                <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+                <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+                <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+                <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+            </lattice:attributes>
+            <lattice:elements/>
+            <lattice:lpc/>
+            <lattice:groups/>
+        </spirit:vendorExtensions>
+    </spirit:component>
+    <spirit:design>
+        <spirit:vendor>LATTICE</spirit:vendor>
+        <spirit:library>LOCAL</spirit:library>
+        <spirit:name>GbePcsExtrefclk</spirit:name>
+        <spirit:version>1.0</spirit:version>
+        <spirit:componentInstances>
+            <spirit:componentInstance>
+                <spirit:instanceName>extref</spirit:instanceName>
+                <spirit:componentRef>
+                    <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
+                    <spirit:library>LEGACY</spirit:library>
+                    <spirit:name>EXTREF</spirit:name>
+                    <spirit:version>1.1</spirit:version>
+                    <spirit:fileSets>
+                        <spirit:fileset>
+                            <spirit:name>Diamond_Simulation</spirit:name>
+                            <spirit:group>simulation</spirit:group>
+                            <spirit:file>
+                                <spirit:name>./extref/extref.vhd</spirit:name>
+                                <spirit:fileType>vhdlSource</spirit:fileType>
+                            </spirit:file>
+                        </spirit:fileset>
+                        <spirit:fileset>
+                            <spirit:name>Diamond_Synthesis</spirit:name>
+                            <spirit:group>synthesis</spirit:group>
+                            <spirit:file>
+                                <spirit:name>./extref/extref.vhd</spirit:name>
+                                <spirit:fileType>vhdlSource</spirit:fileType>
+                            </spirit:file>
+                        </spirit:fileset>
+                    </spirit:fileSets>
+                    <spirit:componentGenerators>
+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>Configuration</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
+                            <spirit:group>CONFIG</spirit:group>
+                        </spirit:componentGenerator>
+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>CreateNGD</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_ngd.tcl</spirit:generatorExe>
+                            <spirit:group>CONFIG</spirit:group>
+                        </spirit:componentGenerator>
+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>Generation</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
+                            <spirit:group>GENERATE</spirit:group>
+                        </spirit:componentGenerator>
+                    </spirit:componentGenerators>
+                    <spirit:model>
+                        <spirit:views/>
+                        <spirit:ports>
+                            <spirit:port>
+                                <spirit:name>refclkn</spirit:name>
+                                <spirit:displayName>refclkn</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                                <spirit:vendorExtensions>
+                                    <lattice:attributes>
+                                        <lattice:attribute lattice:name="PadPin">true</lattice:attribute>
+                                    </lattice:attributes>
+                                </spirit:vendorExtensions>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>refclko</spirit:name>
+                                <spirit:displayName>refclko</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>refclkp</spirit:name>
+                                <spirit:displayName>refclkp</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                                <spirit:vendorExtensions>
+                                    <lattice:attributes>
+                                        <lattice:attribute lattice:name="PadPin">true</lattice:attribute>
+                                    </lattice:attributes>
+                                </spirit:vendorExtensions>
+                            </spirit:port>
+                        </spirit:ports>
+                    </spirit:model>
+                    <spirit:vendorExtensions>
+                        <lattice:synthesis>synplify</lattice:synthesis>
+                        <lattice:modified>2019-05-13.10:35:48 AM</lattice:modified>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+                            <lattice:attribute lattice:name="BBox">false</lattice:attribute>
+                            <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+                            <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute>
+                            <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute>
+                            <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute>
+                            <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+                            <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+                        </lattice:attributes>
+                        <lattice:elements>
+                            <lattice:element>
+                                <lattice:name>EXTREF</lattice:name>
+                                <lattice:type>EXTREF</lattice:type>
+                                <lattice:attributes>
+                                    <lattice:attribute lattice:name="ElementDrag">true</lattice:attribute>
+                                    <lattice:attribute lattice:name="ElementHide">false</lattice:attribute>
+                                    <lattice:attribute lattice:name="ElementType">EXTREF</lattice:attribute>
+                                    <lattice:attribute lattice:name="Locate">4</lattice:attribute>
+                                </lattice:attributes>
+                            </lattice:element>
+                        </lattice:elements>
+                        <lattice:lpc>
+                            <lattice:lpcsection lattice:name="Device"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Family</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">ecp5um</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>OperatingCondition</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Package</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">CABGA756</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PartName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F-8BG756C</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PartType</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SpeedGrade</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Status</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">P</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="IP"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">EXTREF</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreRevision</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1.1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreStatus</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreType</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Date</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">05/13/2019</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ModuleName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">extref</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SourceFormat</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">vhdl</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Time</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">09:10:11</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>VendorName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="Parameters"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Destination</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>EDIF</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>EXTREFDCBIAS</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>EXTREFTERMRES</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">50 ohms</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Expression</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">BusA(0 to 7)</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>IO</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Order</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>VHDL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Verilog</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                        </lattice:lpc>
+                        <lattice:groups>
+                            <lattice:group>
+                                <lattice:name>EXTREF</lattice:name>
+                                <lattice:category>1</lattice:category>
+                                <lattice:attributes>
+                                    <lattice:attribute lattice:name="GroupDrag">true</lattice:attribute>
+                                    <lattice:attribute lattice:name="GroupHide">false</lattice:attribute>
+                                    <lattice:attribute lattice:name="GroupType">EXTREF</lattice:attribute>
+                                </lattice:attributes>
+                                <lattice:elementref>EXTREF</lattice:elementref>
+                            </lattice:group>
+                        </lattice:groups>
+                    </spirit:vendorExtensions>
+                </spirit:componentRef>
+            </spirit:componentInstance>
+            <spirit:componentInstance>
+                <spirit:instanceName>sgmii_ecp5</spirit:instanceName>
+                <spirit:componentRef>
+                    <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
+                    <spirit:library>LEGACY</spirit:library>
+                    <spirit:name>PCS</spirit:name>
+                    <spirit:version>8.2</spirit:version>
+                    <spirit:fileSets>
+                        <spirit:fileset>
+                            <spirit:name>Diamond_Simulation</spirit:name>
+                            <spirit:group>simulation</spirit:group>
+                            <spirit:file>
+                                <spirit:name>./sgmii_ecp5/sgmii_ecp5_softlogic.v</spirit:name>
+                                <spirit:fileType>verilogSource</spirit:fileType>
+                            </spirit:file>
+                            <spirit:file>
+                                <spirit:name>./sgmii_ecp5/sgmii_ecp5.vhd</spirit:name>
+                                <spirit:fileType>vhdlSource</spirit:fileType>
+                            </spirit:file>
+                        </spirit:fileset>
+                        <spirit:fileset>
+                            <spirit:name>Diamond_Synthesis</spirit:name>
+                            <spirit:group>synthesis</spirit:group>
+                            <spirit:file>
+                                <spirit:name>./sgmii_ecp5/sgmii_ecp5_softlogic.v</spirit:name>
+                                <spirit:fileType>verilogSource</spirit:fileType>
+                            </spirit:file>
+                            <spirit:file>
+                                <spirit:name>./sgmii_ecp5/sgmii_ecp5.vhd</spirit:name>
+                                <spirit:fileType>vhdlSource</spirit:fileType>
+                            </spirit:file>
+                        </spirit:fileset>
+                    </spirit:fileSets>
+                    <spirit:componentGenerators>
+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>Configuration</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
+                            <spirit:group>CONFIG</spirit:group>
+                        </spirit:componentGenerator>
+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>CreateNGD</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_ngd.tcl</spirit:generatorExe>
+                            <spirit:group>CONFIG</spirit:group>
+                        </spirit:componentGenerator>
+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>Generation</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
+                            <spirit:group>GENERATE</spirit:group>
+                        </spirit:componentGenerator>
+                    </spirit:componentGenerators>
+                    <spirit:model>
+                        <spirit:views/>
+                        <spirit:ports>
+                            <spirit:port>
+                                <spirit:name>ctc_del_s</spirit:name>
+                                <spirit:displayName>ctc_del_s</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>ctc_ins_s</spirit:name>
+                                <spirit:displayName>ctc_ins_s</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>ctc_orun_s</spirit:name>
+                                <spirit:displayName>ctc_orun_s</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>ctc_urun_s</spirit:name>
+                                <spirit:displayName>ctc_urun_s</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>cyawstn</spirit:name>
+                                <spirit:displayName>cyawstn</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>hdinn</spirit:name>
+                                <spirit:displayName>hdinn</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                                <spirit:vendorExtensions>
+                                    <lattice:attributes>
+                                        <lattice:attribute lattice:name="PadPin">true</lattice:attribute>
+                                    </lattice:attributes>
+                                </spirit:vendorExtensions>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>hdinp</spirit:name>
+                                <spirit:displayName>hdinp</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                                <spirit:vendorExtensions>
+                                    <lattice:attributes>
+                                        <lattice:attribute lattice:name="PadPin">true</lattice:attribute>
+                                    </lattice:attributes>
+                                </spirit:vendorExtensions>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>hdoutn</spirit:name>
+                                <spirit:displayName>hdoutn</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                                <spirit:vendorExtensions>
+                                    <lattice:attributes>
+                                        <lattice:attribute lattice:name="PadPin">true</lattice:attribute>
+                                    </lattice:attributes>
+                                </spirit:vendorExtensions>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>hdoutp</spirit:name>
+                                <spirit:displayName>hdoutp</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                                <spirit:vendorExtensions>
+                                    <lattice:attributes>
+                                        <lattice:attribute lattice:name="PadPin">true</lattice:attribute>
+                                    </lattice:attributes>
+                                </spirit:vendorExtensions>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>lsm_status_s</spirit:name>
+                                <spirit:displayName>lsm_status_s</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>pll_lol</spirit:name>
+                                <spirit:displayName>pll_lol</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>pll_refclki</spirit:name>
+                                <spirit:displayName>pll_refclki</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rsl_disable</spirit:name>
+                                <spirit:displayName>rsl_disable</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rsl_rst</spirit:name>
+                                <spirit:displayName>rsl_rst</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rsl_rx_rdy</spirit:name>
+                                <spirit:displayName>rsl_rx_rdy</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rsl_tx_rdy</spirit:name>
+                                <spirit:displayName>rsl_tx_rdy</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rst_dual_c</spirit:name>
+                                <spirit:displayName>rst_dual_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_cdr_lol_s</spirit:name>
+                                <spirit:displayName>rx_cdr_lol_s</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_los_low_s</spirit:name>
+                                <spirit:displayName>rx_los_low_s</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_pcs_rst_c</spirit:name>
+                                <spirit:displayName>rx_pcs_rst_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_pwrup_c</spirit:name>
+                                <spirit:displayName>rx_pwrup_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_serdes_rst_c</spirit:name>
+                                <spirit:displayName>rx_serdes_rst_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rxrefclk</spirit:name>
+                                <spirit:displayName>rxrefclk</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_en</spirit:name>
+                                <spirit:displayName>sci_en</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_en_dual</spirit:name>
+                                <spirit:displayName>sci_en_dual</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_int</spirit:name>
+                                <spirit:displayName>sci_int</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_rd</spirit:name>
+                                <spirit:displayName>sci_rd</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_sel</spirit:name>
+                                <spirit:displayName>sci_sel</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_sel_dual</spirit:name>
+                                <spirit:displayName>sci_sel_dual</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_wrn</spirit:name>
+                                <spirit:displayName>sci_wrn</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>serdes_pdb</spirit:name>
+                                <spirit:displayName>serdes_pdb</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>serdes_rst_dual_c</spirit:name>
+                                <spirit:displayName>serdes_rst_dual_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>signal_detect_c</spirit:name>
+                                <spirit:displayName>signal_detect_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sli_rst</spirit:name>
+                                <spirit:displayName>sli_rst</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                                <spirit:vendorExtensions>
+                                    <lattice:attributes>
+                                        <lattice:attribute lattice:name="Hide">true</lattice:attribute>
+                                    </lattice:attributes>
+                                </spirit:vendorExtensions>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_pclk</spirit:name>
+                                <spirit:displayName>tx_pclk</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_pcs_rst_c</spirit:name>
+                                <spirit:displayName>tx_pcs_rst_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_pwrup_c</spirit:name>
+                                <spirit:displayName>tx_pwrup_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_serdes_rst_c</spirit:name>
+                                <spirit:displayName>tx_serdes_rst_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>txi_clk</spirit:name>
+                                <spirit:displayName>txi_clk</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_cv_err</spirit:name>
+                                <spirit:displayName>rx_cv_err</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>0</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_disp_err</spirit:name>
+                                <spirit:displayName>rx_disp_err</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>0</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_k</spirit:name>
+                                <spirit:displayName>rx_k</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>0</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rxdata</spirit:name>
+                                <spirit:displayName>rxdata</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>7</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_addr</spirit:name>
+                                <spirit:displayName>sci_addr</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>5</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_rddata</spirit:name>
+                                <spirit:displayName>sci_rddata</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>7</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_wrdata</spirit:name>
+                                <spirit:displayName>sci_wrdata</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>7</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_disp_correct</spirit:name>
+                                <spirit:displayName>tx_disp_correct</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>0</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_k</spirit:name>
+                                <spirit:displayName>tx_k</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>0</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>txdata</spirit:name>
+                                <spirit:displayName>txdata</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>7</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>xmit</spirit:name>
+                                <spirit:displayName>xmit</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>0</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                        </spirit:ports>
+                    </spirit:model>
+                    <spirit:vendorExtensions>
+                        <lattice:synthesis>synplify</lattice:synthesis>
+                        <lattice:modified>2019-05-13.10:35:48 AM</lattice:modified>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+                            <lattice:attribute lattice:name="BBox">false</lattice:attribute>
+                            <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+                            <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute>
+                            <lattice:attribute lattice:name="DCU_RXREFCLK">DCU1_EXTREF</lattice:attribute>
+                            <lattice:attribute lattice:name="DCU_TXREFCLK">DCU1_EXTREF</lattice:attribute>
+                            <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+                            <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+                        </lattice:attributes>
+                        <lattice:elements>
+                            <lattice:element>
+                                <lattice:name>Lane0</lattice:name>
+                                <lattice:type>DCUCHANNEL</lattice:type>
+                                <lattice:attributes>
+                                    <lattice:attribute lattice:name="ElementDrag">true</lattice:attribute>
+                                    <lattice:attribute lattice:name="ElementHide">false</lattice:attribute>
+                                    <lattice:attribute lattice:name="ElementType">DCUCHANNEL</lattice:attribute>
+                                    <lattice:attribute lattice:name="Locate">9</lattice:attribute>
+                                </lattice:attributes>
+                            </lattice:element>
+                        </lattice:elements>
+                        <lattice:lpc>
+                            <lattice:lpcsection lattice:name="Device"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Family</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">ecp5um</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>OperatingCondition</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Package</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">CABGA756</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PartName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F-8BG756C</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PartType</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SpeedGrade</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Status</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">P</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="IP"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">PCS</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreRevision</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">8.2</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreStatus</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreType</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Date</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">05/13/2019</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ModuleName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">sgmii_ecp5</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SourceFormat</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">VHDL</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Time</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">09:09:01</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>VendorName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="Parameters"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>;ACHARA</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>;ACHARB</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>;ACHARM</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>;RXMCAENABLE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CDRLOLACTION</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Full Recalibration</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CDRLOLRANGE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CDR_MAX_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1.25</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CDR_MULT</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">10X</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CDR_REF_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">125.0000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CH_MODE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Rx and Tx</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Destination</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>EDIF</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Expression</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">BusA(0 to 7)</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>IO</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>IO_TYPE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">GbE</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>LEQ</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>LOOPBACK</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>LOSPORT</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>NUM_CHS</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Order</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PPORT_RX_RDY</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PPORT_TX_RDY</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PROTOCOL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">GbE</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PWAIT_RX_RDY</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">3000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PWAIT_TX_RDY</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">3000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RCSRC</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>REFCLK_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">125.0000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RSTSEQSEL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RX8B10B</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCOMMAA</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1010000011</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCOMMAB</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0101111100</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCOMMAM</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1111111111</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCOUPLING</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">AC</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCTC</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCTCBYTEN</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCTCBYTEN1</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCTCBYTEN2</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1 BCH</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCTCBYTEN3</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0 50H</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCTCMATCHPATTERN</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">M2-S2</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXDIFFTERM</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">50 ohms</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXFIFO_ENABLE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXINVPOL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Non-invert</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXLDR</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Off</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXLOSTHRESHOLD</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">2</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXLSM</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXSC</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">K28P5</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXWA</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Barrel Shift</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RX_DATA_WIDTH</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">8/10-Bit</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RX_FICLK_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">125.0000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RX_LINE_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1.2500</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RX_RATE_DIV</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Full Rate</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SCIPORT</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SOFTLOL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TX8B10B</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXAMPLITUDE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1100</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXDEPOST</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXDEPRE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXDIFFTERM</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">50 ohms</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXFIFO_ENABLE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXINVPOL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Non-invert</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXLDR</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Off</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXPLLLOLTHRESHOLD</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXPLLMULT</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">10X</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TX_DATA_WIDTH</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">8/10-Bit</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TX_FICLK_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">125.0000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TX_LINE_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1.2500</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TX_MAX_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1.25</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TX_RATE_DIV</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Full Rate</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>VHDL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Verilog</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="FilesGenerated"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>sgmii_ecp5.pp</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">pp</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>sgmii_ecp5.sym</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">sym</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>sgmii_ecp5.tft</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">tft</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>sgmii_ecp5.txt</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">pcs_module</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                        </lattice:lpc>
+                        <lattice:groups>
+                            <lattice:group>
+                                <lattice:name>DCUCHANNEL</lattice:name>
+                                <lattice:category>1</lattice:category>
+                                <lattice:attributes>
+                                    <lattice:attribute lattice:name="GroupDrag">true</lattice:attribute>
+                                    <lattice:attribute lattice:name="GroupHide">false</lattice:attribute>
+                                    <lattice:attribute lattice:name="GroupType">DCUCHANNEL</lattice:attribute>
+                                </lattice:attributes>
+                                <lattice:elementref>Lane0</lattice:elementref>
+                            </lattice:group>
+                        </lattice:groups>
+                    </spirit:vendorExtensions>
+                </spirit:componentRef>
+            </spirit:componentInstance>
+        </spirit:componentInstances>
+        <spirit:adHocConnections>
+            <spirit:adHocConnection>
+                <spirit:name>extref_refclkn</spirit:name>
+                <spirit:displayName>extref_refclkn</spirit:displayName>
+                <spirit:vendorExtensions>
+                    <lattice:attributes>
+                        <lattice:attribute lattice:name="export">sys_yes</lattice:attribute>
+                    </lattice:attributes>
+                </spirit:vendorExtensions>
+                <spirit:internalPortReference spirit:portRef="refclkn" spirit:componentRef="extref"/>
+                <spirit:externalPortReference spirit:portRef="extref_refclkn"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>extref_refclko</spirit:name>
+                <spirit:displayName>extref_refclko</spirit:displayName>
+                <spirit:description>extref_refclko</spirit:description>
+                <spirit:vendorExtensions>
+                    <lattice:attributes>
+                        <lattice:attribute lattice:name="export">sys_no</lattice:attribute>
+                        <lattice:attribute lattice:name="type">internal</lattice:attribute>
+                    </lattice:attributes>
+                </spirit:vendorExtensions>
+                <spirit:internalPortReference spirit:portRef="refclko" spirit:componentRef="extref"/>
+                <spirit:internalPortReference spirit:portRef="rxrefclk" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:internalPortReference spirit:portRef="pll_refclki" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>extref_refclkp</spirit:name>
+                <spirit:displayName>extref_refclkp</spirit:displayName>
+                <spirit:vendorExtensions>
+                    <lattice:attributes>
+                        <lattice:attribute lattice:name="export">sys_yes</lattice:attribute>
+                    </lattice:attributes>
+                </spirit:vendorExtensions>
+                <spirit:internalPortReference spirit:portRef="refclkp" spirit:componentRef="extref"/>
+                <spirit:externalPortReference spirit:portRef="extref_refclkp"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_ctc_del_s</spirit:name>
+                <spirit:displayName>sgmii_ecp5_ctc_del_s</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="ctc_del_s" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_ctc_del_s"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_ctc_ins_s</spirit:name>
+                <spirit:displayName>sgmii_ecp5_ctc_ins_s</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="ctc_ins_s" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_ctc_ins_s"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_ctc_orun_s</spirit:name>
+                <spirit:displayName>sgmii_ecp5_ctc_orun_s</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="ctc_orun_s" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_ctc_orun_s"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_ctc_urun_s</spirit:name>
+                <spirit:displayName>sgmii_ecp5_ctc_urun_s</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="ctc_urun_s" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_ctc_urun_s"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_cyawstn</spirit:name>
+                <spirit:displayName>sgmii_ecp5_cyawstn</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="cyawstn" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_cyawstn"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_hdinn</spirit:name>
+                <spirit:displayName>sgmii_ecp5_hdinn</spirit:displayName>
+                <spirit:vendorExtensions>
+                    <lattice:attributes>
+                        <lattice:attribute lattice:name="export">sys_yes</lattice:attribute>
+                    </lattice:attributes>
+                </spirit:vendorExtensions>
+                <spirit:internalPortReference spirit:portRef="hdinn" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_hdinn"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_hdinp</spirit:name>
+                <spirit:displayName>sgmii_ecp5_hdinp</spirit:displayName>
+                <spirit:vendorExtensions>
+                    <lattice:attributes>
+                        <lattice:attribute lattice:name="export">sys_yes</lattice:attribute>
+                    </lattice:attributes>
+                </spirit:vendorExtensions>
+                <spirit:internalPortReference spirit:portRef="hdinp" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_hdinp"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_hdoutn</spirit:name>
+                <spirit:displayName>sgmii_ecp5_hdoutn</spirit:displayName>
+                <spirit:vendorExtensions>
+                    <lattice:attributes>
+                        <lattice:attribute lattice:name="export">sys_yes</lattice:attribute>
+                    </lattice:attributes>
+                </spirit:vendorExtensions>
+                <spirit:internalPortReference spirit:portRef="hdoutn" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_hdoutn"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_hdoutp</spirit:name>
+                <spirit:displayName>sgmii_ecp5_hdoutp</spirit:displayName>
+                <spirit:vendorExtensions>
+                    <lattice:attributes>
+                        <lattice:attribute lattice:name="export">sys_yes</lattice:attribute>
+                    </lattice:attributes>
+                </spirit:vendorExtensions>
+                <spirit:internalPortReference spirit:portRef="hdoutp" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_hdoutp"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_lsm_status_s</spirit:name>
+                <spirit:displayName>sgmii_ecp5_lsm_status_s</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="lsm_status_s" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_lsm_status_s"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_pll_lol</spirit:name>
+                <spirit:displayName>sgmii_ecp5_pll_lol</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="pll_lol" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_pll_lol"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rsl_disable</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rsl_disable</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rsl_disable" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rsl_disable"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rsl_rst</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rsl_rst</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rsl_rst" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rsl_rst"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rsl_rx_rdy</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rsl_rx_rdy</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rsl_rx_rdy" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rsl_rx_rdy"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rsl_tx_rdy</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rsl_tx_rdy</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rsl_tx_rdy" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rsl_tx_rdy"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rst_dual_c</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rst_dual_c</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rst_dual_c" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rst_dual_c"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rx_cdr_lol_s</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rx_cdr_lol_s</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rx_cdr_lol_s" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rx_cdr_lol_s"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rx_los_low_s</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rx_los_low_s</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rx_los_low_s" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rx_los_low_s"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rx_pcs_rst_c</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rx_pcs_rst_c</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rx_pcs_rst_c" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rx_pcs_rst_c"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rx_pwrup_c</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rx_pwrup_c</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rx_pwrup_c" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rx_pwrup_c"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rx_serdes_rst_c</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rx_serdes_rst_c</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rx_serdes_rst_c" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rx_serdes_rst_c"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_en</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_en</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_en" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_en"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_en_dual</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_en_dual</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_en_dual" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_en_dual"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_int</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_int</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_int" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_int"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_rd</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_rd</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_rd" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_rd"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_sel</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_sel</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_sel" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_sel"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_sel_dual</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_sel_dual</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_sel_dual" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_sel_dual"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_wrn</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_wrn</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_wrn" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_wrn"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_serdes_pdb</spirit:name>
+                <spirit:displayName>sgmii_ecp5_serdes_pdb</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="serdes_pdb" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_serdes_pdb"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_serdes_rst_dual_c</spirit:name>
+                <spirit:displayName>sgmii_ecp5_serdes_rst_dual_c</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="serdes_rst_dual_c" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_serdes_rst_dual_c"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_signal_detect_c</spirit:name>
+                <spirit:displayName>sgmii_ecp5_signal_detect_c</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="signal_detect_c" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_signal_detect_c"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_tx_pclk</spirit:name>
+                <spirit:displayName>sgmii_ecp5_tx_pclk</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="tx_pclk" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_tx_pclk"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_tx_pcs_rst_c</spirit:name>
+                <spirit:displayName>sgmii_ecp5_tx_pcs_rst_c</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="tx_pcs_rst_c" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_tx_pcs_rst_c"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_tx_pwrup_c</spirit:name>
+                <spirit:displayName>sgmii_ecp5_tx_pwrup_c</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="tx_pwrup_c" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_tx_pwrup_c"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_tx_serdes_rst_c</spirit:name>
+                <spirit:displayName>sgmii_ecp5_tx_serdes_rst_c</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="tx_serdes_rst_c" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_tx_serdes_rst_c"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_txi_clk</spirit:name>
+                <spirit:displayName>sgmii_ecp5_txi_clk</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="txi_clk" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_txi_clk"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rx_cv_err</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rx_cv_err</spirit:displayName>
+                <spirit:internalPortReference spirit:right="0" spirit:portRef="rx_cv_err" spirit:componentRef="sgmii_ecp5" spirit:left="0"/>
+                <spirit:externalPortReference spirit:right="0" spirit:portRef="sgmii_ecp5_rx_cv_err" spirit:left="0"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rx_cv_err[0]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rx_cv_err[0]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rx_cv_err[0]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rx_cv_err[0]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rx_disp_err</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rx_disp_err</spirit:displayName>
+                <spirit:internalPortReference spirit:right="0" spirit:portRef="rx_disp_err" spirit:componentRef="sgmii_ecp5" spirit:left="0"/>
+                <spirit:externalPortReference spirit:right="0" spirit:portRef="sgmii_ecp5_rx_disp_err" spirit:left="0"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rx_disp_err[0]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rx_disp_err[0]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rx_disp_err[0]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rx_disp_err[0]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rx_k</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rx_k</spirit:displayName>
+                <spirit:internalPortReference spirit:right="0" spirit:portRef="rx_k" spirit:componentRef="sgmii_ecp5" spirit:left="0"/>
+                <spirit:externalPortReference spirit:right="0" spirit:portRef="sgmii_ecp5_rx_k" spirit:left="0"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rx_k[0]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rx_k[0]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rx_k[0]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rx_k[0]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rxdata</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rxdata</spirit:displayName>
+                <spirit:internalPortReference spirit:right="0" spirit:portRef="rxdata" spirit:componentRef="sgmii_ecp5" spirit:left="7"/>
+                <spirit:externalPortReference spirit:right="0" spirit:portRef="sgmii_ecp5_rxdata" spirit:left="7"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rxdata[0]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rxdata[0]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rxdata[0]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rxdata[0]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rxdata[1]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rxdata[1]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rxdata[1]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rxdata[1]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rxdata[2]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rxdata[2]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rxdata[2]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rxdata[2]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rxdata[3]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rxdata[3]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rxdata[3]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rxdata[3]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rxdata[4]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rxdata[4]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rxdata[4]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rxdata[4]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rxdata[5]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rxdata[5]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rxdata[5]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rxdata[5]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rxdata[6]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rxdata[6]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rxdata[6]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rxdata[6]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rxdata[7]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rxdata[7]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rxdata[7]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rxdata[7]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_addr</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_addr</spirit:displayName>
+                <spirit:internalPortReference spirit:right="0" spirit:portRef="sci_addr" spirit:componentRef="sgmii_ecp5" spirit:left="5"/>
+                <spirit:externalPortReference spirit:right="0" spirit:portRef="sgmii_ecp5_sci_addr" spirit:left="5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_addr[0]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_addr[0]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_addr[0]"/>
+                <spirit:internalPortReference spirit:portRef="sci_addr[0]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_addr[1]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_addr[1]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_addr[1]"/>
+                <spirit:internalPortReference spirit:portRef="sci_addr[1]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_addr[2]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_addr[2]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_addr[2]"/>
+                <spirit:internalPortReference spirit:portRef="sci_addr[2]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_addr[3]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_addr[3]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_addr[3]"/>
+                <spirit:internalPortReference spirit:portRef="sci_addr[3]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_addr[4]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_addr[4]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_addr[4]"/>
+                <spirit:internalPortReference spirit:portRef="sci_addr[4]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_addr[5]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_addr[5]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_addr[5]"/>
+                <spirit:internalPortReference spirit:portRef="sci_addr[5]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_rddata</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_rddata</spirit:displayName>
+                <spirit:internalPortReference spirit:right="0" spirit:portRef="sci_rddata" spirit:componentRef="sgmii_ecp5" spirit:left="7"/>
+                <spirit:externalPortReference spirit:right="0" spirit:portRef="sgmii_ecp5_sci_rddata" spirit:left="7"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_rddata[0]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_rddata[0]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_rddata[0]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_rddata[0]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_rddata[1]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_rddata[1]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_rddata[1]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_rddata[1]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_rddata[2]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_rddata[2]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_rddata[2]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_rddata[2]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_rddata[3]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_rddata[3]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_rddata[3]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_rddata[3]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_rddata[4]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_rddata[4]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_rddata[4]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_rddata[4]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_rddata[5]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_rddata[5]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_rddata[5]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_rddata[5]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_rddata[6]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_rddata[6]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_rddata[6]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_rddata[6]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_rddata[7]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_rddata[7]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_rddata[7]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_rddata[7]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_wrdata</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_wrdata</spirit:displayName>
+                <spirit:internalPortReference spirit:right="0" spirit:portRef="sci_wrdata" spirit:componentRef="sgmii_ecp5" spirit:left="7"/>
+                <spirit:externalPortReference spirit:right="0" spirit:portRef="sgmii_ecp5_sci_wrdata" spirit:left="7"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_wrdata[0]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_wrdata[0]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_wrdata[0]"/>
+                <spirit:internalPortReference spirit:portRef="sci_wrdata[0]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_wrdata[1]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_wrdata[1]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_wrdata[1]"/>
+                <spirit:internalPortReference spirit:portRef="sci_wrdata[1]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_wrdata[2]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_wrdata[2]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_wrdata[2]"/>
+                <spirit:internalPortReference spirit:portRef="sci_wrdata[2]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_wrdata[3]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_wrdata[3]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_wrdata[3]"/>
+                <spirit:internalPortReference spirit:portRef="sci_wrdata[3]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_wrdata[4]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_wrdata[4]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_wrdata[4]"/>
+                <spirit:internalPortReference spirit:portRef="sci_wrdata[4]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_wrdata[5]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_wrdata[5]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_wrdata[5]"/>
+                <spirit:internalPortReference spirit:portRef="sci_wrdata[5]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_wrdata[6]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_wrdata[6]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_wrdata[6]"/>
+                <spirit:internalPortReference spirit:portRef="sci_wrdata[6]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_wrdata[7]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_wrdata[7]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_wrdata[7]"/>
+                <spirit:internalPortReference spirit:portRef="sci_wrdata[7]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_tx_disp_correct</spirit:name>
+                <spirit:displayName>sgmii_ecp5_tx_disp_correct</spirit:displayName>
+                <spirit:internalPortReference spirit:right="0" spirit:portRef="tx_disp_correct" spirit:componentRef="sgmii_ecp5" spirit:left="0"/>
+                <spirit:externalPortReference spirit:right="0" spirit:portRef="sgmii_ecp5_tx_disp_correct" spirit:left="0"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_tx_disp_correct[0]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_tx_disp_correct[0]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_tx_disp_correct[0]"/>
+                <spirit:internalPortReference spirit:portRef="tx_disp_correct[0]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_tx_k</spirit:name>
+                <spirit:displayName>sgmii_ecp5_tx_k</spirit:displayName>
+                <spirit:internalPortReference spirit:right="0" spirit:portRef="tx_k" spirit:componentRef="sgmii_ecp5" spirit:left="0"/>
+                <spirit:externalPortReference spirit:right="0" spirit:portRef="sgmii_ecp5_tx_k" spirit:left="0"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_tx_k[0]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_tx_k[0]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_tx_k[0]"/>
+                <spirit:internalPortReference spirit:portRef="tx_k[0]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_txdata</spirit:name>
+                <spirit:displayName>sgmii_ecp5_txdata</spirit:displayName>
+                <spirit:internalPortReference spirit:right="0" spirit:portRef="txdata" spirit:componentRef="sgmii_ecp5" spirit:left="7"/>
+                <spirit:externalPortReference spirit:right="0" spirit:portRef="sgmii_ecp5_txdata" spirit:left="7"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_txdata[0]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_txdata[0]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_txdata[0]"/>
+                <spirit:internalPortReference spirit:portRef="txdata[0]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_txdata[1]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_txdata[1]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_txdata[1]"/>
+                <spirit:internalPortReference spirit:portRef="txdata[1]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_txdata[2]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_txdata[2]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_txdata[2]"/>
+                <spirit:internalPortReference spirit:portRef="txdata[2]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_txdata[3]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_txdata[3]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_txdata[3]"/>
+                <spirit:internalPortReference spirit:portRef="txdata[3]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_txdata[4]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_txdata[4]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_txdata[4]"/>
+                <spirit:internalPortReference spirit:portRef="txdata[4]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_txdata[5]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_txdata[5]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_txdata[5]"/>
+                <spirit:internalPortReference spirit:portRef="txdata[5]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_txdata[6]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_txdata[6]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_txdata[6]"/>
+                <spirit:internalPortReference spirit:portRef="txdata[6]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_txdata[7]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_txdata[7]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_txdata[7]"/>
+                <spirit:internalPortReference spirit:portRef="txdata[7]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_xmit</spirit:name>
+                <spirit:displayName>sgmii_ecp5_xmit</spirit:displayName>
+                <spirit:internalPortReference spirit:right="0" spirit:portRef="xmit" spirit:componentRef="sgmii_ecp5" spirit:left="0"/>
+                <spirit:externalPortReference spirit:right="0" spirit:portRef="sgmii_ecp5_xmit" spirit:left="0"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_xmit[0]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_xmit[0]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_xmit[0]"/>
+                <spirit:internalPortReference spirit:portRef="xmit[0]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+        </spirit:adHocConnections>
+    </spirit:design>
+</lattice:project>

diff --git a/gbe/cores/GbePcsExtrefclk/GbePcsExtrefclk.vhd b/gbe/cores/GbePcsExtrefclk/GbePcsExtrefclk.vhd
new file mode 100644 (file)
index 0000000..a9521ee
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/GbePcsExtrefclk.vhd
@@ -0,0 +1,179 @@
+
+
+
+--
+-- Verific VHDL Description of module GbePcsExtrefclk
+--
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+entity GbePcsExtrefclk is
+    port (sgmii_ecp5_rx_cv_err: out std_logic_vector(0 downto 0);
+        sgmii_ecp5_rx_disp_err: out std_logic_vector(0 downto 0);
+        sgmii_ecp5_rx_k: out std_logic_vector(0 downto 0);
+        sgmii_ecp5_rxdata: out std_logic_vector(7 downto 0);
+        sgmii_ecp5_sci_addr: in std_logic_vector(5 downto 0);
+        sgmii_ecp5_sci_rddata: out std_logic_vector(7 downto 0);
+        sgmii_ecp5_sci_wrdata: in std_logic_vector(7 downto 0);
+        sgmii_ecp5_tx_disp_correct: in std_logic_vector(0 downto 0);
+        sgmii_ecp5_tx_k: in std_logic_vector(0 downto 0);
+        sgmii_ecp5_txdata: in std_logic_vector(7 downto 0);
+        sgmii_ecp5_xmit: in std_logic_vector(0 downto 0);
+        extref_refclkn: in std_logic;
+        extref_refclkp: in std_logic;
+        sgmii_ecp5_ctc_del_s: out std_logic;
+        sgmii_ecp5_ctc_ins_s: out std_logic;
+        sgmii_ecp5_ctc_orun_s: out std_logic;
+        sgmii_ecp5_ctc_urun_s: out std_logic;
+        sgmii_ecp5_cyawstn: in std_logic;
+        sgmii_ecp5_hdinn: in std_logic;
+        sgmii_ecp5_hdinp: in std_logic;
+        sgmii_ecp5_hdoutn: out std_logic;
+        sgmii_ecp5_hdoutp: out std_logic;
+        sgmii_ecp5_lsm_status_s: out std_logic;
+        sgmii_ecp5_pll_lol: out std_logic;
+        sgmii_ecp5_rsl_disable: in std_logic;
+        sgmii_ecp5_rsl_rst: in std_logic;
+        sgmii_ecp5_rsl_rx_rdy: out std_logic;
+        sgmii_ecp5_rsl_tx_rdy: out std_logic;
+        sgmii_ecp5_rst_dual_c: in std_logic;
+        sgmii_ecp5_rx_cdr_lol_s: out std_logic;
+        sgmii_ecp5_rx_los_low_s: out std_logic;
+        sgmii_ecp5_rx_pcs_rst_c: in std_logic;
+        sgmii_ecp5_rx_pwrup_c: in std_logic;
+        sgmii_ecp5_rx_serdes_rst_c: in std_logic;
+        sgmii_ecp5_sci_en: in std_logic;
+        sgmii_ecp5_sci_en_dual: in std_logic;
+        sgmii_ecp5_sci_int: out std_logic;
+        sgmii_ecp5_sci_rd: in std_logic;
+        sgmii_ecp5_sci_sel: in std_logic;
+        sgmii_ecp5_sci_sel_dual: in std_logic;
+        sgmii_ecp5_sci_wrn: in std_logic;
+        sgmii_ecp5_serdes_pdb: in std_logic;
+        sgmii_ecp5_serdes_rst_dual_c: in std_logic;
+        sgmii_ecp5_signal_detect_c: in std_logic;
+        sgmii_ecp5_tx_pclk: out std_logic;
+        sgmii_ecp5_tx_pcs_rst_c: in std_logic;
+        sgmii_ecp5_tx_pwrup_c: in std_logic;
+        sgmii_ecp5_tx_serdes_rst_c: in std_logic;
+        sgmii_ecp5_txi_clk: in std_logic
+    );
+    
+end entity GbePcsExtrefclk; -- sbp_module=true 
+
+architecture GbePcsExtrefclk of GbePcsExtrefclk is 
+    component extref is
+        port (refclkn: in std_logic;
+            refclko: out std_logic;
+            refclkp: in std_logic
+        );
+        
+    end component extref; -- not_need_bbox=true 
+    
+    
+    component sgmii_ecp5 is
+        port (rx_cv_err: out std_logic_vector(0 downto 0);
+            rx_disp_err: out std_logic_vector(0 downto 0);
+            rx_k: out std_logic_vector(0 downto 0);
+            rxdata: out std_logic_vector(7 downto 0);
+            sci_addr: in std_logic_vector(5 downto 0);
+            sci_rddata: out std_logic_vector(7 downto 0);
+            sci_wrdata: in std_logic_vector(7 downto 0);
+            tx_disp_correct: in std_logic_vector(0 downto 0);
+            tx_k: in std_logic_vector(0 downto 0);
+            txdata: in std_logic_vector(7 downto 0);
+            xmit: in std_logic_vector(0 downto 0);
+            ctc_del_s: out std_logic;
+            ctc_ins_s: out std_logic;
+            ctc_orun_s: out std_logic;
+            ctc_urun_s: out std_logic;
+            cyawstn: in std_logic;
+            hdinn: in std_logic;
+            hdinp: in std_logic;
+            hdoutn: out std_logic;
+            hdoutp: out std_logic;
+            lsm_status_s: out std_logic;
+            pll_lol: out std_logic;
+            pll_refclki: in std_logic;
+            rsl_disable: in std_logic;
+            rsl_rst: in std_logic;
+            rsl_rx_rdy: out std_logic;
+            rsl_tx_rdy: out std_logic;
+            rst_dual_c: in std_logic;
+            rx_cdr_lol_s: out std_logic;
+            rx_los_low_s: out std_logic;
+            rx_pcs_rst_c: in std_logic;
+            rx_pwrup_c: in std_logic;
+            rx_serdes_rst_c: in std_logic;
+            rxrefclk: in std_logic;
+            sci_en: in std_logic;
+            sci_en_dual: in std_logic;
+            sci_int: out std_logic;
+            sci_rd: in std_logic;
+            sci_sel: in std_logic;
+            sci_sel_dual: in std_logic;
+            sci_wrn: in std_logic;
+            serdes_pdb: in std_logic;
+            serdes_rst_dual_c: in std_logic;
+            signal_detect_c: in std_logic;
+            sli_rst: in std_logic;
+            tx_pclk: out std_logic;
+            tx_pcs_rst_c: in std_logic;
+            tx_pwrup_c: in std_logic;
+            tx_serdes_rst_c: in std_logic;
+            txi_clk: in std_logic
+        );
+        
+    end component sgmii_ecp5; -- not_need_bbox=true 
+    
+    
+    signal extref_refclko,sli_rst_wire0,gnd : std_logic; 
+begin
+    sli_rst_wire0 <= sgmii_ecp5_serdes_rst_dual_c OR  sgmii_ecp5_tx_serdes_rst_c OR  (NOT sgmii_ecp5_serdes_pdb) OR  (NOT sgmii_ecp5_tx_pwrup_c);
+    extref_inst: component extref port map (refclkn=>extref_refclkn,refclko=>extref_refclko,
+            refclkp=>extref_refclkp);
+    sgmii_ecp5_inst: component sgmii_ecp5 port map (rx_cv_err(0)=>sgmii_ecp5_rx_cv_err(0),
+            rx_disp_err(0)=>sgmii_ecp5_rx_disp_err(0),rx_k(0)=>sgmii_ecp5_rx_k(0),
+            rxdata(7)=>sgmii_ecp5_rxdata(7),rxdata(6)=>sgmii_ecp5_rxdata(6),
+            rxdata(5)=>sgmii_ecp5_rxdata(5),rxdata(4)=>sgmii_ecp5_rxdata(4),
+            rxdata(3)=>sgmii_ecp5_rxdata(3),rxdata(2)=>sgmii_ecp5_rxdata(2),
+            rxdata(1)=>sgmii_ecp5_rxdata(1),rxdata(0)=>sgmii_ecp5_rxdata(0),
+            sci_addr(5)=>sgmii_ecp5_sci_addr(5),sci_addr(4)=>sgmii_ecp5_sci_addr(4),
+            sci_addr(3)=>sgmii_ecp5_sci_addr(3),sci_addr(2)=>sgmii_ecp5_sci_addr(2),
+            sci_addr(1)=>sgmii_ecp5_sci_addr(1),sci_addr(0)=>sgmii_ecp5_sci_addr(0),
+            sci_rddata(7)=>sgmii_ecp5_sci_rddata(7),sci_rddata(6)=>sgmii_ecp5_sci_rddata(6),
+            sci_rddata(5)=>sgmii_ecp5_sci_rddata(5),sci_rddata(4)=>sgmii_ecp5_sci_rddata(4),
+            sci_rddata(3)=>sgmii_ecp5_sci_rddata(3),sci_rddata(2)=>sgmii_ecp5_sci_rddata(2),
+            sci_rddata(1)=>sgmii_ecp5_sci_rddata(1),sci_rddata(0)=>sgmii_ecp5_sci_rddata(0),
+            sci_wrdata(7)=>sgmii_ecp5_sci_wrdata(7),sci_wrdata(6)=>sgmii_ecp5_sci_wrdata(6),
+            sci_wrdata(5)=>sgmii_ecp5_sci_wrdata(5),sci_wrdata(4)=>sgmii_ecp5_sci_wrdata(4),
+            sci_wrdata(3)=>sgmii_ecp5_sci_wrdata(3),sci_wrdata(2)=>sgmii_ecp5_sci_wrdata(2),
+            sci_wrdata(1)=>sgmii_ecp5_sci_wrdata(1),sci_wrdata(0)=>sgmii_ecp5_sci_wrdata(0),
+            tx_disp_correct(0)=>sgmii_ecp5_tx_disp_correct(0),tx_k(0)=>sgmii_ecp5_tx_k(0),
+            txdata(7)=>sgmii_ecp5_txdata(7),txdata(6)=>sgmii_ecp5_txdata(6),
+            txdata(5)=>sgmii_ecp5_txdata(5),txdata(4)=>sgmii_ecp5_txdata(4),
+            txdata(3)=>sgmii_ecp5_txdata(3),txdata(2)=>sgmii_ecp5_txdata(2),
+            txdata(1)=>sgmii_ecp5_txdata(1),txdata(0)=>sgmii_ecp5_txdata(0),
+            xmit(0)=>sgmii_ecp5_xmit(0),ctc_del_s=>sgmii_ecp5_ctc_del_s,ctc_ins_s=>sgmii_ecp5_ctc_ins_s,
+            ctc_orun_s=>sgmii_ecp5_ctc_orun_s,ctc_urun_s=>sgmii_ecp5_ctc_urun_s,
+            cyawstn=>sgmii_ecp5_cyawstn,hdinn=>sgmii_ecp5_hdinn,hdinp=>sgmii_ecp5_hdinp,
+            hdoutn=>sgmii_ecp5_hdoutn,hdoutp=>sgmii_ecp5_hdoutp,lsm_status_s=>sgmii_ecp5_lsm_status_s,
+            pll_lol=>sgmii_ecp5_pll_lol,pll_refclki=>extref_refclko,rsl_disable=>sgmii_ecp5_rsl_disable,
+            rsl_rst=>sgmii_ecp5_rsl_rst,rsl_rx_rdy=>sgmii_ecp5_rsl_rx_rdy,
+            rsl_tx_rdy=>sgmii_ecp5_rsl_tx_rdy,rst_dual_c=>sgmii_ecp5_rst_dual_c,
+            rx_cdr_lol_s=>sgmii_ecp5_rx_cdr_lol_s,rx_los_low_s=>sgmii_ecp5_rx_los_low_s,
+            rx_pcs_rst_c=>sgmii_ecp5_rx_pcs_rst_c,rx_pwrup_c=>sgmii_ecp5_rx_pwrup_c,
+            rx_serdes_rst_c=>sgmii_ecp5_rx_serdes_rst_c,rxrefclk=>extref_refclko,
+            sci_en=>sgmii_ecp5_sci_en,sci_en_dual=>sgmii_ecp5_sci_en_dual,
+            sci_int=>sgmii_ecp5_sci_int,sci_rd=>sgmii_ecp5_sci_rd,sci_sel=>sgmii_ecp5_sci_sel,
+            sci_sel_dual=>sgmii_ecp5_sci_sel_dual,sci_wrn=>sgmii_ecp5_sci_wrn,
+            serdes_pdb=>sgmii_ecp5_serdes_pdb,serdes_rst_dual_c=>sgmii_ecp5_serdes_rst_dual_c,
+            signal_detect_c=>sgmii_ecp5_signal_detect_c,sli_rst=>sli_rst_wire0,
+            tx_pclk=>sgmii_ecp5_tx_pclk,tx_pcs_rst_c=>sgmii_ecp5_tx_pcs_rst_c,
+            tx_pwrup_c=>sgmii_ecp5_tx_pwrup_c,tx_serdes_rst_c=>sgmii_ecp5_tx_serdes_rst_c,
+            txi_clk=>sgmii_ecp5_txi_clk);
+    gnd <= '0' ;
+    
+end architecture GbePcsExtrefclk; -- sbp_module=true 
+

diff --git a/gbe/cores/GbePcsExtrefclk/GbePcsExtrefclk_tmpl.v b/gbe/cores/GbePcsExtrefclk/GbePcsExtrefclk_tmpl.v
new file mode 100644 (file)
index 0000000..0876ac6
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/GbePcsExtrefclk_tmpl.v
@@ -0,0 +1,19 @@
+//Verilog instantiation template
+
+GbePcsExtrefclk _inst (.extref_refclkn(), .extref_refclkp(), .sgmii_ecp5_rx_cv_err(), 
+            .sgmii_ecp5_rx_disp_err(), .sgmii_ecp5_rx_k(), .sgmii_ecp5_rxdata(), 
+            .sgmii_ecp5_sci_addr(), .sgmii_ecp5_sci_rddata(), .sgmii_ecp5_sci_wrdata(), 
+            .sgmii_ecp5_tx_disp_correct(), .sgmii_ecp5_tx_k(), .sgmii_ecp5_txdata(), 
+            .sgmii_ecp5_xmit(), .sgmii_ecp5_ctc_del_s(), .sgmii_ecp5_ctc_ins_s(), 
+            .sgmii_ecp5_ctc_orun_s(), .sgmii_ecp5_ctc_urun_s(), .sgmii_ecp5_cyawstn(), 
+            .sgmii_ecp5_hdinn(), .sgmii_ecp5_hdinp(), .sgmii_ecp5_hdoutn(), 
+            .sgmii_ecp5_hdoutp(), .sgmii_ecp5_lsm_status_s(), .sgmii_ecp5_pll_lol(), 
+            .sgmii_ecp5_rsl_disable(), .sgmii_ecp5_rsl_rst(), .sgmii_ecp5_rsl_rx_rdy(), 
+            .sgmii_ecp5_rsl_tx_rdy(), .sgmii_ecp5_rst_dual_c(), .sgmii_ecp5_rx_cdr_lol_s(), 
+            .sgmii_ecp5_rx_los_low_s(), .sgmii_ecp5_rx_pcs_rst_c(), .sgmii_ecp5_rx_pwrup_c(), 
+            .sgmii_ecp5_rx_serdes_rst_c(), .sgmii_ecp5_sci_en(), .sgmii_ecp5_sci_en_dual(), 
+            .sgmii_ecp5_sci_int(), .sgmii_ecp5_sci_rd(), .sgmii_ecp5_sci_sel(), 
+            .sgmii_ecp5_sci_sel_dual(), .sgmii_ecp5_sci_wrn(), .sgmii_ecp5_serdes_pdb(), 
+            .sgmii_ecp5_serdes_rst_dual_c(), .sgmii_ecp5_signal_detect_c(), 
+            .sgmii_ecp5_tx_pclk(), .sgmii_ecp5_tx_pcs_rst_c(), .sgmii_ecp5_tx_pwrup_c(), 
+            .sgmii_ecp5_tx_serdes_rst_c(), .sgmii_ecp5_txi_clk());
\ No newline at end of file

diff --git a/gbe/cores/GbePcsExtrefclk/extref/extref.cmd b/gbe/cores/GbePcsExtrefclk/extref/extref.cmd
new file mode 100644 (file)
index 0000000..6dfe979
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/extref.cmd
@@ -0,0 +1,18 @@
+PROJECT: extref
+               working_path: "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results"
+               module: extref
+               verilog_file_list: "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd"
+               vlog_std_v2001: true
+               constraint_file_name: "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.fdc"
+               suffix_name: edn
+               output_file_name: extref
+               write_prf: true
+               disable_io_insertion: true
+               force_gsr: false
+               frequency: 100
+               fanout_limit: 50
+               retiming: false
+               pipe: false
+               part: LFE5UM-85F
+               speed_grade: 8
+               

diff --git a/gbe/cores/GbePcsExtrefclk/extref/extref.fdc b/gbe/cores/GbePcsExtrefclk/extref/extref.fdc
new file mode 100644 (file)
index 0000000..6fbcac9
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/extref.fdc
@@ -0,0 +1,2 @@
+###==== Start Configuration
+

diff --git a/gbe/cores/GbePcsExtrefclk/extref/extref.lpc b/gbe/cores/GbePcsExtrefclk/extref/extref.lpc
new file mode 100644 (file)
index 0000000..0365a5c
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/extref.lpc
@@ -0,0 +1,31 @@
+[Device]
+Family=ecp5um
+OperatingCondition=COM
+Package=CABGA756
+PartName=LFE5UM-85F-8BG756C
+PartType=LFE5UM-85F
+SpeedGrade=8
+Status=P
+[IP]
+CoreName=EXTREF
+CoreRevision=1.1
+CoreStatus=Demo
+CoreType=LPM
+Date=05/13/2019
+ModuleName=extref
+ParameterFileVersion=1.0
+SourceFormat=vhdl
+Time=09:10:11
+VendorName=Lattice Semiconductor Corporation
+[Parameters]
+Destination=Synplicity
+EDIF=1
+EXTREFDCBIAS=Disabled
+EXTREFTERMRES=50 ohms
+Expression=BusA(0 to 7)
+IO=0
+Order=Big Endian [MSB:LSB]
+VHDL=1
+Verilog=0
+[SYSTEMPNR]
+EXTREF=DCU1

diff --git a/gbe/cores/GbePcsExtrefclk/extref/extref.ngd b/gbe/cores/GbePcsExtrefclk/extref/extref.ngd
new file mode 100644 (file)
index 0000000..0df76d6
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/extref/extref.ngd differ

diff --git a/gbe/cores/GbePcsExtrefclk/extref/extref.ngo b/gbe/cores/GbePcsExtrefclk/extref/extref.ngo
new file mode 100644 (file)
index 0000000..6c808f3
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/extref/extref.ngo differ

diff --git a/gbe/cores/GbePcsExtrefclk/extref/extref.vhd b/gbe/cores/GbePcsExtrefclk/extref/extref.vhd
new file mode 100644 (file)
index 0000000..f65248a
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/extref.vhd
@@ -0,0 +1,40 @@
+
+--
+-- Verific VHDL Description of module EXTREFB
+--
+
+-- EXTREFB is a black-box. Cannot print a valid VHDL entity description for it
+
+--
+-- Verific VHDL Description of module extref
+--
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+library ecp5um ;
+use ecp5um.components.all ;
+
+entity extref is
+    port (refclkp: in std_logic;
+        refclkn: in std_logic;
+        refclko: out std_logic
+    );
+    
+end entity extref;
+
+architecture v1 of extref is 
+    signal n2,n1,gnd,pwr : std_logic; 
+    attribute LOC : string;
+    attribute LOC of EXTREF1_inst : label is "EXTREF1";
+begin
+    EXTREF1_inst: component EXTREFB generic map (REFCK_PWDNB=>"0b1",REFCK_RTERM=>"0b1",
+        REFCK_DCBIAS_EN=>"0b0")
+     port map (REFCLKP=>refclkp,REFCLKN=>refclkn,REFCLKO=>refclko);
+    n2 <= '1' ;
+    n1 <= '0' ;
+    gnd <= '0' ;
+    pwr <= '1' ;
+    
+end architecture v1;
+

diff --git a/gbe/cores/GbePcsExtrefclk/extref/extref_ngd.asd b/gbe/cores/GbePcsExtrefclk/extref/extref_ngd.asd
new file mode 100644 (file)
index 0000000..c265c78
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/extref_ngd.asd
@@ -0,0 +1 @@
+[ActiveSupport NGD]

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/.recordref b/gbe/cores/GbePcsExtrefclk/extref/syn_results/.recordref
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/_CMD_.CML b/gbe/cores/GbePcsExtrefclk/extref/syn_results/_CMD_.CML
new file mode 100644 (file)
index 0000000..59e765e
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/_CMD_.CML
@@ -0,0 +1 @@
+ -osyn  /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synwork/extref_comp.srs  -top  extref  -hdllog  /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/extref_compiler.srr  -encrypt  -mp  4  -verification_mode 0  -vhdl  -prodtype  synplify_pro  -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver  -encrypt  -pro  -dmgen  /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/dm  -lite -ui -fid2 -ram -sharing on -ll 2000 -autosm  -ignore_undefined_lib  -lib work /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd  -jobname  "compiler" 
\ No newline at end of file

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/_cmd._cml b/gbe/cores/GbePcsExtrefclk/extref/syn_results/_cmd._cml
new file mode 100644 (file)
index 0000000..840870f
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/_cmd._cml
@@ -0,0 +1 @@
+-link    -encrypt        -top extref -osyn /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synwork/extref_comp.srs /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synwork/layer0.srs   
\ No newline at end of file

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/dm/layer0.xdm b/gbe/cores/GbePcsExtrefclk/extref/syn_results/dm/layer0.xdm
new file mode 100644 (file)
index 0000000..6d7c478
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/dm/layer0.xdm
@@ -0,0 +1,79 @@
+%%% protect protected_file
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diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.areasrr b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.areasrr
new file mode 100644 (file)
index 0000000..7038b76
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.areasrr
@@ -0,0 +1,15 @@
+----------------------------------------------------------------------
+Report for cell extref.v1
+
+Register bits: 0 of 24288 (0%)
+PIC Latch:       0
+I/O cells:       0
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                            EXTREFB        1       100.0
+                                GSR        1       100.0
+                                PUR        1       100.0
+                                VHI        1       100.0
+                                VLO        1       100.0
+                            
+                         TOTAL             5           

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.fse b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.fse
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.htm b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.htm
new file mode 100644 (file)
index 0000000..80016ba
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.htm
@@ -0,0 +1,9 @@
+<html>
+ <head>
+ <title>syntmp/extref_srr.htm log file</title>
+ </head>
+ <frameset cols="20%, 80%">
+ <frame src="syntmp/extref_toc.htm" name="tocFrame" />
+                                <frame src="syntmp/extref_srr.htm" name="srrFrame"/>
+</frameset>
+ </html>

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.prj b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.prj
new file mode 100644 (file)
index 0000000..c373cbc
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.prj
@@ -0,0 +1,46 @@
+#-- Lattice Semiconductor Corporation Ltd.
+#-- Synplify OEM project file /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref.prj
+#-- Written on Mon May 13 09:10:13 2019
+
+
+#device options
+set_option -technology ecp5um
+set_option -part LFE5UM-85F
+set_option -speed_grade 8
+
+#use verilog 2001 standard option
+set_option -vlog_std v2001
+
+#map options
+set_option -frequency 100
+set_option -fanout_limit 50
+set_option -disable_io_insertion true
+set_option -retiming false
+set_option -pipe false
+set_option -pipe false
+set_option -force_gsr false
+
+#simulation options
+set_option -write_verilog true
+set_option -write_vhdl true
+
+#timing analysis options
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#-- add_file options
+add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd"
+add_file -constraint {"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.fdc"}
+
+#-- top module name
+set_option -top_module extref
+
+#-- set result format/file last
+project -result_file "extref.edn"
+
+#-- error message log file
+project -log_file extref.srf
+
+#-- run Synplify with 'arrange VHDL file'
+project -run

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.srd b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.srd
new file mode 100644 (file)
index 0000000..d6fab21
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.srd differ

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.srf b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.srf
new file mode 100644 (file)
index 0000000..9224860
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.srf
@@ -0,0 +1,333 @@
+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
+#install: /home/soft/lattice/diamond/3.10_x64/synpbase
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Mon May 13 09:10:13 2019
+
+#Implementation: syn_results
+
+Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":18:7:18:12|Top entity is set to extref.
+VHDL syntax check successful!
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":18:7:18:12|Synthesizing work.extref.v1.
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2147:10:2147:16|Synthesizing ecp5um.extrefb.syn_black_box.
+Post processing for ecp5um.extrefb.syn_black_box
+Post processing for work.extref.v1
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon May 13 09:10:14 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon May 13 09:10:14 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon May 13 09:10:14 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon May 13 09:10:15 2019
+
+###########################################################]
+Pre-mapping Report
+
+# Mon May 13 09:10:15 2019
+
+Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.fdc
+@L: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref_scck.rpt 
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref_scck.rpt" file 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist extref
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
+
+
+
+Clock Summary
+******************
+
+          Start     Requested     Requested     Clock     Clock     Clock
+Level     Clock     Frequency     Period        Type      Group     Load 
+-------------------------------------------------------------------------
+=========================================================================
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 142MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Mon May 13 09:10:16 2019
+
+###########################################################]
+Map & Optimize Report
+
+# Mon May 13 09:10:16 2019
+
+Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synwork/extref_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 143MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref.edn
+M-2017.03L-SP1-1
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
+
+@W: MT246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":31:4:31:15|Blackbox EXTREFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Mon May 13 09:10:18 2019
+#
+
+
+Top view:               extref
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.fdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: NA
+
+                   Requested     Estimated     Requested     Estimated               Clock      Clock          
+Starting Clock     Frequency     Frequency     Period        Period        Slack     Type       Group          
+---------------------------------------------------------------------------------------------------------------
+System             100.0 MHz     NA            10.000        NA            NA        system     system_clkgroup
+===============================================================================================================
+Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks            |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+--------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
+--------------------------------------------------------------------------------------------------------
+========================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 0 of 24288 (0%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+EXTREFB:        1
+GSR:            1
+PUR:            1
+VHI:            1
+VLO:            1
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 146MB)
+
+Process took 0h:00m:02s realtime, 0h:00m:02s cputime
+# Mon May 13 09:10:18 2019
+
+###########################################################]

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.srm b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.srm
new file mode 100644 (file)
index 0000000..4b18ebf
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.srm differ

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.srr b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.srr
new file mode 100644 (file)
index 0000000..9224860
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.srr
@@ -0,0 +1,333 @@
+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
+#install: /home/soft/lattice/diamond/3.10_x64/synpbase
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Mon May 13 09:10:13 2019
+
+#Implementation: syn_results
+
+Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":18:7:18:12|Top entity is set to extref.
+VHDL syntax check successful!
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":18:7:18:12|Synthesizing work.extref.v1.
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2147:10:2147:16|Synthesizing ecp5um.extrefb.syn_black_box.
+Post processing for ecp5um.extrefb.syn_black_box
+Post processing for work.extref.v1
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon May 13 09:10:14 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon May 13 09:10:14 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon May 13 09:10:14 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon May 13 09:10:15 2019
+
+###########################################################]
+Pre-mapping Report
+
+# Mon May 13 09:10:15 2019
+
+Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.fdc
+@L: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref_scck.rpt 
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref_scck.rpt" file 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist extref
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
+
+
+
+Clock Summary
+******************
+
+          Start     Requested     Requested     Clock     Clock     Clock
+Level     Clock     Frequency     Period        Type      Group     Load 
+-------------------------------------------------------------------------
+=========================================================================
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 142MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Mon May 13 09:10:16 2019
+
+###########################################################]
+Map & Optimize Report
+
+# Mon May 13 09:10:16 2019
+
+Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synwork/extref_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 143MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref.edn
+M-2017.03L-SP1-1
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
+
+@W: MT246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":31:4:31:15|Blackbox EXTREFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Mon May 13 09:10:18 2019
+#
+
+
+Top view:               extref
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.fdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: NA
+
+                   Requested     Estimated     Requested     Estimated               Clock      Clock          
+Starting Clock     Frequency     Frequency     Period        Period        Slack     Type       Group          
+---------------------------------------------------------------------------------------------------------------
+System             100.0 MHz     NA            10.000        NA            NA        system     system_clkgroup
+===============================================================================================================
+Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks            |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+--------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
+--------------------------------------------------------------------------------------------------------
+========================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 0 of 24288 (0%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+EXTREFB:        1
+GSR:            1
+PUR:            1
+VHI:            1
+VLO:            1
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 146MB)
+
+Process took 0h:00m:02s realtime, 0h:00m:02s cputime
+# Mon May 13 09:10:18 2019
+
+###########################################################]

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.srr.db b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.srr.db
new file mode 100644 (file)
index 0000000..0a4a135
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.srr.db differ

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.srs b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.srs
new file mode 100644 (file)
index 0000000..8be0fe9
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.srs differ

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.vhm b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.vhm
new file mode 100644 (file)
index 0000000..d1e4544
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.vhm
@@ -0,0 +1,54 @@
+--
+-- Written by Synplicity
+-- Product Version "M-2017.03L-SP1-1"
+-- Program "Synplify Pro", Mapper "maplat, Build 1796R"
+-- Mon May 13 09:10:18 2019
+--
+
+--
+-- Written by Synplify Pro version Build 1796R
+-- Mon May 13 09:10:18 2019
+--
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library synplify;
+use synplify.components.all;
+library pmi;
+use pmi.pmi_components.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity extref is
+port(
+  refclkp :  in std_logic;
+  refclkn :  in std_logic;
+  refclko :  out std_logic);
+end extref;
+
+architecture beh of extref is
+  signal GND : std_logic ;
+  signal VCC : std_logic ;
+begin
+GND_0: VLO port map (
+    Z => GND);
+VCC_0: VHI port map (
+    Z => VCC);
+PUR_INST: PUR port map (
+    PUR => VCC);
+GSR_INST: GSR port map (
+    GSR => VCC);
+EXTREF1_INST: EXTREFB 
+  generic map( 
+    REFCK_PWDNB => "0b1", 
+    REFCK_RTERM => "0b1", 
+    REFCK_DCBIAS_EN => "0b0"
+  ) 
+  port map (
+    REFCLKP => refclkp,
+    REFCLKN => refclkn,
+    REFCLKO => refclko);
+end beh;
+

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.vm b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.vm
new file mode 100644 (file)
index 0000000..aa10424
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref.vm
@@ -0,0 +1,59 @@
+//
+// Written by Synplify Pro 
+// Product Version "M-2017.03L-SP1-1"
+// Program "Synplify Pro", Mapper "maplat, Build 1796R"
+// Mon May 13 09:10:18 2019
+//
+// Source file index table:
+// Object locations will have the form <file>:<line>
+// file 0 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd "
+// file 1 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd "
+// file 2 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd "
+// file 3 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd "
+// file 4 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd "
+// file 5 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd "
+// file 6 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd "
+// file 7 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd "
+// file 8 "\/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd "
+// file 9 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd "
+// file 10 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/nlconst.dat "
+// file 11 "\/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.fdc "
+
+`timescale 100 ps/100 ps
+module extref (
+  refclkp,
+  refclkn,
+  refclko
+)
+;
+input refclkp ;
+input refclkn ;
+output refclko ;
+wire refclkp ;
+wire refclkn ;
+wire refclko ;
+wire GND ;
+wire VCC ;
+  VLO GND_0 (
+       .Z(GND)
+);
+  VHI VCC_0 (
+       .Z(VCC)
+);
+  PUR PUR_INST (
+       .PUR(VCC)
+);
+  GSR GSR_INST (
+       .GSR(VCC)
+);
+// @8:31
+(* LOC="EXTREF1" *)  EXTREFB EXTREF1_inst (
+       .REFCLKP(refclkp),
+       .REFCLKN(refclkn),
+       .REFCLKO(refclko)
+);
+defparam EXTREF1_inst.REFCK_PWDNB = "0b1";
+defparam EXTREF1_inst.REFCK_RTERM = "0b1";
+defparam EXTREF1_inst.REFCK_DCBIAS_EN = "0b0";
+endmodule /* extref */
+

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref_cck.rpt.db b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref_cck.rpt.db
new file mode 100644 (file)
index 0000000..029fa7a
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref_cck.rpt.db differ

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref_scck.rpt.db b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref_scck.rpt.db
new file mode 100644 (file)
index 0000000..029fa7a
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref_scck.rpt.db differ

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref_synplify.lpf b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref_synplify.lpf
new file mode 100644 (file)
index 0000000..8e445e1
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref_synplify.lpf
@@ -0,0 +1,20 @@
+#
+# Logical Preferences generated for Lattice by Synplify maplat, Build 1796R.
+#
+
+# Period Constraints 
+
+
+# Output Constraints 
+
+# Input Constraints 
+
+# Point-to-point Delay Constraints 
+
+
+
+# Block Path Constraints 
+
+BLOCK ASYNCPATHS;
+
+# End of generated Logical Preferences.

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref_synplify_tmp2.lpf b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref_synplify_tmp2.lpf
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref_synplify_tmp4.lpf b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref_synplify_tmp4.lpf
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref_synplify_tmp8.lpf b/gbe/cores/GbePcsExtrefclk/extref/syn_results/extref_synplify_tmp8.lpf
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/run_options.txt b/gbe/cores/GbePcsExtrefclk/extref/syn_results/run_options.txt
new file mode 100644 (file)
index 0000000..1343a58
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/run_options.txt
@@ -0,0 +1,75 @@
+#--  Synopsys, Inc.
+#--  Version M-2017.03L-SP1-1
+#--  Project file /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/run_options.txt
+#--  Written on Mon May 13 09:10:13 2019
+
+
+#project files
+add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd"
+add_file -fpga_constraint "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.fdc"
+
+
+
+#implementation: "syn_results"
+impl -add syn_results -type fpga
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+
+#device options
+set_option -technology ecp5um
+set_option -part LFE5UM_25F
+set_option -package MG285C
+set_option -speed_grade -6
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -top_module "extref"
+
+# hdl_compiler_options
+set_option -distributed_compile 0
+
+# mapper_without_write_options
+set_option -frequency 100
+set_option -srs_instrumentation 1
+
+# mapper_options
+set_option -write_verilog 1
+set_option -write_vhdl 1
+
+# Lattice XP
+set_option -maxfan 50
+set_option -disable_io_insertion 1
+set_option -retiming 0
+set_option -pipe 0
+set_option -forcegsr false
+set_option -fix_gated_and_generated_clocks 1
+set_option -rw_check_on_ram 1
+set_option -update_models_cp 0
+set_option -syn_edif_array_rename 1
+set_option -Write_declared_clocks_only 1
+
+# NFilter
+set_option -no_sequential_opt 0
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "./extref.edn"
+
+#set log file 
+set_option log_file "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref.srf" 
+impl -active "syn_results"

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/scemi_cfg.txt b/gbe/cores/GbePcsExtrefclk/extref/syn_results/scemi_cfg.txt
new file mode 100644 (file)
index 0000000..868d437
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/scemi_cfg.txt
@@ -0,0 +1,3 @@
+## UMR3 MESSAGE PORT CONFIGURATION FILE
+## ************************************
+XTOR_DPI_MSG_PORT_UMR_ADDR_VERSION=0

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/scratchproject.prs b/gbe/cores/GbePcsExtrefclk/extref/syn_results/scratchproject.prs
new file mode 100644 (file)
index 0000000..6a93ebc
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/scratchproject.prs
@@ -0,0 +1,73 @@
+#--  Synopsys, Inc.
+#--  Version M-2017.03L-SP1-1
+#--  Project file /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/scratchproject.prs
+
+#project files
+add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd"
+add_file -fpga_constraint "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.fdc"
+
+
+
+#implementation: "syn_results"
+impl -add /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results -type fpga
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+
+#device options
+set_option -technology ecp5um
+set_option -part LFE5UM_25F
+set_option -package MG285C
+set_option -speed_grade -6
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -top_module "extref"
+
+# hdl_compiler_options
+set_option -distributed_compile 0
+
+# mapper_without_write_options
+set_option -frequency 100
+set_option -srs_instrumentation 1
+
+# mapper_options
+set_option -write_verilog 1
+set_option -write_vhdl 1
+
+# Lattice XP
+set_option -maxfan 50
+set_option -disable_io_insertion 1
+set_option -retiming 0
+set_option -pipe 0
+set_option -forcegsr false
+set_option -fix_gated_and_generated_clocks 1
+set_option -rw_check_on_ram 1
+set_option -update_models_cp 0
+set_option -syn_edif_array_rename 1
+set_option -Write_declared_clocks_only 1
+
+# NFilter
+set_option -no_sequential_opt 0
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref.edn"
+
+#set log file 
+set_option log_file "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref.srf" 
+impl -active "syn_results"

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_compiler.srr b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_compiler.srr
new file mode 100644 (file)
index 0000000..c36cce0
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_compiler.srr
@@ -0,0 +1,46 @@
+Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":18:7:18:12|Top entity is set to extref.
+VHDL syntax check successful!
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":18:7:18:12|Synthesizing work.extref.v1.
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2147:10:2147:16|Synthesizing ecp5um.extrefb.syn_black_box.
+Post processing for ecp5um.extrefb.syn_black_box
+Post processing for work.extref.v1
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon May 13 09:10:14 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon May 13 09:10:14 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon May 13 09:10:14 2019
+
+###########################################################]

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_compiler.srr.db b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_compiler.srr.db
new file mode 100644 (file)
index 0000000..f12ad97
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_compiler.srr.db differ

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_compiler.srr.rptmap b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_compiler.srr.rptmap
new file mode 100644 (file)
index 0000000..e3a80a7
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_compiler.srr.rptmap
@@ -0,0 +1 @@
+./synlog/extref_compiler.srr,extref_compiler.srr,Compile Log

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_fpga_mapper.srr b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_fpga_mapper.srr
new file mode 100644 (file)
index 0000000..e5eaf3d
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_fpga_mapper.srr
@@ -0,0 +1,201 @@
+# Mon May 13 09:10:16 2019
+
+Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synwork/extref_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 143MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref.edn
+M-2017.03L-SP1-1
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
+
+@W: MT246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":31:4:31:15|Blackbox EXTREFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Mon May 13 09:10:18 2019
+#
+
+
+Top view:               extref
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.fdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: NA
+
+                   Requested     Estimated     Requested     Estimated               Clock      Clock          
+Starting Clock     Frequency     Frequency     Period        Period        Slack     Type       Group          
+---------------------------------------------------------------------------------------------------------------
+System             100.0 MHz     NA            10.000        NA            NA        system     system_clkgroup
+===============================================================================================================
+Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks            |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+--------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
+--------------------------------------------------------------------------------------------------------
+========================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 0 of 24288 (0%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+EXTREFB:        1
+GSR:            1
+PUR:            1
+VHI:            1
+VLO:            1
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 146MB)
+
+Process took 0h:00m:02s realtime, 0h:00m:02s cputime
+# Mon May 13 09:10:18 2019
+
+###########################################################]

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_fpga_mapper.srr.db b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_fpga_mapper.srr.db
new file mode 100644 (file)
index 0000000..767fffc
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_fpga_mapper.srr.db differ

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_fpga_mapper.szr b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_fpga_mapper.szr
new file mode 100644 (file)
index 0000000..2564d4f
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_fpga_mapper.szr differ

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_multi_srs_gen.srr b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_multi_srs_gen.srr
new file mode 100644 (file)
index 0000000..3e8860c
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_multi_srs_gen.srr
@@ -0,0 +1,11 @@
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon May 13 09:10:15 2019
+
+###########################################################]

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_multi_srs_gen.srr.db b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_multi_srs_gen.srr.db
new file mode 100644 (file)
index 0000000..029fa7a
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_multi_srs_gen.srr.db differ

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_premap.srr b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_premap.srr
new file mode 100644 (file)
index 0000000..27b114b
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_premap.srr
@@ -0,0 +1,62 @@
+# Mon May 13 09:10:15 2019
+
+Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.fdc
+@L: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref_scck.rpt 
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref_scck.rpt" file 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist extref
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
+
+
+
+Clock Summary
+******************
+
+          Start     Requested     Requested     Clock     Clock     Clock
+Level     Clock     Frequency     Period        Type      Group     Load 
+-------------------------------------------------------------------------
+=========================================================================
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 142MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Mon May 13 09:10:16 2019
+
+###########################################################]

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_premap.srr.db b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_premap.srr.db
new file mode 100644 (file)
index 0000000..4dd9838
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_premap.srr.db differ

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_premap.szr b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_premap.szr
new file mode 100644 (file)
index 0000000..e4da5e4
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/extref_premap.szr differ

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/layer0.tlg.rptmap b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/layer0.tlg.rptmap
new file mode 100644 (file)
index 0000000..3910cac
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/layer0.tlg.rptmap
@@ -0,0 +1 @@
+./synwork/layer0.tlg,layer0.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages.

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_compiler_notes.txt b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_compiler_notes.txt
new file mode 100644 (file)
index 0000000..40a0990
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_compiler_notes.txt
@@ -0,0 +1,8 @@
+@N|Running in 64-bit mode
+@N|Running in 64-bit mode
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":18:7:18:12|Top entity is set to extref.
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":18:7:18:12|Synthesizing work.extref.v1.
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2147:10:2147:16|Synthesizing ecp5um.extrefb.syn_black_box.
+@N|Running in 64-bit mode
+

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_compiler_runstatus.xml b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_compiler_runstatus.xml
new file mode 100644 (file)
index 0000000..3573f63
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_compiler_runstatus.xml
@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the job information from compiler to be displayed as part of the summary report.
+*******************************************************************************************-->
+
+<job_run_status name="compiler"> 
+  <report_link name="Detailed report">
+    <data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/extref_compiler.srr</data>
+    <title>Synopsys HDL Compiler</title>
+  </report_link> 
+  <job_status>
+    <data>Completed    </data>
+  </job_status>
+<job_info> 
+                       <info name="Notes">
+  <data>7</data>
+  <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_compiler_notes.txt</data></report_link>
+  </info>
+                       <info name="Warnings">
+  <data>0</data>
+  <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_compiler_warnings.txt</data></report_link>
+  </info>
+                       <info name="Errors">
+  <data>0</data>
+  <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_compiler_errors.txt</data></report_link>
+  </info>
+                       <info name="CPU Time">
+  <data>-</data>
+  </info>
+                       <info name="Real Time">
+  <data>00h:00m:01s</data>
+  </info>
+                       <info name="Peak Memory">
+  <data>-</data>
+  </info>
+                       <info name="Date &amp;Time">
+  <data type="timestamp">1557731414</data>
+  </info>
+                       </job_info>
+</job_run_status>
\ No newline at end of file

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_area_report.xml b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_area_report.xml
new file mode 100644 (file)
index 0000000..6f8fcea
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_area_report.xml
@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the area information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<report_table display_priority="1" name="Area Summary">
+<report_link name="Detailed report">
+<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_resourceusage.rpt</data>
+<title>Resource Usage</title>
+</report_link>
+<parameter tooltip="Total Register bits used" name="Register bits">
+<data>0</data>
+</parameter>
+<parameter tooltip="Total I/O cells used" name="I/O cells">
+<data>0</data>
+</parameter>
+<parameter tcl_name="v_ram" tooltip="Total Block RAMs used" name="Block RAMs">
+<data>0</data>
+</parameter>
+<parameter tcl_name="dsp_used" tooltip="Total DSPs used" name="DSPs">
+<data>0</data>
+</parameter>
+<parameter tcl_name="total_luts" tooltip="Total ORCA LUTs used" name="ORCA LUTs">
+<data>0</data>
+</parameter>
+</report_table>

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_errors.txt b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_errors.txt
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_notes.txt b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_notes.txt
new file mode 100644 (file)
index 0000000..aa9d230
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_notes.txt
@@ -0,0 +1,7 @@
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref.edn
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_opt_report.xml b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_opt_report.xml
new file mode 100644 (file)
index 0000000..1ad405d
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_opt_report.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the optimization information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<report_table display_priority="3" name="Optimizations Summary">
+<parameter tooltip="Non-gated/non-generated clock trees / Gated/generated clock trees" name="Combined Clock Conversion">
+<data>0 / 0</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_combined_clk.rpt</data>
+<title>START OF CLOCK OPTIMIZATION REPORT</title>
+</report_link>
+</parameter>
+</report_table>

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_runstatus.xml b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_runstatus.xml
new file mode 100644 (file)
index 0000000..68def92
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_runstatus.xml
@@ -0,0 +1,46 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the job information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<job_run_status name="Mapper">
+<report_link name="Detailed report">
+<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/extref_fpga_mapper.srr</data>
+<title>Synopsys Lattice Technology Mapper</title>
+</report_link>
+<job_status>
+<data>Completed</data>
+</job_status>
+<job_info>
+<info name="Notes">
+<data>7</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_notes.txt</data>
+</report_link>
+</info>
+<info name="Warnings">
+<data>1</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_warnings.txt</data>
+</report_link>
+</info>
+<info name="Errors">
+<data>0</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_errors.txt</data>
+</report_link>
+</info>
+<info name="CPU Time">
+<data>0h:00m:02s</data>
+</info>
+<info name="Real Time">
+<data>0h:00m:02s</data>
+</info>
+<info name="Peak Memory">
+<data>146MB</data>
+</info>
+<info name="Date &amp; Time">
+<data type="timestamp">1557731418</data>
+</info>
+</job_info>
+</job_run_status>

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_timing_report.xml b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_timing_report.xml
new file mode 100644 (file)
index 0000000..52701c6
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_timing_report.xml
@@ -0,0 +1,23 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+Max Top 5 critical clocks will be reported. For rest user needs to refer to Detailed report
+*******************************************************************************************-->
+<report_table display_priority="2" name="Timing Summary">
+<report_link name="Detailed report">
+<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/extref_fpga_mapper.srr</data>
+<title>START OF TIMING REPORT</title>
+</report_link>
+<row>
+<data tcl_name="clock_name">Clock Name</data>
+<data tcl_name="req_freq">Req Freq</data>
+<data tcl_name="est_freq">Est Freq</data>
+<data tcl_name="slack">Slack</data>
+</row>
+<row>
+<data>System</data>
+<data>100.0 MHz</data>
+<data>NA</data>
+<data>NA</data>
+</row>
+</report_table>

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_warnings.txt b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_warnings.txt
new file mode 100644 (file)
index 0000000..b99a088
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_fpga_mapper_warnings.txt
@@ -0,0 +1 @@
+@W: MT246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":31:4:31:15|Blackbox EXTREFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_errors.txt b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_errors.txt
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_notes.txt b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_notes.txt
new file mode 100644 (file)
index 0000000..eed8756
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_notes.txt
@@ -0,0 +1,2 @@
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_runstatus.xml b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_runstatus.xml
new file mode 100644 (file)
index 0000000..963604b
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_runstatus.xml
@@ -0,0 +1,46 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the job information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<job_run_status name="Mapper">
+<report_link name="Detailed report">
+<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/extref_premap.srr</data>
+<title>Synopsys Lattice Technology Pre-mapping</title>
+</report_link>
+<job_status>
+<data>Completed</data>
+</job_status>
+<job_info>
+<info name="Notes">
+<data>2</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_notes.txt</data>
+</report_link>
+</info>
+<info name="Warnings">
+<data>0</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_warnings.txt</data>
+</report_link>
+</info>
+<info name="Errors">
+<data>0</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_errors.txt</data>
+</report_link>
+</info>
+<info name="CPU Time">
+<data>0h:00m:00s</data>
+</info>
+<info name="Real Time">
+<data>0h:00m:00s</data>
+</info>
+<info name="Peak Memory">
+<data>142MB</data>
+</info>
+<info name="Date &amp; Time">
+<data type="timestamp">1557731416</data>
+</info>
+</job_info>
+</job_run_status>

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_warnings.txt b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/extref_premap_warnings.txt
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/metrics.db b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/metrics.db
new file mode 100644 (file)
index 0000000..145597c
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/report/metrics.db differ

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/syntax_constraint_check.rpt.rptmap b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/syntax_constraint_check.rpt.rptmap
new file mode 100644 (file)
index 0000000..6daf021
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synlog/syntax_constraint_check.rpt.rptmap
@@ -0,0 +1 @@
+./extref_scck.rpt,syntax_constraint_check.rpt,Syntax Constraint Check Report

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/closed.png b/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/closed.png
new file mode 100644 (file)
index 0000000..0d78634
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/closed.png differ

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/extref.plg b/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/extref.plg
new file mode 100644 (file)
index 0000000..1796220
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/extref.plg
@@ -0,0 +1,8 @@
+@P:  Worst Slack : NA
+@P:  System - Estimated Frequency : NA
+@P:  System - Requested Frequency : 100.0 MHz
+@P:  System - Estimated Period : NA
+@P:  System - Requested Period : 10.000
+@P:  System - Slack : NA
+@P:  Total Area : 0.0
+@P:  CPU Time : 0h:00m:02s

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/extref_srr.htm b/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/extref_srr.htm
new file mode 100644 (file)
index 0000000..d3d80ba
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/extref_srr.htm
@@ -0,0 +1,357 @@
+<html><body><samp><pre>
+<!@TC:1557731413>
+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
+#install: /home/soft/lattice/diamond/3.10_x64/synpbase
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Mon May 13 09:10:13 2019
+
+#Implementation: syn_results
+
+<a name=compilerReport1></a>Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1557731414> | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+<a name=compilerReport2></a>Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1557731414> | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1557731414> | Setting time resolution to ps
+@N: : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd:18:7:18:13:@N::@XP_MSG">extref.vhd(18)</a><!@TM:1557731414> | Top entity is set to extref.
+VHDL syntax check successful!
+@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd:18:7:18:13:@N:CD630:@XP_MSG">extref.vhd(18)</a><!@TM:1557731414> | Synthesizing work.extref.v1.
+@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd:2147:10:2147:17:@N:CD630:@XP_MSG">ecp5um.vhd(2147)</a><!@TM:1557731414> | Synthesizing ecp5um.extrefb.syn_black_box.
+Post processing for ecp5um.extrefb.syn_black_box
+Post processing for work.extref.v1
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon May 13 09:10:14 2019
+
+###########################################################]
+<a name=compilerReport3></a>Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1557731414> | Running in 64-bit mode 
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon May 13 09:10:14 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon May 13 09:10:14 2019
+
+###########################################################]
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1557731413>
+<a name=compilerReport4></a>Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1557731415> | Running in 64-bit mode 
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon May 13 09:10:15 2019
+
+###########################################################]
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1557731413>
+Pre-mapping Report
+
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1557731413>
+# Mon May 13 09:10:15 2019
+
+<a name=mapperReport5></a>Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35</a>
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.fdc
+Linked File: <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref_scck.rpt:@XP_FILE">extref_scck.rpt</a>
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref_scck.rpt" file 
+@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1557731416> | Running in 64-bit mode. 
+@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1557731416> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist extref
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
+
+
+
+<a name=mapperReport6></a>Clock Summary</a>
+******************
+
+          Start     Requested     Requested     Clock     Clock     Clock
+Level     Clock     Frequency     Period        Type      Group     Load 
+-------------------------------------------------------------------------
+=========================================================================
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 142MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Mon May 13 09:10:16 2019
+
+###########################################################]
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1557731413>
+Map & Optimize Report
+
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1557731413>
+# Mon May 13 09:10:16 2019
+
+<a name=mapperReport7></a>Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35</a>
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1557731418> | Running in 64-bit mode. 
+@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1557731418> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1557731418> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+<a name=clockReport8></a>#### START OF CLOCK OPTIMIZATION REPORT #####[</a>
+
+0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synwork/extref_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 143MB)
+
+Writing EDIF Netlist and constraint files
+@N:<a href="@N:FX1056:@XP_HELP">FX1056</a> : <!@TM:1557731418> | Writing EDF file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref.edn 
+M-2017.03L-SP1-1
+@N:<a href="@N:BW106:@XP_HELP">BW106</a> : <!@TM:1557731418> | Synplicity Constraint File capacitance units using default value of 1pF  
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
+
+<font color=#A52A2A>@W:<a href="@W:MT246:@XP_HELP">MT246</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd:31:4:31:16:@W:MT246:@XP_MSG">extref.vhd(31)</a><!@TM:1557731418> | Blackbox EXTREFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) </font>
+
+
+<a name=timingReport9></a>##### START OF TIMING REPORT #####[</a>
+# Timing Report written on Mon May 13 09:10:18 2019
+#
+
+
+Top view:               extref
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.fdc
+                       
+@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1557731418> | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 
+
+@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1557731418> | Clock constraints include only register-to-register paths associated with each individual clock. 
+
+
+
+<a name=performanceSummary10></a>Performance Summary</a>
+*******************
+
+
+Worst slack in design: NA
+
+                   Requested     Estimated     Requested     Estimated               Clock      Clock          
+Starting Clock     Frequency     Frequency     Period        Period        Slack     Type       Group          
+---------------------------------------------------------------------------------------------------------------
+System             100.0 MHz     NA            10.000        NA            NA        system     system_clkgroup
+===============================================================================================================
+Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
+
+
+
+
+
+<a name=clockRelationships11></a>Clock Relationships</a>
+*******************
+
+Clocks            |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+--------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
+--------------------------------------------------------------------------------------------------------
+========================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+<a name=interfaceInfo12></a>Interface Information </a>
+*********************
+
+No IO constraint found
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
+
+---------------------------------------
+<a name=resourceUsage13></a>Resource Usage Report</a>
+Part: lfe5um_25f-6
+
+Register bits: 0 of 24288 (0%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+EXTREFB:        1
+GSR:            1
+PUR:            1
+VHI:            1
+VLO:            1
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 146MB)
+
+Process took 0h:00m:02s realtime, 0h:00m:02s cputime
+# Mon May 13 09:10:18 2019
+
+###########################################################]
+
+</pre></samp></body></html>

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/extref_toc.htm b/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/extref_toc.htm
new file mode 100644 (file)
index 0000000..88bb149
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/extref_toc.htm
@@ -0,0 +1,38 @@
+ <html> 
+  <head>
+    <script type="text/javascript" src="file:///home/soft/lattice/diamond/3.10_x64/synpbase/lib/report/reportlog_tree.js"></script>
+    <link rel="stylesheet" type="text/css" href="file:///home/soft/lattice/diamond/3.10_x64/synpbase/lib/report/reportlog_tree.css" />  
+  </head> 
+
+  <body style="background-color:#e0e0ff;">
+   <script type="text/javascript"> reportLogObj.loadImage("closed.png", "open.png")</script>
+    <ul id="syn_results-menu" class="treeview" style="padding-left:12;">
+        <li style="font-size:12; font-style:normal"> <b style="background-color:#a2bff0; font-weight:bold">extref (syn_results)</b> 
+         <ul rel="open" style="font-size:small;">
+
+<li style="font-size:12; font-style:normal"><b style="background-color:#a2bff0; font-weight:bold">Synthesis -  </b> 
+<ul rel="open">
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/syntmp/extref_srr.htm#compilerReport1" target="srrFrame" title="">Compiler Report</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/syntmp/extref_srr.htm#compilerReport3" target="srrFrame" title="">Compiler Constraint Applicator</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/syntmp/extref_srr.htm#mapperReport5" target="srrFrame" title="">Pre-mapping Report</a>  
+<ul rel="open" >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/syntmp/extref_srr.htm#mapperReport6" target="srrFrame" title="">Clock Summary</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/syntmp/extref_srr.htm#mapperReport7" target="srrFrame" title="">Mapper Report</a>  
+<ul rel="open" >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/syntmp/extref_srr.htm#clockReport8" target="srrFrame" title="">Clock Conversion</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/syntmp/extref_srr.htm#timingReport9" target="srrFrame" title="">Timing Report</a>  
+<ul rel="open" >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/syntmp/extref_srr.htm#performanceSummary10" target="srrFrame" title="">Performance Summary</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/syntmp/extref_srr.htm#clockRelationships11" target="srrFrame" title="">Clock Relationships</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/syntmp/extref_srr.htm#interfaceInfo12" target="srrFrame" title="">Interface Information</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/syntmp/extref_srr.htm#resourceUsage13" target="srrFrame" title="">Resource Utilization</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/extref_cck.rpt" target="srrFrame" title="">Constraint Checker Report (09:10 13-May)</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/stdout.log" target="srrFrame" title="">Session Log (09:10 13-May)</a>  
+<ul  ></ul></li>         </ul>
+        </li>
+   </ul>
+
+   <script type="text/javascript"> reportLogObj.generateLog("syn_results-menu")</script>
+
+  </body>
+ </html>
\ No newline at end of file

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/open.png b/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/open.png
new file mode 100644 (file)
index 0000000..a227005
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/open.png differ

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/run_option.xml b/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/run_option.xml
new file mode 100644 (file)
index 0000000..e23ec94
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/run_option.xml
@@ -0,0 +1,24 @@
+<?xml version="1.0" encoding="utf-8"?> 
+<!-- 
+  Synopsys, Inc.
+  Version M-2017.03L-SP1-1
+  Project file /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/syntmp/run_option.xml
+  Written on Mon May 13 09:10:13 2019
+
+
+--> 
+<project_attribute_list name="Project Settings"> 
+     <option name="project_name" display_name="Project Name">extref</option>
+     <option name="device_name" display_name="Device Name">syn_results: Lattice ECP5UM : LFE5UM_25F</option>
+     <option name="impl_name" display_name="Implementation Name">syn_results</option>
+     <option name="top_module" display_name="Top Module">extref</option>
+     <option name="pipe" display_name="Pipelining">0</option>
+     <option name="retiming" display_name="Retiming">0</option>
+     <option name="resource_sharing" display_name="Resource Sharing">1</option>
+     <option name="maxfan" display_name="Fanout Guide">50</option>
+     <option name="disable_io_insertion" display_name="Disable I/O Insertion">1</option>
+     <option name="no_sequential_opt" display_name="Disable Sequential Optimizations">0</option>
+     <option name="fix_gated_and_generated_clocks" display_name="Clock Conversion">1</option>
+     <option name="symbolic_fsm_compiler" display_name="FSM Compiler">1</option>
+</project_attribute_list>
+

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/statusReport.html b/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/statusReport.html
new file mode 100644 (file)
index 0000000..0991010
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/syntmp/statusReport.html
@@ -0,0 +1,112 @@
+<html> 
+                       <head>                  <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1" />
+                       <title>Project Status Summary Page</title>
+                       <link rel="stylesheet" type="text/css" href="projectstatuspage.css" />
+                       <script type = "text/javascript" src="projectstatuspage.js"></script>
+                       </head>
+
+                       <body style="background-color:#f0f0ff;">
+                       
+<table style="border:none;" width="100%" ><tr> <td class="outline">
+<table width="100%" border="0" cellspacing="0" cellpadding="0">             <thead class="tablehead"><tr><th colspan="4">Project Settings</th><tr> 
+ <tr> <td class="optionTitle" align="left"> Project Name</td> <td> extref</td> <td class="optionTitle" align="left"> Device Name</td> <td> syn_results: Lattice ECP5UM : LFE5UM_25F</td> </tr>
+<tr> <td class="optionTitle" align="left"> Implementation Name</td> <td> syn_results</td> <td class="optionTitle" align="left"> Top Module</td> <td> extref</td> </tr>
+                </thead> 
+                <tbody> <tr> <td class="optionTitle" align="left"> Pipelining</td> <td> 0</td> <td class="optionTitle" align="left"> Retiming</td> <td> 0</td> </tr>
+<tr> <td class="optionTitle" align="left"> Resource Sharing</td> <td> 1</td> <td class="optionTitle" align="left"> Fanout Guide</td> <td> 50</td> </tr>
+<tr> <td class="optionTitle" align="left"> Disable I/O Insertion</td> <td> 1</td> <td class="optionTitle" align="left"> Disable Sequential Optimizations</td> <td> 0</td> </tr>
+<tr> <td class="optionTitle" align="left"> Clock Conversion</td> <td> 1</td> <td class="optionTitle" align="left"> FSM Compiler</td> <td> 1</td> </tr>
+ 
+</tbody> 
+  </table><br>  <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
+                                  <thead class="tablehead"><tr><th   colspan="9">Run Status</th></tr></thead>
+         <tbody>
+               <tr>
+                       <th align="left" width="17%">Job Name</th>
+                       <th align="left">Status</th>
+                       <td class="lnote" align="center" title="Notes"></td>
+                       <td class="lwarn" align="center" title="Warnings"></td>
+                       <td class="lerror" align="center" title="Errors"></td>
+                       <th align="left">CPU Time</th>
+                       <th align="left">Real Time</th>
+                       <th align="left">Memory</th>
+                       <th align="left">Date/Time</th>
+         </tr>
+  <tr>
+  <td class="optionTitle"> (compiler)</td><td>Complete</td>
+ <td>7</td>
+<td>0</td>
+<td>0</td>
+<td>-</td>
+<td>00m:01s</td>
+<td>-</td>
+<td><font size="-1">5/13/19</font><br/><font size="-2">9:10 AM</font></td>
+</tr> 
+
+ <tr>
+  <td class="optionTitle"> (premap)</td><td>Complete</td>
+ <td>2</td>
+<td>0</td>
+<td>0</td>
+<td>0m:00s</td>
+<td>0m:00s</td>
+<td>142MB</td>
+<td><font size="-1">5/13/19</font><br/><font size="-2">9:10 AM</font></td>
+</tr> 
+
+ <tr>
+  <td class="optionTitle"> (fpga_mapper)</td><td>Complete</td>
+ <td>7</td>
+ <td>1</td>
+<td>0</td>
+<td>0m:02s</td>
+<td>0m:02s</td>
+<td>146MB</td>
+<td><font size="-1">5/13/19</font><br/><font size="-2">9:10 AM</font></td>
+</tr> 
+
+<tr>
+  <td class="optionTitle">Multi-srs Generator</td>
+  <td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td></td><td class="empty"></td><td class="empty"></td><td><font size="-1">5/13/19</font><br/><font size="-2">9:10 AM</font></td>              </tbody>
+     </table>
+ <br> 
+ <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
+                                  <thead class="tablehead"><tr><th   colspan="4">Area Summary</th></tr></thead>
+<tfoot> <tr> <td class="optionTitle" colspan="4"></td></tr> 
+ </tfoot> 
+ <tbody> <tr> 
+<td title ="Total Register bits used" class="optionTitle" align="left">Register bits</td> <td>0</td>
+<td title ="Total I/O cells used" class="optionTitle" align="left">I/O cells</td> <td>0</td>
+</tr>
+<tr> 
+<td title ="Total Block RAMs used" class="optionTitle" align="left">Block RAMs
+(v_ram)</td> <td>0</td>
+<td title ="Total DSPs used" class="optionTitle" align="left">DSPs
+(dsp_used)</td> <td>0</td>
+</tr>
+<tr> 
+<td title ="Total ORCA LUTs used" class="optionTitle" align="left">ORCA LUTs
+(total_luts)</td> <td>0</td>
+<td class="optionTitle"></td><td></td></tr> 
+</tbody>
+    </table><br>
+ <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
+                                  <thead class="tablehead"><tr><th   colspan="4">Timing Summary</th></tr></thead>
+<tfoot> <tr> <td class="optionTitle" colspan="2"></td></tr> 
+ </tfoot> 
+<tbody> 
+   <tr><th class="optionTitle" align= "left ">Clock Name</th><th class="optionTitle" align= "left ">Req Freq</th><th class="optionTitle" align= "left ">Est Freq</th><th class="optionTitle" align= "left ">Slack</th></tr> 
+<tr> <td  align="left">System</td><td  align="left">100.0 MHz</td><td  align="left">NA</td><td  align="left">NA</td></tr> 
+</tbody> 
+ </table>
+<br>
+ <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
+                                  <thead class="tablehead"><tr><th   colspan="4">Optimizations Summary</th></tr></thead>
+ <tbody> <tr> 
+<td title ="Non-gated/non-generated clock trees / Gated/generated clock trees" class="optionTitle" align="left">Combined Clock Conversion</td> <td>0 / 0</td>
+<td class="optionTitle"></td><td></td></tr> 
+</tbody>
+    </table><br>
+<br> 
+</td></tr></table></body> 
+ </html>
\ No newline at end of file

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/.cckTransfer b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/.cckTransfer
new file mode 100644 (file)
index 0000000..c1fdce9
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/.cckTransfer differ

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/_mh_info b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/_mh_info
new file mode 100644 (file)
index 0000000..37bc105
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/_mh_info
@@ -0,0 +1 @@
+|1|

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/extref_comp.fdep b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/extref_comp.fdep
new file mode 100644 (file)
index 0000000..3c02189
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/extref_comp.fdep
@@ -0,0 +1,21 @@
+#OPTIONS:"|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synwork/extref_comp.srs|-top|extref|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610
+#CUR:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":1557731412
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599
+0                      "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd" vhdl
+#Dependency Lists(Uses List)
+0 -1
+#Dependency Lists(Users Of)
+0 -1
+#Design Unit to File Association
+module work extref 0
+arch work extref v1 0

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/extref_comp.srs b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/extref_comp.srs
new file mode 100644 (file)
index 0000000..d2a9a97
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/extref_comp.srs differ

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/extref_m.srm b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/extref_m.srm
new file mode 100644 (file)
index 0000000..4b18ebf
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diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/extref_m_srm/fileinfo.srm b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/extref_m_srm/fileinfo.srm
new file mode 100644 (file)
index 0000000..622949f
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/extref_m_srm/fileinfo.srm differ

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/extref_mult.srs b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/extref_mult.srs
new file mode 100644 (file)
index 0000000..8be0fe9
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/extref_mult.srs differ

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/extref_mult_srs/fileinfo.srs b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/extref_mult_srs/fileinfo.srs
new file mode 100644 (file)
index 0000000..e6cd3c9
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/extref_mult_srs/fileinfo.srs differ

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/extref_mult_srs/skeleton.srs b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/extref_mult_srs/skeleton.srs
new file mode 100644 (file)
index 0000000..a27d685
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/extref_mult_srs/skeleton.srs differ

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/extref_prem.fse b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/extref_prem.fse
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/extref_prem.srd b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/extref_prem.srd
new file mode 100644 (file)
index 0000000..c040012
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/extref_prem.srd differ

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/layer0.fdep b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/layer0.fdep
new file mode 100644 (file)
index 0000000..f50b372
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/layer0.fdep
@@ -0,0 +1,28 @@
+#defaultlanguage:vhdl
+#OPTIONS:"|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synwork/extref_comp.srs|-top|extref|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610
+#CUR:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":1557731412
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599
+0 "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd" vhdl
+
+# Dependency Lists (Uses list)
+0 -1
+
+# Dependency Lists (Users Of)
+0 -1
+
+# Design Unit to File Association
+arch work extref v1 0
+module work extref 0
+
+
+# Configuration files used

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/layer0.fdeporig b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/layer0.fdeporig
new file mode 100644 (file)
index 0000000..79d35eb
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/layer0.fdeporig
@@ -0,0 +1,24 @@
+#defaultlanguage:vhdl
+#OPTIONS:"|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/syn_results/synwork/extref_comp.srs|-top|extref|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610
+#CUR:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":1557731412
+0 "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd" vhdl
+
+# Dependency Lists (Uses list)
+0 -1
+
+# Dependency Lists (Users Of)
+0 -1
+
+# Design Unit to File Association
+arch work extref v1 0
+module work extref 0

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/layer0.srs b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/layer0.srs
new file mode 100644 (file)
index 0000000..a94cc5b
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/layer0.srs differ

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/layer0.tlg b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/layer0.tlg
new file mode 100644 (file)
index 0000000..f51a047
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/layer0.tlg
@@ -0,0 +1,4 @@
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/extref/extref.vhd":18:7:18:12|Synthesizing work.extref.v1.
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2147:10:2147:16|Synthesizing ecp5um.extrefb.syn_black_box.
+Post processing for ecp5um.extrefb.syn_black_box
+Post processing for work.extref.v1

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/layer0.tlg.db b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/layer0.tlg.db
new file mode 100644 (file)
index 0000000..100a087
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/layer0.tlg.db differ

diff --git a/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/modulechange.db b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/modulechange.db
new file mode 100644 (file)
index 0000000..fc98a82
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/extref/syn_results/synwork/modulechange.db differ

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.cmd b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.cmd
new file mode 100644 (file)
index 0000000..6d63b98
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.cmd
@@ -0,0 +1,18 @@
+PROJECT: sgmii_ecp5
+               working_path: "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results"
+               module: sgmii_ecp5
+               verilog_file_list: "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd" "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v"
+               vlog_std_v2001: true
+               constraint_file_name: "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.fdc"
+               suffix_name: edn
+               output_file_name: sgmii_ecp5
+               write_prf: true
+               disable_io_insertion: true
+               force_gsr: false
+               frequency: 100
+               fanout_limit: 50
+               retiming: false
+               pipe: false
+               part: LFE5UM-85F
+               speed_grade: 8
+               

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.cst b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.cst
new file mode 100644 (file)
index 0000000..4ece745
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.cst
@@ -0,0 +1,3 @@
+Date=05/13/2019
+Time=09:09:01
+

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.fdc b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.fdc
new file mode 100644 (file)
index 0000000..5424a21
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.fdc
@@ -0,0 +1,3 @@
+###==== Start Generation
+
+define_attribute  {i:Lane0} {loc} {DCU1_CH1}

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.lpc b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.lpc
new file mode 100644 (file)
index 0000000..b5d8969
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.lpc
@@ -0,0 +1,97 @@
+[Device]
+Family=ecp5um
+OperatingCondition=COM
+Package=CABGA756
+PartName=LFE5UM-85F-8BG756C
+PartType=LFE5UM-85F
+SpeedGrade=8
+Status=P
+[IP]
+CoreName=PCS
+CoreRevision=8.2
+CoreStatus=Demo
+CoreType=LPM
+Date=05/13/2019
+ModuleName=sgmii_ecp5
+ParameterFileVersion=1.0
+SourceFormat=VHDL
+Time=09:09:01
+VendorName=Lattice Semiconductor Corporation
+[Parameters]
+;ACHARA=0 00H
+;ACHARB=0 00H
+;ACHARM=0 00H
+;RXMCAENABLE=Disabled
+CDRLOLACTION=Full Recalibration
+CDRLOLRANGE=0
+CDR_MAX_RATE=1.25
+CDR_MULT=10X
+CDR_REF_RATE=125.0000
+CH_MODE=Rx and Tx
+Destination=Synplicity
+EDIF=1
+Expression=BusA(0 to 7)
+IO=0
+IO_TYPE=GbE
+LEQ=0
+LOOPBACK=Disabled
+LOSPORT=Enabled
+NUM_CHS=1
+Order=Big Endian [MSB:LSB]
+PPORT_RX_RDY=Enabled
+PPORT_TX_RDY=Enabled
+PROTOCOL=GbE
+PWAIT_RX_RDY=3000
+PWAIT_TX_RDY=3000
+RCSRC=Disabled
+REFCLK_RATE=125.0000
+RSTSEQSEL=Enabled
+RX8B10B=Enabled
+RXCOMMAA=1010000011
+RXCOMMAB=0101111100
+RXCOMMAM=1111111111
+RXCOUPLING=AC
+RXCTC=Enabled
+RXCTCBYTEN=0 00H
+RXCTCBYTEN1=0 00H
+RXCTCBYTEN2=1 BCH
+RXCTCBYTEN3=0 50H
+RXCTCMATCHPATTERN=M2-S2
+RXDIFFTERM=50 ohms
+RXFIFO_ENABLE=Enabled
+RXINVPOL=Non-invert
+RXLDR=Off
+RXLOSTHRESHOLD=2
+RXLSM=Enabled
+RXSC=K28P5
+RXWA=Barrel Shift
+RX_DATA_WIDTH=8/10-Bit
+RX_FICLK_RATE=125.0000
+RX_LINE_RATE=1.2500
+RX_RATE_DIV=Full Rate
+SCIPORT=Enabled
+SOFTLOL=Enabled
+TX8B10B=Enabled
+TXAMPLITUDE=1100
+TXDEPOST=Disabled
+TXDEPRE=Disabled
+TXDIFFTERM=50 ohms
+TXFIFO_ENABLE=Enabled
+TXINVPOL=Non-invert
+TXLDR=Off
+TXPLLLOLTHRESHOLD=0
+TXPLLMULT=10X
+TX_DATA_WIDTH=8/10-Bit
+TX_FICLK_RATE=125.0000
+TX_LINE_RATE=1.2500
+TX_MAX_RATE=1.25
+TX_RATE_DIV=Full Rate
+VHDL=1
+Verilog=0
+[FilesGenerated]
+sgmii_ecp5.pp=pp
+sgmii_ecp5.sym=sym
+sgmii_ecp5.tft=tft
+sgmii_ecp5.txt=pcs_module
+[SYSTEMPNR]
+LN0=DCU1_CH1

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.ngd b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.ngd
new file mode 100644 (file)
index 0000000..0fdf86b
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.ngd differ

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.ngo b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.ngo
new file mode 100644 (file)
index 0000000..1f36cd8
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.ngo differ

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd
new file mode 100644 (file)
index 0000000..5cb3267
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd
@@ -0,0 +1,433 @@
+
+--
+-- Verific VHDL Description of module DCUA
+--
+
+-- DCUA is a black-box. Cannot print a valid VHDL entity description for it
+
+--
+-- Verific VHDL Description of module sgmii_ecp5rsl_core
+--
+
+-- sgmii_ecp5rsl_core is a black-box. Cannot print a valid VHDL entity description for it
+
+--
+-- Verific VHDL Description of module sgmii_ecp5sll_core
+--
+
+-- sgmii_ecp5sll_core is a black-box. Cannot print a valid VHDL entity description for it
+
+--
+-- Verific VHDL Description of module sgmii_ecp5
+--
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+library ecp5um ;
+use ecp5um.components.all ;
+
+entity sgmii_ecp5 is
+    port (hdoutp: out std_logic;
+        hdoutn: out std_logic;
+        hdinp: in std_logic;
+        hdinn: in std_logic;
+        rxrefclk: in std_logic;
+        tx_pclk: out std_logic;
+        txi_clk: in std_logic;
+        txdata: in std_logic_vector(7 downto 0);
+        tx_k: in std_logic_vector(0 downto 0);
+        xmit: in std_logic_vector(0 downto 0);
+        tx_disp_correct: in std_logic_vector(0 downto 0);
+        rxdata: out std_logic_vector(7 downto 0);
+        rx_k: out std_logic_vector(0 downto 0);
+        rx_disp_err: out std_logic_vector(0 downto 0);
+        rx_cv_err: out std_logic_vector(0 downto 0);
+        signal_detect_c: in std_logic;
+        rx_los_low_s: out std_logic;
+        lsm_status_s: out std_logic;
+        ctc_urun_s: out std_logic;
+        ctc_orun_s: out std_logic;
+        rx_cdr_lol_s: out std_logic;
+        ctc_ins_s: out std_logic;
+        ctc_del_s: out std_logic;
+        sli_rst: in std_logic;
+        tx_pwrup_c: in std_logic;
+        rx_pwrup_c: in std_logic;
+        sci_wrdata: in std_logic_vector(7 downto 0);
+        sci_addr: in std_logic_vector(5 downto 0);
+        sci_rddata: out std_logic_vector(7 downto 0);
+        sci_en_dual: in std_logic;
+        sci_sel_dual: in std_logic;
+        sci_en: in std_logic;
+        sci_sel: in std_logic;
+        sci_rd: in std_logic;
+        sci_wrn: in std_logic;
+        sci_int: out std_logic;
+        cyawstn: in std_logic;
+        serdes_pdb: in std_logic;
+        pll_refclki: in std_logic;
+        rsl_disable: in std_logic;
+        rsl_rst: in std_logic;
+        serdes_rst_dual_c: in std_logic;
+        rst_dual_c: in std_logic;
+        tx_serdes_rst_c: in std_logic;
+        tx_pcs_rst_c: in std_logic;
+        pll_lol: out std_logic;
+        rsl_tx_rdy: out std_logic;
+        rx_serdes_rst_c: in std_logic;
+        rx_pcs_rst_c: in std_logic;
+        rsl_rx_rdy: out std_logic
+    );
+    
+end entity sgmii_ecp5;
+
+architecture v1 of sgmii_ecp5 is 
+    component sgmii_ecp5rsl_core is
+        generic (pnum_channels: integer := 1;
+            pprotocol: string := "GBE";
+            pserdes_mode: string := "RX AND TX";
+            pport_tx_rdy: string := "ENABLED";
+            pwait_tx_rdy: integer := 3000;
+            pport_rx_rdy: string := "ENABLED";
+            pwait_rx_rdy: integer := 3000);
+        port (rui_rst: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(132)
+            rui_serdes_rst_dual_c: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(133)
+            rui_rst_dual_c: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(134)
+            rui_rsl_disable: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(135)
+            rui_tx_ref_clk: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(137)
+            rui_tx_serdes_rst_c: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(138)
+            rui_tx_pcs_rst_c: in std_logic_vector(3 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(139)
+            rdi_pll_lol: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(140)
+            rui_rx_ref_clk: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(142)
+            rui_rx_serdes_rst_c: in std_logic_vector(3 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(143)
+            rui_rx_pcs_rst_c: in std_logic_vector(3 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(144)
+            rdi_rx_los_low_s: in std_logic_vector(3 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(145)
+            rdi_rx_cdr_lol_s: in std_logic_vector(3 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(146)
+            rdo_serdes_rst_dual_c: out std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(149)
+            rdo_rst_dual_c: out std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(150)
+            ruo_tx_rdy: out std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(152)
+            rdo_tx_serdes_rst_c: out std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(153)
+            rdo_tx_pcs_rst_c: out std_logic_vector(3 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(154)
+            ruo_rx_rdy: out std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(156)
+            rdo_rx_serdes_rst_c: out std_logic_vector(3 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(157)
+            rdo_rx_pcs_rst_c: out std_logic_vector(3 downto 0)   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(158)
+        );
+        
+    end component sgmii_ecp5rsl_core; -- syn_black_box=1    -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(88)
+    component sgmii_ecp5sll_core is
+        generic (PPROTOCOL: string := "GBE";
+            PLOL_SETTING: integer := 0;
+            PDYN_RATE_CTRL: string := "DISABLED";
+            PPCIE_MAX_RATE: string := "2.5";
+            PDIFF_VAL_LOCK: integer := 39;
+            PDIFF_VAL_UNLOCK: integer := 78;
+            PPCLK_TC: integer := 131072;
+            PDIFF_DIV11_VAL_LOCK: integer := 0;
+            PDIFF_DIV11_VAL_UNLOCK: integer := 0;
+            PPCLK_DIV11_TC: integer := 0);
+        port (sli_rst: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(125)
+            sli_refclk: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(126)
+            sli_pclk: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(127)
+            sli_div2_rate: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(128)
+            sli_div11_rate: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(129)
+            sli_gear_mode: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(130)
+            sli_cpri_mode: in std_logic_vector(2 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(131)
+            sli_pcie_mode: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(132)
+            slo_plol: out std_logic   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(135)
+        );
+        
+    end component sgmii_ecp5sll_core; -- syn_black_box=1    -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(107)
+    signal n45,n44,n1,n2,n3,n4,tx_pclk_c,n5,n6,n7,n8,n9,n10,n11,
+        n12,n13,rx_los_low_s_c,n14,n15,rx_cdr_lol_s_c,rsl_tx_pcs_rst_c,
+        rsl_rx_pcs_rst_c,rsl_rx_serdes_rst_c,rsl_rst_dual_c,rsl_serdes_rst_dual_c,
+        rsl_tx_serdes_rst_c,n16,n17,n18,n19,n20,n21,n22,n23,n24,n25,
+        n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37,n38,n39,
+        n40,n41,n42,n43,n46,n103,n102,n47,n48,n49,n50,n51,n52,n53,
+        n54,n55,n56,n57,n58,n59,n60,n61,n62,n63,n64,n65,n66,n67,
+        n68,n69,n70,n71,n72,n73,n74,n75,n76,n77,n78,n79,n80,n81,
+        n82,n83,n84,n85,n86,n87,n88,n89,n90,n91,n92,n93,n94,n95,
+        n96,n97,n98,n99,n100,n101,n112,n111,n110,pll_lol_c,n122,n121,
+        n113,n114,n115,n116,n117,n118,n119,n120,\_Z\,n124,n123,gnd,
+        pwr : std_logic; 
+    attribute LOC : string;
+    attribute LOC of DCU1_inst : label is "DCU1";
+    attribute CHAN : string;
+    attribute CHAN of DCU1_inst : label is "CH1";
+begin
+    tx_pclk <= tx_pclk_c;
+    rx_los_low_s <= rx_los_low_s_c;
+    rx_cdr_lol_s <= rx_cdr_lol_s_c;
+    pll_lol <= pll_lol_c;
+    DCU1_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1",
+        D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0",
+        D_CDR_LOL_SET=>"0b00",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1",
+        D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1",
+        D_SYNC_ND_EN=>"0b0",CH1_UC_MODE=>"0b0",CH1_PCIE_MODE=>"0b0",CH1_RIO_MODE=>"0b0",
+        CH1_WA_MODE=>"0b0",CH1_INVERT_RX=>"0b0",CH1_INVERT_TX=>"0b0",CH1_PRBS_SELECTION=>"0b0",
+        CH1_GE_AN_ENABLE=>"0b0",CH1_PRBS_LOCK=>"0b0",CH1_PRBS_ENABLE=>"0b0",
+        CH1_ENABLE_CG_ALIGN=>"0b1",CH1_TX_GEAR_MODE=>"0b0",CH1_RX_GEAR_MODE=>"0b0",
+        CH1_PCS_DET_TIME_SEL=>"0b00",CH1_PCIE_EI_EN=>"0b0",CH1_TX_GEAR_BYPASS=>"0b0",
+        CH1_ENC_BYPASS=>"0b0",CH1_SB_BYPASS=>"0b0",CH1_RX_SB_BYPASS=>"0b0",
+        CH1_WA_BYPASS=>"0b0",CH1_DEC_BYPASS=>"0b0",CH1_CTC_BYPASS=>"0b0",
+        CH1_RX_GEAR_BYPASS=>"0b0",CH1_LSM_DISABLE=>"0b0",CH1_MATCH_2_ENABLE=>"0b1",
+        CH1_MATCH_4_ENABLE=>"0b0",CH1_MIN_IPG_CNT=>"0b11",CH1_CC_MATCH_1=>"0x000",
+        CH1_CC_MATCH_2=>"0x000",CH1_CC_MATCH_3=>"0x1BC",CH1_CC_MATCH_4=>"0x050",
+        CH1_UDF_COMMA_MASK=>"0x3ff",CH1_UDF_COMMA_A=>"0x283",CH1_UDF_COMMA_B=>"0x17C",
+        CH1_RX_DCO_CK_DIV=>"0b010",CH1_RCV_DCC_EN=>"0b0",CH1_TPWDNB=>"0b1",
+        CH1_RATE_MODE_TX=>"0b0",CH1_RTERM_TX=>"0d19",CH1_TX_CM_SEL=>"0b00",
+        CH1_TDRV_PRE_EN=>"0b0",CH1_TDRV_SLICE0_SEL=>"0b01",CH1_TDRV_SLICE1_SEL=>"0b00",
+        CH1_TDRV_SLICE2_SEL=>"0b01",CH1_TDRV_SLICE3_SEL=>"0b01",CH1_TDRV_SLICE4_SEL=>"0b01",
+        CH1_TDRV_SLICE5_SEL=>"0b01",CH1_TDRV_SLICE0_CUR=>"0b101",CH1_TDRV_SLICE1_CUR=>"0b000",
+        CH1_TDRV_SLICE2_CUR=>"0b11",CH1_TDRV_SLICE3_CUR=>"0b11",CH1_TDRV_SLICE4_CUR=>"0b11",
+        CH1_TDRV_SLICE5_CUR=>"0b00",CH1_TDRV_DAT_SEL=>"0b00",CH1_TX_DIV11_SEL=>"0b0",
+        CH1_RPWDNB=>"0b1",CH1_RATE_MODE_RX=>"0b0",CH1_RX_DIV11_SEL=>"0b0",
+        CH1_SEL_SD_RX_CLK=>"0b0",CH1_FF_RX_H_CLK_EN=>"0b0",CH1_FF_RX_F_CLK_DIS=>"0b0",
+        CH1_FF_TX_H_CLK_EN=>"0b0",CH1_FF_TX_F_CLK_DIS=>"0b0",CH1_TDRV_POST_EN=>"0b0",
+        CH1_TX_POST_SIGN=>"0b0",CH1_TX_PRE_SIGN=>"0b0",CH1_REQ_LVL_SET=>"0b00",
+        CH1_REQ_EN=>"0b1",CH1_RTERM_RX=>"0d22",CH1_RXTERM_CM=>"0b11",CH1_PDEN_SEL=>"0b1",
+        CH1_RXIN_CM=>"0b11",CH1_LEQ_OFFSET_SEL=>"0b0",CH1_LEQ_OFFSET_TRIM=>"0b000",
+        CH1_RLOS_SEL=>"0b1",CH1_RX_LOS_LVL=>"0b010",CH1_RX_LOS_CEQ=>"0b11",
+        CH1_RX_LOS_HYST_EN=>"0b0",CH1_RX_LOS_EN=>"0b1",CH1_LDR_RX2CORE_SEL=>"0b0",
+        CH1_LDR_CORE2TX_SEL=>"0b0",D_TX_MAX_RATE=>"1.25",CH1_CDR_MAX_RATE=>"1.25",
+        CH1_TXAMPLITUDE=>"0d1100",CH1_TXDEPRE=>"DISABLED",CH1_TXDEPOST=>"DISABLED",
+        CH1_PROTOCOL=>"GBE",D_ISETLOS=>"0d0",D_SETIRPOLY_AUX=>"0b00",D_SETICONST_AUX=>"0b00",
+        D_SETIRPOLY_CH=>"0b00",D_SETICONST_CH=>"0b00",D_REQ_ISET=>"0b000",
+        D_PD_ISET=>"0b00",D_DCO_CALIB_TIME_SEL=>"0b00",CH1_CDR_CNT4SEL=>"0b00",
+        CH1_CDR_CNT8SEL=>"0b00",CH1_DCOATDCFG=>"0b00",CH1_DCOATDDLY=>"0b00",
+        CH1_DCOBYPSATD=>"0b1",CH1_DCOCALDIV=>"0b001",CH1_DCOCTLGI=>"0b010",
+        CH1_DCODISBDAVOID=>"0b0",CH1_DCOFLTDAC=>"0b01",CH1_DCOFTNRG=>"0b110",
+        CH1_DCOIOSTUNE=>"0b000",CH1_DCOITUNE=>"0b00",CH1_DCOITUNE4LSB=>"0b111",
+        CH1_DCOIUPDNX2=>"0b1",CH1_DCONUOFLSB=>"0b101",CH1_DCOSCALEI=>"0b00",
+        CH1_DCOSTARTVAL=>"0b000",CH1_DCOSTEP=>"0b00",CH1_BAND_THRESHOLD=>"0d0",
+        CH1_AUTO_FACQ_EN=>"0b1",CH1_AUTO_CALIB_EN=>"0b1",CH1_CALIB_CK_MODE=>"0b0",
+        CH1_REG_BAND_OFFSET=>"0d0",CH1_REG_BAND_SEL=>"0d0",CH1_REG_IDAC_SEL=>"0d0",
+        CH1_REG_IDAC_EN=>"0b0",D_CMUSETISCL4VCO=>"0b000",D_CMUSETI4VCO=>"0b00",
+        D_CMUSETINITVCT=>"0b00",D_CMUSETZGM=>"0b000",D_CMUSETP2AGM=>"0b000",
+        D_CMUSETP1GM=>"0b000",D_CMUSETI4CPZ=>"0d3",D_CMUSETI4CPP=>"0d3",D_CMUSETICP4Z=>"0b101",
+        D_CMUSETICP4P=>"0b01",D_CMUSETBIASI=>"0b00",D_SETPLLRC=>"0d1",CH1_RX_RATE_SEL=>"0d8",
+        D_REFCK_MODE=>"0b001",D_TX_VCO_CK_DIV=>"0b010",D_PLL_LOL_SET=>"0b00",
+        D_RG_EN=>"0b0",D_RG_SET=>"0b00")
+     port map (CH0_HDINP=>n103,CH1_HDINP=>hdinp,CH0_HDINN=>n103,CH1_HDINN=>hdinn,
+    D_TXBIT_CLKP_FROM_ND=>n44,D_TXBIT_CLKN_FROM_ND=>n44,D_SYNC_ND=>n44,D_TXPLL_LOL_FROM_ND=>n44,
+    CH0_RX_REFCLK=>n103,CH1_RX_REFCLK=>rxrefclk,CH0_FF_RXI_CLK=>n102,CH1_FF_RXI_CLK=>tx_pclk_c,
+    CH0_FF_TXI_CLK=>n102,CH1_FF_TXI_CLK=>txi_clk,CH0_FF_EBRD_CLK=>n102,CH1_FF_EBRD_CLK=>tx_pclk_c,
+    CH0_FF_TX_D_0=>n103,CH1_FF_TX_D_0=>txdata(0),CH0_FF_TX_D_1=>n103,CH1_FF_TX_D_1=>txdata(1),
+    CH0_FF_TX_D_2=>n103,CH1_FF_TX_D_2=>txdata(2),CH0_FF_TX_D_3=>n103,CH1_FF_TX_D_3=>txdata(3),
+    CH0_FF_TX_D_4=>n103,CH1_FF_TX_D_4=>txdata(4),CH0_FF_TX_D_5=>n103,CH1_FF_TX_D_5=>txdata(5),
+    CH0_FF_TX_D_6=>n103,CH1_FF_TX_D_6=>txdata(6),CH0_FF_TX_D_7=>n103,CH1_FF_TX_D_7=>txdata(7),
+    CH0_FF_TX_D_8=>n103,CH1_FF_TX_D_8=>tx_k(0),CH0_FF_TX_D_9=>n103,CH1_FF_TX_D_9=>n44,
+    CH0_FF_TX_D_10=>n103,CH1_FF_TX_D_10=>xmit(0),CH0_FF_TX_D_11=>n103,CH1_FF_TX_D_11=>tx_disp_correct(0),
+    CH0_FF_TX_D_12=>n103,CH1_FF_TX_D_12=>n103,CH0_FF_TX_D_13=>n103,CH1_FF_TX_D_13=>n103,
+    CH0_FF_TX_D_14=>n103,CH1_FF_TX_D_14=>n103,CH0_FF_TX_D_15=>n103,CH1_FF_TX_D_15=>n103,
+    CH0_FF_TX_D_16=>n103,CH1_FF_TX_D_16=>n103,CH0_FF_TX_D_17=>n103,CH1_FF_TX_D_17=>n103,
+    CH0_FF_TX_D_18=>n103,CH1_FF_TX_D_18=>n103,CH0_FF_TX_D_19=>n103,CH1_FF_TX_D_19=>n103,
+    CH0_FF_TX_D_20=>n103,CH1_FF_TX_D_20=>n103,CH0_FF_TX_D_21=>n103,CH1_FF_TX_D_21=>n44,
+    CH0_FF_TX_D_22=>n103,CH1_FF_TX_D_22=>n103,CH0_FF_TX_D_23=>n103,CH1_FF_TX_D_23=>n103,
+    CH0_FFC_EI_EN=>n103,CH1_FFC_EI_EN=>n44,CH0_FFC_PCIE_DET_EN=>n103,CH1_FFC_PCIE_DET_EN=>n44,
+    CH0_FFC_PCIE_CT=>n103,CH1_FFC_PCIE_CT=>n44,CH0_FFC_SB_INV_RX=>n103,CH1_FFC_SB_INV_RX=>n103,
+    CH0_FFC_ENABLE_CGALIGN=>n103,CH1_FFC_ENABLE_CGALIGN=>n103,CH0_FFC_SIGNAL_DETECT=>n103,
+    CH1_FFC_SIGNAL_DETECT=>signal_detect_c,CH0_FFC_FB_LOOPBACK=>n103,CH1_FFC_FB_LOOPBACK=>n44,
+    CH0_FFC_SB_PFIFO_LP=>n103,CH1_FFC_SB_PFIFO_LP=>n44,CH0_FFC_PFIFO_CLR=>n103,
+    CH1_FFC_PFIFO_CLR=>n44,CH0_FFC_RATE_MODE_RX=>n103,CH1_FFC_RATE_MODE_RX=>n44,
+    CH0_FFC_RATE_MODE_TX=>n103,CH1_FFC_RATE_MODE_TX=>n44,CH0_FFC_DIV11_MODE_RX=>n103,
+    CH1_FFC_DIV11_MODE_RX=>n44,CH0_FFC_DIV11_MODE_TX=>n103,CH1_FFC_DIV11_MODE_TX=>n44,
+    CH0_FFC_RX_GEAR_MODE=>n103,CH1_FFC_RX_GEAR_MODE=>n44,CH0_FFC_TX_GEAR_MODE=>n103,
+    CH1_FFC_TX_GEAR_MODE=>n44,CH0_FFC_LDR_CORE2TX_EN=>n103,CH1_FFC_LDR_CORE2TX_EN=>n103,
+    CH0_FFC_LANE_TX_RST=>n103,CH1_FFC_LANE_TX_RST=>rsl_tx_pcs_rst_c,CH0_FFC_LANE_RX_RST=>n103,
+    CH1_FFC_LANE_RX_RST=>rsl_rx_pcs_rst_c,CH0_FFC_RRST=>n103,CH1_FFC_RRST=>rsl_rx_serdes_rst_c,
+    CH0_FFC_TXPWDNB=>n103,CH1_FFC_TXPWDNB=>tx_pwrup_c,CH0_FFC_RXPWDNB=>n103,
+    CH1_FFC_RXPWDNB=>rx_pwrup_c,CH0_LDR_CORE2TX=>n103,CH1_LDR_CORE2TX=>n103,
+    D_SCIWDATA0=>sci_wrdata(0),D_SCIWDATA1=>sci_wrdata(1),D_SCIWDATA2=>sci_wrdata(2),
+    D_SCIWDATA3=>sci_wrdata(3),D_SCIWDATA4=>sci_wrdata(4),D_SCIWDATA5=>sci_wrdata(5),
+    D_SCIWDATA6=>sci_wrdata(6),D_SCIWDATA7=>sci_wrdata(7),D_SCIADDR0=>sci_addr(0),
+    D_SCIADDR1=>sci_addr(1),D_SCIADDR2=>sci_addr(2),D_SCIADDR3=>sci_addr(3),
+    D_SCIADDR4=>sci_addr(4),D_SCIADDR5=>sci_addr(5),D_SCIENAUX=>sci_en_dual,
+    D_SCISELAUX=>sci_sel_dual,CH0_SCIEN=>n103,CH1_SCIEN=>sci_en,CH0_SCISEL=>n103,
+    CH1_SCISEL=>sci_sel,D_SCIRD=>sci_rd,D_SCIWSTN=>sci_wrn,D_CYAWSTN=>cyawstn,
+    D_FFC_SYNC_TOGGLE=>n103,D_FFC_DUAL_RST=>rsl_rst_dual_c,D_FFC_MACRO_RST=>rsl_serdes_rst_dual_c,
+    D_FFC_MACROPDB=>serdes_pdb,D_FFC_TRST=>rsl_tx_serdes_rst_c,CH0_FFC_CDR_EN_BITSLIP=>n103,
+    CH1_FFC_CDR_EN_BITSLIP=>n44,D_SCAN_ENABLE=>n44,D_SCAN_IN_0=>n44,D_SCAN_IN_1=>n44,
+    D_SCAN_IN_2=>n44,D_SCAN_IN_3=>n44,D_SCAN_IN_4=>n44,D_SCAN_IN_5=>n44,
+    D_SCAN_IN_6=>n44,D_SCAN_IN_7=>n44,D_SCAN_MODE=>n44,D_SCAN_RESET=>n44,
+    D_CIN0=>n44,D_CIN1=>n44,D_CIN2=>n44,D_CIN3=>n44,D_CIN4=>n44,D_CIN5=>n44,
+    D_CIN6=>n44,D_CIN7=>n44,D_CIN8=>n44,D_CIN9=>n44,D_CIN10=>n44,D_CIN11=>n44,
+    CH0_HDOUTP=>n47,CH1_HDOUTP=>hdoutp,CH0_HDOUTN=>n48,CH1_HDOUTN=>hdoutn,
+    D_TXBIT_CLKP_TO_ND=>n1,D_TXBIT_CLKN_TO_ND=>n2,D_SYNC_PULSE2ND=>n3,D_TXPLL_LOL_TO_ND=>n4,
+    CH0_FF_RX_F_CLK=>n49,CH1_FF_RX_F_CLK=>n5,CH0_FF_RX_H_CLK=>n50,CH1_FF_RX_H_CLK=>n6,
+    CH0_FF_TX_F_CLK=>n51,CH1_FF_TX_F_CLK=>n7,CH0_FF_TX_H_CLK=>n52,CH1_FF_TX_H_CLK=>n8,
+    CH0_FF_RX_PCLK=>n53,CH1_FF_RX_PCLK=>n9,CH0_FF_TX_PCLK=>n54,CH1_FF_TX_PCLK=>tx_pclk_c,
+    CH0_FF_RX_D_0=>n55,CH1_FF_RX_D_0=>rxdata(0),CH0_FF_RX_D_1=>n56,CH1_FF_RX_D_1=>rxdata(1),
+    CH0_FF_RX_D_2=>n57,CH1_FF_RX_D_2=>rxdata(2),CH0_FF_RX_D_3=>n58,CH1_FF_RX_D_3=>rxdata(3),
+    CH0_FF_RX_D_4=>n59,CH1_FF_RX_D_4=>rxdata(4),CH0_FF_RX_D_5=>n60,CH1_FF_RX_D_5=>rxdata(5),
+    CH0_FF_RX_D_6=>n61,CH1_FF_RX_D_6=>rxdata(6),CH0_FF_RX_D_7=>n62,CH1_FF_RX_D_7=>rxdata(7),
+    CH0_FF_RX_D_8=>n63,CH1_FF_RX_D_8=>rx_k(0),CH0_FF_RX_D_9=>n64,CH1_FF_RX_D_9=>rx_disp_err(0),
+    CH0_FF_RX_D_10=>n65,CH1_FF_RX_D_10=>rx_cv_err(0),CH0_FF_RX_D_11=>n66,
+    CH1_FF_RX_D_11=>n10,CH0_FF_RX_D_12=>n67,CH1_FF_RX_D_12=>n68,CH0_FF_RX_D_13=>n69,
+    CH1_FF_RX_D_13=>n70,CH0_FF_RX_D_14=>n71,CH1_FF_RX_D_14=>n72,CH0_FF_RX_D_15=>n73,
+    CH1_FF_RX_D_15=>n74,CH0_FF_RX_D_16=>n75,CH1_FF_RX_D_16=>n76,CH0_FF_RX_D_17=>n77,
+    CH1_FF_RX_D_17=>n78,CH0_FF_RX_D_18=>n79,CH1_FF_RX_D_18=>n80,CH0_FF_RX_D_19=>n81,
+    CH1_FF_RX_D_19=>n82,CH0_FF_RX_D_20=>n83,CH1_FF_RX_D_20=>n84,CH0_FF_RX_D_21=>n85,
+    CH1_FF_RX_D_21=>n86,CH0_FF_RX_D_22=>n87,CH1_FF_RX_D_22=>n88,CH0_FF_RX_D_23=>n89,
+    CH1_FF_RX_D_23=>n11,CH0_FFS_PCIE_DONE=>n90,CH1_FFS_PCIE_DONE=>n12,CH0_FFS_PCIE_CON=>n91,
+    CH1_FFS_PCIE_CON=>n13,CH0_FFS_RLOS=>n92,CH1_FFS_RLOS=>rx_los_low_s_c,
+    CH0_FFS_LS_SYNC_STATUS=>n93,CH1_FFS_LS_SYNC_STATUS=>lsm_status_s,CH0_FFS_CC_UNDERRUN=>n94,
+    CH1_FFS_CC_UNDERRUN=>ctc_urun_s,CH0_FFS_CC_OVERRUN=>n95,CH1_FFS_CC_OVERRUN=>ctc_orun_s,
+    CH0_FFS_RXFBFIFO_ERROR=>n96,CH1_FFS_RXFBFIFO_ERROR=>n14,CH0_FFS_TXFBFIFO_ERROR=>n97,
+    CH1_FFS_TXFBFIFO_ERROR=>n15,CH0_FFS_RLOL=>n98,CH1_FFS_RLOL=>rx_cdr_lol_s_c,
+    CH0_FFS_SKP_ADDED=>n99,CH1_FFS_SKP_ADDED=>ctc_ins_s,CH0_FFS_SKP_DELETED=>n100,
+    CH1_FFS_SKP_DELETED=>ctc_del_s,CH0_LDR_RX2CORE=>n101,CH1_LDR_RX2CORE=>n112,
+    D_SCIRDATA0=>sci_rddata(0),D_SCIRDATA1=>sci_rddata(1),D_SCIRDATA2=>sci_rddata(2),
+    D_SCIRDATA3=>sci_rddata(3),D_SCIRDATA4=>sci_rddata(4),D_SCIRDATA5=>sci_rddata(5),
+    D_SCIRDATA6=>sci_rddata(6),D_SCIRDATA7=>sci_rddata(7),D_SCIINT=>sci_int,
+    D_SCAN_OUT_0=>n16,D_SCAN_OUT_1=>n17,D_SCAN_OUT_2=>n18,D_SCAN_OUT_3=>n19,
+    D_SCAN_OUT_4=>n20,D_SCAN_OUT_5=>n21,D_SCAN_OUT_6=>n22,D_SCAN_OUT_7=>n23,
+    D_COUT0=>n24,D_COUT1=>n25,D_COUT2=>n26,D_COUT3=>n27,D_COUT4=>n28,D_COUT5=>n29,
+    D_COUT6=>n30,D_COUT7=>n31,D_COUT8=>n32,D_COUT9=>n33,D_COUT10=>n34,D_COUT11=>n35,
+    D_COUT12=>n36,D_COUT13=>n37,D_COUT14=>n38,D_COUT15=>n39,D_COUT16=>n40,
+    D_COUT17=>n41,D_COUT18=>n42,D_COUT19=>n43,D_REFCLKI=>pll_refclki,D_FFS_PLOL=>n46);
+    n45 <= '1' ;
+    n44 <= '0' ;
+    n1 <= 'Z' ;
+    n2 <= 'Z' ;
+    n3 <= 'Z' ;
+    n4 <= 'Z' ;
+    n5 <= 'Z' ;
+    n6 <= 'Z' ;
+    n7 <= 'Z' ;
+    n8 <= 'Z' ;
+    n9 <= 'Z' ;
+    n10 <= 'Z' ;
+    n11 <= 'Z' ;
+    n12 <= 'Z' ;
+    n13 <= 'Z' ;
+    n14 <= 'Z' ;
+    n15 <= 'Z' ;
+    n16 <= 'Z' ;
+    n17 <= 'Z' ;
+    n18 <= 'Z' ;
+    n19 <= 'Z' ;
+    n20 <= 'Z' ;
+    n21 <= 'Z' ;
+    n22 <= 'Z' ;
+    n23 <= 'Z' ;
+    n24 <= 'Z' ;
+    n25 <= 'Z' ;
+    n26 <= 'Z' ;
+    n27 <= 'Z' ;
+    n28 <= 'Z' ;
+    n29 <= 'Z' ;
+    n30 <= 'Z' ;
+    n31 <= 'Z' ;
+    n32 <= 'Z' ;
+    n33 <= 'Z' ;
+    n34 <= 'Z' ;
+    n35 <= 'Z' ;
+    n36 <= 'Z' ;
+    n37 <= 'Z' ;
+    n38 <= 'Z' ;
+    n39 <= 'Z' ;
+    n40 <= 'Z' ;
+    n41 <= 'Z' ;
+    n42 <= 'Z' ;
+    n43 <= 'Z' ;
+    n46 <= 'Z' ;
+    n103 <= '0' ;
+    n102 <= '1' ;
+    n47 <= 'Z' ;
+    n48 <= 'Z' ;
+    n49 <= 'Z' ;
+    n50 <= 'Z' ;
+    n51 <= 'Z' ;
+    n52 <= 'Z' ;
+    n53 <= 'Z' ;
+    n54 <= 'Z' ;
+    n55 <= 'Z' ;
+    n56 <= 'Z' ;
+    n57 <= 'Z' ;
+    n58 <= 'Z' ;
+    n59 <= 'Z' ;
+    n60 <= 'Z' ;
+    n61 <= 'Z' ;
+    n62 <= 'Z' ;
+    n63 <= 'Z' ;
+    n64 <= 'Z' ;
+    n65 <= 'Z' ;
+    n66 <= 'Z' ;
+    n67 <= 'Z' ;
+    n68 <= 'Z' ;
+    n69 <= 'Z' ;
+    n70 <= 'Z' ;
+    n71 <= 'Z' ;
+    n72 <= 'Z' ;
+    n73 <= 'Z' ;
+    n74 <= 'Z' ;
+    n75 <= 'Z' ;
+    n76 <= 'Z' ;
+    n77 <= 'Z' ;
+    n78 <= 'Z' ;
+    n79 <= 'Z' ;
+    n80 <= 'Z' ;
+    n81 <= 'Z' ;
+    n82 <= 'Z' ;
+    n83 <= 'Z' ;
+    n84 <= 'Z' ;
+    n85 <= 'Z' ;
+    n86 <= 'Z' ;
+    n87 <= 'Z' ;
+    n88 <= 'Z' ;
+    n89 <= 'Z' ;
+    n90 <= 'Z' ;
+    n91 <= 'Z' ;
+    n92 <= 'Z' ;
+    n93 <= 'Z' ;
+    n94 <= 'Z' ;
+    n95 <= 'Z' ;
+    n96 <= 'Z' ;
+    n97 <= 'Z' ;
+    n98 <= 'Z' ;
+    n99 <= 'Z' ;
+    n100 <= 'Z' ;
+    n101 <= 'Z' ;
+    n112 <= 'Z' ;
+    rsl_inst: component sgmii_ecp5rsl_core port map (rui_rst=>rsl_rst,rui_serdes_rst_dual_c=>serdes_rst_dual_c,
+            rui_rst_dual_c=>rst_dual_c,rui_rsl_disable=>rsl_disable,rui_tx_ref_clk=>pll_refclki,
+            rui_tx_serdes_rst_c=>tx_serdes_rst_c,rui_tx_pcs_rst_c(3)=>n122,
+            rui_tx_pcs_rst_c(2)=>n122,rui_tx_pcs_rst_c(1)=>n122,rui_tx_pcs_rst_c(0)=>tx_pcs_rst_c,
+            rdi_pll_lol=>pll_lol_c,rui_rx_ref_clk=>rxrefclk,rui_rx_serdes_rst_c(3)=>n122,
+            rui_rx_serdes_rst_c(2)=>n122,rui_rx_serdes_rst_c(1)=>n122,rui_rx_serdes_rst_c(0)=>rx_serdes_rst_c,
+            rui_rx_pcs_rst_c(3)=>n122,rui_rx_pcs_rst_c(2)=>n122,rui_rx_pcs_rst_c(1)=>n122,
+            rui_rx_pcs_rst_c(0)=>rx_pcs_rst_c,rdi_rx_los_low_s(3)=>n122,rdi_rx_los_low_s(2)=>n122,
+            rdi_rx_los_low_s(1)=>n122,rdi_rx_los_low_s(0)=>rx_los_low_s_c,
+            rdi_rx_cdr_lol_s(3)=>n122,rdi_rx_cdr_lol_s(2)=>n122,rdi_rx_cdr_lol_s(1)=>n122,
+            rdi_rx_cdr_lol_s(0)=>rx_cdr_lol_s_c,rdo_serdes_rst_dual_c=>rsl_serdes_rst_dual_c,
+            rdo_rst_dual_c=>rsl_rst_dual_c,ruo_tx_rdy=>rsl_tx_rdy,rdo_tx_serdes_rst_c=>rsl_tx_serdes_rst_c,
+            rdo_tx_pcs_rst_c(3)=>n113,rdo_tx_pcs_rst_c(2)=>n114,rdo_tx_pcs_rst_c(1)=>n115,
+            rdo_tx_pcs_rst_c(0)=>rsl_tx_pcs_rst_c,ruo_rx_rdy=>rsl_rx_rdy,rdo_rx_serdes_rst_c(3)=>n116,
+            rdo_rx_serdes_rst_c(2)=>n117,rdo_rx_serdes_rst_c(1)=>n118,rdo_rx_serdes_rst_c(0)=>rsl_rx_serdes_rst_c,
+            rdo_rx_pcs_rst_c(3)=>n119,rdo_rx_pcs_rst_c(2)=>n120,rdo_rx_pcs_rst_c(1)=>\_Z\,
+            rdo_rx_pcs_rst_c(0)=>rsl_rx_pcs_rst_c);
+    n111 <= '1' ;
+    n110 <= '0' ;
+    n122 <= '0' ;
+    n121 <= '1' ;
+    n113 <= 'Z' ;
+    n114 <= 'Z' ;
+    n115 <= 'Z' ;
+    n116 <= 'Z' ;
+    n117 <= 'Z' ;
+    n118 <= 'Z' ;
+    n119 <= 'Z' ;
+    n120 <= 'Z' ;
+    \_Z\ <= 'Z' ;
+    sll_inst: component sgmii_ecp5sll_core port map (sli_rst=>sli_rst,sli_refclk=>pll_refclki,
+            sli_pclk=>tx_pclk_c,sli_div2_rate=>gnd,sli_div11_rate=>gnd,sli_gear_mode=>gnd,
+            sli_cpri_mode(2)=>gnd,sli_cpri_mode(1)=>gnd,sli_cpri_mode(0)=>gnd,
+            sli_pcie_mode=>gnd,slo_plol=>pll_lol_c);
+    n124 <= '1' ;
+    n123 <= '0' ;
+    gnd <= '0' ;
+    pwr <= '1' ;
+    
+end architecture v1;
+

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_ngd.asd b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_ngd.asd
new file mode 100644 (file)
index 0000000..c265c78
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_ngd.asd
@@ -0,0 +1 @@
+[ActiveSupport NGD]

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v
new file mode 100644 (file)
index 0000000..69a023d
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v
@@ -0,0 +1,2003 @@
+
+
+//   ===========================================================================
+//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
+//   ---------------------------------------------------------------------------
+//   Copyright (c) 2016 by Lattice Semiconductor Corporation
+//   ALL RIGHTS RESERVED
+//   ------------------------------------------------------------------
+//
+//   Permission:
+//
+//      Lattice SG Pte. Ltd. grants permission to use this code
+//      pursuant to the terms of the Lattice Reference Design License Agreement.
+//
+//
+//   Disclaimer:
+//
+//      This VHDL or Verilog source code is intended as a design reference
+//      which illustrates how these types of functions can be implemented.
+//      It is the user's responsibility to verify their design for
+//      consistency and functionality through the use of formal
+//      verification methods.  Lattice provides no warranty
+//      regarding the use or functionality of this code.
+//
+//   ---------------------------------------------------------------------------
+//
+//                  Lattice SG Pte. Ltd.
+//                  101 Thomson Road, United Square #07-02
+//                  Singapore 307591
+//
+//
+//                  TEL: 1-800-Lattice (USA and Canada)
+//                       +65-6631-2000 (Singapore)
+//                       +1-503-268-8001 (other locations)
+//
+//                  web: http://www.latticesemi.com/
+//                  email: techsupport@latticesemi.com
+//
+//   ---------------------------------------------------------------------------
+//
+// =============================================================================
+//                         FILE DETAILS
+// Project               : RSL- Reset Sequence Logic
+// File                  : rsl_core.v
+// Title                 : Top-level file for RSL
+// Dependencies          : 1.
+//                       : 2.
+// Description           :
+// =============================================================================
+//                        REVISION HISTORY
+// Version               : 1.0
+// Author(s)             : BM
+// Mod. Date             : October 28, 2013
+// Changes Made          : Initial Creation
+// -----------------------------------------------------------------------------
+// Version               : 1.1
+// Author(s)             : BM
+// Mod. Date             : November 06, 2013
+// Changes Made          : Tx/Rx separation, ready port code exclusion
+// -----------------------------------------------------------------------------
+// Version               : 1.2
+// Author(s)             : BM
+// Mod. Date             : June 13, 2014
+// Changes Made          : Updated Rx PCS reset method
+// -----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
+// Version               : 1.3
+// Author(s)             : UA
+// Mod. Date             : Dec 19, 2014
+// Changes Made          : Added new parameter fro PCIE
+// -----------------------------------------------------------------------------
+// Version               : 1.31
+// Author(s)             : BM/UM
+// Mod. Date             : Feb 23, 2016
+// Changes Made          : Behavior of rx_rdy output modified. The output rx_rdy
+//                         and the rx_rdy wait counter are reset to zero on
+//                         LOL or LOS. Reverted back the counter value change for PCIE.
+// -----------------------------------------------------------------------------
+// Version               : 1.4
+// Author(s)             : EB
+// Mod. Date:            : March 21, 2017
+// Changes Made          :
+// -----------------------------------------------------------------------------
+// Version               : 1.5
+// Author(s)             : ES
+// Mod. Date:            : May 8, 2017
+// Changes Made          : Implemented common RSL behaviour as proposed by BM.
+// =============================================================================
+
+`timescale 1ns/10ps
+
+module sgmii_ecp5rsl_core (
+      // ------------ Inputs
+      // Common
+      rui_rst,               // Active high reset for the RSL module
+      rui_serdes_rst_dual_c, // SERDES macro reset user command
+      rui_rst_dual_c,        // PCS dual reset user command
+      rui_rsl_disable,       // Active high signal that disables all reset outputs of RSL
+      // Tx
+      rui_tx_ref_clk,        // Tx reference clock
+      rui_tx_serdes_rst_c,   // Tx SERDES reset user command
+      rui_tx_pcs_rst_c,      // Tx lane reset user command
+      rdi_pll_lol,           // Tx PLL Loss of Lock status input from the SERDES
+      // Rx
+      rui_rx_ref_clk,        // Rx reference clock
+      rui_rx_serdes_rst_c,   // SERDES Receive channel reset user command
+      rui_rx_pcs_rst_c,      // Rx lane reset user command
+      rdi_rx_los_low_s,      // Receive loss of signal status input from SERDES
+      rdi_rx_cdr_lol_s,      // Receive CDR loss of lock status input from SERDES
+
+      // ------------ Outputs
+      // Common
+      rdo_serdes_rst_dual_c, // SERDES macro reset command output
+      rdo_rst_dual_c,        // PCS dual reset command output
+      // Tx
+      ruo_tx_rdy,            // Tx lane ready status output
+      rdo_tx_serdes_rst_c,   // SERDES Tx reset command output
+      rdo_tx_pcs_rst_c,      // PCS Tx lane reset command output
+      // Rx
+      ruo_rx_rdy,            // Rx lane ready status output
+      rdo_rx_serdes_rst_c,   // SERDES Rx channel reset command output
+      rdo_rx_pcs_rst_c       // PCS Rx lane reset command output
+      );
+
+// ------------ Module parameters
+`ifdef NUM_CHANNELS
+   parameter pnum_channels = `NUM_CHANNELS;    // 1,2,4
+`else
+   parameter pnum_channels = 1;
+`endif
+
+`ifdef PCIE
+   parameter pprotocol    = "PCIE";
+`else
+   parameter pprotocol    = "";
+`endif
+
+`ifdef RX_ONLY
+   parameter pserdes_mode    = "RX ONLY";
+`else
+   `ifdef TX_ONLY
+      parameter pserdes_mode = "TX ONLY";
+   `else
+      parameter pserdes_mode = "RX AND TX";
+   `endif
+`endif
+
+`ifdef PORT_TX_RDY
+   parameter pport_tx_rdy = "ENABLED";
+`else
+   parameter pport_tx_rdy = "DISABLED";
+`endif
+
+`ifdef WAIT_TX_RDY
+   parameter pwait_tx_rdy = `WAIT_TX_RDY;
+`else
+   parameter pwait_tx_rdy = 3000;
+`endif
+
+`ifdef PORT_RX_RDY
+   parameter pport_rx_rdy = "ENABLED";
+`else
+   parameter pport_rx_rdy = "DISABLED";
+`endif
+
+`ifdef WAIT_RX_RDY
+   parameter pwait_rx_rdy = `WAIT_RX_RDY;
+`else
+   parameter pwait_rx_rdy = 3000;
+`endif
+
+// ------------ Local parameters
+   localparam wa_num_cycles      = 1024;
+   localparam dac_num_cycles     = 3;
+   localparam lreset_pwidth      = 3;      // reset pulse width-1, default=4-1=3
+   localparam lwait_b4_trst      = 781250; // 5ms wait with worst-case Fmax=156 MHz
+   localparam lwait_b4_trst_s    = 781;    // for simulation
+   localparam lplol_cnt_width    = 20;     // width for lwait_b4_trst
+   localparam lwait_after_plol0  = 4;
+   localparam lwait_b4_rrst      = 180224; // total calibration time
+   localparam lrrst_wait_width   = 20;
+   localparam lwait_after_rrst   = 800000; // For CPRI- unused
+   localparam lwait_b4_rrst_s    = 460;    // wait cycles provided by design team
+   localparam lrlol_cnt_width    = 19;     // width for lwait_b4_rrst
+   localparam lwait_after_lols   = (16384 * dac_num_cycles) + wa_num_cycles;  // 16384 cycles * dac_num_cycles + 1024 cycles
+   localparam lwait_after_lols_s = 150;    // wait cycles provided by design team
+   localparam llols_cnt_width    = 18;     // lols count width
+   localparam lrdb_max           = 15;     // maximum debounce count
+   localparam ltxr_wait_width    = 12;     // width of tx ready wait counter
+   localparam lrxr_wait_width    = 12;     // width of tx ready wait counter
+
+// ------------ input ports
+   input                         rui_rst;
+   input                         rui_serdes_rst_dual_c;
+   input                         rui_rst_dual_c;
+   input                         rui_rsl_disable;
+
+   input                         rui_tx_ref_clk;
+   input                         rui_tx_serdes_rst_c;
+   input  [3:0]                  rui_tx_pcs_rst_c;
+   input                         rdi_pll_lol;
+
+   input                         rui_rx_ref_clk;
+   input  [3:0]                  rui_rx_serdes_rst_c;
+   input  [3:0]                  rui_rx_pcs_rst_c;
+   input  [3:0]                  rdi_rx_los_low_s;
+   input  [3:0]                  rdi_rx_cdr_lol_s;
+
+// ------------ output ports
+   output                        rdo_serdes_rst_dual_c;
+   output                        rdo_rst_dual_c;
+
+   output                        ruo_tx_rdy;
+   output                        rdo_tx_serdes_rst_c;
+   output [3:0]                  rdo_tx_pcs_rst_c;
+
+   output                        ruo_rx_rdy;
+   output [3:0]                  rdo_rx_serdes_rst_c;
+   output [3:0]                  rdo_rx_pcs_rst_c;
+
+// ------------ Internal registers and wires
+   // inputs
+   wire                          rui_rst;
+   wire                          rui_serdes_rst_dual_c;
+   wire                          rui_rst_dual_c;
+   wire                          rui_rsl_disable;
+   wire                          rui_tx_ref_clk;
+   wire                          rui_tx_serdes_rst_c;
+   wire   [3:0]                  rui_tx_pcs_rst_c;
+   wire                          rdi_pll_lol;
+   wire                          rui_rx_ref_clk;
+   wire   [3:0]                  rui_rx_serdes_rst_c;
+   wire   [3:0]                  rui_rx_pcs_rst_c;
+   wire   [3:0]                  rdi_rx_los_low_s;
+   wire   [3:0]                  rdi_rx_cdr_lol_s;
+
+   // outputs
+   wire                          rdo_serdes_rst_dual_c;
+   wire                          rdo_rst_dual_c;
+   wire                          ruo_tx_rdy;
+   wire                          rdo_tx_serdes_rst_c;
+   wire   [3:0]                  rdo_tx_pcs_rst_c;
+   wire                          ruo_rx_rdy;
+   wire   [3:0]                  rdo_rx_serdes_rst_c;
+   wire   [3:0]                  rdo_rx_pcs_rst_c;
+
+   // internal signals
+   // common
+   wire                          rsl_enable;
+   wire   [lplol_cnt_width-1:0]  wait_b4_trst;
+   wire   [lrlol_cnt_width-1:0]  wait_b4_rrst;
+   wire   [llols_cnt_width-1:0]  wait_after_lols;
+   reg                           pll_lol_p1;
+   reg                           pll_lol_p2;
+   reg                           pll_lol_p3;
+   // ------------ Tx
+   // rdo_tx_serdes_rst_c
+   reg    [lplol_cnt_width-1:0]  plol_cnt;
+   wire                          plol_cnt_tc;
+
+   reg    [2:0]                  txs_cnt;
+   reg                           txs_rst;
+   wire                          txs_cnt_tc;
+   // rdo_tx_pcs_rst_c
+   wire                          plol_fedge;
+   wire                          plol_redge;
+   reg                           waita_plol0;
+   reg    [2:0]                  plol0_cnt;
+   wire                          plol0_cnt_tc;
+   reg    [2:0]                  txp_cnt;
+   reg                           txp_rst;
+   wire                          txp_cnt_tc;
+   // ruo_tx_rdy
+   wire                          dual_or_serd_rst;
+   wire                          tx_any_pcs_rst;
+   wire                          tx_any_rst;
+   reg                           txsr_appd /* synthesis syn_keep=1 */;
+   reg                           txdpr_appd;
+   reg    [pnum_channels-1:0]    txpr_appd;
+   reg                           txr_wt_en;
+   reg    [ltxr_wait_width-1:0]  txr_wt_cnt;
+   wire                          txr_wt_tc;
+   reg                           ruo_tx_rdyr;
+
+   // ------------ Rx
+   wire                          comb_rlos;
+   wire                          comb_rlol;
+   //wire                          rlols;
+   wire                          rx_all_well;
+
+   //reg                           rlols_p1;
+   //reg                           rlols_p2;
+   //reg                           rlols_p3;
+
+   reg                           rlol_p1;
+   reg                           rlol_p2;
+   reg                           rlol_p3;
+   reg                           rlos_p1;
+   reg                           rlos_p2;
+   reg                           rlos_p3;
+
+   //reg    [3:0]                  rdb_cnt;
+   //wire                          rdb_cnt_max;
+   //wire                          rdb_cnt_zero;
+   //reg                           rlols_db;
+   //reg                           rlols_db_p1;
+
+   reg    [3:0]                  rlol_db_cnt;
+   wire                          rlol_db_cnt_max;
+   wire                          rlol_db_cnt_zero;
+   reg                           rlol_db;
+   reg                                  rlol_db_p1;
+
+   reg    [3:0]                  rlos_db_cnt;
+   wire                          rlos_db_cnt_max;
+   wire                          rlos_db_cnt_zero;
+   reg                           rlos_db;
+   reg                                  rlos_db_p1;
+
+   // rdo_rx_serdes_rst_c
+   reg    [lrlol_cnt_width-1:0]  rlol1_cnt;
+   wire                          rlol1_cnt_tc;
+   reg    [2:0]                  rxs_cnt;
+   reg                           rxs_rst;
+   wire                          rxs_cnt_tc;
+   reg    [lrrst_wait_width-1:0] rrst_cnt;
+   wire                          rrst_cnt_tc;
+   reg                           rrst_wait;
+   // rdo_rx_pcs_rst_c
+   //wire                          rlols_fedge;
+   //wire                          rlols_redge;
+   wire                          rlol_fedge;
+   wire                          rlol_redge;
+   wire                          rlos_fedge;
+   wire                          rlos_redge;
+
+   reg                           wait_calib;
+   reg                           waita_rlols0;
+   reg    [llols_cnt_width-1:0]  rlols0_cnt;
+   wire                          rlols0_cnt_tc;
+   reg    [2:0]                  rxp_cnt;
+   reg                           rxp_rst;
+   wire                          rxp_cnt_tc;
+
+   wire                          rx_any_serd_rst;
+   reg    [llols_cnt_width-1:0]  rlolsz_cnt;
+   wire                          rlolsz_cnt_tc;
+   reg [2:0]                    rxp_cnt2;
+   reg                           rxp_rst2;
+   wire                          rxp_cnt2_tc;
+   reg [15:0]                    data_loop_b_cnt;
+   reg                           data_loop_b;
+   wire                          data_loop_b_tc;
+
+   // ruo_rx_rdy
+   reg    [pnum_channels-1:0]    rxsr_appd;
+   reg    [pnum_channels-1:0]    rxpr_appd;
+   reg                           rxsdr_appd /* synthesis syn_keep=1 */;
+   reg                           rxdpr_appd;
+   wire                          rxsdr_or_sr_appd;
+   wire                          dual_or_rserd_rst;
+   wire                          rx_any_pcs_rst;
+   wire                          rx_any_rst;
+   reg                           rxr_wt_en;
+   reg    [lrxr_wait_width-1:0]  rxr_wt_cnt;
+   wire                          rxr_wt_tc;
+   reg                           ruo_rx_rdyr;
+
+// ==================================================================
+//                          Start of code
+// ==================================================================
+   assign rsl_enable = ~rui_rsl_disable;
+
+// ------------ rdo_serdes_rst_dual_c
+   assign rdo_serdes_rst_dual_c = (rui_rst&rsl_enable) | rui_serdes_rst_dual_c;
+
+// ------------ rdo_rst_dual_c
+   assign rdo_rst_dual_c = rui_rst_dual_c;
+
+// ------------ Setting counter values for RSL_SIM_MODE
+   `ifdef RSL_SIM_MODE
+      assign wait_b4_trst    = lwait_b4_trst_s;
+      assign wait_b4_rrst    = lwait_b4_rrst_s;
+      assign wait_after_lols = lwait_after_lols_s;
+   `else
+      assign wait_b4_trst    = lwait_b4_trst;
+      assign wait_b4_rrst    = lwait_b4_rrst;
+      assign wait_after_lols = lwait_after_lols;
+   `endif
+
+// ==================================================================
+//                                 Tx
+// ==================================================================
+   generate
+   if((pserdes_mode=="RX AND TX")||(pserdes_mode=="TX ONLY")) begin
+
+// ------------ Synchronizing pll_lol to the tx clock
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) begin
+         pll_lol_p1 <= 1'd0;
+         pll_lol_p2 <= 1'd0;
+         pll_lol_p3 <= 1'd0;
+      end
+      else begin
+         pll_lol_p1 <= rdi_pll_lol;
+         pll_lol_p2 <= pll_lol_p1;
+         pll_lol_p3 <= pll_lol_p2;
+      end
+   end
+
+// ------------ rdo_tx_serdes_rst_c
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         plol_cnt    <= 'd0;
+      else if((pll_lol_p2==0)||(plol_cnt_tc==1)||(rdo_tx_serdes_rst_c==1))
+         plol_cnt    <= 'd0;
+      else
+         plol_cnt    <= plol_cnt+1;
+   end
+   assign plol_cnt_tc = (plol_cnt==wait_b4_trst)?1'b1:1'b0;
+
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) begin
+         txs_cnt  <= 'd0;   // tx serdes reset pulse count
+         txs_rst  <= 1'b0;  // tx serdes reset
+      end
+      else if(plol_cnt_tc==1)
+         txs_rst  <= 1'b1;
+      else if(txs_cnt_tc==1) begin
+         txs_cnt  <= 'd0;
+         txs_rst  <= 1'b0;
+      end
+      else if(txs_rst==1)
+         txs_cnt  <= txs_cnt+1;
+   end
+   assign txs_cnt_tc = (txs_cnt==lreset_pwidth)?1'b1:1'b0;
+
+   assign rdo_tx_serdes_rst_c = (rsl_enable&txs_rst)| rui_tx_serdes_rst_c;
+
+// ------------ rdo_tx_pcs_rst_c
+   assign plol_fedge = ~pll_lol_p2 & pll_lol_p3;
+   assign plol_redge = pll_lol_p2 & ~pll_lol_p3;
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         waita_plol0  <= 1'd0;
+      else if(plol_fedge==1'b1)
+         waita_plol0  <= 1'b1;
+      else if((plol0_cnt_tc==1)||(plol_redge==1))
+         waita_plol0  <= 1'd0;
+   end
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         plol0_cnt    <= 'd0;
+      else if((pll_lol_p2==1)||(plol0_cnt_tc==1))
+         plol0_cnt    <= 'd0;
+      else if(waita_plol0==1'b1)
+         plol0_cnt    <= plol0_cnt+1;
+   end
+   assign plol0_cnt_tc = (plol0_cnt==lwait_after_plol0)?1'b1:1'b0;
+
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) begin
+         txp_cnt  <= 'd0;   // tx serdes reset pulse count
+         txp_rst  <= 1'b0;  // tx serdes reset
+      end
+      else if(plol0_cnt_tc==1)
+         txp_rst  <= 1'b1;
+      else if(txp_cnt_tc==1) begin
+         txp_cnt  <= 'd0;
+         txp_rst  <= 1'b0;
+      end
+      else if(txp_rst==1)
+         txp_cnt  <= txp_cnt+1;
+   end
+   assign txp_cnt_tc = (txp_cnt==lreset_pwidth)?1'b1:1'b0;
+
+   genvar i;
+   for(i=0;i<pnum_channels;i=i+1) begin : ifor
+      assign rdo_tx_pcs_rst_c[i] = (rsl_enable&txp_rst)| rui_tx_pcs_rst_c[i];
+   end
+   if(pnum_channels==1)
+      assign rdo_tx_pcs_rst_c[3:1] = 3'b000;
+   else if(pnum_channels==2)
+      assign rdo_tx_pcs_rst_c[3:2] = 2'b00;
+
+   // ------------ ruo_tx_rdy
+   if(pport_tx_rdy=="ENABLED") begin
+   assign dual_or_serd_rst = rdo_serdes_rst_dual_c|rdo_tx_serdes_rst_c;
+   assign tx_any_pcs_rst = rdo_rst_dual_c|(|rdo_tx_pcs_rst_c[pnum_channels-1:0]);
+   assign tx_any_rst = dual_or_serd_rst | tx_any_pcs_rst;
+
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         txsr_appd <= 1'b1; // tx serdes reset applied
+      else if(dual_or_serd_rst==1)
+         txsr_appd <= 1'b1;
+   end
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         txdpr_appd <= 1'b0; // tx dual (pcs) reset applied
+      else if(pll_lol_p2|rdo_serdes_rst_dual_c|rdo_tx_serdes_rst_c)
+         txdpr_appd <= 1'b0;
+      else if(rdo_rst_dual_c==1)
+         txdpr_appd <= 1'b1;
+   end
+
+   genvar m;
+   for(m=0;m<pnum_channels;m=m+1) begin :mfor
+      always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         txpr_appd[m] <= 1'b0; // tx pcs reset applied
+      else if(pll_lol_p2|rdo_serdes_rst_dual_c|rdo_tx_serdes_rst_c)
+         txpr_appd[m] <= 1'b0;
+      else if(txsr_appd&(rdo_tx_pcs_rst_c[m]|txdpr_appd))
+         txpr_appd[m] <= 1'b1;
+      end
+   end
+
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         txr_wt_en  <= 0;  // tx ready wait counter enable
+      else if((txr_wt_tc==1)||(dual_or_serd_rst==1))
+         txr_wt_en  <= 0;
+      else if((~ruo_tx_rdyr)&(~pll_lol_p2)&(&txpr_appd))
+         txr_wt_en  <= 1;
+   end
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         txr_wt_cnt  <= 'd0;  // tx ready wait count
+      else if((txr_wt_tc==1)||(tx_any_rst==1))
+         txr_wt_cnt  <= 'd0;
+      else if(txr_wt_en==1)
+         txr_wt_cnt  <= txr_wt_cnt+1;
+   end
+   assign txr_wt_tc = (txr_wt_cnt==pwait_tx_rdy)?1'b1:1'b0;
+
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         ruo_tx_rdyr <= 1'b0; // tx serdes reset applied
+      else if((tx_any_rst==1)||(pll_lol_p2==1))
+         ruo_tx_rdyr <= 1'b0;
+      else if(txr_wt_tc==1)
+         ruo_tx_rdyr <= 1'b1;
+   end
+   assign ruo_tx_rdy = ruo_tx_rdyr;
+   end         // if pport_tx_rdy
+   else
+      assign ruo_tx_rdy = 1'b0;
+   end         // generate if(Rx and Tx) or (Tx only)
+   else begin  // generate else (Rx only)
+      assign rdo_tx_serdes_rst_c = 1'b0;
+      assign rdo_tx_pcs_rst_c = 4'd0;
+      assign ruo_tx_rdy = 1'b0;
+   end
+   endgenerate
+
+// ==================================================================
+//                                 Rx
+// ==================================================================
+   generate
+   if((pserdes_mode=="RX AND TX")||(pserdes_mode=="RX ONLY")) begin
+   assign comb_rlos = |rdi_rx_los_low_s[pnum_channels-1:0];
+   assign comb_rlol = |rdi_rx_cdr_lol_s[pnum_channels-1:0];
+   //assign rlols     = comb_rlos|comb_rlol;
+
+   // ------------ Synchronizing rlols to the rx ref clock
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) begin
+        //rlols_p1    <= 1'd0;
+        //rlols_p2    <= 1'd0;
+        //rlols_p3    <= 1'd0;
+        //rlols_db_p1 <= 1'd1;
+
+        rlol_p1     <= 1'd0;
+        rlol_p2     <= 1'd0;
+        rlol_p3     <= 1'd0;
+        rlol_db_p1  <= 1'd1;
+
+        rlos_p1    <= 1'd0;
+        rlos_p2    <= 1'd0;
+        rlos_p3    <= 1'd0;
+        rlos_db_p1 <= 1'd1;
+      end
+      else begin
+        //rlols_p1    <= rlols;
+        //rlols_p2    <= rlols_p1;
+        //rlols_p3    <= rlols_p2;
+        //rlols_db_p1 <= rlols_db;
+
+        rlol_p1     <= comb_rlol;
+        rlol_p2     <= rlol_p1;
+        rlol_p3     <= rlol_p2;
+       rlol_db_p1  <= rlol_db;
+
+        rlos_p1    <= comb_rlos;
+        rlos_p2    <= rlos_p1;
+        rlos_p3    <= rlos_p2;
+        rlos_db_p1 <= rlos_db;
+      end
+   end
+   assign rx_all_well = ~rlol_db && ~rlos_db;
+
+//******************************************************************************
+// [ES:05.03.17] Unused registers for clean-up
+//------------------------------------------------------------------------------
+// ------------ Debouncing rlols
+//   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+//      if(rui_rst==1'b1) rdb_cnt  <= lrdb_max;
+//      else if(rlols_p2==1) begin
+//         if(!rdb_cnt_max) rdb_cnt <= rdb_cnt+1;
+//      end
+//      else if(!rdb_cnt_zero) rdb_cnt <= rdb_cnt-1;
+//   end
+//   assign rdb_cnt_max  = (rdb_cnt==lrdb_max);
+//   assign rdb_cnt_zero = (rdb_cnt==0);
+//   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+//      if(rui_rst==1'b1) rlols_db <= 1;
+//      else if(rdb_cnt_max)  rlols_db <= 1;
+//      else if(rdb_cnt_zero) rlols_db <= 0;
+//   end
+//******************************************************************************
+
+// ------------ Debouncing rlol
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) rlol_db_cnt  <= lrdb_max;
+      else if(rlol_p2==1) begin
+         if(!rlol_db_cnt_max) rlol_db_cnt <= rlol_db_cnt+1;
+      end
+      else if(!rlol_db_cnt_zero) rlol_db_cnt <= rlol_db_cnt-1;
+   end
+   assign rlol_db_cnt_max  = (rlol_db_cnt==lrdb_max);
+   assign rlol_db_cnt_zero = (rlol_db_cnt==0);
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) rlol_db <= 1;
+      else if(rlol_db_cnt_max)  rlol_db <= 1;
+      else if(rlol_db_cnt_zero) rlol_db <= 0;
+   end
+
+// ------------ Debouncing rlos
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) rlos_db_cnt  <= lrdb_max;
+      else if(rlos_p2==1) begin
+         if(!rlos_db_cnt_max) rlos_db_cnt <= rlos_db_cnt+1;
+      end
+      else if(!rlos_db_cnt_zero) rlos_db_cnt <= rlos_db_cnt-1;
+   end
+   assign rlos_db_cnt_max  = (rlos_db_cnt==lrdb_max);
+   assign rlos_db_cnt_zero = (rlos_db_cnt==0);
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) rlos_db <= 1;
+      else if(rlos_db_cnt_max)  rlos_db <= 1;
+      else if(rlos_db_cnt_zero) rlos_db <= 0;
+   end
+
+// ------------ Calib time trigger
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+     if (rui_rst==1'b1) begin
+       wait_calib <= 1'd1;
+     end
+     else begin
+       if (rlol1_cnt_tc) begin
+         if (rlol_db)
+           wait_calib <= 1'd1;
+         else
+           wait_calib <= 1'd0;
+       end
+       else if (rlos_redge)
+         wait_calib <= 1'd0;
+       else if (rlos_fedge) begin
+         wait_calib <= 1'd1;
+       end
+     end
+   end
+
+   //***************************************************************************
+   // Total calibration time counter
+   // - this covers the band calibration time (256 cycles * 64) and
+   //   DAC calibration time (16384 cycles * 10 bits)
+   //---------------------------------------------------------------------------
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+     if (rui_rst==1'b1) begin
+       rlol1_cnt  <= 'd0;  // Counting when Rx LOL is 1 and Rx LOS is 0
+     end
+     else begin
+       if(rxs_rst || rlol1_cnt_tc || rlos_redge)
+         rlol1_cnt  <= 'd0;
+       else if (wait_calib)
+         rlol1_cnt <= rlol1_cnt+1;
+     end
+   end
+   assign rlol1_cnt_tc = (rlol1_cnt==wait_b4_rrst);
+
+// ------------ rdo_rx_serdes_rst_c
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+     if (rui_rst==1'b1) begin
+       rxs_cnt  <= 'd0;   // rx serdes reset pulse count
+       rxs_rst  <= 1'b0;  // rx serdes reset
+     end
+     else begin
+       if (rlos_db)
+         rxs_rst <= 1'b0;
+       else if (rlol1_cnt_tc && rlol_db)
+         rxs_rst <= 1'b1;
+       else if (rxs_cnt_tc==1) begin
+         rxs_rst  <= 1'b0;
+       end
+
+       if (rxs_cnt_tc)
+         rxs_cnt <= 'd0;
+       else
+         if (rxs_rst==1)
+           rxs_cnt <= rxs_cnt+1;
+     end
+   end
+   assign rxs_cnt_tc  = (rxs_cnt==lreset_pwidth)?1'b1:1'b0;
+
+   //***************************************************************************
+   // [ES:05.03.17] Unused logic from CPRI rrst_wait
+   //---------------------------------------------------------------------------
+   // always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+   //    if(rui_rst==1'b1)
+   //       rrst_cnt    <= 'd0;
+   //    else if(rlol1_cnt_tc)
+   //       rrst_cnt    <= 'd0;
+   //    else if(rrst_wait)
+   //       rrst_cnt    <= rrst_cnt+1;
+   // end
+   // assign rrst_cnt_tc = (rrst_cnt==lwait_after_rrst) ? 1'b1 : 1'b0;
+   // always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+   //    if(rui_rst==1'b1)
+   //       rrst_wait    <= 0;
+   //    else if(pprotocol != "CPRI")
+   //       rrst_wait    <= 0;
+   //    else if(rlol1_cnt_tc)
+   //       rrst_wait    <= 1;
+   //    else if(rrst_cnt_tc==1)
+   //       rrst_wait    <= 0;
+   // end
+   //***************************************************************************
+
+   genvar j;
+   for(j=0;j<pnum_channels;j=j+1) begin :jfor
+      assign rdo_rx_serdes_rst_c[j] = (rsl_enable&rxs_rst)| rui_rx_serdes_rst_c[j];
+   end
+   if(pnum_channels==1)
+      assign rdo_rx_serdes_rst_c[3:1] = 3'b000;
+   else if(pnum_channels==2)
+      assign rdo_rx_serdes_rst_c[3:2] = 2'b00;
+
+// ------------ rdo_rx_pcs_rst_c
+   //assign rlols_fedge = ~rlols_db & rlols_db_p1;
+   //assign rlols_redge = rlols_db & ~rlols_db_p1;
+
+   assign rlol_fedge  = ~rlol_db & rlol_db_p1;
+   assign rlol_redge  = rlol_db & ~rlol_db_p1;
+   assign rlos_fedge  = ~rlos_db & rlos_db_p1;
+   assign rlos_redge  = rlos_db & ~rlos_db_p1;
+
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if (rui_rst==1'b1) begin
+        waita_rlols0 <= 1'd0;
+      end
+      else begin
+        if ((rlos_fedge && ~rlol_db) || (rlol_fedge && ~rlos_db))
+          waita_rlols0 <= 1'b1;
+        else if (rlos_redge || rlol_redge)
+          waita_rlols0 <= 1'd0;
+        else if (rlols0_cnt_tc==1)
+          waita_rlols0 <= 1'd0;
+      end
+   end
+
+   //***************************************************************************
+   // Post RLOL check before pcs_rst deassertion
+   // - allowance of 2-4 DAC calibration cycles + 1024 cycles for WA module
+   //   (word alignment).
+   //---------------------------------------------------------------------------
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+     if (rui_rst==1'b1) begin
+       rlols0_cnt <= 'd0;
+     end
+     else begin
+       if (rlol_redge || rlos_redge || rlols0_cnt_tc)
+         rlols0_cnt <= 'd0;
+       else if (waita_rlols0==1)
+         rlols0_cnt <= rlols0_cnt+1;
+     end
+   end
+   assign rlols0_cnt_tc   = (rlols0_cnt == wait_after_lols);
+   assign rx_any_serd_rst = rdo_serdes_rst_dual_c|(|rdo_rx_serdes_rst_c);
+
+   //***************************************************************************
+   // [ES:05.03.17] Unused registers for clean-up
+   //---------------------------------------------------------------------------
+   // always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+   //    if(rui_rst==1'b1)
+   //       rlolsz_cnt  <= 'd0;  // Counting when both Rx LOL is 0 and Rx LOS is 0
+   //    else if((rlol_db|rx_any_serd_rst)||(rlolsz_cnt_tc==1))
+   //       rlolsz_cnt  <= 'd0;
+   //    else if((rlolsz_cnt_tc==0)&&(rlol_db==0))
+   //       rlolsz_cnt  <= rlolsz_cnt+1;
+   // end
+   // assign rlolsz_cnt_tc = (rlolsz_cnt==wait_after_lols);
+   //***************************************************************************
+
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+     if (rui_rst==1'b1) begin
+       rxp_cnt2  <= 'd0;   // pcs serdes reset pulse count
+       rxp_rst2  <= 1'b1;  // rx pcs reset
+     end
+     else begin
+       if (rx_any_serd_rst || rlos_redge) begin
+         rxp_rst2 <= 1'b1;
+       end
+       else if (rlols0_cnt_tc) begin
+         rxp_rst2 <= 1'b0;
+       end
+       //***********************************************************************
+       // [ES:05.03.17] No need for pulse width
+       //-----------------------------------------------------------------------
+       // else if(rxp_cnt2_tc==1) begin
+       //   rxp_cnt2  <= 'd0;
+       //   rxp_rst2  <= 1'b0;
+       // end
+       //***********************************************************************
+       // [ES:05.03.17] No need for pulse width
+       //-----------------------------------------------------------------------
+       // else if (rxp_rst2==1)
+       //   rxp_cnt2 <= rxp_cnt2+1;
+       //***********************************************************************
+     end // else: !if(rui_rst==1'b1)
+   end // always @ (posedge rui_rx_ref_clk or posedge rui_rst)
+   //assign rxp_cnt2_tc = (rxp_cnt2==lreset_pwidth)?1'b1:1'b0;
+
+   //***************************************************************************
+   // [ES:05.03.17] No need for pulse width
+   //---------------------------------------------------------------------------
+   //else begin
+   //   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+   //      if(rui_rst==1'b1)
+   //         rxp_rst2  <= 1'b1;  // rx pcs reset
+   //      else if(rx_any_serd_rst)
+   //         rxp_rst2  <= 1'b1;
+   //      else if(rlolsz_cnt_tc==1)
+   //         rxp_rst2  <= 1'b0;
+   //   end
+   //end
+   //***************************************************************************
+
+   genvar k;
+   for(k=0;k<pnum_channels;k=k+1) begin: kfor
+      assign rdo_rx_pcs_rst_c[k] = (rsl_enable&rxp_rst2)| rui_rx_pcs_rst_c[k];
+   end
+   if(pnum_channels==1)
+      assign rdo_rx_pcs_rst_c[3:1] = 3'b000;
+   else if(pnum_channels==2)
+      assign rdo_rx_pcs_rst_c[3:2] = 2'b00;
+
+// ------------ ruo_rx_rdy
+   if(pport_rx_rdy=="ENABLED") begin
+   assign dual_or_rserd_rst = rdo_serdes_rst_dual_c|(|rdo_rx_serdes_rst_c[pnum_channels-1:0]);
+   assign rx_any_pcs_rst = rdo_rst_dual_c|(|rdo_rx_pcs_rst_c[pnum_channels-1:0]);
+   assign rx_any_rst = dual_or_rserd_rst | rx_any_pcs_rst;
+
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         rxsdr_appd <= 1'b1;  // Serdes dual reset (macro reset) applied
+      else if(rdo_serdes_rst_dual_c==1)
+         rxsdr_appd <= 1'b1;
+   end
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         rxdpr_appd <= 1'b0;  // Rx dual PCS reset (dual reset) applied
+      else if(~rx_all_well|dual_or_rserd_rst)
+         rxdpr_appd <= 1'b0;
+      else if(rdo_rst_dual_c==1)
+         rxdpr_appd <= 1'b1;
+   end
+
+   genvar l;
+   for(l=0;l<pnum_channels;l=l+1) begin : lfor
+      always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+         if(rui_rst==1'b1)
+            rxsr_appd[l] <= 1'b0; // rx serdes reset applied
+         else if(rdo_rx_serdes_rst_c[l]==1)
+            rxsr_appd[l] <= 1'b1;
+      end
+      always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         rxpr_appd[l] <= 1'b0; // rx pcs reset applied
+      else if(rdi_rx_los_low_s[l]|rdi_rx_cdr_lol_s[l]|rdo_serdes_rst_dual_c|rdo_rx_serdes_rst_c[l])
+         rxpr_appd[l] <= 1'b0;
+      else if(rxsdr_or_sr_appd&(~rx_all_well)&rdo_rx_pcs_rst_c[l])
+         rxpr_appd[l] <= 1'b1;
+      end
+   end
+
+   assign rxsdr_or_sr_appd = rxsdr_appd|(&rxsr_appd);
+
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         rxr_wt_en  <= 0;  // rx ready wait counter enable
+      //else if((rxr_wt_tc==1)||(dual_or_rserd_rst==1))
+      else if((rxr_wt_tc==1)||(dual_or_rserd_rst==1)||(rx_all_well==0)) // BM, 2/4/16
+         rxr_wt_en  <= 0;
+      else if(~ruo_rx_rdyr&rx_all_well&((&rxpr_appd)|rxdpr_appd))
+         rxr_wt_en  <= 1;
+   end
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         rxr_wt_cnt  <= 'd0;  // rx ready wait count
+      //else if((rxr_wt_tc==1)||(rx_any_rst==1))
+      else if((rxr_wt_tc==1)||(rx_any_rst==1)||(rx_all_well==0)) // BM, 2/4/16
+         rxr_wt_cnt  <= 'd0;
+      else if(rxr_wt_en==1)
+         rxr_wt_cnt  <= rxr_wt_cnt+1;
+   end
+   assign rxr_wt_tc = (rxr_wt_cnt==pwait_rx_rdy)?1'b1:1'b0;
+
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         ruo_rx_rdyr <= 1'b0; // rx serdes reset applied
+      else if((rx_any_rst==1)||(rx_all_well==0))
+         ruo_rx_rdyr <= 1'b0;
+      else if(rxr_wt_tc==1)
+         ruo_rx_rdyr <= 1'b1;
+   end
+   assign ruo_rx_rdy = ruo_rx_rdyr;
+   end         // if pport_rx_rdy
+   else
+      assign ruo_rx_rdy = 1'b0;
+   end // if ((pserdes_mode=="RX AND TX")||(pserdes_mode=="RX ONLY"))
+
+   else begin  // generate else (Tx only)
+      assign rdo_rx_serdes_rst_c = 4'd0;
+      assign rdo_rx_pcs_rst_c = 4'd0;
+      assign ruo_rx_rdy = 1'b0;
+   end // else: !if((pserdes_mode=="RX AND TX")||(pserdes_mode=="RX ONLY"))
+
+   endgenerate
+
+endmodule
+
+
+//   ===========================================================================
+//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
+//   ---------------------------------------------------------------------------
+//   Copyright (c) 2015 by Lattice Semiconductor Corporation
+//   ALL RIGHTS RESERVED 
+//   ------------------------------------------------------------------
+//
+//   Permission:
+//
+//      Lattice SG Pte. Ltd. grants permission to use this code
+//      pursuant to the terms of the Lattice Reference Design License Agreement. 
+//
+//
+//   Disclaimer:
+//
+//      This VHDL or Verilog source code is intended as a design reference
+//      which illustrates how these types of functions can be implemented.
+//      It is the user's responsibility to verify their design for
+//      consistency and functionality through the use of formal
+//      verification methods.  Lattice provides no warranty
+//      regarding the use or functionality of this code.
+//
+//   ---------------------------------------------------------------------------
+//
+//                  Lattice SG Pte. Ltd.
+//                  101 Thomson Road, United Square #07-02 
+//                  Singapore 307591
+//
+//
+//                  TEL: 1-800-Lattice (USA and Canada)
+//                       +65-6631-2000 (Singapore)
+//                       +1-503-268-8001 (other locations)
+//
+//                  web: http://www.latticesemi.com/
+//                  email: techsupport@latticesemi.com
+//
+//   ---------------------------------------------------------------------------
+//
+// =============================================================================
+//                         FILE DETAILS         
+// Project               : SLL - Soft Loss Of Lock(LOL) Logic
+// File                  : sll_core.v
+// Title                 : Top-level file for SLL 
+// Dependencies          : 1.
+//                       : 2.
+// Description           : 
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.0
+// Author(s)             : AV
+// Mod. Date             : March 2, 2015
+// Changes Made          : Initial Creation
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.1
+// Author(s)             : AV
+// Mod. Date             : June 8, 2015
+// Changes Made          : Following updates were made 
+//                       : 1. Changed all the PLOL status logic and FSM to run
+//                       :    on sli_refclk. 
+//                       : 2. Added the HB logic for presence of tx_pclk 
+//                       : 3. Changed the lparam assignment scheme for 
+//                       :    simulation purposes. 
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.2
+// Author(s)             : AV
+// Mod. Date             : June 24, 2015
+// Changes Made          : Updated the gearing logic for SDI dynamic rate change
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.3
+// Author(s)             : AV
+// Mod. Date             : July 14, 2015
+// Changes Made          : Added the logic for dynamic rate change in CPRI
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.4
+// Author(s)             : AV
+// Mod. Date             : August 21, 2015
+// Changes Made          : Added the logic for dynamic rate change of 5G CPRI & 
+//                         PCIe.
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.5
+// Author(s)             : ES/EB
+// Mod. Date             : March 21, 2017
+// Changes Made          : 1. Added pdiff_sync signal to syncrhonize pcount_diff 
+//                       :    to sli_refclk.
+//                       : 2. Updated terminal count logic for PCIe 5G
+//                       : 3. Modified checking of pcount_diff in SLL state
+//                       :    machine to cover actual count
+//                       :    (from 16-bits to 22-bits)
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.6
+// Author(s)             : ES
+// Mod. Date             : April 19, 2017
+// Changes Made          : 1. Added registered lock and unlock signal from
+//                            pdiff_sync to totally decouple pcount_diff from
+//                            SLL state machine.
+//                       : 2. Modified LPCLK_TC_4 to 1:1 clock ratio when CPRI
+//                            is operating @ 4.9125Gbps data rate.
+// =============================================================================
+`timescale 1ns/10ps
+
+module sgmii_ecp5sll_core ( 
+  //Reset and Clock inputs
+  sli_rst,         //Active high asynchronous reset input
+  sli_refclk,      //Refclk input to the Tx PLL
+  sli_pclk,        //Tx pclk output from the PCS
+  
+  //Control inputs
+  sli_div2_rate,   //Divide by 2 control; 0 - Full rate; 1 - Half rate
+  sli_div11_rate,  //Divide by 11 control; 0 - Full rate; 1 - Div by 11
+  sli_gear_mode,   //Gear mode control for PCS; 0 - 8/10; 1- 16/20
+  sli_cpri_mode,   //Mode of operation specific to CPRI protocol
+  sli_pcie_mode,   //Mode of operation specific to PCIe mode (2.5G or 5G)
+  
+  //LOL Output
+  slo_plol         //Tx PLL Loss of Lock output to the user logic
+  );
+  
+// Inputs
+input       sli_rst;
+input       sli_refclk;
+input       sli_pclk;
+input       sli_div2_rate;
+input       sli_div11_rate;
+input       sli_gear_mode;
+input [2:0] sli_cpri_mode;
+input       sli_pcie_mode;
+
+// Outputs
+output      slo_plol;
+
+
+// Parameters
+parameter PPROTOCOL              = "PCIE";     //Protocol selected by the User
+parameter PLOL_SETTING           = 0;          //PLL LOL setting. Possible values are 0,1,2,3
+parameter PDYN_RATE_CTRL         = "DISABLED"; //PCS Dynamic Rate control
+parameter PPCIE_MAX_RATE         = "2.5";      //PCIe max data rate
+parameter PDIFF_VAL_LOCK         = 20;         //Differential count value for Lock
+parameter PDIFF_VAL_UNLOCK       = 39;         //Differential count value for Unlock
+parameter PPCLK_TC               = 65535;      //Terminal count value for counter running on sli_pclk
+parameter PDIFF_DIV11_VAL_LOCK   = 3;          //Differential count value for Lock for SDI Div11
+parameter PDIFF_DIV11_VAL_UNLOCK = 3;          //Differential count value for Unlock for SDI Div11
+parameter PPCLK_DIV11_TC         = 2383;       //Terminal count value (SDI Div11) for counter running on sli_pclk
+
+
+// Local Parameters
+localparam [1:0]  LPLL_LOSS_ST         = 2'b00;       //PLL Loss state
+localparam [1:0]  LPLL_PRELOSS_ST      = 2'b01;       //PLL Pre-Loss state
+localparam [1:0]  LPLL_PRELOCK_ST      = 2'b10;       //PLL Pre-Lock state
+localparam [1:0]  LPLL_LOCK_ST         = 2'b11;       //PLL Lock state
+`ifdef RSL_SIM_MODE
+localparam [15:0] LRCLK_TC             = 16'd63;   //Terminal count value for counter running on sli_refclk
+`else
+localparam [15:0] LRCLK_TC             = 16'd65535;   //Terminal count value for counter running on sli_refclk
+`endif
+localparam [15:0] LRCLK_TC_PUL_WIDTH   = 16'd50;      //Pulse width for the Refclk terminal count pulse
+localparam [7:0]  LHB_WAIT_CNT         = 8'd255;      //Wait count for the Heartbeat signal
+
+// Local Parameters related to the CPRI dynamic modes
+// Terminal count values for the four CPRI modes
+localparam LPCLK_TC_0 = 32768;
+localparam LPCLK_TC_1 = 65536;
+localparam LPCLK_TC_2 = 131072;
+localparam LPCLK_TC_3 = 163840;
+localparam LPCLK_TC_4 = 65536;
+
+// Lock values count values for the four CPRI modes and four PLOL settings (4x5)
+// CPRI rate mode 0                CPRI rate mode 1                   CPRI rate mode 2                    CPRI rate mode 3                     CPRI rate mode 4
+localparam LPDIFF_LOCK_00 = 9;     localparam LPDIFF_LOCK_10 = 19;    localparam LPDIFF_LOCK_20 = 39;     localparam LPDIFF_LOCK_30 = 49;      localparam LPDIFF_LOCK_40 = 19;
+localparam LPDIFF_LOCK_01 = 9;     localparam LPDIFF_LOCK_11 = 19;    localparam LPDIFF_LOCK_21 = 39;     localparam LPDIFF_LOCK_31 = 49;      localparam LPDIFF_LOCK_41 = 19;
+localparam LPDIFF_LOCK_02 = 49;    localparam LPDIFF_LOCK_12 = 98;    localparam LPDIFF_LOCK_22 = 196;    localparam LPDIFF_LOCK_32 = 245;     localparam LPDIFF_LOCK_42 = 98;
+localparam LPDIFF_LOCK_03 = 131;   localparam LPDIFF_LOCK_13 = 262;   localparam LPDIFF_LOCK_23 = 524;    localparam LPDIFF_LOCK_33 = 655;     localparam LPDIFF_LOCK_43 = 262;
+
+// Unlock values count values for the four CPRI modes and four PLOL settings (4x5)
+// CPRI rate mode 0                  CPRI rate mode 1                      CPRI rate mode 2                       CPRI rate mode 3                         CPRI rate mode 4
+localparam LPDIFF_UNLOCK_00 = 19;    localparam LPDIFF_UNLOCK_10 = 39;     localparam LPDIFF_UNLOCK_20 = 78;      localparam LPDIFF_UNLOCK_30 = 98;        localparam LPDIFF_UNLOCK_40 = 39;
+localparam LPDIFF_UNLOCK_01 = 65;    localparam LPDIFF_UNLOCK_11 = 131;    localparam LPDIFF_UNLOCK_21 = 262;     localparam LPDIFF_UNLOCK_31 = 327;       localparam LPDIFF_UNLOCK_41 = 131;
+localparam LPDIFF_UNLOCK_02 = 72;    localparam LPDIFF_UNLOCK_12 = 144;    localparam LPDIFF_UNLOCK_22 = 288;     localparam LPDIFF_UNLOCK_32 = 360;       localparam LPDIFF_UNLOCK_42 = 144;
+localparam LPDIFF_UNLOCK_03 = 196;   localparam LPDIFF_UNLOCK_13 = 393;    localparam LPDIFF_UNLOCK_23 = 786;     localparam LPDIFF_UNLOCK_33 = 983;       localparam LPDIFF_UNLOCK_43 = 393;
+
+// Input and Output reg and wire declarations
+wire       sli_rst;
+wire       sli_refclk;
+wire       sli_pclk;
+wire       sli_div2_rate;
+wire       sli_div11_rate;
+wire       sli_gear_mode;
+wire [2:0] sli_cpri_mode;
+wire       sli_pcie_mode;
+wire       slo_plol;
+
+//-------------- Internal signals reg and wire declarations --------------------
+
+//Signals running on sli_refclk
+reg  [15:0] rcount;           //16-bit Counter
+reg         rtc_pul;          //Terminal count pulse
+reg         rtc_pul_p1;       //Terminal count pulse pipeline
+reg         rtc_ctrl;         //Terminal count pulse control
+
+reg  [7:0]  rhb_wait_cnt;     //Heartbeat wait counter
+
+//Heatbeat synchronization and pipeline registers
+wire        rhb_sync;
+reg         rhb_sync_p2;
+reg         rhb_sync_p1;
+
+//Pipeling registers for dynamic control mode
+wire        rgear;
+wire        rdiv2;
+wire        rdiv11;
+reg         rgear_p1;
+reg         rdiv2_p1;
+reg         rdiv11_p1;
+
+reg         rstat_pclk;        //Pclk presence/absence status
+
+reg  [21:0] rcount_tc;         //Tx_pclk terminal count register
+reg  [15:0] rdiff_comp_lock;   //Differential comparison value for Lock
+reg  [15:0] rdiff_comp_unlock; //Differential compariosn value for Unlock
+
+wire        rpcie_mode;        //PCIe mode signal synchronized to refclk
+reg         rpcie_mode_p1;     //PCIe mode pipeline register
+
+wire        rcpri_mod_ch_sync; //CPRI mode change synchronized to refclk
+reg         rcpri_mod_ch_p1;   //CPRI mode change pipeline register
+reg         rcpri_mod_ch_p2;   //CPRI mode change pipeline register
+reg         rcpri_mod_ch_st;   //CPRI mode change status
+
+reg  [1:0]  sll_state;         //Current-state register for LOL FSM
+
+reg         pll_lock;          //PLL Lock signal
+
+//Signals running on sli_pclk
+//Synchronization and pipeline registers
+wire        ppul_sync;
+reg         ppul_sync_p1;
+reg         ppul_sync_p2;
+reg         ppul_sync_p3;
+
+wire        pdiff_sync;
+reg         pdiff_sync_p1;
+   
+reg  [21:0] pcount;            //22-bit counter
+reg  [21:0] pcount_diff;       //Differential value between Tx_pclk counter and theoritical value
+
+//Heartbeat counter and heartbeat signal running on pclk
+reg  [2:0]  phb_cnt;
+reg         phb;
+
+//CPRI dynamic mode releated signals
+reg  [2:0]  pcpri_mode;
+reg         pcpri_mod_ch;
+
+//Assignment scheme changed mainly for simulation purpose
+wire [15:0] LRCLK_TC_w;
+assign LRCLK_TC_w = LRCLK_TC;
+
+reg         unlock;
+reg         lock;
+
+//Heartbeat synchronization
+sync # (.PDATA_RST_VAL(0)) phb_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (phb),
+  .data_out(rhb_sync)
+  );
+  
+  
+//Terminal count pulse synchronization
+sync # (.PDATA_RST_VAL(0)) rtc_sync_inst ( 
+  .clk     (sli_pclk),
+  .rst     (sli_rst),
+  .data_in (rtc_pul),
+  .data_out(ppul_sync)
+  );
+
+//Differential value logic update synchronization
+sync # (.PDATA_RST_VAL(0)) pdiff_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (ppul_sync),
+  .data_out(pdiff_sync)
+  );
+
+//Gear mode synchronization
+sync # (.PDATA_RST_VAL(0)) gear_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (sli_gear_mode),
+  .data_out(rgear)
+  );
+  
+//Div2 synchronization
+sync # (.PDATA_RST_VAL(0)) div2_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (sli_div2_rate),
+  .data_out(rdiv2)
+  );
+  
+//Div11 synchronization
+sync # (.PDATA_RST_VAL(0)) div11_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (sli_div11_rate),
+  .data_out(rdiv11)
+  );
+  
+//CPRI mode change synchronization
+sync # (.PDATA_RST_VAL(0)) cpri_mod_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (pcpri_mod_ch),
+  .data_out(rcpri_mod_ch_sync)
+  );
+  
+//PCIe mode change synchronization
+sync # (.PDATA_RST_VAL(0)) pcie_mod_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (sli_pcie_mode),
+  .data_out(rpcie_mode)
+  );  
+
+// =============================================================================
+// Synchronized Lock/Unlock signals
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    unlock        <= 1'b0;
+    lock          <= 1'b0;
+    pdiff_sync_p1 <= 1'b0;
+  end
+  else begin
+    pdiff_sync_p1 <= pdiff_sync;
+    if (unlock) begin
+      unlock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : unlock;
+    end
+    else begin
+      unlock <= pdiff_sync ? (pcount_diff[21:0] > {6'd0, rdiff_comp_unlock}) : 1'b0;
+    end
+    if (lock) begin
+      lock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : lock;
+    end
+    else begin
+      lock <= pdiff_sync ? (pcount_diff[21:0] <= {6'd0, rdiff_comp_lock}) : 1'b0;
+    end
+  end
+end
+
+// =============================================================================
+// Refclk Counter, pulse generation logic and Heartbeat monitor logic
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rcount     <= 16'd0;
+    rtc_pul    <= 1'b0;
+    rtc_ctrl   <= 1'b0;
+    rtc_pul_p1 <= 1'b0;
+  end
+  else begin
+    //Counter logic
+    if ((rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin
+      if (rtc_ctrl == 1'b1) begin
+        rcount <= LRCLK_TC_PUL_WIDTH;
+      end  
+    end
+    else begin
+      if (rcount != LRCLK_TC_w) begin
+        rcount <= rcount + 1;
+      end
+      else begin
+        rcount <= 16'd0;   
+      end
+    end
+    
+    //Pulse control logic
+    if (rcount == LRCLK_TC_w - 1) begin
+      rtc_ctrl <= 1'b1;
+    end
+    
+    //Pulse Generation logic
+    if (rtc_ctrl == 1'b1) begin
+      if ((rcount == LRCLK_TC_w) || (rcount < LRCLK_TC_PUL_WIDTH)) begin
+        rtc_pul <= 1'b1;
+    end  
+      else begin
+        rtc_pul <= 1'b0;  
+      end
+    end
+    
+    rtc_pul_p1 <= rtc_pul;  
+  end  
+end
+
+
+// =============================================================================
+// Heartbeat synchronization & monitor logic and Dynamic mode pipeline logic 
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rhb_sync_p1     <= 1'b0;
+    rhb_sync_p2     <= 1'b0;
+    rhb_wait_cnt    <= 8'd0;
+    rstat_pclk      <= 1'b0;
+    rgear_p1        <= 1'b0;
+    rdiv2_p1        <= 1'b0;
+    rdiv11_p1       <= 1'b0;
+    rcpri_mod_ch_p1 <= 1'b0;
+    rcpri_mod_ch_p2 <= 1'b0;
+    rcpri_mod_ch_st <= 1'b0;
+    rpcie_mode_p1   <= 1'b0;
+    
+  end
+  else begin
+    //Pipeline stages for the Heartbeat
+    rhb_sync_p1 <= rhb_sync;
+    rhb_sync_p2 <= rhb_sync_p1;
+    
+    //Pipeline stages of the Dynamic rate control signals
+    rgear_p1  <= rgear;
+    rdiv2_p1  <= rdiv2;
+    rdiv11_p1 <= rdiv11;
+    
+    //Pipeline stage for PCIe mode
+    rpcie_mode_p1 <= rpcie_mode;
+    
+    //Pipeline stage for CPRI mode change
+    rcpri_mod_ch_p1 <= rcpri_mod_ch_sync;
+    rcpri_mod_ch_p2 <= rcpri_mod_ch_p1;
+    
+    //CPRI mode change status logic
+    if (rcpri_mod_ch_p1^rcpri_mod_ch_sync == 1'b1) begin
+      rcpri_mod_ch_st <= 1'b1;
+    end 
+    
+    //Heartbeat wait counter and monitor logic
+    if (rtc_ctrl == 1'b1) begin
+      if (rhb_sync_p1 == 1'b1 && rhb_sync_p2 == 1'b0) begin
+        rhb_wait_cnt <= 8'd0;
+        rstat_pclk   <= 1'b1;
+      end
+      else if (rhb_wait_cnt == LHB_WAIT_CNT) begin
+        rhb_wait_cnt <= 8'd0;
+        rstat_pclk   <= 1'b0;
+      end
+      else begin
+        rhb_wait_cnt <= rhb_wait_cnt + 1;
+      end
+    end
+  end  
+end
+
+
+// =============================================================================
+// Pipleline registers for the TC pulse and CPRI mode change logic
+// =============================================================================
+always @(posedge sli_pclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    ppul_sync_p1 <= 1'b0;
+    ppul_sync_p2 <= 1'b0;
+    ppul_sync_p3 <= 1'b0;
+    pcpri_mode   <= 3'b0;
+    pcpri_mod_ch <= 1'b0;
+  end
+  else begin
+    ppul_sync_p1 <= ppul_sync;
+    ppul_sync_p2 <= ppul_sync_p1;
+    ppul_sync_p3 <= ppul_sync_p2;
+    
+    //CPRI mode change logic
+    pcpri_mode <= sli_cpri_mode;
+    
+    if (pcpri_mode != sli_cpri_mode) begin
+      pcpri_mod_ch <= ~pcpri_mod_ch;
+    end 
+  end  
+end
+   
+
+// =============================================================================
+// Terminal count logic
+// =============================================================================
+
+//For SDI protocol with Dynamic rate control enabled
+generate
+if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "SDI")) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rcount_tc         <= 22'd0;
+    rdiff_comp_lock   <= 16'd0;
+    rdiff_comp_unlock <= 16'd0;
+  end
+  else begin
+    //Terminal count logic
+    //Div by 11 is enabled
+    if (rdiv11 == 1'b1) begin
+      //Gear mode is 16/20
+      if (rgear == 1'b1) begin
+        rcount_tc         <= PPCLK_DIV11_TC;
+        rdiff_comp_lock   <= PDIFF_DIV11_VAL_LOCK;
+        rdiff_comp_unlock <= PDIFF_DIV11_VAL_UNLOCK;
+      end
+      else begin
+        rcount_tc         <= {PPCLK_DIV11_TC[20:0], 1'b0};
+        rdiff_comp_lock   <= {PDIFF_DIV11_VAL_LOCK[14:0], 1'b0};
+        rdiff_comp_unlock <= {PDIFF_DIV11_VAL_UNLOCK[14:0], 1'b0};
+      end
+    end
+    //Div by 2 is enabled
+    else if (rdiv2 == 1'b1) begin
+      //Gear mode is 16/20
+      if (rgear == 1'b1) begin
+        rcount_tc         <= {1'b0,PPCLK_TC[21:1]};
+        rdiff_comp_lock   <= {1'b0,PDIFF_VAL_LOCK[15:1]};
+        rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]};
+      end
+      else begin
+        rcount_tc         <= PPCLK_TC;
+        rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+        rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+      end
+    end
+    //Both div by 11 and div by 2 are disabled
+    else begin
+      //Gear mode is 16/20
+      if (rgear == 1'b1) begin
+        rcount_tc         <= PPCLK_TC;
+        rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+        rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+      end
+      else begin
+        rcount_tc         <= {PPCLK_TC[20:0],1'b0};
+        rdiff_comp_lock   <= {PDIFF_VAL_LOCK[14:0],1'b0};
+        rdiff_comp_unlock <= {PDIFF_VAL_UNLOCK[14:0],1'b0};
+      end
+    end
+  end  
+end
+end
+endgenerate
+
+//For G8B10B protocol with Dynamic rate control enabled
+generate
+if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "G8B10B")) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rcount_tc         <= 22'd0;
+    rdiff_comp_lock   <= 16'd0;
+    rdiff_comp_unlock <= 16'd0;
+  end
+  else begin
+    //Terminal count logic
+    //Div by 2 is enabled
+    if (rdiv2 == 1'b1) begin
+      rcount_tc         <= {1'b0,PPCLK_TC[21:1]};
+      rdiff_comp_lock   <= {1'b0,PDIFF_VAL_LOCK[15:1]};
+      rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]};
+    end
+    else begin
+      rcount_tc         <= PPCLK_TC;
+      rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+      rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+    end
+  end  
+end
+end
+endgenerate
+
+
+//For CPRI protocol with Dynamic rate control is disabled
+generate
+if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "CPRI")) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rcount_tc         <= 22'd0;
+    rdiff_comp_lock   <= 16'd0;
+    rdiff_comp_unlock <= 16'd0;
+  end
+  else begin
+    //Terminal count logic for CPRI protocol
+    //Only if there is a change in the rate mode from the default
+    if (rcpri_mod_ch_st == 1'b1) begin
+      if (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) begin
+        case(sli_cpri_mode)
+          3'd0 : begin //For 0.6Gbps
+            rcount_tc         <= LPCLK_TC_0;
+            case(PLOL_SETTING)
+              'd0 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_00;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_00;
+              end
+              
+              'd1 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_01;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_01;
+              end
+              
+              'd2 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_02;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_02;
+              end
+              
+              'd3 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_03;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_03;
+              end
+              
+              default : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_00;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_00;
+              end
+            endcase
+          end
+          
+          3'd1 : begin //For 1.2Gbps
+            rcount_tc         <= LPCLK_TC_1;
+            case(PLOL_SETTING)
+              'd0 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_10;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_10;
+              end
+              
+              'd1 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_11;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_11;
+              end
+              
+              'd2 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_12;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_12;
+              end
+              
+              'd3 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_13;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_13;
+              end
+              
+              default : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_10;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_10;
+              end
+            endcase
+          end
+          
+          3'd2 : begin //For 2.4Gbps
+            rcount_tc         <= LPCLK_TC_2;
+            case(PLOL_SETTING)
+              'd0 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_20;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_20;
+              end
+              
+              'd1 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_21;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_21;
+              end
+              
+              'd2 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_22;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_22;
+              end
+              
+              'd3 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_23;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_23;
+              end
+              
+              default : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_20;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_20;
+              end
+            endcase
+          end
+          
+          3'd3 : begin //For 3.07Gbps
+            rcount_tc         <= LPCLK_TC_3;
+            case(PLOL_SETTING)
+              'd0 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_30;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_30;
+              end
+              
+              'd1 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_31;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_31;
+              end
+              
+              'd2 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_32;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_32;
+              end
+              
+              'd3 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_33;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_33;
+              end
+            endcase
+          end    
+              
+          3'd4 : begin //For 4.9125bps
+            rcount_tc         <= LPCLK_TC_4;
+            case(PLOL_SETTING)
+              'd0 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_40;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_40;
+              end
+              
+              'd1 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_41;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_41;
+              end
+              
+              'd2 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_42;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_42;
+              end
+              
+              'd3 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_43;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_43;
+              end  
+            
+              default : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_40;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_40;
+              end
+            endcase
+          end
+        
+          default : begin
+            rcount_tc         <= LPCLK_TC_0;
+            rdiff_comp_lock   <= LPDIFF_LOCK_00;
+            rdiff_comp_unlock <= LPDIFF_UNLOCK_00;
+          end
+        endcase
+      end
+    end
+    else begin
+      //If there is no change in the CPRI rate mode from default
+      rcount_tc         <= PPCLK_TC;
+      rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+      rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+    end  
+  end  
+end
+end
+endgenerate
+
+//For PCIe protocol with Dynamic rate control disabled
+generate
+if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "PCIE")) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rcount_tc         <= 22'd0;
+    rdiff_comp_lock   <= 16'd0;
+    rdiff_comp_unlock <= 16'd0;
+  end
+  else begin
+    //Terminal count logic
+    if (PPCIE_MAX_RATE == "2.5") begin
+      //2.5G mode is enabled
+      rcount_tc         <= PPCLK_TC;
+      rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+      rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+    end
+    else begin
+      //5G mode is enabled
+      if (rpcie_mode == 1'b1) begin
+        rcount_tc         <= PPCLK_TC;
+        rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+        rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+      end
+      else begin
+        //2.5G mode is enabled
+        rcount_tc         <= {1'b0,PPCLK_TC[21:1]};
+        rdiff_comp_lock   <= {1'b0,PDIFF_VAL_LOCK[15:1]};
+        rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]};
+      end 
+    end          
+  end  
+end
+end
+endgenerate
+
+//For all protocols other than CPRI & PCIe
+generate
+if ((PDYN_RATE_CTRL == "DISABLED") && ((PPROTOCOL != "CPRI") && (PPROTOCOL != "PCIE"))) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rcount_tc         <= 22'd0;
+    rdiff_comp_lock   <= 16'd0;
+    rdiff_comp_unlock <= 16'd0;
+  end
+  else begin
+    //Terminal count logic for all protocols other than CPRI & PCIe
+    rcount_tc         <= PPCLK_TC;
+    rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+    rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+  end  
+end
+end
+endgenerate
+
+
+// =============================================================================
+// Tx_pclk counter, Heartbeat and Differential value logic
+// =============================================================================
+always @(posedge sli_pclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    pcount      <= 22'd0;
+    pcount_diff <= 22'd65535;
+    phb_cnt     <= 3'd0;
+    phb         <= 1'b0;
+  end
+  else begin
+    //Counter logic
+    if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin
+      pcount <= 22'd0;
+    end
+    else begin
+      pcount <= pcount + 1;
+    end
+    
+    //Heartbeat logic
+    phb_cnt <= phb_cnt + 1;
+    
+    if ((phb_cnt < 3'd4) && (phb_cnt >= 3'd0)) begin
+      phb <= 1'b1;
+    end  
+    else begin
+      phb <= 1'b0;  
+    end 
+    
+    //Differential value logic
+    if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin
+      pcount_diff <= rcount_tc + ~(pcount) + 1;
+    end  
+    else if (ppul_sync_p2 == 1'b1 && ppul_sync_p3 == 1'b0) begin
+      if (pcount_diff[21] == 1'b1) begin
+        pcount_diff <= ~(pcount_diff) + 1;
+      end
+    end
+  end  
+end
+
+
+// =============================================================================
+// State transition logic for SLL FSM
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    sll_state <= LPLL_LOSS_ST; 
+  end
+  else begin
+    //Reasons to declare an immediate loss - Absence of Tx_pclk, Dynamic rate change for SDI or CPRI
+    if ((rstat_pclk == 1'b0) || (rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || 
+    (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin
+      sll_state <= LPLL_LOSS_ST;
+    end
+    else begin  
+      case(sll_state)
+        LPLL_LOSS_ST : begin
+          if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin
+            if (unlock) begin
+              sll_state <= LPLL_LOSS_ST;
+            end
+            else if (lock) begin
+              if (PLOL_SETTING == 2'd0) begin
+                sll_state <= LPLL_PRELOCK_ST;
+              end
+              else begin
+                sll_state <= LPLL_LOCK_ST;
+              end
+            end
+          end
+        end
+        
+        LPLL_LOCK_ST : begin
+          if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin
+            if (lock) begin
+              sll_state <= LPLL_LOCK_ST;
+            end
+            else begin
+              if (PLOL_SETTING == 2'd0) begin
+                sll_state <= LPLL_LOSS_ST;
+              end
+              else begin
+                sll_state <= LPLL_PRELOSS_ST;
+              end
+            end
+          end
+        end
+        
+        LPLL_PRELOCK_ST : begin
+          if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin
+            if (lock) begin
+              sll_state <= LPLL_LOCK_ST;
+            end
+            else begin
+              sll_state <= LPLL_PRELOSS_ST;
+            end
+          end
+        end
+        
+        LPLL_PRELOSS_ST : begin
+          if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin
+            if (unlock) begin
+              sll_state <= LPLL_PRELOSS_ST;
+            end
+            else if (lock) begin
+              sll_state <= LPLL_LOCK_ST;
+            end
+          end
+        end
+        
+        default: begin
+          sll_state <= LPLL_LOSS_ST;
+        end
+      endcase
+    end  
+  end  
+end
+
+
+// =============================================================================
+// Logic for Tx PLL Lock
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    pll_lock <= 1'b0; 
+  end
+  else begin
+    case(sll_state)
+      LPLL_LOSS_ST : begin
+        pll_lock <= 1'b0;
+      end
+      
+      LPLL_LOCK_ST : begin
+        pll_lock <= 1'b1;
+      end
+      
+      LPLL_PRELOSS_ST : begin
+        pll_lock <= 1'b0;
+      end
+      
+      default: begin
+        pll_lock <= 1'b0;
+      end
+    endcase
+  end  
+end
+
+assign slo_plol = ~(pll_lock);
+
+endmodule  
+
+
+//   ===========================================================================
+//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
+//   ---------------------------------------------------------------------------
+//   Copyright (c) 2015 by Lattice Semiconductor Corporation
+//   ALL RIGHTS RESERVED 
+//   ------------------------------------------------------------------
+//
+//   Permission:
+//
+//      Lattice SG Pte. Ltd. grants permission to use this code
+//      pursuant to the terms of the Lattice Reference Design License Agreement. 
+//
+//
+//   Disclaimer:
+//
+//      This VHDL or Verilog source code is intended as a design reference
+//      which illustrates how these types of functions can be implemented.
+//      It is the user's responsibility to verify their design for
+//      consistency and functionality through the use of formal
+//      verification methods.  Lattice provides no warranty
+//      regarding the use or functionality of this code.
+//
+//   ---------------------------------------------------------------------------
+//
+//                  Lattice SG Pte. Ltd.
+//                  101 Thomson Road, United Square #07-02 
+//                  Singapore 307591
+//
+//
+//                  TEL: 1-800-Lattice (USA and Canada)
+//                       +65-6631-2000 (Singapore)
+//                       +1-503-268-8001 (other locations)
+//
+//                  web: http://www.latticesemi.com/
+//                  email: techsupport@latticesemi.com
+//
+//   ---------------------------------------------------------------------------
+//
+// =============================================================================
+//                         FILE DETAILS
+// Project               : Synchronizer Logic
+// File                  : sync.v
+// Title                 : Synchronizer module
+// Description           : 
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.0
+// Author(s)             : AV
+// Mod. Date             : July 7, 2015
+// Changes Made          : Initial Creation
+// -----------------------------------------------------------------------------
+// Version               : 1.1
+// Author(s)             : EB
+// Mod. Date             : March 21, 2017
+// Changes Made          : 
+// =============================================================================
+
+`ifndef PCS_SYNC_MODULE
+`define PCS_SYNC_MODULE
+module sync ( 
+  clk,
+  rst,
+  data_in,
+  data_out
+  );
+  
+input  clk;                  //Clock in which the async data needs to be synchronized to
+input  rst;                  //Active high reset
+input  data_in;              //Asynchronous data
+output data_out;             //Synchronized data
+
+parameter PDATA_RST_VAL = 0; //Reset value for the registers
+
+reg data_p1;
+reg data_p2;
+
+// =============================================================================
+// Synchronization logic
+// =============================================================================
+always @(posedge clk or posedge rst) begin
+  if (rst == 1'b1) begin
+    data_p1 <= PDATA_RST_VAL;
+    data_p2 <= PDATA_RST_VAL; 
+  end
+  else begin
+    data_p1 <= data_in;
+    data_p2 <= data_p1;
+  end  
+end
+
+assign data_out = data_p2; 
+
+endmodule    
+`endif
+

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/.recordref b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/.recordref
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/_CMD_.CML b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/_CMD_.CML
new file mode 100644 (file)
index 0000000..5a64106
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/_CMD_.CML
@@ -0,0 +1 @@
+ -osyn  /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs  -top  sgmii_ecp5  -hdllog  /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr  -encrypt  -mp  4  -verification_mode 0  -vhdl  -prodtype  synplify_pro  -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver  -encrypt  -pro  -dmgen  /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/dm  -lite -ui -fid2 -ram -sharing on -ll 2000 -autosm  -ignore_undefined_lib  -lib work /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd  -verilog  -prodtype  synplify_pro  -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver   -I /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/  -I /home/soft/lattice/diamond/3.10_x64/synpbase/lib   -v2001  -devicelib  /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v  -devicelib  /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v  -encrypt  -pro  -dmgen  /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/dm  -ui -fid2 -ram -sharing on -ll 2000 -autosm  -lib work /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v  -jobname  "compiler" 
\ No newline at end of file

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/_cmd._cml b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/_cmd._cml
new file mode 100644 (file)
index 0000000..fd034f6
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/_cmd._cml
@@ -0,0 +1 @@
+-link    -encrypt        -top sgmii_ecp5 -osyn /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer0.srs /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer1.srs   
\ No newline at end of file

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/dm/layer0.xdm b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/dm/layer0.xdm
new file mode 100644 (file)
index 0000000..eca8c09
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/dm/layer0.xdm
@@ -0,0 +1,548 @@
+%%% protect protected_file
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new file mode 100644 (file)
index 0000000..3a16f3e
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diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/run_options.txt b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/run_options.txt
new file mode 100644 (file)
index 0000000..db46984
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/run_options.txt
@@ -0,0 +1,76 @@
+#--  Synopsys, Inc.
+#--  Version M-2017.03L-SP1-1
+#--  Project file /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/run_options.txt
+#--  Written on Mon May 13 09:09:03 2019
+
+
+#project files
+add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd"
+add_file -verilog "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v"
+add_file -fpga_constraint "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.fdc"
+
+
+
+#implementation: "syn_results"
+impl -add syn_results -type fpga
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+
+#device options
+set_option -technology ecp5um
+set_option -part LFE5UM_25F
+set_option -package MG285C
+set_option -speed_grade -6
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -top_module "sgmii_ecp5"
+
+# hdl_compiler_options
+set_option -distributed_compile 0
+
+# mapper_without_write_options
+set_option -frequency 100
+set_option -srs_instrumentation 1
+
+# mapper_options
+set_option -write_verilog 1
+set_option -write_vhdl 1
+
+# Lattice XP
+set_option -maxfan 50
+set_option -disable_io_insertion 1
+set_option -retiming 0
+set_option -pipe 0
+set_option -forcegsr false
+set_option -fix_gated_and_generated_clocks 1
+set_option -rw_check_on_ram 1
+set_option -update_models_cp 0
+set_option -syn_edif_array_rename 1
+set_option -Write_declared_clocks_only 1
+
+# NFilter
+set_option -no_sequential_opt 0
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "./sgmii_ecp5.edn"
+
+#set log file 
+set_option log_file "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.srf" 
+impl -active "syn_results"

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/scemi_cfg.txt b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/scemi_cfg.txt
new file mode 100644 (file)
index 0000000..868d437
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/scemi_cfg.txt
@@ -0,0 +1,3 @@
+## UMR3 MESSAGE PORT CONFIGURATION FILE
+## ************************************
+XTOR_DPI_MSG_PORT_UMR_ADDR_VERSION=0

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/scratchproject.prs b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/scratchproject.prs
new file mode 100644 (file)
index 0000000..7cf9f4b
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/scratchproject.prs
@@ -0,0 +1,74 @@
+#--  Synopsys, Inc.
+#--  Version M-2017.03L-SP1-1
+#--  Project file /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/scratchproject.prs
+
+#project files
+add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd"
+add_file -verilog "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v"
+add_file -fpga_constraint "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.fdc"
+
+
+
+#implementation: "syn_results"
+impl -add /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results -type fpga
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+
+#device options
+set_option -technology ecp5um
+set_option -part LFE5UM_25F
+set_option -package MG285C
+set_option -speed_grade -6
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -top_module "sgmii_ecp5"
+
+# hdl_compiler_options
+set_option -distributed_compile 0
+
+# mapper_without_write_options
+set_option -frequency 100
+set_option -srs_instrumentation 1
+
+# mapper_options
+set_option -write_verilog 1
+set_option -write_vhdl 1
+
+# Lattice XP
+set_option -maxfan 50
+set_option -disable_io_insertion 1
+set_option -retiming 0
+set_option -pipe 0
+set_option -forcegsr false
+set_option -fix_gated_and_generated_clocks 1
+set_option -rw_check_on_ram 1
+set_option -update_models_cp 0
+set_option -syn_edif_array_rename 1
+set_option -Write_declared_clocks_only 1
+
+# NFilter
+set_option -no_sequential_opt 0
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.edn"
+
+#set log file 
+set_option log_file "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.srf" 
+impl -active "syn_results"

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.areasrr b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.areasrr
new file mode 100644 (file)
index 0000000..c3d63b8
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.areasrr
@@ -0,0 +1,97 @@
+----------------------------------------------------------------------
+Report for cell sgmii_ecp5.v1
+
+Register bits: 221 of 24288 (1%)
+PIC Latch:       0
+I/O cells:       0
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                              CCU2C      113       100.0
+                               DCUA        1       100.0
+                            FD1P3BX       20       100.0
+                            FD1P3DX       92       100.0
+                            FD1S3BX       12       100.0
+                            FD1S3DX       97       100.0
+                                GSR        1       100.0
+                                INV        3       100.0
+                           ORCALUT4      154       100.0
+                              PFUMX        2       100.0
+                                PUR        1       100.0
+                                VHI        6       100.0
+                                VLO        6       100.0
+SUB MODULES 
+          sgmii_ecp5rsl_core_Z2_layer1        1       100.0
+          sgmii_ecp5sll_core_Z1_layer1        1       100.0
+                            sync_0s        1       100.0
+                          sync_0s_0        1       100.0
+                          sync_0s_6        1       100.0
+                            
+                         TOTAL           513           
+----------------------------------------------------------------------
+Report for cell sgmii_ecp5rsl_core_Z2_layer1.netlist
+     Instance path:  rsl_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                              CCU2C       51        45.1
+                            FD1P3BX        4        20.0
+                            FD1P3DX       74        80.4
+                            FD1S3BX       12       100.0
+                            FD1S3DX       37        38.1
+                           ORCALUT4      100        64.9
+                              PFUMX        2       100.0
+                                VHI        1        16.7
+                                VLO        1        16.7
+                            
+                         TOTAL           282           
+----------------------------------------------------------------------
+Report for cell sgmii_ecp5sll_core_Z1_layer1.netlist
+     Instance path:  sll_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                              CCU2C       62        54.9
+                            FD1P3BX       16        80.0
+                            FD1P3DX       18        19.6
+                            FD1S3DX       60        61.9
+                                INV        3       100.0
+                           ORCALUT4       54        35.1
+                                VHI        4        66.7
+                                VLO        4        66.7
+SUB MODULES 
+                            sync_0s        1       100.0
+                          sync_0s_0        1       100.0
+                          sync_0s_6        1       100.0
+                            
+                         TOTAL           224           
+----------------------------------------------------------------------
+Report for cell sync_0s_0.netlist
+  Original Cell name sync_0s
+     Instance path:  sll_inst.pdiff_sync_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                            FD1S3DX        2         2.1
+                                VHI        1        16.7
+                                VLO        1        16.7
+                            
+                         TOTAL             4           
+----------------------------------------------------------------------
+Report for cell sync_0s_6.netlist
+  Original Cell name sync_0s
+     Instance path:  sll_inst.rtc_sync_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                            FD1S3DX        2         2.1
+                                VHI        1        16.7
+                                VLO        1        16.7
+                            
+                         TOTAL             4           
+----------------------------------------------------------------------
+Report for cell sync_0s.netlist
+  Original Cell name sync_0s
+     Instance path:  sll_inst.phb_sync_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                            FD1S3DX        2         2.1
+                                VHI        1        16.7
+                                VLO        1        16.7
+                            
+                         TOTAL             4           

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.fse b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.fse
new file mode 100644 (file)
index 0000000..cc147f0
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.fse
@@ -0,0 +1,12 @@
+
+fsm_encoding {61801018011} sequential
+
+fsm_state_encoding {61801018011} LPLL_LOSS_ST {00}
+
+fsm_state_encoding {61801018011} LPLL_PRELOSS_ST {01}
+
+fsm_state_encoding {61801018011} LPLL_PRELOCK_ST {10}
+
+fsm_state_encoding {61801018011} LPLL_LOCK_ST {11}
+
+fsm_registers {61801018011} {sll_state[1]}  {sll_state[0]} 

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.htm b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.htm
new file mode 100644 (file)
index 0000000..31d89ed
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.htm
@@ -0,0 +1,9 @@
+<html>
+ <head>
+ <title>syntmp/sgmii_ecp5_srr.htm log file</title>
+ </head>
+ <frameset cols="20%, 80%">
+ <frame src="syntmp/sgmii_ecp5_toc.htm" name="tocFrame" />
+                                <frame src="syntmp/sgmii_ecp5_srr.htm" name="srrFrame"/>
+</frameset>
+ </html>

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.prj b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.prj
new file mode 100644 (file)
index 0000000..8e1a1a9
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.prj
@@ -0,0 +1,47 @@
+#-- Lattice Semiconductor Corporation Ltd.
+#-- Synplify OEM project file /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.prj
+#-- Written on Mon May 13 09:09:03 2019
+
+
+#device options
+set_option -technology ecp5um
+set_option -part LFE5UM-85F
+set_option -speed_grade 8
+
+#use verilog 2001 standard option
+set_option -vlog_std v2001
+
+#map options
+set_option -frequency 100
+set_option -fanout_limit 50
+set_option -disable_io_insertion true
+set_option -retiming false
+set_option -pipe false
+set_option -pipe false
+set_option -force_gsr false
+
+#simulation options
+set_option -write_verilog true
+set_option -write_vhdl true
+
+#timing analysis options
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#-- add_file options
+add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd"
+add_file -verilog -lib work "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v"
+add_file -constraint {"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.fdc"}
+
+#-- top module name
+set_option -top_module sgmii_ecp5
+
+#-- set result format/file last
+project -result_file "sgmii_ecp5.edn"
+
+#-- error message log file
+project -log_file sgmii_ecp5.srf
+
+#-- run Synplify with 'arrange VHDL file'
+project -run

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.srd b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.srd
new file mode 100644 (file)
index 0000000..d5aca97
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.srd differ

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.srf b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.srf
new file mode 100644 (file)
index 0000000..fe8286f
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.srf
@@ -0,0 +1,1134 @@
+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
+#install: /home/soft/lattice/diamond/3.10_x64/synpbase
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Mon May 13 09:09:03 2019
+
+#Implementation: syn_results
+
+Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
+VHDL syntax check successful!
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Mon May 13 09:09:04 2019
+
+###########################################################]
+Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
+Verilog syntax check successful!
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Mon May 13 09:09:04 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
+VHDL syntax check successful!
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1.
+Post processing for work.sgmii_ecp5.v1
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB)
+
+
+Process completed successfully.
+# Mon May 13 09:09:04 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
+Verilog syntax check successful!
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work.
+
+       PDATA_RST_VAL=32'b00000000000000000000000000000000
+   Generated name = sync_0s
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work.
+
+       PPROTOCOL=24'b010001110100001001000101
+       PLOL_SETTING=32'b00000000000000000000000000000000
+       PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100
+       PPCIE_MAX_RATE=24'b001100100010111000110101
+       PDIFF_VAL_LOCK=32'b00000000000000000000000000100111
+       PDIFF_VAL_UNLOCK=32'b00000000000000000000000001001110
+       PPCLK_TC=32'b00000000000000100000000000000000
+       PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000
+       PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000
+       PPCLK_DIV11_TC=32'b00000000000000000000000000000000
+       LPLL_LOSS_ST=2'b00
+       LPLL_PRELOSS_ST=2'b01
+       LPLL_PRELOCK_ST=2'b10
+       LPLL_LOCK_ST=2'b11
+       LRCLK_TC=16'b1111111111111111
+       LRCLK_TC_PUL_WIDTH=16'b0000000000110010
+       LHB_WAIT_CNT=8'b11111111
+       LPCLK_TC_0=32'b00000000000000001000000000000000
+       LPCLK_TC_1=32'b00000000000000010000000000000000
+       LPCLK_TC_2=32'b00000000000000100000000000000000
+       LPCLK_TC_3=32'b00000000000000101000000000000000
+       LPCLK_TC_4=32'b00000000000000010000000000000000
+       LPDIFF_LOCK_00=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_10=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_20=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_30=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_40=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_01=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_11=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_21=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_31=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_41=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_02=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_12=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_22=32'b00000000000000000000000011000100
+       LPDIFF_LOCK_32=32'b00000000000000000000000011110101
+       LPDIFF_LOCK_42=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_03=32'b00000000000000000000000010000011
+       LPDIFF_LOCK_13=32'b00000000000000000000000100000110
+       LPDIFF_LOCK_23=32'b00000000000000000000001000001100
+       LPDIFF_LOCK_33=32'b00000000000000000000001010001111
+       LPDIFF_LOCK_43=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011
+       LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110
+       LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010
+       LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001
+       LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111
+       LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000
+       LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000
+       LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000
+       LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100
+       LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001
+       LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010
+       LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111
+       LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001
+   Generated name = sgmii_ecp5sll_core_Z1_layer1
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment.
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work.
+
+       pnum_channels=32'b00000000000000000000000000000001
+       pprotocol=24'b010001110100001001000101
+       pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
+       pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_tx_rdy=32'b00000000000000000000101110111000
+       pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_rx_rdy=32'b00000000000000000000101110111000
+       wa_num_cycles=32'b00000000000000000000010000000000
+       dac_num_cycles=32'b00000000000000000000000000000011
+       lreset_pwidth=32'b00000000000000000000000000000011
+       lwait_b4_trst=32'b00000000000010111110101111000010
+       lwait_b4_trst_s=32'b00000000000000000000001100001101
+       lplol_cnt_width=32'b00000000000000000000000000010100
+       lwait_after_plol0=32'b00000000000000000000000000000100
+       lwait_b4_rrst=32'b00000000000000101100000000000000
+       lrrst_wait_width=32'b00000000000000000000000000010100
+       lwait_after_rrst=32'b00000000000011000011010100000000
+       lwait_b4_rrst_s=32'b00000000000000000000000111001100
+       lrlol_cnt_width=32'b00000000000000000000000000010011
+       lwait_after_lols=32'b00000000000000001100010000000000
+       lwait_after_lols_s=32'b00000000000000000000000010010110
+       llols_cnt_width=32'b00000000000000000000000000010010
+       lrdb_max=32'b00000000000000000000000000001111
+       ltxr_wait_width=32'b00000000000000000000000000001100
+       lrxr_wait_width=32'b00000000000000000000000000001100
+   Generated name = sgmii_ecp5rsl_core_Z2_layer1
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers.
+@N: CL201 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state.
+Extracted state machine for register sll_state
+State machine has 4 reachable states with original encodings of:
+   00
+   01
+   10
+   11
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB)
+
+
+Process completed successfully.
+# Mon May 13 09:09:05 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+
+=======================================================================================
+For a summary of linker messages for components that did not bind, please see log file:
+@L: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.linkerlog
+=======================================================================================
+
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon May 13 09:09:05 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon May 13 09:09:05 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon May 13 09:09:06 2019
+
+###########################################################]
+Pre-mapping Report
+
+# Mon May 13 09:09:07 2019
+
+Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.fdc
+@L: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt 
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt" file 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)
+
+@N: BN362 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances.
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist sgmii_ecp5
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+
+Clock Summary
+******************
+
+          Start                                 Requested     Requested     Clock        Clock                   Clock
+Level     Clock                                 Frequency     Period        Type         Group                   Load 
+----------------------------------------------------------------------------------------------------------------------
+0 -       System                                100.0 MHz     10.000        system       system_clkgroup         0    
+                                                                                                                      
+0 -       sgmii_ecp5|pll_refclki                100.0 MHz     10.000        inferred     Inferred_clkgroup_0     93   
+                                                                                                                      
+0 -       sgmii_ecp5|rxrefclk                   100.0 MHz     10.000        inferred     Inferred_clkgroup_1     77   
+                                                                                                                      
+0 -       sgmii_ecp5|tx_pclk_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_2     53   
+======================================================================================================================
+
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   10 -> 10
+   11 -> 11
+@N: MO225 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 144MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Mon May 13 09:09:07 2019
+
+###########################################################]
+Map & Optimize Report
+
+# Mon May 13 09:09:07 2019
+
+Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   10 -> 10
+   11 -> 11
+@N: MO225 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":909:3:909:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":527:3:527:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] 
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+   1           0h:00m:01s                   4.90ns              155 /       221
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 148MB peak: 149MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+3 non-gated/non-generated clock tree(s) driving 221 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+============================================= Non-Gated/Non-Generated Clocks =============================================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                                   
+--------------------------------------------------------------------------------------------------------------------------
+@K:CKID0001       pll_refclki         port                   91         rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]
+@K:CKID0002       rxrefclk            port                   77         rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]
+@K:CKID0003       DCU0_inst           DCUA                   53         sll_inst.pcount[21]                               
+==========================================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 112MB peak: 149MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 149MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.edn
+M-2017.03L-SP1-1
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 153MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+@W: MT246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":162:4:162:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"
+@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"
+@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk"
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Mon May 13 09:09:11 2019
+#
+
+
+Top view:               sgmii_ecp5
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.fdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 4.043
+
+                                      Requested     Estimated     Requested     Estimated               Clock        Clock              
+Starting Clock                        Frequency     Frequency     Period        Period        Slack     Type         Group              
+----------------------------------------------------------------------------------------------------------------------------------------
+sgmii_ecp5|pll_refclki                100.0 MHz     168.9 MHz     10.000        5.921         4.079     inferred     Inferred_clkgroup_0
+sgmii_ecp5|rxrefclk                   100.0 MHz     167.9 MHz     10.000        5.957         4.043     inferred     Inferred_clkgroup_1
+sgmii_ecp5|tx_pclk_inferred_clock     100.0 MHz     237.5 MHz     10.000        4.211         5.789     inferred     Inferred_clkgroup_2
+System                                100.0 MHz     840.7 MHz     10.000        1.190         8.810     system       system_clkgroup    
+========================================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                                                                |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+Starting                           Ending                             |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+System                             sgmii_ecp5|rxrefclk                |  10.000      8.811  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             System                             |  10.000      8.253  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             sgmii_ecp5|pll_refclki             |  10.000      4.079  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             sgmii_ecp5|tx_pclk_inferred_clock  |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|rxrefclk                System                             |  10.000      8.277  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|rxrefclk                sgmii_ecp5|rxrefclk                |  10.000      4.043  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|tx_pclk_inferred_clock  sgmii_ecp5|pll_refclki             |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|tx_pclk_inferred_clock  sgmii_ecp5|tx_pclk_inferred_clock  |  10.000      5.789  |  No paths    -      |  No paths    -      |  No paths    -    
+============================================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|pll_refclki
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                   Starting                                                        Arrival          
+Instance                           Reference                  Type        Pin     Net              Time        Slack
+                                   Clock                                                                            
+--------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[2]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[2]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[3]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[3]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[17]     sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[17]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[19]     sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[19]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[1]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[1]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[4]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[4]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[5]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[5]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[6]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[6]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[7]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[7]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[8]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[8]      0.907       4.684
+====================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                   Starting                                                          Required          
+Instance                           Reference                  Type        Pin     Net                Time         Slack
+                                   Clock                                                                               
+-----------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[19]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[19]     9.946        4.079
+rsl_inst.genblk1\.plol_cnt[17]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[17]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[18]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[18]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[15]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[15]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[16]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[16]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[13]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[13]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[14]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[14]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[11]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[11]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[12]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[12]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[9]      sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[9]      9.946        4.383
+=======================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.867
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.079
+
+    Number of logic level(s):                15
+    Starting point:                          rsl_inst.genblk1\.plol_cnt[2] / Q
+    Ending point:                            rsl_inst.genblk1\.plol_cnt[19] / D
+    The start point is clocked by            sgmii_ecp5|pll_refclki [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|pll_refclki [rising] on pin CK
+
+Instance / Net                                        Pin      Pin               Arrival     No. of    
+Name                                     Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[2]            FD1S3DX      Q        Out     0.907     0.907       -         
+plol_cnt[2]                              Net          -        -       -         -           2         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     Z        Out     0.606     1.513       -         
+un1_plol_cnt_tc_10                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     Z        Out     0.606     2.119       -         
+un1_plol_cnt_tc_14                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     Z        Out     0.762     2.881       -         
+un1_plol_cnt_tc                          Net          -        -       -         -           5         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     B        In      0.000     2.881       -         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     Z        Out     0.840     3.721       -         
+plol_cnt                                 Net          -        -       -         -           21        
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.721       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.621       -         
+plol_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.621       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.682       -         
+plol_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.682       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.743       -         
+plol_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.743       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.804       -         
+plol_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.804       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.865       -         
+plol_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.865       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.926       -         
+plol_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.926       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.987       -         
+plol_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.987       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.048       -         
+plol_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.048       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.109       -         
+plol_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.109       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        COUT     Out     0.061     5.170       -         
+plol_cnt_cry[18]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        CIN      In      0.000     5.170       -         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        S0       Out     0.698     5.867       -         
+plol_cnt_s[19]                           Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt[19]           FD1S3DX      D        In      0.000     5.867       -         
+=======================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|rxrefclk
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                    Starting                                                      Arrival          
+Instance                            Reference               Type        Pin     Net               Time        Slack
+                                    Clock                                                                          
+-------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rxs_rst           sgmii_ecp5|rxrefclk     FD1P3DX     Q       rxs_rst           1.015       4.043
+rsl_inst.genblk2\.rlol1_cnt[7]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[7]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[8]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[8]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[9]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[9]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[10]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[10]     0.907       4.136
+rsl_inst.genblk2\.rlols0_cnt[1]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[1]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[2]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[2]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[3]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[3]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[4]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[4]     0.907       4.170
+rsl_inst.genblk2\.rlol1_cnt[0]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[0]      0.907       4.742
+===================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                              Starting                                                         Required          
+Instance                                      Reference               Type        Pin     Net                  Time         Slack
+                                              Clock                                                                              
+---------------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[11]     9.946        4.043
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[9]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[9]      9.946        4.104
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[10]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[10]     9.946        4.104
+rsl_inst.genblk2\.rlol1_cnt[17]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[17]      9.946        4.136
+rsl_inst.genblk2\.rlol1_cnt[18]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[18]      9.946        4.136
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[7]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[7]      9.946        4.165
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[8]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[8]      9.946        4.165
+rsl_inst.genblk2\.rlols0_cnt[17]              sgmii_ecp5|rxrefclk     FD1P3DX     D       rlols0_cnt_s[17]     9.946        4.170
+rsl_inst.genblk2\.rlol1_cnt[15]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[15]      9.946        4.197
+rsl_inst.genblk2\.rlol1_cnt[16]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[16]      9.946        4.197
+=================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.902
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     4.043
+
+    Number of logic level(s):                11
+    Starting point:                          rsl_inst.genblk2\.rxs_rst / Q
+    Ending point:                            rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] / D
+    The start point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+
+Instance / Net                                                  Pin      Pin               Arrival     No. of    
+Name                                               Type         Name     Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rxs_rst                          FD1P3DX      Q        Out     1.015     1.015       -         
+rxs_rst                                            Net          -        -       -         -           6         
+rsl_inst.rdo_rx_serdes_rst_c_1[0]                  ORCALUT4     B        In      0.000     1.015       -         
+rsl_inst.rdo_rx_serdes_rst_c_1[0]                  ORCALUT4     Z        Out     0.708     1.723       -         
+rsl_rx_serdes_rst_c                                Net          -        -       -         -           3         
+rsl_inst.dual_or_rserd_rst                         ORCALUT4     A        In      0.000     1.723       -         
+rsl_inst.dual_or_rserd_rst                         ORCALUT4     Z        Out     0.798     2.521       -         
+dual_or_rserd_rst                                  Net          -        -       -         -           9         
+rsl_inst.rx_any_rst                                ORCALUT4     A        In      0.000     2.521       -         
+rsl_inst.rx_any_rst                                ORCALUT4     Z        Out     0.660     3.181       -         
+rx_any_rst                                         Net          -        -       -         -           2         
+rsl_inst.rx_any_rst_RNIFD021                       ORCALUT4     A        In      0.000     3.181       -         
+rsl_inst.rx_any_rst_RNIFD021                       ORCALUT4     Z        Out     0.819     4.000       -         
+rxr_wt_cnt9                                        Net          -        -       -         -           14        
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0]     CCU2C        A1       In      0.000     4.000       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0]     CCU2C        COUT     Out     0.900     4.900       -         
+rxr_wt_cnt_cry[0]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1]     CCU2C        CIN      In      0.000     4.900       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1]     CCU2C        COUT     Out     0.061     4.961       -         
+rxr_wt_cnt_cry[2]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3]     CCU2C        CIN      In      0.000     4.961       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3]     CCU2C        COUT     Out     0.061     5.022       -         
+rxr_wt_cnt_cry[4]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5]     CCU2C        CIN      In      0.000     5.022       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5]     CCU2C        COUT     Out     0.061     5.083       -         
+rxr_wt_cnt_cry[6]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7]     CCU2C        CIN      In      0.000     5.083       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7]     CCU2C        COUT     Out     0.061     5.144       -         
+rxr_wt_cnt_cry[8]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9]     CCU2C        CIN      In      0.000     5.144       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9]     CCU2C        COUT     Out     0.061     5.205       -         
+rxr_wt_cnt_cry[10]                                 Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11]      CCU2C        CIN      In      0.000     5.205       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11]      CCU2C        S0       Out     0.698     5.902       -         
+rxr_wt_cnt_s[11]                                   Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11]          FD1P3DX      D        In      0.000     5.902       -         
+=================================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|tx_pclk_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                            Starting                                                                   Arrival          
+Instance                    Reference                             Type        Pin     Net              Time        Slack
+                            Clock                                                                                       
+------------------------------------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1       sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p1     1.098       5.789
+sll_inst.ppul_sync_p2       sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p2     1.098       5.789
+sll_inst.pcount_diff[0]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_0      0.985       6.147
+sll_inst.pcount[0]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[0]        0.955       6.178
+sll_inst.pcount_diff[1]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_1      0.955       6.239
+sll_inst.pcount_diff[2]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_2      0.955       6.239
+sll_inst.pcount[1]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[1]        0.907       6.287
+sll_inst.pcount[2]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[2]        0.907       6.287
+sll_inst.pcount_diff[3]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_3      0.955       6.300
+sll_inst.pcount_diff[4]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_4      0.955       6.300
+========================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                             Starting                                                                                  Required          
+Instance                     Reference                             Type        Pin     Net                             Time         Slack
+                             Clock                                                                                                       
+-----------------------------------------------------------------------------------------------------------------------------------------
+sll_inst.pcount[21]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[21]                    9.946        5.789
+sll_inst.pcount[19]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[19]                    9.946        5.850
+sll_inst.pcount[20]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[20]                    9.946        5.850
+sll_inst.pcount[17]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[17]                    9.946        5.911
+sll_inst.pcount[18]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[18]                    9.946        5.911
+sll_inst.pcount[15]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[15]                    9.946        5.972
+sll_inst.pcount[16]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[16]                    9.946        5.972
+sll_inst.pcount[13]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[13]                    9.946        6.033
+sll_inst.pcount[14]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[14]                    9.946        6.033
+sll_inst.pcount_diff[21]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3DX     D       un1_pcount_diff_1_s_21_0_S0     9.946        6.034
+=========================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      4.157
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 5.789
+
+    Number of logic level(s):                13
+    Starting point:                          sll_inst.ppul_sync_p1 / Q
+    Ending point:                            sll_inst.pcount[21] / D
+    The start point is clocked by            sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
+
+Instance / Net                             Pin      Pin               Arrival     No. of    
+Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1         FD1S3DX      Q        Out     1.098     1.098       -         
+ppul_sync_p1                  Net          -        -       -         -           25        
+sll_inst.pcount10_0_o3        ORCALUT4     A        In      0.000     1.098       -         
+sll_inst.pcount10_0_o3        ORCALUT4     Z        Out     0.851     1.950       -         
+N_8                           Net          -        -       -         -           25        
+sll_inst.pcount_cry_0[0]      CCU2C        A1       In      0.000     1.950       -         
+sll_inst.pcount_cry_0[0]      CCU2C        COUT     Out     0.900     2.850       -         
+pcount_cry[0]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[1]      CCU2C        CIN      In      0.000     2.850       -         
+sll_inst.pcount_cry_0[1]      CCU2C        COUT     Out     0.061     2.911       -         
+pcount_cry[2]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[3]      CCU2C        CIN      In      0.000     2.911       -         
+sll_inst.pcount_cry_0[3]      CCU2C        COUT     Out     0.061     2.972       -         
+pcount_cry[4]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[5]      CCU2C        CIN      In      0.000     2.972       -         
+sll_inst.pcount_cry_0[5]      CCU2C        COUT     Out     0.061     3.033       -         
+pcount_cry[6]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[7]      CCU2C        CIN      In      0.000     3.033       -         
+sll_inst.pcount_cry_0[7]      CCU2C        COUT     Out     0.061     3.094       -         
+pcount_cry[8]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[9]      CCU2C        CIN      In      0.000     3.094       -         
+sll_inst.pcount_cry_0[9]      CCU2C        COUT     Out     0.061     3.155       -         
+pcount_cry[10]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[11]     CCU2C        CIN      In      0.000     3.155       -         
+sll_inst.pcount_cry_0[11]     CCU2C        COUT     Out     0.061     3.216       -         
+pcount_cry[12]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[13]     CCU2C        CIN      In      0.000     3.216       -         
+sll_inst.pcount_cry_0[13]     CCU2C        COUT     Out     0.061     3.277       -         
+pcount_cry[14]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[15]     CCU2C        CIN      In      0.000     3.277       -         
+sll_inst.pcount_cry_0[15]     CCU2C        COUT     Out     0.061     3.338       -         
+pcount_cry[16]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[17]     CCU2C        CIN      In      0.000     3.338       -         
+sll_inst.pcount_cry_0[17]     CCU2C        COUT     Out     0.061     3.399       -         
+pcount_cry[18]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[19]     CCU2C        CIN      In      0.000     3.399       -         
+sll_inst.pcount_cry_0[19]     CCU2C        COUT     Out     0.061     3.460       -         
+pcount_cry[20]                Net          -        -       -         -           1         
+sll_inst.pcount_s_0[21]       CCU2C        CIN      In      0.000     3.460       -         
+sll_inst.pcount_s_0[21]       CCU2C        S0       Out     0.698     4.157       -         
+pcount_s[21]                  Net          -        -       -         -           1         
+sll_inst.pcount[21]           FD1S3DX      D        In      0.000     4.157       -         
+============================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                                 Arrival          
+Instance      Reference     Type     Pin              Net              Time        Slack
+              Clock                                                                     
+----------------------------------------------------------------------------------------
+DCU0_inst     System        DCUA     CH0_FFS_RLOL     rx_cdr_lol_s     0.000       8.810
+DCU0_inst     System        DCUA     CH0_FFS_RLOS     rx_los_low_s     0.000       8.810
+========================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                       Starting                                                            Required          
+Instance                                               Reference     Type        Pin     Net                               Time         Slack
+                                                       Clock                                                                                 
+---------------------------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     SP      un2_rdo_serdes_rst_dual_c_2_i     9.806        8.810
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     D       rxpr_appd_RNO[0]                  9.946        9.556
+rsl_inst.genblk2\.rlol_p1                              System        FD1S3DX     D       rx_cdr_lol_s                      9.946        9.946
+rsl_inst.genblk2\.rlos_p1                              System        FD1S3DX     D       rx_los_low_s                      9.946        9.946
+=============================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.194
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.806
+
+    - Propagation time:                      0.996
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 8.810
+
+    Number of logic level(s):                2
+    Starting point:                          DCU0_inst / CH0_FFS_RLOL
+    Ending point:                            rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+
+Instance / Net                                                            Pin              Pin               Arrival     No. of    
+Name                                                         Type         Name             Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------------------------------------------------------
+DCU0_inst                                                    DCUA         CH0_FFS_RLOL     Out     0.000     0.000       -         
+rx_cdr_lol_s                                                 Net          -                -       -         -           4         
+rsl_inst.un2_rdo_serdes_rst_dual_c_1_1                       ORCALUT4     A                In      0.000     0.000       -         
+rsl_inst.un2_rdo_serdes_rst_dual_c_1_1                       ORCALUT4     Z                Out     0.606     0.606       -         
+un2_rdo_serdes_rst_dual_c_1_1                                Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0]     ORCALUT4     B                In      0.000     0.606       -         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0]     ORCALUT4     Z                Out     0.390     0.996       -         
+un2_rdo_serdes_rst_dual_c_2_i                                Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]           FD1P3DX      SP               In      0.000     0.996       -         
+===================================================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 221 of 24288 (1%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+CCU2C:          113
+DCUA:           1
+FD1P3BX:        20
+FD1P3DX:        92
+FD1S3BX:        12
+FD1S3DX:        97
+GSR:            1
+INV:            3
+ORCALUT4:       154
+PFUMX:          2
+PUR:            1
+VHI:            6
+VLO:            6
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 153MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Mon May 13 09:09:11 2019
+
+###########################################################]

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.srm b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.srm
new file mode 100644 (file)
index 0000000..c431948
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.srm differ

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.srr b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.srr
new file mode 100644 (file)
index 0000000..fe8286f
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.srr
@@ -0,0 +1,1134 @@
+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
+#install: /home/soft/lattice/diamond/3.10_x64/synpbase
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Mon May 13 09:09:03 2019
+
+#Implementation: syn_results
+
+Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
+VHDL syntax check successful!
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Mon May 13 09:09:04 2019
+
+###########################################################]
+Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
+Verilog syntax check successful!
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Mon May 13 09:09:04 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
+VHDL syntax check successful!
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1.
+Post processing for work.sgmii_ecp5.v1
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB)
+
+
+Process completed successfully.
+# Mon May 13 09:09:04 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
+Verilog syntax check successful!
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work.
+
+       PDATA_RST_VAL=32'b00000000000000000000000000000000
+   Generated name = sync_0s
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work.
+
+       PPROTOCOL=24'b010001110100001001000101
+       PLOL_SETTING=32'b00000000000000000000000000000000
+       PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100
+       PPCIE_MAX_RATE=24'b001100100010111000110101
+       PDIFF_VAL_LOCK=32'b00000000000000000000000000100111
+       PDIFF_VAL_UNLOCK=32'b00000000000000000000000001001110
+       PPCLK_TC=32'b00000000000000100000000000000000
+       PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000
+       PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000
+       PPCLK_DIV11_TC=32'b00000000000000000000000000000000
+       LPLL_LOSS_ST=2'b00
+       LPLL_PRELOSS_ST=2'b01
+       LPLL_PRELOCK_ST=2'b10
+       LPLL_LOCK_ST=2'b11
+       LRCLK_TC=16'b1111111111111111
+       LRCLK_TC_PUL_WIDTH=16'b0000000000110010
+       LHB_WAIT_CNT=8'b11111111
+       LPCLK_TC_0=32'b00000000000000001000000000000000
+       LPCLK_TC_1=32'b00000000000000010000000000000000
+       LPCLK_TC_2=32'b00000000000000100000000000000000
+       LPCLK_TC_3=32'b00000000000000101000000000000000
+       LPCLK_TC_4=32'b00000000000000010000000000000000
+       LPDIFF_LOCK_00=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_10=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_20=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_30=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_40=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_01=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_11=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_21=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_31=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_41=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_02=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_12=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_22=32'b00000000000000000000000011000100
+       LPDIFF_LOCK_32=32'b00000000000000000000000011110101
+       LPDIFF_LOCK_42=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_03=32'b00000000000000000000000010000011
+       LPDIFF_LOCK_13=32'b00000000000000000000000100000110
+       LPDIFF_LOCK_23=32'b00000000000000000000001000001100
+       LPDIFF_LOCK_33=32'b00000000000000000000001010001111
+       LPDIFF_LOCK_43=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011
+       LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110
+       LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010
+       LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001
+       LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111
+       LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000
+       LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000
+       LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000
+       LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100
+       LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001
+       LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010
+       LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111
+       LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001
+   Generated name = sgmii_ecp5sll_core_Z1_layer1
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment.
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work.
+
+       pnum_channels=32'b00000000000000000000000000000001
+       pprotocol=24'b010001110100001001000101
+       pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
+       pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_tx_rdy=32'b00000000000000000000101110111000
+       pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_rx_rdy=32'b00000000000000000000101110111000
+       wa_num_cycles=32'b00000000000000000000010000000000
+       dac_num_cycles=32'b00000000000000000000000000000011
+       lreset_pwidth=32'b00000000000000000000000000000011
+       lwait_b4_trst=32'b00000000000010111110101111000010
+       lwait_b4_trst_s=32'b00000000000000000000001100001101
+       lplol_cnt_width=32'b00000000000000000000000000010100
+       lwait_after_plol0=32'b00000000000000000000000000000100
+       lwait_b4_rrst=32'b00000000000000101100000000000000
+       lrrst_wait_width=32'b00000000000000000000000000010100
+       lwait_after_rrst=32'b00000000000011000011010100000000
+       lwait_b4_rrst_s=32'b00000000000000000000000111001100
+       lrlol_cnt_width=32'b00000000000000000000000000010011
+       lwait_after_lols=32'b00000000000000001100010000000000
+       lwait_after_lols_s=32'b00000000000000000000000010010110
+       llols_cnt_width=32'b00000000000000000000000000010010
+       lrdb_max=32'b00000000000000000000000000001111
+       ltxr_wait_width=32'b00000000000000000000000000001100
+       lrxr_wait_width=32'b00000000000000000000000000001100
+   Generated name = sgmii_ecp5rsl_core_Z2_layer1
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers.
+@N: CL201 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state.
+Extracted state machine for register sll_state
+State machine has 4 reachable states with original encodings of:
+   00
+   01
+   10
+   11
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB)
+
+
+Process completed successfully.
+# Mon May 13 09:09:05 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+
+=======================================================================================
+For a summary of linker messages for components that did not bind, please see log file:
+@L: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.linkerlog
+=======================================================================================
+
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon May 13 09:09:05 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon May 13 09:09:05 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon May 13 09:09:06 2019
+
+###########################################################]
+Pre-mapping Report
+
+# Mon May 13 09:09:07 2019
+
+Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.fdc
+@L: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt 
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt" file 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)
+
+@N: BN362 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances.
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist sgmii_ecp5
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+
+Clock Summary
+******************
+
+          Start                                 Requested     Requested     Clock        Clock                   Clock
+Level     Clock                                 Frequency     Period        Type         Group                   Load 
+----------------------------------------------------------------------------------------------------------------------
+0 -       System                                100.0 MHz     10.000        system       system_clkgroup         0    
+                                                                                                                      
+0 -       sgmii_ecp5|pll_refclki                100.0 MHz     10.000        inferred     Inferred_clkgroup_0     93   
+                                                                                                                      
+0 -       sgmii_ecp5|rxrefclk                   100.0 MHz     10.000        inferred     Inferred_clkgroup_1     77   
+                                                                                                                      
+0 -       sgmii_ecp5|tx_pclk_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_2     53   
+======================================================================================================================
+
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   10 -> 10
+   11 -> 11
+@N: MO225 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 144MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Mon May 13 09:09:07 2019
+
+###########################################################]
+Map & Optimize Report
+
+# Mon May 13 09:09:07 2019
+
+Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   10 -> 10
+   11 -> 11
+@N: MO225 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":909:3:909:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":527:3:527:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] 
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+   1           0h:00m:01s                   4.90ns              155 /       221
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 148MB peak: 149MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+3 non-gated/non-generated clock tree(s) driving 221 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+============================================= Non-Gated/Non-Generated Clocks =============================================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                                   
+--------------------------------------------------------------------------------------------------------------------------
+@K:CKID0001       pll_refclki         port                   91         rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]
+@K:CKID0002       rxrefclk            port                   77         rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]
+@K:CKID0003       DCU0_inst           DCUA                   53         sll_inst.pcount[21]                               
+==========================================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 112MB peak: 149MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 149MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.edn
+M-2017.03L-SP1-1
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 153MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+@W: MT246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":162:4:162:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"
+@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"
+@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk"
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Mon May 13 09:09:11 2019
+#
+
+
+Top view:               sgmii_ecp5
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.fdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 4.043
+
+                                      Requested     Estimated     Requested     Estimated               Clock        Clock              
+Starting Clock                        Frequency     Frequency     Period        Period        Slack     Type         Group              
+----------------------------------------------------------------------------------------------------------------------------------------
+sgmii_ecp5|pll_refclki                100.0 MHz     168.9 MHz     10.000        5.921         4.079     inferred     Inferred_clkgroup_0
+sgmii_ecp5|rxrefclk                   100.0 MHz     167.9 MHz     10.000        5.957         4.043     inferred     Inferred_clkgroup_1
+sgmii_ecp5|tx_pclk_inferred_clock     100.0 MHz     237.5 MHz     10.000        4.211         5.789     inferred     Inferred_clkgroup_2
+System                                100.0 MHz     840.7 MHz     10.000        1.190         8.810     system       system_clkgroup    
+========================================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                                                                |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+Starting                           Ending                             |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+System                             sgmii_ecp5|rxrefclk                |  10.000      8.811  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             System                             |  10.000      8.253  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             sgmii_ecp5|pll_refclki             |  10.000      4.079  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             sgmii_ecp5|tx_pclk_inferred_clock  |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|rxrefclk                System                             |  10.000      8.277  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|rxrefclk                sgmii_ecp5|rxrefclk                |  10.000      4.043  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|tx_pclk_inferred_clock  sgmii_ecp5|pll_refclki             |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|tx_pclk_inferred_clock  sgmii_ecp5|tx_pclk_inferred_clock  |  10.000      5.789  |  No paths    -      |  No paths    -      |  No paths    -    
+============================================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|pll_refclki
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                   Starting                                                        Arrival          
+Instance                           Reference                  Type        Pin     Net              Time        Slack
+                                   Clock                                                                            
+--------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[2]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[2]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[3]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[3]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[17]     sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[17]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[19]     sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[19]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[1]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[1]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[4]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[4]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[5]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[5]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[6]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[6]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[7]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[7]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[8]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[8]      0.907       4.684
+====================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                   Starting                                                          Required          
+Instance                           Reference                  Type        Pin     Net                Time         Slack
+                                   Clock                                                                               
+-----------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[19]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[19]     9.946        4.079
+rsl_inst.genblk1\.plol_cnt[17]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[17]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[18]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[18]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[15]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[15]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[16]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[16]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[13]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[13]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[14]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[14]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[11]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[11]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[12]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[12]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[9]      sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[9]      9.946        4.383
+=======================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.867
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.079
+
+    Number of logic level(s):                15
+    Starting point:                          rsl_inst.genblk1\.plol_cnt[2] / Q
+    Ending point:                            rsl_inst.genblk1\.plol_cnt[19] / D
+    The start point is clocked by            sgmii_ecp5|pll_refclki [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|pll_refclki [rising] on pin CK
+
+Instance / Net                                        Pin      Pin               Arrival     No. of    
+Name                                     Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[2]            FD1S3DX      Q        Out     0.907     0.907       -         
+plol_cnt[2]                              Net          -        -       -         -           2         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     Z        Out     0.606     1.513       -         
+un1_plol_cnt_tc_10                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     Z        Out     0.606     2.119       -         
+un1_plol_cnt_tc_14                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     Z        Out     0.762     2.881       -         
+un1_plol_cnt_tc                          Net          -        -       -         -           5         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     B        In      0.000     2.881       -         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     Z        Out     0.840     3.721       -         
+plol_cnt                                 Net          -        -       -         -           21        
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.721       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.621       -         
+plol_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.621       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.682       -         
+plol_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.682       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.743       -         
+plol_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.743       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.804       -         
+plol_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.804       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.865       -         
+plol_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.865       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.926       -         
+plol_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.926       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.987       -         
+plol_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.987       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.048       -         
+plol_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.048       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.109       -         
+plol_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.109       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        COUT     Out     0.061     5.170       -         
+plol_cnt_cry[18]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        CIN      In      0.000     5.170       -         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        S0       Out     0.698     5.867       -         
+plol_cnt_s[19]                           Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt[19]           FD1S3DX      D        In      0.000     5.867       -         
+=======================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|rxrefclk
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                    Starting                                                      Arrival          
+Instance                            Reference               Type        Pin     Net               Time        Slack
+                                    Clock                                                                          
+-------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rxs_rst           sgmii_ecp5|rxrefclk     FD1P3DX     Q       rxs_rst           1.015       4.043
+rsl_inst.genblk2\.rlol1_cnt[7]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[7]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[8]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[8]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[9]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[9]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[10]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[10]     0.907       4.136
+rsl_inst.genblk2\.rlols0_cnt[1]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[1]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[2]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[2]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[3]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[3]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[4]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[4]     0.907       4.170
+rsl_inst.genblk2\.rlol1_cnt[0]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[0]      0.907       4.742
+===================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                              Starting                                                         Required          
+Instance                                      Reference               Type        Pin     Net                  Time         Slack
+                                              Clock                                                                              
+---------------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[11]     9.946        4.043
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[9]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[9]      9.946        4.104
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[10]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[10]     9.946        4.104
+rsl_inst.genblk2\.rlol1_cnt[17]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[17]      9.946        4.136
+rsl_inst.genblk2\.rlol1_cnt[18]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[18]      9.946        4.136
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[7]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[7]      9.946        4.165
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[8]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[8]      9.946        4.165
+rsl_inst.genblk2\.rlols0_cnt[17]              sgmii_ecp5|rxrefclk     FD1P3DX     D       rlols0_cnt_s[17]     9.946        4.170
+rsl_inst.genblk2\.rlol1_cnt[15]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[15]      9.946        4.197
+rsl_inst.genblk2\.rlol1_cnt[16]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[16]      9.946        4.197
+=================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.902
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     4.043
+
+    Number of logic level(s):                11
+    Starting point:                          rsl_inst.genblk2\.rxs_rst / Q
+    Ending point:                            rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] / D
+    The start point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+
+Instance / Net                                                  Pin      Pin               Arrival     No. of    
+Name                                               Type         Name     Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rxs_rst                          FD1P3DX      Q        Out     1.015     1.015       -         
+rxs_rst                                            Net          -        -       -         -           6         
+rsl_inst.rdo_rx_serdes_rst_c_1[0]                  ORCALUT4     B        In      0.000     1.015       -         
+rsl_inst.rdo_rx_serdes_rst_c_1[0]                  ORCALUT4     Z        Out     0.708     1.723       -         
+rsl_rx_serdes_rst_c                                Net          -        -       -         -           3         
+rsl_inst.dual_or_rserd_rst                         ORCALUT4     A        In      0.000     1.723       -         
+rsl_inst.dual_or_rserd_rst                         ORCALUT4     Z        Out     0.798     2.521       -         
+dual_or_rserd_rst                                  Net          -        -       -         -           9         
+rsl_inst.rx_any_rst                                ORCALUT4     A        In      0.000     2.521       -         
+rsl_inst.rx_any_rst                                ORCALUT4     Z        Out     0.660     3.181       -         
+rx_any_rst                                         Net          -        -       -         -           2         
+rsl_inst.rx_any_rst_RNIFD021                       ORCALUT4     A        In      0.000     3.181       -         
+rsl_inst.rx_any_rst_RNIFD021                       ORCALUT4     Z        Out     0.819     4.000       -         
+rxr_wt_cnt9                                        Net          -        -       -         -           14        
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0]     CCU2C        A1       In      0.000     4.000       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0]     CCU2C        COUT     Out     0.900     4.900       -         
+rxr_wt_cnt_cry[0]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1]     CCU2C        CIN      In      0.000     4.900       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1]     CCU2C        COUT     Out     0.061     4.961       -         
+rxr_wt_cnt_cry[2]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3]     CCU2C        CIN      In      0.000     4.961       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3]     CCU2C        COUT     Out     0.061     5.022       -         
+rxr_wt_cnt_cry[4]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5]     CCU2C        CIN      In      0.000     5.022       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5]     CCU2C        COUT     Out     0.061     5.083       -         
+rxr_wt_cnt_cry[6]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7]     CCU2C        CIN      In      0.000     5.083       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7]     CCU2C        COUT     Out     0.061     5.144       -         
+rxr_wt_cnt_cry[8]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9]     CCU2C        CIN      In      0.000     5.144       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9]     CCU2C        COUT     Out     0.061     5.205       -         
+rxr_wt_cnt_cry[10]                                 Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11]      CCU2C        CIN      In      0.000     5.205       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11]      CCU2C        S0       Out     0.698     5.902       -         
+rxr_wt_cnt_s[11]                                   Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11]          FD1P3DX      D        In      0.000     5.902       -         
+=================================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|tx_pclk_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                            Starting                                                                   Arrival          
+Instance                    Reference                             Type        Pin     Net              Time        Slack
+                            Clock                                                                                       
+------------------------------------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1       sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p1     1.098       5.789
+sll_inst.ppul_sync_p2       sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p2     1.098       5.789
+sll_inst.pcount_diff[0]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_0      0.985       6.147
+sll_inst.pcount[0]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[0]        0.955       6.178
+sll_inst.pcount_diff[1]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_1      0.955       6.239
+sll_inst.pcount_diff[2]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_2      0.955       6.239
+sll_inst.pcount[1]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[1]        0.907       6.287
+sll_inst.pcount[2]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[2]        0.907       6.287
+sll_inst.pcount_diff[3]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_3      0.955       6.300
+sll_inst.pcount_diff[4]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_4      0.955       6.300
+========================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                             Starting                                                                                  Required          
+Instance                     Reference                             Type        Pin     Net                             Time         Slack
+                             Clock                                                                                                       
+-----------------------------------------------------------------------------------------------------------------------------------------
+sll_inst.pcount[21]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[21]                    9.946        5.789
+sll_inst.pcount[19]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[19]                    9.946        5.850
+sll_inst.pcount[20]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[20]                    9.946        5.850
+sll_inst.pcount[17]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[17]                    9.946        5.911
+sll_inst.pcount[18]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[18]                    9.946        5.911
+sll_inst.pcount[15]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[15]                    9.946        5.972
+sll_inst.pcount[16]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[16]                    9.946        5.972
+sll_inst.pcount[13]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[13]                    9.946        6.033
+sll_inst.pcount[14]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[14]                    9.946        6.033
+sll_inst.pcount_diff[21]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3DX     D       un1_pcount_diff_1_s_21_0_S0     9.946        6.034
+=========================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      4.157
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 5.789
+
+    Number of logic level(s):                13
+    Starting point:                          sll_inst.ppul_sync_p1 / Q
+    Ending point:                            sll_inst.pcount[21] / D
+    The start point is clocked by            sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
+
+Instance / Net                             Pin      Pin               Arrival     No. of    
+Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1         FD1S3DX      Q        Out     1.098     1.098       -         
+ppul_sync_p1                  Net          -        -       -         -           25        
+sll_inst.pcount10_0_o3        ORCALUT4     A        In      0.000     1.098       -         
+sll_inst.pcount10_0_o3        ORCALUT4     Z        Out     0.851     1.950       -         
+N_8                           Net          -        -       -         -           25        
+sll_inst.pcount_cry_0[0]      CCU2C        A1       In      0.000     1.950       -         
+sll_inst.pcount_cry_0[0]      CCU2C        COUT     Out     0.900     2.850       -         
+pcount_cry[0]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[1]      CCU2C        CIN      In      0.000     2.850       -         
+sll_inst.pcount_cry_0[1]      CCU2C        COUT     Out     0.061     2.911       -         
+pcount_cry[2]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[3]      CCU2C        CIN      In      0.000     2.911       -         
+sll_inst.pcount_cry_0[3]      CCU2C        COUT     Out     0.061     2.972       -         
+pcount_cry[4]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[5]      CCU2C        CIN      In      0.000     2.972       -         
+sll_inst.pcount_cry_0[5]      CCU2C        COUT     Out     0.061     3.033       -         
+pcount_cry[6]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[7]      CCU2C        CIN      In      0.000     3.033       -         
+sll_inst.pcount_cry_0[7]      CCU2C        COUT     Out     0.061     3.094       -         
+pcount_cry[8]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[9]      CCU2C        CIN      In      0.000     3.094       -         
+sll_inst.pcount_cry_0[9]      CCU2C        COUT     Out     0.061     3.155       -         
+pcount_cry[10]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[11]     CCU2C        CIN      In      0.000     3.155       -         
+sll_inst.pcount_cry_0[11]     CCU2C        COUT     Out     0.061     3.216       -         
+pcount_cry[12]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[13]     CCU2C        CIN      In      0.000     3.216       -         
+sll_inst.pcount_cry_0[13]     CCU2C        COUT     Out     0.061     3.277       -         
+pcount_cry[14]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[15]     CCU2C        CIN      In      0.000     3.277       -         
+sll_inst.pcount_cry_0[15]     CCU2C        COUT     Out     0.061     3.338       -         
+pcount_cry[16]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[17]     CCU2C        CIN      In      0.000     3.338       -         
+sll_inst.pcount_cry_0[17]     CCU2C        COUT     Out     0.061     3.399       -         
+pcount_cry[18]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[19]     CCU2C        CIN      In      0.000     3.399       -         
+sll_inst.pcount_cry_0[19]     CCU2C        COUT     Out     0.061     3.460       -         
+pcount_cry[20]                Net          -        -       -         -           1         
+sll_inst.pcount_s_0[21]       CCU2C        CIN      In      0.000     3.460       -         
+sll_inst.pcount_s_0[21]       CCU2C        S0       Out     0.698     4.157       -         
+pcount_s[21]                  Net          -        -       -         -           1         
+sll_inst.pcount[21]           FD1S3DX      D        In      0.000     4.157       -         
+============================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                                 Arrival          
+Instance      Reference     Type     Pin              Net              Time        Slack
+              Clock                                                                     
+----------------------------------------------------------------------------------------
+DCU0_inst     System        DCUA     CH0_FFS_RLOL     rx_cdr_lol_s     0.000       8.810
+DCU0_inst     System        DCUA     CH0_FFS_RLOS     rx_los_low_s     0.000       8.810
+========================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                       Starting                                                            Required          
+Instance                                               Reference     Type        Pin     Net                               Time         Slack
+                                                       Clock                                                                                 
+---------------------------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     SP      un2_rdo_serdes_rst_dual_c_2_i     9.806        8.810
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     D       rxpr_appd_RNO[0]                  9.946        9.556
+rsl_inst.genblk2\.rlol_p1                              System        FD1S3DX     D       rx_cdr_lol_s                      9.946        9.946
+rsl_inst.genblk2\.rlos_p1                              System        FD1S3DX     D       rx_los_low_s                      9.946        9.946
+=============================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.194
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.806
+
+    - Propagation time:                      0.996
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 8.810
+
+    Number of logic level(s):                2
+    Starting point:                          DCU0_inst / CH0_FFS_RLOL
+    Ending point:                            rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+
+Instance / Net                                                            Pin              Pin               Arrival     No. of    
+Name                                                         Type         Name             Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------------------------------------------------------
+DCU0_inst                                                    DCUA         CH0_FFS_RLOL     Out     0.000     0.000       -         
+rx_cdr_lol_s                                                 Net          -                -       -         -           4         
+rsl_inst.un2_rdo_serdes_rst_dual_c_1_1                       ORCALUT4     A                In      0.000     0.000       -         
+rsl_inst.un2_rdo_serdes_rst_dual_c_1_1                       ORCALUT4     Z                Out     0.606     0.606       -         
+un2_rdo_serdes_rst_dual_c_1_1                                Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0]     ORCALUT4     B                In      0.000     0.606       -         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0]     ORCALUT4     Z                Out     0.390     0.996       -         
+un2_rdo_serdes_rst_dual_c_2_i                                Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]           FD1P3DX      SP               In      0.000     0.996       -         
+===================================================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 221 of 24288 (1%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+CCU2C:          113
+DCUA:           1
+FD1P3BX:        20
+FD1P3DX:        92
+FD1S3BX:        12
+FD1S3DX:        97
+GSR:            1
+INV:            3
+ORCALUT4:       154
+PFUMX:          2
+PUR:            1
+VHI:            6
+VLO:            6
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 153MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Mon May 13 09:09:11 2019
+
+###########################################################]

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.srr.db b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.srr.db
new file mode 100644 (file)
index 0000000..52f21b6
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.srr.db differ

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.srs b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.srs
new file mode 100644 (file)
index 0000000..f5b5ff0
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.srs differ

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.vhm b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.vhm
new file mode 100644 (file)
index 0000000..a488a9a
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.vhm
@@ -0,0 +1,6445 @@
+--
+-- Written by Synplicity
+-- Product Version "M-2017.03L-SP1-1"
+-- Program "Synplify Pro", Mapper "maplat, Build 1796R"
+-- Mon May 13 09:09:11 2019
+--
+
+--
+-- Written by Synplify Pro version Build 1796R
+-- Mon May 13 09:09:11 2019
+--
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library synplify;
+use synplify.components.all;
+library pmi;
+use pmi.pmi_components.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity sync_0s_0 is
+port(
+  ppul_sync :  in std_logic;
+  pdiff_sync :  out std_logic;
+  sli_rst :  in std_logic;
+  pll_refclki :  in std_logic);
+end sync_0s_0;
+
+architecture beh of sync_0s_0 is
+  signal DATA_P1 : std_logic ;
+  signal DATA_P2_QN_1 : std_logic ;
+  signal VCC : std_logic ;
+  signal DATA_P1_QN_1 : std_logic ;
+  signal GND : std_logic ;
+begin
+DATA_P2_REG_Z10: FD1S3DX port map (
+    D => DATA_P1,
+    CK => pll_refclki,
+    CD => sli_rst,
+    Q => pdiff_sync);
+DATA_P1_REG_Z12: FD1S3DX port map (
+    D => ppul_sync,
+    CK => pll_refclki,
+    CD => sli_rst,
+    Q => DATA_P1);
+VCC_0: VHI port map (
+    Z => VCC);
+II_GND: VLO port map (
+    Z => GND);
+end beh;
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library synplify;
+use synplify.components.all;
+library pmi;
+use pmi.pmi_components.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity sync_0s_6 is
+port(
+rtc_pul :  in std_logic;
+ppul_sync :  out std_logic;
+sli_rst :  in std_logic;
+tx_pclk :  in std_logic);
+end sync_0s_6;
+
+architecture beh of sync_0s_6 is
+signal DATA_P1 : std_logic ;
+signal DATA_P2_QN : std_logic ;
+signal VCC : std_logic ;
+signal DATA_P1_QN : std_logic ;
+signal GND : std_logic ;
+begin
+DATA_P2_REG_Z10: FD1S3DX port map (
+  D => DATA_P1,
+  CK => tx_pclk,
+  CD => sli_rst,
+  Q => ppul_sync);
+DATA_P1_REG_Z12: FD1S3DX port map (
+  D => rtc_pul,
+  CK => tx_pclk,
+  CD => sli_rst,
+  Q => DATA_P1);
+VCC_0: VHI port map (
+  Z => VCC);
+II_GND: VLO port map (
+  Z => GND);
+end beh;
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library synplify;
+use synplify.components.all;
+library pmi;
+use pmi.pmi_components.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity sync_0s is
+port(
+phb :  in std_logic;
+rhb_sync :  out std_logic;
+sli_rst :  in std_logic;
+pll_refclki :  in std_logic);
+end sync_0s;
+
+architecture beh of sync_0s is
+signal DATA_P1 : std_logic ;
+signal DATA_P2_QN_0 : std_logic ;
+signal VCC : std_logic ;
+signal DATA_P1_QN_0 : std_logic ;
+signal GND : std_logic ;
+begin
+DATA_P2_REG_Z10: FD1S3DX port map (
+D => DATA_P1,
+CK => pll_refclki,
+CD => sli_rst,
+Q => rhb_sync);
+DATA_P1_REG_Z12: FD1S3DX port map (
+D => phb,
+CK => pll_refclki,
+CD => sli_rst,
+Q => DATA_P1);
+VCC_0: VHI port map (
+Z => VCC);
+II_GND: VLO port map (
+Z => GND);
+end beh;
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library synplify;
+use synplify.components.all;
+library pmi;
+use pmi.pmi_components.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity sgmii_ecp5rsl_core_Z2_layer1 is
+port(
+rx_pcs_rst_c :  in std_logic;
+tx_pcs_rst_c :  in std_logic;
+tx_serdes_rst_c :  in std_logic;
+serdes_rst_dual_c :  in std_logic;
+rsl_tx_pcs_rst_c :  out std_logic;
+rsl_rx_serdes_rst_c :  out std_logic;
+rsl_serdes_rst_dual_c :  out std_logic;
+rsl_tx_serdes_rst_c :  out std_logic;
+rsl_tx_rdy :  out std_logic;
+pll_lock_i :  in std_logic;
+pll_refclki :  in std_logic;
+rsl_rx_rdy :  out std_logic;
+rsl_rst :  in std_logic;
+rxrefclk :  in std_logic;
+rsl_disable :  in std_logic;
+rx_serdes_rst_c :  in std_logic;
+rsl_rx_pcs_rst_c :  out std_logic;
+rst_dual_c :  in std_logic;
+rx_cdr_lol_s :  in std_logic;
+rx_los_low_s :  in std_logic);
+end sgmii_ecp5rsl_core_Z2_layer1;
+
+architecture beh of sgmii_ecp5rsl_core_Z2_layer1 is
+signal RXS_CNT : std_logic_vector(1 downto 0);
+signal RXS_CNT_3 : std_logic_vector(1 downto 0);
+signal RXPR_APPD_RNO : std_logic_vector(0 to 0);
+signal PLOL0_CNT : std_logic_vector(2 downto 0);
+signal PLOL0_CNT_3 : std_logic_vector(2 downto 0);
+signal RXSR_APPD : std_logic_vector(0 to 0);
+signal RXS_CNT_QN : std_logic_vector(1 downto 0);
+signal RLOS_DB_CNT : std_logic_vector(3 downto 0);
+signal RLOS_DB_CNT_QN : std_logic_vector(3 downto 0);
+signal RLOLS0_CNT_S : std_logic_vector(17 downto 0);
+signal RLOLS0_CNT : std_logic_vector(17 downto 0);
+signal RLOLS0_CNT_QN : std_logic_vector(17 downto 0);
+signal RLOL_DB_CNT : std_logic_vector(3 downto 0);
+signal RLOL_DB_CNT_QN : std_logic_vector(3 downto 0);
+signal RLOL1_CNT_S : std_logic_vector(18 downto 0);
+signal RLOL1_CNT : std_logic_vector(18 downto 0);
+signal RLOL1_CNT_QN : std_logic_vector(18 downto 0);
+signal RXR_WT_CNT_S : std_logic_vector(11 downto 0);
+signal RXR_WT_CNT : std_logic_vector(11 downto 0);
+signal RXR_WT_CNT_QN : std_logic_vector(11 downto 0);
+signal RXSR_APPD_QN : std_logic_vector(0 to 0);
+signal RXPR_APPD : std_logic_vector(0 to 0);
+signal RXPR_APPD_QN : std_logic_vector(0 to 0);
+signal TXS_CNT : std_logic_vector(1 downto 0);
+signal TXS_CNT_QN : std_logic_vector(1 downto 0);
+signal TXS_CNT_RNO : std_logic_vector(1 to 1);
+signal TXP_CNT : std_logic_vector(1 downto 0);
+signal TXP_CNT_QN : std_logic_vector(1 downto 0);
+signal TXP_CNT_RNO : std_logic_vector(1 to 1);
+signal PLOL_CNT_S : std_logic_vector(19 downto 0);
+signal PLOL_CNT : std_logic_vector(19 downto 0);
+signal PLOL_CNT_QN : std_logic_vector(19 downto 0);
+signal PLOL0_CNT_QN : std_logic_vector(2 downto 0);
+signal TXR_WT_CNT_S : std_logic_vector(11 downto 0);
+signal TXR_WT_CNT : std_logic_vector(11 downto 0);
+signal TXR_WT_CNT_QN : std_logic_vector(11 downto 0);
+signal TXPR_APPD : std_logic_vector(0 to 0);
+signal TXPR_APPD_QN : std_logic_vector(0 to 0);
+signal UN1_RLOL_DB_CNT_ZERO : std_logic_vector(0 to 0);
+signal UN1_RLOS_DB_CNT_ZERO : std_logic_vector(0 to 0);
+signal UN1_RLOL_DB_CNT_ZERO_BM : std_logic_vector(0 to 0);
+signal UN1_RLOL_DB_CNT_ZERO_AM : std_logic_vector(0 to 0);
+signal UN1_RLOS_DB_CNT_ZERO_BM : std_logic_vector(0 to 0);
+signal UN1_RLOS_DB_CNT_ZERO_AM : std_logic_vector(0 to 0);
+signal RLOL1_CNT_CRY : std_logic_vector(16 downto 0);
+signal RLOL1_CNT_CRY_0_S0 : std_logic_vector(0 to 0);
+signal RLOL1_CNT_CRY_0_COUT : std_logic_vector(17 to 17);
+signal RLOLS0_CNT_CRY : std_logic_vector(16 downto 0);
+signal RLOLS0_CNT_CRY_0_S0 : std_logic_vector(0 to 0);
+signal RLOLS0_CNT_S_0_COUT : std_logic_vector(17 to 17);
+signal RLOLS0_CNT_S_0_S1 : std_logic_vector(17 to 17);
+signal TXR_WT_CNT_CRY : std_logic_vector(10 downto 0);
+signal TXR_WT_CNT_CRY_0_S0 : std_logic_vector(0 to 0);
+signal TXR_WT_CNT_S_0_COUT : std_logic_vector(11 to 11);
+signal TXR_WT_CNT_S_0_S1 : std_logic_vector(11 to 11);
+signal RXR_WT_CNT_CRY : std_logic_vector(10 downto 0);
+signal RXR_WT_CNT_CRY_0_S0 : std_logic_vector(0 to 0);
+signal RXR_WT_CNT_S_0_COUT : std_logic_vector(11 to 11);
+signal RXR_WT_CNT_S_0_S1 : std_logic_vector(11 to 11);
+signal PLOL_CNT_CRY : std_logic_vector(18 downto 0);
+signal PLOL_CNT_CRY_0_S0 : std_logic_vector(0 to 0);
+signal PLOL_CNT_S_0_COUT : std_logic_vector(19 to 19);
+signal PLOL_CNT_S_0_S1 : std_logic_vector(19 to 19);
+signal RXS_RST : std_logic ;
+signal VCC : std_logic ;
+signal DUAL_OR_RSERD_RST : std_logic ;
+signal PLOL0_CNT9 : std_logic ;
+signal WAITA_PLOL0 : std_logic ;
+signal RLOS_DB_P1 : std_logic ;
+signal RLOS_DB : std_logic ;
+signal RXP_RST25 : std_logic ;
+signal RLOL_DB : std_logic ;
+signal UN1_RUI_RST_DUAL_C_1_1 : std_logic ;
+signal RX_ALL_WELL : std_logic ;
+signal RSL_RX_PCS_RST_C_10 : std_logic ;
+signal UN3_RX_ALL_WELL_2 : std_logic ;
+signal UN17_RXR_WT_TC : std_logic ;
+signal UN3_RX_ALL_WELL_1 : std_logic ;
+signal RX_ANY_RST : std_logic ;
+signal RXR_WT_CNT9 : std_logic ;
+signal UN1_RUI_RST_DUAL_C_1_I : std_logic ;
+signal RLOL1_CNT_TC_1 : std_logic ;
+signal \RLOL1_CNT_\ : std_logic ;
+signal RXR_WT_EN : std_logic ;
+signal RXR_WT_CNTE : std_logic ;
+signal RLOLS0_CNT_TC_1 : std_logic ;
+signal UN2_RLOS_REDGE_1_I : std_logic ;
+signal UN18_TXR_WT_TC : std_logic ;
+signal TX_ANY_RST : std_logic ;
+signal PLL_LOL_P2 : std_logic ;
+signal UN2_PLOL_FEDGE_5_I : std_logic ;
+signal N_2124_0 : std_logic ;
+signal WAITA_RLOLS06 : std_logic ;
+signal UN1_RLOLS0_CNT_TC : std_logic ;
+signal WAITA_RLOLS0 : std_logic ;
+signal WAITA_RLOLS0_QN : std_logic ;
+signal WAIT_CALIB_RNO : std_logic ;
+signal UN1_RLOS_FEDGE_1 : std_logic ;
+signal WAIT_CALIB : std_logic ;
+signal WAIT_CALIB_QN : std_logic ;
+signal RXS_RST6 : std_logic ;
+signal UN1_RXS_CNT_TC : std_logic ;
+signal RXS_RST_QN : std_logic ;
+signal RXP_RST2 : std_logic ;
+signal RXP_RST2_QN : std_logic ;
+signal RLOS_P1 : std_logic ;
+signal RLOS_P2 : std_logic ;
+signal RLOS_P2_QN : std_logic ;
+signal RLOS_P1_QN : std_logic ;
+signal RLOS_DB_P1_QN : std_logic ;
+signal RLOS_DB_CNT_AXB_0 : std_logic ;
+signal RLOS_DB_CNT_CRY_1_0_S0 : std_logic ;
+signal RLOS_DB_CNT_CRY_1_0_S1 : std_logic ;
+signal RLOS_DB_CNT_S_3_0_S0 : std_logic ;
+signal UN1_RLOS_DB_CNT_MAX : std_logic ;
+signal RLOS_DB_QN : std_logic ;
+signal RLOLS0_CNTE : std_logic ;
+signal RLOL_P1 : std_logic ;
+signal RLOL_P2 : std_logic ;
+signal RLOL_P2_QN : std_logic ;
+signal RLOL_P1_QN : std_logic ;
+signal RLOL_DB_P1 : std_logic ;
+signal RLOL_DB_P1_QN : std_logic ;
+signal RLOL_DB_CNT_AXB_0 : std_logic ;
+signal RLOL_DB_CNT_CRY_1_0_S0 : std_logic ;
+signal RLOL_DB_CNT_CRY_1_0_S1 : std_logic ;
+signal RLOL_DB_CNT_S_3_0_S0 : std_logic ;
+signal UN1_RLOL_DB_CNT_MAX : std_logic ;
+signal RLOL_DB_QN : std_logic ;
+signal RLOL1_CNTE : std_logic ;
+signal RXSDR_APPD_2 : std_logic ;
+signal RXSDR_APPD : std_logic ;
+signal RXSDR_APPD_QN : std_logic ;
+signal UN1_DUAL_OR_RSERD_RST_2_I : std_logic ;
+signal RXR_WT_EN_QN : std_logic ;
+signal RXDPR_APPD : std_logic ;
+signal RXDPR_APPD_QN : std_logic ;
+signal RSL_RX_RDY_9 : std_logic ;
+signal RUO_RX_RDYR_QN : std_logic ;
+signal UN2_RDO_SERDES_RST_DUAL_C_2_I : std_logic ;
+signal PLOL_FEDGE : std_logic ;
+signal UN1_PLOL0_CNT_TC_1_I : std_logic ;
+signal WAITA_PLOL0_QN : std_logic ;
+signal UN1_PLOL_CNT_TC : std_logic ;
+signal UN2_PLOL_CNT_TC : std_logic ;
+signal TXS_RST : std_logic ;
+signal TXS_RST_QN : std_logic ;
+signal N_10_I : std_logic ;
+signal UN9_PLOL0_CNT_TC : std_logic ;
+signal UN1_PLOL0_CNT_TC_1 : std_logic ;
+signal TXP_RST : std_logic ;
+signal TXP_RST_QN : std_logic ;
+signal N_11_I : std_logic ;
+signal PLL_LOL_P3 : std_logic ;
+signal PLL_LOL_P3_QN : std_logic ;
+signal PLL_LOL_P1 : std_logic ;
+signal PLL_LOL_P2_QN : std_logic ;
+signal PLL_LOL_P1_QN : std_logic ;
+signal TXSR_APPD_2 : std_logic ;
+signal TXSR_APPD : std_logic ;
+signal TXSR_APPD_QN : std_logic ;
+signal UN1_DUAL_OR_SERD_RST_1_1 : std_logic ;
+signal UN1_DUAL_OR_SERD_RST_1_I : std_logic ;
+signal TXR_WT_EN : std_logic ;
+signal TXR_WT_EN_QN : std_logic ;
+signal TXR_WT_CNTE : std_logic ;
+signal UN2_PLOL_FEDGE_2 : std_logic ;
+signal UN2_PLOL_FEDGE_3_I : std_logic ;
+signal TXDPR_APPD : std_logic ;
+signal TXDPR_APPD_QN : std_logic ;
+signal UN2_PLOL_FEDGE_5_1 : std_logic ;
+signal RSL_TX_RDY_8 : std_logic ;
+signal RUO_TX_RDYR_QN : std_logic ;
+signal UN2_PLOL_FEDGE_8_I : std_logic ;
+signal RLOS_REDGE : std_logic ;
+signal RLOLS0_CNT11_0 : std_logic ;
+signal RSL_TX_SERDES_RST_C_7 : std_logic ;
+signal \PLOL_CNT_\ : std_logic ;
+signal \RLOLS0_CNT_\ : std_logic ;
+signal UN8_RXS_CNT_TC : std_logic ;
+signal UN1_TXSR_APPD : std_logic ;
+signal RSL_SERDES_RST_DUAL_C_6 : std_logic ;
+signal UN3_RX_ALL_WELL_2_1 : std_logic ;
+signal UN1_RXSDR_OR_SR_APPD : std_logic ;
+signal UN2_RDO_SERDES_RST_DUAL_C_1_1 : std_logic ;
+signal RSL_RX_SERDES_RST_C_5 : std_logic ;
+signal RLOLS0_CNT_TC_1_10 : std_logic ;
+signal RLOLS0_CNT_TC_1_11 : std_logic ;
+signal RLOLS0_CNT_TC_1_12 : std_logic ;
+signal RLOLS0_CNT_TC_1_13 : std_logic ;
+signal UN1_PLOL_CNT_TC_11 : std_logic ;
+signal UN1_PLOL_CNT_TC_12 : std_logic ;
+signal UN1_PLOL_CNT_TC_13 : std_logic ;
+signal UN1_PLOL_CNT_TC_14 : std_logic ;
+signal RLOL1_CNT_TC_1_11 : std_logic ;
+signal RLOL1_CNT_TC_1_12 : std_logic ;
+signal RLOL1_CNT_TC_1_13 : std_logic ;
+signal RLOL1_CNT_TC_1_14 : std_logic ;
+signal TXSR_APPD_4 : std_logic ;
+signal RSL_TX_PCS_RST_C_4 : std_logic ;
+signal CO0_2 : std_logic ;
+signal UN18_TXR_WT_TC_6 : std_logic ;
+signal UN18_TXR_WT_TC_7 : std_logic ;
+signal UN18_TXR_WT_TC_8 : std_logic ;
+signal UN17_RXR_WT_TC_6 : std_logic ;
+signal UN17_RXR_WT_TC_7 : std_logic ;
+signal UN17_RXR_WT_TC_8 : std_logic ;
+signal RXSDR_APPD_4 : std_logic ;
+signal RLOLS0_CNT_TC_1_9 : std_logic ;
+signal UN1_PLOL_CNT_TC_10 : std_logic ;
+signal RLOL1_CNT_TC_1_10 : std_logic ;
+signal \TXR_WT_CNT_\ : std_logic ;
+signal RLOS_DB_CNT_CRY_0 : std_logic ;
+signal RLOS_DB_CNT_CRY_0_0_S0 : std_logic ;
+signal RLOS_DB_CNT_CRY_0_0_S1 : std_logic ;
+signal RLOS_DB_CNT_CRY_2 : std_logic ;
+signal RLOS_DB_CNT_S_3_0_COUT : std_logic ;
+signal RLOS_DB_CNT_S_3_0_S1 : std_logic ;
+signal RLOL_DB_CNT_CRY_0 : std_logic ;
+signal RLOL_DB_CNT_CRY_0_0_S0 : std_logic ;
+signal RLOL_DB_CNT_CRY_0_0_S1 : std_logic ;
+signal RLOL_DB_CNT_CRY_2 : std_logic ;
+signal RLOL_DB_CNT_S_3_0_COUT : std_logic ;
+signal RLOL_DB_CNT_S_3_0_S1 : std_logic ;
+signal GND : std_logic ;
+signal N_1 : std_logic ;
+signal N_2 : std_logic ;
+signal N_3 : std_logic ;
+signal N_4 : std_logic ;
+signal N_5 : std_logic ;
+signal N_6 : std_logic ;
+signal N_7 : std_logic ;
+begin
+\GENBLK2.RXS_CNT_RNO[0]\: LUT4 
+generic map(
+  init => X"2626"
+)
+port map (
+A => RXS_RST,
+B => RXS_CNT(0),
+C => RXS_CNT(1),
+D => VCC,
+Z => RXS_CNT_3(0));
+\GENBLK2.GENBLK3.LFOR[0].RXPR_APPD_RNO[0]\: LUT4 
+generic map(
+  init => X"0101"
+)
+port map (
+A => DUAL_OR_RSERD_RST,
+B => rx_los_low_s,
+C => rx_cdr_lol_s,
+D => VCC,
+Z => RXPR_APPD_RNO(0));
+\GENBLK1.PLOL0_CNT_RNO[1]\: LUT4 
+generic map(
+  init => X"1222"
+)
+port map (
+A => PLOL0_CNT(1),
+B => PLOL0_CNT9,
+C => WAITA_PLOL0,
+D => PLOL0_CNT(0),
+Z => PLOL0_CNT_3(1));
+\GENBLK2.RXP_RST2_RNO\: LUT4 
+generic map(
+  init => X"BABA"
+)
+port map (
+A => DUAL_OR_RSERD_RST,
+B => RLOS_DB_P1,
+C => RLOS_DB,
+D => VCC,
+Z => RXP_RST25);
+\GENBLK2.GENBLK3.RXDPR_APPD_RNO\: LUT4 
+generic map(
+  init => X"0101"
+)
+port map (
+A => DUAL_OR_RSERD_RST,
+B => RLOS_DB,
+C => RLOL_DB,
+D => VCC,
+Z => UN1_RUI_RST_DUAL_C_1_1);
+\GENBLK2.GENBLK3.RUO_RX_RDYR_RNO\: LUT4 
+generic map(
+  init => X"0002"
+)
+port map (
+A => RX_ALL_WELL,
+B => rst_dual_c,
+C => RSL_RX_PCS_RST_C_10,
+D => DUAL_OR_RSERD_RST,
+Z => UN3_RX_ALL_WELL_2);
+\GENBLK2.GENBLK3.RXR_WT_EN_RNO\: LUT4 
+generic map(
+  init => X"0404"
+)
+port map (
+A => UN17_RXR_WT_TC,
+B => RX_ALL_WELL,
+C => DUAL_OR_RSERD_RST,
+D => VCC,
+Z => UN3_RX_ALL_WELL_1);
+RX_ANY_RST_RNIFD021: LUT4 
+generic map(
+  init => X"FFFE"
+)
+port map (
+A => RX_ANY_RST,
+B => UN17_RXR_WT_TC,
+C => RLOS_DB,
+D => RLOL_DB,
+Z => RXR_WT_CNT9);
+\GENBLK2.GENBLK3.RXDPR_APPD_RNO_0\: LUT4 
+generic map(
+  init => X"FBFB"
+)
+port map (
+A => rst_dual_c,
+B => RX_ALL_WELL,
+C => DUAL_OR_RSERD_RST,
+D => VCC,
+Z => UN1_RUI_RST_DUAL_C_1_I);
+\GENBLK2.RXS_RST_RNIS0OP\: LUT4 
+generic map(
+  init => X"1011"
+)
+port map (
+A => RLOL1_CNT_TC_1,
+B => RXS_RST,
+C => RLOS_DB_P1,
+D => RLOS_DB,
+Z => \RLOL1_CNT_\);
+\GENBLK2.GENBLK3.RXR_WT_EN_RNIQF0H1\: LUT4 
+generic map(
+  init => X"FFEF"
+)
+port map (
+A => RXR_WT_EN,
+B => RX_ANY_RST,
+C => RX_ALL_WELL,
+D => UN17_RXR_WT_TC,
+Z => RXR_WT_CNTE);
+\GENBLK2.RXP_RST2_RNO_0\: LUT4 
+generic map(
+  init => X"EFEE"
+)
+port map (
+A => RLOLS0_CNT_TC_1,
+B => DUAL_OR_RSERD_RST,
+C => RLOS_DB_P1,
+D => RLOS_DB,
+Z => UN2_RLOS_REDGE_1_I);
+\GENBLK1.GENBLK2.RUO_TX_RDYR_RNO\: LUT4 
+generic map(
+  init => X"FEFE"
+)
+port map (
+A => UN18_TXR_WT_TC,
+B => TX_ANY_RST,
+C => PLL_LOL_P2,
+D => VCC,
+Z => UN2_PLOL_FEDGE_5_I);
+\GENBLK2.GENBLK3.LFOR[0].RXSR_APPD_RNO[0]\: LUT4 
+generic map(
+  init => X"EEFE"
+)
+port map (
+A => RXSR_APPD(0),
+B => rx_serdes_rst_c,
+C => RXS_RST,
+D => rsl_disable,
+Z => N_2124_0);
+\GENBLK2.WAITA_RLOLS0_REG_Z618\: FD1P3DX port map (
+D => WAITA_RLOLS06,
+SP => UN1_RLOLS0_CNT_TC,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => WAITA_RLOLS0);
+\GENBLK2.WAIT_CALIB_REG_Z620\: FD1P3BX port map (
+D => WAIT_CALIB_RNO,
+SP => UN1_RLOS_FEDGE_1,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => WAIT_CALIB);
+\GENBLK2.RXS_RST_REG_Z622\: FD1P3DX port map (
+D => RXS_RST6,
+SP => UN1_RXS_CNT_TC,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXS_RST);
+\GENBLK2.RXS_CNT[0]_REG_Z624\: FD1S3DX port map (
+D => RXS_CNT_3(0),
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXS_CNT(0));
+\GENBLK2.RXS_CNT[1]_REG_Z626\: FD1S3DX port map (
+D => RXS_CNT_3(1),
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXS_CNT(1));
+\GENBLK2.RXP_RST2_REG_Z628\: FD1P3BX port map (
+D => RXP_RST25,
+SP => UN2_RLOS_REDGE_1_I,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RXP_RST2);
+\GENBLK2.RLOS_P2_REG_Z630\: FD1S3DX port map (
+D => RLOS_P1,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOS_P2);
+\GENBLK2.RLOS_P1_REG_Z632\: FD1S3DX port map (
+D => rx_los_low_s,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOS_P1);
+\GENBLK2.RLOS_DB_P1_REG_Z634\: FD1S3BX port map (
+D => RLOS_DB,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOS_DB_P1);
+\GENBLK2.RLOS_DB_CNT[0]_REG_Z636\: FD1S3BX port map (
+D => RLOS_DB_CNT_AXB_0,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOS_DB_CNT(0));
+\GENBLK2.RLOS_DB_CNT[1]_REG_Z638\: FD1S3BX port map (
+D => RLOS_DB_CNT_CRY_1_0_S0,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOS_DB_CNT(1));
+\GENBLK2.RLOS_DB_CNT[2]_REG_Z640\: FD1S3BX port map (
+D => RLOS_DB_CNT_CRY_1_0_S1,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOS_DB_CNT(2));
+\GENBLK2.RLOS_DB_CNT[3]_REG_Z642\: FD1S3BX port map (
+D => RLOS_DB_CNT_S_3_0_S0,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOS_DB_CNT(3));
+\GENBLK2.RLOS_DB_REG_Z644\: FD1P3BX port map (
+D => RLOS_DB_CNT(1),
+SP => UN1_RLOS_DB_CNT_MAX,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOS_DB);
+\GENBLK2.RLOLS0_CNT[0]_REG_Z646\: FD1P3DX port map (
+D => RLOLS0_CNT_S(0),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(0));
+\GENBLK2.RLOLS0_CNT[1]_REG_Z648\: FD1P3DX port map (
+D => RLOLS0_CNT_S(1),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(1));
+\GENBLK2.RLOLS0_CNT[2]_REG_Z650\: FD1P3DX port map (
+D => RLOLS0_CNT_S(2),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(2));
+\GENBLK2.RLOLS0_CNT[3]_REG_Z652\: FD1P3DX port map (
+D => RLOLS0_CNT_S(3),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(3));
+\GENBLK2.RLOLS0_CNT[4]_REG_Z654\: FD1P3DX port map (
+D => RLOLS0_CNT_S(4),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(4));
+\GENBLK2.RLOLS0_CNT[5]_REG_Z656\: FD1P3DX port map (
+D => RLOLS0_CNT_S(5),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(5));
+\GENBLK2.RLOLS0_CNT[6]_REG_Z658\: FD1P3DX port map (
+D => RLOLS0_CNT_S(6),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(6));
+\GENBLK2.RLOLS0_CNT[7]_REG_Z660\: FD1P3DX port map (
+D => RLOLS0_CNT_S(7),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(7));
+\GENBLK2.RLOLS0_CNT[8]_REG_Z662\: FD1P3DX port map (
+D => RLOLS0_CNT_S(8),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(8));
+\GENBLK2.RLOLS0_CNT[9]_REG_Z664\: FD1P3DX port map (
+D => RLOLS0_CNT_S(9),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(9));
+\GENBLK2.RLOLS0_CNT[10]_REG_Z666\: FD1P3DX port map (
+D => RLOLS0_CNT_S(10),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(10));
+\GENBLK2.RLOLS0_CNT[11]_REG_Z668\: FD1P3DX port map (
+D => RLOLS0_CNT_S(11),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(11));
+\GENBLK2.RLOLS0_CNT[12]_REG_Z670\: FD1P3DX port map (
+D => RLOLS0_CNT_S(12),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(12));
+\GENBLK2.RLOLS0_CNT[13]_REG_Z672\: FD1P3DX port map (
+D => RLOLS0_CNT_S(13),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(13));
+\GENBLK2.RLOLS0_CNT[14]_REG_Z674\: FD1P3DX port map (
+D => RLOLS0_CNT_S(14),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(14));
+\GENBLK2.RLOLS0_CNT[15]_REG_Z676\: FD1P3DX port map (
+D => RLOLS0_CNT_S(15),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(15));
+\GENBLK2.RLOLS0_CNT[16]_REG_Z678\: FD1P3DX port map (
+D => RLOLS0_CNT_S(16),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(16));
+\GENBLK2.RLOLS0_CNT[17]_REG_Z680\: FD1P3DX port map (
+D => RLOLS0_CNT_S(17),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(17));
+\GENBLK2.RLOL_P2_REG_Z682\: FD1S3DX port map (
+D => RLOL_P1,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL_P2);
+\GENBLK2.RLOL_P1_REG_Z684\: FD1S3DX port map (
+D => rx_cdr_lol_s,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL_P1);
+\GENBLK2.RLOL_DB_P1_REG_Z686\: FD1S3BX port map (
+D => RLOL_DB,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOL_DB_P1);
+\GENBLK2.RLOL_DB_CNT[0]_REG_Z688\: FD1S3BX port map (
+D => RLOL_DB_CNT_AXB_0,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOL_DB_CNT(0));
+\GENBLK2.RLOL_DB_CNT[1]_REG_Z690\: FD1S3BX port map (
+D => RLOL_DB_CNT_CRY_1_0_S0,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOL_DB_CNT(1));
+\GENBLK2.RLOL_DB_CNT[2]_REG_Z692\: FD1S3BX port map (
+D => RLOL_DB_CNT_CRY_1_0_S1,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOL_DB_CNT(2));
+\GENBLK2.RLOL_DB_CNT[3]_REG_Z694\: FD1S3BX port map (
+D => RLOL_DB_CNT_S_3_0_S0,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOL_DB_CNT(3));
+\GENBLK2.RLOL_DB_REG_Z696\: FD1P3BX port map (
+D => RLOL_DB_CNT(1),
+SP => UN1_RLOL_DB_CNT_MAX,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOL_DB);
+\GENBLK2.RLOL1_CNT[0]_REG_Z698\: FD1P3DX port map (
+D => RLOL1_CNT_S(0),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(0));
+\GENBLK2.RLOL1_CNT[1]_REG_Z700\: FD1P3DX port map (
+D => RLOL1_CNT_S(1),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(1));
+\GENBLK2.RLOL1_CNT[2]_REG_Z702\: FD1P3DX port map (
+D => RLOL1_CNT_S(2),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(2));
+\GENBLK2.RLOL1_CNT[3]_REG_Z704\: FD1P3DX port map (
+D => RLOL1_CNT_S(3),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(3));
+\GENBLK2.RLOL1_CNT[4]_REG_Z706\: FD1P3DX port map (
+D => RLOL1_CNT_S(4),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(4));
+\GENBLK2.RLOL1_CNT[5]_REG_Z708\: FD1P3DX port map (
+D => RLOL1_CNT_S(5),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(5));
+\GENBLK2.RLOL1_CNT[6]_REG_Z710\: FD1P3DX port map (
+D => RLOL1_CNT_S(6),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(6));
+\GENBLK2.RLOL1_CNT[7]_REG_Z712\: FD1P3DX port map (
+D => RLOL1_CNT_S(7),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(7));
+\GENBLK2.RLOL1_CNT[8]_REG_Z714\: FD1P3DX port map (
+D => RLOL1_CNT_S(8),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(8));
+\GENBLK2.RLOL1_CNT[9]_REG_Z716\: FD1P3DX port map (
+D => RLOL1_CNT_S(9),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(9));
+\GENBLK2.RLOL1_CNT[10]_REG_Z718\: FD1P3DX port map (
+D => RLOL1_CNT_S(10),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(10));
+\GENBLK2.RLOL1_CNT[11]_REG_Z720\: FD1P3DX port map (
+D => RLOL1_CNT_S(11),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(11));
+\GENBLK2.RLOL1_CNT[12]_REG_Z722\: FD1P3DX port map (
+D => RLOL1_CNT_S(12),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(12));
+\GENBLK2.RLOL1_CNT[13]_REG_Z724\: FD1P3DX port map (
+D => RLOL1_CNT_S(13),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(13));
+\GENBLK2.RLOL1_CNT[14]_REG_Z726\: FD1P3DX port map (
+D => RLOL1_CNT_S(14),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(14));
+\GENBLK2.RLOL1_CNT[15]_REG_Z728\: FD1P3DX port map (
+D => RLOL1_CNT_S(15),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(15));
+\GENBLK2.RLOL1_CNT[16]_REG_Z730\: FD1P3DX port map (
+D => RLOL1_CNT_S(16),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(16));
+\GENBLK2.RLOL1_CNT[17]_REG_Z732\: FD1P3DX port map (
+D => RLOL1_CNT_S(17),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(17));
+\GENBLK2.RLOL1_CNT[18]_REG_Z734\: FD1P3DX port map (
+D => RLOL1_CNT_S(18),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(18));
+\GENBLK2.GENBLK3.RXSDR_APPD_REG_Z736\: FD1S3BX port map (
+D => RXSDR_APPD_2,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RXSDR_APPD);
+\GENBLK2.GENBLK3.RXR_WT_EN_REG_Z738\: FD1P3DX port map (
+D => UN3_RX_ALL_WELL_1,
+SP => UN1_DUAL_OR_RSERD_RST_2_I,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_EN);
+\GENBLK2.GENBLK3.RXR_WT_CNT[0]_REG_Z740\: FD1P3DX port map (
+D => RXR_WT_CNT_S(0),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(0));
+\GENBLK2.GENBLK3.RXR_WT_CNT[1]_REG_Z742\: FD1P3DX port map (
+D => RXR_WT_CNT_S(1),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(1));
+\GENBLK2.GENBLK3.RXR_WT_CNT[2]_REG_Z744\: FD1P3DX port map (
+D => RXR_WT_CNT_S(2),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(2));
+\GENBLK2.GENBLK3.RXR_WT_CNT[3]_REG_Z746\: FD1P3DX port map (
+D => RXR_WT_CNT_S(3),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(3));
+\GENBLK2.GENBLK3.RXR_WT_CNT[4]_REG_Z748\: FD1P3DX port map (
+D => RXR_WT_CNT_S(4),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(4));
+\GENBLK2.GENBLK3.RXR_WT_CNT[5]_REG_Z750\: FD1P3DX port map (
+D => RXR_WT_CNT_S(5),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(5));
+\GENBLK2.GENBLK3.RXR_WT_CNT[6]_REG_Z752\: FD1P3DX port map (
+D => RXR_WT_CNT_S(6),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(6));
+\GENBLK2.GENBLK3.RXR_WT_CNT[7]_REG_Z754\: FD1P3DX port map (
+D => RXR_WT_CNT_S(7),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(7));
+\GENBLK2.GENBLK3.RXR_WT_CNT[8]_REG_Z756\: FD1P3DX port map (
+D => RXR_WT_CNT_S(8),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(8));
+\GENBLK2.GENBLK3.RXR_WT_CNT[9]_REG_Z758\: FD1P3DX port map (
+D => RXR_WT_CNT_S(9),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(9));
+\GENBLK2.GENBLK3.RXR_WT_CNT[10]_REG_Z760\: FD1P3DX port map (
+D => RXR_WT_CNT_S(10),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(10));
+\GENBLK2.GENBLK3.RXR_WT_CNT[11]_REG_Z762\: FD1P3DX port map (
+D => RXR_WT_CNT_S(11),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(11));
+\GENBLK2.GENBLK3.RXDPR_APPD_REG_Z764\: FD1P3DX port map (
+D => UN1_RUI_RST_DUAL_C_1_1,
+SP => UN1_RUI_RST_DUAL_C_1_I,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXDPR_APPD);
+\GENBLK2.GENBLK3.RUO_RX_RDYR_REG_Z766\: FD1P3DX port map (
+D => UN3_RX_ALL_WELL_2,
+SP => RXR_WT_CNT9,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RSL_RX_RDY_9);
+\GENBLK2.GENBLK3.LFOR[0].RXSR_APPD[0]_REG_Z768\: FD1S3DX port map (
+D => N_2124_0,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXSR_APPD(0));
+\GENBLK2.GENBLK3.LFOR[0].RXPR_APPD[0]_REG_Z770\: FD1P3DX port map (
+D => RXPR_APPD_RNO(0),
+SP => UN2_RDO_SERDES_RST_DUAL_C_2_I,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXPR_APPD(0));
+\GENBLK1.WAITA_PLOL0_REG_Z772\: FD1P3DX port map (
+D => PLOL_FEDGE,
+SP => UN1_PLOL0_CNT_TC_1_I,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => WAITA_PLOL0);
+\GENBLK1.TXS_RST_REG_Z774\: FD1P3DX port map (
+D => UN1_PLOL_CNT_TC,
+SP => UN2_PLOL_CNT_TC,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXS_RST);
+\GENBLK1.TXS_CNT[0]_REG_Z776\: FD1S3DX port map (
+D => N_10_I,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXS_CNT(0));
+\GENBLK1.TXS_CNT[1]_REG_Z778\: FD1S3DX port map (
+D => TXS_CNT_RNO(1),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXS_CNT(1));
+\GENBLK1.TXP_RST_REG_Z780\: FD1P3DX port map (
+D => UN9_PLOL0_CNT_TC,
+SP => UN1_PLOL0_CNT_TC_1,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXP_RST);
+\GENBLK1.TXP_CNT[0]_REG_Z782\: FD1S3DX port map (
+D => N_11_I,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXP_CNT(0));
+\GENBLK1.TXP_CNT[1]_REG_Z784\: FD1S3DX port map (
+D => TXP_CNT_RNO(1),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXP_CNT(1));
+\GENBLK1.PLOL_CNT[0]_REG_Z786\: FD1S3DX port map (
+D => PLOL_CNT_S(0),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(0));
+\GENBLK1.PLOL_CNT[1]_REG_Z788\: FD1S3DX port map (
+D => PLOL_CNT_S(1),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(1));
+\GENBLK1.PLOL_CNT[2]_REG_Z790\: FD1S3DX port map (
+D => PLOL_CNT_S(2),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(2));
+\GENBLK1.PLOL_CNT[3]_REG_Z792\: FD1S3DX port map (
+D => PLOL_CNT_S(3),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(3));
+\GENBLK1.PLOL_CNT[4]_REG_Z794\: FD1S3DX port map (
+D => PLOL_CNT_S(4),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(4));
+\GENBLK1.PLOL_CNT[5]_REG_Z796\: FD1S3DX port map (
+D => PLOL_CNT_S(5),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(5));
+\GENBLK1.PLOL_CNT[6]_REG_Z798\: FD1S3DX port map (
+D => PLOL_CNT_S(6),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(6));
+\GENBLK1.PLOL_CNT[7]_REG_Z800\: FD1S3DX port map (
+D => PLOL_CNT_S(7),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(7));
+\GENBLK1.PLOL_CNT[8]_REG_Z802\: FD1S3DX port map (
+D => PLOL_CNT_S(8),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(8));
+\GENBLK1.PLOL_CNT[9]_REG_Z804\: FD1S3DX port map (
+D => PLOL_CNT_S(9),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(9));
+\GENBLK1.PLOL_CNT[10]_REG_Z806\: FD1S3DX port map (
+D => PLOL_CNT_S(10),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(10));
+\GENBLK1.PLOL_CNT[11]_REG_Z808\: FD1S3DX port map (
+D => PLOL_CNT_S(11),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(11));
+\GENBLK1.PLOL_CNT[12]_REG_Z810\: FD1S3DX port map (
+D => PLOL_CNT_S(12),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(12));
+\GENBLK1.PLOL_CNT[13]_REG_Z812\: FD1S3DX port map (
+D => PLOL_CNT_S(13),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(13));
+\GENBLK1.PLOL_CNT[14]_REG_Z814\: FD1S3DX port map (
+D => PLOL_CNT_S(14),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(14));
+\GENBLK1.PLOL_CNT[15]_REG_Z816\: FD1S3DX port map (
+D => PLOL_CNT_S(15),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(15));
+\GENBLK1.PLOL_CNT[16]_REG_Z818\: FD1S3DX port map (
+D => PLOL_CNT_S(16),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(16));
+\GENBLK1.PLOL_CNT[17]_REG_Z820\: FD1S3DX port map (
+D => PLOL_CNT_S(17),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(17));
+\GENBLK1.PLOL_CNT[18]_REG_Z822\: FD1S3DX port map (
+D => PLOL_CNT_S(18),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(18));
+\GENBLK1.PLOL_CNT[19]_REG_Z824\: FD1S3DX port map (
+D => PLOL_CNT_S(19),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(19));
+\GENBLK1.PLOL0_CNT[0]_REG_Z826\: FD1S3DX port map (
+D => PLOL0_CNT_3(0),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL0_CNT(0));
+\GENBLK1.PLOL0_CNT[1]_REG_Z828\: FD1S3DX port map (
+D => PLOL0_CNT_3(1),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL0_CNT(1));
+\GENBLK1.PLOL0_CNT[2]_REG_Z830\: FD1S3DX port map (
+D => PLOL0_CNT_3(2),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL0_CNT(2));
+\GENBLK1.PLL_LOL_P3_REG_Z832\: FD1S3DX port map (
+D => PLL_LOL_P2,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLL_LOL_P3);
+\GENBLK1.PLL_LOL_P2_REG_Z834\: FD1S3DX port map (
+D => PLL_LOL_P1,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLL_LOL_P2);
+\GENBLK1.PLL_LOL_P1_REG_Z836\: FD1S3DX port map (
+D => pll_lock_i,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLL_LOL_P1);
+\GENBLK1.GENBLK2.TXSR_APPD_REG_Z838\: FD1S3BX port map (
+D => TXSR_APPD_2,
+CK => pll_refclki,
+PD => rsl_rst,
+Q => TXSR_APPD);
+\GENBLK1.GENBLK2.TXR_WT_EN_REG_Z840\: FD1P3DX port map (
+D => UN1_DUAL_OR_SERD_RST_1_1,
+SP => UN1_DUAL_OR_SERD_RST_1_I,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_EN);
+\GENBLK1.GENBLK2.TXR_WT_CNT[0]_REG_Z842\: FD1P3DX port map (
+D => TXR_WT_CNT_S(0),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(0));
+\GENBLK1.GENBLK2.TXR_WT_CNT[1]_REG_Z844\: FD1P3DX port map (
+D => TXR_WT_CNT_S(1),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(1));
+\GENBLK1.GENBLK2.TXR_WT_CNT[2]_REG_Z846\: FD1P3DX port map (
+D => TXR_WT_CNT_S(2),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(2));
+\GENBLK1.GENBLK2.TXR_WT_CNT[3]_REG_Z848\: FD1P3DX port map (
+D => TXR_WT_CNT_S(3),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(3));
+\GENBLK1.GENBLK2.TXR_WT_CNT[4]_REG_Z850\: FD1P3DX port map (
+D => TXR_WT_CNT_S(4),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(4));
+\GENBLK1.GENBLK2.TXR_WT_CNT[5]_REG_Z852\: FD1P3DX port map (
+D => TXR_WT_CNT_S(5),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(5));
+\GENBLK1.GENBLK2.TXR_WT_CNT[6]_REG_Z854\: FD1P3DX port map (
+D => TXR_WT_CNT_S(6),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(6));
+\GENBLK1.GENBLK2.TXR_WT_CNT[7]_REG_Z856\: FD1P3DX port map (
+D => TXR_WT_CNT_S(7),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(7));
+\GENBLK1.GENBLK2.TXR_WT_CNT[8]_REG_Z858\: FD1P3DX port map (
+D => TXR_WT_CNT_S(8),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(8));
+\GENBLK1.GENBLK2.TXR_WT_CNT[9]_REG_Z860\: FD1P3DX port map (
+D => TXR_WT_CNT_S(9),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(9));
+\GENBLK1.GENBLK2.TXR_WT_CNT[10]_REG_Z862\: FD1P3DX port map (
+D => TXR_WT_CNT_S(10),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(10));
+\GENBLK1.GENBLK2.TXR_WT_CNT[11]_REG_Z864\: FD1P3DX port map (
+D => TXR_WT_CNT_S(11),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(11));
+\GENBLK1.GENBLK2.TXDPR_APPD_REG_Z866\: FD1P3DX port map (
+D => UN2_PLOL_FEDGE_2,
+SP => UN2_PLOL_FEDGE_3_I,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXDPR_APPD);
+\GENBLK1.GENBLK2.RUO_TX_RDYR_REG_Z868\: FD1P3DX port map (
+D => UN2_PLOL_FEDGE_5_1,
+SP => UN2_PLOL_FEDGE_5_I,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => RSL_TX_RDY_8);
+\GENBLK1.GENBLK2.MFOR[0].TXPR_APPD[0]_REG_Z870\: FD1P3DX port map (
+D => UN2_PLOL_FEDGE_2,
+SP => UN2_PLOL_FEDGE_8_I,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXPR_APPD(0));
+\GENBLK1.TXS_CNT_RNO[0]\: LUT4 
+generic map(
+  init => X"A6A6"
+)
+port map (
+A => TXS_CNT(0),
+B => TXS_RST,
+C => UN1_PLOL_CNT_TC,
+D => VCC,
+Z => N_10_I);
+\GENBLK1.TXS_CNT_RNO[1]\: LUT4 
+generic map(
+  init => X"CC6C"
+)
+port map (
+A => TXS_CNT(0),
+B => TXS_CNT(1),
+C => TXS_RST,
+D => UN1_PLOL_CNT_TC,
+Z => TXS_CNT_RNO(1));
+\GENBLK1.GENBLK2.TXR_WT_EN_RNO\: LUT4 
+generic map(
+  init => X"0F2F"
+)
+port map (
+A => TXPR_APPD(0),
+B => PLL_LOL_P2,
+C => UN1_DUAL_OR_SERD_RST_1_1,
+D => RSL_TX_RDY_8,
+Z => UN1_DUAL_OR_SERD_RST_1_I);
+\GENBLK2.RXS_RST6\: LUT4 
+generic map(
+  init => X"2020"
+)
+port map (
+A => RLOL_DB,
+B => RLOS_DB,
+C => RLOL1_CNT_TC_1,
+D => VCC,
+Z => RXS_RST6);
+\GENBLK2.WAIT_CALIB_RNIKRP81\: LUT4 
+generic map(
+  init => X"FFFE"
+)
+port map (
+A => RXS_RST,
+B => WAIT_CALIB,
+C => RLOL1_CNT_TC_1,
+D => RLOS_REDGE,
+Z => RLOL1_CNTE);
+\GENBLK2.WAITA_RLOLS0_RNI266C\: LUT4 
+generic map(
+  init => X"FEFE"
+)
+port map (
+A => RLOLS0_CNT11_0,
+B => WAITA_RLOLS0,
+C => RLOLS0_CNT_TC_1,
+D => VCC,
+Z => RLOLS0_CNTE);
+\GENBLK1.PLOL_CNT11_I\: LUT4 
+generic map(
+  init => X"0202"
+)
+port map (
+A => PLL_LOL_P2,
+B => UN1_PLOL_CNT_TC,
+C => RSL_TX_SERDES_RST_C_7,
+D => VCC,
+Z => \PLOL_CNT_\);
+\GENBLK2.RLOLS0_CNT11_I\: LUT4 
+generic map(
+  init => X"1111"
+)
+port map (
+A => RLOLS0_CNT11_0,
+B => RLOLS0_CNT_TC_1,
+C => VCC,
+D => VCC,
+Z => \RLOLS0_CNT_\);
+\GENBLK2.UN1_RXS_CNT_TC\: LUT4 
+generic map(
+  init => X"FEFC"
+)
+port map (
+A => RLOL_DB,
+B => RLOS_DB,
+C => UN8_RXS_CNT_TC,
+D => RLOL1_CNT_TC_1,
+Z => UN1_RXS_CNT_TC);
+\GENBLK2.WAIT_CALIB_RNO\: LUT4 
+generic map(
+  init => X"A3A3"
+)
+port map (
+A => RLOL_DB,
+B => RLOS_DB,
+C => RLOL1_CNT_TC_1,
+D => VCC,
+Z => WAIT_CALIB_RNO);
+\GENBLK1.GENBLK2.MFOR[0].TXPR_APPD_RNO[0]\: LUT4 
+generic map(
+  init => X"FFFE"
+)
+port map (
+A => UN1_TXSR_APPD,
+B => PLL_LOL_P2,
+C => RSL_SERDES_RST_DUAL_C_6,
+D => RSL_TX_SERDES_RST_C_7,
+Z => UN2_PLOL_FEDGE_8_I);
+\GENBLK2.GENBLK3.RXR_WT_EN_RNO_0\: LUT4 
+generic map(
+  init => X"FEFF"
+)
+port map (
+A => DUAL_OR_RSERD_RST,
+B => UN3_RX_ALL_WELL_2_1,
+C => UN17_RXR_WT_TC,
+D => RX_ALL_WELL,
+Z => UN1_DUAL_OR_RSERD_RST_2_I);
+\GENBLK2.GENBLK3.LFOR[0].RXPR_APPD_RNO_0[0]\: LUT4 
+generic map(
+  init => X"FFFB"
+)
+port map (
+A => UN1_RXSDR_OR_SR_APPD,
+B => UN2_RDO_SERDES_RST_DUAL_C_1_1,
+C => RSL_RX_SERDES_RST_C_5,
+D => RSL_SERDES_RST_DUAL_C_6,
+Z => UN2_RDO_SERDES_RST_DUAL_C_2_I);
+\GENBLK1.UN2_PLOL_CNT_TC\: LUT4 
+generic map(
+  init => X"F8F8"
+)
+port map (
+A => TXS_CNT(0),
+B => TXS_CNT(1),
+C => UN1_PLOL_CNT_TC,
+D => VCC,
+Z => UN2_PLOL_CNT_TC);
+\GENBLK1.GENBLK2.TXR_WT_EN_RNICEBT\: LUT4 
+generic map(
+  init => X"FEFE"
+)
+port map (
+A => TXR_WT_EN,
+B => UN18_TXR_WT_TC,
+C => TX_ANY_RST,
+D => VCC,
+Z => TXR_WT_CNTE);
+\GENBLK2.UN1_RLOS_FEDGE_1\: LUT4 
+generic map(
+  init => X"F6F6"
+)
+port map (
+A => RLOS_DB,
+B => RLOS_DB_P1,
+C => RLOL1_CNT_TC_1,
+D => VCC,
+Z => UN1_RLOS_FEDGE_1);
+\GENBLK2.UN1_RLOLS0_CNT_TC\: LUT4 
+generic map(
+  init => X"FEFE"
+)
+port map (
+A => RLOLS0_CNT11_0,
+B => WAITA_RLOLS06,
+C => RLOLS0_CNT_TC_1,
+D => VCC,
+Z => UN1_RLOLS0_CNT_TC);
+\GENBLK1.GENBLK2.TXDPR_APPD_RNO\: LUT4 
+generic map(
+  init => X"FFFE"
+)
+port map (
+A => PLL_LOL_P2,
+B => RSL_SERDES_RST_DUAL_C_6,
+C => RSL_TX_SERDES_RST_C_7,
+D => rst_dual_c,
+Z => UN2_PLOL_FEDGE_3_I);
+\GENBLK1.TXP_CNT_RNO[0]\: LUT4 
+generic map(
+  init => X"A6A6"
+)
+port map (
+A => TXP_CNT(0),
+B => TXP_RST,
+C => UN9_PLOL0_CNT_TC,
+D => VCC,
+Z => N_11_I);
+UN2_PLOL_FEDGE_5_1_Z890: LUT4 
+generic map(
+  init => X"1111"
+)
+port map (
+A => PLL_LOL_P2,
+B => TX_ANY_RST,
+C => VCC,
+D => VCC,
+Z => UN2_PLOL_FEDGE_5_1);
+UN1_DUAL_OR_SERD_RST_1_1_Z891: LUT4 
+generic map(
+  init => X"0101"
+)
+port map (
+A => UN18_TXR_WT_TC,
+B => RSL_SERDES_RST_DUAL_C_6,
+C => RSL_TX_SERDES_RST_C_7,
+D => VCC,
+Z => UN1_DUAL_OR_SERD_RST_1_1);
+\GENBLK1.TXP_CNT_RNO[1]\: LUT4 
+generic map(
+  init => X"CC6C"
+)
+port map (
+A => TXP_CNT(0),
+B => TXP_CNT(1),
+C => TXP_RST,
+D => UN9_PLOL0_CNT_TC,
+Z => TXP_CNT_RNO(1));
+RLOLS0_CNT_TC_1_Z893: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RLOLS0_CNT_TC_1_10,
+B => RLOLS0_CNT_TC_1_11,
+C => RLOLS0_CNT_TC_1_12,
+D => RLOLS0_CNT_TC_1_13,
+Z => RLOLS0_CNT_TC_1);
+\GENBLK1.UN1_PLOL_CNT_TC\: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => UN1_PLOL_CNT_TC_11,
+B => UN1_PLOL_CNT_TC_12,
+C => UN1_PLOL_CNT_TC_13,
+D => UN1_PLOL_CNT_TC_14,
+Z => UN1_PLOL_CNT_TC);
+RLOL1_CNT_TC_1_Z895: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RLOL1_CNT_TC_1_11,
+B => RLOL1_CNT_TC_1_12,
+C => RLOL1_CNT_TC_1_13,
+D => RLOL1_CNT_TC_1_14,
+Z => RLOL1_CNT_TC_1);
+\UN1_GENBLK2.RLOL_DB_CNT_AXB_0\: LUT4 
+generic map(
+  init => X"9999"
+)
+port map (
+A => RLOL_DB_CNT(0),
+B => UN1_RLOL_DB_CNT_ZERO(0),
+C => VCC,
+D => VCC,
+Z => RLOL_DB_CNT_AXB_0);
+\UN1_GENBLK2.RLOS_DB_CNT_AXB_0\: LUT4 
+generic map(
+  init => X"9999"
+)
+port map (
+A => RLOS_DB_CNT(0),
+B => UN1_RLOS_DB_CNT_ZERO(0),
+C => VCC,
+D => VCC,
+Z => RLOS_DB_CNT_AXB_0);
+\GENBLK1.WAITA_PLOL0_RNO\: LUT4 
+generic map(
+  init => X"F6F6"
+)
+port map (
+A => PLL_LOL_P2,
+B => PLL_LOL_P3,
+C => UN9_PLOL0_CNT_TC,
+D => VCC,
+Z => UN1_PLOL0_CNT_TC_1_I);
+\GENBLK1.GENBLK2.MFOR[0].UN1_TXSR_APPD\: LUT4 
+generic map(
+  init => X"C8C8"
+)
+port map (
+A => TXDPR_APPD,
+B => TXSR_APPD_4,
+C => RSL_TX_PCS_RST_C_4,
+D => VCC,
+Z => UN1_TXSR_APPD);
+\GENBLK1.GENBLK2.TXSR_APPD_2\: LUT4 
+generic map(
+  init => X"FEFE"
+)
+port map (
+A => TXSR_APPD_4,
+B => RSL_SERDES_RST_DUAL_C_6,
+C => RSL_TX_SERDES_RST_C_7,
+D => VCC,
+Z => TXSR_APPD_2);
+\GENBLK1.PLOL0_CNT_3[0]\: LUT4 
+generic map(
+  init => X"1414"
+)
+port map (
+A => PLOL0_CNT9,
+B => PLOL0_CNT(0),
+C => WAITA_PLOL0,
+D => VCC,
+Z => PLOL0_CNT_3(0));
+\GENBLK1.PLOL0_CNT_3[2]\: LUT4 
+generic map(
+  init => X"1320"
+)
+port map (
+A => CO0_2,
+B => PLOL0_CNT9,
+C => PLOL0_CNT(1),
+D => PLOL0_CNT(2),
+Z => PLOL0_CNT_3(2));
+\GENBLK1.GENBLK2.UN18_TXR_WT_TC\: LUT4 
+generic map(
+  init => X"8080"
+)
+port map (
+A => UN18_TXR_WT_TC_6,
+B => UN18_TXR_WT_TC_7,
+C => UN18_TXR_WT_TC_8,
+D => VCC,
+Z => UN18_TXR_WT_TC);
+UN2_PLOL_FEDGE_2_Z904: LUT4 
+generic map(
+  init => X"0101"
+)
+port map (
+A => PLL_LOL_P2,
+B => RSL_SERDES_RST_DUAL_C_6,
+C => RSL_TX_SERDES_RST_C_7,
+D => VCC,
+Z => UN2_PLOL_FEDGE_2);
+TX_ANY_RST_Z905: LUT4 
+generic map(
+  init => X"FFFE"
+)
+port map (
+A => RSL_SERDES_RST_DUAL_C_6,
+B => RSL_TX_PCS_RST_C_4,
+C => RSL_TX_SERDES_RST_C_7,
+D => rst_dual_c,
+Z => TX_ANY_RST);
+RX_ANY_RST_Z906: LUT4 
+generic map(
+  init => X"FEFE"
+)
+port map (
+A => DUAL_OR_RSERD_RST,
+B => RSL_RX_PCS_RST_C_10,
+C => rst_dual_c,
+D => VCC,
+Z => RX_ANY_RST);
+\GENBLK2.GENBLK3.UN17_RXR_WT_TC\: LUT4 
+generic map(
+  init => X"8080"
+)
+port map (
+A => UN17_RXR_WT_TC_6,
+B => UN17_RXR_WT_TC_7,
+C => UN17_RXR_WT_TC_8,
+D => VCC,
+Z => UN17_RXR_WT_TC);
+\UN1_RLOL_DB_CNT_ZERO_BM[0]_Z908\: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RLOL_DB_CNT(0),
+B => RLOL_DB_CNT(1),
+C => RLOL_DB_CNT(2),
+D => RLOL_DB_CNT(3),
+Z => UN1_RLOL_DB_CNT_ZERO_BM(0));
+\UN1_RLOL_DB_CNT_ZERO[0]_Z909\: PFUMX port map (
+ALUT => UN1_RLOL_DB_CNT_ZERO_BM(0),
+BLUT => UN1_RLOL_DB_CNT_ZERO_AM(0),
+C0 => RLOL_P2,
+Z => UN1_RLOL_DB_CNT_ZERO(0));
+\UN1_RLOS_DB_CNT_ZERO_BM[0]_Z910\: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RLOS_DB_CNT(0),
+B => RLOS_DB_CNT(1),
+C => RLOS_DB_CNT(2),
+D => RLOS_DB_CNT(3),
+Z => UN1_RLOS_DB_CNT_ZERO_BM(0));
+\UN1_RLOS_DB_CNT_ZERO[0]_Z911\: PFUMX port map (
+ALUT => UN1_RLOS_DB_CNT_ZERO_BM(0),
+BLUT => UN1_RLOS_DB_CNT_ZERO_AM(0),
+C0 => RLOS_P2,
+Z => UN1_RLOS_DB_CNT_ZERO(0));
+\GENBLK2.UN1_RLOL_DB_CNT_MAX\: LUT4 
+generic map(
+  init => X"8001"
+)
+port map (
+A => RLOL_DB_CNT(0),
+B => RLOL_DB_CNT(1),
+C => RLOL_DB_CNT(2),
+D => RLOL_DB_CNT(3),
+Z => UN1_RLOL_DB_CNT_MAX);
+\GENBLK2.UN1_RLOS_DB_CNT_MAX\: LUT4 
+generic map(
+  init => X"8001"
+)
+port map (
+A => RLOS_DB_CNT(0),
+B => RLOS_DB_CNT(1),
+C => RLOS_DB_CNT(2),
+D => RLOS_DB_CNT(3),
+Z => UN1_RLOS_DB_CNT_MAX);
+\GENBLK1.UN1_PLOL0_CNT_TC_1\: LUT4 
+generic map(
+  init => X"F8F8"
+)
+port map (
+A => TXP_CNT(0),
+B => TXP_CNT(1),
+C => UN9_PLOL0_CNT_TC,
+D => VCC,
+Z => UN1_PLOL0_CNT_TC_1);
+\GENBLK2.WAITA_RLOLS06\: LUT4 
+generic map(
+  init => X"0504"
+)
+port map (
+A => RLOL_DB,
+B => RLOL_DB_P1,
+C => RLOS_DB,
+D => RLOS_DB_P1,
+Z => WAITA_RLOLS06);
+\RXS_CNT_3[1]_Z916\: LUT4 
+generic map(
+  init => X"6464"
+)
+port map (
+A => RXS_CNT(0),
+B => RXS_CNT(1),
+C => RXS_RST,
+D => VCC,
+Z => RXS_CNT_3(1));
+\GENBLK2.GENBLK3.LFOR[0].UN1_RXSDR_OR_SR_APPD\: LUT4 
+generic map(
+  init => X"3200"
+)
+port map (
+A => RXSR_APPD(0),
+B => RX_ALL_WELL,
+C => RXSDR_APPD_4,
+D => RSL_RX_PCS_RST_C_10,
+Z => UN1_RXSDR_OR_SR_APPD);
+RLOLS0_CNT_TC_1_13_Z918: LUT4 
+generic map(
+  init => X"1010"
+)
+port map (
+A => RLOLS0_CNT(16),
+B => RLOLS0_CNT(17),
+C => RLOLS0_CNT_TC_1_9,
+D => VCC,
+Z => RLOLS0_CNT_TC_1_13);
+\GENBLK1.UN1_PLOL_CNT_TC_14\: LUT4 
+generic map(
+  init => X"0100"
+)
+port map (
+A => PLOL_CNT(4),
+B => PLOL_CNT(5),
+C => PLOL_CNT(18),
+D => UN1_PLOL_CNT_TC_10,
+Z => UN1_PLOL_CNT_TC_14);
+RLOL1_CNT_TC_1_14_Z920: LUT4 
+generic map(
+  init => X"0100"
+)
+port map (
+A => RLOL1_CNT(11),
+B => RLOL1_CNT(12),
+C => RLOL1_CNT(18),
+D => RLOL1_CNT_TC_1_10,
+Z => RLOL1_CNT_TC_1_14);
+\GENBLK2.GENBLK3.UN3_RX_ALL_WELL_2_1\: LUT4 
+generic map(
+  init => X"0E0E"
+)
+port map (
+A => RXPR_APPD(0),
+B => RXDPR_APPD,
+C => RSL_RX_RDY_9,
+D => VCC,
+Z => UN3_RX_ALL_WELL_2_1);
+RDO_SERDES_RST_DUAL_C: LUT4 
+generic map(
+  init => X"F4F4"
+)
+port map (
+A => rsl_disable,
+B => rsl_rst,
+C => serdes_rst_dual_c,
+D => VCC,
+Z => RSL_SERDES_RST_DUAL_C_6);
+RDO_TX_SERDES_RST_C: LUT4 
+generic map(
+  init => X"F4F4"
+)
+port map (
+A => rsl_disable,
+B => TXS_RST,
+C => tx_serdes_rst_c,
+D => VCC,
+Z => RSL_TX_SERDES_RST_C_7);
+\RDO_TX_PCS_RST_C_1[0]\: LUT4 
+generic map(
+  init => X"F4F4"
+)
+port map (
+A => rsl_disable,
+B => TXP_RST,
+C => tx_pcs_rst_c,
+D => VCC,
+Z => RSL_TX_PCS_RST_C_4);
+\RDO_RX_SERDES_RST_C_1[0]\: LUT4 
+generic map(
+  init => X"F4F4"
+)
+port map (
+A => rsl_disable,
+B => RXS_RST,
+C => rx_serdes_rst_c,
+D => VCC,
+Z => RSL_RX_SERDES_RST_C_5);
+\RDO_RX_PCS_RST_C_1[0]\: LUT4 
+generic map(
+  init => X"F4F4"
+)
+port map (
+A => rsl_disable,
+B => RXP_RST2,
+C => rx_pcs_rst_c,
+D => VCC,
+Z => RSL_RX_PCS_RST_C_10);
+\GENBLK1.UN9_PLOL0_CNT_TC\: LUT4 
+generic map(
+  init => X"1010"
+)
+port map (
+A => PLOL0_CNT(0),
+B => PLOL0_CNT(1),
+C => PLOL0_CNT(2),
+D => VCC,
+Z => UN9_PLOL0_CNT_TC);
+\GENBLK2.GENBLK3.UN17_RXR_WT_TC_6\: LUT4 
+generic map(
+  init => X"4000"
+)
+port map (
+A => RXR_WT_CNT(0),
+B => RXR_WT_CNT(8),
+C => RXR_WT_CNT(9),
+D => RXR_WT_CNT(11),
+Z => UN17_RXR_WT_TC_6);
+\GENBLK2.GENBLK3.UN17_RXR_WT_TC_7\: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RXR_WT_CNT(3),
+B => RXR_WT_CNT(4),
+C => RXR_WT_CNT(5),
+D => RXR_WT_CNT(7),
+Z => UN17_RXR_WT_TC_7);
+\GENBLK2.GENBLK3.UN17_RXR_WT_TC_8\: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RXR_WT_CNT(1),
+B => RXR_WT_CNT(2),
+C => RXR_WT_CNT(6),
+D => RXR_WT_CNT(10),
+Z => UN17_RXR_WT_TC_8);
+\GENBLK1.GENBLK2.UN18_TXR_WT_TC_6\: LUT4 
+generic map(
+  init => X"4000"
+)
+port map (
+A => TXR_WT_CNT(0),
+B => TXR_WT_CNT(8),
+C => TXR_WT_CNT(9),
+D => TXR_WT_CNT(11),
+Z => UN18_TXR_WT_TC_6);
+\GENBLK1.GENBLK2.UN18_TXR_WT_TC_7\: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => TXR_WT_CNT(3),
+B => TXR_WT_CNT(4),
+C => TXR_WT_CNT(5),
+D => TXR_WT_CNT(7),
+Z => UN18_TXR_WT_TC_7);
+\GENBLK1.GENBLK2.UN18_TXR_WT_TC_8\: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => TXR_WT_CNT(1),
+B => TXR_WT_CNT(2),
+C => TXR_WT_CNT(6),
+D => TXR_WT_CNT(10),
+Z => UN18_TXR_WT_TC_8);
+RLOLS0_CNT_TC_1_9_Z934: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RLOLS0_CNT(1),
+B => RLOLS0_CNT(2),
+C => RLOLS0_CNT(3),
+D => RLOLS0_CNT(4),
+Z => RLOLS0_CNT_TC_1_9);
+RLOLS0_CNT_TC_1_10_Z935: LUT4 
+generic map(
+  init => X"4000"
+)
+port map (
+A => RLOLS0_CNT(0),
+B => RLOLS0_CNT(10),
+C => RLOLS0_CNT(14),
+D => RLOLS0_CNT(15),
+Z => RLOLS0_CNT_TC_1_10);
+RLOLS0_CNT_TC_1_11_Z936: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RLOLS0_CNT(9),
+B => RLOLS0_CNT(11),
+C => RLOLS0_CNT(12),
+D => RLOLS0_CNT(13),
+Z => RLOLS0_CNT_TC_1_11);
+RLOLS0_CNT_TC_1_12_Z937: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RLOLS0_CNT(5),
+B => RLOLS0_CNT(6),
+C => RLOLS0_CNT(7),
+D => RLOLS0_CNT(8),
+Z => RLOLS0_CNT_TC_1_12);
+\GENBLK1.UN1_PLOL_CNT_TC_10\: LUT4 
+generic map(
+  init => X"1000"
+)
+port map (
+A => PLOL_CNT(2),
+B => PLOL_CNT(3),
+C => PLOL_CNT(17),
+D => PLOL_CNT(19),
+Z => UN1_PLOL_CNT_TC_10);
+\GENBLK1.UN1_PLOL_CNT_TC_11\: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => PLOL_CNT(13),
+B => PLOL_CNT(14),
+C => PLOL_CNT(15),
+D => PLOL_CNT(16),
+Z => UN1_PLOL_CNT_TC_11);
+\GENBLK1.UN1_PLOL_CNT_TC_12\: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => PLOL_CNT(7),
+B => PLOL_CNT(8),
+C => PLOL_CNT(9),
+D => PLOL_CNT(11),
+Z => UN1_PLOL_CNT_TC_12);
+\GENBLK1.UN1_PLOL_CNT_TC_13\: LUT4 
+generic map(
+  init => X"0008"
+)
+port map (
+A => PLOL_CNT(1),
+B => PLOL_CNT(6),
+C => PLOL_CNT(10),
+D => PLOL_CNT(12),
+Z => UN1_PLOL_CNT_TC_13);
+RLOL1_CNT_TC_1_10_Z942: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RLOL1_CNT(7),
+B => RLOL1_CNT(8),
+C => RLOL1_CNT(9),
+D => RLOL1_CNT(10),
+Z => RLOL1_CNT_TC_1_10);
+RLOL1_CNT_TC_1_11_Z943: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RLOL1_CNT(3),
+B => RLOL1_CNT(4),
+C => RLOL1_CNT(5),
+D => RLOL1_CNT(6),
+Z => RLOL1_CNT_TC_1_11);
+RLOL1_CNT_TC_1_12_Z944: LUT4 
+generic map(
+  init => X"0100"
+)
+port map (
+A => RLOL1_CNT(0),
+B => RLOL1_CNT(1),
+C => RLOL1_CNT(2),
+D => RLOL1_CNT(17),
+Z => RLOL1_CNT_TC_1_12);
+RLOL1_CNT_TC_1_13_Z945: LUT4 
+generic map(
+  init => X"0040"
+)
+port map (
+A => RLOL1_CNT(13),
+B => RLOL1_CNT(14),
+C => RLOL1_CNT(15),
+D => RLOL1_CNT(16),
+Z => RLOL1_CNT_TC_1_13);
+\GENBLK2.GENBLK3.RXSDR_APPD_2\: LUT4 
+generic map(
+  init => X"EEEE"
+)
+port map (
+A => RXSDR_APPD_4,
+B => serdes_rst_dual_c,
+C => VCC,
+D => VCC,
+Z => RXSDR_APPD_2);
+RX_ALL_WELL_Z947: LUT4 
+generic map(
+  init => X"1111"
+)
+port map (
+A => RLOL_DB,
+B => RLOS_DB,
+C => VCC,
+D => VCC,
+Z => RX_ALL_WELL);
+\GENBLK2.UN8_RXS_CNT_TC\: LUT4 
+generic map(
+  init => X"8888"
+)
+port map (
+A => RXS_CNT(0),
+B => RXS_CNT(1),
+C => VCC,
+D => VCC,
+Z => UN8_RXS_CNT_TC);
+PLOL_FEDGE_Z949: LUT4 
+generic map(
+  init => X"4444"
+)
+port map (
+A => PLL_LOL_P2,
+B => PLL_LOL_P3,
+C => VCC,
+D => VCC,
+Z => PLOL_FEDGE);
+RLOS_REDGE_Z950: LUT4 
+generic map(
+  init => X"2222"
+)
+port map (
+A => RLOS_DB,
+B => RLOS_DB_P1,
+C => VCC,
+D => VCC,
+Z => RLOS_REDGE);
+\GENBLK1.PLOL0_CNT_3_RNO[2]\: LUT4 
+generic map(
+  init => X"8888"
+)
+port map (
+A => PLOL0_CNT(0),
+B => WAITA_PLOL0,
+C => VCC,
+D => VCC,
+Z => CO0_2);
+UN2_RDO_SERDES_RST_DUAL_C_1_1_Z952: LUT4 
+generic map(
+  init => X"1111"
+)
+port map (
+A => rx_cdr_lol_s,
+B => rx_los_low_s,
+C => VCC,
+D => VCC,
+Z => UN2_RDO_SERDES_RST_DUAL_C_1_1);
+\UN1_RLOS_DB_CNT_ZERO_AM[0]_Z953\: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RLOS_DB_CNT(0),
+B => RLOS_DB_CNT(1),
+C => RLOS_DB_CNT(2),
+D => RLOS_DB_CNT(3),
+Z => UN1_RLOS_DB_CNT_ZERO_AM(0));
+\UN1_RLOL_DB_CNT_ZERO_AM[0]_Z954\: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RLOL_DB_CNT(0),
+B => RLOL_DB_CNT(1),
+C => RLOL_DB_CNT(2),
+D => RLOL_DB_CNT(3),
+Z => UN1_RLOL_DB_CNT_ZERO_AM(0));
+DUAL_OR_RSERD_RST_Z955: LUT4 
+generic map(
+  init => X"EEFE"
+)
+port map (
+A => RSL_RX_SERDES_RST_C_5,
+B => serdes_rst_dual_c,
+C => rsl_rst,
+D => rsl_disable,
+Z => DUAL_OR_RSERD_RST);
+\GENBLK1.PLOL0_CNT9\: LUT4 
+generic map(
+  init => X"AAAE"
+)
+port map (
+A => PLL_LOL_P2,
+B => PLOL0_CNT(2),
+C => PLOL0_CNT(1),
+D => PLOL0_CNT(0),
+Z => PLOL0_CNT9);
+\GENBLK2.RLOLS0_CNT11_0\: LUT4 
+generic map(
+  init => X"4F44"
+)
+port map (
+A => RLOL_DB_P1,
+B => RLOL_DB,
+C => RLOS_DB_P1,
+D => RLOS_DB,
+Z => RLOLS0_CNT11_0);
+\GENBLK1.GENBLK2.TXR_WT_CNT9_I\: LUT4 
+generic map(
+  init => X"1555"
+)
+port map (
+A => TX_ANY_RST,
+B => UN18_TXR_WT_TC_8,
+C => UN18_TXR_WT_TC_7,
+D => UN18_TXR_WT_TC_6,
+Z => \TXR_WT_CNT_\);
+\GENBLK2.RLOL1_CNT_CRY_0[0]\: CCU2C 
+generic map(
+  INIT0 => X"500c",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => \RLOL1_CNT_\,
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_7,
+COUT => RLOL1_CNT_CRY(0),
+S0 => RLOL1_CNT_CRY_0_S0(0),
+S1 => RLOL1_CNT_S(0));
+\GENBLK2.RLOL1_CNT_CRY_0[1]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOL1_CNT_\,
+B0 => RLOL1_CNT(1),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(2),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL1_CNT_CRY(0),
+COUT => RLOL1_CNT_CRY(2),
+S0 => RLOL1_CNT_S(1),
+S1 => RLOL1_CNT_S(2));
+\GENBLK2.RLOL1_CNT_CRY_0[3]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOL1_CNT_\,
+B0 => RLOL1_CNT(3),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(4),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL1_CNT_CRY(2),
+COUT => RLOL1_CNT_CRY(4),
+S0 => RLOL1_CNT_S(3),
+S1 => RLOL1_CNT_S(4));
+\GENBLK2.RLOL1_CNT_CRY_0[5]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOL1_CNT_\,
+B0 => RLOL1_CNT(5),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(6),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL1_CNT_CRY(4),
+COUT => RLOL1_CNT_CRY(6),
+S0 => RLOL1_CNT_S(5),
+S1 => RLOL1_CNT_S(6));
+\GENBLK2.RLOL1_CNT_CRY_0[7]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOL1_CNT_\,
+B0 => RLOL1_CNT(7),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(8),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL1_CNT_CRY(6),
+COUT => RLOL1_CNT_CRY(8),
+S0 => RLOL1_CNT_S(7),
+S1 => RLOL1_CNT_S(8));
+\GENBLK2.RLOL1_CNT_CRY_0[9]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOL1_CNT_\,
+B0 => RLOL1_CNT(9),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(10),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL1_CNT_CRY(8),
+COUT => RLOL1_CNT_CRY(10),
+S0 => RLOL1_CNT_S(9),
+S1 => RLOL1_CNT_S(10));
+\GENBLK2.RLOL1_CNT_CRY_0[11]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOL1_CNT_\,
+B0 => RLOL1_CNT(11),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(12),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL1_CNT_CRY(10),
+COUT => RLOL1_CNT_CRY(12),
+S0 => RLOL1_CNT_S(11),
+S1 => RLOL1_CNT_S(12));
+\GENBLK2.RLOL1_CNT_CRY_0[13]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOL1_CNT_\,
+B0 => RLOL1_CNT(13),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(14),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL1_CNT_CRY(12),
+COUT => RLOL1_CNT_CRY(14),
+S0 => RLOL1_CNT_S(13),
+S1 => RLOL1_CNT_S(14));
+\GENBLK2.RLOL1_CNT_CRY_0[15]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOL1_CNT_\,
+B0 => RLOL1_CNT(15),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(16),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL1_CNT_CRY(14),
+COUT => RLOL1_CNT_CRY(16),
+S0 => RLOL1_CNT_S(15),
+S1 => RLOL1_CNT_S(16));
+\GENBLK2.RLOL1_CNT_CRY_0[17]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"800a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOL1_CNT_\,
+B0 => RLOL1_CNT(17),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(18),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL1_CNT_CRY(16),
+COUT => RLOL1_CNT_CRY_0_COUT(17),
+S0 => RLOL1_CNT_S(17),
+S1 => RLOL1_CNT_S(18));
+\GENBLK2.RLOLS0_CNT_CRY_0[0]\: CCU2C 
+generic map(
+  INIT0 => X"500c",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => \RLOLS0_CNT_\,
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOLS0_CNT_\,
+B1 => RLOLS0_CNT(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_6,
+COUT => RLOLS0_CNT_CRY(0),
+S0 => RLOLS0_CNT_CRY_0_S0(0),
+S1 => RLOLS0_CNT_S(0));
+\GENBLK2.RLOLS0_CNT_CRY_0[1]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOLS0_CNT_\,
+B0 => RLOLS0_CNT(1),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOLS0_CNT_\,
+B1 => RLOLS0_CNT(2),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOLS0_CNT_CRY(0),
+COUT => RLOLS0_CNT_CRY(2),
+S0 => RLOLS0_CNT_S(1),
+S1 => RLOLS0_CNT_S(2));
+\GENBLK2.RLOLS0_CNT_CRY_0[3]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOLS0_CNT_\,
+B0 => RLOLS0_CNT(3),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOLS0_CNT_\,
+B1 => RLOLS0_CNT(4),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOLS0_CNT_CRY(2),
+COUT => RLOLS0_CNT_CRY(4),
+S0 => RLOLS0_CNT_S(3),
+S1 => RLOLS0_CNT_S(4));
+\GENBLK2.RLOLS0_CNT_CRY_0[5]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOLS0_CNT_\,
+B0 => RLOLS0_CNT(5),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOLS0_CNT_\,
+B1 => RLOLS0_CNT(6),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOLS0_CNT_CRY(4),
+COUT => RLOLS0_CNT_CRY(6),
+S0 => RLOLS0_CNT_S(5),
+S1 => RLOLS0_CNT_S(6));
+\GENBLK2.RLOLS0_CNT_CRY_0[7]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOLS0_CNT_\,
+B0 => RLOLS0_CNT(7),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOLS0_CNT_\,
+B1 => RLOLS0_CNT(8),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOLS0_CNT_CRY(6),
+COUT => RLOLS0_CNT_CRY(8),
+S0 => RLOLS0_CNT_S(7),
+S1 => RLOLS0_CNT_S(8));
+\GENBLK2.RLOLS0_CNT_CRY_0[9]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOLS0_CNT_\,
+B0 => RLOLS0_CNT(9),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOLS0_CNT_\,
+B1 => RLOLS0_CNT(10),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOLS0_CNT_CRY(8),
+COUT => RLOLS0_CNT_CRY(10),
+S0 => RLOLS0_CNT_S(9),
+S1 => RLOLS0_CNT_S(10));
+\GENBLK2.RLOLS0_CNT_CRY_0[11]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOLS0_CNT_\,
+B0 => RLOLS0_CNT(11),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOLS0_CNT_\,
+B1 => RLOLS0_CNT(12),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOLS0_CNT_CRY(10),
+COUT => RLOLS0_CNT_CRY(12),
+S0 => RLOLS0_CNT_S(11),
+S1 => RLOLS0_CNT_S(12));
+\GENBLK2.RLOLS0_CNT_CRY_0[13]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOLS0_CNT_\,
+B0 => RLOLS0_CNT(13),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOLS0_CNT_\,
+B1 => RLOLS0_CNT(14),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOLS0_CNT_CRY(12),
+COUT => RLOLS0_CNT_CRY(14),
+S0 => RLOLS0_CNT_S(13),
+S1 => RLOLS0_CNT_S(14));
+\GENBLK2.RLOLS0_CNT_CRY_0[15]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOLS0_CNT_\,
+B0 => RLOLS0_CNT(15),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOLS0_CNT_\,
+B1 => RLOLS0_CNT(16),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOLS0_CNT_CRY(14),
+COUT => RLOLS0_CNT_CRY(16),
+S0 => RLOLS0_CNT_S(15),
+S1 => RLOLS0_CNT_S(16));
+\GENBLK2.RLOLS0_CNT_S_0[17]\: CCU2C 
+generic map(
+  INIT0 => X"800a",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOLS0_CNT_\,
+B0 => RLOLS0_CNT(17),
+C0 => VCC,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => RLOLS0_CNT_CRY(16),
+COUT => RLOLS0_CNT_S_0_COUT(17),
+S0 => RLOLS0_CNT_S(17),
+S1 => RLOLS0_CNT_S_0_S1(17));
+\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[0]\: CCU2C 
+generic map(
+  INIT0 => X"500c",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => \TXR_WT_CNT_\,
+C0 => VCC,
+D0 => VCC,
+A1 => \TXR_WT_CNT_\,
+B1 => TXR_WT_CNT(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_5,
+COUT => TXR_WT_CNT_CRY(0),
+S0 => TXR_WT_CNT_CRY_0_S0(0),
+S1 => TXR_WT_CNT_S(0));
+\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[1]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \TXR_WT_CNT_\,
+B0 => TXR_WT_CNT(1),
+C0 => VCC,
+D0 => VCC,
+A1 => \TXR_WT_CNT_\,
+B1 => TXR_WT_CNT(2),
+C1 => VCC,
+D1 => VCC,
+CIN => TXR_WT_CNT_CRY(0),
+COUT => TXR_WT_CNT_CRY(2),
+S0 => TXR_WT_CNT_S(1),
+S1 => TXR_WT_CNT_S(2));
+\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[3]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \TXR_WT_CNT_\,
+B0 => TXR_WT_CNT(3),
+C0 => VCC,
+D0 => VCC,
+A1 => \TXR_WT_CNT_\,
+B1 => TXR_WT_CNT(4),
+C1 => VCC,
+D1 => VCC,
+CIN => TXR_WT_CNT_CRY(2),
+COUT => TXR_WT_CNT_CRY(4),
+S0 => TXR_WT_CNT_S(3),
+S1 => TXR_WT_CNT_S(4));
+\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[5]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \TXR_WT_CNT_\,
+B0 => TXR_WT_CNT(5),
+C0 => VCC,
+D0 => VCC,
+A1 => \TXR_WT_CNT_\,
+B1 => TXR_WT_CNT(6),
+C1 => VCC,
+D1 => VCC,
+CIN => TXR_WT_CNT_CRY(4),
+COUT => TXR_WT_CNT_CRY(6),
+S0 => TXR_WT_CNT_S(5),
+S1 => TXR_WT_CNT_S(6));
+\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[7]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \TXR_WT_CNT_\,
+B0 => TXR_WT_CNT(7),
+C0 => VCC,
+D0 => VCC,
+A1 => \TXR_WT_CNT_\,
+B1 => TXR_WT_CNT(8),
+C1 => VCC,
+D1 => VCC,
+CIN => TXR_WT_CNT_CRY(6),
+COUT => TXR_WT_CNT_CRY(8),
+S0 => TXR_WT_CNT_S(7),
+S1 => TXR_WT_CNT_S(8));
+\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[9]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \TXR_WT_CNT_\,
+B0 => TXR_WT_CNT(9),
+C0 => VCC,
+D0 => VCC,
+A1 => \TXR_WT_CNT_\,
+B1 => TXR_WT_CNT(10),
+C1 => VCC,
+D1 => VCC,
+CIN => TXR_WT_CNT_CRY(8),
+COUT => TXR_WT_CNT_CRY(10),
+S0 => TXR_WT_CNT_S(9),
+S1 => TXR_WT_CNT_S(10));
+\GENBLK1.GENBLK2.TXR_WT_CNT_S_0[11]\: CCU2C 
+generic map(
+  INIT0 => X"800a",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \TXR_WT_CNT_\,
+B0 => TXR_WT_CNT(11),
+C0 => VCC,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => TXR_WT_CNT_CRY(10),
+COUT => TXR_WT_CNT_S_0_COUT(11),
+S0 => TXR_WT_CNT_S(11),
+S1 => TXR_WT_CNT_S_0_S1(11));
+\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[0]\: CCU2C 
+generic map(
+  INIT0 => X"5003",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => RXR_WT_CNT9,
+C0 => VCC,
+D0 => VCC,
+A1 => RXR_WT_CNT9,
+B1 => RXR_WT_CNT(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_4,
+COUT => RXR_WT_CNT_CRY(0),
+S0 => RXR_WT_CNT_CRY_0_S0(0),
+S1 => RXR_WT_CNT_S(0));
+\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[1]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => RXR_WT_CNT9,
+B0 => RXR_WT_CNT(1),
+C0 => VCC,
+D0 => VCC,
+A1 => RXR_WT_CNT9,
+B1 => RXR_WT_CNT(2),
+C1 => VCC,
+D1 => VCC,
+CIN => RXR_WT_CNT_CRY(0),
+COUT => RXR_WT_CNT_CRY(2),
+S0 => RXR_WT_CNT_S(1),
+S1 => RXR_WT_CNT_S(2));
+\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[3]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => RXR_WT_CNT9,
+B0 => RXR_WT_CNT(3),
+C0 => VCC,
+D0 => VCC,
+A1 => RXR_WT_CNT9,
+B1 => RXR_WT_CNT(4),
+C1 => VCC,
+D1 => VCC,
+CIN => RXR_WT_CNT_CRY(2),
+COUT => RXR_WT_CNT_CRY(4),
+S0 => RXR_WT_CNT_S(3),
+S1 => RXR_WT_CNT_S(4));
+\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[5]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => RXR_WT_CNT9,
+B0 => RXR_WT_CNT(5),
+C0 => VCC,
+D0 => VCC,
+A1 => RXR_WT_CNT9,
+B1 => RXR_WT_CNT(6),
+C1 => VCC,
+D1 => VCC,
+CIN => RXR_WT_CNT_CRY(4),
+COUT => RXR_WT_CNT_CRY(6),
+S0 => RXR_WT_CNT_S(5),
+S1 => RXR_WT_CNT_S(6));
+\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[7]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => RXR_WT_CNT9,
+B0 => RXR_WT_CNT(7),
+C0 => VCC,
+D0 => VCC,
+A1 => RXR_WT_CNT9,
+B1 => RXR_WT_CNT(8),
+C1 => VCC,
+D1 => VCC,
+CIN => RXR_WT_CNT_CRY(6),
+COUT => RXR_WT_CNT_CRY(8),
+S0 => RXR_WT_CNT_S(7),
+S1 => RXR_WT_CNT_S(8));
+\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[9]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => RXR_WT_CNT9,
+B0 => RXR_WT_CNT(9),
+C0 => VCC,
+D0 => VCC,
+A1 => RXR_WT_CNT9,
+B1 => RXR_WT_CNT(10),
+C1 => VCC,
+D1 => VCC,
+CIN => RXR_WT_CNT_CRY(8),
+COUT => RXR_WT_CNT_CRY(10),
+S0 => RXR_WT_CNT_S(9),
+S1 => RXR_WT_CNT_S(10));
+\GENBLK2.GENBLK3.RXR_WT_CNT_S_0[11]\: CCU2C 
+generic map(
+  INIT0 => X"4005",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => RXR_WT_CNT9,
+B0 => RXR_WT_CNT(11),
+C0 => VCC,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => RXR_WT_CNT_CRY(10),
+COUT => RXR_WT_CNT_S_0_COUT(11),
+S0 => RXR_WT_CNT_S(11),
+S1 => RXR_WT_CNT_S_0_S1(11));
+\GENBLK1.PLOL_CNT_CRY_0[0]\: CCU2C 
+generic map(
+  INIT0 => X"500c",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => \PLOL_CNT_\,
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_3,
+COUT => PLOL_CNT_CRY(0),
+S0 => PLOL_CNT_CRY_0_S0(0),
+S1 => PLOL_CNT_S(0));
+\GENBLK1.PLOL_CNT_CRY_0[1]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(1),
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(2),
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(0),
+COUT => PLOL_CNT_CRY(2),
+S0 => PLOL_CNT_S(1),
+S1 => PLOL_CNT_S(2));
+\GENBLK1.PLOL_CNT_CRY_0[3]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(3),
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(4),
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(2),
+COUT => PLOL_CNT_CRY(4),
+S0 => PLOL_CNT_S(3),
+S1 => PLOL_CNT_S(4));
+\GENBLK1.PLOL_CNT_CRY_0[5]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(5),
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(6),
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(4),
+COUT => PLOL_CNT_CRY(6),
+S0 => PLOL_CNT_S(5),
+S1 => PLOL_CNT_S(6));
+\GENBLK1.PLOL_CNT_CRY_0[7]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(7),
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(8),
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(6),
+COUT => PLOL_CNT_CRY(8),
+S0 => PLOL_CNT_S(7),
+S1 => PLOL_CNT_S(8));
+\GENBLK1.PLOL_CNT_CRY_0[9]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(9),
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(10),
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(8),
+COUT => PLOL_CNT_CRY(10),
+S0 => PLOL_CNT_S(9),
+S1 => PLOL_CNT_S(10));
+\GENBLK1.PLOL_CNT_CRY_0[11]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(11),
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(12),
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(10),
+COUT => PLOL_CNT_CRY(12),
+S0 => PLOL_CNT_S(11),
+S1 => PLOL_CNT_S(12));
+\GENBLK1.PLOL_CNT_CRY_0[13]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(13),
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(14),
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(12),
+COUT => PLOL_CNT_CRY(14),
+S0 => PLOL_CNT_S(13),
+S1 => PLOL_CNT_S(14));
+\GENBLK1.PLOL_CNT_CRY_0[15]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(15),
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(16),
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(14),
+COUT => PLOL_CNT_CRY(16),
+S0 => PLOL_CNT_S(15),
+S1 => PLOL_CNT_S(16));
+\GENBLK1.PLOL_CNT_CRY_0[17]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(17),
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(18),
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(16),
+COUT => PLOL_CNT_CRY(18),
+S0 => PLOL_CNT_S(17),
+S1 => PLOL_CNT_S(18));
+\GENBLK1.PLOL_CNT_S_0[19]\: CCU2C 
+generic map(
+  INIT0 => X"800a",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(19),
+C0 => VCC,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(18),
+COUT => PLOL_CNT_S_0_COUT(19),
+S0 => PLOL_CNT_S(19),
+S1 => PLOL_CNT_S_0_S1(19));
+\UN1_GENBLK2.RLOS_DB_CNT_CRY_0_0\: CCU2C 
+generic map(
+  INIT0 => X"5003",
+  INIT1 => X"900a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => RLOS_DB_CNT(0),
+B1 => UN1_RLOS_DB_CNT_ZERO(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_2,
+COUT => RLOS_DB_CNT_CRY_0,
+S0 => RLOS_DB_CNT_CRY_0_0_S0,
+S1 => RLOS_DB_CNT_CRY_0_0_S1);
+\UN1_GENBLK2.RLOS_DB_CNT_CRY_1_0\: CCU2C 
+generic map(
+  INIT0 => X"e101",
+  INIT1 => X"e101",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RLOS_DB_CNT_ZERO(0),
+B0 => RLOS_P2,
+C0 => RLOS_DB_CNT(1),
+D0 => VCC,
+A1 => UN1_RLOS_DB_CNT_ZERO(0),
+B1 => RLOS_P2,
+C1 => RLOS_DB_CNT(2),
+D1 => VCC,
+CIN => RLOS_DB_CNT_CRY_0,
+COUT => RLOS_DB_CNT_CRY_2,
+S0 => RLOS_DB_CNT_CRY_1_0_S0,
+S1 => RLOS_DB_CNT_CRY_1_0_S1);
+\UN1_GENBLK2.RLOS_DB_CNT_S_3_0\: CCU2C 
+generic map(
+  INIT0 => X"a90a",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => RLOS_DB_CNT(3),
+B0 => RLOS_P2,
+C0 => UN1_RLOS_DB_CNT_ZERO(0),
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => RLOS_DB_CNT_CRY_2,
+COUT => RLOS_DB_CNT_S_3_0_COUT,
+S0 => RLOS_DB_CNT_S_3_0_S0,
+S1 => RLOS_DB_CNT_S_3_0_S1);
+\UN1_GENBLK2.RLOL_DB_CNT_CRY_0_0\: CCU2C 
+generic map(
+  INIT0 => X"5003",
+  INIT1 => X"900a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => RLOL_DB_CNT(0),
+B1 => UN1_RLOL_DB_CNT_ZERO(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_1,
+COUT => RLOL_DB_CNT_CRY_0,
+S0 => RLOL_DB_CNT_CRY_0_0_S0,
+S1 => RLOL_DB_CNT_CRY_0_0_S1);
+\UN1_GENBLK2.RLOL_DB_CNT_CRY_1_0\: CCU2C 
+generic map(
+  INIT0 => X"e101",
+  INIT1 => X"e101",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RLOL_DB_CNT_ZERO(0),
+B0 => RLOL_P2,
+C0 => RLOL_DB_CNT(1),
+D0 => VCC,
+A1 => UN1_RLOL_DB_CNT_ZERO(0),
+B1 => RLOL_P2,
+C1 => RLOL_DB_CNT(2),
+D1 => VCC,
+CIN => RLOL_DB_CNT_CRY_0,
+COUT => RLOL_DB_CNT_CRY_2,
+S0 => RLOL_DB_CNT_CRY_1_0_S0,
+S1 => RLOL_DB_CNT_CRY_1_0_S1);
+\UN1_GENBLK2.RLOL_DB_CNT_S_3_0\: CCU2C 
+generic map(
+  INIT0 => X"a90a",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => RLOL_DB_CNT(3),
+B0 => RLOL_P2,
+C0 => UN1_RLOL_DB_CNT_ZERO(0),
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL_DB_CNT_CRY_2,
+COUT => RLOL_DB_CNT_S_3_0_COUT,
+S0 => RLOL_DB_CNT_S_3_0_S0,
+S1 => RLOL_DB_CNT_S_3_0_S1);
+RXSDR_APPD_4 <= RXSDR_APPD;
+TXSR_APPD_4 <= TXSR_APPD;
+VCC_0: VHI port map (
+Z => VCC);
+II_GND: VLO port map (
+Z => GND);
+rsl_tx_pcs_rst_c <= RSL_TX_PCS_RST_C_4;
+rsl_rx_serdes_rst_c <= RSL_RX_SERDES_RST_C_5;
+rsl_serdes_rst_dual_c <= RSL_SERDES_RST_DUAL_C_6;
+rsl_tx_serdes_rst_c <= RSL_TX_SERDES_RST_C_7;
+rsl_tx_rdy <= RSL_TX_RDY_8;
+rsl_rx_rdy <= RSL_RX_RDY_9;
+rsl_rx_pcs_rst_c <= RSL_RX_PCS_RST_C_10;
+end beh;
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library synplify;
+use synplify.components.all;
+library pmi;
+use pmi.pmi_components.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity sgmii_ecp5sll_core_Z1_layer1 is
+port(
+tx_pclk :  in std_logic;
+sli_rst :  in std_logic;
+pll_refclki :  in std_logic;
+pll_lock_i :  out std_logic);
+end sgmii_ecp5sll_core_Z1_layer1;
+
+architecture beh of sgmii_ecp5sll_core_Z1_layer1 is
+signal PHB_CNT : std_logic_vector(2 downto 0);
+signal PHB_CNT_I : std_logic_vector(2 downto 0);
+signal RCOUNT : std_logic_vector(15 downto 0);
+signal PCOUNT : std_logic_vector(21 downto 0);
+signal UN1_PCOUNT_DIFF_I : std_logic_vector(0 to 0);
+signal SLL_STATE : std_logic_vector(1 downto 0);
+signal SLL_STATE_QN : std_logic_vector(1 downto 0);
+signal RHB_WAIT_CNT_S : std_logic_vector(7 downto 0);
+signal RHB_WAIT_CNT : std_logic_vector(7 downto 0);
+signal RHB_WAIT_CNT_QN : std_logic_vector(7 downto 0);
+signal RCOUNT_S : std_logic_vector(15 downto 0);
+signal RCOUNT_QN : std_logic_vector(15 downto 0);
+signal PHB_CNT_QN : std_logic_vector(2 downto 0);
+signal PHB_CNT_RNO : std_logic_vector(2 downto 1);
+signal PCOUNT_S : std_logic_vector(21 downto 0);
+signal PCOUNT_QN : std_logic_vector(21 downto 0);
+signal PCOUNT_DIFF_QN : std_logic_vector(21 downto 0);
+signal RDIFF_COMP_LOCK : std_logic_vector(2 to 2);
+signal RDIFF_COMP_LOCK_QN : std_logic_vector(2 to 2);
+signal UN1_PCOUNT_DIFF : std_logic_vector(0 to 0);
+signal PCOUNT_CRY : std_logic_vector(20 downto 0);
+signal PCOUNT_CRY_0_S0 : std_logic_vector(0 to 0);
+signal PCOUNT_S_0_COUT : std_logic_vector(21 to 21);
+signal PCOUNT_S_0_S1 : std_logic_vector(21 to 21);
+signal RCOUNT_CRY : std_logic_vector(14 downto 0);
+signal RCOUNT_CRY_0_S0 : std_logic_vector(0 to 0);
+signal RCOUNT_S_0_COUT : std_logic_vector(15 to 15);
+signal RCOUNT_S_0_S1 : std_logic_vector(15 to 15);
+signal RHB_WAIT_CNT_CRY : std_logic_vector(6 downto 0);
+signal RHB_WAIT_CNT_CRY_0_S0 : std_logic_vector(0 to 0);
+signal RHB_WAIT_CNT_S_0_COUT : std_logic_vector(7 to 7);
+signal RHB_WAIT_CNT_S_0_S1 : std_logic_vector(7 to 7);
+signal PLL_LOCK : std_logic ;
+signal RTC_CTRL4_0_A3_1 : std_logic ;
+signal UN13_LOCK_20 : std_logic ;
+signal PPUL_SYNC_P2 : std_logic ;
+signal PPUL_SYNC_P1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_20 : std_logic ;
+signal UN13_LOCK_19 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_19 : std_logic ;
+signal UN13_LOCK_18 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_18 : std_logic ;
+signal UN13_LOCK_17 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_17_0_RNO : std_logic ;
+signal UN13_LOCK_16 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_16 : std_logic ;
+signal UN13_LOCK_15 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_15 : std_logic ;
+signal UN13_LOCK_14 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_14 : std_logic ;
+signal UN13_LOCK_13 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_13 : std_logic ;
+signal UN13_LOCK_12 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_12 : std_logic ;
+signal UN13_LOCK_11 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_11 : std_logic ;
+signal UN13_LOCK_10 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_10 : std_logic ;
+signal UN13_LOCK_9 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_9 : std_logic ;
+signal UN13_LOCK_8 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_8 : std_logic ;
+signal UN13_LOCK_7 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_7 : std_logic ;
+signal UN13_LOCK_6 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_6 : std_logic ;
+signal UN13_LOCK_5 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_5 : std_logic ;
+signal UN13_LOCK_4 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_4 : std_logic ;
+signal UN13_LOCK_3 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_3 : std_logic ;
+signal UN13_LOCK_2 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_2 : std_logic ;
+signal UN13_LOCK_1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_1 : std_logic ;
+signal UN13_LOCK_21 : std_logic ;
+signal PPUL_SYNC_P3 : std_logic ;
+signal N_7 : std_logic ;
+signal UN13_LOCK_0 : std_logic ;
+signal RTC_CTRL4 : std_logic ;
+signal RTC_CTRL : std_logic ;
+signal VCC : std_logic ;
+signal N_2085_0 : std_logic ;
+signal UNLOCK_5 : std_logic ;
+signal UNLOCK_1_SQMUXA_I : std_logic ;
+signal UNLOCK : std_logic ;
+signal UNLOCK_QN : std_logic ;
+signal N_95_I : std_logic ;
+signal N_97_I : std_logic ;
+signal RTC_PUL : std_logic ;
+signal RTC_PUL_P1 : std_logic ;
+signal RTC_PUL_P1_QN : std_logic ;
+signal RTC_PUL5 : std_logic ;
+signal RTC_PUL_QN : std_logic ;
+signal RTC_CTRL_QN : std_logic ;
+signal RSTAT_PCLK_2 : std_logic ;
+signal RSTAT_PCLK : std_logic ;
+signal RSTAT_PCLK_QN : std_logic ;
+signal RHB_SYNC_P1 : std_logic ;
+signal RHB_SYNC_P2 : std_logic ;
+signal RHB_SYNC_P2_QN : std_logic ;
+signal RHB_SYNC : std_logic ;
+signal RHB_SYNC_P1_QN : std_logic ;
+signal PPUL_SYNC_P3_QN : std_logic ;
+signal PPUL_SYNC_P2_QN : std_logic ;
+signal PPUL_SYNC : std_logic ;
+signal PPUL_SYNC_P1_QN : std_logic ;
+signal N_53_I : std_logic ;
+signal PLL_LOCK_QN : std_logic ;
+signal PHB : std_logic ;
+signal PHB_QN : std_logic ;
+signal PDIFF_SYNC : std_logic ;
+signal PDIFF_SYNC_P1 : std_logic ;
+signal PDIFF_SYNC_P1_QN : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_1_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_1_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_3_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_3_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_5_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_5_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_7_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_7_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_9_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_9_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_11_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_11_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_13_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_13_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_15_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_15_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_17_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_17_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_19_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_19_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_S_21_0_S0 : std_logic ;
+signal LOCK_5 : std_logic ;
+signal LOCK_1_SQMUXA_I : std_logic ;
+signal LOCK : std_logic ;
+signal LOCK_QN : std_logic ;
+signal N_98 : std_logic ;
+signal RTC_PUL5_0_O3 : std_logic ;
+signal RTC_PUL5_0_A3_6 : std_logic ;
+signal RTC_PUL5_0_A3_7 : std_logic ;
+signal UN1_RCOUNT_1_0_A3 : std_logic ;
+signal RHB_WAIT_CNT12 : std_logic ;
+signal UN1_RHB_WAIT_CNT_4 : std_logic ;
+signal UN1_RHB_WAIT_CNT_5 : std_logic ;
+signal N_99 : std_logic ;
+signal RTC_CTRL4_0_A3_12_4 : std_logic ;
+signal RTC_CTRL4_0_A3_12_5 : std_logic ;
+signal RTC_CTRL4_10 : std_logic ;
+signal UN1_RCOUNT_1_0_A3_1 : std_logic ;
+signal N_6 : std_logic ;
+signal RTC_PUL5_0_A3_5 : std_logic ;
+signal N_8 : std_logic ;
+signal UN13_UNLOCK_CRY_21 : std_logic ;
+signal UN13_LOCK_CRY_21_I : std_logic ;
+signal \RHB_WAIT_CNT_\ : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_0_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_0_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_2 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_4 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_6 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_8 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_10 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_12 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_14 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_16 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_18 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_20 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_S_21_0_COUT : std_logic ;
+signal UN1_PCOUNT_DIFF_1_S_21_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_0 : std_logic ;
+signal UN13_LOCK_CRY_0_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_0_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_2 : std_logic ;
+signal UN13_LOCK_CRY_1_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_1_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_4 : std_logic ;
+signal UN13_LOCK_CRY_3_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_3_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_6 : std_logic ;
+signal UN13_LOCK_CRY_5_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_5_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_8 : std_logic ;
+signal UN13_LOCK_CRY_7_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_7_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_10 : std_logic ;
+signal UN13_LOCK_CRY_9_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_9_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_12 : std_logic ;
+signal UN13_LOCK_CRY_11_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_11_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_14 : std_logic ;
+signal UN13_LOCK_CRY_13_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_13_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_16 : std_logic ;
+signal UN13_LOCK_CRY_15_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_15_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_18 : std_logic ;
+signal UN13_LOCK_CRY_17_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_17_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_20 : std_logic ;
+signal UN13_LOCK_CRY_19_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_19_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_21_0_COUT : std_logic ;
+signal UN13_LOCK_CRY_21_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_0 : std_logic ;
+signal UN13_UNLOCK_CRY_0_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_0_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_2 : std_logic ;
+signal UN13_UNLOCK_CRY_1_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_1_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_4 : std_logic ;
+signal UN13_UNLOCK_CRY_3_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_3_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_6 : std_logic ;
+signal UN13_UNLOCK_CRY_5_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_5_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_8 : std_logic ;
+signal UN13_UNLOCK_CRY_7_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_7_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_10 : std_logic ;
+signal UN13_UNLOCK_CRY_9_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_9_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_12 : std_logic ;
+signal UN13_UNLOCK_CRY_11_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_11_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_14 : std_logic ;
+signal UN13_UNLOCK_CRY_13_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_13_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_16 : std_logic ;
+signal UN13_UNLOCK_CRY_15_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_15_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_18 : std_logic ;
+signal UN13_UNLOCK_CRY_17_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_17_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_20 : std_logic ;
+signal UN13_UNLOCK_CRY_19_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_19_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_21_0_COUT : std_logic ;
+signal UN13_UNLOCK_CRY_21_0_S0 : std_logic ;
+signal N_21 : std_logic ;
+signal N_20 : std_logic ;
+signal N_19 : std_logic ;
+signal N_18 : std_logic ;
+signal N_14 : std_logic ;
+signal GND : std_logic ;
+signal N_1 : std_logic ;
+signal N_2 : std_logic ;
+signal N_3 : std_logic ;
+signal N_4 : std_logic ;
+signal N_5 : std_logic ;
+signal N_9 : std_logic ;
+component sync_0s
+port(
+phb :  in std_logic;
+rhb_sync :  out std_logic;
+sli_rst :  in std_logic;
+pll_refclki :  in std_logic  );
+end component;
+component sync_0s_6
+port(
+rtc_pul :  in std_logic;
+ppul_sync :  out std_logic;
+sli_rst :  in std_logic;
+tx_pclk :  in std_logic  );
+end component;
+component sync_0s_0
+port(
+ppul_sync :  in std_logic;
+pdiff_sync :  out std_logic;
+sli_rst :  in std_logic;
+pll_refclki :  in std_logic  );
+end component;
+begin
+PHB_RNO: INV port map (
+A => PHB_CNT(2),
+Z => PHB_CNT_I(2));
+\PHB_CNT_RNO[0]\: INV port map (
+A => PHB_CNT(0),
+Z => PHB_CNT_I(0));
+PLL_LOCK_RNI6JK9: INV port map (
+A => PLL_LOCK,
+Z => pll_lock_i);
+RTC_CTRL4_0_A3_RNO: LUT4 
+generic map(
+  init => X"2000"
+)
+port map (
+A => RCOUNT(2),
+B => RCOUNT(0),
+C => RCOUNT(5),
+D => RCOUNT(4),
+Z => RTC_CTRL4_0_A3_1);
+UN1_PCOUNT_DIFF_1_CRY_19_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_20,
+B => PCOUNT(20),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_20);
+UN1_PCOUNT_DIFF_1_CRY_19_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_19,
+B => PCOUNT(19),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_19);
+UN1_PCOUNT_DIFF_1_CRY_17_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_18,
+B => PCOUNT(18),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_18);
+UN1_PCOUNT_DIFF_1_CRY_17_0_RNO_Z477: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_17,
+B => PCOUNT(17),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_CRY_17_0_RNO);
+UN1_PCOUNT_DIFF_1_CRY_15_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_16,
+B => PCOUNT(16),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_16);
+UN1_PCOUNT_DIFF_1_CRY_15_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_15,
+B => PCOUNT(15),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_15);
+UN1_PCOUNT_DIFF_1_CRY_13_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_14,
+B => PCOUNT(14),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_14);
+UN1_PCOUNT_DIFF_1_CRY_13_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_13,
+B => PCOUNT(13),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_13);
+UN1_PCOUNT_DIFF_1_CRY_11_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_12,
+B => PCOUNT(12),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_12);
+UN1_PCOUNT_DIFF_1_CRY_11_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_11,
+B => PCOUNT(11),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_11);
+UN1_PCOUNT_DIFF_1_CRY_9_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_10,
+B => PCOUNT(10),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_10);
+UN1_PCOUNT_DIFF_1_CRY_9_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_9,
+B => PCOUNT(9),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_9);
+UN1_PCOUNT_DIFF_1_CRY_7_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_8,
+B => PCOUNT(8),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_8);
+UN1_PCOUNT_DIFF_1_CRY_7_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_7,
+B => PCOUNT(7),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_7);
+UN1_PCOUNT_DIFF_1_CRY_5_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_6,
+B => PCOUNT(6),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_6);
+UN1_PCOUNT_DIFF_1_CRY_5_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_5,
+B => PCOUNT(5),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_5);
+UN1_PCOUNT_DIFF_1_CRY_3_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_4,
+B => PCOUNT(4),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_4);
+UN1_PCOUNT_DIFF_1_CRY_3_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_3,
+B => PCOUNT(3),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_3);
+UN1_PCOUNT_DIFF_1_CRY_1_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_2,
+B => PCOUNT(2),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_2);
+UN1_PCOUNT_DIFF_1_CRY_1_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_1,
+B => PCOUNT(1),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_1);
+PPUL_SYNC_P3_RNIU65C: LUT4 
+generic map(
+  init => X"2F20"
+)
+port map (
+A => UN13_LOCK_21,
+B => PPUL_SYNC_P3,
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => N_7);
+\PCOUNT_DIFF_RNO[0]\: LUT4 
+generic map(
+  init => X"FD20"
+)
+port map (
+A => PPUL_SYNC_P1,
+B => PPUL_SYNC_P2,
+C => PCOUNT(0),
+D => UN13_LOCK_0,
+Z => UN1_PCOUNT_DIFF_I(0));
+RTC_CTRL_0: LUT4 
+generic map(
+  init => X"EEEE"
+)
+port map (
+A => RTC_CTRL4,
+B => RTC_CTRL,
+C => VCC,
+D => VCC,
+Z => N_2085_0);
+UNLOCK_REG_Z498: FD1P3DX port map (
+D => UNLOCK_5,
+SP => UNLOCK_1_SQMUXA_I,
+CK => pll_refclki,
+CD => sli_rst,
+Q => UNLOCK);
+\SLL_STATE[0]_REG_Z500\: FD1S3DX port map (
+D => N_95_I,
+CK => pll_refclki,
+CD => sli_rst,
+Q => SLL_STATE(0));
+\SLL_STATE[1]_REG_Z502\: FD1S3DX port map (
+D => N_97_I,
+CK => pll_refclki,
+CD => sli_rst,
+Q => SLL_STATE(1));
+RTC_PUL_P1_REG_Z504: FD1S3DX port map (
+D => RTC_PUL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RTC_PUL_P1);
+RTC_PUL_REG_Z506: FD1P3DX port map (
+D => RTC_PUL5,
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RTC_PUL);
+RTC_CTRL_REG_Z508: FD1S3DX port map (
+D => N_2085_0,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RTC_CTRL);
+RSTAT_PCLK_REG_Z510: FD1P3DX port map (
+D => RSTAT_PCLK_2,
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RSTAT_PCLK);
+\RHB_WAIT_CNT[0]_REG_Z512\: FD1P3DX port map (
+D => RHB_WAIT_CNT_S(0),
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_WAIT_CNT(0));
+\RHB_WAIT_CNT[1]_REG_Z514\: FD1P3DX port map (
+D => RHB_WAIT_CNT_S(1),
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_WAIT_CNT(1));
+\RHB_WAIT_CNT[2]_REG_Z516\: FD1P3DX port map (
+D => RHB_WAIT_CNT_S(2),
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_WAIT_CNT(2));
+\RHB_WAIT_CNT[3]_REG_Z518\: FD1P3DX port map (
+D => RHB_WAIT_CNT_S(3),
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_WAIT_CNT(3));
+\RHB_WAIT_CNT[4]_REG_Z520\: FD1P3DX port map (
+D => RHB_WAIT_CNT_S(4),
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_WAIT_CNT(4));
+\RHB_WAIT_CNT[5]_REG_Z522\: FD1P3DX port map (
+D => RHB_WAIT_CNT_S(5),
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_WAIT_CNT(5));
+\RHB_WAIT_CNT[6]_REG_Z524\: FD1P3DX port map (
+D => RHB_WAIT_CNT_S(6),
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_WAIT_CNT(6));
+\RHB_WAIT_CNT[7]_REG_Z526\: FD1P3DX port map (
+D => RHB_WAIT_CNT_S(7),
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_WAIT_CNT(7));
+RHB_SYNC_P2_REG_Z528: FD1S3DX port map (
+D => RHB_SYNC_P1,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_SYNC_P2);
+RHB_SYNC_P1_REG_Z530: FD1S3DX port map (
+D => RHB_SYNC,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_SYNC_P1);
+\RCOUNT[0]_REG_Z532\: FD1S3DX port map (
+D => RCOUNT_S(0),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(0));
+\RCOUNT[1]_REG_Z534\: FD1S3DX port map (
+D => RCOUNT_S(1),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(1));
+\RCOUNT[2]_REG_Z536\: FD1S3DX port map (
+D => RCOUNT_S(2),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(2));
+\RCOUNT[3]_REG_Z538\: FD1S3DX port map (
+D => RCOUNT_S(3),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(3));
+\RCOUNT[4]_REG_Z540\: FD1S3DX port map (
+D => RCOUNT_S(4),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(4));
+\RCOUNT[5]_REG_Z542\: FD1S3DX port map (
+D => RCOUNT_S(5),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(5));
+\RCOUNT[6]_REG_Z544\: FD1S3DX port map (
+D => RCOUNT_S(6),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(6));
+\RCOUNT[7]_REG_Z546\: FD1S3DX port map (
+D => RCOUNT_S(7),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(7));
+\RCOUNT[8]_REG_Z548\: FD1S3DX port map (
+D => RCOUNT_S(8),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(8));
+\RCOUNT[9]_REG_Z550\: FD1S3DX port map (
+D => RCOUNT_S(9),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(9));
+\RCOUNT[10]_REG_Z552\: FD1S3DX port map (
+D => RCOUNT_S(10),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(10));
+\RCOUNT[11]_REG_Z554\: FD1S3DX port map (
+D => RCOUNT_S(11),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(11));
+\RCOUNT[12]_REG_Z556\: FD1S3DX port map (
+D => RCOUNT_S(12),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(12));
+\RCOUNT[13]_REG_Z558\: FD1S3DX port map (
+D => RCOUNT_S(13),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(13));
+\RCOUNT[14]_REG_Z560\: FD1S3DX port map (
+D => RCOUNT_S(14),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(14));
+\RCOUNT[15]_REG_Z562\: FD1S3DX port map (
+D => RCOUNT_S(15),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(15));
+PPUL_SYNC_P3_REG_Z564: FD1S3DX port map (
+D => PPUL_SYNC_P2,
+CK => tx_pclk,
+CD => sli_rst,
+Q => PPUL_SYNC_P3);
+PPUL_SYNC_P2_REG_Z566: FD1S3DX port map (
+D => PPUL_SYNC_P1,
+CK => tx_pclk,
+CD => sli_rst,
+Q => PPUL_SYNC_P2);
+PPUL_SYNC_P1_REG_Z568: FD1S3DX port map (
+D => PPUL_SYNC,
+CK => tx_pclk,
+CD => sli_rst,
+Q => PPUL_SYNC_P1);
+PLL_LOCK_REG_Z570: FD1S3DX port map (
+D => N_53_I,
+CK => pll_refclki,
+CD => sli_rst,
+Q => PLL_LOCK);
+\PHB_CNT[0]_REG_Z572\: FD1S3DX port map (
+D => PHB_CNT_I(0),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PHB_CNT(0));
+\PHB_CNT[1]_REG_Z574\: FD1S3DX port map (
+D => PHB_CNT_RNO(1),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PHB_CNT(1));
+\PHB_CNT[2]_REG_Z576\: FD1S3DX port map (
+D => PHB_CNT_RNO(2),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PHB_CNT(2));
+PHB_REG_Z578: FD1S3DX port map (
+D => PHB_CNT_I(2),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PHB);
+PDIFF_SYNC_P1_REG_Z580: FD1S3DX port map (
+D => PDIFF_SYNC,
+CK => pll_refclki,
+CD => sli_rst,
+Q => PDIFF_SYNC_P1);
+\PCOUNT[0]_REG_Z582\: FD1S3DX port map (
+D => PCOUNT_S(0),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(0));
+\PCOUNT_DIFF[0]_REG_Z584\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_I(0),
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_0);
+\PCOUNT[1]_REG_Z586\: FD1S3DX port map (
+D => PCOUNT_S(1),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(1));
+\PCOUNT_DIFF[1]_REG_Z588\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_1_0_S0,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_1);
+\PCOUNT_DIFF[2]_REG_Z590\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_1_0_S1,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_2);
+\PCOUNT[2]_REG_Z592\: FD1S3DX port map (
+D => PCOUNT_S(2),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(2));
+\PCOUNT_DIFF[3]_REG_Z594\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_3_0_S0,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_3);
+\PCOUNT[3]_REG_Z596\: FD1S3DX port map (
+D => PCOUNT_S(3),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(3));
+\PCOUNT_DIFF[4]_REG_Z598\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_3_0_S1,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_4);
+\PCOUNT[4]_REG_Z600\: FD1S3DX port map (
+D => PCOUNT_S(4),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(4));
+\PCOUNT_DIFF[5]_REG_Z602\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_5_0_S0,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_5);
+\PCOUNT[5]_REG_Z604\: FD1S3DX port map (
+D => PCOUNT_S(5),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(5));
+\PCOUNT[6]_REG_Z606\: FD1S3DX port map (
+D => PCOUNT_S(6),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(6));
+\PCOUNT_DIFF[6]_REG_Z608\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_5_0_S1,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_6);
+\PCOUNT[7]_REG_Z610\: FD1S3DX port map (
+D => PCOUNT_S(7),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(7));
+\PCOUNT_DIFF[7]_REG_Z612\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_7_0_S0,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_7);
+\PCOUNT[8]_REG_Z614\: FD1S3DX port map (
+D => PCOUNT_S(8),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(8));
+\PCOUNT_DIFF[8]_REG_Z616\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_7_0_S1,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_8);
+\PCOUNT_DIFF[9]_REG_Z618\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_9_0_S0,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_9);
+\PCOUNT[9]_REG_Z620\: FD1S3DX port map (
+D => PCOUNT_S(9),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(9));
+\PCOUNT[10]_REG_Z622\: FD1S3DX port map (
+D => PCOUNT_S(10),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(10));
+\PCOUNT_DIFF[10]_REG_Z624\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_9_0_S1,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_10);
+\PCOUNT_DIFF[11]_REG_Z626\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_11_0_S0,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_11);
+\PCOUNT[11]_REG_Z628\: FD1S3DX port map (
+D => PCOUNT_S(11),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(11));
+\PCOUNT[12]_REG_Z630\: FD1S3DX port map (
+D => PCOUNT_S(12),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(12));
+\PCOUNT_DIFF[12]_REG_Z632\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_11_0_S1,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_12);
+\PCOUNT_DIFF[13]_REG_Z634\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_13_0_S0,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_13);
+\PCOUNT[13]_REG_Z636\: FD1S3DX port map (
+D => PCOUNT_S(13),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(13));
+\PCOUNT_DIFF[14]_REG_Z638\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_13_0_S1,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_14);
+\PCOUNT[14]_REG_Z640\: FD1S3DX port map (
+D => PCOUNT_S(14),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(14));
+\PCOUNT[15]_REG_Z642\: FD1S3DX port map (
+D => PCOUNT_S(15),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(15));
+\PCOUNT_DIFF[15]_REG_Z644\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_15_0_S0,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_15);
+\PCOUNT[16]_REG_Z646\: FD1S3DX port map (
+D => PCOUNT_S(16),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(16));
+\PCOUNT_DIFF[16]_REG_Z648\: FD1P3DX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_15_0_S1,
+SP => N_7,
+CK => tx_pclk,
+CD => sli_rst,
+Q => UN13_LOCK_16);
+\PCOUNT_DIFF[17]_REG_Z650\: FD1P3DX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_17_0_S0,
+SP => N_7,
+CK => tx_pclk,
+CD => sli_rst,
+Q => UN13_LOCK_17);
+\PCOUNT[17]_REG_Z652\: FD1S3DX port map (
+D => PCOUNT_S(17),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(17));
+\PCOUNT_DIFF[18]_REG_Z654\: FD1P3DX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_17_0_S1,
+SP => N_7,
+CK => tx_pclk,
+CD => sli_rst,
+Q => UN13_LOCK_18);
+\PCOUNT[18]_REG_Z656\: FD1S3DX port map (
+D => PCOUNT_S(18),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(18));
+\PCOUNT[19]_REG_Z658\: FD1S3DX port map (
+D => PCOUNT_S(19),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(19));
+\PCOUNT_DIFF[19]_REG_Z660\: FD1P3DX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_19_0_S0,
+SP => N_7,
+CK => tx_pclk,
+CD => sli_rst,
+Q => UN13_LOCK_19);
+\PCOUNT[20]_REG_Z662\: FD1S3DX port map (
+D => PCOUNT_S(20),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(20));
+\PCOUNT_DIFF[20]_REG_Z664\: FD1P3DX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_19_0_S1,
+SP => N_7,
+CK => tx_pclk,
+CD => sli_rst,
+Q => UN13_LOCK_20);
+\PCOUNT_DIFF[21]_REG_Z666\: FD1P3DX port map (
+D => UN1_PCOUNT_DIFF_1_S_21_0_S0,
+SP => N_7,
+CK => tx_pclk,
+CD => sli_rst,
+Q => UN13_LOCK_21);
+\PCOUNT[21]_REG_Z668\: FD1S3DX port map (
+D => PCOUNT_S(21),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(21));
+LOCK_REG_Z670: FD1P3DX port map (
+D => LOCK_5,
+SP => LOCK_1_SQMUXA_I,
+CK => pll_refclki,
+CD => sli_rst,
+Q => LOCK);
+\GENBLK5.RDIFF_COMP_LOCK[2]_REG_Z672\: FD1S3DX port map (
+D => VCC,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RDIFF_COMP_LOCK(2));
+\SLL_STATE_RNO[0]\: LUT4 
+generic map(
+  init => X"E050"
+)
+port map (
+A => N_98,
+B => LOCK,
+C => RSTAT_PCLK,
+D => SLL_STATE(0),
+Z => N_95_I);
+RTC_PUL5_0_0: LUT4 
+generic map(
+  init => X"FF80"
+)
+port map (
+A => RTC_PUL5_0_O3,
+B => RTC_PUL5_0_A3_6,
+C => RTC_PUL5_0_A3_7,
+D => UN1_RCOUNT_1_0_A3,
+Z => RTC_PUL5);
+RSTAT_PCLK_2_IV: LUT4 
+generic map(
+  init => X"AEEE"
+)
+port map (
+A => RHB_WAIT_CNT12,
+B => RSTAT_PCLK,
+C => UN1_RHB_WAIT_CNT_4,
+D => UN1_RHB_WAIT_CNT_5,
+Z => RSTAT_PCLK_2);
+\SLL_STATE_RNO[1]\: LUT4 
+generic map(
+  init => X"8088"
+)
+port map (
+A => N_99,
+B => RSTAT_PCLK,
+C => SLL_STATE(1),
+D => UNLOCK,
+Z => N_97_I);
+RTC_CTRL4_0_A3: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RTC_CTRL4_0_A3_1,
+B => RTC_CTRL4_0_A3_12_4,
+C => RTC_CTRL4_0_A3_12_5,
+D => RTC_CTRL4_10,
+Z => RTC_CTRL4);
+UN1_RCOUNT_1_0_A3_Z678: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RTC_CTRL4_0_A3_12_4,
+B => RTC_CTRL4_0_A3_12_5,
+C => RTC_CTRL4_10,
+D => UN1_RCOUNT_1_0_A3_1,
+Z => UN1_RCOUNT_1_0_A3);
+LOCK_1_SQMUXA_I_Z679: LUT4 
+generic map(
+  init => X"7575"
+)
+port map (
+A => LOCK,
+B => PDIFF_SYNC,
+C => PDIFF_SYNC_P1,
+D => VCC,
+Z => LOCK_1_SQMUXA_I);
+UNLOCK_1_SQMUXA_I_Z680: LUT4 
+generic map(
+  init => X"4F4F"
+)
+port map (
+A => PDIFF_SYNC,
+B => PDIFF_SYNC_P1,
+C => UNLOCK,
+D => VCC,
+Z => UNLOCK_1_SQMUXA_I);
+RTC_PUL5_0_O3_Z681: LUT4 
+generic map(
+  init => X"AAAB"
+)
+port map (
+A => N_6,
+B => RCOUNT(1),
+C => RCOUNT(2),
+D => RCOUNT(3),
+Z => RTC_PUL5_0_O3);
+RTC_PUL5_0_A3_7_Z682: LUT4 
+generic map(
+  init => X"1010"
+)
+port map (
+A => RCOUNT(7),
+B => RCOUNT(8),
+C => RTC_PUL5_0_A3_5,
+D => VCC,
+Z => RTC_PUL5_0_A3_7);
+\SLL_STATE_NS_I_M4[1]\: LUT4 
+generic map(
+  init => X"EF20"
+)
+port map (
+A => LOCK,
+B => RTC_PUL,
+C => RTC_PUL_P1,
+D => SLL_STATE(1),
+Z => N_99);
+PLL_LOCK_RNO: LUT4 
+generic map(
+  init => X"8888"
+)
+port map (
+A => SLL_STATE(0),
+B => SLL_STATE(1),
+C => VCC,
+D => VCC,
+Z => N_53_I);
+\PHB_CNT_RNO[2]_Z685\: LUT4 
+generic map(
+  init => X"7878"
+)
+port map (
+A => PHB_CNT(0),
+B => PHB_CNT(1),
+C => PHB_CNT(2),
+D => VCC,
+Z => PHB_CNT_RNO(2));
+\SLL_STATE_NS_I_O4[0]\: LUT4 
+generic map(
+  init => X"BFBF"
+)
+port map (
+A => RTC_PUL,
+B => RTC_PUL_P1,
+C => SLL_STATE(1),
+D => VCC,
+Z => N_98);
+RTC_CTRL4_0_A3_10: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RCOUNT(1),
+B => RCOUNT(3),
+C => RCOUNT(6),
+D => RCOUNT(15),
+Z => RTC_CTRL4_10);
+UN1_RHB_WAIT_CNT_4_Z688: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RHB_WAIT_CNT(4),
+B => RHB_WAIT_CNT(5),
+C => RHB_WAIT_CNT(6),
+D => RHB_WAIT_CNT(7),
+Z => UN1_RHB_WAIT_CNT_4);
+UN1_RHB_WAIT_CNT_5_Z689: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RHB_WAIT_CNT(0),
+B => RHB_WAIT_CNT(1),
+C => RHB_WAIT_CNT(2),
+D => RHB_WAIT_CNT(3),
+Z => UN1_RHB_WAIT_CNT_5);
+RTC_CTRL4_0_A3_12_4_Z690: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RCOUNT(11),
+B => RCOUNT(12),
+C => RCOUNT(13),
+D => RCOUNT(14),
+Z => RTC_CTRL4_0_A3_12_4);
+RTC_CTRL4_0_A3_12_5_Z691: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RCOUNT(7),
+B => RCOUNT(8),
+C => RCOUNT(9),
+D => RCOUNT(10),
+Z => RTC_CTRL4_0_A3_12_5);
+RTC_PUL5_0_A3_5_Z692: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RCOUNT(6),
+B => RCOUNT(13),
+C => RCOUNT(14),
+D => RCOUNT(15),
+Z => RTC_PUL5_0_A3_5);
+RTC_PUL5_0_A3_6_Z693: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RCOUNT(9),
+B => RCOUNT(10),
+C => RCOUNT(11),
+D => RCOUNT(12),
+Z => RTC_PUL5_0_A3_6);
+PCOUNT10_0_O3: LUT4 
+generic map(
+  init => X"DDDD"
+)
+port map (
+A => PPUL_SYNC_P1,
+B => PPUL_SYNC_P2,
+C => VCC,
+D => VCC,
+Z => N_8);
+\PHB_CNT_RNO[1]_Z695\: LUT4 
+generic map(
+  init => X"6666"
+)
+port map (
+A => PHB_CNT(0),
+B => PHB_CNT(1),
+C => VCC,
+D => VCC,
+Z => PHB_CNT_RNO(1));
+RTC_CTRL4_0_O3: LUT4 
+generic map(
+  init => X"7777"
+)
+port map (
+A => RCOUNT(4),
+B => RCOUNT(5),
+C => VCC,
+D => VCC,
+Z => N_6);
+UNLOCK_5_Z697: LUT4 
+generic map(
+  init => X"8888"
+)
+port map (
+A => PDIFF_SYNC,
+B => UN13_UNLOCK_CRY_21,
+C => VCC,
+D => VCC,
+Z => UNLOCK_5);
+LOCK_5_Z698: LUT4 
+generic map(
+  init => X"8888"
+)
+port map (
+A => PDIFF_SYNC,
+B => UN13_LOCK_CRY_21_I,
+C => VCC,
+D => VCC,
+Z => LOCK_5);
+RHB_WAIT_CNT12_Z699: LUT4 
+generic map(
+  init => X"2222"
+)
+port map (
+A => RHB_SYNC_P1,
+B => RHB_SYNC_P2,
+C => VCC,
+D => VCC,
+Z => RHB_WAIT_CNT12);
+\UN1_PCOUNT_DIFF[0]_Z700\: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_0,
+B => PCOUNT(0),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF(0));
+UN1_RCOUNT_1_0_A3_1_Z701: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RCOUNT(2),
+B => RCOUNT(0),
+C => RCOUNT(5),
+D => RCOUNT(4),
+Z => UN1_RCOUNT_1_0_A3_1);
+RHB_SYNC_P2_RNIU9TG1: LUT4 
+generic map(
+  init => X"7077"
+)
+port map (
+A => UN1_RHB_WAIT_CNT_5,
+B => UN1_RHB_WAIT_CNT_4,
+C => RHB_SYNC_P2,
+D => RHB_SYNC_P1,
+Z => \RHB_WAIT_CNT_\);
+\PCOUNT_CRY_0[0]\: CCU2C 
+generic map(
+  INIT0 => X"500c",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => N_8,
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_9,
+COUT => PCOUNT_CRY(0),
+S0 => PCOUNT_CRY_0_S0(0),
+S1 => PCOUNT_S(0));
+\PCOUNT_CRY_0[1]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(1),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(2),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(0),
+COUT => PCOUNT_CRY(2),
+S0 => PCOUNT_S(1),
+S1 => PCOUNT_S(2));
+\PCOUNT_CRY_0[3]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(3),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(4),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(2),
+COUT => PCOUNT_CRY(4),
+S0 => PCOUNT_S(3),
+S1 => PCOUNT_S(4));
+\PCOUNT_CRY_0[5]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(5),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(6),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(4),
+COUT => PCOUNT_CRY(6),
+S0 => PCOUNT_S(5),
+S1 => PCOUNT_S(6));
+\PCOUNT_CRY_0[7]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(7),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(8),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(6),
+COUT => PCOUNT_CRY(8),
+S0 => PCOUNT_S(7),
+S1 => PCOUNT_S(8));
+\PCOUNT_CRY_0[9]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(9),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(10),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(8),
+COUT => PCOUNT_CRY(10),
+S0 => PCOUNT_S(9),
+S1 => PCOUNT_S(10));
+\PCOUNT_CRY_0[11]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(11),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(12),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(10),
+COUT => PCOUNT_CRY(12),
+S0 => PCOUNT_S(11),
+S1 => PCOUNT_S(12));
+\PCOUNT_CRY_0[13]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(13),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(14),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(12),
+COUT => PCOUNT_CRY(14),
+S0 => PCOUNT_S(13),
+S1 => PCOUNT_S(14));
+\PCOUNT_CRY_0[15]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(15),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(16),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(14),
+COUT => PCOUNT_CRY(16),
+S0 => PCOUNT_S(15),
+S1 => PCOUNT_S(16));
+\PCOUNT_CRY_0[17]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(17),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(18),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(16),
+COUT => PCOUNT_CRY(18),
+S0 => PCOUNT_S(17),
+S1 => PCOUNT_S(18));
+\PCOUNT_CRY_0[19]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(19),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(20),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(18),
+COUT => PCOUNT_CRY(20),
+S0 => PCOUNT_S(19),
+S1 => PCOUNT_S(20));
+\PCOUNT_S_0[21]\: CCU2C 
+generic map(
+  INIT0 => X"800a",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(21),
+C0 => VCC,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(20),
+COUT => PCOUNT_S_0_COUT(21),
+S0 => PCOUNT_S(21),
+S1 => PCOUNT_S_0_S1(21));
+\RCOUNT_CRY_0[0]\: CCU2C 
+generic map(
+  INIT0 => X"5003",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => UN1_RCOUNT_1_0_A3,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_RCOUNT_1_0_A3,
+B1 => RCOUNT(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_5,
+COUT => RCOUNT_CRY(0),
+S0 => RCOUNT_CRY_0_S0(0),
+S1 => RCOUNT_S(0));
+\RCOUNT_CRY_0[1]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RCOUNT_1_0_A3,
+B0 => RCOUNT(1),
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_RCOUNT_1_0_A3,
+B1 => RCOUNT(2),
+C1 => VCC,
+D1 => VCC,
+CIN => RCOUNT_CRY(0),
+COUT => RCOUNT_CRY(2),
+S0 => RCOUNT_S(1),
+S1 => RCOUNT_S(2));
+\RCOUNT_CRY_0[3]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RCOUNT_1_0_A3,
+B0 => RCOUNT(3),
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_RCOUNT_1_0_A3,
+B1 => RCOUNT(4),
+C1 => VCC,
+D1 => VCC,
+CIN => RCOUNT_CRY(2),
+COUT => RCOUNT_CRY(4),
+S0 => RCOUNT_S(3),
+S1 => RCOUNT_S(4));
+\RCOUNT_CRY_0[5]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RCOUNT_1_0_A3,
+B0 => RCOUNT(5),
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_RCOUNT_1_0_A3,
+B1 => RCOUNT(6),
+C1 => VCC,
+D1 => VCC,
+CIN => RCOUNT_CRY(4),
+COUT => RCOUNT_CRY(6),
+S0 => RCOUNT_S(5),
+S1 => RCOUNT_S(6));
+\RCOUNT_CRY_0[7]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RCOUNT_1_0_A3,
+B0 => RCOUNT(7),
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_RCOUNT_1_0_A3,
+B1 => RCOUNT(8),
+C1 => VCC,
+D1 => VCC,
+CIN => RCOUNT_CRY(6),
+COUT => RCOUNT_CRY(8),
+S0 => RCOUNT_S(7),
+S1 => RCOUNT_S(8));
+\RCOUNT_CRY_0[9]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RCOUNT_1_0_A3,
+B0 => RCOUNT(9),
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_RCOUNT_1_0_A3,
+B1 => RCOUNT(10),
+C1 => VCC,
+D1 => VCC,
+CIN => RCOUNT_CRY(8),
+COUT => RCOUNT_CRY(10),
+S0 => RCOUNT_S(9),
+S1 => RCOUNT_S(10));
+\RCOUNT_CRY_0[11]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RCOUNT_1_0_A3,
+B0 => RCOUNT(11),
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_RCOUNT_1_0_A3,
+B1 => RCOUNT(12),
+C1 => VCC,
+D1 => VCC,
+CIN => RCOUNT_CRY(10),
+COUT => RCOUNT_CRY(12),
+S0 => RCOUNT_S(11),
+S1 => RCOUNT_S(12));
+\RCOUNT_CRY_0[13]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RCOUNT_1_0_A3,
+B0 => RCOUNT(13),
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_RCOUNT_1_0_A3,
+B1 => RCOUNT(14),
+C1 => VCC,
+D1 => VCC,
+CIN => RCOUNT_CRY(12),
+COUT => RCOUNT_CRY(14),
+S0 => RCOUNT_S(13),
+S1 => RCOUNT_S(14));
+\RCOUNT_S_0[15]\: CCU2C 
+generic map(
+  INIT0 => X"4005",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RCOUNT_1_0_A3,
+B0 => RCOUNT(15),
+C0 => VCC,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => RCOUNT_CRY(14),
+COUT => RCOUNT_S_0_COUT(15),
+S0 => RCOUNT_S(15),
+S1 => RCOUNT_S_0_S1(15));
+\RHB_WAIT_CNT_CRY_0[0]\: CCU2C 
+generic map(
+  INIT0 => X"500c",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => \RHB_WAIT_CNT_\,
+C0 => VCC,
+D0 => VCC,
+A1 => \RHB_WAIT_CNT_\,
+B1 => RHB_WAIT_CNT(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_4,
+COUT => RHB_WAIT_CNT_CRY(0),
+S0 => RHB_WAIT_CNT_CRY_0_S0(0),
+S1 => RHB_WAIT_CNT_S(0));
+\RHB_WAIT_CNT_CRY_0[1]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RHB_WAIT_CNT_\,
+B0 => RHB_WAIT_CNT(1),
+C0 => VCC,
+D0 => VCC,
+A1 => \RHB_WAIT_CNT_\,
+B1 => RHB_WAIT_CNT(2),
+C1 => VCC,
+D1 => VCC,
+CIN => RHB_WAIT_CNT_CRY(0),
+COUT => RHB_WAIT_CNT_CRY(2),
+S0 => RHB_WAIT_CNT_S(1),
+S1 => RHB_WAIT_CNT_S(2));
+\RHB_WAIT_CNT_CRY_0[3]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RHB_WAIT_CNT_\,
+B0 => RHB_WAIT_CNT(3),
+C0 => VCC,
+D0 => VCC,
+A1 => \RHB_WAIT_CNT_\,
+B1 => RHB_WAIT_CNT(4),
+C1 => VCC,
+D1 => VCC,
+CIN => RHB_WAIT_CNT_CRY(2),
+COUT => RHB_WAIT_CNT_CRY(4),
+S0 => RHB_WAIT_CNT_S(3),
+S1 => RHB_WAIT_CNT_S(4));
+\RHB_WAIT_CNT_CRY_0[5]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RHB_WAIT_CNT_\,
+B0 => RHB_WAIT_CNT(5),
+C0 => VCC,
+D0 => VCC,
+A1 => \RHB_WAIT_CNT_\,
+B1 => RHB_WAIT_CNT(6),
+C1 => VCC,
+D1 => VCC,
+CIN => RHB_WAIT_CNT_CRY(4),
+COUT => RHB_WAIT_CNT_CRY(6),
+S0 => RHB_WAIT_CNT_S(5),
+S1 => RHB_WAIT_CNT_S(6));
+\RHB_WAIT_CNT_S_0[7]\: CCU2C 
+generic map(
+  INIT0 => X"800a",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RHB_WAIT_CNT_\,
+B0 => RHB_WAIT_CNT(7),
+C0 => VCC,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => RHB_WAIT_CNT_CRY(6),
+COUT => RHB_WAIT_CNT_S_0_COUT(7),
+S0 => RHB_WAIT_CNT_S(7),
+S1 => RHB_WAIT_CNT_S_0_S1(7));
+UN1_PCOUNT_DIFF_1_CRY_0_0: CCU2C 
+generic map(
+  INIT0 => X"5003",
+  INIT1 => X"500f",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF(0),
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => N_3,
+COUT => UN1_PCOUNT_DIFF_1_CRY_0,
+S0 => UN1_PCOUNT_DIFF_1_CRY_0_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_0_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_1_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_1,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_2,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_0,
+COUT => UN1_PCOUNT_DIFF_1_CRY_2,
+S0 => UN1_PCOUNT_DIFF_1_CRY_1_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_1_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_3_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_3,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_4,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_2,
+COUT => UN1_PCOUNT_DIFF_1_CRY_4,
+S0 => UN1_PCOUNT_DIFF_1_CRY_3_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_3_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_5_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_5,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_6,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_4,
+COUT => UN1_PCOUNT_DIFF_1_CRY_6,
+S0 => UN1_PCOUNT_DIFF_1_CRY_5_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_5_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_7_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_7,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_8,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_6,
+COUT => UN1_PCOUNT_DIFF_1_CRY_8,
+S0 => UN1_PCOUNT_DIFF_1_CRY_7_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_7_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_9_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_9,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_10,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_8,
+COUT => UN1_PCOUNT_DIFF_1_CRY_10,
+S0 => UN1_PCOUNT_DIFF_1_CRY_9_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_9_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_11_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_11,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_12,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_10,
+COUT => UN1_PCOUNT_DIFF_1_CRY_12,
+S0 => UN1_PCOUNT_DIFF_1_CRY_11_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_11_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_13_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_13,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_14,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_12,
+COUT => UN1_PCOUNT_DIFF_1_CRY_14,
+S0 => UN1_PCOUNT_DIFF_1_CRY_13_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_13_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_15_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_15,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_16,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_14,
+COUT => UN1_PCOUNT_DIFF_1_CRY_16,
+S0 => UN1_PCOUNT_DIFF_1_CRY_15_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_15_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_17_0: CCU2C 
+generic map(
+  INIT0 => X"b404",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => RDIFF_COMP_LOCK(2),
+C0 => UN1_PCOUNT_DIFF_1_CRY_17_0_RNO,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_18,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_16,
+COUT => UN1_PCOUNT_DIFF_1_CRY_18,
+S0 => UN1_PCOUNT_DIFF_1_CRY_17_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_17_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_19_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_19,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_20,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_18,
+COUT => UN1_PCOUNT_DIFF_1_CRY_20,
+S0 => UN1_PCOUNT_DIFF_1_CRY_19_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_19_0_S1);
+UN1_PCOUNT_DIFF_1_S_21_0: CCU2C 
+generic map(
+  INIT0 => X"350a",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => PCOUNT(21),
+B0 => UN13_LOCK_21,
+C0 => N_8,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_20,
+COUT => UN1_PCOUNT_DIFF_1_S_21_0_COUT,
+S0 => UN1_PCOUNT_DIFF_1_S_21_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_S_21_0_S1);
+UN13_LOCK_CRY_0_0: CCU2C 
+generic map(
+  INIT0 => X"5003",
+  INIT1 => X"900a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_0,
+B1 => RDIFF_COMP_LOCK(2),
+C1 => VCC,
+D1 => VCC,
+CIN => N_2,
+COUT => UN13_LOCK_CRY_0,
+S0 => UN13_LOCK_CRY_0_0_S0,
+S1 => UN13_LOCK_CRY_0_0_S1);
+UN13_LOCK_CRY_1_0: CCU2C 
+generic map(
+  INIT0 => X"900a",
+  INIT1 => X"900a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_1,
+B0 => RDIFF_COMP_LOCK(2),
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_2,
+B1 => RDIFF_COMP_LOCK(2),
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_0,
+COUT => UN13_LOCK_CRY_2,
+S0 => UN13_LOCK_CRY_1_0_S0,
+S1 => UN13_LOCK_CRY_1_0_S1);
+UN13_LOCK_CRY_3_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_3,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_4,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_2,
+COUT => UN13_LOCK_CRY_4,
+S0 => UN13_LOCK_CRY_3_0_S0,
+S1 => UN13_LOCK_CRY_3_0_S1);
+UN13_LOCK_CRY_5_0: CCU2C 
+generic map(
+  INIT0 => X"900a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_5,
+B0 => RDIFF_COMP_LOCK(2),
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_6,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_4,
+COUT => UN13_LOCK_CRY_6,
+S0 => UN13_LOCK_CRY_5_0_S0,
+S1 => UN13_LOCK_CRY_5_0_S1);
+UN13_LOCK_CRY_7_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_7,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_8,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_6,
+COUT => UN13_LOCK_CRY_8,
+S0 => UN13_LOCK_CRY_7_0_S0,
+S1 => UN13_LOCK_CRY_7_0_S1);
+UN13_LOCK_CRY_9_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_9,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_10,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_8,
+COUT => UN13_LOCK_CRY_10,
+S0 => UN13_LOCK_CRY_9_0_S0,
+S1 => UN13_LOCK_CRY_9_0_S1);
+UN13_LOCK_CRY_11_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_11,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_12,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_10,
+COUT => UN13_LOCK_CRY_12,
+S0 => UN13_LOCK_CRY_11_0_S0,
+S1 => UN13_LOCK_CRY_11_0_S1);
+UN13_LOCK_CRY_13_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_13,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_14,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_12,
+COUT => UN13_LOCK_CRY_14,
+S0 => UN13_LOCK_CRY_13_0_S0,
+S1 => UN13_LOCK_CRY_13_0_S1);
+UN13_LOCK_CRY_15_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_15,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_16,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_14,
+COUT => UN13_LOCK_CRY_16,
+S0 => UN13_LOCK_CRY_15_0_S0,
+S1 => UN13_LOCK_CRY_15_0_S1);
+UN13_LOCK_CRY_17_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_17,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_18,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_16,
+COUT => UN13_LOCK_CRY_18,
+S0 => UN13_LOCK_CRY_17_0_S0,
+S1 => UN13_LOCK_CRY_17_0_S1);
+UN13_LOCK_CRY_19_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_19,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_20,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_18,
+COUT => UN13_LOCK_CRY_20,
+S0 => UN13_LOCK_CRY_19_0_S0,
+S1 => UN13_LOCK_CRY_19_0_S1);
+UN13_LOCK_CRY_21_0: CCU2C 
+generic map(
+  INIT0 => X"500f",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_21,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_20,
+COUT => UN13_LOCK_CRY_21_0_COUT,
+S0 => UN13_LOCK_CRY_21_0_S0,
+S1 => UN13_LOCK_CRY_21_I);
+UN13_UNLOCK_CRY_0_0: CCU2C 
+generic map(
+  INIT0 => X"5003",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_0,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => N_1,
+COUT => UN13_UNLOCK_CRY_0,
+S0 => UN13_UNLOCK_CRY_0_0_S0,
+S1 => UN13_UNLOCK_CRY_0_0_S1);
+UN13_UNLOCK_CRY_1_0: CCU2C 
+generic map(
+  INIT0 => X"900a",
+  INIT1 => X"900a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_1,
+B0 => RDIFF_COMP_LOCK(2),
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_2,
+B1 => RDIFF_COMP_LOCK(2),
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_0,
+COUT => UN13_UNLOCK_CRY_2,
+S0 => UN13_UNLOCK_CRY_1_0_S0,
+S1 => UN13_UNLOCK_CRY_1_0_S1);
+UN13_UNLOCK_CRY_3_0: CCU2C 
+generic map(
+  INIT0 => X"900a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_3,
+B0 => RDIFF_COMP_LOCK(2),
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_4,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_2,
+COUT => UN13_UNLOCK_CRY_4,
+S0 => UN13_UNLOCK_CRY_3_0_S0,
+S1 => UN13_UNLOCK_CRY_3_0_S1);
+UN13_UNLOCK_CRY_5_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"900a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_5,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_6,
+B1 => RDIFF_COMP_LOCK(2),
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_4,
+COUT => UN13_UNLOCK_CRY_6,
+S0 => UN13_UNLOCK_CRY_5_0_S0,
+S1 => UN13_UNLOCK_CRY_5_0_S1);
+UN13_UNLOCK_CRY_7_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_7,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_8,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_6,
+COUT => UN13_UNLOCK_CRY_8,
+S0 => UN13_UNLOCK_CRY_7_0_S0,
+S1 => UN13_UNLOCK_CRY_7_0_S1);
+UN13_UNLOCK_CRY_9_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_9,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_10,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_8,
+COUT => UN13_UNLOCK_CRY_10,
+S0 => UN13_UNLOCK_CRY_9_0_S0,
+S1 => UN13_UNLOCK_CRY_9_0_S1);
+UN13_UNLOCK_CRY_11_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_11,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_12,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_10,
+COUT => UN13_UNLOCK_CRY_12,
+S0 => UN13_UNLOCK_CRY_11_0_S0,
+S1 => UN13_UNLOCK_CRY_11_0_S1);
+UN13_UNLOCK_CRY_13_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_13,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_14,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_12,
+COUT => UN13_UNLOCK_CRY_14,
+S0 => UN13_UNLOCK_CRY_13_0_S0,
+S1 => UN13_UNLOCK_CRY_13_0_S1);
+UN13_UNLOCK_CRY_15_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_15,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_16,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_14,
+COUT => UN13_UNLOCK_CRY_16,
+S0 => UN13_UNLOCK_CRY_15_0_S0,
+S1 => UN13_UNLOCK_CRY_15_0_S1);
+UN13_UNLOCK_CRY_17_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_17,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_18,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_16,
+COUT => UN13_UNLOCK_CRY_18,
+S0 => UN13_UNLOCK_CRY_17_0_S0,
+S1 => UN13_UNLOCK_CRY_17_0_S1);
+UN13_UNLOCK_CRY_19_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_19,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_20,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_18,
+COUT => UN13_UNLOCK_CRY_20,
+S0 => UN13_UNLOCK_CRY_19_0_S0,
+S1 => UN13_UNLOCK_CRY_19_0_S1);
+UN13_UNLOCK_CRY_21_0: CCU2C 
+generic map(
+  INIT0 => X"500f",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_21,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_20,
+COUT => UN13_UNLOCK_CRY_21_0_COUT,
+S0 => UN13_UNLOCK_CRY_21_0_S0,
+S1 => UN13_UNLOCK_CRY_21);
+PHB_SYNC_INST: sync_0s port map (
+phb => PHB,
+rhb_sync => RHB_SYNC,
+sli_rst => sli_rst,
+pll_refclki => pll_refclki);
+RTC_SYNC_INST: sync_0s_6 port map (
+rtc_pul => RTC_PUL,
+ppul_sync => PPUL_SYNC,
+sli_rst => sli_rst,
+tx_pclk => tx_pclk);
+PDIFF_SYNC_INST: sync_0s_0 port map (
+ppul_sync => PPUL_SYNC,
+pdiff_sync => PDIFF_SYNC,
+sli_rst => sli_rst,
+pll_refclki => pll_refclki);
+VCC_0: VHI port map (
+Z => VCC);
+II_GND: VLO port map (
+Z => GND);
+end beh;
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library synplify;
+use synplify.components.all;
+library pmi;
+use pmi.pmi_components.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity sgmii_ecp5 is
+port(
+hdoutp :  out std_logic;
+hdoutn :  out std_logic;
+hdinp :  in std_logic;
+hdinn :  in std_logic;
+rxrefclk :  in std_logic;
+tx_pclk :  out std_logic;
+txi_clk :  in std_logic;
+txdata : in std_logic_vector(7 downto 0);
+tx_k : in std_logic_vector(0 downto 0);
+xmit : in std_logic_vector(0 downto 0);
+tx_disp_correct : in std_logic_vector(0 downto 0);
+rxdata : out std_logic_vector(7 downto 0);
+rx_k : out std_logic_vector(0 downto 0);
+rx_disp_err : out std_logic_vector(0 downto 0);
+rx_cv_err : out std_logic_vector(0 downto 0);
+signal_detect_c :  in std_logic;
+rx_los_low_s :  out std_logic;
+lsm_status_s :  out std_logic;
+ctc_urun_s :  out std_logic;
+ctc_orun_s :  out std_logic;
+rx_cdr_lol_s :  out std_logic;
+ctc_ins_s :  out std_logic;
+ctc_del_s :  out std_logic;
+sli_rst :  in std_logic;
+tx_pwrup_c :  in std_logic;
+rx_pwrup_c :  in std_logic;
+sci_wrdata : in std_logic_vector(7 downto 0);
+sci_addr : in std_logic_vector(5 downto 0);
+sci_rddata : out std_logic_vector(7 downto 0);
+sci_en_dual :  in std_logic;
+sci_sel_dual :  in std_logic;
+sci_en :  in std_logic;
+sci_sel :  in std_logic;
+sci_rd :  in std_logic;
+sci_wrn :  in std_logic;
+sci_int :  out std_logic;
+cyawstn :  in std_logic;
+serdes_pdb :  in std_logic;
+pll_refclki :  in std_logic;
+rsl_disable :  in std_logic;
+rsl_rst :  in std_logic;
+serdes_rst_dual_c :  in std_logic;
+rst_dual_c :  in std_logic;
+tx_serdes_rst_c :  in std_logic;
+tx_pcs_rst_c :  in std_logic;
+pll_lol :  out std_logic;
+rsl_tx_rdy :  out std_logic;
+rx_serdes_rst_c :  in std_logic;
+rx_pcs_rst_c :  in std_logic;
+rsl_rx_rdy :  out std_logic);
+end sgmii_ecp5;
+
+architecture beh of sgmii_ecp5 is
+signal TX_PCLK_11 : std_logic ;
+signal RX_LOS_LOW_S_12 : std_logic ;
+signal RX_CDR_LOL_S_13 : std_logic ;
+signal RSL_TX_PCS_RST_C : std_logic ;
+signal RSL_RX_PCS_RST_C : std_logic ;
+signal RSL_RX_SERDES_RST_C : std_logic ;
+signal RSL_SERDES_RST_DUAL_C : std_logic ;
+signal RSL_TX_SERDES_RST_C : std_logic ;
+signal N47_1 : std_logic ;
+signal N48_1 : std_logic ;
+signal N1_1 : std_logic ;
+signal N2_1 : std_logic ;
+signal N3_1 : std_logic ;
+signal N4_1 : std_logic ;
+signal N5_1 : std_logic ;
+signal N49_1 : std_logic ;
+signal N6_1 : std_logic ;
+signal N50_1 : std_logic ;
+signal N7_1 : std_logic ;
+signal N51_1 : std_logic ;
+signal N8_1 : std_logic ;
+signal N52_1 : std_logic ;
+signal N9_1 : std_logic ;
+signal N53_1 : std_logic ;
+signal N54_1 : std_logic ;
+signal N55_1 : std_logic ;
+signal N56_1 : std_logic ;
+signal N57_1 : std_logic ;
+signal N58_1 : std_logic ;
+signal N59_1 : std_logic ;
+signal N60_1 : std_logic ;
+signal N61_1 : std_logic ;
+signal N62_1 : std_logic ;
+signal N63_1 : std_logic ;
+signal N64_1 : std_logic ;
+signal N65_1 : std_logic ;
+signal N10_1 : std_logic ;
+signal N66_1 : std_logic ;
+signal N67_1 : std_logic ;
+signal N68_1 : std_logic ;
+signal N69_1 : std_logic ;
+signal N70_1 : std_logic ;
+signal N71_1 : std_logic ;
+signal N72_1 : std_logic ;
+signal N73_1 : std_logic ;
+signal N74_1 : std_logic ;
+signal N75_1 : std_logic ;
+signal N76_1 : std_logic ;
+signal N77_1 : std_logic ;
+signal N78_1 : std_logic ;
+signal N79_1 : std_logic ;
+signal N80_1 : std_logic ;
+signal N81_1 : std_logic ;
+signal N82_1 : std_logic ;
+signal N83_1 : std_logic ;
+signal N84_1 : std_logic ;
+signal N85_1 : std_logic ;
+signal N86_1 : std_logic ;
+signal N87_1 : std_logic ;
+signal N88_1 : std_logic ;
+signal N11_1 : std_logic ;
+signal N89_1 : std_logic ;
+signal N12_1 : std_logic ;
+signal N90_1 : std_logic ;
+signal N13_1 : std_logic ;
+signal N91_1 : std_logic ;
+signal N92_1 : std_logic ;
+signal N93_1 : std_logic ;
+signal N94_1 : std_logic ;
+signal N95_1 : std_logic ;
+signal N14_1 : std_logic ;
+signal N96_1 : std_logic ;
+signal N15_1 : std_logic ;
+signal N97_1 : std_logic ;
+signal N98_1 : std_logic ;
+signal N99_1 : std_logic ;
+signal N100_1 : std_logic ;
+signal N101_1 : std_logic ;
+signal N112_1 : std_logic ;
+signal N16_1 : std_logic ;
+signal N17_1 : std_logic ;
+signal N18_1 : std_logic ;
+signal N19_1 : std_logic ;
+signal N20_1 : std_logic ;
+signal N21_1 : std_logic ;
+signal N22_1 : std_logic ;
+signal N23_1 : std_logic ;
+signal N24_1 : std_logic ;
+signal N25_1 : std_logic ;
+signal N26_1 : std_logic ;
+signal N27_1 : std_logic ;
+signal N28_1 : std_logic ;
+signal N29_1 : std_logic ;
+signal N30_1 : std_logic ;
+signal N31_1 : std_logic ;
+signal N32_1 : std_logic ;
+signal N33_1 : std_logic ;
+signal N34_1 : std_logic ;
+signal N35_1 : std_logic ;
+signal N36_1 : std_logic ;
+signal N37_1 : std_logic ;
+signal N38_1 : std_logic ;
+signal N39_1 : std_logic ;
+signal N40_1 : std_logic ;
+signal N41_1 : std_logic ;
+signal N42_1 : std_logic ;
+signal N43_1 : std_logic ;
+signal N46_1 : std_logic ;
+signal TX_PCLK_I : std_logic ;
+signal GND : std_logic ;
+signal VCC : std_logic ;
+signal \SLL_INST.PLL_LOCK_I_14\ : std_logic ;
+component sgmii_ecp5sll_core_Z1_layer1
+port(
+tx_pclk :  in std_logic;
+sli_rst :  in std_logic;
+pll_refclki :  in std_logic;
+pll_lock_i :  out std_logic  );
+end component;
+component sgmii_ecp5rsl_core_Z2_layer1
+port(
+rx_pcs_rst_c :  in std_logic;
+tx_pcs_rst_c :  in std_logic;
+tx_serdes_rst_c :  in std_logic;
+serdes_rst_dual_c :  in std_logic;
+rsl_tx_pcs_rst_c :  out std_logic;
+rsl_rx_serdes_rst_c :  out std_logic;
+rsl_serdes_rst_dual_c :  out std_logic;
+rsl_tx_serdes_rst_c :  out std_logic;
+rsl_tx_rdy :  out std_logic;
+pll_lock_i :  in std_logic;
+pll_refclki :  in std_logic;
+rsl_rx_rdy :  out std_logic;
+rsl_rst :  in std_logic;
+rxrefclk :  in std_logic;
+rsl_disable :  in std_logic;
+rx_serdes_rst_c :  in std_logic;
+rsl_rx_pcs_rst_c :  out std_logic;
+rst_dual_c :  in std_logic;
+rx_cdr_lol_s :  in std_logic;
+rx_los_low_s :  in std_logic  );
+end component;
+begin
+VCC_0: VHI port map (
+Z => VCC);
+GND_0: VLO port map (
+Z => GND);
+PUR_INST: PUR port map (
+PUR => VCC);
+GSR_INST: GSR port map (
+GSR => VCC);
+TX_PCLK_11 <= TX_PCLK_I;
+DCU0_INST: DCUA 
+generic map( 
+  D_MACROPDB => "0b1", 
+  D_IB_PWDNB => "0b1", 
+  D_XGE_MODE => "0b0", 
+  D_LOW_MARK => "0d4", 
+  D_HIGH_MARK => "0d12", 
+  D_BUS8BIT_SEL => "0b0", 
+  D_CDR_LOL_SET => "0b00", 
+  D_BITCLK_LOCAL_EN => "0b1", 
+  D_BITCLK_ND_EN => "0b0", 
+  D_BITCLK_FROM_ND_EN => "0b0", 
+  D_SYNC_LOCAL_EN => "0b1", 
+  D_SYNC_ND_EN => "0b0", 
+  CH0_UC_MODE => "0b0", 
+  CH0_PCIE_MODE => "0b0", 
+  CH0_RIO_MODE => "0b0", 
+  CH0_WA_MODE => "0b0", 
+  CH0_INVERT_RX => "0b0", 
+  CH0_INVERT_TX => "0b0", 
+  CH0_PRBS_SELECTION => "0b0", 
+  CH0_GE_AN_ENABLE => "0b0", 
+  CH0_PRBS_LOCK => "0b0", 
+  CH0_PRBS_ENABLE => "0b0", 
+  CH0_ENABLE_CG_ALIGN => "0b1", 
+  CH0_TX_GEAR_MODE => "0b0", 
+  CH0_RX_GEAR_MODE => "0b0", 
+  CH0_PCS_DET_TIME_SEL => "0b00", 
+  CH0_PCIE_EI_EN => "0b0", 
+  CH0_TX_GEAR_BYPASS => "0b0", 
+  CH0_ENC_BYPASS => "0b0", 
+  CH0_SB_BYPASS => "0b0", 
+  CH0_RX_SB_BYPASS => "0b0", 
+  CH0_WA_BYPASS => "0b0", 
+  CH0_DEC_BYPASS => "0b0", 
+  CH0_CTC_BYPASS => "0b0", 
+  CH0_RX_GEAR_BYPASS => "0b0", 
+  CH0_LSM_DISABLE => "0b0", 
+  CH0_MATCH_2_ENABLE => "0b1", 
+  CH0_MATCH_4_ENABLE => "0b0", 
+  CH0_MIN_IPG_CNT => "0b11", 
+  CH0_CC_MATCH_1 => "0x000", 
+  CH0_CC_MATCH_2 => "0x000", 
+  CH0_CC_MATCH_3 => "0x1BC", 
+  CH0_CC_MATCH_4 => "0x050", 
+  CH0_UDF_COMMA_MASK => "0x3ff", 
+  CH0_UDF_COMMA_A => "0x283", 
+  CH0_UDF_COMMA_B => "0x17C", 
+  CH0_RX_DCO_CK_DIV => "0b010", 
+  CH0_RCV_DCC_EN => "0b0", 
+  CH0_REQ_LVL_SET => "0b00", 
+  CH0_REQ_EN => "0b1", 
+  CH0_RTERM_RX => "0d22", 
+  CH0_PDEN_SEL => "0b1", 
+  CH0_LDR_RX2CORE_SEL => "0b0", 
+  CH0_LDR_CORE2TX_SEL => "0b0", 
+  CH0_TPWDNB => "0b1", 
+  CH0_RATE_MODE_TX => "0b0", 
+  CH0_RTERM_TX => "0d19", 
+  CH0_TX_CM_SEL => "0b00", 
+  CH0_TDRV_PRE_EN => "0b0", 
+  CH0_TDRV_SLICE0_SEL => "0b01", 
+  CH0_TDRV_SLICE1_SEL => "0b00", 
+  CH0_TDRV_SLICE2_SEL => "0b01", 
+  CH0_TDRV_SLICE3_SEL => "0b01", 
+  CH0_TDRV_SLICE4_SEL => "0b01", 
+  CH0_TDRV_SLICE5_SEL => "0b01", 
+  CH0_TDRV_SLICE0_CUR => "0b101", 
+  CH0_TDRV_SLICE1_CUR => "0b000", 
+  CH0_TDRV_SLICE2_CUR => "0b11", 
+  CH0_TDRV_SLICE3_CUR => "0b11", 
+  CH0_TDRV_SLICE4_CUR => "0b11", 
+  CH0_TDRV_SLICE5_CUR => "0b00", 
+  CH0_TDRV_DAT_SEL => "0b00", 
+  CH0_TX_DIV11_SEL => "0b0", 
+  CH0_RPWDNB => "0b1", 
+  CH0_RATE_MODE_RX => "0b0", 
+  CH0_RLOS_SEL => "0b1", 
+  CH0_RX_LOS_LVL => "0b010", 
+  CH0_RX_LOS_CEQ => "0b11", 
+  CH0_RX_LOS_HYST_EN => "0b0", 
+  CH0_RX_LOS_EN => "0b1", 
+  CH0_RX_DIV11_SEL => "0b0", 
+  CH0_SEL_SD_RX_CLK => "0b0", 
+  CH0_FF_RX_H_CLK_EN => "0b0", 
+  CH0_FF_RX_F_CLK_DIS => "0b0", 
+  CH0_FF_TX_H_CLK_EN => "0b0", 
+  CH0_FF_TX_F_CLK_DIS => "0b0", 
+  CH0_RX_RATE_SEL => "0d8", 
+  CH0_TDRV_POST_EN => "0b0", 
+  CH0_TX_POST_SIGN => "0b0", 
+  CH0_TX_PRE_SIGN => "0b0", 
+  CH0_RXTERM_CM => "0b11", 
+  CH0_RXIN_CM => "0b11", 
+  CH0_LEQ_OFFSET_SEL => "0b0", 
+  CH0_LEQ_OFFSET_TRIM => "0b000", 
+  D_TX_MAX_RATE => "1.25", 
+  CH0_CDR_MAX_RATE => "1.25", 
+  CH0_TXAMPLITUDE => "0d1100", 
+  CH0_TXDEPRE => "DISABLED", 
+  CH0_TXDEPOST => "DISABLED", 
+  CH0_PROTOCOL => "GBE", 
+  D_ISETLOS => "0d0", 
+  D_SETIRPOLY_AUX => "0b00", 
+  D_SETICONST_AUX => "0b00", 
+  D_SETIRPOLY_CH => "0b00", 
+  D_SETICONST_CH => "0b00", 
+  D_REQ_ISET => "0b000", 
+  D_PD_ISET => "0b00", 
+  D_DCO_CALIB_TIME_SEL => "0b00", 
+  CH0_DCOCTLGI => "0b010", 
+  CH0_DCOATDDLY => "0b00", 
+  CH0_DCOATDCFG => "0b00", 
+  CH0_DCOBYPSATD => "0b1", 
+  CH0_DCOSCALEI => "0b00", 
+  CH0_DCOITUNE4LSB => "0b111", 
+  CH0_DCOIOSTUNE => "0b000", 
+  CH0_DCODISBDAVOID => "0b0", 
+  CH0_DCOCALDIV => "0b001", 
+  CH0_DCONUOFLSB => "0b101", 
+  CH0_DCOIUPDNX2 => "0b1", 
+  CH0_DCOSTEP => "0b00", 
+  CH0_DCOSTARTVAL => "0b000", 
+  CH0_DCOFLTDAC => "0b01", 
+  CH0_DCOITUNE => "0b00", 
+  CH0_DCOFTNRG => "0b110", 
+  CH0_CDR_CNT4SEL => "0b00", 
+  CH0_CDR_CNT8SEL => "0b00", 
+  CH0_BAND_THRESHOLD => "0d0", 
+  CH0_AUTO_FACQ_EN => "0b1", 
+  CH0_AUTO_CALIB_EN => "0b1", 
+  CH0_CALIB_CK_MODE => "0b0", 
+  CH0_REG_BAND_OFFSET => "0d0", 
+  CH0_REG_BAND_SEL => "0d0", 
+  CH0_REG_IDAC_SEL => "0d0", 
+  CH0_REG_IDAC_EN => "0b0", 
+  D_TXPLL_PWDNB => "0b1", 
+  D_SETPLLRC => "0d1", 
+  D_REFCK_MODE => "0b001", 
+  D_TX_VCO_CK_DIV => "0b010", 
+  D_PLL_LOL_SET => "0b00", 
+  D_RG_EN => "0b0", 
+  D_RG_SET => "0b00", 
+  D_CMUSETISCL4VCO => "0b000", 
+  D_CMUSETI4VCO => "0b00", 
+  D_CMUSETINITVCT => "0b00", 
+  D_CMUSETZGM => "0b000", 
+  D_CMUSETP2AGM => "0b000", 
+  D_CMUSETP1GM => "0b000", 
+  D_CMUSETI4CPZ => "0d3", 
+  D_CMUSETI4CPP => "0d3", 
+  D_CMUSETICP4Z => "0b101", 
+  D_CMUSETICP4P => "0b01", 
+  D_CMUSETBIASI => "0b00"
+) 
+port map (
+CH0_HDINP => hdinp,
+CH1_HDINP => GND,
+CH0_HDINN => hdinn,
+CH1_HDINN => GND,
+D_TXBIT_CLKP_FROM_ND => GND,
+D_TXBIT_CLKN_FROM_ND => GND,
+D_SYNC_ND => GND,
+D_TXPLL_LOL_FROM_ND => GND,
+CH0_RX_REFCLK => rxrefclk,
+CH1_RX_REFCLK => GND,
+CH0_FF_RXI_CLK => TX_PCLK_11,
+CH1_FF_RXI_CLK => VCC,
+CH0_FF_TXI_CLK => txi_clk,
+CH1_FF_TXI_CLK => VCC,
+CH0_FF_EBRD_CLK => TX_PCLK_11,
+CH1_FF_EBRD_CLK => VCC,
+CH0_FF_TX_D_0 => txdata(0),
+CH1_FF_TX_D_0 => GND,
+CH0_FF_TX_D_1 => txdata(1),
+CH1_FF_TX_D_1 => GND,
+CH0_FF_TX_D_2 => txdata(2),
+CH1_FF_TX_D_2 => GND,
+CH0_FF_TX_D_3 => txdata(3),
+CH1_FF_TX_D_3 => GND,
+CH0_FF_TX_D_4 => txdata(4),
+CH1_FF_TX_D_4 => GND,
+CH0_FF_TX_D_5 => txdata(5),
+CH1_FF_TX_D_5 => GND,
+CH0_FF_TX_D_6 => txdata(6),
+CH1_FF_TX_D_6 => GND,
+CH0_FF_TX_D_7 => txdata(7),
+CH1_FF_TX_D_7 => GND,
+CH0_FF_TX_D_8 => tx_k(0),
+CH1_FF_TX_D_8 => GND,
+CH0_FF_TX_D_9 => GND,
+CH1_FF_TX_D_9 => GND,
+CH0_FF_TX_D_10 => xmit(0),
+CH1_FF_TX_D_10 => GND,
+CH0_FF_TX_D_11 => tx_disp_correct(0),
+CH1_FF_TX_D_11 => GND,
+CH0_FF_TX_D_12 => GND,
+CH1_FF_TX_D_12 => GND,
+CH0_FF_TX_D_13 => GND,
+CH1_FF_TX_D_13 => GND,
+CH0_FF_TX_D_14 => GND,
+CH1_FF_TX_D_14 => GND,
+CH0_FF_TX_D_15 => GND,
+CH1_FF_TX_D_15 => GND,
+CH0_FF_TX_D_16 => GND,
+CH1_FF_TX_D_16 => GND,
+CH0_FF_TX_D_17 => GND,
+CH1_FF_TX_D_17 => GND,
+CH0_FF_TX_D_18 => GND,
+CH1_FF_TX_D_18 => GND,
+CH0_FF_TX_D_19 => GND,
+CH1_FF_TX_D_19 => GND,
+CH0_FF_TX_D_20 => GND,
+CH1_FF_TX_D_20 => GND,
+CH0_FF_TX_D_21 => GND,
+CH1_FF_TX_D_21 => GND,
+CH0_FF_TX_D_22 => GND,
+CH1_FF_TX_D_22 => GND,
+CH0_FF_TX_D_23 => GND,
+CH1_FF_TX_D_23 => GND,
+CH0_FFC_EI_EN => GND,
+CH1_FFC_EI_EN => GND,
+CH0_FFC_PCIE_DET_EN => GND,
+CH1_FFC_PCIE_DET_EN => GND,
+CH0_FFC_PCIE_CT => GND,
+CH1_FFC_PCIE_CT => GND,
+CH0_FFC_SB_INV_RX => GND,
+CH1_FFC_SB_INV_RX => GND,
+CH0_FFC_ENABLE_CGALIGN => GND,
+CH1_FFC_ENABLE_CGALIGN => GND,
+CH0_FFC_SIGNAL_DETECT => signal_detect_c,
+CH1_FFC_SIGNAL_DETECT => GND,
+CH0_FFC_FB_LOOPBACK => GND,
+CH1_FFC_FB_LOOPBACK => GND,
+CH0_FFC_SB_PFIFO_LP => GND,
+CH1_FFC_SB_PFIFO_LP => GND,
+CH0_FFC_PFIFO_CLR => GND,
+CH1_FFC_PFIFO_CLR => GND,
+CH0_FFC_RATE_MODE_RX => GND,
+CH1_FFC_RATE_MODE_RX => GND,
+CH0_FFC_RATE_MODE_TX => GND,
+CH1_FFC_RATE_MODE_TX => GND,
+CH0_FFC_DIV11_MODE_RX => GND,
+CH1_FFC_DIV11_MODE_RX => GND,
+CH0_FFC_RX_GEAR_MODE => GND,
+CH1_FFC_RX_GEAR_MODE => GND,
+CH0_FFC_TX_GEAR_MODE => GND,
+CH1_FFC_TX_GEAR_MODE => GND,
+CH0_FFC_DIV11_MODE_TX => GND,
+CH1_FFC_DIV11_MODE_TX => GND,
+CH0_FFC_LDR_CORE2TX_EN => GND,
+CH1_FFC_LDR_CORE2TX_EN => GND,
+CH0_FFC_LANE_TX_RST => RSL_TX_PCS_RST_C,
+CH1_FFC_LANE_TX_RST => GND,
+CH0_FFC_LANE_RX_RST => RSL_RX_PCS_RST_C,
+CH1_FFC_LANE_RX_RST => GND,
+CH0_FFC_RRST => RSL_RX_SERDES_RST_C,
+CH1_FFC_RRST => GND,
+CH0_FFC_TXPWDNB => tx_pwrup_c,
+CH1_FFC_TXPWDNB => GND,
+CH0_FFC_RXPWDNB => rx_pwrup_c,
+CH1_FFC_RXPWDNB => GND,
+CH0_LDR_CORE2TX => GND,
+CH1_LDR_CORE2TX => GND,
+D_SCIWDATA0 => sci_wrdata(0),
+D_SCIWDATA1 => sci_wrdata(1),
+D_SCIWDATA2 => sci_wrdata(2),
+D_SCIWDATA3 => sci_wrdata(3),
+D_SCIWDATA4 => sci_wrdata(4),
+D_SCIWDATA5 => sci_wrdata(5),
+D_SCIWDATA6 => sci_wrdata(6),
+D_SCIWDATA7 => sci_wrdata(7),
+D_SCIADDR0 => sci_addr(0),
+D_SCIADDR1 => sci_addr(1),
+D_SCIADDR2 => sci_addr(2),
+D_SCIADDR3 => sci_addr(3),
+D_SCIADDR4 => sci_addr(4),
+D_SCIADDR5 => sci_addr(5),
+D_SCIENAUX => sci_en_dual,
+D_SCISELAUX => sci_sel_dual,
+CH0_SCIEN => sci_en,
+CH1_SCIEN => GND,
+CH0_SCISEL => sci_sel,
+CH1_SCISEL => GND,
+D_SCIRD => sci_rd,
+D_SCIWSTN => sci_wrn,
+D_CYAWSTN => cyawstn,
+D_FFC_SYNC_TOGGLE => GND,
+D_FFC_DUAL_RST => rst_dual_c,
+D_FFC_MACRO_RST => RSL_SERDES_RST_DUAL_C,
+D_FFC_MACROPDB => serdes_pdb,
+D_FFC_TRST => RSL_TX_SERDES_RST_C,
+CH0_FFC_CDR_EN_BITSLIP => GND,
+CH1_FFC_CDR_EN_BITSLIP => GND,
+D_SCAN_ENABLE => GND,
+D_SCAN_IN_0 => GND,
+D_SCAN_IN_1 => GND,
+D_SCAN_IN_2 => GND,
+D_SCAN_IN_3 => GND,
+D_SCAN_IN_4 => GND,
+D_SCAN_IN_5 => GND,
+D_SCAN_IN_6 => GND,
+D_SCAN_IN_7 => GND,
+D_SCAN_MODE => GND,
+D_SCAN_RESET => GND,
+D_CIN0 => GND,
+D_CIN1 => GND,
+D_CIN2 => GND,
+D_CIN3 => GND,
+D_CIN4 => GND,
+D_CIN5 => GND,
+D_CIN6 => GND,
+D_CIN7 => GND,
+D_CIN8 => GND,
+D_CIN9 => GND,
+D_CIN10 => GND,
+D_CIN11 => GND,
+CH0_HDOUTP => hdoutp,
+CH1_HDOUTP => N47_1,
+CH0_HDOUTN => hdoutn,
+CH1_HDOUTN => N48_1,
+D_TXBIT_CLKP_TO_ND => N1_1,
+D_TXBIT_CLKN_TO_ND => N2_1,
+D_SYNC_PULSE2ND => N3_1,
+D_TXPLL_LOL_TO_ND => N4_1,
+CH0_FF_RX_F_CLK => N5_1,
+CH1_FF_RX_F_CLK => N49_1,
+CH0_FF_RX_H_CLK => N6_1,
+CH1_FF_RX_H_CLK => N50_1,
+CH0_FF_TX_F_CLK => N7_1,
+CH1_FF_TX_F_CLK => N51_1,
+CH0_FF_TX_H_CLK => N8_1,
+CH1_FF_TX_H_CLK => N52_1,
+CH0_FF_RX_PCLK => N9_1,
+CH1_FF_RX_PCLK => N53_1,
+CH0_FF_TX_PCLK => TX_PCLK_I,
+CH1_FF_TX_PCLK => N54_1,
+CH0_FF_RX_D_0 => rxdata(0),
+CH1_FF_RX_D_0 => N55_1,
+CH0_FF_RX_D_1 => rxdata(1),
+CH1_FF_RX_D_1 => N56_1,
+CH0_FF_RX_D_2 => rxdata(2),
+CH1_FF_RX_D_2 => N57_1,
+CH0_FF_RX_D_3 => rxdata(3),
+CH1_FF_RX_D_3 => N58_1,
+CH0_FF_RX_D_4 => rxdata(4),
+CH1_FF_RX_D_4 => N59_1,
+CH0_FF_RX_D_5 => rxdata(5),
+CH1_FF_RX_D_5 => N60_1,
+CH0_FF_RX_D_6 => rxdata(6),
+CH1_FF_RX_D_6 => N61_1,
+CH0_FF_RX_D_7 => rxdata(7),
+CH1_FF_RX_D_7 => N62_1,
+CH0_FF_RX_D_8 => rx_k(0),
+CH1_FF_RX_D_8 => N63_1,
+CH0_FF_RX_D_9 => rx_disp_err(0),
+CH1_FF_RX_D_9 => N64_1,
+CH0_FF_RX_D_10 => rx_cv_err(0),
+CH1_FF_RX_D_10 => N65_1,
+CH0_FF_RX_D_11 => N10_1,
+CH1_FF_RX_D_11 => N66_1,
+CH0_FF_RX_D_12 => N67_1,
+CH1_FF_RX_D_12 => N68_1,
+CH0_FF_RX_D_13 => N69_1,
+CH1_FF_RX_D_13 => N70_1,
+CH0_FF_RX_D_14 => N71_1,
+CH1_FF_RX_D_14 => N72_1,
+CH0_FF_RX_D_15 => N73_1,
+CH1_FF_RX_D_15 => N74_1,
+CH0_FF_RX_D_16 => N75_1,
+CH1_FF_RX_D_16 => N76_1,
+CH0_FF_RX_D_17 => N77_1,
+CH1_FF_RX_D_17 => N78_1,
+CH0_FF_RX_D_18 => N79_1,
+CH1_FF_RX_D_18 => N80_1,
+CH0_FF_RX_D_19 => N81_1,
+CH1_FF_RX_D_19 => N82_1,
+CH0_FF_RX_D_20 => N83_1,
+CH1_FF_RX_D_20 => N84_1,
+CH0_FF_RX_D_21 => N85_1,
+CH1_FF_RX_D_21 => N86_1,
+CH0_FF_RX_D_22 => N87_1,
+CH1_FF_RX_D_22 => N88_1,
+CH0_FF_RX_D_23 => N11_1,
+CH1_FF_RX_D_23 => N89_1,
+CH0_FFS_PCIE_DONE => N12_1,
+CH1_FFS_PCIE_DONE => N90_1,
+CH0_FFS_PCIE_CON => N13_1,
+CH1_FFS_PCIE_CON => N91_1,
+CH0_FFS_RLOS => RX_LOS_LOW_S_12,
+CH1_FFS_RLOS => N92_1,
+CH0_FFS_LS_SYNC_STATUS => lsm_status_s,
+CH1_FFS_LS_SYNC_STATUS => N93_1,
+CH0_FFS_CC_UNDERRUN => ctc_urun_s,
+CH1_FFS_CC_UNDERRUN => N94_1,
+CH0_FFS_CC_OVERRUN => ctc_orun_s,
+CH1_FFS_CC_OVERRUN => N95_1,
+CH0_FFS_RXFBFIFO_ERROR => N14_1,
+CH1_FFS_RXFBFIFO_ERROR => N96_1,
+CH0_FFS_TXFBFIFO_ERROR => N15_1,
+CH1_FFS_TXFBFIFO_ERROR => N97_1,
+CH0_FFS_RLOL => RX_CDR_LOL_S_13,
+CH1_FFS_RLOL => N98_1,
+CH0_FFS_SKP_ADDED => ctc_ins_s,
+CH1_FFS_SKP_ADDED => N99_1,
+CH0_FFS_SKP_DELETED => ctc_del_s,
+CH1_FFS_SKP_DELETED => N100_1,
+CH0_LDR_RX2CORE => N101_1,
+CH1_LDR_RX2CORE => N112_1,
+D_SCIRDATA0 => sci_rddata(0),
+D_SCIRDATA1 => sci_rddata(1),
+D_SCIRDATA2 => sci_rddata(2),
+D_SCIRDATA3 => sci_rddata(3),
+D_SCIRDATA4 => sci_rddata(4),
+D_SCIRDATA5 => sci_rddata(5),
+D_SCIRDATA6 => sci_rddata(6),
+D_SCIRDATA7 => sci_rddata(7),
+D_SCIINT => sci_int,
+D_SCAN_OUT_0 => N16_1,
+D_SCAN_OUT_1 => N17_1,
+D_SCAN_OUT_2 => N18_1,
+D_SCAN_OUT_3 => N19_1,
+D_SCAN_OUT_4 => N20_1,
+D_SCAN_OUT_5 => N21_1,
+D_SCAN_OUT_6 => N22_1,
+D_SCAN_OUT_7 => N23_1,
+D_COUT0 => N24_1,
+D_COUT1 => N25_1,
+D_COUT2 => N26_1,
+D_COUT3 => N27_1,
+D_COUT4 => N28_1,
+D_COUT5 => N29_1,
+D_COUT6 => N30_1,
+D_COUT7 => N31_1,
+D_COUT8 => N32_1,
+D_COUT9 => N33_1,
+D_COUT10 => N34_1,
+D_COUT11 => N35_1,
+D_COUT12 => N36_1,
+D_COUT13 => N37_1,
+D_COUT14 => N38_1,
+D_COUT15 => N39_1,
+D_COUT16 => N40_1,
+D_COUT17 => N41_1,
+D_COUT18 => N42_1,
+D_COUT19 => N43_1,
+D_REFCLKI => pll_refclki,
+D_FFS_PLOL => N46_1);
+SLL_INST: sgmii_ecp5sll_core_Z1_layer1 port map (
+tx_pclk => TX_PCLK_11,
+sli_rst => sli_rst,
+pll_refclki => pll_refclki,
+pll_lock_i => \SLL_INST.PLL_LOCK_I_14\);
+RSL_INST: sgmii_ecp5rsl_core_Z2_layer1 port map (
+rx_pcs_rst_c => rx_pcs_rst_c,
+tx_pcs_rst_c => tx_pcs_rst_c,
+tx_serdes_rst_c => tx_serdes_rst_c,
+serdes_rst_dual_c => serdes_rst_dual_c,
+rsl_tx_pcs_rst_c => RSL_TX_PCS_RST_C,
+rsl_rx_serdes_rst_c => RSL_RX_SERDES_RST_C,
+rsl_serdes_rst_dual_c => RSL_SERDES_RST_DUAL_C,
+rsl_tx_serdes_rst_c => RSL_TX_SERDES_RST_C,
+rsl_tx_rdy => rsl_tx_rdy,
+pll_lock_i => \SLL_INST.PLL_LOCK_I_14\,
+pll_refclki => pll_refclki,
+rsl_rx_rdy => rsl_rx_rdy,
+rsl_rst => rsl_rst,
+rxrefclk => rxrefclk,
+rsl_disable => rsl_disable,
+rx_serdes_rst_c => rx_serdes_rst_c,
+rsl_rx_pcs_rst_c => RSL_RX_PCS_RST_C,
+rst_dual_c => rst_dual_c,
+rx_cdr_lol_s => RX_CDR_LOL_S_13,
+rx_los_low_s => RX_LOS_LOW_S_12);
+tx_pclk <= TX_PCLK_11;
+rx_los_low_s <= RX_LOS_LOW_S_12;
+rx_cdr_lol_s <= RX_CDR_LOL_S_13;
+pll_lol <= \SLL_INST.PLL_LOCK_I_14\;
+end beh;
+

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.vm b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.vm
new file mode 100644 (file)
index 0000000..eff3561
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.vm
@@ -0,0 +1,6626 @@
+//
+// Written by Synplify Pro 
+// Product Version "M-2017.03L-SP1-1"
+// Program "Synplify Pro", Mapper "maplat, Build 1796R"
+// Mon May 13 09:09:10 2019
+//
+// Source file index table:
+// Object locations will have the form <file>:<line>
+// file 0 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd "
+// file 1 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd "
+// file 2 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd "
+// file 3 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd "
+// file 4 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd "
+// file 5 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd "
+// file 6 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd "
+// file 7 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd "
+// file 8 "\/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd "
+// file 9 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd "
+// file 10 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v "
+// file 11 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v "
+// file 12 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v "
+// file 13 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v "
+// file 14 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v "
+// file 15 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh "
+// file 16 "\/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v "
+// file 17 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/nlconst.dat "
+// file 18 "\/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.fdc "
+
+`timescale 100 ps/100 ps
+module sync_0s (
+  phb,
+  rhb_sync,
+  sli_rst,
+  pll_refclki
+)
+;
+input phb ;
+output rhb_sync ;
+input sli_rst ;
+input pll_refclki ;
+wire phb ;
+wire rhb_sync ;
+wire sli_rst ;
+wire pll_refclki ;
+wire data_p1 ;
+wire data_p2_QN_0 ;
+wire VCC ;
+wire data_p1_QN_0 ;
+wire GND ;
+// @16:1988
+  FD1S3DX data_p2 (
+       .D(data_p1),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_sync)
+);
+// @16:1988
+  FD1S3DX data_p1_reg (
+       .D(phb),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(data_p1)
+);
+  VHI VCC_0 (
+       .Z(VCC)
+);
+// @16:865
+  VLO GND_cZ (
+       .Z(GND)
+);
+endmodule /* sync_0s */
+
+module sync_0s_6 (
+  rtc_pul,
+  ppul_sync,
+  sli_rst,
+  tx_pclk
+)
+;
+input rtc_pul ;
+output ppul_sync ;
+input sli_rst ;
+input tx_pclk ;
+wire rtc_pul ;
+wire ppul_sync ;
+wire sli_rst ;
+wire tx_pclk ;
+wire data_p1 ;
+wire data_p2_QN ;
+wire VCC ;
+wire data_p1_QN ;
+wire GND ;
+// @16:1988
+  FD1S3DX data_p2 (
+       .D(data_p1),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(ppul_sync)
+);
+// @16:1988
+  FD1S3DX data_p1_reg (
+       .D(rtc_pul),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(data_p1)
+);
+  VHI VCC_0 (
+       .Z(VCC)
+);
+// @16:865
+  VLO GND_cZ (
+       .Z(GND)
+);
+endmodule /* sync_0s_6 */
+
+module sync_0s_0 (
+  ppul_sync,
+  pdiff_sync,
+  sli_rst,
+  pll_refclki
+)
+;
+input ppul_sync ;
+output pdiff_sync ;
+input sli_rst ;
+input pll_refclki ;
+wire ppul_sync ;
+wire pdiff_sync ;
+wire sli_rst ;
+wire pll_refclki ;
+wire data_p1 ;
+wire data_p2_QN_1 ;
+wire VCC ;
+wire data_p1_QN_1 ;
+wire GND ;
+// @16:1988
+  FD1S3DX data_p2 (
+       .D(data_p1),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(pdiff_sync)
+);
+// @16:1988
+  FD1S3DX data_p1_reg (
+       .D(ppul_sync),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(data_p1)
+);
+  VHI VCC_0 (
+       .Z(VCC)
+);
+// @16:865
+  VLO GND_cZ (
+       .Z(GND)
+);
+endmodule /* sync_0s_0 */
+
+module sgmii_ecp5sll_core_Z1_layer1 (
+  tx_pclk,
+  sli_rst,
+  pll_refclki,
+  pll_lock_i
+)
+;
+input tx_pclk ;
+input sli_rst ;
+input pll_refclki ;
+output pll_lock_i ;
+wire tx_pclk ;
+wire sli_rst ;
+wire pll_refclki ;
+wire pll_lock_i ;
+wire [2:0] phb_cnt;
+wire [2:0] phb_cnt_i;
+wire [15:0] rcount;
+wire [21:0] pcount;
+wire [0:0] un1_pcount_diff_i;
+wire [1:0] sll_state;
+wire [1:0] sll_state_QN;
+wire [7:0] rhb_wait_cnt_s;
+wire [7:0] rhb_wait_cnt;
+wire [7:0] rhb_wait_cnt_QN;
+wire [15:0] rcount_s;
+wire [15:0] rcount_QN;
+wire [2:0] phb_cnt_QN;
+wire [2:1] phb_cnt_RNO;
+wire [21:0] pcount_s;
+wire [21:0] pcount_QN;
+wire [21:0] pcount_diff_QN;
+wire [2:2] rdiff_comp_lock;
+wire [2:2] rdiff_comp_lock_QN;
+wire [0:0] un1_pcount_diff;
+wire [20:0] pcount_cry;
+wire [0:0] pcount_cry_0_S0;
+wire [21:21] pcount_s_0_COUT;
+wire [21:21] pcount_s_0_S1;
+wire [14:0] rcount_cry;
+wire [0:0] rcount_cry_0_S0;
+wire [15:15] rcount_s_0_COUT;
+wire [15:15] rcount_s_0_S1;
+wire [6:0] rhb_wait_cnt_cry;
+wire [0:0] rhb_wait_cnt_cry_0_S0;
+wire [7:7] rhb_wait_cnt_s_0_COUT;
+wire [7:7] rhb_wait_cnt_s_0_S1;
+wire pll_lock ;
+wire rtc_ctrl4_0_a3_1 ;
+wire un13_lock_20 ;
+wire ppul_sync_p2 ;
+wire ppul_sync_p1 ;
+wire un1_pcount_diff_1_axb_20 ;
+wire un13_lock_19 ;
+wire un1_pcount_diff_1_axb_19 ;
+wire un13_lock_18 ;
+wire un1_pcount_diff_1_axb_18 ;
+wire un13_lock_17 ;
+wire un1_pcount_diff_1_cry_17_0_RNO ;
+wire un13_lock_16 ;
+wire un1_pcount_diff_1_axb_16 ;
+wire un13_lock_15 ;
+wire un1_pcount_diff_1_axb_15 ;
+wire un13_lock_14 ;
+wire un1_pcount_diff_1_axb_14 ;
+wire un13_lock_13 ;
+wire un1_pcount_diff_1_axb_13 ;
+wire un13_lock_12 ;
+wire un1_pcount_diff_1_axb_12 ;
+wire un13_lock_11 ;
+wire un1_pcount_diff_1_axb_11 ;
+wire un13_lock_10 ;
+wire un1_pcount_diff_1_axb_10 ;
+wire un13_lock_9 ;
+wire un1_pcount_diff_1_axb_9 ;
+wire un13_lock_8 ;
+wire un1_pcount_diff_1_axb_8 ;
+wire un13_lock_7 ;
+wire un1_pcount_diff_1_axb_7 ;
+wire un13_lock_6 ;
+wire un1_pcount_diff_1_axb_6 ;
+wire un13_lock_5 ;
+wire un1_pcount_diff_1_axb_5 ;
+wire un13_lock_4 ;
+wire un1_pcount_diff_1_axb_4 ;
+wire un13_lock_3 ;
+wire un1_pcount_diff_1_axb_3 ;
+wire un13_lock_2 ;
+wire un1_pcount_diff_1_axb_2 ;
+wire un13_lock_1 ;
+wire un1_pcount_diff_1_axb_1 ;
+wire un13_lock_21 ;
+wire ppul_sync_p3 ;
+wire N_7 ;
+wire un13_lock_0 ;
+wire rtc_ctrl4 ;
+wire rtc_ctrl ;
+wire VCC ;
+wire N_2085_0 ;
+wire unlock_5 ;
+wire unlock_1_sqmuxa_i ;
+wire unlock ;
+wire unlock_QN ;
+wire N_95_i ;
+wire N_97_i ;
+wire rtc_pul ;
+wire rtc_pul_p1 ;
+wire rtc_pul_p1_QN ;
+wire rtc_pul5 ;
+wire rtc_pul_QN ;
+wire rtc_ctrl_QN ;
+wire rstat_pclk_2 ;
+wire rstat_pclk ;
+wire rstat_pclk_QN ;
+wire rhb_sync_p1 ;
+wire rhb_sync_p2 ;
+wire rhb_sync_p2_QN ;
+wire rhb_sync ;
+wire rhb_sync_p1_QN ;
+wire ppul_sync_p3_QN ;
+wire ppul_sync_p2_QN ;
+wire ppul_sync ;
+wire ppul_sync_p1_QN ;
+wire N_53_i ;
+wire pll_lock_QN ;
+wire phb ;
+wire phb_QN ;
+wire pdiff_sync ;
+wire pdiff_sync_p1 ;
+wire pdiff_sync_p1_QN ;
+wire un1_pcount_diff_1_cry_1_0_S0 ;
+wire un1_pcount_diff_1_cry_1_0_S1 ;
+wire un1_pcount_diff_1_cry_3_0_S0 ;
+wire un1_pcount_diff_1_cry_3_0_S1 ;
+wire un1_pcount_diff_1_cry_5_0_S0 ;
+wire un1_pcount_diff_1_cry_5_0_S1 ;
+wire un1_pcount_diff_1_cry_7_0_S0 ;
+wire un1_pcount_diff_1_cry_7_0_S1 ;
+wire un1_pcount_diff_1_cry_9_0_S0 ;
+wire un1_pcount_diff_1_cry_9_0_S1 ;
+wire un1_pcount_diff_1_cry_11_0_S0 ;
+wire un1_pcount_diff_1_cry_11_0_S1 ;
+wire un1_pcount_diff_1_cry_13_0_S0 ;
+wire un1_pcount_diff_1_cry_13_0_S1 ;
+wire un1_pcount_diff_1_cry_15_0_S0 ;
+wire un1_pcount_diff_1_cry_15_0_S1 ;
+wire un1_pcount_diff_1_cry_17_0_S0 ;
+wire un1_pcount_diff_1_cry_17_0_S1 ;
+wire un1_pcount_diff_1_cry_19_0_S0 ;
+wire un1_pcount_diff_1_cry_19_0_S1 ;
+wire un1_pcount_diff_1_s_21_0_S0 ;
+wire lock_5 ;
+wire lock_1_sqmuxa_i ;
+wire lock ;
+wire lock_QN ;
+wire N_98 ;
+wire rtc_pul5_0_o3 ;
+wire rtc_pul5_0_a3_6 ;
+wire rtc_pul5_0_a3_7 ;
+wire un1_rcount_1_0_a3 ;
+wire rhb_wait_cnt12 ;
+wire un1_rhb_wait_cnt_4 ;
+wire un1_rhb_wait_cnt_5 ;
+wire N_99 ;
+wire rtc_ctrl4_0_a3_12_4 ;
+wire rtc_ctrl4_0_a3_12_5 ;
+wire rtc_ctrl4_10 ;
+wire un1_rcount_1_0_a3_1 ;
+wire N_6 ;
+wire rtc_pul5_0_a3_5 ;
+wire N_8 ;
+wire un13_unlock_cry_21 ;
+wire un13_lock_cry_21_i ;
+wire rhb_wait_cnt_scalar ;
+wire un1_pcount_diff_1_cry_0 ;
+wire un1_pcount_diff_1_cry_0_0_S0 ;
+wire un1_pcount_diff_1_cry_0_0_S1 ;
+wire un1_pcount_diff_1_cry_2 ;
+wire un1_pcount_diff_1_cry_4 ;
+wire un1_pcount_diff_1_cry_6 ;
+wire un1_pcount_diff_1_cry_8 ;
+wire un1_pcount_diff_1_cry_10 ;
+wire un1_pcount_diff_1_cry_12 ;
+wire un1_pcount_diff_1_cry_14 ;
+wire un1_pcount_diff_1_cry_16 ;
+wire un1_pcount_diff_1_cry_18 ;
+wire un1_pcount_diff_1_cry_20 ;
+wire un1_pcount_diff_1_s_21_0_COUT ;
+wire un1_pcount_diff_1_s_21_0_S1 ;
+wire un13_lock_cry_0 ;
+wire un13_lock_cry_0_0_S0 ;
+wire un13_lock_cry_0_0_S1 ;
+wire un13_lock_cry_2 ;
+wire un13_lock_cry_1_0_S0 ;
+wire un13_lock_cry_1_0_S1 ;
+wire un13_lock_cry_4 ;
+wire un13_lock_cry_3_0_S0 ;
+wire un13_lock_cry_3_0_S1 ;
+wire un13_lock_cry_6 ;
+wire un13_lock_cry_5_0_S0 ;
+wire un13_lock_cry_5_0_S1 ;
+wire un13_lock_cry_8 ;
+wire un13_lock_cry_7_0_S0 ;
+wire un13_lock_cry_7_0_S1 ;
+wire un13_lock_cry_10 ;
+wire un13_lock_cry_9_0_S0 ;
+wire un13_lock_cry_9_0_S1 ;
+wire un13_lock_cry_12 ;
+wire un13_lock_cry_11_0_S0 ;
+wire un13_lock_cry_11_0_S1 ;
+wire un13_lock_cry_14 ;
+wire un13_lock_cry_13_0_S0 ;
+wire un13_lock_cry_13_0_S1 ;
+wire un13_lock_cry_16 ;
+wire un13_lock_cry_15_0_S0 ;
+wire un13_lock_cry_15_0_S1 ;
+wire un13_lock_cry_18 ;
+wire un13_lock_cry_17_0_S0 ;
+wire un13_lock_cry_17_0_S1 ;
+wire un13_lock_cry_20 ;
+wire un13_lock_cry_19_0_S0 ;
+wire un13_lock_cry_19_0_S1 ;
+wire un13_lock_cry_21_0_COUT ;
+wire un13_lock_cry_21_0_S0 ;
+wire un13_unlock_cry_0 ;
+wire un13_unlock_cry_0_0_S0 ;
+wire un13_unlock_cry_0_0_S1 ;
+wire un13_unlock_cry_2 ;
+wire un13_unlock_cry_1_0_S0 ;
+wire un13_unlock_cry_1_0_S1 ;
+wire un13_unlock_cry_4 ;
+wire un13_unlock_cry_3_0_S0 ;
+wire un13_unlock_cry_3_0_S1 ;
+wire un13_unlock_cry_6 ;
+wire un13_unlock_cry_5_0_S0 ;
+wire un13_unlock_cry_5_0_S1 ;
+wire un13_unlock_cry_8 ;
+wire un13_unlock_cry_7_0_S0 ;
+wire un13_unlock_cry_7_0_S1 ;
+wire un13_unlock_cry_10 ;
+wire un13_unlock_cry_9_0_S0 ;
+wire un13_unlock_cry_9_0_S1 ;
+wire un13_unlock_cry_12 ;
+wire un13_unlock_cry_11_0_S0 ;
+wire un13_unlock_cry_11_0_S1 ;
+wire un13_unlock_cry_14 ;
+wire un13_unlock_cry_13_0_S0 ;
+wire un13_unlock_cry_13_0_S1 ;
+wire un13_unlock_cry_16 ;
+wire un13_unlock_cry_15_0_S0 ;
+wire un13_unlock_cry_15_0_S1 ;
+wire un13_unlock_cry_18 ;
+wire un13_unlock_cry_17_0_S0 ;
+wire un13_unlock_cry_17_0_S1 ;
+wire un13_unlock_cry_20 ;
+wire un13_unlock_cry_19_0_S0 ;
+wire un13_unlock_cry_19_0_S1 ;
+wire un13_unlock_cry_21_0_COUT ;
+wire un13_unlock_cry_21_0_S0 ;
+wire N_21 ;
+wire N_20 ;
+wire N_19 ;
+wire N_18 ;
+wire N_14 ;
+wire GND ;
+wire N_1 ;
+wire N_2 ;
+wire N_3 ;
+wire N_4 ;
+wire N_5 ;
+wire N_9 ;
+  INV phb_RNO (
+       .A(phb_cnt[2]),
+       .Z(phb_cnt_i[2])
+);
+  INV \phb_cnt_RNO[0]  (
+       .A(phb_cnt[0]),
+       .Z(phb_cnt_i[0])
+);
+  INV pll_lock_RNI6JK9 (
+       .A(pll_lock),
+       .Z(pll_lock_i)
+);
+  LUT4 rtc_ctrl4_0_a3_RNO (
+       .A(rcount[2]),
+       .B(rcount[0]),
+       .C(rcount[5]),
+       .D(rcount[4]),
+       .Z(rtc_ctrl4_0_a3_1)
+);
+defparam rtc_ctrl4_0_a3_RNO.init=16'h2000;
+  LUT4 un1_pcount_diff_1_cry_19_0_RNO_0 (
+       .A(un13_lock_20),
+       .B(pcount[20]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_20)
+);
+defparam un1_pcount_diff_1_cry_19_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_19_0_RNO (
+       .A(un13_lock_19),
+       .B(pcount[19]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_19)
+);
+defparam un1_pcount_diff_1_cry_19_0_RNO.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_17_0_RNO_0 (
+       .A(un13_lock_18),
+       .B(pcount[18]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_18)
+);
+defparam un1_pcount_diff_1_cry_17_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_17_0_RNO_cZ (
+       .A(un13_lock_17),
+       .B(pcount[17]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_cry_17_0_RNO)
+);
+defparam un1_pcount_diff_1_cry_17_0_RNO_cZ.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_15_0_RNO_0 (
+       .A(un13_lock_16),
+       .B(pcount[16]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_16)
+);
+defparam un1_pcount_diff_1_cry_15_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_15_0_RNO (
+       .A(un13_lock_15),
+       .B(pcount[15]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_15)
+);
+defparam un1_pcount_diff_1_cry_15_0_RNO.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_13_0_RNO_0 (
+       .A(un13_lock_14),
+       .B(pcount[14]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_14)
+);
+defparam un1_pcount_diff_1_cry_13_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_13_0_RNO (
+       .A(un13_lock_13),
+       .B(pcount[13]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_13)
+);
+defparam un1_pcount_diff_1_cry_13_0_RNO.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_11_0_RNO_0 (
+       .A(un13_lock_12),
+       .B(pcount[12]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_12)
+);
+defparam un1_pcount_diff_1_cry_11_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_11_0_RNO (
+       .A(un13_lock_11),
+       .B(pcount[11]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_11)
+);
+defparam un1_pcount_diff_1_cry_11_0_RNO.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_9_0_RNO_0 (
+       .A(un13_lock_10),
+       .B(pcount[10]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_10)
+);
+defparam un1_pcount_diff_1_cry_9_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_9_0_RNO (
+       .A(un13_lock_9),
+       .B(pcount[9]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_9)
+);
+defparam un1_pcount_diff_1_cry_9_0_RNO.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_7_0_RNO_0 (
+       .A(un13_lock_8),
+       .B(pcount[8]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_8)
+);
+defparam un1_pcount_diff_1_cry_7_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_7_0_RNO (
+       .A(un13_lock_7),
+       .B(pcount[7]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_7)
+);
+defparam un1_pcount_diff_1_cry_7_0_RNO.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_5_0_RNO_0 (
+       .A(un13_lock_6),
+       .B(pcount[6]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_6)
+);
+defparam un1_pcount_diff_1_cry_5_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_5_0_RNO (
+       .A(un13_lock_5),
+       .B(pcount[5]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_5)
+);
+defparam un1_pcount_diff_1_cry_5_0_RNO.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_3_0_RNO_0 (
+       .A(un13_lock_4),
+       .B(pcount[4]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_4)
+);
+defparam un1_pcount_diff_1_cry_3_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_3_0_RNO (
+       .A(un13_lock_3),
+       .B(pcount[3]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_3)
+);
+defparam un1_pcount_diff_1_cry_3_0_RNO.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_1_0_RNO_0 (
+       .A(un13_lock_2),
+       .B(pcount[2]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_2)
+);
+defparam un1_pcount_diff_1_cry_1_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_1_0_RNO (
+       .A(un13_lock_1),
+       .B(pcount[1]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_1)
+);
+defparam un1_pcount_diff_1_cry_1_0_RNO.init=16'h5355;
+  LUT4 ppul_sync_p3_RNIU65C (
+       .A(un13_lock_21),
+       .B(ppul_sync_p3),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(N_7)
+);
+defparam ppul_sync_p3_RNIU65C.init=16'h2F20;
+  LUT4 \pcount_diff_RNO[0]  (
+       .A(ppul_sync_p1),
+       .B(ppul_sync_p2),
+       .C(pcount[0]),
+       .D(un13_lock_0),
+       .Z(un1_pcount_diff_i[0])
+);
+defparam \pcount_diff_RNO[0] .init=16'hFD20;
+// @16:1304
+  LUT4 rtc_ctrl_0 (
+       .A(rtc_ctrl4),
+       .B(rtc_ctrl),
+       .C(VCC),
+       .D(VCC),
+       .Z(N_2085_0)
+);
+defparam rtc_ctrl_0.init=16'hEEEE;
+// @16:1278
+  FD1P3DX unlock_reg (
+       .D(unlock_5),
+       .SP(unlock_1_sqmuxa_i),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(unlock)
+);
+// @16:1801
+  FD1S3DX \sll_state_reg[0]  (
+       .D(N_95_i),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(sll_state[0])
+);
+// @16:1801
+  FD1S3DX \sll_state_reg[1]  (
+       .D(N_97_i),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(sll_state[1])
+);
+// @16:1304
+  FD1S3DX rtc_pul_p1_reg (
+       .D(rtc_pul),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rtc_pul_p1)
+);
+// @16:1304
+  FD1P3DX rtc_pul_reg (
+       .D(rtc_pul5),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rtc_pul)
+);
+// @16:1304
+  FD1S3DX rtc_ctrl_reg (
+       .D(N_2085_0),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rtc_ctrl)
+);
+// @16:1350
+  FD1P3DX rstat_pclk_reg (
+       .D(rstat_pclk_2),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rstat_pclk)
+);
+// @16:1350
+  FD1P3DX \rhb_wait_cnt_reg[0]  (
+       .D(rhb_wait_cnt_s[0]),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_wait_cnt[0])
+);
+// @16:1350
+  FD1P3DX \rhb_wait_cnt_reg[1]  (
+       .D(rhb_wait_cnt_s[1]),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_wait_cnt[1])
+);
+// @16:1350
+  FD1P3DX \rhb_wait_cnt_reg[2]  (
+       .D(rhb_wait_cnt_s[2]),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_wait_cnt[2])
+);
+// @16:1350
+  FD1P3DX \rhb_wait_cnt_reg[3]  (
+       .D(rhb_wait_cnt_s[3]),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_wait_cnt[3])
+);
+// @16:1350
+  FD1P3DX \rhb_wait_cnt_reg[4]  (
+       .D(rhb_wait_cnt_s[4]),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_wait_cnt[4])
+);
+// @16:1350
+  FD1P3DX \rhb_wait_cnt_reg[5]  (
+       .D(rhb_wait_cnt_s[5]),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_wait_cnt[5])
+);
+// @16:1350
+  FD1P3DX \rhb_wait_cnt_reg[6]  (
+       .D(rhb_wait_cnt_s[6]),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_wait_cnt[6])
+);
+// @16:1350
+  FD1P3DX \rhb_wait_cnt_reg[7]  (
+       .D(rhb_wait_cnt_s[7]),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_wait_cnt[7])
+);
+// @16:1350
+  FD1S3DX rhb_sync_p2_reg (
+       .D(rhb_sync_p1),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_sync_p2)
+);
+// @16:1350
+  FD1S3DX rhb_sync_p1_reg (
+       .D(rhb_sync),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_sync_p1)
+);
+// @16:1304
+  FD1S3DX \rcount_reg[0]  (
+       .D(rcount_s[0]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[0])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[1]  (
+       .D(rcount_s[1]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[1])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[2]  (
+       .D(rcount_s[2]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[2])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[3]  (
+       .D(rcount_s[3]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[3])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[4]  (
+       .D(rcount_s[4]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[4])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[5]  (
+       .D(rcount_s[5]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[5])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[6]  (
+       .D(rcount_s[6]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[6])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[7]  (
+       .D(rcount_s[7]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[7])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[8]  (
+       .D(rcount_s[8]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[8])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[9]  (
+       .D(rcount_s[9]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[9])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[10]  (
+       .D(rcount_s[10]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[10])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[11]  (
+       .D(rcount_s[11]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[11])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[12]  (
+       .D(rcount_s[12]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[12])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[13]  (
+       .D(rcount_s[13]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[13])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[14]  (
+       .D(rcount_s[14]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[14])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[15]  (
+       .D(rcount_s[15]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[15])
+);
+// @16:1408
+  FD1S3DX ppul_sync_p3_reg (
+       .D(ppul_sync_p2),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(ppul_sync_p3)
+);
+// @16:1408
+  FD1S3DX ppul_sync_p2_reg (
+       .D(ppul_sync_p1),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(ppul_sync_p2)
+);
+// @16:1408
+  FD1S3DX ppul_sync_p1_reg (
+       .D(ppul_sync),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(ppul_sync_p1)
+);
+// @16:1879
+  FD1S3DX pll_lock_reg (
+       .D(N_53_i),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(pll_lock)
+);
+// @16:1759
+  FD1S3DX \phb_cnt_reg[0]  (
+       .D(phb_cnt_i[0]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(phb_cnt[0])
+);
+// @16:1759
+  FD1S3DX \phb_cnt_reg[1]  (
+       .D(phb_cnt_RNO[1]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(phb_cnt[1])
+);
+// @16:1759
+  FD1S3DX \phb_cnt_reg[2]  (
+       .D(phb_cnt_RNO[2]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(phb_cnt[2])
+);
+// @16:1759
+  FD1S3DX phb_reg (
+       .D(phb_cnt_i[2]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(phb)
+);
+// @16:1278
+  FD1S3DX pdiff_sync_p1_reg (
+       .D(pdiff_sync),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(pdiff_sync_p1)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[0]  (
+       .D(pcount_s[0]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[0])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[0]  (
+       .D(un1_pcount_diff_i[0]),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_0)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[1]  (
+       .D(pcount_s[1]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[1])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[1]  (
+       .D(un1_pcount_diff_1_cry_1_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_1)
+);
+// @16:1759
+  FD1P3BX \pcount_diff[2]  (
+       .D(un1_pcount_diff_1_cry_1_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_2)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[2]  (
+       .D(pcount_s[2]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[2])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[3]  (
+       .D(un1_pcount_diff_1_cry_3_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_3)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[3]  (
+       .D(pcount_s[3]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[3])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[4]  (
+       .D(un1_pcount_diff_1_cry_3_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_4)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[4]  (
+       .D(pcount_s[4]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[4])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[5]  (
+       .D(un1_pcount_diff_1_cry_5_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_5)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[5]  (
+       .D(pcount_s[5]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[5])
+);
+// @16:1759
+  FD1S3DX \pcount_reg[6]  (
+       .D(pcount_s[6]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[6])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[6]  (
+       .D(un1_pcount_diff_1_cry_5_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_6)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[7]  (
+       .D(pcount_s[7]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[7])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[7]  (
+       .D(un1_pcount_diff_1_cry_7_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_7)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[8]  (
+       .D(pcount_s[8]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[8])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[8]  (
+       .D(un1_pcount_diff_1_cry_7_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_8)
+);
+// @16:1759
+  FD1P3BX \pcount_diff[9]  (
+       .D(un1_pcount_diff_1_cry_9_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_9)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[9]  (
+       .D(pcount_s[9]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[9])
+);
+// @16:1759
+  FD1S3DX \pcount_reg[10]  (
+       .D(pcount_s[10]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[10])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[10]  (
+       .D(un1_pcount_diff_1_cry_9_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_10)
+);
+// @16:1759
+  FD1P3BX \pcount_diff[11]  (
+       .D(un1_pcount_diff_1_cry_11_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_11)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[11]  (
+       .D(pcount_s[11]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[11])
+);
+// @16:1759
+  FD1S3DX \pcount_reg[12]  (
+       .D(pcount_s[12]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[12])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[12]  (
+       .D(un1_pcount_diff_1_cry_11_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_12)
+);
+// @16:1759
+  FD1P3BX \pcount_diff[13]  (
+       .D(un1_pcount_diff_1_cry_13_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_13)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[13]  (
+       .D(pcount_s[13]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[13])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[14]  (
+       .D(un1_pcount_diff_1_cry_13_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_14)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[14]  (
+       .D(pcount_s[14]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[14])
+);
+// @16:1759
+  FD1S3DX \pcount_reg[15]  (
+       .D(pcount_s[15]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[15])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[15]  (
+       .D(un1_pcount_diff_1_cry_15_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_15)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[16]  (
+       .D(pcount_s[16]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[16])
+);
+// @16:1759
+  FD1P3DX \pcount_diff[16]  (
+       .D(un1_pcount_diff_1_cry_15_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(un13_lock_16)
+);
+// @16:1759
+  FD1P3DX \pcount_diff[17]  (
+       .D(un1_pcount_diff_1_cry_17_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(un13_lock_17)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[17]  (
+       .D(pcount_s[17]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[17])
+);
+// @16:1759
+  FD1P3DX \pcount_diff[18]  (
+       .D(un1_pcount_diff_1_cry_17_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(un13_lock_18)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[18]  (
+       .D(pcount_s[18]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[18])
+);
+// @16:1759
+  FD1S3DX \pcount_reg[19]  (
+       .D(pcount_s[19]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[19])
+);
+// @16:1759
+  FD1P3DX \pcount_diff[19]  (
+       .D(un1_pcount_diff_1_cry_19_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(un13_lock_19)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[20]  (
+       .D(pcount_s[20]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[20])
+);
+// @16:1759
+  FD1P3DX \pcount_diff[20]  (
+       .D(un1_pcount_diff_1_cry_19_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(un13_lock_20)
+);
+// @16:1759
+  FD1P3DX \pcount_diff[21]  (
+       .D(un1_pcount_diff_1_s_21_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(un13_lock_21)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[21]  (
+       .D(pcount_s[21]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[21])
+);
+// @16:1278
+  FD1P3DX lock_reg (
+       .D(lock_5),
+       .SP(lock_1_sqmuxa_i),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(lock)
+);
+// @16:1739
+  FD1S3DX \genblk5.rdiff_comp_lock[2]  (
+       .D(VCC),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rdiff_comp_lock[2])
+);
+// @16:1801
+  LUT4 \sll_state_RNO[0]  (
+       .A(N_98),
+       .B(lock),
+       .C(rstat_pclk),
+       .D(sll_state[0]),
+       .Z(N_95_i)
+);
+defparam \sll_state_RNO[0] .init=16'hE050;
+// @16:1334
+  LUT4 rtc_pul5_0_0 (
+       .A(rtc_pul5_0_o3),
+       .B(rtc_pul5_0_a3_6),
+       .C(rtc_pul5_0_a3_7),
+       .D(un1_rcount_1_0_a3),
+       .Z(rtc_pul5)
+);
+defparam rtc_pul5_0_0.init=16'hFF80;
+// @16:1389
+  LUT4 rstat_pclk_2_iv (
+       .A(rhb_wait_cnt12),
+       .B(rstat_pclk),
+       .C(un1_rhb_wait_cnt_4),
+       .D(un1_rhb_wait_cnt_5),
+       .Z(rstat_pclk_2)
+);
+defparam rstat_pclk_2_iv.init=16'hAEEE;
+// @16:1801
+  LUT4 \sll_state_RNO[1]  (
+       .A(N_99),
+       .B(rstat_pclk),
+       .C(sll_state[1]),
+       .D(unlock),
+       .Z(N_97_i)
+);
+defparam \sll_state_RNO[1] .init=16'h8088;
+// @16:1328
+  LUT4 rtc_ctrl4_0_a3 (
+       .A(rtc_ctrl4_0_a3_1),
+       .B(rtc_ctrl4_0_a3_12_4),
+       .C(rtc_ctrl4_0_a3_12_5),
+       .D(rtc_ctrl4_10),
+       .Z(rtc_ctrl4)
+);
+defparam rtc_ctrl4_0_a3.init=16'h8000;
+// @16:1319
+  LUT4 un1_rcount_1_0_a3_cZ (
+       .A(rtc_ctrl4_0_a3_12_4),
+       .B(rtc_ctrl4_0_a3_12_5),
+       .C(rtc_ctrl4_10),
+       .D(un1_rcount_1_0_a3_1),
+       .Z(un1_rcount_1_0_a3)
+);
+defparam un1_rcount_1_0_a3_cZ.init=16'h8000;
+// @16:1278
+  LUT4 lock_1_sqmuxa_i_cZ (
+       .A(lock),
+       .B(pdiff_sync),
+       .C(pdiff_sync_p1),
+       .D(VCC),
+       .Z(lock_1_sqmuxa_i)
+);
+defparam lock_1_sqmuxa_i_cZ.init=16'h7575;
+// @16:1278
+  LUT4 unlock_1_sqmuxa_i_cZ (
+       .A(pdiff_sync),
+       .B(pdiff_sync_p1),
+       .C(unlock),
+       .D(VCC),
+       .Z(unlock_1_sqmuxa_i)
+);
+defparam unlock_1_sqmuxa_i_cZ.init=16'h4F4F;
+// @16:1334
+  LUT4 rtc_pul5_0_o3_cZ (
+       .A(N_6),
+       .B(rcount[1]),
+       .C(rcount[2]),
+       .D(rcount[3]),
+       .Z(rtc_pul5_0_o3)
+);
+defparam rtc_pul5_0_o3_cZ.init=16'hAAAB;
+// @16:1334
+  LUT4 rtc_pul5_0_a3_7_cZ (
+       .A(rcount[7]),
+       .B(rcount[8]),
+       .C(rtc_pul5_0_a3_5),
+       .D(VCC),
+       .Z(rtc_pul5_0_a3_7)
+);
+defparam rtc_pul5_0_a3_7_cZ.init=16'h1010;
+// @16:1801
+  LUT4 \sll_state_ns_i_m4[1]  (
+       .A(lock),
+       .B(rtc_pul),
+       .C(rtc_pul_p1),
+       .D(sll_state[1]),
+       .Z(N_99)
+);
+defparam \sll_state_ns_i_m4[1] .init=16'hEF20;
+// @16:1879
+  LUT4 pll_lock_RNO (
+       .A(sll_state[0]),
+       .B(sll_state[1]),
+       .C(VCC),
+       .D(VCC),
+       .Z(N_53_i)
+);
+defparam pll_lock_RNO.init=16'h8888;
+// @16:1776
+  LUT4 \phb_cnt_RNO_cZ[2]  (
+       .A(phb_cnt[0]),
+       .B(phb_cnt[1]),
+       .C(phb_cnt[2]),
+       .D(VCC),
+       .Z(phb_cnt_RNO[2])
+);
+defparam \phb_cnt_RNO_cZ[2] .init=16'h7878;
+// @16:1801
+  LUT4 \sll_state_ns_i_o4[0]  (
+       .A(rtc_pul),
+       .B(rtc_pul_p1),
+       .C(sll_state[1]),
+       .D(VCC),
+       .Z(N_98)
+);
+defparam \sll_state_ns_i_o4[0] .init=16'hBFBF;
+// @16:1328
+  LUT4 rtc_ctrl4_0_a3_10 (
+       .A(rcount[1]),
+       .B(rcount[3]),
+       .C(rcount[6]),
+       .D(rcount[15]),
+       .Z(rtc_ctrl4_10)
+);
+defparam rtc_ctrl4_0_a3_10.init=16'h8000;
+// @16:1393
+  LUT4 un1_rhb_wait_cnt_4_cZ (
+       .A(rhb_wait_cnt[4]),
+       .B(rhb_wait_cnt[5]),
+       .C(rhb_wait_cnt[6]),
+       .D(rhb_wait_cnt[7]),
+       .Z(un1_rhb_wait_cnt_4)
+);
+defparam un1_rhb_wait_cnt_4_cZ.init=16'h8000;
+// @16:1393
+  LUT4 un1_rhb_wait_cnt_5_cZ (
+       .A(rhb_wait_cnt[0]),
+       .B(rhb_wait_cnt[1]),
+       .C(rhb_wait_cnt[2]),
+       .D(rhb_wait_cnt[3]),
+       .Z(un1_rhb_wait_cnt_5)
+);
+defparam un1_rhb_wait_cnt_5_cZ.init=16'h8000;
+// @16:1328
+  LUT4 rtc_ctrl4_0_a3_12_4_cZ (
+       .A(rcount[11]),
+       .B(rcount[12]),
+       .C(rcount[13]),
+       .D(rcount[14]),
+       .Z(rtc_ctrl4_0_a3_12_4)
+);
+defparam rtc_ctrl4_0_a3_12_4_cZ.init=16'h8000;
+// @16:1328
+  LUT4 rtc_ctrl4_0_a3_12_5_cZ (
+       .A(rcount[7]),
+       .B(rcount[8]),
+       .C(rcount[9]),
+       .D(rcount[10]),
+       .Z(rtc_ctrl4_0_a3_12_5)
+);
+defparam rtc_ctrl4_0_a3_12_5_cZ.init=16'h8000;
+// @16:1334
+  LUT4 rtc_pul5_0_a3_5_cZ (
+       .A(rcount[6]),
+       .B(rcount[13]),
+       .C(rcount[14]),
+       .D(rcount[15]),
+       .Z(rtc_pul5_0_a3_5)
+);
+defparam rtc_pul5_0_a3_5_cZ.init=16'h0001;
+// @16:1334
+  LUT4 rtc_pul5_0_a3_6_cZ (
+       .A(rcount[9]),
+       .B(rcount[10]),
+       .C(rcount[11]),
+       .D(rcount[12]),
+       .Z(rtc_pul5_0_a3_6)
+);
+defparam rtc_pul5_0_a3_6_cZ.init=16'h0001;
+// @16:1768
+  LUT4 pcount10_0_o3 (
+       .A(ppul_sync_p1),
+       .B(ppul_sync_p2),
+       .C(VCC),
+       .D(VCC),
+       .Z(N_8)
+);
+defparam pcount10_0_o3.init=16'hDDDD;
+// @16:1776
+  LUT4 \phb_cnt_RNO_cZ[1]  (
+       .A(phb_cnt[0]),
+       .B(phb_cnt[1]),
+       .C(VCC),
+       .D(VCC),
+       .Z(phb_cnt_RNO[1])
+);
+defparam \phb_cnt_RNO_cZ[1] .init=16'h6666;
+// @16:1328
+  LUT4 rtc_ctrl4_0_o3 (
+       .A(rcount[4]),
+       .B(rcount[5]),
+       .C(VCC),
+       .D(VCC),
+       .Z(N_6)
+);
+defparam rtc_ctrl4_0_o3.init=16'h7777;
+// @16:1286
+  LUT4 unlock_5_cZ (
+       .A(pdiff_sync),
+       .B(un13_unlock_cry_21),
+       .C(VCC),
+       .D(VCC),
+       .Z(unlock_5)
+);
+defparam unlock_5_cZ.init=16'h8888;
+// @16:1292
+  LUT4 lock_5_cZ (
+       .A(pdiff_sync),
+       .B(un13_lock_cry_21_i),
+       .C(VCC),
+       .D(VCC),
+       .Z(lock_5)
+);
+defparam lock_5_cZ.init=16'h8888;
+// @16:1389
+  LUT4 rhb_wait_cnt12_cZ (
+       .A(rhb_sync_p1),
+       .B(rhb_sync_p2),
+       .C(VCC),
+       .D(VCC),
+       .Z(rhb_wait_cnt12)
+);
+defparam rhb_wait_cnt12_cZ.init=16'h2222;
+// @16:1786
+  LUT4 \un1_pcount_diff_cZ[0]  (
+       .A(un13_lock_0),
+       .B(pcount[0]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff[0])
+);
+defparam \un1_pcount_diff_cZ[0] .init=16'h5355;
+// @16:1319
+  LUT4 un1_rcount_1_0_a3_1_cZ (
+       .A(rcount[2]),
+       .B(rcount[0]),
+       .C(rcount[5]),
+       .D(rcount[4]),
+       .Z(un1_rcount_1_0_a3_1)
+);
+defparam un1_rcount_1_0_a3_1_cZ.init=16'h8000;
+// @16:1350
+  LUT4 rhb_sync_p2_RNIU9TG1 (
+       .A(un1_rhb_wait_cnt_5),
+       .B(un1_rhb_wait_cnt_4),
+       .C(rhb_sync_p2),
+       .D(rhb_sync_p1),
+       .Z(rhb_wait_cnt_scalar)
+);
+defparam rhb_sync_p2_RNIU9TG1.init=16'h7077;
+  CCU2C \pcount_cry_0[0]  (
+       .A0(VCC),
+       .B0(N_8),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_9),
+       .COUT(pcount_cry[0]),
+       .S0(pcount_cry_0_S0[0]),
+       .S1(pcount_s[0])
+);
+defparam \pcount_cry_0[0] .INIT0=16'h500c;
+defparam \pcount_cry_0[0] .INIT1=16'h8000;
+defparam \pcount_cry_0[0] .INJECT1_0="NO";
+defparam \pcount_cry_0[0] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[1]  (
+       .A0(N_8),
+       .B0(pcount[1]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[0]),
+       .COUT(pcount_cry[2]),
+       .S0(pcount_s[1]),
+       .S1(pcount_s[2])
+);
+defparam \pcount_cry_0[1] .INIT0=16'h8000;
+defparam \pcount_cry_0[1] .INIT1=16'h8000;
+defparam \pcount_cry_0[1] .INJECT1_0="NO";
+defparam \pcount_cry_0[1] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[3]  (
+       .A0(N_8),
+       .B0(pcount[3]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[4]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[2]),
+       .COUT(pcount_cry[4]),
+       .S0(pcount_s[3]),
+       .S1(pcount_s[4])
+);
+defparam \pcount_cry_0[3] .INIT0=16'h8000;
+defparam \pcount_cry_0[3] .INIT1=16'h8000;
+defparam \pcount_cry_0[3] .INJECT1_0="NO";
+defparam \pcount_cry_0[3] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[5]  (
+       .A0(N_8),
+       .B0(pcount[5]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[6]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[4]),
+       .COUT(pcount_cry[6]),
+       .S0(pcount_s[5]),
+       .S1(pcount_s[6])
+);
+defparam \pcount_cry_0[5] .INIT0=16'h8000;
+defparam \pcount_cry_0[5] .INIT1=16'h8000;
+defparam \pcount_cry_0[5] .INJECT1_0="NO";
+defparam \pcount_cry_0[5] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[7]  (
+       .A0(N_8),
+       .B0(pcount[7]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[8]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[6]),
+       .COUT(pcount_cry[8]),
+       .S0(pcount_s[7]),
+       .S1(pcount_s[8])
+);
+defparam \pcount_cry_0[7] .INIT0=16'h8000;
+defparam \pcount_cry_0[7] .INIT1=16'h8000;
+defparam \pcount_cry_0[7] .INJECT1_0="NO";
+defparam \pcount_cry_0[7] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[9]  (
+       .A0(N_8),
+       .B0(pcount[9]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[10]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[8]),
+       .COUT(pcount_cry[10]),
+       .S0(pcount_s[9]),
+       .S1(pcount_s[10])
+);
+defparam \pcount_cry_0[9] .INIT0=16'h8000;
+defparam \pcount_cry_0[9] .INIT1=16'h8000;
+defparam \pcount_cry_0[9] .INJECT1_0="NO";
+defparam \pcount_cry_0[9] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[11]  (
+       .A0(N_8),
+       .B0(pcount[11]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[12]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[10]),
+       .COUT(pcount_cry[12]),
+       .S0(pcount_s[11]),
+       .S1(pcount_s[12])
+);
+defparam \pcount_cry_0[11] .INIT0=16'h8000;
+defparam \pcount_cry_0[11] .INIT1=16'h8000;
+defparam \pcount_cry_0[11] .INJECT1_0="NO";
+defparam \pcount_cry_0[11] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[13]  (
+       .A0(N_8),
+       .B0(pcount[13]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[14]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[12]),
+       .COUT(pcount_cry[14]),
+       .S0(pcount_s[13]),
+       .S1(pcount_s[14])
+);
+defparam \pcount_cry_0[13] .INIT0=16'h8000;
+defparam \pcount_cry_0[13] .INIT1=16'h8000;
+defparam \pcount_cry_0[13] .INJECT1_0="NO";
+defparam \pcount_cry_0[13] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[15]  (
+       .A0(N_8),
+       .B0(pcount[15]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[16]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[14]),
+       .COUT(pcount_cry[16]),
+       .S0(pcount_s[15]),
+       .S1(pcount_s[16])
+);
+defparam \pcount_cry_0[15] .INIT0=16'h8000;
+defparam \pcount_cry_0[15] .INIT1=16'h8000;
+defparam \pcount_cry_0[15] .INJECT1_0="NO";
+defparam \pcount_cry_0[15] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[17]  (
+       .A0(N_8),
+       .B0(pcount[17]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[18]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[16]),
+       .COUT(pcount_cry[18]),
+       .S0(pcount_s[17]),
+       .S1(pcount_s[18])
+);
+defparam \pcount_cry_0[17] .INIT0=16'h8000;
+defparam \pcount_cry_0[17] .INIT1=16'h8000;
+defparam \pcount_cry_0[17] .INJECT1_0="NO";
+defparam \pcount_cry_0[17] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[19]  (
+       .A0(N_8),
+       .B0(pcount[19]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[20]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[18]),
+       .COUT(pcount_cry[20]),
+       .S0(pcount_s[19]),
+       .S1(pcount_s[20])
+);
+defparam \pcount_cry_0[19] .INIT0=16'h8000;
+defparam \pcount_cry_0[19] .INIT1=16'h8000;
+defparam \pcount_cry_0[19] .INJECT1_0="NO";
+defparam \pcount_cry_0[19] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_s_0[21]  (
+       .A0(N_8),
+       .B0(pcount[21]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[20]),
+       .COUT(pcount_s_0_COUT[21]),
+       .S0(pcount_s[21]),
+       .S1(pcount_s_0_S1[21])
+);
+defparam \pcount_s_0[21] .INIT0=16'h800a;
+defparam \pcount_s_0[21] .INIT1=16'h5003;
+defparam \pcount_s_0[21] .INJECT1_0="NO";
+defparam \pcount_s_0[21] .INJECT1_1="NO";
+  CCU2C \rcount_cry_0[0]  (
+       .A0(VCC),
+       .B0(un1_rcount_1_0_a3),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_rcount_1_0_a3),
+       .B1(rcount[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_5),
+       .COUT(rcount_cry[0]),
+       .S0(rcount_cry_0_S0[0]),
+       .S1(rcount_s[0])
+);
+defparam \rcount_cry_0[0] .INIT0=16'h5003;
+defparam \rcount_cry_0[0] .INIT1=16'h4000;
+defparam \rcount_cry_0[0] .INJECT1_0="NO";
+defparam \rcount_cry_0[0] .INJECT1_1="NO";
+// @16:1304
+  CCU2C \rcount_cry_0[1]  (
+       .A0(un1_rcount_1_0_a3),
+       .B0(rcount[1]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_rcount_1_0_a3),
+       .B1(rcount[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rcount_cry[0]),
+       .COUT(rcount_cry[2]),
+       .S0(rcount_s[1]),
+       .S1(rcount_s[2])
+);
+defparam \rcount_cry_0[1] .INIT0=16'h4000;
+defparam \rcount_cry_0[1] .INIT1=16'h4000;
+defparam \rcount_cry_0[1] .INJECT1_0="NO";
+defparam \rcount_cry_0[1] .INJECT1_1="NO";
+// @16:1304
+  CCU2C \rcount_cry_0[3]  (
+       .A0(un1_rcount_1_0_a3),
+       .B0(rcount[3]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_rcount_1_0_a3),
+       .B1(rcount[4]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rcount_cry[2]),
+       .COUT(rcount_cry[4]),
+       .S0(rcount_s[3]),
+       .S1(rcount_s[4])
+);
+defparam \rcount_cry_0[3] .INIT0=16'h4000;
+defparam \rcount_cry_0[3] .INIT1=16'h4000;
+defparam \rcount_cry_0[3] .INJECT1_0="NO";
+defparam \rcount_cry_0[3] .INJECT1_1="NO";
+// @16:1304
+  CCU2C \rcount_cry_0[5]  (
+       .A0(un1_rcount_1_0_a3),
+       .B0(rcount[5]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_rcount_1_0_a3),
+       .B1(rcount[6]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rcount_cry[4]),
+       .COUT(rcount_cry[6]),
+       .S0(rcount_s[5]),
+       .S1(rcount_s[6])
+);
+defparam \rcount_cry_0[5] .INIT0=16'h4000;
+defparam \rcount_cry_0[5] .INIT1=16'h4000;
+defparam \rcount_cry_0[5] .INJECT1_0="NO";
+defparam \rcount_cry_0[5] .INJECT1_1="NO";
+// @16:1304
+  CCU2C \rcount_cry_0[7]  (
+       .A0(un1_rcount_1_0_a3),
+       .B0(rcount[7]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_rcount_1_0_a3),
+       .B1(rcount[8]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rcount_cry[6]),
+       .COUT(rcount_cry[8]),
+       .S0(rcount_s[7]),
+       .S1(rcount_s[8])
+);
+defparam \rcount_cry_0[7] .INIT0=16'h4000;
+defparam \rcount_cry_0[7] .INIT1=16'h4000;
+defparam \rcount_cry_0[7] .INJECT1_0="NO";
+defparam \rcount_cry_0[7] .INJECT1_1="NO";
+// @16:1304
+  CCU2C \rcount_cry_0[9]  (
+       .A0(un1_rcount_1_0_a3),
+       .B0(rcount[9]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_rcount_1_0_a3),
+       .B1(rcount[10]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rcount_cry[8]),
+       .COUT(rcount_cry[10]),
+       .S0(rcount_s[9]),
+       .S1(rcount_s[10])
+);
+defparam \rcount_cry_0[9] .INIT0=16'h4000;
+defparam \rcount_cry_0[9] .INIT1=16'h4000;
+defparam \rcount_cry_0[9] .INJECT1_0="NO";
+defparam \rcount_cry_0[9] .INJECT1_1="NO";
+// @16:1304
+  CCU2C \rcount_cry_0[11]  (
+       .A0(un1_rcount_1_0_a3),
+       .B0(rcount[11]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_rcount_1_0_a3),
+       .B1(rcount[12]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rcount_cry[10]),
+       .COUT(rcount_cry[12]),
+       .S0(rcount_s[11]),
+       .S1(rcount_s[12])
+);
+defparam \rcount_cry_0[11] .INIT0=16'h4000;
+defparam \rcount_cry_0[11] .INIT1=16'h4000;
+defparam \rcount_cry_0[11] .INJECT1_0="NO";
+defparam \rcount_cry_0[11] .INJECT1_1="NO";
+// @16:1304
+  CCU2C \rcount_cry_0[13]  (
+       .A0(un1_rcount_1_0_a3),
+       .B0(rcount[13]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_rcount_1_0_a3),
+       .B1(rcount[14]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rcount_cry[12]),
+       .COUT(rcount_cry[14]),
+       .S0(rcount_s[13]),
+       .S1(rcount_s[14])
+);
+defparam \rcount_cry_0[13] .INIT0=16'h4000;
+defparam \rcount_cry_0[13] .INIT1=16'h4000;
+defparam \rcount_cry_0[13] .INJECT1_0="NO";
+defparam \rcount_cry_0[13] .INJECT1_1="NO";
+// @16:1304
+  CCU2C \rcount_s_0[15]  (
+       .A0(un1_rcount_1_0_a3),
+       .B0(rcount[15]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rcount_cry[14]),
+       .COUT(rcount_s_0_COUT[15]),
+       .S0(rcount_s[15]),
+       .S1(rcount_s_0_S1[15])
+);
+defparam \rcount_s_0[15] .INIT0=16'h4005;
+defparam \rcount_s_0[15] .INIT1=16'h5003;
+defparam \rcount_s_0[15] .INJECT1_0="NO";
+defparam \rcount_s_0[15] .INJECT1_1="NO";
+  CCU2C \rhb_wait_cnt_cry_0[0]  (
+       .A0(VCC),
+       .B0(rhb_wait_cnt_scalar),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rhb_wait_cnt_scalar),
+       .B1(rhb_wait_cnt[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_4),
+       .COUT(rhb_wait_cnt_cry[0]),
+       .S0(rhb_wait_cnt_cry_0_S0[0]),
+       .S1(rhb_wait_cnt_s[0])
+);
+defparam \rhb_wait_cnt_cry_0[0] .INIT0=16'h500c;
+defparam \rhb_wait_cnt_cry_0[0] .INIT1=16'h8000;
+defparam \rhb_wait_cnt_cry_0[0] .INJECT1_0="NO";
+defparam \rhb_wait_cnt_cry_0[0] .INJECT1_1="NO";
+// @16:1350
+  CCU2C \rhb_wait_cnt_cry_0[1]  (
+       .A0(rhb_wait_cnt_scalar),
+       .B0(rhb_wait_cnt[1]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rhb_wait_cnt_scalar),
+       .B1(rhb_wait_cnt[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rhb_wait_cnt_cry[0]),
+       .COUT(rhb_wait_cnt_cry[2]),
+       .S0(rhb_wait_cnt_s[1]),
+       .S1(rhb_wait_cnt_s[2])
+);
+defparam \rhb_wait_cnt_cry_0[1] .INIT0=16'h8000;
+defparam \rhb_wait_cnt_cry_0[1] .INIT1=16'h8000;
+defparam \rhb_wait_cnt_cry_0[1] .INJECT1_0="NO";
+defparam \rhb_wait_cnt_cry_0[1] .INJECT1_1="NO";
+// @16:1350
+  CCU2C \rhb_wait_cnt_cry_0[3]  (
+       .A0(rhb_wait_cnt_scalar),
+       .B0(rhb_wait_cnt[3]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rhb_wait_cnt_scalar),
+       .B1(rhb_wait_cnt[4]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rhb_wait_cnt_cry[2]),
+       .COUT(rhb_wait_cnt_cry[4]),
+       .S0(rhb_wait_cnt_s[3]),
+       .S1(rhb_wait_cnt_s[4])
+);
+defparam \rhb_wait_cnt_cry_0[3] .INIT0=16'h8000;
+defparam \rhb_wait_cnt_cry_0[3] .INIT1=16'h8000;
+defparam \rhb_wait_cnt_cry_0[3] .INJECT1_0="NO";
+defparam \rhb_wait_cnt_cry_0[3] .INJECT1_1="NO";
+// @16:1350
+  CCU2C \rhb_wait_cnt_cry_0[5]  (
+       .A0(rhb_wait_cnt_scalar),
+       .B0(rhb_wait_cnt[5]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rhb_wait_cnt_scalar),
+       .B1(rhb_wait_cnt[6]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rhb_wait_cnt_cry[4]),
+       .COUT(rhb_wait_cnt_cry[6]),
+       .S0(rhb_wait_cnt_s[5]),
+       .S1(rhb_wait_cnt_s[6])
+);
+defparam \rhb_wait_cnt_cry_0[5] .INIT0=16'h8000;
+defparam \rhb_wait_cnt_cry_0[5] .INIT1=16'h8000;
+defparam \rhb_wait_cnt_cry_0[5] .INJECT1_0="NO";
+defparam \rhb_wait_cnt_cry_0[5] .INJECT1_1="NO";
+// @16:1350
+  CCU2C \rhb_wait_cnt_s_0[7]  (
+       .A0(rhb_wait_cnt_scalar),
+       .B0(rhb_wait_cnt[7]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rhb_wait_cnt_cry[6]),
+       .COUT(rhb_wait_cnt_s_0_COUT[7]),
+       .S0(rhb_wait_cnt_s[7]),
+       .S1(rhb_wait_cnt_s_0_S1[7])
+);
+defparam \rhb_wait_cnt_s_0[7] .INIT0=16'h800a;
+defparam \rhb_wait_cnt_s_0[7] .INIT1=16'h5003;
+defparam \rhb_wait_cnt_s_0[7] .INJECT1_0="NO";
+defparam \rhb_wait_cnt_s_0[7] .INJECT1_1="NO";
+  CCU2C un1_pcount_diff_1_cry_0_0 (
+       .A0(VCC),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff[0]),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_3),
+       .COUT(un1_pcount_diff_1_cry_0),
+       .S0(un1_pcount_diff_1_cry_0_0_S0),
+       .S1(un1_pcount_diff_1_cry_0_0_S1)
+);
+defparam un1_pcount_diff_1_cry_0_0.INIT0=16'h5003;
+defparam un1_pcount_diff_1_cry_0_0.INIT1=16'h500f;
+defparam un1_pcount_diff_1_cry_0_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_0_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_1_0 (
+       .A0(un1_pcount_diff_1_axb_1),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_2),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_0),
+       .COUT(un1_pcount_diff_1_cry_2),
+       .S0(un1_pcount_diff_1_cry_1_0_S0),
+       .S1(un1_pcount_diff_1_cry_1_0_S1)
+);
+defparam un1_pcount_diff_1_cry_1_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_1_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_1_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_1_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_3_0 (
+       .A0(un1_pcount_diff_1_axb_3),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_4),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_2),
+       .COUT(un1_pcount_diff_1_cry_4),
+       .S0(un1_pcount_diff_1_cry_3_0_S0),
+       .S1(un1_pcount_diff_1_cry_3_0_S1)
+);
+defparam un1_pcount_diff_1_cry_3_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_3_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_3_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_3_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_5_0 (
+       .A0(un1_pcount_diff_1_axb_5),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_6),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_4),
+       .COUT(un1_pcount_diff_1_cry_6),
+       .S0(un1_pcount_diff_1_cry_5_0_S0),
+       .S1(un1_pcount_diff_1_cry_5_0_S1)
+);
+defparam un1_pcount_diff_1_cry_5_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_5_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_5_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_5_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_7_0 (
+       .A0(un1_pcount_diff_1_axb_7),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_8),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_6),
+       .COUT(un1_pcount_diff_1_cry_8),
+       .S0(un1_pcount_diff_1_cry_7_0_S0),
+       .S1(un1_pcount_diff_1_cry_7_0_S1)
+);
+defparam un1_pcount_diff_1_cry_7_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_7_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_7_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_7_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_9_0 (
+       .A0(un1_pcount_diff_1_axb_9),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_10),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_8),
+       .COUT(un1_pcount_diff_1_cry_10),
+       .S0(un1_pcount_diff_1_cry_9_0_S0),
+       .S1(un1_pcount_diff_1_cry_9_0_S1)
+);
+defparam un1_pcount_diff_1_cry_9_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_9_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_9_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_9_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_11_0 (
+       .A0(un1_pcount_diff_1_axb_11),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_12),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_10),
+       .COUT(un1_pcount_diff_1_cry_12),
+       .S0(un1_pcount_diff_1_cry_11_0_S0),
+       .S1(un1_pcount_diff_1_cry_11_0_S1)
+);
+defparam un1_pcount_diff_1_cry_11_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_11_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_11_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_11_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_13_0 (
+       .A0(un1_pcount_diff_1_axb_13),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_14),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_12),
+       .COUT(un1_pcount_diff_1_cry_14),
+       .S0(un1_pcount_diff_1_cry_13_0_S0),
+       .S1(un1_pcount_diff_1_cry_13_0_S1)
+);
+defparam un1_pcount_diff_1_cry_13_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_13_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_13_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_13_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_15_0 (
+       .A0(un1_pcount_diff_1_axb_15),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_16),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_14),
+       .COUT(un1_pcount_diff_1_cry_16),
+       .S0(un1_pcount_diff_1_cry_15_0_S0),
+       .S1(un1_pcount_diff_1_cry_15_0_S1)
+);
+defparam un1_pcount_diff_1_cry_15_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_15_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_15_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_15_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_17_0 (
+       .A0(N_8),
+       .B0(rdiff_comp_lock[2]),
+       .C0(un1_pcount_diff_1_cry_17_0_RNO),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_18),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_16),
+       .COUT(un1_pcount_diff_1_cry_18),
+       .S0(un1_pcount_diff_1_cry_17_0_S0),
+       .S1(un1_pcount_diff_1_cry_17_0_S1)
+);
+defparam un1_pcount_diff_1_cry_17_0.INIT0=16'hb404;
+defparam un1_pcount_diff_1_cry_17_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_17_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_17_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_19_0 (
+       .A0(un1_pcount_diff_1_axb_19),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_20),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_18),
+       .COUT(un1_pcount_diff_1_cry_20),
+       .S0(un1_pcount_diff_1_cry_19_0_S0),
+       .S1(un1_pcount_diff_1_cry_19_0_S1)
+);
+defparam un1_pcount_diff_1_cry_19_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_19_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_19_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_19_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_s_21_0 (
+       .A0(pcount[21]),
+       .B0(un13_lock_21),
+       .C0(N_8),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_20),
+       .COUT(un1_pcount_diff_1_s_21_0_COUT),
+       .S0(un1_pcount_diff_1_s_21_0_S0),
+       .S1(un1_pcount_diff_1_s_21_0_S1)
+);
+defparam un1_pcount_diff_1_s_21_0.INIT0=16'h350a;
+defparam un1_pcount_diff_1_s_21_0.INIT1=16'h5003;
+defparam un1_pcount_diff_1_s_21_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_s_21_0.INJECT1_1="NO";
+  CCU2C un13_lock_cry_0_0 (
+       .A0(VCC),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_0),
+       .B1(rdiff_comp_lock[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_2),
+       .COUT(un13_lock_cry_0),
+       .S0(un13_lock_cry_0_0_S0),
+       .S1(un13_lock_cry_0_0_S1)
+);
+defparam un13_lock_cry_0_0.INIT0=16'h5003;
+defparam un13_lock_cry_0_0.INIT1=16'h900a;
+defparam un13_lock_cry_0_0.INJECT1_0="NO";
+defparam un13_lock_cry_0_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_1_0 (
+       .A0(un13_lock_1),
+       .B0(rdiff_comp_lock[2]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_2),
+       .B1(rdiff_comp_lock[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_0),
+       .COUT(un13_lock_cry_2),
+       .S0(un13_lock_cry_1_0_S0),
+       .S1(un13_lock_cry_1_0_S1)
+);
+defparam un13_lock_cry_1_0.INIT0=16'h900a;
+defparam un13_lock_cry_1_0.INIT1=16'h900a;
+defparam un13_lock_cry_1_0.INJECT1_0="NO";
+defparam un13_lock_cry_1_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_3_0 (
+       .A0(un13_lock_3),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_4),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_2),
+       .COUT(un13_lock_cry_4),
+       .S0(un13_lock_cry_3_0_S0),
+       .S1(un13_lock_cry_3_0_S1)
+);
+defparam un13_lock_cry_3_0.INIT0=16'h500a;
+defparam un13_lock_cry_3_0.INIT1=16'h500a;
+defparam un13_lock_cry_3_0.INJECT1_0="NO";
+defparam un13_lock_cry_3_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_5_0 (
+       .A0(un13_lock_5),
+       .B0(rdiff_comp_lock[2]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_6),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_4),
+       .COUT(un13_lock_cry_6),
+       .S0(un13_lock_cry_5_0_S0),
+       .S1(un13_lock_cry_5_0_S1)
+);
+defparam un13_lock_cry_5_0.INIT0=16'h900a;
+defparam un13_lock_cry_5_0.INIT1=16'h500a;
+defparam un13_lock_cry_5_0.INJECT1_0="NO";
+defparam un13_lock_cry_5_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_7_0 (
+       .A0(un13_lock_7),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_8),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_6),
+       .COUT(un13_lock_cry_8),
+       .S0(un13_lock_cry_7_0_S0),
+       .S1(un13_lock_cry_7_0_S1)
+);
+defparam un13_lock_cry_7_0.INIT0=16'h500a;
+defparam un13_lock_cry_7_0.INIT1=16'h500a;
+defparam un13_lock_cry_7_0.INJECT1_0="NO";
+defparam un13_lock_cry_7_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_9_0 (
+       .A0(un13_lock_9),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_10),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_8),
+       .COUT(un13_lock_cry_10),
+       .S0(un13_lock_cry_9_0_S0),
+       .S1(un13_lock_cry_9_0_S1)
+);
+defparam un13_lock_cry_9_0.INIT0=16'h500a;
+defparam un13_lock_cry_9_0.INIT1=16'h500a;
+defparam un13_lock_cry_9_0.INJECT1_0="NO";
+defparam un13_lock_cry_9_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_11_0 (
+       .A0(un13_lock_11),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_12),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_10),
+       .COUT(un13_lock_cry_12),
+       .S0(un13_lock_cry_11_0_S0),
+       .S1(un13_lock_cry_11_0_S1)
+);
+defparam un13_lock_cry_11_0.INIT0=16'h500a;
+defparam un13_lock_cry_11_0.INIT1=16'h500a;
+defparam un13_lock_cry_11_0.INJECT1_0="NO";
+defparam un13_lock_cry_11_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_13_0 (
+       .A0(un13_lock_13),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_14),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_12),
+       .COUT(un13_lock_cry_14),
+       .S0(un13_lock_cry_13_0_S0),
+       .S1(un13_lock_cry_13_0_S1)
+);
+defparam un13_lock_cry_13_0.INIT0=16'h500a;
+defparam un13_lock_cry_13_0.INIT1=16'h500a;
+defparam un13_lock_cry_13_0.INJECT1_0="NO";
+defparam un13_lock_cry_13_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_15_0 (
+       .A0(un13_lock_15),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_16),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_14),
+       .COUT(un13_lock_cry_16),
+       .S0(un13_lock_cry_15_0_S0),
+       .S1(un13_lock_cry_15_0_S1)
+);
+defparam un13_lock_cry_15_0.INIT0=16'h500a;
+defparam un13_lock_cry_15_0.INIT1=16'h500a;
+defparam un13_lock_cry_15_0.INJECT1_0="NO";
+defparam un13_lock_cry_15_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_17_0 (
+       .A0(un13_lock_17),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_18),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_16),
+       .COUT(un13_lock_cry_18),
+       .S0(un13_lock_cry_17_0_S0),
+       .S1(un13_lock_cry_17_0_S1)
+);
+defparam un13_lock_cry_17_0.INIT0=16'h500a;
+defparam un13_lock_cry_17_0.INIT1=16'h500a;
+defparam un13_lock_cry_17_0.INJECT1_0="NO";
+defparam un13_lock_cry_17_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_19_0 (
+       .A0(un13_lock_19),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_20),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_18),
+       .COUT(un13_lock_cry_20),
+       .S0(un13_lock_cry_19_0_S0),
+       .S1(un13_lock_cry_19_0_S1)
+);
+defparam un13_lock_cry_19_0.INIT0=16'h500a;
+defparam un13_lock_cry_19_0.INIT1=16'h500a;
+defparam un13_lock_cry_19_0.INJECT1_0="NO";
+defparam un13_lock_cry_19_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_21_0 (
+       .A0(un13_lock_21),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_20),
+       .COUT(un13_lock_cry_21_0_COUT),
+       .S0(un13_lock_cry_21_0_S0),
+       .S1(un13_lock_cry_21_i)
+);
+defparam un13_lock_cry_21_0.INIT0=16'h500f;
+defparam un13_lock_cry_21_0.INIT1=16'ha003;
+defparam un13_lock_cry_21_0.INJECT1_0="NO";
+defparam un13_lock_cry_21_0.INJECT1_1="NO";
+  CCU2C un13_unlock_cry_0_0 (
+       .A0(VCC),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_0),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_1),
+       .COUT(un13_unlock_cry_0),
+       .S0(un13_unlock_cry_0_0_S0),
+       .S1(un13_unlock_cry_0_0_S1)
+);
+defparam un13_unlock_cry_0_0.INIT0=16'h5003;
+defparam un13_unlock_cry_0_0.INIT1=16'h500a;
+defparam un13_unlock_cry_0_0.INJECT1_0="NO";
+defparam un13_unlock_cry_0_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_1_0 (
+       .A0(un13_lock_1),
+       .B0(rdiff_comp_lock[2]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_2),
+       .B1(rdiff_comp_lock[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_0),
+       .COUT(un13_unlock_cry_2),
+       .S0(un13_unlock_cry_1_0_S0),
+       .S1(un13_unlock_cry_1_0_S1)
+);
+defparam un13_unlock_cry_1_0.INIT0=16'h900a;
+defparam un13_unlock_cry_1_0.INIT1=16'h900a;
+defparam un13_unlock_cry_1_0.INJECT1_0="NO";
+defparam un13_unlock_cry_1_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_3_0 (
+       .A0(un13_lock_3),
+       .B0(rdiff_comp_lock[2]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_4),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_2),
+       .COUT(un13_unlock_cry_4),
+       .S0(un13_unlock_cry_3_0_S0),
+       .S1(un13_unlock_cry_3_0_S1)
+);
+defparam un13_unlock_cry_3_0.INIT0=16'h900a;
+defparam un13_unlock_cry_3_0.INIT1=16'h500a;
+defparam un13_unlock_cry_3_0.INJECT1_0="NO";
+defparam un13_unlock_cry_3_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_5_0 (
+       .A0(un13_lock_5),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_6),
+       .B1(rdiff_comp_lock[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_4),
+       .COUT(un13_unlock_cry_6),
+       .S0(un13_unlock_cry_5_0_S0),
+       .S1(un13_unlock_cry_5_0_S1)
+);
+defparam un13_unlock_cry_5_0.INIT0=16'h500a;
+defparam un13_unlock_cry_5_0.INIT1=16'h900a;
+defparam un13_unlock_cry_5_0.INJECT1_0="NO";
+defparam un13_unlock_cry_5_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_7_0 (
+       .A0(un13_lock_7),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_8),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_6),
+       .COUT(un13_unlock_cry_8),
+       .S0(un13_unlock_cry_7_0_S0),
+       .S1(un13_unlock_cry_7_0_S1)
+);
+defparam un13_unlock_cry_7_0.INIT0=16'h500a;
+defparam un13_unlock_cry_7_0.INIT1=16'h500a;
+defparam un13_unlock_cry_7_0.INJECT1_0="NO";
+defparam un13_unlock_cry_7_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_9_0 (
+       .A0(un13_lock_9),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_10),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_8),
+       .COUT(un13_unlock_cry_10),
+       .S0(un13_unlock_cry_9_0_S0),
+       .S1(un13_unlock_cry_9_0_S1)
+);
+defparam un13_unlock_cry_9_0.INIT0=16'h500a;
+defparam un13_unlock_cry_9_0.INIT1=16'h500a;
+defparam un13_unlock_cry_9_0.INJECT1_0="NO";
+defparam un13_unlock_cry_9_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_11_0 (
+       .A0(un13_lock_11),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_12),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_10),
+       .COUT(un13_unlock_cry_12),
+       .S0(un13_unlock_cry_11_0_S0),
+       .S1(un13_unlock_cry_11_0_S1)
+);
+defparam un13_unlock_cry_11_0.INIT0=16'h500a;
+defparam un13_unlock_cry_11_0.INIT1=16'h500a;
+defparam un13_unlock_cry_11_0.INJECT1_0="NO";
+defparam un13_unlock_cry_11_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_13_0 (
+       .A0(un13_lock_13),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_14),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_12),
+       .COUT(un13_unlock_cry_14),
+       .S0(un13_unlock_cry_13_0_S0),
+       .S1(un13_unlock_cry_13_0_S1)
+);
+defparam un13_unlock_cry_13_0.INIT0=16'h500a;
+defparam un13_unlock_cry_13_0.INIT1=16'h500a;
+defparam un13_unlock_cry_13_0.INJECT1_0="NO";
+defparam un13_unlock_cry_13_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_15_0 (
+       .A0(un13_lock_15),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_16),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_14),
+       .COUT(un13_unlock_cry_16),
+       .S0(un13_unlock_cry_15_0_S0),
+       .S1(un13_unlock_cry_15_0_S1)
+);
+defparam un13_unlock_cry_15_0.INIT0=16'h500a;
+defparam un13_unlock_cry_15_0.INIT1=16'h500a;
+defparam un13_unlock_cry_15_0.INJECT1_0="NO";
+defparam un13_unlock_cry_15_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_17_0 (
+       .A0(un13_lock_17),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_18),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_16),
+       .COUT(un13_unlock_cry_18),
+       .S0(un13_unlock_cry_17_0_S0),
+       .S1(un13_unlock_cry_17_0_S1)
+);
+defparam un13_unlock_cry_17_0.INIT0=16'h500a;
+defparam un13_unlock_cry_17_0.INIT1=16'h500a;
+defparam un13_unlock_cry_17_0.INJECT1_0="NO";
+defparam un13_unlock_cry_17_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_19_0 (
+       .A0(un13_lock_19),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_20),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_18),
+       .COUT(un13_unlock_cry_20),
+       .S0(un13_unlock_cry_19_0_S0),
+       .S1(un13_unlock_cry_19_0_S1)
+);
+defparam un13_unlock_cry_19_0.INIT0=16'h500a;
+defparam un13_unlock_cry_19_0.INIT1=16'h500a;
+defparam un13_unlock_cry_19_0.INJECT1_0="NO";
+defparam un13_unlock_cry_19_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_21_0 (
+       .A0(un13_lock_21),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_20),
+       .COUT(un13_unlock_cry_21_0_COUT),
+       .S0(un13_unlock_cry_21_0_S0),
+       .S1(un13_unlock_cry_21)
+);
+defparam un13_unlock_cry_21_0.INIT0=16'h500f;
+defparam un13_unlock_cry_21_0.INIT1=16'h5003;
+defparam un13_unlock_cry_21_0.INJECT1_0="NO";
+defparam un13_unlock_cry_21_0.INJECT1_1="NO";
+//@16:1801
+//@8:424
+// @16:1211
+  sync_0s phb_sync_inst (
+       .phb(phb),
+       .rhb_sync(rhb_sync),
+       .sli_rst(sli_rst),
+       .pll_refclki(pll_refclki)
+);
+// @16:1220
+  sync_0s_6 rtc_sync_inst (
+       .rtc_pul(rtc_pul),
+       .ppul_sync(ppul_sync),
+       .sli_rst(sli_rst),
+       .tx_pclk(tx_pclk)
+);
+// @16:1228
+  sync_0s_0 pdiff_sync_inst (
+       .ppul_sync(ppul_sync),
+       .pdiff_sync(pdiff_sync),
+       .sli_rst(sli_rst),
+       .pll_refclki(pll_refclki)
+);
+  VHI VCC_0 (
+       .Z(VCC)
+);
+// @16:865
+  VLO GND_cZ (
+       .Z(GND)
+);
+endmodule /* sgmii_ecp5sll_core_Z1_layer1 */
+
+module sgmii_ecp5rsl_core_Z2_layer1 (
+  rx_pcs_rst_c,
+  tx_pcs_rst_c,
+  tx_serdes_rst_c,
+  serdes_rst_dual_c,
+  rsl_tx_pcs_rst_c,
+  rsl_rx_serdes_rst_c,
+  rsl_serdes_rst_dual_c,
+  rsl_tx_serdes_rst_c,
+  rsl_tx_rdy,
+  pll_lock_i,
+  pll_refclki,
+  rsl_rx_rdy,
+  rsl_rst,
+  rxrefclk,
+  rsl_disable,
+  rx_serdes_rst_c,
+  rsl_rx_pcs_rst_c,
+  rst_dual_c,
+  rx_cdr_lol_s,
+  rx_los_low_s
+)
+;
+input rx_pcs_rst_c ;
+input tx_pcs_rst_c ;
+input tx_serdes_rst_c ;
+input serdes_rst_dual_c ;
+output rsl_tx_pcs_rst_c ;
+output rsl_rx_serdes_rst_c ;
+output rsl_serdes_rst_dual_c ;
+output rsl_tx_serdes_rst_c ;
+output rsl_tx_rdy ;
+input pll_lock_i ;
+input pll_refclki ;
+output rsl_rx_rdy ;
+input rsl_rst ;
+input rxrefclk ;
+input rsl_disable ;
+input rx_serdes_rst_c ;
+output rsl_rx_pcs_rst_c ;
+input rst_dual_c ;
+input rx_cdr_lol_s ;
+input rx_los_low_s ;
+wire rx_pcs_rst_c ;
+wire tx_pcs_rst_c ;
+wire tx_serdes_rst_c ;
+wire serdes_rst_dual_c ;
+wire rsl_tx_pcs_rst_c ;
+wire rsl_rx_serdes_rst_c ;
+wire rsl_serdes_rst_dual_c ;
+wire rsl_tx_serdes_rst_c ;
+wire rsl_tx_rdy ;
+wire pll_lock_i ;
+wire pll_refclki ;
+wire rsl_rx_rdy ;
+wire rsl_rst ;
+wire rxrefclk ;
+wire rsl_disable ;
+wire rx_serdes_rst_c ;
+wire rsl_rx_pcs_rst_c ;
+wire rst_dual_c ;
+wire rx_cdr_lol_s ;
+wire rx_los_low_s ;
+wire [1:0] rxs_cnt;
+wire [1:0] rxs_cnt_3;
+wire [0:0] rxpr_appd_RNO;
+wire [2:0] plol0_cnt;
+wire [2:0] plol0_cnt_3;
+wire [0:0] rxsr_appd;
+wire [1:0] rxs_cnt_QN;
+wire [3:0] rlos_db_cnt;
+wire [3:0] rlos_db_cnt_QN;
+wire [17:0] rlols0_cnt_s;
+wire [17:0] rlols0_cnt;
+wire [17:0] rlols0_cnt_QN;
+wire [3:0] rlol_db_cnt;
+wire [3:0] rlol_db_cnt_QN;
+wire [18:0] rlol1_cnt_s;
+wire [18:0] rlol1_cnt;
+wire [18:0] rlol1_cnt_QN;
+wire [11:0] rxr_wt_cnt_s;
+wire [11:0] rxr_wt_cnt;
+wire [11:0] rxr_wt_cnt_QN;
+wire [0:0] rxsr_appd_QN;
+wire [0:0] rxpr_appd;
+wire [0:0] rxpr_appd_QN;
+wire [1:0] txs_cnt;
+wire [1:0] txs_cnt_QN;
+wire [1:1] txs_cnt_RNO;
+wire [1:0] txp_cnt;
+wire [1:0] txp_cnt_QN;
+wire [1:1] txp_cnt_RNO;
+wire [19:0] plol_cnt_s;
+wire [19:0] plol_cnt;
+wire [19:0] plol_cnt_QN;
+wire [2:0] plol0_cnt_QN;
+wire [11:0] txr_wt_cnt_s;
+wire [11:0] txr_wt_cnt;
+wire [11:0] txr_wt_cnt_QN;
+wire [0:0] txpr_appd;
+wire [0:0] txpr_appd_QN;
+wire [0:0] un1_rlol_db_cnt_zero;
+wire [0:0] un1_rlos_db_cnt_zero;
+wire [0:0] un1_rlol_db_cnt_zero_bm;
+wire [0:0] un1_rlol_db_cnt_zero_am;
+wire [0:0] un1_rlos_db_cnt_zero_bm;
+wire [0:0] un1_rlos_db_cnt_zero_am;
+wire [16:0] rlol1_cnt_cry;
+wire [0:0] rlol1_cnt_cry_0_S0;
+wire [17:17] rlol1_cnt_cry_0_COUT;
+wire [16:0] rlols0_cnt_cry;
+wire [0:0] rlols0_cnt_cry_0_S0;
+wire [17:17] rlols0_cnt_s_0_COUT;
+wire [17:17] rlols0_cnt_s_0_S1;
+wire [10:0] txr_wt_cnt_cry;
+wire [0:0] txr_wt_cnt_cry_0_S0;
+wire [11:11] txr_wt_cnt_s_0_COUT;
+wire [11:11] txr_wt_cnt_s_0_S1;
+wire [10:0] rxr_wt_cnt_cry;
+wire [0:0] rxr_wt_cnt_cry_0_S0;
+wire [11:11] rxr_wt_cnt_s_0_COUT;
+wire [11:11] rxr_wt_cnt_s_0_S1;
+wire [18:0] plol_cnt_cry;
+wire [0:0] plol_cnt_cry_0_S0;
+wire [19:19] plol_cnt_s_0_COUT;
+wire [19:19] plol_cnt_s_0_S1;
+wire rxs_rst ;
+wire VCC ;
+wire dual_or_rserd_rst ;
+wire plol0_cnt9 ;
+wire waita_plol0 ;
+wire rlos_db_p1 ;
+wire rlos_db ;
+wire rxp_rst25 ;
+wire rlol_db ;
+wire un1_rui_rst_dual_c_1_1 ;
+wire rx_all_well ;
+wire un3_rx_all_well_2 ;
+wire un17_rxr_wt_tc ;
+wire un3_rx_all_well_1 ;
+wire rx_any_rst ;
+wire rxr_wt_cnt9 ;
+wire un1_rui_rst_dual_c_1_i ;
+wire rlol1_cnt_tc_1 ;
+wire rlol1_cnt_scalar ;
+wire rxr_wt_en ;
+wire rxr_wt_cnte ;
+wire rlols0_cnt_tc_1 ;
+wire un2_rlos_redge_1_i ;
+wire un18_txr_wt_tc ;
+wire tx_any_rst ;
+wire pll_lol_p2 ;
+wire un2_plol_fedge_5_i ;
+wire N_2124_0 ;
+wire waita_rlols06 ;
+wire un1_rlols0_cnt_tc ;
+wire waita_rlols0 ;
+wire waita_rlols0_QN ;
+wire wait_calib_RNO ;
+wire un1_rlos_fedge_1 ;
+wire wait_calib ;
+wire wait_calib_QN ;
+wire rxs_rst6 ;
+wire un1_rxs_cnt_tc ;
+wire rxs_rst_QN ;
+wire rxp_rst2 ;
+wire rxp_rst2_QN ;
+wire rlos_p1 ;
+wire rlos_p2 ;
+wire rlos_p2_QN ;
+wire rlos_p1_QN ;
+wire rlos_db_p1_QN ;
+wire rlos_db_cnt_axb_0 ;
+wire rlos_db_cnt_cry_1_0_S0 ;
+wire rlos_db_cnt_cry_1_0_S1 ;
+wire rlos_db_cnt_s_3_0_S0 ;
+wire un1_rlos_db_cnt_max ;
+wire rlos_db_QN ;
+wire rlols0_cnte ;
+wire rlol_p1 ;
+wire rlol_p2 ;
+wire rlol_p2_QN ;
+wire rlol_p1_QN ;
+wire rlol_db_p1 ;
+wire rlol_db_p1_QN ;
+wire rlol_db_cnt_axb_0 ;
+wire rlol_db_cnt_cry_1_0_S0 ;
+wire rlol_db_cnt_cry_1_0_S1 ;
+wire rlol_db_cnt_s_3_0_S0 ;
+wire un1_rlol_db_cnt_max ;
+wire rlol_db_QN ;
+wire rlol1_cnte ;
+wire rxsdr_appd_2 ;
+wire rxsdr_appd_4 ;
+wire rxsdr_appd_QN ;
+wire un1_dual_or_rserd_rst_2_i ;
+wire rxr_wt_en_QN ;
+wire rxdpr_appd ;
+wire rxdpr_appd_QN ;
+wire ruo_rx_rdyr_QN ;
+wire un2_rdo_serdes_rst_dual_c_2_i ;
+wire plol_fedge ;
+wire un1_plol0_cnt_tc_1_i ;
+wire waita_plol0_QN ;
+wire un1_plol_cnt_tc ;
+wire un2_plol_cnt_tc ;
+wire txs_rst ;
+wire txs_rst_QN ;
+wire N_10_i ;
+wire un9_plol0_cnt_tc ;
+wire un1_plol0_cnt_tc_1 ;
+wire txp_rst ;
+wire txp_rst_QN ;
+wire N_11_i ;
+wire pll_lol_p3 ;
+wire pll_lol_p3_QN ;
+wire pll_lol_p1 ;
+wire pll_lol_p2_QN ;
+wire pll_lol_p1_QN ;
+wire txsr_appd_2 ;
+wire txsr_appd_4 ;
+wire txsr_appd_QN ;
+wire un1_dual_or_serd_rst_1_1 ;
+wire un1_dual_or_serd_rst_1_i ;
+wire txr_wt_en ;
+wire txr_wt_en_QN ;
+wire txr_wt_cnte ;
+wire un2_plol_fedge_2 ;
+wire un2_plol_fedge_3_i ;
+wire txdpr_appd ;
+wire txdpr_appd_QN ;
+wire un2_plol_fedge_5_1 ;
+wire ruo_tx_rdyr_QN ;
+wire un2_plol_fedge_8_i ;
+wire rlos_redge ;
+wire rlols0_cnt11_0 ;
+wire plol_cnt_scalar ;
+wire rlols0_cnt_scalar ;
+wire un8_rxs_cnt_tc ;
+wire un1_txsr_appd ;
+wire un3_rx_all_well_2_1 ;
+wire un1_rxsdr_or_sr_appd ;
+wire un2_rdo_serdes_rst_dual_c_1_1 ;
+wire rlols0_cnt_tc_1_10 ;
+wire rlols0_cnt_tc_1_11 ;
+wire rlols0_cnt_tc_1_12 ;
+wire rlols0_cnt_tc_1_13 ;
+wire un1_plol_cnt_tc_11 ;
+wire un1_plol_cnt_tc_12 ;
+wire un1_plol_cnt_tc_13 ;
+wire un1_plol_cnt_tc_14 ;
+wire rlol1_cnt_tc_1_11 ;
+wire rlol1_cnt_tc_1_12 ;
+wire rlol1_cnt_tc_1_13 ;
+wire rlol1_cnt_tc_1_14 ;
+wire CO0_2 ;
+wire un18_txr_wt_tc_6 ;
+wire un18_txr_wt_tc_7 ;
+wire un18_txr_wt_tc_8 ;
+wire un17_rxr_wt_tc_6 ;
+wire un17_rxr_wt_tc_7 ;
+wire un17_rxr_wt_tc_8 ;
+wire rlols0_cnt_tc_1_9 ;
+wire un1_plol_cnt_tc_10 ;
+wire rlol1_cnt_tc_1_10 ;
+wire txr_wt_cnt_scalar ;
+wire rlos_db_cnt_cry_0 ;
+wire rlos_db_cnt_cry_0_0_S0 ;
+wire rlos_db_cnt_cry_0_0_S1 ;
+wire rlos_db_cnt_cry_2 ;
+wire rlos_db_cnt_s_3_0_COUT ;
+wire rlos_db_cnt_s_3_0_S1 ;
+wire rlol_db_cnt_cry_0 ;
+wire rlol_db_cnt_cry_0_0_S0 ;
+wire rlol_db_cnt_cry_0_0_S1 ;
+wire rlol_db_cnt_cry_2 ;
+wire rlol_db_cnt_s_3_0_COUT ;
+wire rlol_db_cnt_s_3_0_S1 ;
+wire GND ;
+wire N_1 ;
+wire N_2 ;
+wire N_3 ;
+wire N_4 ;
+wire N_5 ;
+wire N_6 ;
+wire N_7 ;
+  LUT4 \genblk2.rxs_cnt_RNO[0]  (
+       .A(rxs_rst),
+       .B(rxs_cnt[0]),
+       .C(rxs_cnt[1]),
+       .D(VCC),
+       .Z(rxs_cnt_3[0])
+);
+defparam \genblk2.rxs_cnt_RNO[0] .init=16'h2626;
+  LUT4 \genblk2.genblk3.lfor[0].rxpr_appd_RNO[0]  (
+       .A(dual_or_rserd_rst),
+       .B(rx_los_low_s),
+       .C(rx_cdr_lol_s),
+       .D(VCC),
+       .Z(rxpr_appd_RNO[0])
+);
+defparam \genblk2.genblk3.lfor[0].rxpr_appd_RNO[0] .init=16'h0101;
+  LUT4 \genblk1.plol0_cnt_RNO[1]  (
+       .A(plol0_cnt[1]),
+       .B(plol0_cnt9),
+       .C(waita_plol0),
+       .D(plol0_cnt[0]),
+       .Z(plol0_cnt_3[1])
+);
+defparam \genblk1.plol0_cnt_RNO[1] .init=16'h1222;
+  LUT4 \genblk2.rxp_rst2_RNO  (
+       .A(dual_or_rserd_rst),
+       .B(rlos_db_p1),
+       .C(rlos_db),
+       .D(VCC),
+       .Z(rxp_rst25)
+);
+defparam \genblk2.rxp_rst2_RNO .init=16'hBABA;
+  LUT4 \genblk2.genblk3.rxdpr_appd_RNO  (
+       .A(dual_or_rserd_rst),
+       .B(rlos_db),
+       .C(rlol_db),
+       .D(VCC),
+       .Z(un1_rui_rst_dual_c_1_1)
+);
+defparam \genblk2.genblk3.rxdpr_appd_RNO .init=16'h0101;
+  LUT4 \genblk2.genblk3.ruo_rx_rdyr_RNO  (
+       .A(rx_all_well),
+       .B(rst_dual_c),
+       .C(rsl_rx_pcs_rst_c),
+       .D(dual_or_rserd_rst),
+       .Z(un3_rx_all_well_2)
+);
+defparam \genblk2.genblk3.ruo_rx_rdyr_RNO .init=16'h0002;
+  LUT4 \genblk2.genblk3.rxr_wt_en_RNO  (
+       .A(un17_rxr_wt_tc),
+       .B(rx_all_well),
+       .C(dual_or_rserd_rst),
+       .D(VCC),
+       .Z(un3_rx_all_well_1)
+);
+defparam \genblk2.genblk3.rxr_wt_en_RNO .init=16'h0404;
+  LUT4 rx_any_rst_RNIFD021 (
+       .A(rx_any_rst),
+       .B(un17_rxr_wt_tc),
+       .C(rlos_db),
+       .D(rlol_db),
+       .Z(rxr_wt_cnt9)
+);
+defparam rx_any_rst_RNIFD021.init=16'hFFFE;
+  LUT4 \genblk2.genblk3.rxdpr_appd_RNO_0  (
+       .A(rst_dual_c),
+       .B(rx_all_well),
+       .C(dual_or_rserd_rst),
+       .D(VCC),
+       .Z(un1_rui_rst_dual_c_1_i)
+);
+defparam \genblk2.genblk3.rxdpr_appd_RNO_0 .init=16'hFBFB;
+  LUT4 \genblk2.rxs_rst_RNIS0OP  (
+       .A(rlol1_cnt_tc_1),
+       .B(rxs_rst),
+       .C(rlos_db_p1),
+       .D(rlos_db),
+       .Z(rlol1_cnt_scalar)
+);
+defparam \genblk2.rxs_rst_RNIS0OP .init=16'h1011;
+  LUT4 \genblk2.genblk3.rxr_wt_en_RNIQF0H1  (
+       .A(rxr_wt_en),
+       .B(rx_any_rst),
+       .C(rx_all_well),
+       .D(un17_rxr_wt_tc),
+       .Z(rxr_wt_cnte)
+);
+defparam \genblk2.genblk3.rxr_wt_en_RNIQF0H1 .init=16'hFFEF;
+  LUT4 \genblk2.rxp_rst2_RNO_0  (
+       .A(rlols0_cnt_tc_1),
+       .B(dual_or_rserd_rst),
+       .C(rlos_db_p1),
+       .D(rlos_db),
+       .Z(un2_rlos_redge_1_i)
+);
+defparam \genblk2.rxp_rst2_RNO_0 .init=16'hEFEE;
+  LUT4 \genblk1.genblk2.ruo_tx_rdyr_RNO  (
+       .A(un18_txr_wt_tc),
+       .B(tx_any_rst),
+       .C(pll_lol_p2),
+       .D(VCC),
+       .Z(un2_plol_fedge_5_i)
+);
+defparam \genblk1.genblk2.ruo_tx_rdyr_RNO .init=16'hFEFE;
+  LUT4 \genblk2.genblk3.lfor[0].rxsr_appd_RNO[0]  (
+       .A(rxsr_appd[0]),
+       .B(rx_serdes_rst_c),
+       .C(rxs_rst),
+       .D(rsl_disable),
+       .Z(N_2124_0)
+);
+defparam \genblk2.genblk3.lfor[0].rxsr_appd_RNO[0] .init=16'hEEFE;
+// @16:759
+  FD1P3DX \genblk2.waita_rlols0  (
+       .D(waita_rlols06),
+       .SP(un1_rlols0_cnt_tc),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(waita_rlols0)
+);
+// @16:656
+  FD1P3BX \genblk2.wait_calib  (
+       .D(wait_calib_RNO),
+       .SP(un1_rlos_fedge_1),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(wait_calib)
+);
+// @16:694
+  FD1P3DX \genblk2.rxs_rst  (
+       .D(rxs_rst6),
+       .SP(un1_rxs_cnt_tc),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxs_rst)
+);
+// @16:694
+  FD1S3DX \genblk2.rxs_cnt[0]  (
+       .D(rxs_cnt_3[0]),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxs_cnt[0])
+);
+// @16:694
+  FD1S3DX \genblk2.rxs_cnt[1]  (
+       .D(rxs_cnt_3[1]),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxs_cnt[1])
+);
+// @16:806
+  FD1P3BX \genblk2.rxp_rst2  (
+       .D(rxp_rst25),
+       .SP(un2_rlos_redge_1_i),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rxp_rst2)
+);
+// @16:567
+  FD1S3DX \genblk2.rlos_p2  (
+       .D(rlos_p1),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlos_p2)
+);
+// @16:567
+  FD1S3DX \genblk2.rlos_p1  (
+       .D(rx_los_low_s),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlos_p1)
+);
+// @16:567
+  FD1S3BX \genblk2.rlos_db_p1  (
+       .D(rlos_db),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlos_db_p1)
+);
+// @16:640
+  FD1S3BX \genblk2.rlos_db_cnt[0]  (
+       .D(rlos_db_cnt_axb_0),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlos_db_cnt[0])
+);
+// @16:640
+  FD1S3BX \genblk2.rlos_db_cnt[1]  (
+       .D(rlos_db_cnt_cry_1_0_S0),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlos_db_cnt[1])
+);
+// @16:640
+  FD1S3BX \genblk2.rlos_db_cnt[2]  (
+       .D(rlos_db_cnt_cry_1_0_S1),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlos_db_cnt[2])
+);
+// @16:640
+  FD1S3BX \genblk2.rlos_db_cnt[3]  (
+       .D(rlos_db_cnt_s_3_0_S0),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlos_db_cnt[3])
+);
+// @16:649
+  FD1P3BX \genblk2.rlos_db  (
+       .D(rlos_db_cnt[1]),
+       .SP(un1_rlos_db_cnt_max),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlos_db)
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[0]  (
+       .D(rlols0_cnt_s[0]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[0])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[1]  (
+       .D(rlols0_cnt_s[1]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[1])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[2]  (
+       .D(rlols0_cnt_s[2]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[2])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[3]  (
+       .D(rlols0_cnt_s[3]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[3])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[4]  (
+       .D(rlols0_cnt_s[4]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[4])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[5]  (
+       .D(rlols0_cnt_s[5]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[5])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[6]  (
+       .D(rlols0_cnt_s[6]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[6])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[7]  (
+       .D(rlols0_cnt_s[7]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[7])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[8]  (
+       .D(rlols0_cnt_s[8]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[8])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[9]  (
+       .D(rlols0_cnt_s[9]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[9])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[10]  (
+       .D(rlols0_cnt_s[10]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[10])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[11]  (
+       .D(rlols0_cnt_s[11]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[11])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[12]  (
+       .D(rlols0_cnt_s[12]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[12])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[13]  (
+       .D(rlols0_cnt_s[13]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[13])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[14]  (
+       .D(rlols0_cnt_s[14]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[14])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[15]  (
+       .D(rlols0_cnt_s[15]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[15])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[16]  (
+       .D(rlols0_cnt_s[16]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[16])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[17]  (
+       .D(rlols0_cnt_s[17]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[17])
+);
+// @16:567
+  FD1S3DX \genblk2.rlol_p2  (
+       .D(rlol_p1),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol_p2)
+);
+// @16:567
+  FD1S3DX \genblk2.rlol_p1  (
+       .D(rx_cdr_lol_s),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol_p1)
+);
+// @16:567
+  FD1S3BX \genblk2.rlol_db_p1  (
+       .D(rlol_db),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlol_db_p1)
+);
+// @16:624
+  FD1S3BX \genblk2.rlol_db_cnt[0]  (
+       .D(rlol_db_cnt_axb_0),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlol_db_cnt[0])
+);
+// @16:624
+  FD1S3BX \genblk2.rlol_db_cnt[1]  (
+       .D(rlol_db_cnt_cry_1_0_S0),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlol_db_cnt[1])
+);
+// @16:624
+  FD1S3BX \genblk2.rlol_db_cnt[2]  (
+       .D(rlol_db_cnt_cry_1_0_S1),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlol_db_cnt[2])
+);
+// @16:624
+  FD1S3BX \genblk2.rlol_db_cnt[3]  (
+       .D(rlol_db_cnt_s_3_0_S0),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlol_db_cnt[3])
+);
+// @16:633
+  FD1P3BX \genblk2.rlol_db  (
+       .D(rlol_db_cnt[1]),
+       .SP(un1_rlol_db_cnt_max),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlol_db)
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[0]  (
+       .D(rlol1_cnt_s[0]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[0])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[1]  (
+       .D(rlol1_cnt_s[1]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[1])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[2]  (
+       .D(rlol1_cnt_s[2]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[2])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[3]  (
+       .D(rlol1_cnt_s[3]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[3])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[4]  (
+       .D(rlol1_cnt_s[4]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[4])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[5]  (
+       .D(rlol1_cnt_s[5]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[5])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[6]  (
+       .D(rlol1_cnt_s[6]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[6])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[7]  (
+       .D(rlol1_cnt_s[7]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[7])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[8]  (
+       .D(rlol1_cnt_s[8]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[8])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[9]  (
+       .D(rlol1_cnt_s[9]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[9])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[10]  (
+       .D(rlol1_cnt_s[10]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[10])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[11]  (
+       .D(rlol1_cnt_s[11]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[11])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[12]  (
+       .D(rlol1_cnt_s[12]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[12])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[13]  (
+       .D(rlol1_cnt_s[13]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[13])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[14]  (
+       .D(rlol1_cnt_s[14]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[14])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[15]  (
+       .D(rlol1_cnt_s[15]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[15])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[16]  (
+       .D(rlol1_cnt_s[16]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[16])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[17]  (
+       .D(rlol1_cnt_s[17]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[17])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[18]  (
+       .D(rlol1_cnt_s[18]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[18])
+);
+// @16:865
+  FD1S3BX \genblk2.genblk3.rxsdr_appd  (
+       .D(rxsdr_appd_2),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rxsdr_appd_4)
+);
+// @16:900
+  FD1P3DX \genblk2.genblk3.rxr_wt_en  (
+       .D(un3_rx_all_well_1),
+       .SP(un1_dual_or_rserd_rst_2_i),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_en)
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[0]  (
+       .D(rxr_wt_cnt_s[0]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[0])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[1]  (
+       .D(rxr_wt_cnt_s[1]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[1])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[2]  (
+       .D(rxr_wt_cnt_s[2]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[2])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[3]  (
+       .D(rxr_wt_cnt_s[3]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[3])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[4]  (
+       .D(rxr_wt_cnt_s[4]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[4])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[5]  (
+       .D(rxr_wt_cnt_s[5]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[5])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[6]  (
+       .D(rxr_wt_cnt_s[6]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[6])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[7]  (
+       .D(rxr_wt_cnt_s[7]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[7])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[8]  (
+       .D(rxr_wt_cnt_s[8]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[8])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[9]  (
+       .D(rxr_wt_cnt_s[9]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[9])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[10]  (
+       .D(rxr_wt_cnt_s[10]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[10])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[11]  (
+       .D(rxr_wt_cnt_s[11]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[11])
+);
+// @16:871
+  FD1P3DX \genblk2.genblk3.rxdpr_appd  (
+       .D(un1_rui_rst_dual_c_1_1),
+       .SP(un1_rui_rst_dual_c_1_i),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxdpr_appd)
+);
+// @16:920
+  FD1P3DX \genblk2.genblk3.ruo_rx_rdyr  (
+       .D(un3_rx_all_well_2),
+       .SP(rxr_wt_cnt9),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rsl_rx_rdy)
+);
+// @16:882
+  FD1S3DX \genblk2.genblk3.lfor[0].rxsr_appd[0]  (
+       .D(N_2124_0),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxsr_appd[0])
+);
+// @16:888
+  FD1P3DX \genblk2.genblk3.lfor[0].rxpr_appd[0]  (
+       .D(rxpr_appd_RNO[0]),
+       .SP(un2_rdo_serdes_rst_dual_c_2_i),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxpr_appd[0])
+);
+// @16:443
+  FD1P3DX \genblk1.waita_plol0  (
+       .D(plol_fedge),
+       .SP(un1_plol0_cnt_tc_1_i),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(waita_plol0)
+);
+// @16:422
+  FD1P3DX \genblk1.txs_rst  (
+       .D(un1_plol_cnt_tc),
+       .SP(un2_plol_cnt_tc),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txs_rst)
+);
+// @16:422
+  FD1S3DX \genblk1.txs_cnt[0]  (
+       .D(N_10_i),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txs_cnt[0])
+);
+// @16:422
+  FD1S3DX \genblk1.txs_cnt[1]  (
+       .D(txs_cnt_RNO[1]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txs_cnt[1])
+);
+// @16:461
+  FD1P3DX \genblk1.txp_rst  (
+       .D(un9_plol0_cnt_tc),
+       .SP(un1_plol0_cnt_tc_1),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txp_rst)
+);
+// @16:461
+  FD1S3DX \genblk1.txp_cnt[0]  (
+       .D(N_11_i),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txp_cnt[0])
+);
+// @16:461
+  FD1S3DX \genblk1.txp_cnt[1]  (
+       .D(txp_cnt_RNO[1]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txp_cnt[1])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[0]  (
+       .D(plol_cnt_s[0]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[0])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[1]  (
+       .D(plol_cnt_s[1]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[1])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[2]  (
+       .D(plol_cnt_s[2]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[2])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[3]  (
+       .D(plol_cnt_s[3]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[3])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[4]  (
+       .D(plol_cnt_s[4]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[4])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[5]  (
+       .D(plol_cnt_s[5]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[5])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[6]  (
+       .D(plol_cnt_s[6]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[6])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[7]  (
+       .D(plol_cnt_s[7]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[7])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[8]  (
+       .D(plol_cnt_s[8]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[8])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[9]  (
+       .D(plol_cnt_s[9]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[9])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[10]  (
+       .D(plol_cnt_s[10]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[10])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[11]  (
+       .D(plol_cnt_s[11]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[11])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[12]  (
+       .D(plol_cnt_s[12]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[12])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[13]  (
+       .D(plol_cnt_s[13]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[13])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[14]  (
+       .D(plol_cnt_s[14]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[14])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[15]  (
+       .D(plol_cnt_s[15]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[15])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[16]  (
+       .D(plol_cnt_s[16]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[16])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[17]  (
+       .D(plol_cnt_s[17]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[17])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[18]  (
+       .D(plol_cnt_s[18]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[18])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[19]  (
+       .D(plol_cnt_s[19]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[19])
+);
+// @16:451
+  FD1S3DX \genblk1.plol0_cnt[0]  (
+       .D(plol0_cnt_3[0]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol0_cnt[0])
+);
+// @16:451
+  FD1S3DX \genblk1.plol0_cnt[1]  (
+       .D(plol0_cnt_3[1]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol0_cnt[1])
+);
+// @16:451
+  FD1S3DX \genblk1.plol0_cnt[2]  (
+       .D(plol0_cnt_3[2]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol0_cnt[2])
+);
+// @16:398
+  FD1S3DX \genblk1.pll_lol_p3  (
+       .D(pll_lol_p2),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(pll_lol_p3)
+);
+// @16:398
+  FD1S3DX \genblk1.pll_lol_p2  (
+       .D(pll_lol_p1),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(pll_lol_p2)
+);
+// @16:398
+  FD1S3DX \genblk1.pll_lol_p1  (
+       .D(pll_lock_i),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(pll_lol_p1)
+);
+// @16:492
+  FD1S3BX \genblk1.genblk2.txsr_appd  (
+       .D(txsr_appd_2),
+       .CK(pll_refclki),
+       .PD(rsl_rst),
+       .Q(txsr_appd_4)
+);
+// @16:519
+  FD1P3DX \genblk1.genblk2.txr_wt_en  (
+       .D(un1_dual_or_serd_rst_1_1),
+       .SP(un1_dual_or_serd_rst_1_i),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_en)
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[0]  (
+       .D(txr_wt_cnt_s[0]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[0])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[1]  (
+       .D(txr_wt_cnt_s[1]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[1])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[2]  (
+       .D(txr_wt_cnt_s[2]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[2])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[3]  (
+       .D(txr_wt_cnt_s[3]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[3])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[4]  (
+       .D(txr_wt_cnt_s[4]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[4])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[5]  (
+       .D(txr_wt_cnt_s[5]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[5])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[6]  (
+       .D(txr_wt_cnt_s[6]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[6])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[7]  (
+       .D(txr_wt_cnt_s[7]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[7])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[8]  (
+       .D(txr_wt_cnt_s[8]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[8])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[9]  (
+       .D(txr_wt_cnt_s[9]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[9])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[10]  (
+       .D(txr_wt_cnt_s[10]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[10])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[11]  (
+       .D(txr_wt_cnt_s[11]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[11])
+);
+// @16:498
+  FD1P3DX \genblk1.genblk2.txdpr_appd  (
+       .D(un2_plol_fedge_2),
+       .SP(un2_plol_fedge_3_i),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txdpr_appd)
+);
+// @16:537
+  FD1P3DX \genblk1.genblk2.ruo_tx_rdyr  (
+       .D(un2_plol_fedge_5_1),
+       .SP(un2_plol_fedge_5_i),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(rsl_tx_rdy)
+);
+// @16:509
+  FD1P3DX \genblk1.genblk2.mfor[0].txpr_appd[0]  (
+       .D(un2_plol_fedge_2),
+       .SP(un2_plol_fedge_8_i),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txpr_appd[0])
+);
+// @16:422
+  LUT4 \genblk1.txs_cnt_RNO[0]  (
+       .A(txs_cnt[0]),
+       .B(txs_rst),
+       .C(un1_plol_cnt_tc),
+       .D(VCC),
+       .Z(N_10_i)
+);
+defparam \genblk1.txs_cnt_RNO[0] .init=16'hA6A6;
+// @16:434
+  LUT4 \genblk1.txs_cnt_RNO[1]  (
+       .A(txs_cnt[0]),
+       .B(txs_cnt[1]),
+       .C(txs_rst),
+       .D(un1_plol_cnt_tc),
+       .Z(txs_cnt_RNO[1])
+);
+defparam \genblk1.txs_cnt_RNO[1] .init=16'hCC6C;
+// @16:519
+  LUT4 \genblk1.genblk2.txr_wt_en_RNO  (
+       .A(txpr_appd[0]),
+       .B(pll_lol_p2),
+       .C(un1_dual_or_serd_rst_1_1),
+       .D(rsl_tx_rdy),
+       .Z(un1_dual_or_serd_rst_1_i)
+);
+defparam \genblk1.genblk2.txr_wt_en_RNO .init=16'h0F2F;
+// @16:317
+  LUT4 \genblk2.rxs_rst6  (
+       .A(rlol_db),
+       .B(rlos_db),
+       .C(rlol1_cnt_tc_1),
+       .D(VCC),
+       .Z(rxs_rst6)
+);
+defparam \genblk2.rxs_rst6 .init=16'h2020;
+// @8:394
+  LUT4 \genblk2.wait_calib_RNIKRP81  (
+       .A(rxs_rst),
+       .B(wait_calib),
+       .C(rlol1_cnt_tc_1),
+       .D(rlos_redge),
+       .Z(rlol1_cnte)
+);
+defparam \genblk2.wait_calib_RNIKRP81 .init=16'hFFFE;
+// @8:394
+  LUT4 \genblk2.waita_rlols0_RNI266C  (
+       .A(rlols0_cnt11_0),
+       .B(waita_rlols0),
+       .C(rlols0_cnt_tc_1),
+       .D(VCC),
+       .Z(rlols0_cnte)
+);
+defparam \genblk2.waita_rlols0_RNI266C .init=16'hFEFE;
+// @16:412
+  LUT4 \genblk1.plol_cnt11_i  (
+       .A(pll_lol_p2),
+       .B(un1_plol_cnt_tc),
+       .C(rsl_tx_serdes_rst_c),
+       .D(VCC),
+       .Z(plol_cnt_scalar)
+);
+defparam \genblk1.plol_cnt11_i .init=16'h0202;
+// @16:778
+  LUT4 \genblk2.rlols0_cnt11_i  (
+       .A(rlols0_cnt11_0),
+       .B(rlols0_cnt_tc_1),
+       .C(VCC),
+       .D(VCC),
+       .Z(rlols0_cnt_scalar)
+);
+defparam \genblk2.rlols0_cnt11_i .init=16'h1111;
+// @16:317
+  LUT4 \genblk2.un1_rxs_cnt_tc  (
+       .A(rlol_db),
+       .B(rlos_db),
+       .C(un8_rxs_cnt_tc),
+       .D(rlol1_cnt_tc_1),
+       .Z(un1_rxs_cnt_tc)
+);
+defparam \genblk2.un1_rxs_cnt_tc .init=16'hFEFC;
+// @8:394
+  LUT4 \genblk2.wait_calib_RNO  (
+       .A(rlol_db),
+       .B(rlos_db),
+       .C(rlol1_cnt_tc_1),
+       .D(VCC),
+       .Z(wait_calib_RNO)
+);
+defparam \genblk2.wait_calib_RNO .init=16'hA3A3;
+// @16:509
+  LUT4 \genblk1.genblk2.mfor[0].txpr_appd_RNO[0]  (
+       .A(un1_txsr_appd),
+       .B(pll_lol_p2),
+       .C(rsl_serdes_rst_dual_c),
+       .D(rsl_tx_serdes_rst_c),
+       .Z(un2_plol_fedge_8_i)
+);
+defparam \genblk1.genblk2.mfor[0].txpr_appd_RNO[0] .init=16'hFFFE;
+// @16:900
+  LUT4 \genblk2.genblk3.rxr_wt_en_RNO_0  (
+       .A(dual_or_rserd_rst),
+       .B(un3_rx_all_well_2_1),
+       .C(un17_rxr_wt_tc),
+       .D(rx_all_well),
+       .Z(un1_dual_or_rserd_rst_2_i)
+);
+defparam \genblk2.genblk3.rxr_wt_en_RNO_0 .init=16'hFEFF;
+// @16:888
+  LUT4 \genblk2.genblk3.lfor[0].rxpr_appd_RNO_0[0]  (
+       .A(un1_rxsdr_or_sr_appd),
+       .B(un2_rdo_serdes_rst_dual_c_1_1),
+       .C(rsl_rx_serdes_rst_c),
+       .D(rsl_serdes_rst_dual_c),
+       .Z(un2_rdo_serdes_rst_dual_c_2_i)
+);
+defparam \genblk2.genblk3.lfor[0].rxpr_appd_RNO_0[0] .init=16'hFFFB;
+// @16:259
+  LUT4 \genblk1.un2_plol_cnt_tc  (
+       .A(txs_cnt[0]),
+       .B(txs_cnt[1]),
+       .C(un1_plol_cnt_tc),
+       .D(VCC),
+       .Z(un2_plol_cnt_tc)
+);
+defparam \genblk1.un2_plol_cnt_tc .init=16'hF8F8;
+// @8:394
+  LUT4 \genblk1.genblk2.txr_wt_en_RNICEBT  (
+       .A(txr_wt_en),
+       .B(un18_txr_wt_tc),
+       .C(tx_any_rst),
+       .D(VCC),
+       .Z(txr_wt_cnte)
+);
+defparam \genblk1.genblk2.txr_wt_en_RNICEBT .init=16'hFEFE;
+// @16:322
+  LUT4 \genblk2.un1_rlos_fedge_1  (
+       .A(rlos_db),
+       .B(rlos_db_p1),
+       .C(rlol1_cnt_tc_1),
+       .D(VCC),
+       .Z(un1_rlos_fedge_1)
+);
+defparam \genblk2.un1_rlos_fedge_1 .init=16'hF6F6;
+// @16:340
+  LUT4 \genblk2.un1_rlols0_cnt_tc  (
+       .A(rlols0_cnt11_0),
+       .B(waita_rlols06),
+       .C(rlols0_cnt_tc_1),
+       .D(VCC),
+       .Z(un1_rlols0_cnt_tc)
+);
+defparam \genblk2.un1_rlols0_cnt_tc .init=16'hFEFE;
+// @16:498
+  LUT4 \genblk1.genblk2.txdpr_appd_RNO  (
+       .A(pll_lol_p2),
+       .B(rsl_serdes_rst_dual_c),
+       .C(rsl_tx_serdes_rst_c),
+       .D(rst_dual_c),
+       .Z(un2_plol_fedge_3_i)
+);
+defparam \genblk1.genblk2.txdpr_appd_RNO .init=16'hFFFE;
+// @16:461
+  LUT4 \genblk1.txp_cnt_RNO[0]  (
+       .A(txp_cnt[0]),
+       .B(txp_rst),
+       .C(un9_plol0_cnt_tc),
+       .D(VCC),
+       .Z(N_11_i)
+);
+defparam \genblk1.txp_cnt_RNO[0] .init=16'hA6A6;
+// @16:282
+  LUT4 un2_plol_fedge_5_1_cZ (
+       .A(pll_lol_p2),
+       .B(tx_any_rst),
+       .C(VCC),
+       .D(VCC),
+       .Z(un2_plol_fedge_5_1)
+);
+defparam un2_plol_fedge_5_1_cZ.init=16'h1111;
+// @16:522
+  LUT4 un1_dual_or_serd_rst_1_1_cZ (
+       .A(un18_txr_wt_tc),
+       .B(rsl_serdes_rst_dual_c),
+       .C(rsl_tx_serdes_rst_c),
+       .D(VCC),
+       .Z(un1_dual_or_serd_rst_1_1)
+);
+defparam un1_dual_or_serd_rst_1_1_cZ.init=16'h0101;
+// @16:473
+  LUT4 \genblk1.txp_cnt_RNO[1]  (
+       .A(txp_cnt[0]),
+       .B(txp_cnt[1]),
+       .C(txp_rst),
+       .D(un9_plol0_cnt_tc),
+       .Z(txp_cnt_RNO[1])
+);
+defparam \genblk1.txp_cnt_RNO[1] .init=16'hCC6C;
+// @16:388
+  LUT4 rlols0_cnt_tc_1_cZ (
+       .A(rlols0_cnt_tc_1_10),
+       .B(rlols0_cnt_tc_1_11),
+       .C(rlols0_cnt_tc_1_12),
+       .D(rlols0_cnt_tc_1_13),
+       .Z(rlols0_cnt_tc_1)
+);
+defparam rlols0_cnt_tc_1_cZ.init=16'h8000;
+// @16:386
+  LUT4 \genblk1.un1_plol_cnt_tc  (
+       .A(un1_plol_cnt_tc_11),
+       .B(un1_plol_cnt_tc_12),
+       .C(un1_plol_cnt_tc_13),
+       .D(un1_plol_cnt_tc_14),
+       .Z(un1_plol_cnt_tc)
+);
+defparam \genblk1.un1_plol_cnt_tc .init=16'h8000;
+// @16:387
+  LUT4 rlol1_cnt_tc_1_cZ (
+       .A(rlol1_cnt_tc_1_11),
+       .B(rlol1_cnt_tc_1_12),
+       .C(rlol1_cnt_tc_1_13),
+       .D(rlol1_cnt_tc_1_14),
+       .Z(rlol1_cnt_tc_1)
+);
+defparam rlol1_cnt_tc_1_cZ.init=16'h8000;
+// @16:625
+  LUT4 \un1_genblk2.rlol_db_cnt_axb_0  (
+       .A(rlol_db_cnt[0]),
+       .B(un1_rlol_db_cnt_zero[0]),
+       .C(VCC),
+       .D(VCC),
+       .Z(rlol_db_cnt_axb_0)
+);
+defparam \un1_genblk2.rlol_db_cnt_axb_0 .init=16'h9999;
+// @16:641
+  LUT4 \un1_genblk2.rlos_db_cnt_axb_0  (
+       .A(rlos_db_cnt[0]),
+       .B(un1_rlos_db_cnt_zero[0]),
+       .C(VCC),
+       .D(VCC),
+       .Z(rlos_db_cnt_axb_0)
+);
+defparam \un1_genblk2.rlos_db_cnt_axb_0 .init=16'h9999;
+// @16:443
+  LUT4 \genblk1.waita_plol0_RNO  (
+       .A(pll_lol_p2),
+       .B(pll_lol_p3),
+       .C(un9_plol0_cnt_tc),
+       .D(VCC),
+       .Z(un1_plol0_cnt_tc_1_i)
+);
+defparam \genblk1.waita_plol0_RNO .init=16'hF6F6;
+// @16:514
+  LUT4 \genblk1.genblk2.mfor[0].un1_txsr_appd  (
+       .A(txdpr_appd),
+       .B(txsr_appd_4),
+       .C(rsl_tx_pcs_rst_c),
+       .D(VCC),
+       .Z(un1_txsr_appd)
+);
+defparam \genblk1.genblk2.mfor[0].un1_txsr_appd .init=16'hC8C8;
+// @16:493
+  LUT4 \genblk1.genblk2.txsr_appd_2  (
+       .A(txsr_appd_4),
+       .B(rsl_serdes_rst_dual_c),
+       .C(rsl_tx_serdes_rst_c),
+       .D(VCC),
+       .Z(txsr_appd_2)
+);
+defparam \genblk1.genblk2.txsr_appd_2 .init=16'hFEFE;
+// @16:452
+  LUT4 \genblk1.plol0_cnt_3[0]  (
+       .A(plol0_cnt9),
+       .B(plol0_cnt[0]),
+       .C(waita_plol0),
+       .D(VCC),
+       .Z(plol0_cnt_3[0])
+);
+defparam \genblk1.plol0_cnt_3[0] .init=16'h1414;
+// @16:452
+  LUT4 \genblk1.plol0_cnt_3[2]  (
+       .A(CO0_2),
+       .B(plol0_cnt9),
+       .C(plol0_cnt[1]),
+       .D(plol0_cnt[2]),
+       .Z(plol0_cnt_3[2])
+);
+defparam \genblk1.plol0_cnt_3[2] .init=16'h1320;
+// @16:535
+  LUT4 \genblk1.genblk2.un18_txr_wt_tc  (
+       .A(un18_txr_wt_tc_6),
+       .B(un18_txr_wt_tc_7),
+       .C(un18_txr_wt_tc_8),
+       .D(VCC),
+       .Z(un18_txr_wt_tc)
+);
+defparam \genblk1.genblk2.un18_txr_wt_tc .init=16'h8080;
+// @16:211
+  LUT4 un2_plol_fedge_2_cZ (
+       .A(pll_lol_p2),
+       .B(rsl_serdes_rst_dual_c),
+       .C(rsl_tx_serdes_rst_c),
+       .D(VCC),
+       .Z(un2_plol_fedge_2)
+);
+defparam un2_plol_fedge_2_cZ.init=16'h0101;
+// @16:490
+  LUT4 tx_any_rst_cZ (
+       .A(rsl_serdes_rst_dual_c),
+       .B(rsl_tx_pcs_rst_c),
+       .C(rsl_tx_serdes_rst_c),
+       .D(rst_dual_c),
+       .Z(tx_any_rst)
+);
+defparam tx_any_rst_cZ.init=16'hFFFE;
+// @16:863
+  LUT4 rx_any_rst_cZ (
+       .A(dual_or_rserd_rst),
+       .B(rsl_rx_pcs_rst_c),
+       .C(rst_dual_c),
+       .D(VCC),
+       .Z(rx_any_rst)
+);
+defparam rx_any_rst_cZ.init=16'hFEFE;
+// @16:535
+  LUT4 \genblk2.genblk3.un17_rxr_wt_tc  (
+       .A(un17_rxr_wt_tc_6),
+       .B(un17_rxr_wt_tc_7),
+       .C(un17_rxr_wt_tc_8),
+       .D(VCC),
+       .Z(un17_rxr_wt_tc)
+);
+defparam \genblk2.genblk3.un17_rxr_wt_tc .init=16'h8080;
+// @16:219
+  LUT4 \un1_rlol_db_cnt_zero_bm_cZ[0]  (
+       .A(rlol_db_cnt[0]),
+       .B(rlol_db_cnt[1]),
+       .C(rlol_db_cnt[2]),
+       .D(rlol_db_cnt[3]),
+       .Z(un1_rlol_db_cnt_zero_bm[0])
+);
+defparam \un1_rlol_db_cnt_zero_bm_cZ[0] .init=16'h8000;
+// @16:219
+  PFUMX \un1_rlol_db_cnt_zero_cZ[0]  (
+       .ALUT(un1_rlol_db_cnt_zero_bm[0]),
+       .BLUT(un1_rlol_db_cnt_zero_am[0]),
+       .C0(rlol_p2),
+       .Z(un1_rlol_db_cnt_zero[0])
+);
+// @16:219
+  LUT4 \un1_rlos_db_cnt_zero_bm_cZ[0]  (
+       .A(rlos_db_cnt[0]),
+       .B(rlos_db_cnt[1]),
+       .C(rlos_db_cnt[2]),
+       .D(rlos_db_cnt[3]),
+       .Z(un1_rlos_db_cnt_zero_bm[0])
+);
+defparam \un1_rlos_db_cnt_zero_bm_cZ[0] .init=16'h8000;
+// @16:219
+  PFUMX \un1_rlos_db_cnt_zero_cZ[0]  (
+       .ALUT(un1_rlos_db_cnt_zero_bm[0]),
+       .BLUT(un1_rlos_db_cnt_zero_am[0]),
+       .C0(rlos_p2),
+       .Z(un1_rlos_db_cnt_zero[0])
+);
+// @16:309
+  LUT4 \genblk2.un1_rlol_db_cnt_max  (
+       .A(rlol_db_cnt[0]),
+       .B(rlol_db_cnt[1]),
+       .C(rlol_db_cnt[2]),
+       .D(rlol_db_cnt[3]),
+       .Z(un1_rlol_db_cnt_max)
+);
+defparam \genblk2.un1_rlol_db_cnt_max .init=16'h8001;
+// @16:315
+  LUT4 \genblk2.un1_rlos_db_cnt_max  (
+       .A(rlos_db_cnt[0]),
+       .B(rlos_db_cnt[1]),
+       .C(rlos_db_cnt[2]),
+       .D(rlos_db_cnt[3]),
+       .Z(un1_rlos_db_cnt_max)
+);
+defparam \genblk2.un1_rlos_db_cnt_max .init=16'h8001;
+// @16:269
+  LUT4 \genblk1.un1_plol0_cnt_tc_1  (
+       .A(txp_cnt[0]),
+       .B(txp_cnt[1]),
+       .C(un9_plol0_cnt_tc),
+       .D(VCC),
+       .Z(un1_plol0_cnt_tc_1)
+);
+defparam \genblk1.un1_plol0_cnt_tc_1 .init=16'hF8F8;
+// @16:764
+  LUT4 \genblk2.waita_rlols06  (
+       .A(rlol_db),
+       .B(rlol_db_p1),
+       .C(rlos_db),
+       .D(rlos_db_p1),
+       .Z(waita_rlols06)
+);
+defparam \genblk2.waita_rlols06 .init=16'h0504;
+// @16:708
+  LUT4 \rxs_cnt_3_cZ[1]  (
+       .A(rxs_cnt[0]),
+       .B(rxs_cnt[1]),
+       .C(rxs_rst),
+       .D(VCC),
+       .Z(rxs_cnt_3[1])
+);
+defparam \rxs_cnt_3_cZ[1] .init=16'h6464;
+// @16:893
+  LUT4 \genblk2.genblk3.lfor[0].un1_rxsdr_or_sr_appd  (
+       .A(rxsr_appd[0]),
+       .B(rx_all_well),
+       .C(rxsdr_appd_4),
+       .D(rsl_rx_pcs_rst_c),
+       .Z(un1_rxsdr_or_sr_appd)
+);
+defparam \genblk2.genblk3.lfor[0].un1_rxsdr_or_sr_appd .init=16'h3200;
+// @16:388
+  LUT4 rlols0_cnt_tc_1_13_cZ (
+       .A(rlols0_cnt[16]),
+       .B(rlols0_cnt[17]),
+       .C(rlols0_cnt_tc_1_9),
+       .D(VCC),
+       .Z(rlols0_cnt_tc_1_13)
+);
+defparam rlols0_cnt_tc_1_13_cZ.init=16'h1010;
+// @16:386
+  LUT4 \genblk1.un1_plol_cnt_tc_14  (
+       .A(plol_cnt[4]),
+       .B(plol_cnt[5]),
+       .C(plol_cnt[18]),
+       .D(un1_plol_cnt_tc_10),
+       .Z(un1_plol_cnt_tc_14)
+);
+defparam \genblk1.un1_plol_cnt_tc_14 .init=16'h0100;
+// @16:387
+  LUT4 rlol1_cnt_tc_1_14_cZ (
+       .A(rlol1_cnt[11]),
+       .B(rlol1_cnt[12]),
+       .C(rlol1_cnt[18]),
+       .D(rlol1_cnt_tc_1_10),
+       .Z(rlol1_cnt_tc_1_14)
+);
+defparam rlol1_cnt_tc_1_14_cZ.init=16'h0100;
+// @16:906
+  LUT4 \genblk2.genblk3.un3_rx_all_well_2_1  (
+       .A(rxpr_appd[0]),
+       .B(rxdpr_appd),
+       .C(rsl_rx_rdy),
+       .D(VCC),
+       .Z(un3_rx_all_well_2_1)
+);
+defparam \genblk2.genblk3.un3_rx_all_well_2_1 .init=16'h0E0E;
+// @16:375
+  LUT4 rdo_serdes_rst_dual_c (
+       .A(rsl_disable),
+       .B(rsl_rst),
+       .C(serdes_rst_dual_c),
+       .D(VCC),
+       .Z(rsl_serdes_rst_dual_c)
+);
+defparam rdo_serdes_rst_dual_c.init=16'hF4F4;
+// @16:438
+  LUT4 rdo_tx_serdes_rst_c (
+       .A(rsl_disable),
+       .B(txs_rst),
+       .C(tx_serdes_rst_c),
+       .D(VCC),
+       .Z(rsl_tx_serdes_rst_c)
+);
+defparam rdo_tx_serdes_rst_c.init=16'hF4F4;
+// @16:479
+  LUT4 \rdo_tx_pcs_rst_c_1[0]  (
+       .A(rsl_disable),
+       .B(txp_rst),
+       .C(tx_pcs_rst_c),
+       .D(VCC),
+       .Z(rsl_tx_pcs_rst_c)
+);
+defparam \rdo_tx_pcs_rst_c_1[0] .init=16'hF4F4;
+// @16:743
+  LUT4 \rdo_rx_serdes_rst_c_1[0]  (
+       .A(rsl_disable),
+       .B(rxs_rst),
+       .C(rx_serdes_rst_c),
+       .D(VCC),
+       .Z(rsl_rx_serdes_rst_c)
+);
+defparam \rdo_rx_serdes_rst_c_1[0] .init=16'hF4F4;
+// @16:852
+  LUT4 \rdo_rx_pcs_rst_c_1[0]  (
+       .A(rsl_disable),
+       .B(rxp_rst2),
+       .C(rx_pcs_rst_c),
+       .D(VCC),
+       .Z(rsl_rx_pcs_rst_c)
+);
+defparam \rdo_rx_pcs_rst_c_1[0] .init=16'hF4F4;
+// @16:459
+  LUT4 \genblk1.un9_plol0_cnt_tc  (
+       .A(plol0_cnt[0]),
+       .B(plol0_cnt[1]),
+       .C(plol0_cnt[2]),
+       .D(VCC),
+       .Z(un9_plol0_cnt_tc)
+);
+defparam \genblk1.un9_plol0_cnt_tc .init=16'h1010;
+// @16:535
+  LUT4 \genblk2.genblk3.un17_rxr_wt_tc_6  (
+       .A(rxr_wt_cnt[0]),
+       .B(rxr_wt_cnt[8]),
+       .C(rxr_wt_cnt[9]),
+       .D(rxr_wt_cnt[11]),
+       .Z(un17_rxr_wt_tc_6)
+);
+defparam \genblk2.genblk3.un17_rxr_wt_tc_6 .init=16'h4000;
+// @16:535
+  LUT4 \genblk2.genblk3.un17_rxr_wt_tc_7  (
+       .A(rxr_wt_cnt[3]),
+       .B(rxr_wt_cnt[4]),
+       .C(rxr_wt_cnt[5]),
+       .D(rxr_wt_cnt[7]),
+       .Z(un17_rxr_wt_tc_7)
+);
+defparam \genblk2.genblk3.un17_rxr_wt_tc_7 .init=16'h8000;
+// @16:535
+  LUT4 \genblk2.genblk3.un17_rxr_wt_tc_8  (
+       .A(rxr_wt_cnt[1]),
+       .B(rxr_wt_cnt[2]),
+       .C(rxr_wt_cnt[6]),
+       .D(rxr_wt_cnt[10]),
+       .Z(un17_rxr_wt_tc_8)
+);
+defparam \genblk2.genblk3.un17_rxr_wt_tc_8 .init=16'h0001;
+// @16:535
+  LUT4 \genblk1.genblk2.un18_txr_wt_tc_6  (
+       .A(txr_wt_cnt[0]),
+       .B(txr_wt_cnt[8]),
+       .C(txr_wt_cnt[9]),
+       .D(txr_wt_cnt[11]),
+       .Z(un18_txr_wt_tc_6)
+);
+defparam \genblk1.genblk2.un18_txr_wt_tc_6 .init=16'h4000;
+// @16:535
+  LUT4 \genblk1.genblk2.un18_txr_wt_tc_7  (
+       .A(txr_wt_cnt[3]),
+       .B(txr_wt_cnt[4]),
+       .C(txr_wt_cnt[5]),
+       .D(txr_wt_cnt[7]),
+       .Z(un18_txr_wt_tc_7)
+);
+defparam \genblk1.genblk2.un18_txr_wt_tc_7 .init=16'h8000;
+// @16:535
+  LUT4 \genblk1.genblk2.un18_txr_wt_tc_8  (
+       .A(txr_wt_cnt[1]),
+       .B(txr_wt_cnt[2]),
+       .C(txr_wt_cnt[6]),
+       .D(txr_wt_cnt[10]),
+       .Z(un18_txr_wt_tc_8)
+);
+defparam \genblk1.genblk2.un18_txr_wt_tc_8 .init=16'h0001;
+// @16:388
+  LUT4 rlols0_cnt_tc_1_9_cZ (
+       .A(rlols0_cnt[1]),
+       .B(rlols0_cnt[2]),
+       .C(rlols0_cnt[3]),
+       .D(rlols0_cnt[4]),
+       .Z(rlols0_cnt_tc_1_9)
+);
+defparam rlols0_cnt_tc_1_9_cZ.init=16'h0001;
+// @16:388
+  LUT4 rlols0_cnt_tc_1_10_cZ (
+       .A(rlols0_cnt[0]),
+       .B(rlols0_cnt[10]),
+       .C(rlols0_cnt[14]),
+       .D(rlols0_cnt[15]),
+       .Z(rlols0_cnt_tc_1_10)
+);
+defparam rlols0_cnt_tc_1_10_cZ.init=16'h4000;
+// @16:388
+  LUT4 rlols0_cnt_tc_1_11_cZ (
+       .A(rlols0_cnt[9]),
+       .B(rlols0_cnt[11]),
+       .C(rlols0_cnt[12]),
+       .D(rlols0_cnt[13]),
+       .Z(rlols0_cnt_tc_1_11)
+);
+defparam rlols0_cnt_tc_1_11_cZ.init=16'h0001;
+// @16:388
+  LUT4 rlols0_cnt_tc_1_12_cZ (
+       .A(rlols0_cnt[5]),
+       .B(rlols0_cnt[6]),
+       .C(rlols0_cnt[7]),
+       .D(rlols0_cnt[8]),
+       .Z(rlols0_cnt_tc_1_12)
+);
+defparam rlols0_cnt_tc_1_12_cZ.init=16'h0001;
+// @16:386
+  LUT4 \genblk1.un1_plol_cnt_tc_10  (
+       .A(plol_cnt[2]),
+       .B(plol_cnt[3]),
+       .C(plol_cnt[17]),
+       .D(plol_cnt[19]),
+       .Z(un1_plol_cnt_tc_10)
+);
+defparam \genblk1.un1_plol_cnt_tc_10 .init=16'h1000;
+// @16:386
+  LUT4 \genblk1.un1_plol_cnt_tc_11  (
+       .A(plol_cnt[13]),
+       .B(plol_cnt[14]),
+       .C(plol_cnt[15]),
+       .D(plol_cnt[16]),
+       .Z(un1_plol_cnt_tc_11)
+);
+defparam \genblk1.un1_plol_cnt_tc_11 .init=16'h8000;
+// @16:386
+  LUT4 \genblk1.un1_plol_cnt_tc_12  (
+       .A(plol_cnt[7]),
+       .B(plol_cnt[8]),
+       .C(plol_cnt[9]),
+       .D(plol_cnt[11]),
+       .Z(un1_plol_cnt_tc_12)
+);
+defparam \genblk1.un1_plol_cnt_tc_12 .init=16'h8000;
+// @16:386
+  LUT4 \genblk1.un1_plol_cnt_tc_13  (
+       .A(plol_cnt[1]),
+       .B(plol_cnt[6]),
+       .C(plol_cnt[10]),
+       .D(plol_cnt[12]),
+       .Z(un1_plol_cnt_tc_13)
+);
+defparam \genblk1.un1_plol_cnt_tc_13 .init=16'h0008;
+// @16:387
+  LUT4 rlol1_cnt_tc_1_10_cZ (
+       .A(rlol1_cnt[7]),
+       .B(rlol1_cnt[8]),
+       .C(rlol1_cnt[9]),
+       .D(rlol1_cnt[10]),
+       .Z(rlol1_cnt_tc_1_10)
+);
+defparam rlol1_cnt_tc_1_10_cZ.init=16'h0001;
+// @16:387
+  LUT4 rlol1_cnt_tc_1_11_cZ (
+       .A(rlol1_cnt[3]),
+       .B(rlol1_cnt[4]),
+       .C(rlol1_cnt[5]),
+       .D(rlol1_cnt[6]),
+       .Z(rlol1_cnt_tc_1_11)
+);
+defparam rlol1_cnt_tc_1_11_cZ.init=16'h0001;
+// @16:387
+  LUT4 rlol1_cnt_tc_1_12_cZ (
+       .A(rlol1_cnt[0]),
+       .B(rlol1_cnt[1]),
+       .C(rlol1_cnt[2]),
+       .D(rlol1_cnt[17]),
+       .Z(rlol1_cnt_tc_1_12)
+);
+defparam rlol1_cnt_tc_1_12_cZ.init=16'h0100;
+// @16:387
+  LUT4 rlol1_cnt_tc_1_13_cZ (
+       .A(rlol1_cnt[13]),
+       .B(rlol1_cnt[14]),
+       .C(rlol1_cnt[15]),
+       .D(rlol1_cnt[16]),
+       .Z(rlol1_cnt_tc_1_13)
+);
+defparam rlol1_cnt_tc_1_13_cZ.init=16'h0040;
+// @16:866
+  LUT4 \genblk2.genblk3.rxsdr_appd_2  (
+       .A(rxsdr_appd_4),
+       .B(serdes_rst_dual_c),
+       .C(VCC),
+       .D(VCC),
+       .Z(rxsdr_appd_2)
+);
+defparam \genblk2.genblk3.rxsdr_appd_2 .init=16'hEEEE;
+// @16:601
+  LUT4 rx_all_well_cZ (
+       .A(rlol_db),
+       .B(rlos_db),
+       .C(VCC),
+       .D(VCC),
+       .Z(rx_all_well)
+);
+defparam rx_all_well_cZ.init=16'h1111;
+// @16:436
+  LUT4 \genblk2.un8_rxs_cnt_tc  (
+       .A(rxs_cnt[0]),
+       .B(rxs_cnt[1]),
+       .C(VCC),
+       .D(VCC),
+       .Z(un8_rxs_cnt_tc)
+);
+defparam \genblk2.un8_rxs_cnt_tc .init=16'h8888;
+// @16:441
+  LUT4 plol_fedge_cZ (
+       .A(pll_lol_p2),
+       .B(pll_lol_p3),
+       .C(VCC),
+       .D(VCC),
+       .Z(plol_fedge)
+);
+defparam plol_fedge_cZ.init=16'h4444;
+// @16:757
+  LUT4 rlos_redge_cZ (
+       .A(rlos_db),
+       .B(rlos_db_p1),
+       .C(VCC),
+       .D(VCC),
+       .Z(rlos_redge)
+);
+defparam rlos_redge_cZ.init=16'h2222;
+// @16:457
+  LUT4 \genblk1.plol0_cnt_3_RNO[2]  (
+       .A(plol0_cnt[0]),
+       .B(waita_plol0),
+       .C(VCC),
+       .D(VCC),
+       .Z(CO0_2)
+);
+defparam \genblk1.plol0_cnt_3_RNO[2] .init=16'h8888;
+// @16:891
+  LUT4 un2_rdo_serdes_rst_dual_c_1_1_cZ (
+       .A(rx_cdr_lol_s),
+       .B(rx_los_low_s),
+       .C(VCC),
+       .D(VCC),
+       .Z(un2_rdo_serdes_rst_dual_c_1_1)
+);
+defparam un2_rdo_serdes_rst_dual_c_1_1_cZ.init=16'h1111;
+// @16:219
+  LUT4 \un1_rlos_db_cnt_zero_am_cZ[0]  (
+       .A(rlos_db_cnt[0]),
+       .B(rlos_db_cnt[1]),
+       .C(rlos_db_cnt[2]),
+       .D(rlos_db_cnt[3]),
+       .Z(un1_rlos_db_cnt_zero_am[0])
+);
+defparam \un1_rlos_db_cnt_zero_am_cZ[0] .init=16'h0001;
+// @16:219
+  LUT4 \un1_rlol_db_cnt_zero_am_cZ[0]  (
+       .A(rlol_db_cnt[0]),
+       .B(rlol_db_cnt[1]),
+       .C(rlol_db_cnt[2]),
+       .D(rlol_db_cnt[3]),
+       .Z(un1_rlol_db_cnt_zero_am[0])
+);
+defparam \un1_rlol_db_cnt_zero_am_cZ[0] .init=16'h0001;
+// @16:861
+  LUT4 dual_or_rserd_rst_cZ (
+       .A(rsl_rx_serdes_rst_c),
+       .B(serdes_rst_dual_c),
+       .C(rsl_rst),
+       .D(rsl_disable),
+       .Z(dual_or_rserd_rst)
+);
+defparam dual_or_rserd_rst_cZ.init=16'hEEFE;
+// @16:454
+  LUT4 \genblk1.plol0_cnt9  (
+       .A(pll_lol_p2),
+       .B(plol0_cnt[2]),
+       .C(plol0_cnt[1]),
+       .D(plol0_cnt[0]),
+       .Z(plol0_cnt9)
+);
+defparam \genblk1.plol0_cnt9 .init=16'hAAAE;
+// @16:783
+  LUT4 \genblk2.rlols0_cnt11_0  (
+       .A(rlol_db_p1),
+       .B(rlol_db),
+       .C(rlos_db_p1),
+       .D(rlos_db),
+       .Z(rlols0_cnt11_0)
+);
+defparam \genblk2.rlols0_cnt11_0 .init=16'h4F44;
+// @16:527
+  LUT4 \genblk1.genblk2.txr_wt_cnt9_i  (
+       .A(tx_any_rst),
+       .B(un18_txr_wt_tc_8),
+       .C(un18_txr_wt_tc_7),
+       .D(un18_txr_wt_tc_6),
+       .Z(txr_wt_cnt_scalar)
+);
+defparam \genblk1.genblk2.txr_wt_cnt9_i .init=16'h1555;
+  CCU2C \genblk2.rlol1_cnt_cry_0[0]  (
+       .A0(VCC),
+       .B0(rlol1_cnt_scalar),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_7),
+       .COUT(rlol1_cnt_cry[0]),
+       .S0(rlol1_cnt_cry_0_S0[0]),
+       .S1(rlol1_cnt_s[0])
+);
+defparam \genblk2.rlol1_cnt_cry_0[0] .INIT0=16'h500c;
+defparam \genblk2.rlol1_cnt_cry_0[0] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[0] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[0] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[1]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[1]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[0]),
+       .COUT(rlol1_cnt_cry[2]),
+       .S0(rlol1_cnt_s[1]),
+       .S1(rlol1_cnt_s[2])
+);
+defparam \genblk2.rlol1_cnt_cry_0[1] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[1] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[1] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[1] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[3]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[3]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[4]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[2]),
+       .COUT(rlol1_cnt_cry[4]),
+       .S0(rlol1_cnt_s[3]),
+       .S1(rlol1_cnt_s[4])
+);
+defparam \genblk2.rlol1_cnt_cry_0[3] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[3] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[3] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[3] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[5]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[5]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[6]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[4]),
+       .COUT(rlol1_cnt_cry[6]),
+       .S0(rlol1_cnt_s[5]),
+       .S1(rlol1_cnt_s[6])
+);
+defparam \genblk2.rlol1_cnt_cry_0[5] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[5] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[5] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[5] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[7]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[7]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[8]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[6]),
+       .COUT(rlol1_cnt_cry[8]),
+       .S0(rlol1_cnt_s[7]),
+       .S1(rlol1_cnt_s[8])
+);
+defparam \genblk2.rlol1_cnt_cry_0[7] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[7] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[7] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[7] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[9]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[9]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[10]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[8]),
+       .COUT(rlol1_cnt_cry[10]),
+       .S0(rlol1_cnt_s[9]),
+       .S1(rlol1_cnt_s[10])
+);
+defparam \genblk2.rlol1_cnt_cry_0[9] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[9] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[9] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[9] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[11]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[11]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[12]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[10]),
+       .COUT(rlol1_cnt_cry[12]),
+       .S0(rlol1_cnt_s[11]),
+       .S1(rlol1_cnt_s[12])
+);
+defparam \genblk2.rlol1_cnt_cry_0[11] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[11] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[11] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[11] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[13]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[13]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[14]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[12]),
+       .COUT(rlol1_cnt_cry[14]),
+       .S0(rlol1_cnt_s[13]),
+       .S1(rlol1_cnt_s[14])
+);
+defparam \genblk2.rlol1_cnt_cry_0[13] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[13] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[13] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[13] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[15]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[15]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[16]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[14]),
+       .COUT(rlol1_cnt_cry[16]),
+       .S0(rlol1_cnt_s[15]),
+       .S1(rlol1_cnt_s[16])
+);
+defparam \genblk2.rlol1_cnt_cry_0[15] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[15] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[15] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[15] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[17]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[17]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[18]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[16]),
+       .COUT(rlol1_cnt_cry_0_COUT[17]),
+       .S0(rlol1_cnt_s[17]),
+       .S1(rlol1_cnt_s[18])
+);
+defparam \genblk2.rlol1_cnt_cry_0[17] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[17] .INIT1=16'h800a;
+defparam \genblk2.rlol1_cnt_cry_0[17] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[17] .INJECT1_1="NO";
+  CCU2C \genblk2.rlols0_cnt_cry_0[0]  (
+       .A0(VCC),
+       .B0(rlols0_cnt_scalar),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_6),
+       .COUT(rlols0_cnt_cry[0]),
+       .S0(rlols0_cnt_cry_0_S0[0]),
+       .S1(rlols0_cnt_s[0])
+);
+defparam \genblk2.rlols0_cnt_cry_0[0] .INIT0=16'h500c;
+defparam \genblk2.rlols0_cnt_cry_0[0] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[0] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[0] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[1]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[1]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[0]),
+       .COUT(rlols0_cnt_cry[2]),
+       .S0(rlols0_cnt_s[1]),
+       .S1(rlols0_cnt_s[2])
+);
+defparam \genblk2.rlols0_cnt_cry_0[1] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[1] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[1] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[1] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[3]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[3]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[4]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[2]),
+       .COUT(rlols0_cnt_cry[4]),
+       .S0(rlols0_cnt_s[3]),
+       .S1(rlols0_cnt_s[4])
+);
+defparam \genblk2.rlols0_cnt_cry_0[3] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[3] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[3] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[3] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[5]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[5]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[6]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[4]),
+       .COUT(rlols0_cnt_cry[6]),
+       .S0(rlols0_cnt_s[5]),
+       .S1(rlols0_cnt_s[6])
+);
+defparam \genblk2.rlols0_cnt_cry_0[5] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[5] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[5] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[5] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[7]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[7]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[8]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[6]),
+       .COUT(rlols0_cnt_cry[8]),
+       .S0(rlols0_cnt_s[7]),
+       .S1(rlols0_cnt_s[8])
+);
+defparam \genblk2.rlols0_cnt_cry_0[7] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[7] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[7] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[7] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[9]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[9]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[10]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[8]),
+       .COUT(rlols0_cnt_cry[10]),
+       .S0(rlols0_cnt_s[9]),
+       .S1(rlols0_cnt_s[10])
+);
+defparam \genblk2.rlols0_cnt_cry_0[9] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[9] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[9] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[9] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[11]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[11]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[12]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[10]),
+       .COUT(rlols0_cnt_cry[12]),
+       .S0(rlols0_cnt_s[11]),
+       .S1(rlols0_cnt_s[12])
+);
+defparam \genblk2.rlols0_cnt_cry_0[11] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[11] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[11] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[11] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[13]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[13]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[14]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[12]),
+       .COUT(rlols0_cnt_cry[14]),
+       .S0(rlols0_cnt_s[13]),
+       .S1(rlols0_cnt_s[14])
+);
+defparam \genblk2.rlols0_cnt_cry_0[13] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[13] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[13] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[13] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[15]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[15]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[16]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[14]),
+       .COUT(rlols0_cnt_cry[16]),
+       .S0(rlols0_cnt_s[15]),
+       .S1(rlols0_cnt_s[16])
+);
+defparam \genblk2.rlols0_cnt_cry_0[15] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[15] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[15] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[15] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_s_0[17]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[17]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[16]),
+       .COUT(rlols0_cnt_s_0_COUT[17]),
+       .S0(rlols0_cnt_s[17]),
+       .S1(rlols0_cnt_s_0_S1[17])
+);
+defparam \genblk2.rlols0_cnt_s_0[17] .INIT0=16'h800a;
+defparam \genblk2.rlols0_cnt_s_0[17] .INIT1=16'h5003;
+defparam \genblk2.rlols0_cnt_s_0[17] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_s_0[17] .INJECT1_1="NO";
+  CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[0]  (
+       .A0(VCC),
+       .B0(txr_wt_cnt_scalar),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(txr_wt_cnt_scalar),
+       .B1(txr_wt_cnt[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_5),
+       .COUT(txr_wt_cnt_cry[0]),
+       .S0(txr_wt_cnt_cry_0_S0[0]),
+       .S1(txr_wt_cnt_s[0])
+);
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[0] .INIT0=16'h500c;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[0] .INIT1=16'h8000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[0] .INJECT1_0="NO";
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[0] .INJECT1_1="NO";
+// @16:527
+  CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[1]  (
+       .A0(txr_wt_cnt_scalar),
+       .B0(txr_wt_cnt[1]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(txr_wt_cnt_scalar),
+       .B1(txr_wt_cnt[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(txr_wt_cnt_cry[0]),
+       .COUT(txr_wt_cnt_cry[2]),
+       .S0(txr_wt_cnt_s[1]),
+       .S1(txr_wt_cnt_s[2])
+);
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[1] .INIT0=16'h8000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[1] .INIT1=16'h8000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[1] .INJECT1_0="NO";
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[1] .INJECT1_1="NO";
+// @16:527
+  CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[3]  (
+       .A0(txr_wt_cnt_scalar),
+       .B0(txr_wt_cnt[3]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(txr_wt_cnt_scalar),
+       .B1(txr_wt_cnt[4]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(txr_wt_cnt_cry[2]),
+       .COUT(txr_wt_cnt_cry[4]),
+       .S0(txr_wt_cnt_s[3]),
+       .S1(txr_wt_cnt_s[4])
+);
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[3] .INIT0=16'h8000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[3] .INIT1=16'h8000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[3] .INJECT1_0="NO";
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[3] .INJECT1_1="NO";
+// @16:527
+  CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[5]  (
+       .A0(txr_wt_cnt_scalar),
+       .B0(txr_wt_cnt[5]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(txr_wt_cnt_scalar),
+       .B1(txr_wt_cnt[6]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(txr_wt_cnt_cry[4]),
+       .COUT(txr_wt_cnt_cry[6]),
+       .S0(txr_wt_cnt_s[5]),
+       .S1(txr_wt_cnt_s[6])
+);
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[5] .INIT0=16'h8000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[5] .INIT1=16'h8000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[5] .INJECT1_0="NO";
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[5] .INJECT1_1="NO";
+// @16:527
+  CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[7]  (
+       .A0(txr_wt_cnt_scalar),
+       .B0(txr_wt_cnt[7]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(txr_wt_cnt_scalar),
+       .B1(txr_wt_cnt[8]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(txr_wt_cnt_cry[6]),
+       .COUT(txr_wt_cnt_cry[8]),
+       .S0(txr_wt_cnt_s[7]),
+       .S1(txr_wt_cnt_s[8])
+);
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[7] .INIT0=16'h8000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[7] .INIT1=16'h8000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[7] .INJECT1_0="NO";
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[7] .INJECT1_1="NO";
+// @16:527
+  CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[9]  (
+       .A0(txr_wt_cnt_scalar),
+       .B0(txr_wt_cnt[9]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(txr_wt_cnt_scalar),
+       .B1(txr_wt_cnt[10]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(txr_wt_cnt_cry[8]),
+       .COUT(txr_wt_cnt_cry[10]),
+       .S0(txr_wt_cnt_s[9]),
+       .S1(txr_wt_cnt_s[10])
+);
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[9] .INIT0=16'h8000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[9] .INIT1=16'h8000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[9] .INJECT1_0="NO";
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[9] .INJECT1_1="NO";
+// @16:527
+  CCU2C \genblk1.genblk2.txr_wt_cnt_s_0[11]  (
+       .A0(txr_wt_cnt_scalar),
+       .B0(txr_wt_cnt[11]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(txr_wt_cnt_cry[10]),
+       .COUT(txr_wt_cnt_s_0_COUT[11]),
+       .S0(txr_wt_cnt_s[11]),
+       .S1(txr_wt_cnt_s_0_S1[11])
+);
+defparam \genblk1.genblk2.txr_wt_cnt_s_0[11] .INIT0=16'h800a;
+defparam \genblk1.genblk2.txr_wt_cnt_s_0[11] .INIT1=16'h5003;
+defparam \genblk1.genblk2.txr_wt_cnt_s_0[11] .INJECT1_0="NO";
+defparam \genblk1.genblk2.txr_wt_cnt_s_0[11] .INJECT1_1="NO";
+  CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[0]  (
+       .A0(VCC),
+       .B0(rxr_wt_cnt9),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rxr_wt_cnt9),
+       .B1(rxr_wt_cnt[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_4),
+       .COUT(rxr_wt_cnt_cry[0]),
+       .S0(rxr_wt_cnt_cry_0_S0[0]),
+       .S1(rxr_wt_cnt_s[0])
+);
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[0] .INIT0=16'h5003;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[0] .INIT1=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[0] .INJECT1_0="NO";
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[0] .INJECT1_1="NO";
+// @16:909
+  CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[1]  (
+       .A0(rxr_wt_cnt9),
+       .B0(rxr_wt_cnt[1]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rxr_wt_cnt9),
+       .B1(rxr_wt_cnt[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rxr_wt_cnt_cry[0]),
+       .COUT(rxr_wt_cnt_cry[2]),
+       .S0(rxr_wt_cnt_s[1]),
+       .S1(rxr_wt_cnt_s[2])
+);
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[1] .INIT0=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[1] .INIT1=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[1] .INJECT1_0="NO";
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[1] .INJECT1_1="NO";
+// @16:909
+  CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[3]  (
+       .A0(rxr_wt_cnt9),
+       .B0(rxr_wt_cnt[3]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rxr_wt_cnt9),
+       .B1(rxr_wt_cnt[4]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rxr_wt_cnt_cry[2]),
+       .COUT(rxr_wt_cnt_cry[4]),
+       .S0(rxr_wt_cnt_s[3]),
+       .S1(rxr_wt_cnt_s[4])
+);
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[3] .INIT0=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[3] .INIT1=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[3] .INJECT1_0="NO";
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[3] .INJECT1_1="NO";
+// @16:909
+  CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[5]  (
+       .A0(rxr_wt_cnt9),
+       .B0(rxr_wt_cnt[5]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rxr_wt_cnt9),
+       .B1(rxr_wt_cnt[6]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rxr_wt_cnt_cry[4]),
+       .COUT(rxr_wt_cnt_cry[6]),
+       .S0(rxr_wt_cnt_s[5]),
+       .S1(rxr_wt_cnt_s[6])
+);
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[5] .INIT0=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[5] .INIT1=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[5] .INJECT1_0="NO";
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[5] .INJECT1_1="NO";
+// @16:909
+  CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[7]  (
+       .A0(rxr_wt_cnt9),
+       .B0(rxr_wt_cnt[7]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rxr_wt_cnt9),
+       .B1(rxr_wt_cnt[8]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rxr_wt_cnt_cry[6]),
+       .COUT(rxr_wt_cnt_cry[8]),
+       .S0(rxr_wt_cnt_s[7]),
+       .S1(rxr_wt_cnt_s[8])
+);
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[7] .INIT0=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[7] .INIT1=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[7] .INJECT1_0="NO";
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[7] .INJECT1_1="NO";
+// @16:909
+  CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[9]  (
+       .A0(rxr_wt_cnt9),
+       .B0(rxr_wt_cnt[9]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rxr_wt_cnt9),
+       .B1(rxr_wt_cnt[10]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rxr_wt_cnt_cry[8]),
+       .COUT(rxr_wt_cnt_cry[10]),
+       .S0(rxr_wt_cnt_s[9]),
+       .S1(rxr_wt_cnt_s[10])
+);
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[9] .INIT0=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[9] .INIT1=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[9] .INJECT1_0="NO";
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[9] .INJECT1_1="NO";
+// @16:909
+  CCU2C \genblk2.genblk3.rxr_wt_cnt_s_0[11]  (
+       .A0(rxr_wt_cnt9),
+       .B0(rxr_wt_cnt[11]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rxr_wt_cnt_cry[10]),
+       .COUT(rxr_wt_cnt_s_0_COUT[11]),
+       .S0(rxr_wt_cnt_s[11]),
+       .S1(rxr_wt_cnt_s_0_S1[11])
+);
+defparam \genblk2.genblk3.rxr_wt_cnt_s_0[11] .INIT0=16'h4005;
+defparam \genblk2.genblk3.rxr_wt_cnt_s_0[11] .INIT1=16'h5003;
+defparam \genblk2.genblk3.rxr_wt_cnt_s_0[11] .INJECT1_0="NO";
+defparam \genblk2.genblk3.rxr_wt_cnt_s_0[11] .INJECT1_1="NO";
+  CCU2C \genblk1.plol_cnt_cry_0[0]  (
+       .A0(VCC),
+       .B0(plol_cnt_scalar),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_3),
+       .COUT(plol_cnt_cry[0]),
+       .S0(plol_cnt_cry_0_S0[0]),
+       .S1(plol_cnt_s[0])
+);
+defparam \genblk1.plol_cnt_cry_0[0] .INIT0=16'h500c;
+defparam \genblk1.plol_cnt_cry_0[0] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[0] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[0] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[1]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[1]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[0]),
+       .COUT(plol_cnt_cry[2]),
+       .S0(plol_cnt_s[1]),
+       .S1(plol_cnt_s[2])
+);
+defparam \genblk1.plol_cnt_cry_0[1] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[1] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[1] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[1] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[3]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[3]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[4]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[2]),
+       .COUT(plol_cnt_cry[4]),
+       .S0(plol_cnt_s[3]),
+       .S1(plol_cnt_s[4])
+);
+defparam \genblk1.plol_cnt_cry_0[3] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[3] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[3] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[3] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[5]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[5]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[6]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[4]),
+       .COUT(plol_cnt_cry[6]),
+       .S0(plol_cnt_s[5]),
+       .S1(plol_cnt_s[6])
+);
+defparam \genblk1.plol_cnt_cry_0[5] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[5] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[5] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[5] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[7]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[7]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[8]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[6]),
+       .COUT(plol_cnt_cry[8]),
+       .S0(plol_cnt_s[7]),
+       .S1(plol_cnt_s[8])
+);
+defparam \genblk1.plol_cnt_cry_0[7] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[7] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[7] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[7] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[9]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[9]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[10]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[8]),
+       .COUT(plol_cnt_cry[10]),
+       .S0(plol_cnt_s[9]),
+       .S1(plol_cnt_s[10])
+);
+defparam \genblk1.plol_cnt_cry_0[9] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[9] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[9] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[9] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[11]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[11]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[12]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[10]),
+       .COUT(plol_cnt_cry[12]),
+       .S0(plol_cnt_s[11]),
+       .S1(plol_cnt_s[12])
+);
+defparam \genblk1.plol_cnt_cry_0[11] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[11] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[11] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[11] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[13]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[13]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[14]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[12]),
+       .COUT(plol_cnt_cry[14]),
+       .S0(plol_cnt_s[13]),
+       .S1(plol_cnt_s[14])
+);
+defparam \genblk1.plol_cnt_cry_0[13] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[13] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[13] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[13] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[15]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[15]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[16]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[14]),
+       .COUT(plol_cnt_cry[16]),
+       .S0(plol_cnt_s[15]),
+       .S1(plol_cnt_s[16])
+);
+defparam \genblk1.plol_cnt_cry_0[15] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[15] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[15] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[15] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[17]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[17]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[18]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[16]),
+       .COUT(plol_cnt_cry[18]),
+       .S0(plol_cnt_s[17]),
+       .S1(plol_cnt_s[18])
+);
+defparam \genblk1.plol_cnt_cry_0[17] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[17] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[17] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[17] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_s_0[19]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[19]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[18]),
+       .COUT(plol_cnt_s_0_COUT[19]),
+       .S0(plol_cnt_s[19]),
+       .S1(plol_cnt_s_0_S1[19])
+);
+defparam \genblk1.plol_cnt_s_0[19] .INIT0=16'h800a;
+defparam \genblk1.plol_cnt_s_0[19] .INIT1=16'h5003;
+defparam \genblk1.plol_cnt_s_0[19] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_s_0[19] .INJECT1_1="NO";
+  CCU2C \un1_genblk2.rlos_db_cnt_cry_0_0  (
+       .A0(VCC),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlos_db_cnt[0]),
+       .B1(un1_rlos_db_cnt_zero[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_2),
+       .COUT(rlos_db_cnt_cry_0),
+       .S0(rlos_db_cnt_cry_0_0_S0),
+       .S1(rlos_db_cnt_cry_0_0_S1)
+);
+defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INIT0=16'h5003;
+defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INIT1=16'h900a;
+defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INJECT1_0="NO";
+defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INJECT1_1="NO";
+// @16:641
+  CCU2C \un1_genblk2.rlos_db_cnt_cry_1_0  (
+       .A0(un1_rlos_db_cnt_zero[0]),
+       .B0(rlos_p2),
+       .C0(rlos_db_cnt[1]),
+       .D0(VCC),
+       .A1(un1_rlos_db_cnt_zero[0]),
+       .B1(rlos_p2),
+       .C1(rlos_db_cnt[2]),
+       .D1(VCC),
+       .CIN(rlos_db_cnt_cry_0),
+       .COUT(rlos_db_cnt_cry_2),
+       .S0(rlos_db_cnt_cry_1_0_S0),
+       .S1(rlos_db_cnt_cry_1_0_S1)
+);
+defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INIT0=16'he101;
+defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INIT1=16'he101;
+defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INJECT1_0="NO";
+defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INJECT1_1="NO";
+// @16:641
+  CCU2C \un1_genblk2.rlos_db_cnt_s_3_0  (
+       .A0(rlos_db_cnt[3]),
+       .B0(rlos_p2),
+       .C0(un1_rlos_db_cnt_zero[0]),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlos_db_cnt_cry_2),
+       .COUT(rlos_db_cnt_s_3_0_COUT),
+       .S0(rlos_db_cnt_s_3_0_S0),
+       .S1(rlos_db_cnt_s_3_0_S1)
+);
+defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INIT0=16'ha90a;
+defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INIT1=16'h5003;
+defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INJECT1_0="NO";
+defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INJECT1_1="NO";
+  CCU2C \un1_genblk2.rlol_db_cnt_cry_0_0  (
+       .A0(VCC),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol_db_cnt[0]),
+       .B1(un1_rlol_db_cnt_zero[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_1),
+       .COUT(rlol_db_cnt_cry_0),
+       .S0(rlol_db_cnt_cry_0_0_S0),
+       .S1(rlol_db_cnt_cry_0_0_S1)
+);
+defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INIT0=16'h5003;
+defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INIT1=16'h900a;
+defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INJECT1_0="NO";
+defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INJECT1_1="NO";
+// @16:625
+  CCU2C \un1_genblk2.rlol_db_cnt_cry_1_0  (
+       .A0(un1_rlol_db_cnt_zero[0]),
+       .B0(rlol_p2),
+       .C0(rlol_db_cnt[1]),
+       .D0(VCC),
+       .A1(un1_rlol_db_cnt_zero[0]),
+       .B1(rlol_p2),
+       .C1(rlol_db_cnt[2]),
+       .D1(VCC),
+       .CIN(rlol_db_cnt_cry_0),
+       .COUT(rlol_db_cnt_cry_2),
+       .S0(rlol_db_cnt_cry_1_0_S0),
+       .S1(rlol_db_cnt_cry_1_0_S1)
+);
+defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INIT0=16'he101;
+defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INIT1=16'he101;
+defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INJECT1_0="NO";
+defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INJECT1_1="NO";
+// @16:625
+  CCU2C \un1_genblk2.rlol_db_cnt_s_3_0  (
+       .A0(rlol_db_cnt[3]),
+       .B0(rlol_p2),
+       .C0(un1_rlol_db_cnt_zero[0]),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol_db_cnt_cry_2),
+       .COUT(rlol_db_cnt_s_3_0_COUT),
+       .S0(rlol_db_cnt_s_3_0_S0),
+       .S1(rlol_db_cnt_s_3_0_S1)
+);
+defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INIT0=16'ha90a;
+defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INIT1=16'h5003;
+defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INJECT1_0="NO";
+defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INJECT1_1="NO";
+//@16:865
+//@16:492
+  VHI VCC_0 (
+       .Z(VCC)
+);
+// @16:865
+  VLO GND_cZ (
+       .Z(GND)
+);
+endmodule /* sgmii_ecp5rsl_core_Z2_layer1 */
+
+module sgmii_ecp5 (
+  hdoutp,
+  hdoutn,
+  hdinp,
+  hdinn,
+  rxrefclk,
+  tx_pclk,
+  txi_clk,
+  txdata,
+  tx_k,
+  xmit,
+  tx_disp_correct,
+  rxdata,
+  rx_k,
+  rx_disp_err,
+  rx_cv_err,
+  signal_detect_c,
+  rx_los_low_s,
+  lsm_status_s,
+  ctc_urun_s,
+  ctc_orun_s,
+  rx_cdr_lol_s,
+  ctc_ins_s,
+  ctc_del_s,
+  sli_rst,
+  tx_pwrup_c,
+  rx_pwrup_c,
+  sci_wrdata,
+  sci_addr,
+  sci_rddata,
+  sci_en_dual,
+  sci_sel_dual,
+  sci_en,
+  sci_sel,
+  sci_rd,
+  sci_wrn,
+  sci_int,
+  cyawstn,
+  serdes_pdb,
+  pll_refclki,
+  rsl_disable,
+  rsl_rst,
+  serdes_rst_dual_c,
+  rst_dual_c,
+  tx_serdes_rst_c,
+  tx_pcs_rst_c,
+  pll_lol,
+  rsl_tx_rdy,
+  rx_serdes_rst_c,
+  rx_pcs_rst_c,
+  rsl_rx_rdy
+)
+;
+output hdoutp ;
+output hdoutn ;
+input hdinp ;
+input hdinn ;
+input rxrefclk ;
+output tx_pclk ;
+input txi_clk ;
+input [7:0] txdata ;
+input [0:0] tx_k ;
+input [0:0] xmit ;
+input [0:0] tx_disp_correct ;
+output [7:0] rxdata ;
+output [0:0] rx_k ;
+output [0:0] rx_disp_err ;
+output [0:0] rx_cv_err ;
+input signal_detect_c ;
+output rx_los_low_s ;
+output lsm_status_s ;
+output ctc_urun_s ;
+output ctc_orun_s ;
+output rx_cdr_lol_s ;
+output ctc_ins_s ;
+output ctc_del_s ;
+input sli_rst ;
+input tx_pwrup_c ;
+input rx_pwrup_c ;
+input [7:0] sci_wrdata ;
+input [5:0] sci_addr ;
+output [7:0] sci_rddata ;
+input sci_en_dual ;
+input sci_sel_dual ;
+input sci_en ;
+input sci_sel ;
+input sci_rd ;
+input sci_wrn ;
+output sci_int ;
+input cyawstn ;
+input serdes_pdb ;
+input pll_refclki ;
+input rsl_disable ;
+input rsl_rst ;
+input serdes_rst_dual_c ;
+input rst_dual_c ;
+input tx_serdes_rst_c ;
+input tx_pcs_rst_c ;
+output pll_lol ;
+output rsl_tx_rdy ;
+input rx_serdes_rst_c ;
+input rx_pcs_rst_c ;
+output rsl_rx_rdy ;
+wire hdoutp ;
+wire hdoutn ;
+wire hdinp ;
+wire hdinn ;
+wire rxrefclk ;
+wire tx_pclk ;
+wire txi_clk ;
+wire signal_detect_c ;
+wire rx_los_low_s ;
+wire lsm_status_s ;
+wire ctc_urun_s ;
+wire ctc_orun_s ;
+wire rx_cdr_lol_s ;
+wire ctc_ins_s ;
+wire ctc_del_s ;
+wire sli_rst ;
+wire tx_pwrup_c ;
+wire rx_pwrup_c ;
+wire sci_en_dual ;
+wire sci_sel_dual ;
+wire sci_en ;
+wire sci_sel ;
+wire sci_rd ;
+wire sci_wrn ;
+wire sci_int ;
+wire cyawstn ;
+wire serdes_pdb ;
+wire pll_refclki ;
+wire rsl_disable ;
+wire rsl_rst ;
+wire serdes_rst_dual_c ;
+wire rst_dual_c ;
+wire tx_serdes_rst_c ;
+wire tx_pcs_rst_c ;
+wire pll_lol ;
+wire rsl_tx_rdy ;
+wire rx_serdes_rst_c ;
+wire rx_pcs_rst_c ;
+wire rsl_rx_rdy ;
+wire rsl_tx_pcs_rst_c ;
+wire rsl_rx_pcs_rst_c ;
+wire rsl_rx_serdes_rst_c ;
+wire rsl_serdes_rst_dual_c ;
+wire rsl_tx_serdes_rst_c ;
+wire n47_1 ;
+wire n48_1 ;
+wire n1_1 ;
+wire n2_1 ;
+wire n3_1 ;
+wire n4_1 ;
+wire n5_1 ;
+wire n49_1 ;
+wire n6_1 ;
+wire n50_1 ;
+wire n7_1 ;
+wire n51_1 ;
+wire n8_1 ;
+wire n52_1 ;
+wire n9_1 ;
+wire n53_1 ;
+wire n54_1 ;
+wire n55_1 ;
+wire n56_1 ;
+wire n57_1 ;
+wire n58_1 ;
+wire n59_1 ;
+wire n60_1 ;
+wire n61_1 ;
+wire n62_1 ;
+wire n63_1 ;
+wire n64_1 ;
+wire n65_1 ;
+wire n10_1 ;
+wire n66_1 ;
+wire n67_1 ;
+wire n68_1 ;
+wire n69_1 ;
+wire n70_1 ;
+wire n71_1 ;
+wire n72_1 ;
+wire n73_1 ;
+wire n74_1 ;
+wire n75_1 ;
+wire n76_1 ;
+wire n77_1 ;
+wire n78_1 ;
+wire n79_1 ;
+wire n80_1 ;
+wire n81_1 ;
+wire n82_1 ;
+wire n83_1 ;
+wire n84_1 ;
+wire n85_1 ;
+wire n86_1 ;
+wire n87_1 ;
+wire n88_1 ;
+wire n11_1 ;
+wire n89_1 ;
+wire n12_1 ;
+wire n90_1 ;
+wire n13_1 ;
+wire n91_1 ;
+wire n92_1 ;
+wire n93_1 ;
+wire n94_1 ;
+wire n95_1 ;
+wire n14_1 ;
+wire n96_1 ;
+wire n15_1 ;
+wire n97_1 ;
+wire n98_1 ;
+wire n99_1 ;
+wire n100_1 ;
+wire n101_1 ;
+wire n112_1 ;
+wire n16_1 ;
+wire n17_1 ;
+wire n18_1 ;
+wire n19_1 ;
+wire n20_1 ;
+wire n21_1 ;
+wire n22_1 ;
+wire n23_1 ;
+wire n24_1 ;
+wire n25_1 ;
+wire n26_1 ;
+wire n27_1 ;
+wire n28_1 ;
+wire n29_1 ;
+wire n30_1 ;
+wire n31_1 ;
+wire n32_1 ;
+wire n33_1 ;
+wire n34_1 ;
+wire n35_1 ;
+wire n36_1 ;
+wire n37_1 ;
+wire n38_1 ;
+wire n39_1 ;
+wire n40_1 ;
+wire n41_1 ;
+wire n42_1 ;
+wire n43_1 ;
+wire n46_1 ;
+wire GND ;
+wire VCC ;
+  VHI VCC_0 (
+       .Z(VCC)
+);
+  VLO GND_0 (
+       .Z(GND)
+);
+// @16:865
+  PUR PUR_INST (
+       .PUR(VCC)
+);
+// @16:865
+  GSR GSR_INST (
+       .GSR(VCC)
+);
+// @8:162
+(* CHAN="CH0" *)  DCUA DCU0_inst (
+       .CH0_HDINP(hdinp),
+       .CH1_HDINP(GND),
+       .CH0_HDINN(hdinn),
+       .CH1_HDINN(GND),
+       .D_TXBIT_CLKP_FROM_ND(GND),
+       .D_TXBIT_CLKN_FROM_ND(GND),
+       .D_SYNC_ND(GND),
+       .D_TXPLL_LOL_FROM_ND(GND),
+       .CH0_RX_REFCLK(rxrefclk),
+       .CH1_RX_REFCLK(GND),
+       .CH0_FF_RXI_CLK(tx_pclk),
+       .CH1_FF_RXI_CLK(VCC),
+       .CH0_FF_TXI_CLK(txi_clk),
+       .CH1_FF_TXI_CLK(VCC),
+       .CH0_FF_EBRD_CLK(tx_pclk),
+       .CH1_FF_EBRD_CLK(VCC),
+       .CH0_FF_TX_D_0(txdata[0]),
+       .CH1_FF_TX_D_0(GND),
+       .CH0_FF_TX_D_1(txdata[1]),
+       .CH1_FF_TX_D_1(GND),
+       .CH0_FF_TX_D_2(txdata[2]),
+       .CH1_FF_TX_D_2(GND),
+       .CH0_FF_TX_D_3(txdata[3]),
+       .CH1_FF_TX_D_3(GND),
+       .CH0_FF_TX_D_4(txdata[4]),
+       .CH1_FF_TX_D_4(GND),
+       .CH0_FF_TX_D_5(txdata[5]),
+       .CH1_FF_TX_D_5(GND),
+       .CH0_FF_TX_D_6(txdata[6]),
+       .CH1_FF_TX_D_6(GND),
+       .CH0_FF_TX_D_7(txdata[7]),
+       .CH1_FF_TX_D_7(GND),
+       .CH0_FF_TX_D_8(tx_k[0]),
+       .CH1_FF_TX_D_8(GND),
+       .CH0_FF_TX_D_9(GND),
+       .CH1_FF_TX_D_9(GND),
+       .CH0_FF_TX_D_10(xmit[0]),
+       .CH1_FF_TX_D_10(GND),
+       .CH0_FF_TX_D_11(tx_disp_correct[0]),
+       .CH1_FF_TX_D_11(GND),
+       .CH0_FF_TX_D_12(GND),
+       .CH1_FF_TX_D_12(GND),
+       .CH0_FF_TX_D_13(GND),
+       .CH1_FF_TX_D_13(GND),
+       .CH0_FF_TX_D_14(GND),
+       .CH1_FF_TX_D_14(GND),
+       .CH0_FF_TX_D_15(GND),
+       .CH1_FF_TX_D_15(GND),
+       .CH0_FF_TX_D_16(GND),
+       .CH1_FF_TX_D_16(GND),
+       .CH0_FF_TX_D_17(GND),
+       .CH1_FF_TX_D_17(GND),
+       .CH0_FF_TX_D_18(GND),
+       .CH1_FF_TX_D_18(GND),
+       .CH0_FF_TX_D_19(GND),
+       .CH1_FF_TX_D_19(GND),
+       .CH0_FF_TX_D_20(GND),
+       .CH1_FF_TX_D_20(GND),
+       .CH0_FF_TX_D_21(GND),
+       .CH1_FF_TX_D_21(GND),
+       .CH0_FF_TX_D_22(GND),
+       .CH1_FF_TX_D_22(GND),
+       .CH0_FF_TX_D_23(GND),
+       .CH1_FF_TX_D_23(GND),
+       .CH0_FFC_EI_EN(GND),
+       .CH1_FFC_EI_EN(GND),
+       .CH0_FFC_PCIE_DET_EN(GND),
+       .CH1_FFC_PCIE_DET_EN(GND),
+       .CH0_FFC_PCIE_CT(GND),
+       .CH1_FFC_PCIE_CT(GND),
+       .CH0_FFC_SB_INV_RX(GND),
+       .CH1_FFC_SB_INV_RX(GND),
+       .CH0_FFC_ENABLE_CGALIGN(GND),
+       .CH1_FFC_ENABLE_CGALIGN(GND),
+       .CH0_FFC_SIGNAL_DETECT(signal_detect_c),
+       .CH1_FFC_SIGNAL_DETECT(GND),
+       .CH0_FFC_FB_LOOPBACK(GND),
+       .CH1_FFC_FB_LOOPBACK(GND),
+       .CH0_FFC_SB_PFIFO_LP(GND),
+       .CH1_FFC_SB_PFIFO_LP(GND),
+       .CH0_FFC_PFIFO_CLR(GND),
+       .CH1_FFC_PFIFO_CLR(GND),
+       .CH0_FFC_RATE_MODE_RX(GND),
+       .CH1_FFC_RATE_MODE_RX(GND),
+       .CH0_FFC_RATE_MODE_TX(GND),
+       .CH1_FFC_RATE_MODE_TX(GND),
+       .CH0_FFC_DIV11_MODE_RX(GND),
+       .CH1_FFC_DIV11_MODE_RX(GND),
+       .CH0_FFC_RX_GEAR_MODE(GND),
+       .CH1_FFC_RX_GEAR_MODE(GND),
+       .CH0_FFC_TX_GEAR_MODE(GND),
+       .CH1_FFC_TX_GEAR_MODE(GND),
+       .CH0_FFC_DIV11_MODE_TX(GND),
+       .CH1_FFC_DIV11_MODE_TX(GND),
+       .CH0_FFC_LDR_CORE2TX_EN(GND),
+       .CH1_FFC_LDR_CORE2TX_EN(GND),
+       .CH0_FFC_LANE_TX_RST(rsl_tx_pcs_rst_c),
+       .CH1_FFC_LANE_TX_RST(GND),
+       .CH0_FFC_LANE_RX_RST(rsl_rx_pcs_rst_c),
+       .CH1_FFC_LANE_RX_RST(GND),
+       .CH0_FFC_RRST(rsl_rx_serdes_rst_c),
+       .CH1_FFC_RRST(GND),
+       .CH0_FFC_TXPWDNB(tx_pwrup_c),
+       .CH1_FFC_TXPWDNB(GND),
+       .CH0_FFC_RXPWDNB(rx_pwrup_c),
+       .CH1_FFC_RXPWDNB(GND),
+       .CH0_LDR_CORE2TX(GND),
+       .CH1_LDR_CORE2TX(GND),
+       .D_SCIWDATA0(sci_wrdata[0]),
+       .D_SCIWDATA1(sci_wrdata[1]),
+       .D_SCIWDATA2(sci_wrdata[2]),
+       .D_SCIWDATA3(sci_wrdata[3]),
+       .D_SCIWDATA4(sci_wrdata[4]),
+       .D_SCIWDATA5(sci_wrdata[5]),
+       .D_SCIWDATA6(sci_wrdata[6]),
+       .D_SCIWDATA7(sci_wrdata[7]),
+       .D_SCIADDR0(sci_addr[0]),
+       .D_SCIADDR1(sci_addr[1]),
+       .D_SCIADDR2(sci_addr[2]),
+       .D_SCIADDR3(sci_addr[3]),
+       .D_SCIADDR4(sci_addr[4]),
+       .D_SCIADDR5(sci_addr[5]),
+       .D_SCIENAUX(sci_en_dual),
+       .D_SCISELAUX(sci_sel_dual),
+       .CH0_SCIEN(sci_en),
+       .CH1_SCIEN(GND),
+       .CH0_SCISEL(sci_sel),
+       .CH1_SCISEL(GND),
+       .D_SCIRD(sci_rd),
+       .D_SCIWSTN(sci_wrn),
+       .D_CYAWSTN(cyawstn),
+       .D_FFC_SYNC_TOGGLE(GND),
+       .D_FFC_DUAL_RST(rst_dual_c),
+       .D_FFC_MACRO_RST(rsl_serdes_rst_dual_c),
+       .D_FFC_MACROPDB(serdes_pdb),
+       .D_FFC_TRST(rsl_tx_serdes_rst_c),
+       .CH0_FFC_CDR_EN_BITSLIP(GND),
+       .CH1_FFC_CDR_EN_BITSLIP(GND),
+       .D_SCAN_ENABLE(GND),
+       .D_SCAN_IN_0(GND),
+       .D_SCAN_IN_1(GND),
+       .D_SCAN_IN_2(GND),
+       .D_SCAN_IN_3(GND),
+       .D_SCAN_IN_4(GND),
+       .D_SCAN_IN_5(GND),
+       .D_SCAN_IN_6(GND),
+       .D_SCAN_IN_7(GND),
+       .D_SCAN_MODE(GND),
+       .D_SCAN_RESET(GND),
+       .D_CIN0(GND),
+       .D_CIN1(GND),
+       .D_CIN2(GND),
+       .D_CIN3(GND),
+       .D_CIN4(GND),
+       .D_CIN5(GND),
+       .D_CIN6(GND),
+       .D_CIN7(GND),
+       .D_CIN8(GND),
+       .D_CIN9(GND),
+       .D_CIN10(GND),
+       .D_CIN11(GND),
+       .CH0_HDOUTP(hdoutp),
+       .CH1_HDOUTP(n47_1),
+       .CH0_HDOUTN(hdoutn),
+       .CH1_HDOUTN(n48_1),
+       .D_TXBIT_CLKP_TO_ND(n1_1),
+       .D_TXBIT_CLKN_TO_ND(n2_1),
+       .D_SYNC_PULSE2ND(n3_1),
+       .D_TXPLL_LOL_TO_ND(n4_1),
+       .CH0_FF_RX_F_CLK(n5_1),
+       .CH1_FF_RX_F_CLK(n49_1),
+       .CH0_FF_RX_H_CLK(n6_1),
+       .CH1_FF_RX_H_CLK(n50_1),
+       .CH0_FF_TX_F_CLK(n7_1),
+       .CH1_FF_TX_F_CLK(n51_1),
+       .CH0_FF_TX_H_CLK(n8_1),
+       .CH1_FF_TX_H_CLK(n52_1),
+       .CH0_FF_RX_PCLK(n9_1),
+       .CH1_FF_RX_PCLK(n53_1),
+       .CH0_FF_TX_PCLK(tx_pclk),
+       .CH1_FF_TX_PCLK(n54_1),
+       .CH0_FF_RX_D_0(rxdata[0]),
+       .CH1_FF_RX_D_0(n55_1),
+       .CH0_FF_RX_D_1(rxdata[1]),
+       .CH1_FF_RX_D_1(n56_1),
+       .CH0_FF_RX_D_2(rxdata[2]),
+       .CH1_FF_RX_D_2(n57_1),
+       .CH0_FF_RX_D_3(rxdata[3]),
+       .CH1_FF_RX_D_3(n58_1),
+       .CH0_FF_RX_D_4(rxdata[4]),
+       .CH1_FF_RX_D_4(n59_1),
+       .CH0_FF_RX_D_5(rxdata[5]),
+       .CH1_FF_RX_D_5(n60_1),
+       .CH0_FF_RX_D_6(rxdata[6]),
+       .CH1_FF_RX_D_6(n61_1),
+       .CH0_FF_RX_D_7(rxdata[7]),
+       .CH1_FF_RX_D_7(n62_1),
+       .CH0_FF_RX_D_8(rx_k[0]),
+       .CH1_FF_RX_D_8(n63_1),
+       .CH0_FF_RX_D_9(rx_disp_err[0]),
+       .CH1_FF_RX_D_9(n64_1),
+       .CH0_FF_RX_D_10(rx_cv_err[0]),
+       .CH1_FF_RX_D_10(n65_1),
+       .CH0_FF_RX_D_11(n10_1),
+       .CH1_FF_RX_D_11(n66_1),
+       .CH0_FF_RX_D_12(n67_1),
+       .CH1_FF_RX_D_12(n68_1),
+       .CH0_FF_RX_D_13(n69_1),
+       .CH1_FF_RX_D_13(n70_1),
+       .CH0_FF_RX_D_14(n71_1),
+       .CH1_FF_RX_D_14(n72_1),
+       .CH0_FF_RX_D_15(n73_1),
+       .CH1_FF_RX_D_15(n74_1),
+       .CH0_FF_RX_D_16(n75_1),
+       .CH1_FF_RX_D_16(n76_1),
+       .CH0_FF_RX_D_17(n77_1),
+       .CH1_FF_RX_D_17(n78_1),
+       .CH0_FF_RX_D_18(n79_1),
+       .CH1_FF_RX_D_18(n80_1),
+       .CH0_FF_RX_D_19(n81_1),
+       .CH1_FF_RX_D_19(n82_1),
+       .CH0_FF_RX_D_20(n83_1),
+       .CH1_FF_RX_D_20(n84_1),
+       .CH0_FF_RX_D_21(n85_1),
+       .CH1_FF_RX_D_21(n86_1),
+       .CH0_FF_RX_D_22(n87_1),
+       .CH1_FF_RX_D_22(n88_1),
+       .CH0_FF_RX_D_23(n11_1),
+       .CH1_FF_RX_D_23(n89_1),
+       .CH0_FFS_PCIE_DONE(n12_1),
+       .CH1_FFS_PCIE_DONE(n90_1),
+       .CH0_FFS_PCIE_CON(n13_1),
+       .CH1_FFS_PCIE_CON(n91_1),
+       .CH0_FFS_RLOS(rx_los_low_s),
+       .CH1_FFS_RLOS(n92_1),
+       .CH0_FFS_LS_SYNC_STATUS(lsm_status_s),
+       .CH1_FFS_LS_SYNC_STATUS(n93_1),
+       .CH0_FFS_CC_UNDERRUN(ctc_urun_s),
+       .CH1_FFS_CC_UNDERRUN(n94_1),
+       .CH0_FFS_CC_OVERRUN(ctc_orun_s),
+       .CH1_FFS_CC_OVERRUN(n95_1),
+       .CH0_FFS_RXFBFIFO_ERROR(n14_1),
+       .CH1_FFS_RXFBFIFO_ERROR(n96_1),
+       .CH0_FFS_TXFBFIFO_ERROR(n15_1),
+       .CH1_FFS_TXFBFIFO_ERROR(n97_1),
+       .CH0_FFS_RLOL(rx_cdr_lol_s),
+       .CH1_FFS_RLOL(n98_1),
+       .CH0_FFS_SKP_ADDED(ctc_ins_s),
+       .CH1_FFS_SKP_ADDED(n99_1),
+       .CH0_FFS_SKP_DELETED(ctc_del_s),
+       .CH1_FFS_SKP_DELETED(n100_1),
+       .CH0_LDR_RX2CORE(n101_1),
+       .CH1_LDR_RX2CORE(n112_1),
+       .D_SCIRDATA0(sci_rddata[0]),
+       .D_SCIRDATA1(sci_rddata[1]),
+       .D_SCIRDATA2(sci_rddata[2]),
+       .D_SCIRDATA3(sci_rddata[3]),
+       .D_SCIRDATA4(sci_rddata[4]),
+       .D_SCIRDATA5(sci_rddata[5]),
+       .D_SCIRDATA6(sci_rddata[6]),
+       .D_SCIRDATA7(sci_rddata[7]),
+       .D_SCIINT(sci_int),
+       .D_SCAN_OUT_0(n16_1),
+       .D_SCAN_OUT_1(n17_1),
+       .D_SCAN_OUT_2(n18_1),
+       .D_SCAN_OUT_3(n19_1),
+       .D_SCAN_OUT_4(n20_1),
+       .D_SCAN_OUT_5(n21_1),
+       .D_SCAN_OUT_6(n22_1),
+       .D_SCAN_OUT_7(n23_1),
+       .D_COUT0(n24_1),
+       .D_COUT1(n25_1),
+       .D_COUT2(n26_1),
+       .D_COUT3(n27_1),
+       .D_COUT4(n28_1),
+       .D_COUT5(n29_1),
+       .D_COUT6(n30_1),
+       .D_COUT7(n31_1),
+       .D_COUT8(n32_1),
+       .D_COUT9(n33_1),
+       .D_COUT10(n34_1),
+       .D_COUT11(n35_1),
+       .D_COUT12(n36_1),
+       .D_COUT13(n37_1),
+       .D_COUT14(n38_1),
+       .D_COUT15(n39_1),
+       .D_COUT16(n40_1),
+       .D_COUT17(n41_1),
+       .D_COUT18(n42_1),
+       .D_COUT19(n43_1),
+       .D_REFCLKI(pll_refclki),
+       .D_FFS_PLOL(n46_1)
+);
+defparam DCU0_inst.D_MACROPDB = "0b1";
+defparam DCU0_inst.D_IB_PWDNB = "0b1";
+defparam DCU0_inst.D_XGE_MODE = "0b0";
+defparam DCU0_inst.D_LOW_MARK = "0d4";
+defparam DCU0_inst.D_HIGH_MARK = "0d12";
+defparam DCU0_inst.D_BUS8BIT_SEL = "0b0";
+defparam DCU0_inst.D_CDR_LOL_SET = "0b00";
+defparam DCU0_inst.D_BITCLK_LOCAL_EN = "0b1";
+defparam DCU0_inst.D_BITCLK_ND_EN = "0b0";
+defparam DCU0_inst.D_BITCLK_FROM_ND_EN = "0b0";
+defparam DCU0_inst.D_SYNC_LOCAL_EN = "0b1";
+defparam DCU0_inst.D_SYNC_ND_EN = "0b0";
+defparam DCU0_inst.CH0_UC_MODE = "0b0";
+defparam DCU0_inst.CH0_PCIE_MODE = "0b0";
+defparam DCU0_inst.CH0_RIO_MODE = "0b0";
+defparam DCU0_inst.CH0_WA_MODE = "0b0";
+defparam DCU0_inst.CH0_INVERT_RX = "0b0";
+defparam DCU0_inst.CH0_INVERT_TX = "0b0";
+defparam DCU0_inst.CH0_PRBS_SELECTION = "0b0";
+defparam DCU0_inst.CH0_GE_AN_ENABLE = "0b0";
+defparam DCU0_inst.CH0_PRBS_LOCK = "0b0";
+defparam DCU0_inst.CH0_PRBS_ENABLE = "0b0";
+defparam DCU0_inst.CH0_ENABLE_CG_ALIGN = "0b1";
+defparam DCU0_inst.CH0_TX_GEAR_MODE = "0b0";
+defparam DCU0_inst.CH0_RX_GEAR_MODE = "0b0";
+defparam DCU0_inst.CH0_PCS_DET_TIME_SEL = "0b00";
+defparam DCU0_inst.CH0_PCIE_EI_EN = "0b0";
+defparam DCU0_inst.CH0_TX_GEAR_BYPASS = "0b0";
+defparam DCU0_inst.CH0_ENC_BYPASS = "0b0";
+defparam DCU0_inst.CH0_SB_BYPASS = "0b0";
+defparam DCU0_inst.CH0_RX_SB_BYPASS = "0b0";
+defparam DCU0_inst.CH0_WA_BYPASS = "0b0";
+defparam DCU0_inst.CH0_DEC_BYPASS = "0b0";
+defparam DCU0_inst.CH0_CTC_BYPASS = "0b0";
+defparam DCU0_inst.CH0_RX_GEAR_BYPASS = "0b0";
+defparam DCU0_inst.CH0_LSM_DISABLE = "0b0";
+defparam DCU0_inst.CH0_MATCH_2_ENABLE = "0b1";
+defparam DCU0_inst.CH0_MATCH_4_ENABLE = "0b0";
+defparam DCU0_inst.CH0_MIN_IPG_CNT = "0b11";
+defparam DCU0_inst.CH0_CC_MATCH_1 = "0x000";
+defparam DCU0_inst.CH0_CC_MATCH_2 = "0x000";
+defparam DCU0_inst.CH0_CC_MATCH_3 = "0x1BC";
+defparam DCU0_inst.CH0_CC_MATCH_4 = "0x050";
+defparam DCU0_inst.CH0_UDF_COMMA_MASK = "0x3ff";
+defparam DCU0_inst.CH0_UDF_COMMA_A = "0x283";
+defparam DCU0_inst.CH0_UDF_COMMA_B = "0x17C";
+defparam DCU0_inst.CH0_RX_DCO_CK_DIV = "0b010";
+defparam DCU0_inst.CH0_RCV_DCC_EN = "0b0";
+defparam DCU0_inst.CH0_REQ_LVL_SET = "0b00";
+defparam DCU0_inst.CH0_REQ_EN = "0b1";
+defparam DCU0_inst.CH0_RTERM_RX = "0d22";
+defparam DCU0_inst.CH0_PDEN_SEL = "0b1";
+defparam DCU0_inst.CH0_LDR_RX2CORE_SEL = "0b0";
+defparam DCU0_inst.CH0_LDR_CORE2TX_SEL = "0b0";
+defparam DCU0_inst.CH0_TPWDNB = "0b1";
+defparam DCU0_inst.CH0_RATE_MODE_TX = "0b0";
+defparam DCU0_inst.CH0_RTERM_TX = "0d19";
+defparam DCU0_inst.CH0_TX_CM_SEL = "0b00";
+defparam DCU0_inst.CH0_TDRV_PRE_EN = "0b0";
+defparam DCU0_inst.CH0_TDRV_SLICE0_SEL = "0b01";
+defparam DCU0_inst.CH0_TDRV_SLICE1_SEL = "0b00";
+defparam DCU0_inst.CH0_TDRV_SLICE2_SEL = "0b01";
+defparam DCU0_inst.CH0_TDRV_SLICE3_SEL = "0b01";
+defparam DCU0_inst.CH0_TDRV_SLICE4_SEL = "0b01";
+defparam DCU0_inst.CH0_TDRV_SLICE5_SEL = "0b01";
+defparam DCU0_inst.CH0_TDRV_SLICE0_CUR = "0b101";
+defparam DCU0_inst.CH0_TDRV_SLICE1_CUR = "0b000";
+defparam DCU0_inst.CH0_TDRV_SLICE2_CUR = "0b11";
+defparam DCU0_inst.CH0_TDRV_SLICE3_CUR = "0b11";
+defparam DCU0_inst.CH0_TDRV_SLICE4_CUR = "0b11";
+defparam DCU0_inst.CH0_TDRV_SLICE5_CUR = "0b00";
+defparam DCU0_inst.CH0_TDRV_DAT_SEL = "0b00";
+defparam DCU0_inst.CH0_TX_DIV11_SEL = "0b0";
+defparam DCU0_inst.CH0_RPWDNB = "0b1";
+defparam DCU0_inst.CH0_RATE_MODE_RX = "0b0";
+defparam DCU0_inst.CH0_RLOS_SEL = "0b1";
+defparam DCU0_inst.CH0_RX_LOS_LVL = "0b010";
+defparam DCU0_inst.CH0_RX_LOS_CEQ = "0b11";
+defparam DCU0_inst.CH0_RX_LOS_HYST_EN = "0b0";
+defparam DCU0_inst.CH0_RX_LOS_EN = "0b1";
+defparam DCU0_inst.CH0_RX_DIV11_SEL = "0b0";
+defparam DCU0_inst.CH0_SEL_SD_RX_CLK = "0b0";
+defparam DCU0_inst.CH0_FF_RX_H_CLK_EN = "0b0";
+defparam DCU0_inst.CH0_FF_RX_F_CLK_DIS = "0b0";
+defparam DCU0_inst.CH0_FF_TX_H_CLK_EN = "0b0";
+defparam DCU0_inst.CH0_FF_TX_F_CLK_DIS = "0b0";
+defparam DCU0_inst.CH0_RX_RATE_SEL = "0d8";
+defparam DCU0_inst.CH0_TDRV_POST_EN = "0b0";
+defparam DCU0_inst.CH0_TX_POST_SIGN = "0b0";
+defparam DCU0_inst.CH0_TX_PRE_SIGN = "0b0";
+defparam DCU0_inst.CH0_RXTERM_CM = "0b11";
+defparam DCU0_inst.CH0_RXIN_CM = "0b11";
+defparam DCU0_inst.CH0_LEQ_OFFSET_SEL = "0b0";
+defparam DCU0_inst.CH0_LEQ_OFFSET_TRIM = "0b000";
+defparam DCU0_inst.D_TX_MAX_RATE = "1.25";
+defparam DCU0_inst.CH0_CDR_MAX_RATE = "1.25";
+defparam DCU0_inst.CH0_TXAMPLITUDE = "0d1100";
+defparam DCU0_inst.CH0_TXDEPRE = "DISABLED";
+defparam DCU0_inst.CH0_TXDEPOST = "DISABLED";
+defparam DCU0_inst.CH0_PROTOCOL = "GBE";
+defparam DCU0_inst.D_ISETLOS = "0d0";
+defparam DCU0_inst.D_SETIRPOLY_AUX = "0b00";
+defparam DCU0_inst.D_SETICONST_AUX = "0b00";
+defparam DCU0_inst.D_SETIRPOLY_CH = "0b00";
+defparam DCU0_inst.D_SETICONST_CH = "0b00";
+defparam DCU0_inst.D_REQ_ISET = "0b000";
+defparam DCU0_inst.D_PD_ISET = "0b00";
+defparam DCU0_inst.D_DCO_CALIB_TIME_SEL = "0b00";
+defparam DCU0_inst.CH0_DCOCTLGI = "0b010";
+defparam DCU0_inst.CH0_DCOATDDLY = "0b00";
+defparam DCU0_inst.CH0_DCOATDCFG = "0b00";
+defparam DCU0_inst.CH0_DCOBYPSATD = "0b1";
+defparam DCU0_inst.CH0_DCOSCALEI = "0b00";
+defparam DCU0_inst.CH0_DCOITUNE4LSB = "0b111";
+defparam DCU0_inst.CH0_DCOIOSTUNE = "0b000";
+defparam DCU0_inst.CH0_DCODISBDAVOID = "0b0";
+defparam DCU0_inst.CH0_DCOCALDIV = "0b001";
+defparam DCU0_inst.CH0_DCONUOFLSB = "0b101";
+defparam DCU0_inst.CH0_DCOIUPDNX2 = "0b1";
+defparam DCU0_inst.CH0_DCOSTEP = "0b00";
+defparam DCU0_inst.CH0_DCOSTARTVAL = "0b000";
+defparam DCU0_inst.CH0_DCOFLTDAC = "0b01";
+defparam DCU0_inst.CH0_DCOITUNE = "0b00";
+defparam DCU0_inst.CH0_DCOFTNRG = "0b110";
+defparam DCU0_inst.CH0_CDR_CNT4SEL = "0b00";
+defparam DCU0_inst.CH0_CDR_CNT8SEL = "0b00";
+defparam DCU0_inst.CH0_BAND_THRESHOLD = "0d0";
+defparam DCU0_inst.CH0_AUTO_FACQ_EN = "0b1";
+defparam DCU0_inst.CH0_AUTO_CALIB_EN = "0b1";
+defparam DCU0_inst.CH0_CALIB_CK_MODE = "0b0";
+defparam DCU0_inst.CH0_REG_BAND_OFFSET = "0d0";
+defparam DCU0_inst.CH0_REG_BAND_SEL = "0d0";
+defparam DCU0_inst.CH0_REG_IDAC_SEL = "0d0";
+defparam DCU0_inst.CH0_REG_IDAC_EN = "0b0";
+defparam DCU0_inst.D_TXPLL_PWDNB = "0b1";
+defparam DCU0_inst.D_SETPLLRC = "0d1";
+defparam DCU0_inst.D_REFCK_MODE = "0b001";
+defparam DCU0_inst.D_TX_VCO_CK_DIV = "0b010";
+defparam DCU0_inst.D_PLL_LOL_SET = "0b00";
+defparam DCU0_inst.D_RG_EN = "0b0";
+defparam DCU0_inst.D_RG_SET = "0b00";
+defparam DCU0_inst.D_CMUSETISCL4VCO = "0b000";
+defparam DCU0_inst.D_CMUSETI4VCO = "0b00";
+defparam DCU0_inst.D_CMUSETINITVCT = "0b00";
+defparam DCU0_inst.D_CMUSETZGM = "0b000";
+defparam DCU0_inst.D_CMUSETP2AGM = "0b000";
+defparam DCU0_inst.D_CMUSETP1GM = "0b000";
+defparam DCU0_inst.D_CMUSETI4CPZ = "0d3";
+defparam DCU0_inst.D_CMUSETI4CPP = "0d3";
+defparam DCU0_inst.D_CMUSETICP4Z = "0b101";
+defparam DCU0_inst.D_CMUSETICP4P = "0b01";
+defparam DCU0_inst.D_CMUSETBIASI = "0b00";
+// @8:424
+  sgmii_ecp5sll_core_Z1_layer1 sll_inst (
+       .tx_pclk(tx_pclk),
+       .sli_rst(sli_rst),
+       .pll_refclki(pll_refclki),
+       .pll_lock_i(pll_lol)
+);
+// @8:394
+  sgmii_ecp5rsl_core_Z2_layer1 rsl_inst (
+       .rx_pcs_rst_c(rx_pcs_rst_c),
+       .tx_pcs_rst_c(tx_pcs_rst_c),
+       .tx_serdes_rst_c(tx_serdes_rst_c),
+       .serdes_rst_dual_c(serdes_rst_dual_c),
+       .rsl_tx_pcs_rst_c(rsl_tx_pcs_rst_c),
+       .rsl_rx_serdes_rst_c(rsl_rx_serdes_rst_c),
+       .rsl_serdes_rst_dual_c(rsl_serdes_rst_dual_c),
+       .rsl_tx_serdes_rst_c(rsl_tx_serdes_rst_c),
+       .rsl_tx_rdy(rsl_tx_rdy),
+       .pll_lock_i(pll_lol),
+       .pll_refclki(pll_refclki),
+       .rsl_rx_rdy(rsl_rx_rdy),
+       .rsl_rst(rsl_rst),
+       .rxrefclk(rxrefclk),
+       .rsl_disable(rsl_disable),
+       .rx_serdes_rst_c(rx_serdes_rst_c),
+       .rsl_rx_pcs_rst_c(rsl_rx_pcs_rst_c),
+       .rst_dual_c(rst_dual_c),
+       .rx_cdr_lol_s(rx_cdr_lol_s),
+       .rx_los_low_s(rx_los_low_s)
+);
+endmodule /* sgmii_ecp5 */
+

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_cck.rpt.db b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_cck.rpt.db
new file mode 100644 (file)
index 0000000..029fa7a
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_cck.rpt.db differ

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt.db b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt.db
new file mode 100644 (file)
index 0000000..029fa7a
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt.db differ

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_synplify.lpf b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_synplify.lpf
new file mode 100644 (file)
index 0000000..9cbac38
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_synplify.lpf
@@ -0,0 +1,29 @@
+#
+# Logical Preferences generated for Lattice by Synplify maplat, Build 1796R.
+#
+
+# Period Constraints 
+#FREQUENCY PORT "pll_refclki" 100.0 MHz;
+#FREQUENCY PORT "rxrefclk" 100.0 MHz;
+#FREQUENCY NET "tx_pclk" 100.0 MHz;
+
+
+# Output Constraints 
+
+# Input Constraints 
+
+# Point-to-point Delay Constraints 
+
+
+
+# Block Path Constraints 
+#BLOCK PATH FROM CLKNET "tx_pclk" TO CLKNET "rxrefclk";
+#BLOCK PATH FROM CLKNET "tx_pclk" TO CLKNET "pll_refclki";
+#BLOCK PATH FROM CLKNET "rxrefclk" TO CLKNET "tx_pclk";
+#BLOCK PATH FROM CLKNET "rxrefclk" TO CLKNET "pll_refclki";
+#BLOCK PATH FROM CLKNET "pll_refclki" TO CLKNET "tx_pclk";
+#BLOCK PATH FROM CLKNET "pll_refclki" TO CLKNET "rxrefclk";
+
+BLOCK ASYNCPATHS;
+
+# End of generated Logical Preferences.

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_synplify_tmp2.lpf b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_synplify_tmp2.lpf
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_synplify_tmp4.lpf b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_synplify_tmp4.lpf
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_synplify_tmp8.lpf b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_synplify_tmp8.lpf
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/layer0.tlg.rptmap b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/layer0.tlg.rptmap
new file mode 100644 (file)
index 0000000..3910cac
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/layer0.tlg.rptmap
@@ -0,0 +1 @@
+./synwork/layer0.tlg,layer0.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages.

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/layer1.tlg.rptmap b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/layer1.tlg.rptmap
new file mode 100644 (file)
index 0000000..af92e0b
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/layer1.tlg.rptmap
@@ -0,0 +1 @@
+./synwork/layer1.tlg,layer1.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages.

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/linker.rpt.rptmap b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/linker.rpt.rptmap
new file mode 100644 (file)
index 0000000..3793ead
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/linker.rpt.rptmap
@@ -0,0 +1 @@
+./synwork/sgmii_ecp5_comp.linkerlog,linker.rpt,Summary of linker messages for components that did not bind

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/metrics.db b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/metrics.db
new file mode 100644 (file)
index 0000000..8452dbd
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/metrics.db differ

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_notes.txt b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_notes.txt
new file mode 100644 (file)
index 0000000..f5277c3
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_notes.txt
@@ -0,0 +1,16 @@
+@N|Running in 64-bit mode
+@N|Running in 64-bit mode
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
+@N|Running in 64-bit mode
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1.
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work.
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work.
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment.
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment.
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work.
+@N: CL201 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state.
+@N|Running in 64-bit mode
+

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_runstatus.xml b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_runstatus.xml
new file mode 100644 (file)
index 0000000..978b9de
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_runstatus.xml
@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the job information from compiler to be displayed as part of the summary report.
+*******************************************************************************************-->
+
+<job_run_status name="compiler"> 
+  <report_link name="Detailed report">
+    <data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr</data>
+    <title>Synopsys HDL Compiler</title>
+  </report_link> 
+  <job_status>
+    <data>Completed    </data>
+  </job_status>
+<job_info> 
+                       <info name="Notes">
+  <data>15</data>
+  <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_notes.txt</data></report_link>
+  </info>
+                       <info name="Warnings">
+  <data>76</data>
+  <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt</data></report_link>
+  </info>
+                       <info name="Errors">
+  <data>0</data>
+  <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_errors.txt</data></report_link>
+  </info>
+                       <info name="CPU Time">
+  <data>-</data>
+  </info>
+                       <info name="Real Time">
+  <data>00h:00m:02s</data>
+  </info>
+                       <info name="Peak Memory">
+  <data>-</data>
+  </info>
+                       <info name="Date &amp;Time">
+  <data type="timestamp">1557731345</data>
+  </info>
+                       </job_info>
+</job_run_status>
\ No newline at end of file

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt
new file mode 100644 (file)
index 0000000..8e5c4f5
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt
@@ -0,0 +1,77 @@
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers.
+

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_area_report.xml b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_area_report.xml
new file mode 100644 (file)
index 0000000..c262d0f
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_area_report.xml
@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the area information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<report_table display_priority="1" name="Area Summary">
+<report_link name="Detailed report">
+<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_resourceusage.rpt</data>
+<title>Resource Usage</title>
+</report_link>
+<parameter tooltip="Total Register bits used" name="Register bits">
+<data>221</data>
+</parameter>
+<parameter tooltip="Total I/O cells used" name="I/O cells">
+<data>0</data>
+</parameter>
+<parameter tcl_name="v_ram" tooltip="Total Block RAMs used" name="Block RAMs">
+<data>0</data>
+</parameter>
+<parameter tcl_name="dsp_used" tooltip="Total DSPs used" name="DSPs">
+<data>0</data>
+</parameter>
+<parameter tcl_name="total_luts" tooltip="Total ORCA LUTs used" name="ORCA LUTs">
+<data>154</data>
+</parameter>
+</report_table>

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_errors.txt b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_errors.txt
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt
new file mode 100644 (file)
index 0000000..b2d9ac0
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt
@@ -0,0 +1,22 @@
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+@N: MO225 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":909:3:909:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":527:3:527:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] 
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.edn
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_opt_report.xml b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_opt_report.xml
new file mode 100644 (file)
index 0000000..68d4e92
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_opt_report.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the optimization information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<report_table display_priority="3" name="Optimizations Summary">
+<parameter tooltip="Non-gated/non-generated clock trees / Gated/generated clock trees" name="Combined Clock Conversion">
+<data>3 / 0</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_combined_clk.rpt</data>
+<title>START OF CLOCK OPTIMIZATION REPORT</title>
+</report_link>
+</parameter>
+</report_table>

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_runstatus.xml b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_runstatus.xml
new file mode 100644 (file)
index 0000000..686a424
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_runstatus.xml
@@ -0,0 +1,46 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the job information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<job_run_status name="Mapper">
+<report_link name="Detailed report">
+<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr</data>
+<title>Synopsys Lattice Technology Mapper</title>
+</report_link>
+<job_status>
+<data>Completed</data>
+</job_status>
+<job_info>
+<info name="Notes">
+<data>22</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt</data>
+</report_link>
+</info>
+<info name="Warnings">
+<data>4</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt</data>
+</report_link>
+</info>
+<info name="Errors">
+<data>0</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_errors.txt</data>
+</report_link>
+</info>
+<info name="CPU Time">
+<data>0h:00m:03s</data>
+</info>
+<info name="Real Time">
+<data>0h:00m:03s</data>
+</info>
+<info name="Peak Memory">
+<data>153MB</data>
+</info>
+<info name="Date &amp; Time">
+<data type="timestamp">1557731351</data>
+</info>
+</job_info>
+</job_run_status>

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_timing_report.xml b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_timing_report.xml
new file mode 100644 (file)
index 0000000..92b3753
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_timing_report.xml
@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+Max Top 5 critical clocks will be reported. For rest user needs to refer to Detailed report
+*******************************************************************************************-->
+<report_table display_priority="2" name="Timing Summary">
+<report_link name="Detailed report">
+<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr</data>
+<title>START OF TIMING REPORT</title>
+</report_link>
+<row>
+<data tcl_name="clock_name">Clock Name</data>
+<data tcl_name="req_freq">Req Freq</data>
+<data tcl_name="est_freq">Est Freq</data>
+<data tcl_name="slack">Slack</data>
+</row>
+<row>
+<data>sgmii_ecp5|pll_refclki</data>
+<data>100.0 MHz</data>
+<data>168.9 MHz</data>
+<data>4.079</data>
+</row>
+<row>
+<data>sgmii_ecp5|rxrefclk</data>
+<data>100.0 MHz</data>
+<data>167.9 MHz</data>
+<data>4.043</data>
+</row>
+<row>
+<data>sgmii_ecp5|tx_pclk_inferred_clock</data>
+<data>100.0 MHz</data>
+<data>237.5 MHz</data>
+<data>5.789</data>
+</row>
+<row>
+<data>System</data>
+<data>100.0 MHz</data>
+<data>840.7 MHz</data>
+<data>8.810</data>
+</row>
+</report_table>

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt
new file mode 100644 (file)
index 0000000..a40a3f6
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt
@@ -0,0 +1,4 @@
+@W: MT246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":162:4:162:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"
+@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"
+@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk"

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_errors.txt b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_errors.txt
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt
new file mode 100644 (file)
index 0000000..958d4b4
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt
@@ -0,0 +1,9 @@
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+@N: BN362 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances.
+@N: MO225 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_runstatus.xml b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_runstatus.xml
new file mode 100644 (file)
index 0000000..552c1b6
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_runstatus.xml
@@ -0,0 +1,46 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the job information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<job_run_status name="Mapper">
+<report_link name="Detailed report">
+<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr</data>
+<title>Synopsys Lattice Technology Pre-mapping</title>
+</report_link>
+<job_status>
+<data>Completed</data>
+</job_status>
+<job_info>
+<info name="Notes">
+<data>9</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt</data>
+</report_link>
+</info>
+<info name="Warnings">
+<data>3</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt</data>
+</report_link>
+</info>
+<info name="Errors">
+<data>0</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_errors.txt</data>
+</report_link>
+</info>
+<info name="CPU Time">
+<data>0h:00m:00s</data>
+</info>
+<info name="Real Time">
+<data>0h:00m:00s</data>
+</info>
+<info name="Peak Memory">
+<data>144MB</data>
+</info>
+<info name="Date &amp; Time">
+<data type="timestamp">1557731347</data>
+</info>
+</job_info>
+</job_run_status>

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt
new file mode 100644 (file)
index 0000000..71c6352
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt
@@ -0,0 +1,3 @@
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr
new file mode 100644 (file)
index 0000000..7b9d5ac
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr
@@ -0,0 +1,351 @@
+Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
+VHDL syntax check successful!
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Mon May 13 09:09:04 2019
+
+###########################################################]
+Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
+Verilog syntax check successful!
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Mon May 13 09:09:04 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
+VHDL syntax check successful!
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1.
+Post processing for work.sgmii_ecp5.v1
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB)
+
+
+Process completed successfully.
+# Mon May 13 09:09:04 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
+Verilog syntax check successful!
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work.
+
+       PDATA_RST_VAL=32'b00000000000000000000000000000000
+   Generated name = sync_0s
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work.
+
+       PPROTOCOL=24'b010001110100001001000101
+       PLOL_SETTING=32'b00000000000000000000000000000000
+       PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100
+       PPCIE_MAX_RATE=24'b001100100010111000110101
+       PDIFF_VAL_LOCK=32'b00000000000000000000000000100111
+       PDIFF_VAL_UNLOCK=32'b00000000000000000000000001001110
+       PPCLK_TC=32'b00000000000000100000000000000000
+       PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000
+       PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000
+       PPCLK_DIV11_TC=32'b00000000000000000000000000000000
+       LPLL_LOSS_ST=2'b00
+       LPLL_PRELOSS_ST=2'b01
+       LPLL_PRELOCK_ST=2'b10
+       LPLL_LOCK_ST=2'b11
+       LRCLK_TC=16'b1111111111111111
+       LRCLK_TC_PUL_WIDTH=16'b0000000000110010
+       LHB_WAIT_CNT=8'b11111111
+       LPCLK_TC_0=32'b00000000000000001000000000000000
+       LPCLK_TC_1=32'b00000000000000010000000000000000
+       LPCLK_TC_2=32'b00000000000000100000000000000000
+       LPCLK_TC_3=32'b00000000000000101000000000000000
+       LPCLK_TC_4=32'b00000000000000010000000000000000
+       LPDIFF_LOCK_00=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_10=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_20=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_30=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_40=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_01=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_11=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_21=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_31=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_41=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_02=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_12=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_22=32'b00000000000000000000000011000100
+       LPDIFF_LOCK_32=32'b00000000000000000000000011110101
+       LPDIFF_LOCK_42=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_03=32'b00000000000000000000000010000011
+       LPDIFF_LOCK_13=32'b00000000000000000000000100000110
+       LPDIFF_LOCK_23=32'b00000000000000000000001000001100
+       LPDIFF_LOCK_33=32'b00000000000000000000001010001111
+       LPDIFF_LOCK_43=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011
+       LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110
+       LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010
+       LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001
+       LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111
+       LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000
+       LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000
+       LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000
+       LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100
+       LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001
+       LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010
+       LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111
+       LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001
+   Generated name = sgmii_ecp5sll_core_Z1_layer1
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment.
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work.
+
+       pnum_channels=32'b00000000000000000000000000000001
+       pprotocol=24'b010001110100001001000101
+       pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
+       pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_tx_rdy=32'b00000000000000000000101110111000
+       pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_rx_rdy=32'b00000000000000000000101110111000
+       wa_num_cycles=32'b00000000000000000000010000000000
+       dac_num_cycles=32'b00000000000000000000000000000011
+       lreset_pwidth=32'b00000000000000000000000000000011
+       lwait_b4_trst=32'b00000000000010111110101111000010
+       lwait_b4_trst_s=32'b00000000000000000000001100001101
+       lplol_cnt_width=32'b00000000000000000000000000010100
+       lwait_after_plol0=32'b00000000000000000000000000000100
+       lwait_b4_rrst=32'b00000000000000101100000000000000
+       lrrst_wait_width=32'b00000000000000000000000000010100
+       lwait_after_rrst=32'b00000000000011000011010100000000
+       lwait_b4_rrst_s=32'b00000000000000000000000111001100
+       lrlol_cnt_width=32'b00000000000000000000000000010011
+       lwait_after_lols=32'b00000000000000001100010000000000
+       lwait_after_lols_s=32'b00000000000000000000000010010110
+       llols_cnt_width=32'b00000000000000000000000000010010
+       lrdb_max=32'b00000000000000000000000000001111
+       ltxr_wait_width=32'b00000000000000000000000000001100
+       lrxr_wait_width=32'b00000000000000000000000000001100
+   Generated name = sgmii_ecp5rsl_core_Z2_layer1
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers.
+@N: CL201 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state.
+Extracted state machine for register sll_state
+State machine has 4 reachable states with original encodings of:
+   00
+   01
+   10
+   11
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB)
+
+
+Process completed successfully.
+# Mon May 13 09:09:05 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+
+=======================================================================================
+For a summary of linker messages for components that did not bind, please see log file:
+@L: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.linkerlog
+=======================================================================================
+
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon May 13 09:09:05 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon May 13 09:09:05 2019
+
+###########################################################]

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr.db b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr.db
new file mode 100644 (file)
index 0000000..22032b2
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr.db differ

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr.rptmap b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr.rptmap
new file mode 100644 (file)
index 0000000..14937c8
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr.rptmap
@@ -0,0 +1 @@
+./synlog/sgmii_ecp5_compiler.srr,sgmii_ecp5_compiler.srr,Compile Log

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr
new file mode 100644 (file)
index 0000000..c238d11
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr
@@ -0,0 +1,673 @@
+# Mon May 13 09:09:07 2019
+
+Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   10 -> 10
+   11 -> 11
+@N: MO225 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":909:3:909:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":527:3:527:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] 
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+   1           0h:00m:01s                   4.90ns              155 /       221
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 148MB peak: 149MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+3 non-gated/non-generated clock tree(s) driving 221 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+============================================= Non-Gated/Non-Generated Clocks =============================================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                                   
+--------------------------------------------------------------------------------------------------------------------------
+@K:CKID0001       pll_refclki         port                   91         rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]
+@K:CKID0002       rxrefclk            port                   77         rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]
+@K:CKID0003       DCU0_inst           DCUA                   53         sll_inst.pcount[21]                               
+==========================================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 112MB peak: 149MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 149MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.edn
+M-2017.03L-SP1-1
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 153MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+@W: MT246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":162:4:162:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"
+@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"
+@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk"
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Mon May 13 09:09:11 2019
+#
+
+
+Top view:               sgmii_ecp5
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.fdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 4.043
+
+                                      Requested     Estimated     Requested     Estimated               Clock        Clock              
+Starting Clock                        Frequency     Frequency     Period        Period        Slack     Type         Group              
+----------------------------------------------------------------------------------------------------------------------------------------
+sgmii_ecp5|pll_refclki                100.0 MHz     168.9 MHz     10.000        5.921         4.079     inferred     Inferred_clkgroup_0
+sgmii_ecp5|rxrefclk                   100.0 MHz     167.9 MHz     10.000        5.957         4.043     inferred     Inferred_clkgroup_1
+sgmii_ecp5|tx_pclk_inferred_clock     100.0 MHz     237.5 MHz     10.000        4.211         5.789     inferred     Inferred_clkgroup_2
+System                                100.0 MHz     840.7 MHz     10.000        1.190         8.810     system       system_clkgroup    
+========================================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                                                                |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+Starting                           Ending                             |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+System                             sgmii_ecp5|rxrefclk                |  10.000      8.811  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             System                             |  10.000      8.253  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             sgmii_ecp5|pll_refclki             |  10.000      4.079  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             sgmii_ecp5|tx_pclk_inferred_clock  |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|rxrefclk                System                             |  10.000      8.277  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|rxrefclk                sgmii_ecp5|rxrefclk                |  10.000      4.043  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|tx_pclk_inferred_clock  sgmii_ecp5|pll_refclki             |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|tx_pclk_inferred_clock  sgmii_ecp5|tx_pclk_inferred_clock  |  10.000      5.789  |  No paths    -      |  No paths    -      |  No paths    -    
+============================================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|pll_refclki
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                   Starting                                                        Arrival          
+Instance                           Reference                  Type        Pin     Net              Time        Slack
+                                   Clock                                                                            
+--------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[2]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[2]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[3]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[3]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[17]     sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[17]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[19]     sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[19]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[1]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[1]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[4]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[4]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[5]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[5]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[6]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[6]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[7]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[7]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[8]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[8]      0.907       4.684
+====================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                   Starting                                                          Required          
+Instance                           Reference                  Type        Pin     Net                Time         Slack
+                                   Clock                                                                               
+-----------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[19]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[19]     9.946        4.079
+rsl_inst.genblk1\.plol_cnt[17]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[17]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[18]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[18]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[15]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[15]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[16]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[16]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[13]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[13]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[14]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[14]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[11]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[11]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[12]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[12]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[9]      sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[9]      9.946        4.383
+=======================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.867
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.079
+
+    Number of logic level(s):                15
+    Starting point:                          rsl_inst.genblk1\.plol_cnt[2] / Q
+    Ending point:                            rsl_inst.genblk1\.plol_cnt[19] / D
+    The start point is clocked by            sgmii_ecp5|pll_refclki [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|pll_refclki [rising] on pin CK
+
+Instance / Net                                        Pin      Pin               Arrival     No. of    
+Name                                     Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[2]            FD1S3DX      Q        Out     0.907     0.907       -         
+plol_cnt[2]                              Net          -        -       -         -           2         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     Z        Out     0.606     1.513       -         
+un1_plol_cnt_tc_10                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     Z        Out     0.606     2.119       -         
+un1_plol_cnt_tc_14                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     Z        Out     0.762     2.881       -         
+un1_plol_cnt_tc                          Net          -        -       -         -           5         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     B        In      0.000     2.881       -         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     Z        Out     0.840     3.721       -         
+plol_cnt                                 Net          -        -       -         -           21        
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.721       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.621       -         
+plol_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.621       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.682       -         
+plol_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.682       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.743       -         
+plol_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.743       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.804       -         
+plol_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.804       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.865       -         
+plol_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.865       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.926       -         
+plol_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.926       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.987       -         
+plol_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.987       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.048       -         
+plol_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.048       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.109       -         
+plol_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.109       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        COUT     Out     0.061     5.170       -         
+plol_cnt_cry[18]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        CIN      In      0.000     5.170       -         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        S0       Out     0.698     5.867       -         
+plol_cnt_s[19]                           Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt[19]           FD1S3DX      D        In      0.000     5.867       -         
+=======================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|rxrefclk
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                    Starting                                                      Arrival          
+Instance                            Reference               Type        Pin     Net               Time        Slack
+                                    Clock                                                                          
+-------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rxs_rst           sgmii_ecp5|rxrefclk     FD1P3DX     Q       rxs_rst           1.015       4.043
+rsl_inst.genblk2\.rlol1_cnt[7]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[7]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[8]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[8]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[9]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[9]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[10]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[10]     0.907       4.136
+rsl_inst.genblk2\.rlols0_cnt[1]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[1]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[2]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[2]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[3]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[3]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[4]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[4]     0.907       4.170
+rsl_inst.genblk2\.rlol1_cnt[0]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[0]      0.907       4.742
+===================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                              Starting                                                         Required          
+Instance                                      Reference               Type        Pin     Net                  Time         Slack
+                                              Clock                                                                              
+---------------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[11]     9.946        4.043
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[9]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[9]      9.946        4.104
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[10]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[10]     9.946        4.104
+rsl_inst.genblk2\.rlol1_cnt[17]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[17]      9.946        4.136
+rsl_inst.genblk2\.rlol1_cnt[18]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[18]      9.946        4.136
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[7]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[7]      9.946        4.165
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[8]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[8]      9.946        4.165
+rsl_inst.genblk2\.rlols0_cnt[17]              sgmii_ecp5|rxrefclk     FD1P3DX     D       rlols0_cnt_s[17]     9.946        4.170
+rsl_inst.genblk2\.rlol1_cnt[15]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[15]      9.946        4.197
+rsl_inst.genblk2\.rlol1_cnt[16]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[16]      9.946        4.197
+=================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.902
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     4.043
+
+    Number of logic level(s):                11
+    Starting point:                          rsl_inst.genblk2\.rxs_rst / Q
+    Ending point:                            rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] / D
+    The start point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+
+Instance / Net                                                  Pin      Pin               Arrival     No. of    
+Name                                               Type         Name     Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rxs_rst                          FD1P3DX      Q        Out     1.015     1.015       -         
+rxs_rst                                            Net          -        -       -         -           6         
+rsl_inst.rdo_rx_serdes_rst_c_1[0]                  ORCALUT4     B        In      0.000     1.015       -         
+rsl_inst.rdo_rx_serdes_rst_c_1[0]                  ORCALUT4     Z        Out     0.708     1.723       -         
+rsl_rx_serdes_rst_c                                Net          -        -       -         -           3         
+rsl_inst.dual_or_rserd_rst                         ORCALUT4     A        In      0.000     1.723       -         
+rsl_inst.dual_or_rserd_rst                         ORCALUT4     Z        Out     0.798     2.521       -         
+dual_or_rserd_rst                                  Net          -        -       -         -           9         
+rsl_inst.rx_any_rst                                ORCALUT4     A        In      0.000     2.521       -         
+rsl_inst.rx_any_rst                                ORCALUT4     Z        Out     0.660     3.181       -         
+rx_any_rst                                         Net          -        -       -         -           2         
+rsl_inst.rx_any_rst_RNIFD021                       ORCALUT4     A        In      0.000     3.181       -         
+rsl_inst.rx_any_rst_RNIFD021                       ORCALUT4     Z        Out     0.819     4.000       -         
+rxr_wt_cnt9                                        Net          -        -       -         -           14        
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0]     CCU2C        A1       In      0.000     4.000       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0]     CCU2C        COUT     Out     0.900     4.900       -         
+rxr_wt_cnt_cry[0]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1]     CCU2C        CIN      In      0.000     4.900       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1]     CCU2C        COUT     Out     0.061     4.961       -         
+rxr_wt_cnt_cry[2]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3]     CCU2C        CIN      In      0.000     4.961       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3]     CCU2C        COUT     Out     0.061     5.022       -         
+rxr_wt_cnt_cry[4]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5]     CCU2C        CIN      In      0.000     5.022       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5]     CCU2C        COUT     Out     0.061     5.083       -         
+rxr_wt_cnt_cry[6]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7]     CCU2C        CIN      In      0.000     5.083       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7]     CCU2C        COUT     Out     0.061     5.144       -         
+rxr_wt_cnt_cry[8]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9]     CCU2C        CIN      In      0.000     5.144       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9]     CCU2C        COUT     Out     0.061     5.205       -         
+rxr_wt_cnt_cry[10]                                 Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11]      CCU2C        CIN      In      0.000     5.205       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11]      CCU2C        S0       Out     0.698     5.902       -         
+rxr_wt_cnt_s[11]                                   Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11]          FD1P3DX      D        In      0.000     5.902       -         
+=================================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|tx_pclk_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                            Starting                                                                   Arrival          
+Instance                    Reference                             Type        Pin     Net              Time        Slack
+                            Clock                                                                                       
+------------------------------------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1       sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p1     1.098       5.789
+sll_inst.ppul_sync_p2       sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p2     1.098       5.789
+sll_inst.pcount_diff[0]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_0      0.985       6.147
+sll_inst.pcount[0]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[0]        0.955       6.178
+sll_inst.pcount_diff[1]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_1      0.955       6.239
+sll_inst.pcount_diff[2]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_2      0.955       6.239
+sll_inst.pcount[1]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[1]        0.907       6.287
+sll_inst.pcount[2]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[2]        0.907       6.287
+sll_inst.pcount_diff[3]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_3      0.955       6.300
+sll_inst.pcount_diff[4]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_4      0.955       6.300
+========================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                             Starting                                                                                  Required          
+Instance                     Reference                             Type        Pin     Net                             Time         Slack
+                             Clock                                                                                                       
+-----------------------------------------------------------------------------------------------------------------------------------------
+sll_inst.pcount[21]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[21]                    9.946        5.789
+sll_inst.pcount[19]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[19]                    9.946        5.850
+sll_inst.pcount[20]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[20]                    9.946        5.850
+sll_inst.pcount[17]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[17]                    9.946        5.911
+sll_inst.pcount[18]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[18]                    9.946        5.911
+sll_inst.pcount[15]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[15]                    9.946        5.972
+sll_inst.pcount[16]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[16]                    9.946        5.972
+sll_inst.pcount[13]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[13]                    9.946        6.033
+sll_inst.pcount[14]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[14]                    9.946        6.033
+sll_inst.pcount_diff[21]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3DX     D       un1_pcount_diff_1_s_21_0_S0     9.946        6.034
+=========================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      4.157
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 5.789
+
+    Number of logic level(s):                13
+    Starting point:                          sll_inst.ppul_sync_p1 / Q
+    Ending point:                            sll_inst.pcount[21] / D
+    The start point is clocked by            sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
+
+Instance / Net                             Pin      Pin               Arrival     No. of    
+Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1         FD1S3DX      Q        Out     1.098     1.098       -         
+ppul_sync_p1                  Net          -        -       -         -           25        
+sll_inst.pcount10_0_o3        ORCALUT4     A        In      0.000     1.098       -         
+sll_inst.pcount10_0_o3        ORCALUT4     Z        Out     0.851     1.950       -         
+N_8                           Net          -        -       -         -           25        
+sll_inst.pcount_cry_0[0]      CCU2C        A1       In      0.000     1.950       -         
+sll_inst.pcount_cry_0[0]      CCU2C        COUT     Out     0.900     2.850       -         
+pcount_cry[0]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[1]      CCU2C        CIN      In      0.000     2.850       -         
+sll_inst.pcount_cry_0[1]      CCU2C        COUT     Out     0.061     2.911       -         
+pcount_cry[2]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[3]      CCU2C        CIN      In      0.000     2.911       -         
+sll_inst.pcount_cry_0[3]      CCU2C        COUT     Out     0.061     2.972       -         
+pcount_cry[4]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[5]      CCU2C        CIN      In      0.000     2.972       -         
+sll_inst.pcount_cry_0[5]      CCU2C        COUT     Out     0.061     3.033       -         
+pcount_cry[6]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[7]      CCU2C        CIN      In      0.000     3.033       -         
+sll_inst.pcount_cry_0[7]      CCU2C        COUT     Out     0.061     3.094       -         
+pcount_cry[8]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[9]      CCU2C        CIN      In      0.000     3.094       -         
+sll_inst.pcount_cry_0[9]      CCU2C        COUT     Out     0.061     3.155       -         
+pcount_cry[10]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[11]     CCU2C        CIN      In      0.000     3.155       -         
+sll_inst.pcount_cry_0[11]     CCU2C        COUT     Out     0.061     3.216       -         
+pcount_cry[12]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[13]     CCU2C        CIN      In      0.000     3.216       -         
+sll_inst.pcount_cry_0[13]     CCU2C        COUT     Out     0.061     3.277       -         
+pcount_cry[14]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[15]     CCU2C        CIN      In      0.000     3.277       -         
+sll_inst.pcount_cry_0[15]     CCU2C        COUT     Out     0.061     3.338       -         
+pcount_cry[16]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[17]     CCU2C        CIN      In      0.000     3.338       -         
+sll_inst.pcount_cry_0[17]     CCU2C        COUT     Out     0.061     3.399       -         
+pcount_cry[18]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[19]     CCU2C        CIN      In      0.000     3.399       -         
+sll_inst.pcount_cry_0[19]     CCU2C        COUT     Out     0.061     3.460       -         
+pcount_cry[20]                Net          -        -       -         -           1         
+sll_inst.pcount_s_0[21]       CCU2C        CIN      In      0.000     3.460       -         
+sll_inst.pcount_s_0[21]       CCU2C        S0       Out     0.698     4.157       -         
+pcount_s[21]                  Net          -        -       -         -           1         
+sll_inst.pcount[21]           FD1S3DX      D        In      0.000     4.157       -         
+============================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                                 Arrival          
+Instance      Reference     Type     Pin              Net              Time        Slack
+              Clock                                                                     
+----------------------------------------------------------------------------------------
+DCU0_inst     System        DCUA     CH0_FFS_RLOL     rx_cdr_lol_s     0.000       8.810
+DCU0_inst     System        DCUA     CH0_FFS_RLOS     rx_los_low_s     0.000       8.810
+========================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                       Starting                                                            Required          
+Instance                                               Reference     Type        Pin     Net                               Time         Slack
+                                                       Clock                                                                                 
+---------------------------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     SP      un2_rdo_serdes_rst_dual_c_2_i     9.806        8.810
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     D       rxpr_appd_RNO[0]                  9.946        9.556
+rsl_inst.genblk2\.rlol_p1                              System        FD1S3DX     D       rx_cdr_lol_s                      9.946        9.946
+rsl_inst.genblk2\.rlos_p1                              System        FD1S3DX     D       rx_los_low_s                      9.946        9.946
+=============================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.194
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.806
+
+    - Propagation time:                      0.996
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 8.810
+
+    Number of logic level(s):                2
+    Starting point:                          DCU0_inst / CH0_FFS_RLOL
+    Ending point:                            rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+
+Instance / Net                                                            Pin              Pin               Arrival     No. of    
+Name                                                         Type         Name             Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------------------------------------------------------
+DCU0_inst                                                    DCUA         CH0_FFS_RLOL     Out     0.000     0.000       -         
+rx_cdr_lol_s                                                 Net          -                -       -         -           4         
+rsl_inst.un2_rdo_serdes_rst_dual_c_1_1                       ORCALUT4     A                In      0.000     0.000       -         
+rsl_inst.un2_rdo_serdes_rst_dual_c_1_1                       ORCALUT4     Z                Out     0.606     0.606       -         
+un2_rdo_serdes_rst_dual_c_1_1                                Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0]     ORCALUT4     B                In      0.000     0.606       -         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0]     ORCALUT4     Z                Out     0.390     0.996       -         
+un2_rdo_serdes_rst_dual_c_2_i                                Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]           FD1P3DX      SP               In      0.000     0.996       -         
+===================================================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 221 of 24288 (1%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+CCU2C:          113
+DCUA:           1
+FD1P3BX:        20
+FD1P3DX:        92
+FD1S3BX:        12
+FD1S3DX:        97
+GSR:            1
+INV:            3
+ORCALUT4:       154
+PFUMX:          2
+PUR:            1
+VHI:            6
+VLO:            6
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 153MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Mon May 13 09:09:11 2019
+
+###########################################################]

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr.db b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr.db
new file mode 100644 (file)
index 0000000..ff725bb
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr.db differ

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.szr b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.szr
new file mode 100644 (file)
index 0000000..0838766
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.szr differ

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.xck b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.xck
new file mode 100644 (file)
index 0000000..eb3488c
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.xck
@@ -0,0 +1,3 @@
+CKID0001:@|S:pll_refclki@|E:rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001 
+CKID0002:@|S:rxrefclk@|E:rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]@|F:@syn_sample_clock_path==CKID0002@|M:ClockId0002 
+CKID0003:@|S:DCU0_inst@|E:sll_inst.pcount[21]@|F:@syn_sample_clock_path==CKID0003@|M:ClockId0003 

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_multi_srs_gen.srr b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_multi_srs_gen.srr
new file mode 100644 (file)
index 0000000..8063bb9
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_multi_srs_gen.srr
@@ -0,0 +1,11 @@
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon May 13 09:09:06 2019
+
+###########################################################]

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_multi_srs_gen.srr.db b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_multi_srs_gen.srr.db
new file mode 100644 (file)
index 0000000..029fa7a
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_multi_srs_gen.srr.db differ

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr
new file mode 100644 (file)
index 0000000..919edaa
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr
@@ -0,0 +1,86 @@
+# Mon May 13 09:09:07 2019
+
+Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.fdc
+@L: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt 
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt" file 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)
+
+@N: BN362 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances.
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist sgmii_ecp5
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+
+Clock Summary
+******************
+
+          Start                                 Requested     Requested     Clock        Clock                   Clock
+Level     Clock                                 Frequency     Period        Type         Group                   Load 
+----------------------------------------------------------------------------------------------------------------------
+0 -       System                                100.0 MHz     10.000        system       system_clkgroup         0    
+                                                                                                                      
+0 -       sgmii_ecp5|pll_refclki                100.0 MHz     10.000        inferred     Inferred_clkgroup_0     93   
+                                                                                                                      
+0 -       sgmii_ecp5|rxrefclk                   100.0 MHz     10.000        inferred     Inferred_clkgroup_1     77   
+                                                                                                                      
+0 -       sgmii_ecp5|tx_pclk_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_2     53   
+======================================================================================================================
+
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   10 -> 10
+   11 -> 11
+@N: MO225 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 144MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Mon May 13 09:09:07 2019
+
+###########################################################]

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr.db b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr.db
new file mode 100644 (file)
index 0000000..a3a5dfe
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr.db differ

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.szr b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.szr
new file mode 100644 (file)
index 0000000..07b0e0e
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.szr differ

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/syntax_constraint_check.rpt.rptmap b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/syntax_constraint_check.rpt.rptmap
new file mode 100644 (file)
index 0000000..fe7eb22
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synlog/syntax_constraint_check.rpt.rptmap
@@ -0,0 +1 @@
+./sgmii_ecp5_scck.rpt,syntax_constraint_check.rpt,Syntax Constraint Check Report

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/closed.png b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/closed.png
new file mode 100644 (file)
index 0000000..0d78634
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/closed.png differ

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/open.png b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/open.png
new file mode 100644 (file)
index 0000000..a227005
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/open.png differ

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/run_option.xml b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/run_option.xml
new file mode 100644 (file)
index 0000000..92c80ed
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/run_option.xml
@@ -0,0 +1,24 @@
+<?xml version="1.0" encoding="utf-8"?> 
+<!-- 
+  Synopsys, Inc.
+  Version M-2017.03L-SP1-1
+  Project file /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/run_option.xml
+  Written on Mon May 13 09:09:03 2019
+
+
+--> 
+<project_attribute_list name="Project Settings"> 
+     <option name="project_name" display_name="Project Name">sgmii_ecp5</option>
+     <option name="device_name" display_name="Device Name">syn_results: Lattice ECP5UM : LFE5UM_25F</option>
+     <option name="impl_name" display_name="Implementation Name">syn_results</option>
+     <option name="top_module" display_name="Top Module">sgmii_ecp5</option>
+     <option name="pipe" display_name="Pipelining">0</option>
+     <option name="retiming" display_name="Retiming">0</option>
+     <option name="resource_sharing" display_name="Resource Sharing">1</option>
+     <option name="maxfan" display_name="Fanout Guide">50</option>
+     <option name="disable_io_insertion" display_name="Disable I/O Insertion">1</option>
+     <option name="no_sequential_opt" display_name="Disable Sequential Optimizations">0</option>
+     <option name="fix_gated_and_generated_clocks" display_name="Clock Conversion">1</option>
+     <option name="symbolic_fsm_compiler" display_name="FSM Compiler">1</option>
+</project_attribute_list>
+

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5.plg b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5.plg
new file mode 100644 (file)
index 0000000..bab41a3
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5.plg
@@ -0,0 +1,28 @@
+@P:  Worst Slack : 4.043
+@P:  sgmii_ecp5|pll_refclki - Estimated Frequency : 168.9 MHz
+@P:  sgmii_ecp5|pll_refclki - Requested Frequency : 100.0 MHz
+@P:  sgmii_ecp5|pll_refclki - Estimated Period : 5.921
+@P:  sgmii_ecp5|pll_refclki - Requested Period : 10.000
+@P:  sgmii_ecp5|pll_refclki - Slack : 4.079
+@P:  sgmii_ecp5|rxrefclk - Estimated Frequency : 167.9 MHz
+@P:  sgmii_ecp5|rxrefclk - Requested Frequency : 100.0 MHz
+@P:  sgmii_ecp5|rxrefclk - Estimated Period : 5.957
+@P:  sgmii_ecp5|rxrefclk - Requested Period : 10.000
+@P:  sgmii_ecp5|rxrefclk - Slack : 4.043
+@P:  sgmii_ecp5|tx_pclk_inferred_clock - Estimated Frequency : 237.5 MHz
+@P:  sgmii_ecp5|tx_pclk_inferred_clock - Requested Frequency : 100.0 MHz
+@P:  sgmii_ecp5|tx_pclk_inferred_clock - Estimated Period : 4.211
+@P:  sgmii_ecp5|tx_pclk_inferred_clock - Requested Period : 10.000
+@P:  sgmii_ecp5|tx_pclk_inferred_clock - Slack : 5.789
+@P:  System - Estimated Frequency : 840.7 MHz
+@P:  System - Requested Frequency : 100.0 MHz
+@P:  System - Estimated Period : 1.190
+@P:  System - Requested Period : 10.000
+@P:  System - Slack : 8.810
+@P:  Total Area : 157.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  CPU Time : 0h:00m:03s

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm
new file mode 100644 (file)
index 0000000..363baae
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm
@@ -0,0 +1,1162 @@
+<html><body><samp><pre>
+<!@TC:1557731343>
+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
+#install: /home/soft/lattice/diamond/3.10_x64/synpbase
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Mon May 13 09:09:03 2019
+
+#Implementation: syn_results
+
+<a name=compilerReport1></a>Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1557731345> | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+<a name=compilerReport2></a>Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1557731345> | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1557731345> | Setting time resolution to ps
+@N: : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd:30:7:30:17:@N::@XP_MSG">sgmii_ecp5.vhd(30)</a><!@TM:1557731345> | Top entity is set to sgmii_ecp5.
+VHDL syntax check successful!
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Mon May 13 09:09:04 2019
+
+###########################################################]
+<a name=compilerReport3></a>Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1557731345> | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
+Verilog syntax check successful!
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Mon May 13 09:09:04 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1557731345> | Setting time resolution to ps
+@N: : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd:30:7:30:17:@N::@XP_MSG">sgmii_ecp5.vhd(30)</a><!@TM:1557731345> | Top entity is set to sgmii_ecp5.
+VHDL syntax check successful!
+@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd:30:7:30:17:@N:CD630:@XP_MSG">sgmii_ecp5.vhd(30)</a><!@TM:1557731345> | Synthesizing work.sgmii_ecp5.v1.
+Post processing for work.sgmii_ecp5.v1
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB)
+
+
+Process completed successfully.
+# Mon May 13 09:09:04 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
+Verilog syntax check successful!
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1968:7:1968:11:@N:CG364:@XP_MSG">sgmii_ecp5_softlogic.v(1968)</a><!@TM:1557731345> | Synthesizing module sync in library work.
+
+       PDATA_RST_VAL=32'b00000000000000000000000000000000
+   Generated name = sync_0s
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1051:7:1051:25:@N:CG364:@XP_MSG">sgmii_ecp5_softlogic.v(1051)</a><!@TM:1557731345> | Synthesizing module sgmii_ecp5sll_core in library work.
+
+       PPROTOCOL=24'b010001110100001001000101
+       PLOL_SETTING=32'b00000000000000000000000000000000
+       PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100
+       PPCIE_MAX_RATE=24'b001100100010111000110101
+       PDIFF_VAL_LOCK=32'b00000000000000000000000000100111
+       PDIFF_VAL_UNLOCK=32'b00000000000000000000000001001110
+       PPCLK_TC=32'b00000000000000100000000000000000
+       PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000
+       PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000
+       PPCLK_DIV11_TC=32'b00000000000000000000000000000000
+       LPLL_LOSS_ST=2'b00
+       LPLL_PRELOSS_ST=2'b01
+       LPLL_PRELOCK_ST=2'b10
+       LPLL_LOCK_ST=2'b11
+       LRCLK_TC=16'b1111111111111111
+       LRCLK_TC_PUL_WIDTH=16'b0000000000110010
+       LHB_WAIT_CNT=8'b11111111
+       LPCLK_TC_0=32'b00000000000000001000000000000000
+       LPCLK_TC_1=32'b00000000000000010000000000000000
+       LPCLK_TC_2=32'b00000000000000100000000000000000
+       LPCLK_TC_3=32'b00000000000000101000000000000000
+       LPCLK_TC_4=32'b00000000000000010000000000000000
+       LPDIFF_LOCK_00=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_10=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_20=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_30=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_40=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_01=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_11=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_21=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_31=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_41=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_02=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_12=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_22=32'b00000000000000000000000011000100
+       LPDIFF_LOCK_32=32'b00000000000000000000000011110101
+       LPDIFF_LOCK_42=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_03=32'b00000000000000000000000010000011
+       LPDIFF_LOCK_13=32'b00000000000000000000000100000110
+       LPDIFF_LOCK_23=32'b00000000000000000000001000001100
+       LPDIFF_LOCK_33=32'b00000000000000000000001010001111
+       LPDIFF_LOCK_43=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011
+       LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110
+       LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010
+       LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001
+       LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111
+       LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000
+       LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000
+       LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000
+       LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100
+       LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001
+       LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010
+       LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111
+       LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001
+   Generated name = sgmii_ecp5sll_core_Z1_layer1
+@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1287:54:1287:60:@N:CG179:@XP_MSG">sgmii_ecp5_softlogic.v(1287)</a><!@TM:1557731345> | Removing redundant assignment.
+@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1293:52:1293:56:@N:CG179:@XP_MSG">sgmii_ecp5_softlogic.v(1293)</a><!@TM:1557731345> | Removing redundant assignment.
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1350:0:1350:6:@W:CL169:@XP_MSG">sgmii_ecp5_softlogic.v(1350)</a><!@TM:1557731345> | Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:92:7:92:25:@N:CG364:@XP_MSG">sgmii_ecp5_softlogic.v(92)</a><!@TM:1557731345> | Synthesizing module sgmii_ecp5rsl_core in library work.
+
+       pnum_channels=32'b00000000000000000000000000000001
+       pprotocol=24'b010001110100001001000101
+       pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
+       pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_tx_rdy=32'b00000000000000000000101110111000
+       pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_rx_rdy=32'b00000000000000000000101110111000
+       wa_num_cycles=32'b00000000000000000000010000000000
+       dac_num_cycles=32'b00000000000000000000000000000011
+       lreset_pwidth=32'b00000000000000000000000000000011
+       lwait_b4_trst=32'b00000000000010111110101111000010
+       lwait_b4_trst_s=32'b00000000000000000000001100001101
+       lplol_cnt_width=32'b00000000000000000000000000010100
+       lwait_after_plol0=32'b00000000000000000000000000000100
+       lwait_b4_rrst=32'b00000000000000101100000000000000
+       lrrst_wait_width=32'b00000000000000000000000000010100
+       lwait_after_rrst=32'b00000000000011000011010100000000
+       lwait_b4_rrst_s=32'b00000000000000000000000111001100
+       lrlol_cnt_width=32'b00000000000000000000000000010011
+       lwait_after_lols=32'b00000000000000001100010000000000
+       lwait_after_lols_s=32'b00000000000000000000000010010110
+       llols_cnt_width=32'b00000000000000000000000000010010
+       lrdb_max=32'b00000000000000000000000000001111
+       ltxr_wait_width=32'b00000000000000000000000000001100
+       lrxr_wait_width=32'b00000000000000000000000000001100
+   Generated name = sgmii_ecp5rsl_core_Z2_layer1
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:326:33:326:41:@W:CG133:@XP_MSG">sgmii_ecp5_softlogic.v(326)</a><!@TM:1557731345> | Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:327:33:327:44:@W:CG360:@XP_MSG">sgmii_ecp5_softlogic.v(327)</a><!@TM:1557731345> | Removing wire rrst_cnt_tc, as there is no assignment to it.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:328:33:328:42:@W:CG133:@XP_MSG">sgmii_ecp5_softlogic.v(328)</a><!@TM:1557731345> | Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:341:33:341:40:@W:CG133:@XP_MSG">sgmii_ecp5_softlogic.v(341)</a><!@TM:1557731345> | Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:342:33:342:40:@W:CG133:@XP_MSG">sgmii_ecp5_softlogic.v(342)</a><!@TM:1557731345> | Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:343:33:343:43:@W:CG360:@XP_MSG">sgmii_ecp5_softlogic.v(343)</a><!@TM:1557731345> | Removing wire rxp_cnt_tc, as there is no assignment to it.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:346:33:346:43:@W:CG133:@XP_MSG">sgmii_ecp5_softlogic.v(346)</a><!@TM:1557731345> | Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:347:33:347:46:@W:CG360:@XP_MSG">sgmii_ecp5_softlogic.v(347)</a><!@TM:1557731345> | Removing wire rlolsz_cnt_tc, as there is no assignment to it.</font>
+<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:350:33:350:44:@W:CG360:@XP_MSG">sgmii_ecp5_softlogic.v(350)</a><!@TM:1557731345> | Removing wire rxp_cnt2_tc, as there is no assignment to it.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:351:33:351:48:@W:CG133:@XP_MSG">sgmii_ecp5_softlogic.v(351)</a><!@TM:1557731345> | Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:352:33:352:44:@W:CG133:@XP_MSG">sgmii_ecp5_softlogic.v(352)</a><!@TM:1557731345> | Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:353:33:353:47:@W:CG360:@XP_MSG">sgmii_ecp5_softlogic.v(353)</a><!@TM:1557731345> | Removing wire data_loop_b_tc, as there is no assignment to it.</font>
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:806:3:806:9:@W:CL169:@XP_MSG">sgmii_ecp5_softlogic.v(806)</a><!@TM:1557731345> | Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.</font>
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:567:3:567:9:@W:CL169:@XP_MSG">sgmii_ecp5_softlogic.v(567)</a><!@TM:1557731345> | Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.</font>
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:567:3:567:9:@W:CL169:@XP_MSG">sgmii_ecp5_softlogic.v(567)</a><!@TM:1557731345> | Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.</font>
+<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:694:3:694:9:@W:CL190:@XP_MSG">sgmii_ecp5_softlogic.v(694)</a><!@TM:1557731345> | Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
+<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:461:3:461:9:@W:CL190:@XP_MSG">sgmii_ecp5_softlogic.v(461)</a><!@TM:1557731345> | Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
+<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:422:3:422:9:@W:CL190:@XP_MSG">sgmii_ecp5_softlogic.v(422)</a><!@TM:1557731345> | Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
+<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:422:3:422:9:@W:CL260:@XP_MSG">sgmii_ecp5_softlogic.v(422)</a><!@TM:1557731345> | Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
+<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:461:3:461:9:@W:CL260:@XP_MSG">sgmii_ecp5_softlogic.v(461)</a><!@TM:1557731345> | Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
+<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:694:3:694:9:@W:CL260:@XP_MSG">sgmii_ecp5_softlogic.v(694)</a><!@TM:1557731345> | Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
+<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:200:33:200:49:@W:CL246:@XP_MSG">sgmii_ecp5_softlogic.v(200)</a><!@TM:1557731345> | Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.</font>
+<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:204:33:204:52:@W:CL246:@XP_MSG">sgmii_ecp5_softlogic.v(204)</a><!@TM:1557731345> | Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.</font>
+<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:205:33:205:49:@W:CL246:@XP_MSG">sgmii_ecp5_softlogic.v(205)</a><!@TM:1557731345> | Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.</font>
+<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:206:33:206:49:@W:CL246:@XP_MSG">sgmii_ecp5_softlogic.v(206)</a><!@TM:1557731345> | Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.</font>
+<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:207:33:207:49:@W:CL246:@XP_MSG">sgmii_ecp5_softlogic.v(207)</a><!@TM:1557731345> | Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.</font>
+<font color=#A52A2A>@W:<a href="@W:CL279:@XP_HELP">CL279</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL279:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.</font>
+<font color=#A52A2A>@W:<a href="@W:CL279:@XP_HELP">CL279</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL279:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.</font>
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL169:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers.</font>
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL169:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557731345> | Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers.</font>
+@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1801:0:1801:6:@N:CL201:@XP_MSG">sgmii_ecp5_softlogic.v(1801)</a><!@TM:1557731345> | Trying to extract state machine for register sll_state.
+Extracted state machine for register sll_state
+State machine has 4 reachable states with original encodings of:
+   00
+   01
+   10
+   11
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB)
+
+
+Process completed successfully.
+# Mon May 13 09:09:05 2019
+
+###########################################################]
+<a name=compilerReport4></a>Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1557731345> | Running in 64-bit mode 
+
+=======================================================================================
+For a summary of linker messages for components that did not bind, please see log file:
+Linked File: <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.linkerlog:@XP_FILE">sgmii_ecp5_comp.linkerlog</a>
+=======================================================================================
+
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon May 13 09:09:05 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon May 13 09:09:05 2019
+
+###########################################################]
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1557731343>
+<a name=compilerReport5></a>Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1557731346> | Running in 64-bit mode 
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon May 13 09:09:06 2019
+
+###########################################################]
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1557731343>
+Pre-mapping Report
+
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1557731343>
+# Mon May 13 09:09:07 2019
+
+<a name=mapperReport6></a>Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35</a>
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.fdc
+Linked File: <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt:@XP_FILE">sgmii_ecp5_scck.rpt</a>
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt" file 
+@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1557731347> | Running in 64-bit mode. 
+@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1557731347> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)
+
+@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1408:0:1408:6:@N:BN362:@XP_MSG">sgmii_ecp5_softlogic.v(1408)</a><!@TM:1557731347> | Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
+@N:<a href="@N:BN115:@XP_HELP">BN115</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1244:27:1244:41:@N:BN115:@XP_MSG">sgmii_ecp5_softlogic.v(1244)</a><!@TM:1557731347> | Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances.
+@N:<a href="@N:BN115:@XP_HELP">BN115</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1252:27:1252:42:@N:BN115:@XP_MSG">sgmii_ecp5_softlogic.v(1252)</a><!@TM:1557731347> | Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances.
+@N:<a href="@N:BN115:@XP_HELP">BN115</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1236:27:1236:41:@N:BN115:@XP_MSG">sgmii_ecp5_softlogic.v(1236)</a><!@TM:1557731347> | Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances.
+@N:<a href="@N:BN115:@XP_HELP">BN115</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1268:27:1268:45:@N:BN115:@XP_MSG">sgmii_ecp5_softlogic.v(1268)</a><!@TM:1557731347> | Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances.
+@N:<a href="@N:BN115:@XP_HELP">BN115</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1260:27:1260:45:@N:BN115:@XP_MSG">sgmii_ecp5_softlogic.v(1260)</a><!@TM:1557731347> | Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances.
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist sgmii_ecp5
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+
+<a name=mapperReport7></a>Clock Summary</a>
+******************
+
+          Start                                 Requested     Requested     Clock        Clock                   Clock
+Level     Clock                                 Frequency     Period        Type         Group                   Load 
+----------------------------------------------------------------------------------------------------------------------
+0 -       System                                100.0 MHz     10.000        system       system_clkgroup         0    
+                                                                                                                      
+0 -       sgmii_ecp5|pll_refclki                100.0 MHz     10.000        inferred     Inferred_clkgroup_0     93   
+                                                                                                                      
+0 -       sgmii_ecp5|rxrefclk                   100.0 MHz     10.000        inferred     Inferred_clkgroup_1     77   
+                                                                                                                      
+0 -       sgmii_ecp5|tx_pclk_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_2     53   
+======================================================================================================================
+
+<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1988:0:1988:6:@W:MT529:@XP_MSG">sgmii_ecp5_softlogic.v(1988)</a><!@TM:1557731347> | Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
+<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:567:3:567:9:@W:MT529:@XP_MSG">sgmii_ecp5_softlogic.v(567)</a><!@TM:1557731347> | Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
+<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1988:0:1988:6:@W:MT529:@XP_MSG">sgmii_ecp5_softlogic.v(1988)</a><!@TM:1557731347> | Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   10 -> 10
+   11 -> 11
+@N:<a href="@N:MO225:@XP_HELP">MO225</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1801:0:1801:6:@N:MO225:@XP_MSG">sgmii_ecp5_softlogic.v(1801)</a><!@TM:1557731347> | There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 144MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Mon May 13 09:09:07 2019
+
+###########################################################]
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1557731343>
+Map & Optimize Report
+
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1557731343>
+# Mon May 13 09:09:07 2019
+
+<a name=mapperReport8></a>Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35</a>
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1557731351> | Running in 64-bit mode. 
+@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1557731351> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   10 -> 10
+   11 -> 11
+@N:<a href="@N:MO225:@XP_HELP">MO225</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1801:0:1801:6:@N:MO225:@XP_MSG">sgmii_ecp5_softlogic.v(1801)</a><!@TM:1557731351> | There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1350:0:1350:6:@N:MO231:@XP_MSG">sgmii_ecp5_softlogic.v(1350)</a><!@TM:1557731351> | Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] 
+@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1304:0:1304:6:@N:MO231:@XP_MSG">sgmii_ecp5_softlogic.v(1304)</a><!@TM:1557731351> | Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] 
+@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1759:0:1759:6:@N:MO231:@XP_MSG">sgmii_ecp5_softlogic.v(1759)</a><!@TM:1557731351> | Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] 
+@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:412:3:412:9:@N:MO231:@XP_MSG">sgmii_ecp5_softlogic.v(412)</a><!@TM:1557731351> | Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] 
+@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:909:3:909:9:@N:MO231:@XP_MSG">sgmii_ecp5_softlogic.v(909)</a><!@TM:1557731351> | Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] 
+@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:527:3:527:9:@N:MO231:@XP_MSG">sgmii_ecp5_softlogic.v(527)</a><!@TM:1557731351> | Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] 
+@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:778:3:778:9:@N:MO231:@XP_MSG">sgmii_ecp5_softlogic.v(778)</a><!@TM:1557731351> | Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] 
+@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:680:3:680:9:@N:MO231:@XP_MSG">sgmii_ecp5_softlogic.v(680)</a><!@TM:1557731351> | Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] 
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+@N:<a href="@N:FX1019:@XP_HELP">FX1019</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1988:0:1988:6:@N:FX1019:@XP_MSG">sgmii_ecp5_softlogic.v(1988)</a><!@TM:1557731351> | Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N:<a href="@N:FX1019:@XP_HELP">FX1019</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1988:0:1988:6:@N:FX1019:@XP_MSG">sgmii_ecp5_softlogic.v(1988)</a><!@TM:1557731351> | Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N:<a href="@N:FX1019:@XP_HELP">FX1019</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1988:0:1988:6:@N:FX1019:@XP_MSG">sgmii_ecp5_softlogic.v(1988)</a><!@TM:1557731351> | Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+   1           0h:00m:01s                   4.90ns              155 /       221
+@N:<a href="@N:FX1019:@XP_HELP">FX1019</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1988:0:1988:6:@N:FX1019:@XP_MSG">sgmii_ecp5_softlogic.v(1988)</a><!@TM:1557731351> | Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N:<a href="@N:FX1019:@XP_HELP">FX1019</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1988:0:1988:6:@N:FX1019:@XP_MSG">sgmii_ecp5_softlogic.v(1988)</a><!@TM:1557731351> | Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N:<a href="@N:FX1019:@XP_HELP">FX1019</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v:1988:0:1988:6:@N:FX1019:@XP_MSG">sgmii_ecp5_softlogic.v(1988)</a><!@TM:1557731351> | Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB)
+
+@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1557731351> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 148MB peak: 149MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+<a name=clockReport9></a>#### START OF CLOCK OPTIMIZATION REPORT #####[</a>
+
+3 non-gated/non-generated clock tree(s) driving 221 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+============================================= Non-Gated/Non-Generated Clocks =============================================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                                   
+--------------------------------------------------------------------------------------------------------------------------
+<a href="@|S:pll_refclki@|E:rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001  @XP_NAMES_BY_PROP">ClockId0001 </a>       pll_refclki         port                   91         rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]
+<a href="@|S:rxrefclk@|E:rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]@|F:@syn_sample_clock_path==CKID0002@|M:ClockId0002  @XP_NAMES_BY_PROP">ClockId0002 </a>       rxrefclk            port                   77         rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]
+<a href="@|S:DCU0_inst@|E:sll_inst.pcount[21]@|F:@syn_sample_clock_path==CKID0003@|M:ClockId0003  @XP_NAMES_BY_PROP">ClockId0003 </a>       DCU0_inst           DCUA                   53         sll_inst.pcount[21]                               
+==========================================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 112MB peak: 149MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 149MB)
+
+Writing EDIF Netlist and constraint files
+@N:<a href="@N:FX1056:@XP_HELP">FX1056</a> : <!@TM:1557731351> | Writing EDF file: /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.edn 
+M-2017.03L-SP1-1
+@N:<a href="@N:BW106:@XP_HELP">BW106</a> : <!@TM:1557731351> | Synplicity Constraint File capacitance units using default value of 1pF  
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 153MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+<font color=#A52A2A>@W:<a href="@W:MT246:@XP_HELP">MT246</a> : <a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd:162:4:162:13:@W:MT246:@XP_MSG">sgmii_ecp5.vhd(162)</a><!@TM:1557731351> | Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) </font>
+<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1557731351> | Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"</font> 
+<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1557731351> | Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"</font> 
+<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1557731351> | Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk"</font> 
+
+
+<a name=timingReport10></a>##### START OF TIMING REPORT #####[</a>
+# Timing Report written on Mon May 13 09:09:11 2019
+#
+
+
+Top view:               sgmii_ecp5
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.fdc
+                       
+@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1557731351> | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 
+
+@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1557731351> | Clock constraints include only register-to-register paths associated with each individual clock. 
+
+
+
+<a name=performanceSummary11></a>Performance Summary</a>
+*******************
+
+
+Worst slack in design: 4.043
+
+                                      Requested     Estimated     Requested     Estimated               Clock        Clock              
+Starting Clock                        Frequency     Frequency     Period        Period        Slack     Type         Group              
+----------------------------------------------------------------------------------------------------------------------------------------
+sgmii_ecp5|pll_refclki                100.0 MHz     168.9 MHz     10.000        5.921         4.079     inferred     Inferred_clkgroup_0
+sgmii_ecp5|rxrefclk                   100.0 MHz     167.9 MHz     10.000        5.957         4.043     inferred     Inferred_clkgroup_1
+sgmii_ecp5|tx_pclk_inferred_clock     100.0 MHz     237.5 MHz     10.000        4.211         5.789     inferred     Inferred_clkgroup_2
+System                                100.0 MHz     840.7 MHz     10.000        1.190         8.810     system       system_clkgroup    
+========================================================================================================================================
+
+
+
+
+
+<a name=clockRelationships12></a>Clock Relationships</a>
+*******************
+
+Clocks                                                                |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+Starting                           Ending                             |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+System                             sgmii_ecp5|rxrefclk                |  10.000      8.811  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             System                             |  10.000      8.253  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             sgmii_ecp5|pll_refclki             |  10.000      4.079  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             sgmii_ecp5|tx_pclk_inferred_clock  |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|rxrefclk                System                             |  10.000      8.277  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|rxrefclk                sgmii_ecp5|rxrefclk                |  10.000      4.043  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|tx_pclk_inferred_clock  sgmii_ecp5|pll_refclki             |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|tx_pclk_inferred_clock  sgmii_ecp5|tx_pclk_inferred_clock  |  10.000      5.789  |  No paths    -      |  No paths    -      |  No paths    -    
+============================================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+<a name=interfaceInfo13></a>Interface Information </a>
+*********************
+
+No IO constraint found
+
+
+
+====================================
+<a name=clockReport14></a>Detailed Report for Clock: sgmii_ecp5|pll_refclki</a>
+====================================
+
+
+
+<a name=startingSlack15></a>Starting Points with Worst Slack</a>
+********************************
+
+                                   Starting                                                        Arrival          
+Instance                           Reference                  Type        Pin     Net              Time        Slack
+                                   Clock                                                                            
+--------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[2]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[2]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[3]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[3]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[17]     sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[17]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[19]     sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[19]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[1]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[1]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[4]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[4]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[5]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[5]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[6]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[6]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[7]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[7]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[8]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[8]      0.907       4.684
+====================================================================================================================
+
+
+<a name=endingSlack16></a>Ending Points with Worst Slack</a>
+******************************
+
+                                   Starting                                                          Required          
+Instance                           Reference                  Type        Pin     Net                Time         Slack
+                                   Clock                                                                               
+-----------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[19]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[19]     9.946        4.079
+rsl_inst.genblk1\.plol_cnt[17]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[17]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[18]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[18]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[15]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[15]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[16]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[16]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[13]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[13]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[14]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[14]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[11]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[11]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[12]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[12]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[9]      sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[9]      9.946        4.383
+=======================================================================================================================
+
+
+
+<a name=worstPaths17></a>Worst Path Information</a>
+<a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.srr:srsf/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.srs:fp:61420:66412:@XP_NAMES_GATE">View Worst Path in Analyst</a>
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.867
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.079
+
+    Number of logic level(s):                15
+    Starting point:                          rsl_inst.genblk1\.plol_cnt[2] / Q
+    Ending point:                            rsl_inst.genblk1\.plol_cnt[19] / D
+    The start point is clocked by            sgmii_ecp5|pll_refclki [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|pll_refclki [rising] on pin CK
+
+Instance / Net                                        Pin      Pin               Arrival     No. of    
+Name                                     Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[2]            FD1S3DX      Q        Out     0.907     0.907       -         
+plol_cnt[2]                              Net          -        -       -         -           2         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     Z        Out     0.606     1.513       -         
+un1_plol_cnt_tc_10                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     Z        Out     0.606     2.119       -         
+un1_plol_cnt_tc_14                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     Z        Out     0.762     2.881       -         
+un1_plol_cnt_tc                          Net          -        -       -         -           5         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     B        In      0.000     2.881       -         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     Z        Out     0.840     3.721       -         
+plol_cnt                                 Net          -        -       -         -           21        
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.721       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.621       -         
+plol_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.621       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.682       -         
+plol_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.682       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.743       -         
+plol_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.743       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.804       -         
+plol_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.804       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.865       -         
+plol_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.865       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.926       -         
+plol_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.926       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.987       -         
+plol_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.987       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.048       -         
+plol_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.048       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.109       -         
+plol_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.109       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        COUT     Out     0.061     5.170       -         
+plol_cnt_cry[18]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        CIN      In      0.000     5.170       -         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        S0       Out     0.698     5.867       -         
+plol_cnt_s[19]                           Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt[19]           FD1S3DX      D        In      0.000     5.867       -         
+=======================================================================================================
+
+
+
+
+====================================
+<a name=clockReport18></a>Detailed Report for Clock: sgmii_ecp5|rxrefclk</a>
+====================================
+
+
+
+<a name=startingSlack19></a>Starting Points with Worst Slack</a>
+********************************
+
+                                    Starting                                                      Arrival          
+Instance                            Reference               Type        Pin     Net               Time        Slack
+                                    Clock                                                                          
+-------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rxs_rst           sgmii_ecp5|rxrefclk     FD1P3DX     Q       rxs_rst           1.015       4.043
+rsl_inst.genblk2\.rlol1_cnt[7]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[7]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[8]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[8]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[9]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[9]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[10]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[10]     0.907       4.136
+rsl_inst.genblk2\.rlols0_cnt[1]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[1]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[2]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[2]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[3]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[3]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[4]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[4]     0.907       4.170
+rsl_inst.genblk2\.rlol1_cnt[0]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[0]      0.907       4.742
+===================================================================================================================
+
+
+<a name=endingSlack20></a>Ending Points with Worst Slack</a>
+******************************
+
+                                              Starting                                                         Required          
+Instance                                      Reference               Type        Pin     Net                  Time         Slack
+                                              Clock                                                                              
+---------------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[11]     9.946        4.043
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[9]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[9]      9.946        4.104
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[10]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[10]     9.946        4.104
+rsl_inst.genblk2\.rlol1_cnt[17]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[17]      9.946        4.136
+rsl_inst.genblk2\.rlol1_cnt[18]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[18]      9.946        4.136
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[7]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[7]      9.946        4.165
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[8]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[8]      9.946        4.165
+rsl_inst.genblk2\.rlols0_cnt[17]              sgmii_ecp5|rxrefclk     FD1P3DX     D       rlols0_cnt_s[17]     9.946        4.170
+rsl_inst.genblk2\.rlol1_cnt[15]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[15]      9.946        4.197
+rsl_inst.genblk2\.rlol1_cnt[16]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[16]      9.946        4.197
+=================================================================================================================================
+
+
+
+<a name=worstPaths21></a>Worst Path Information</a>
+<a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.srr:srsf/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.srs:fp:71656:75760:@XP_NAMES_GATE">View Worst Path in Analyst</a>
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.902
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     4.043
+
+    Number of logic level(s):                11
+    Starting point:                          rsl_inst.genblk2\.rxs_rst / Q
+    Ending point:                            rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] / D
+    The start point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+
+Instance / Net                                                  Pin      Pin               Arrival     No. of    
+Name                                               Type         Name     Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rxs_rst                          FD1P3DX      Q        Out     1.015     1.015       -         
+rxs_rst                                            Net          -        -       -         -           6         
+rsl_inst.rdo_rx_serdes_rst_c_1[0]                  ORCALUT4     B        In      0.000     1.015       -         
+rsl_inst.rdo_rx_serdes_rst_c_1[0]                  ORCALUT4     Z        Out     0.708     1.723       -         
+rsl_rx_serdes_rst_c                                Net          -        -       -         -           3         
+rsl_inst.dual_or_rserd_rst                         ORCALUT4     A        In      0.000     1.723       -         
+rsl_inst.dual_or_rserd_rst                         ORCALUT4     Z        Out     0.798     2.521       -         
+dual_or_rserd_rst                                  Net          -        -       -         -           9         
+rsl_inst.rx_any_rst                                ORCALUT4     A        In      0.000     2.521       -         
+rsl_inst.rx_any_rst                                ORCALUT4     Z        Out     0.660     3.181       -         
+rx_any_rst                                         Net          -        -       -         -           2         
+rsl_inst.rx_any_rst_RNIFD021                       ORCALUT4     A        In      0.000     3.181       -         
+rsl_inst.rx_any_rst_RNIFD021                       ORCALUT4     Z        Out     0.819     4.000       -         
+rxr_wt_cnt9                                        Net          -        -       -         -           14        
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0]     CCU2C        A1       In      0.000     4.000       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0]     CCU2C        COUT     Out     0.900     4.900       -         
+rxr_wt_cnt_cry[0]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1]     CCU2C        CIN      In      0.000     4.900       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1]     CCU2C        COUT     Out     0.061     4.961       -         
+rxr_wt_cnt_cry[2]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3]     CCU2C        CIN      In      0.000     4.961       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3]     CCU2C        COUT     Out     0.061     5.022       -         
+rxr_wt_cnt_cry[4]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5]     CCU2C        CIN      In      0.000     5.022       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5]     CCU2C        COUT     Out     0.061     5.083       -         
+rxr_wt_cnt_cry[6]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7]     CCU2C        CIN      In      0.000     5.083       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7]     CCU2C        COUT     Out     0.061     5.144       -         
+rxr_wt_cnt_cry[8]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9]     CCU2C        CIN      In      0.000     5.144       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9]     CCU2C        COUT     Out     0.061     5.205       -         
+rxr_wt_cnt_cry[10]                                 Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11]      CCU2C        CIN      In      0.000     5.205       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11]      CCU2C        S0       Out     0.698     5.902       -         
+rxr_wt_cnt_s[11]                                   Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11]          FD1P3DX      D        In      0.000     5.902       -         
+=================================================================================================================
+
+
+
+
+====================================
+<a name=clockReport22></a>Detailed Report for Clock: sgmii_ecp5|tx_pclk_inferred_clock</a>
+====================================
+
+
+
+<a name=startingSlack23></a>Starting Points with Worst Slack</a>
+********************************
+
+                            Starting                                                                   Arrival          
+Instance                    Reference                             Type        Pin     Net              Time        Slack
+                            Clock                                                                                       
+------------------------------------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1       sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p1     1.098       5.789
+sll_inst.ppul_sync_p2       sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p2     1.098       5.789
+sll_inst.pcount_diff[0]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_0      0.985       6.147
+sll_inst.pcount[0]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[0]        0.955       6.178
+sll_inst.pcount_diff[1]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_1      0.955       6.239
+sll_inst.pcount_diff[2]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_2      0.955       6.239
+sll_inst.pcount[1]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[1]        0.907       6.287
+sll_inst.pcount[2]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[2]        0.907       6.287
+sll_inst.pcount_diff[3]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_3      0.955       6.300
+sll_inst.pcount_diff[4]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_4      0.955       6.300
+========================================================================================================================
+
+
+<a name=endingSlack24></a>Ending Points with Worst Slack</a>
+******************************
+
+                             Starting                                                                                  Required          
+Instance                     Reference                             Type        Pin     Net                             Time         Slack
+                             Clock                                                                                                       
+-----------------------------------------------------------------------------------------------------------------------------------------
+sll_inst.pcount[21]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[21]                    9.946        5.789
+sll_inst.pcount[19]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[19]                    9.946        5.850
+sll_inst.pcount[20]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[20]                    9.946        5.850
+sll_inst.pcount[17]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[17]                    9.946        5.911
+sll_inst.pcount[18]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[18]                    9.946        5.911
+sll_inst.pcount[15]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[15]                    9.946        5.972
+sll_inst.pcount[16]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[16]                    9.946        5.972
+sll_inst.pcount[13]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[13]                    9.946        6.033
+sll_inst.pcount[14]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[14]                    9.946        6.033
+sll_inst.pcount_diff[21]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3DX     D       un1_pcount_diff_1_s_21_0_S0     9.946        6.034
+=========================================================================================================================================
+
+
+
+<a name=worstPaths25></a>Worst Path Information</a>
+<a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.srr:srsf/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.srs:fp:81162:85068:@XP_NAMES_GATE">View Worst Path in Analyst</a>
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      4.157
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 5.789
+
+    Number of logic level(s):                13
+    Starting point:                          sll_inst.ppul_sync_p1 / Q
+    Ending point:                            sll_inst.pcount[21] / D
+    The start point is clocked by            sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
+
+Instance / Net                             Pin      Pin               Arrival     No. of    
+Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1         FD1S3DX      Q        Out     1.098     1.098       -         
+ppul_sync_p1                  Net          -        -       -         -           25        
+sll_inst.pcount10_0_o3        ORCALUT4     A        In      0.000     1.098       -         
+sll_inst.pcount10_0_o3        ORCALUT4     Z        Out     0.851     1.950       -         
+N_8                           Net          -        -       -         -           25        
+sll_inst.pcount_cry_0[0]      CCU2C        A1       In      0.000     1.950       -         
+sll_inst.pcount_cry_0[0]      CCU2C        COUT     Out     0.900     2.850       -         
+pcount_cry[0]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[1]      CCU2C        CIN      In      0.000     2.850       -         
+sll_inst.pcount_cry_0[1]      CCU2C        COUT     Out     0.061     2.911       -         
+pcount_cry[2]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[3]      CCU2C        CIN      In      0.000     2.911       -         
+sll_inst.pcount_cry_0[3]      CCU2C        COUT     Out     0.061     2.972       -         
+pcount_cry[4]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[5]      CCU2C        CIN      In      0.000     2.972       -         
+sll_inst.pcount_cry_0[5]      CCU2C        COUT     Out     0.061     3.033       -         
+pcount_cry[6]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[7]      CCU2C        CIN      In      0.000     3.033       -         
+sll_inst.pcount_cry_0[7]      CCU2C        COUT     Out     0.061     3.094       -         
+pcount_cry[8]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[9]      CCU2C        CIN      In      0.000     3.094       -         
+sll_inst.pcount_cry_0[9]      CCU2C        COUT     Out     0.061     3.155       -         
+pcount_cry[10]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[11]     CCU2C        CIN      In      0.000     3.155       -         
+sll_inst.pcount_cry_0[11]     CCU2C        COUT     Out     0.061     3.216       -         
+pcount_cry[12]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[13]     CCU2C        CIN      In      0.000     3.216       -         
+sll_inst.pcount_cry_0[13]     CCU2C        COUT     Out     0.061     3.277       -         
+pcount_cry[14]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[15]     CCU2C        CIN      In      0.000     3.277       -         
+sll_inst.pcount_cry_0[15]     CCU2C        COUT     Out     0.061     3.338       -         
+pcount_cry[16]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[17]     CCU2C        CIN      In      0.000     3.338       -         
+sll_inst.pcount_cry_0[17]     CCU2C        COUT     Out     0.061     3.399       -         
+pcount_cry[18]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[19]     CCU2C        CIN      In      0.000     3.399       -         
+sll_inst.pcount_cry_0[19]     CCU2C        COUT     Out     0.061     3.460       -         
+pcount_cry[20]                Net          -        -       -         -           1         
+sll_inst.pcount_s_0[21]       CCU2C        CIN      In      0.000     3.460       -         
+sll_inst.pcount_s_0[21]       CCU2C        S0       Out     0.698     4.157       -         
+pcount_s[21]                  Net          -        -       -         -           1         
+sll_inst.pcount[21]           FD1S3DX      D        In      0.000     4.157       -         
+============================================================================================
+
+
+
+
+====================================
+<a name=clockReport26></a>Detailed Report for Clock: System</a>
+====================================
+
+
+
+<a name=startingSlack27></a>Starting Points with Worst Slack</a>
+********************************
+
+              Starting                                                 Arrival          
+Instance      Reference     Type     Pin              Net              Time        Slack
+              Clock                                                                     
+----------------------------------------------------------------------------------------
+DCU0_inst     System        DCUA     CH0_FFS_RLOL     rx_cdr_lol_s     0.000       8.810
+DCU0_inst     System        DCUA     CH0_FFS_RLOS     rx_los_low_s     0.000       8.810
+========================================================================================
+
+
+<a name=endingSlack28></a>Ending Points with Worst Slack</a>
+******************************
+
+                                                       Starting                                                            Required          
+Instance                                               Reference     Type        Pin     Net                               Time         Slack
+                                                       Clock                                                                                 
+---------------------------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     SP      un2_rdo_serdes_rst_dual_c_2_i     9.806        8.810
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     D       rxpr_appd_RNO[0]                  9.946        9.556
+rsl_inst.genblk2\.rlol_p1                              System        FD1S3DX     D       rx_cdr_lol_s                      9.946        9.946
+rsl_inst.genblk2\.rlos_p1                              System        FD1S3DX     D       rx_los_low_s                      9.946        9.946
+=============================================================================================================================================
+
+
+
+<a name=worstPaths29></a>Worst Path Information</a>
+<a href="/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.srr:srsf/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5.srs:fp:88586:89774:@XP_NAMES_GATE">View Worst Path in Analyst</a>
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.194
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.806
+
+    - Propagation time:                      0.996
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 8.810
+
+    Number of logic level(s):                2
+    Starting point:                          DCU0_inst / CH0_FFS_RLOL
+    Ending point:                            rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+
+Instance / Net                                                            Pin              Pin               Arrival     No. of    
+Name                                                         Type         Name             Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------------------------------------------------------
+DCU0_inst                                                    DCUA         CH0_FFS_RLOL     Out     0.000     0.000       -         
+rx_cdr_lol_s                                                 Net          -                -       -         -           4         
+rsl_inst.un2_rdo_serdes_rst_dual_c_1_1                       ORCALUT4     A                In      0.000     0.000       -         
+rsl_inst.un2_rdo_serdes_rst_dual_c_1_1                       ORCALUT4     Z                Out     0.606     0.606       -         
+un2_rdo_serdes_rst_dual_c_1_1                                Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0]     ORCALUT4     B                In      0.000     0.606       -         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0]     ORCALUT4     Z                Out     0.390     0.996       -         
+un2_rdo_serdes_rst_dual_c_2_i                                Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]           FD1P3DX      SP               In      0.000     0.996       -         
+===================================================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+---------------------------------------
+<a name=resourceUsage30></a>Resource Usage Report</a>
+Part: lfe5um_25f-6
+
+Register bits: 221 of 24288 (1%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+CCU2C:          113
+DCUA:           1
+FD1P3BX:        20
+FD1P3DX:        92
+FD1S3BX:        12
+FD1S3DX:        97
+GSR:            1
+INV:            3
+ORCALUT4:       154
+PFUMX:          2
+PUR:            1
+VHI:            6
+VLO:            6
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 153MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Mon May 13 09:09:11 2019
+
+###########################################################]
+
+</pre></samp></body></html>

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_toc.htm b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_toc.htm
new file mode 100644 (file)
index 0000000..d978345
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_toc.htm
@@ -0,0 +1,60 @@
+ <html> 
+  <head>
+    <script type="text/javascript" src="file:///home/soft/lattice/diamond/3.10_x64/synpbase/lib/report/reportlog_tree.js"></script>
+    <link rel="stylesheet" type="text/css" href="file:///home/soft/lattice/diamond/3.10_x64/synpbase/lib/report/reportlog_tree.css" />  
+  </head> 
+
+  <body style="background-color:#e0e0ff;">
+   <script type="text/javascript"> reportLogObj.loadImage("closed.png", "open.png")</script>
+    <ul id="syn_results-menu" class="treeview" style="padding-left:12;">
+        <li style="font-size:12; font-style:normal"> <b style="background-color:#a2bff0; font-weight:bold">sgmii_ecp5 (syn_results)</b> 
+         <ul rel="open" style="font-size:small;">
+
+<li style="font-size:12; font-style:normal"><b style="background-color:#a2bff0; font-weight:bold">Synthesis -  </b> 
+<ul rel="open">
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#compilerReport1" target="srrFrame" title="">Compiler Report</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#compilerReport4" target="srrFrame" title="">Compiler Constraint Applicator</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#mapperReport6" target="srrFrame" title="">Pre-mapping Report</a>  
+<ul rel="open" >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#mapperReport7" target="srrFrame" title="">Clock Summary</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#mapperReport8" target="srrFrame" title="">Mapper Report</a>  
+<ul rel="open" >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#clockReport9" target="srrFrame" title="">Clock Conversion</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#timingReport10" target="srrFrame" title="">Timing Report</a>  
+<ul rel="open" >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#performanceSummary11" target="srrFrame" title="">Performance Summary</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#clockRelationships12" target="srrFrame" title="">Clock Relationships</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#interfaceInfo13" target="srrFrame" title="">Interface Information</a>  </li>
+<li><a href="file://#" target="srrFrame" title="">Detailed Report for Clocks</a>  
+<ul  >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#clockReport14" target="srrFrame" title="">Clock: sgmii_ecp5|pll_refclki</a>  
+<ul  >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#startingSlack15" target="srrFrame" title="">Starting Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#endingSlack16" target="srrFrame" title="">Ending Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#worstPaths17" target="srrFrame" title="">Worst Path Information</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#clockReport18" target="srrFrame" title="">Clock: sgmii_ecp5|rxrefclk</a>  
+<ul  >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#startingSlack19" target="srrFrame" title="">Starting Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#endingSlack20" target="srrFrame" title="">Ending Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#worstPaths21" target="srrFrame" title="">Worst Path Information</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#clockReport22" target="srrFrame" title="">Clock: sgmii_ecp5|tx_pclk_inferred_clock</a>  
+<ul  >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#startingSlack23" target="srrFrame" title="">Starting Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#endingSlack24" target="srrFrame" title="">Ending Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#worstPaths25" target="srrFrame" title="">Worst Path Information</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#clockReport26" target="srrFrame" title="">Clock: System</a>  
+<ul  >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#startingSlack27" target="srrFrame" title="">Starting Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#endingSlack28" target="srrFrame" title="">Ending Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#worstPaths29" target="srrFrame" title="">Worst Path Information</a>  </li></ul></li></ul></li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#resourceUsage30" target="srrFrame" title="">Resource Utilization</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/sgmii_ecp5_cck.rpt" target="srrFrame" title="">Constraint Checker Report (09:09 13-May)</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/stdout.log" target="srrFrame" title="">Session Log (09:09 13-May)</a>  
+<ul  ></ul></li>         </ul>
+        </li>
+   </ul>
+
+   <script type="text/javascript"> reportLogObj.generateLog("syn_results-menu")</script>
+
+  </body>
+ </html>
\ No newline at end of file

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/statusReport.html b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/statusReport.html
new file mode 100644 (file)
index 0000000..4f4bf5c
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/syntmp/statusReport.html
@@ -0,0 +1,115 @@
+<html> 
+                       <head>                  <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1" />
+                       <title>Project Status Summary Page</title>
+                       <link rel="stylesheet" type="text/css" href="projectstatuspage.css" />
+                       <script type = "text/javascript" src="projectstatuspage.js"></script>
+                       </head>
+
+                       <body style="background-color:#f0f0ff;">
+                       
+<table style="border:none;" width="100%" ><tr> <td class="outline">
+<table width="100%" border="0" cellspacing="0" cellpadding="0">             <thead class="tablehead"><tr><th colspan="4">Project Settings</th><tr> 
+ <tr> <td class="optionTitle" align="left"> Project Name</td> <td> sgmii_ecp5</td> <td class="optionTitle" align="left"> Device Name</td> <td> syn_results: Lattice ECP5UM : LFE5UM_25F</td> </tr>
+<tr> <td class="optionTitle" align="left"> Implementation Name</td> <td> syn_results</td> <td class="optionTitle" align="left"> Top Module</td> <td> sgmii_ecp5</td> </tr>
+                </thead> 
+                <tbody> <tr> <td class="optionTitle" align="left"> Pipelining</td> <td> 0</td> <td class="optionTitle" align="left"> Retiming</td> <td> 0</td> </tr>
+<tr> <td class="optionTitle" align="left"> Resource Sharing</td> <td> 1</td> <td class="optionTitle" align="left"> Fanout Guide</td> <td> 50</td> </tr>
+<tr> <td class="optionTitle" align="left"> Disable I/O Insertion</td> <td> 1</td> <td class="optionTitle" align="left"> Disable Sequential Optimizations</td> <td> 0</td> </tr>
+<tr> <td class="optionTitle" align="left"> Clock Conversion</td> <td> 1</td> <td class="optionTitle" align="left"> FSM Compiler</td> <td> 1</td> </tr>
+ 
+</tbody> 
+  </table><br>  <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
+                                  <thead class="tablehead"><tr><th   colspan="9">Run Status</th></tr></thead>
+         <tbody>
+               <tr>
+                       <th align="left" width="17%">Job Name</th>
+                       <th align="left">Status</th>
+                       <td class="lnote" align="center" title="Notes"></td>
+                       <td class="lwarn" align="center" title="Warnings"></td>
+                       <td class="lerror" align="center" title="Errors"></td>
+                       <th align="left">CPU Time</th>
+                       <th align="left">Real Time</th>
+                       <th align="left">Memory</th>
+                       <th align="left">Date/Time</th>
+         </tr>
+  <tr>
+  <td class="optionTitle"> (compiler)</td><td>Complete</td>
+ <td>15</td>
+ <td>76</td>
+<td>0</td>
+<td>-</td>
+<td>00m:02s</td>
+<td>-</td>
+<td><font size="-1">5/13/19</font><br/><font size="-2">9:09 AM</font></td>
+</tr> 
+
+ <tr>
+  <td class="optionTitle"> (premap)</td><td>Complete</td>
+ <td>9</td>
+ <td>3</td>
+<td>0</td>
+<td>0m:00s</td>
+<td>0m:00s</td>
+<td>144MB</td>
+<td><font size="-1">5/13/19</font><br/><font size="-2">9:09 AM</font></td>
+</tr> 
+
+ <tr>
+  <td class="optionTitle"> (fpga_mapper)</td><td>Complete</td>
+ <td>22</td>
+ <td>4</td>
+<td>0</td>
+<td>0m:03s</td>
+<td>0m:03s</td>
+<td>153MB</td>
+<td><font size="-1">5/13/19</font><br/><font size="-2">9:09 AM</font></td>
+</tr> 
+
+<tr>
+  <td class="optionTitle">Multi-srs Generator</td>
+  <td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td></td><td class="empty"></td><td class="empty"></td><td><font size="-1">5/13/19</font><br/><font size="-2">9:09 AM</font></td>              </tbody>
+     </table>
+ <br> 
+ <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
+                                  <thead class="tablehead"><tr><th   colspan="4">Area Summary</th></tr></thead>
+<tfoot> <tr> <td class="optionTitle" colspan="4"></td></tr> 
+ </tfoot> 
+ <tbody> <tr> 
+<td title ="Total Register bits used" class="optionTitle" align="left">Register bits</td> <td>221</td>
+<td title ="Total I/O cells used" class="optionTitle" align="left">I/O cells</td> <td>0</td>
+</tr>
+<tr> 
+<td title ="Total Block RAMs used" class="optionTitle" align="left">Block RAMs
+(v_ram)</td> <td>0</td>
+<td title ="Total DSPs used" class="optionTitle" align="left">DSPs
+(dsp_used)</td> <td>0</td>
+</tr>
+<tr> 
+<td title ="Total ORCA LUTs used" class="optionTitle" align="left">ORCA LUTs
+(total_luts)</td> <td>154</td>
+<td class="optionTitle"></td><td></td></tr> 
+</tbody>
+    </table><br>
+ <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
+                                  <thead class="tablehead"><tr><th   colspan="4">Timing Summary</th></tr></thead>
+<tfoot> <tr> <td class="optionTitle" colspan="2"></td></tr> 
+ </tfoot> 
+<tbody> 
+   <tr><th class="optionTitle" align= "left ">Clock Name</th><th class="optionTitle" align= "left ">Req Freq</th><th class="optionTitle" align= "left ">Est Freq</th><th class="optionTitle" align= "left ">Slack</th></tr> 
+<tr> <td  align="left">sgmii_ecp5|pll_refclki</td><td  align="left">100.0 MHz</td><td  align="left">168.9 MHz</td><td  align="left">4.079</td></tr> 
+<tr> <td  align="left">sgmii_ecp5|rxrefclk</td><td  align="left">100.0 MHz</td><td  align="left">167.9 MHz</td><td  align="left">4.043</td></tr> 
+<tr> <td  align="left">sgmii_ecp5|tx_pclk_inferred_clock</td><td  align="left">100.0 MHz</td><td  align="left">237.5 MHz</td><td  align="left">5.789</td></tr> 
+<tr> <td  align="left">System</td><td  align="left">100.0 MHz</td><td  align="left">840.7 MHz</td><td  align="left">8.810</td></tr> 
+</tbody> 
+ </table>
+<br>
+ <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
+                                  <thead class="tablehead"><tr><th   colspan="4">Optimizations Summary</th></tr></thead>
+ <tbody> <tr> 
+<td title ="Non-gated/non-generated clock trees / Gated/generated clock trees" class="optionTitle" align="left">Combined Clock Conversion</td> <td>3 / 0</td>
+<td class="optionTitle"></td><td></td></tr> 
+</tbody>
+    </table><br>
+<br> 
+</td></tr></table></body> 
+ </html>
\ No newline at end of file

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/.cckTransfer b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/.cckTransfer
new file mode 100644 (file)
index 0000000..c8ef476
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/.cckTransfer differ

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/_mh_info b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/_mh_info
new file mode 100644 (file)
index 0000000..f62cf42
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/_mh_info
@@ -0,0 +1,2 @@
+|/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer1.info|
+|2|

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/_verilog_hintfile b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/_verilog_hintfile
new file mode 100644 (file)
index 0000000..23e996c
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/_verilog_hintfile
@@ -0,0 +1,69 @@
+%%% protect protected_file
+#OPTIONS:"|-bldtbl|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
+#CUR:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":1557731342
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599
+@E8lFkRDC#HolHO_CbD6
+HNLssI$RF
+s      Fbk0kE0R80Fkb
+R4Fbk0kE0R80FkM
+R4HkMb08REHRMb4M
+HbRk0EM8HM
+R4HkMb0GRssOCVD4       R
+0FkbRk00bG_ORD 4M
+HbRk00_GHORD   4M
+HbRk00NG80UNR
+bHMk00RGR_     4M
+HbRk0G0lHRH4
+M0bkR_0G8bH#_sOFs0CORF4
+kk0b0GRs8NN0RFU
+kk0b0GRs_4     R
+0FkbRk0s8G_H_#bCRss4k
+F00bkR_sGOCP_s4sR
+bHMk#0RHNoMDC_800CO_4OR
+0FkbRk0sDG_FD#_F#I_RF4
+kk0b0#RDl0_#N#0k_4#R
+0FkbRk0O_0OkMsk_4#R
+0FkbRk0O_0OFMsk_4#R
+0FkbRk0sOG_8Ds_F#D_RF4
+kk0b00ROOM_H#R_#4k
+F00bkROO0_D8C_4#R
+bHMk#0RDsH_#40R
+bHMk00RGI_bs_kbO
+R4HkMb0GRs_sbIkOb_RH4
+M0bkRH#O_8IsNR0NUM
+HbRk0#_OHNs88RFn
+kk0b0OR#H8_s8NN0RHU
+M0bkRH#O__CM8DkNRH4
+M0bkRH#O_D#C_N8kD
+R4HkMb0OR#HM_CRH4
+M0bkRH#O_D#CRH4
+M0bkRH#O_Rs84M
+HbRk0#_OHIRsM4k
+F00bkRH#O_0HMRH4
+M0bkRNO$IM#0RH4
+M0bkRs#C8_C#bR8L4M
+HbRk0b_DDsOCVDR        H4M
+HbRk0s_#D8NH#LRDC4M
+HbRk0s_#DsR#04M
+HbRk0#8CsCs#_#80_k_NDO
+R4HkMb0#Rs0k_8NOD_RH4
+M0bkR_0G#8CsCs#_#O0_RH4
+M0bkR_0Gb_O#s_#0O
+R4Fbk0kb0RDDD_F4DR
+0FkbRk0s_#D0sG_84$R
+bHMks0RGC_#s#8C_0s#_4OR
+bHMks0RGO_b##_s0R_O4k
+F00bkRDs#__sGsR8$4M
+C88lFk
+DC
+
+@ 

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer0.fdep b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer0.fdep
new file mode 100644 (file)
index 0000000..d9fad1a
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer0.fdep
@@ -0,0 +1,33 @@
+#defaultlanguage:vhdl
+#OPTIONS:"|-mixedhdl|-top|sgmii_ecp5|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610
+#CUR:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":1557731342
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599
+0 "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd" vhdl
+
+# Dependency Lists (Uses list)
+0 -1
+
+# Dependency Lists (Users Of)
+0 -1
+
+# Design Unit to File Association
+arch work sgmii_ecp5 v1 0
+module work sgmii_ecp5 0
+
+# Unbound Instances to File Association
+inst work sgmii_ecp5 sgmii_ecp5sll_core 0
+inst work sgmii_ecp5 sgmii_ecp5rsl_core 0
+inst work sgmii_ecp5 dcua 0
+
+
+# Configuration files used

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer0.fdeporig b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer0.fdeporig
new file mode 100644 (file)
index 0000000..d7cdb87
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer0.fdeporig
@@ -0,0 +1,29 @@
+#defaultlanguage:vhdl
+#OPTIONS:"|-mixedhdl|-top|sgmii_ecp5|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610
+#CUR:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":1557731342
+0 "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd" vhdl
+
+# Dependency Lists (Uses list)
+0 -1
+
+# Dependency Lists (Users Of)
+0 -1
+
+# Design Unit to File Association
+arch work sgmii_ecp5 v1 0
+module work sgmii_ecp5 0
+
+# Unbound Instances to File Association
+inst work sgmii_ecp5 sgmii_ecp5sll_core 0
+inst work sgmii_ecp5 sgmii_ecp5rsl_core 0
+inst work sgmii_ecp5 dcua 0

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer0.srs b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer0.srs
new file mode 100644 (file)
index 0000000..ac50db1
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer0.srs differ

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer0.tlg b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer0.tlg
new file mode 100644 (file)
index 0000000..c29e6b8
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer0.tlg
@@ -0,0 +1,2 @@
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1.
+Post processing for work.sgmii_ecp5.v1

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer0.tlg.db b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer0.tlg.db
new file mode 100644 (file)
index 0000000..e466bdc
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer0.tlg.db differ

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer1.fdep b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer1.fdep
new file mode 100644 (file)
index 0000000..fbef846
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer1.fdep
@@ -0,0 +1,22 @@
+#OPTIONS:"|-mixedhdl|-modhint|/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/_verilog_hintfile|-top|work.sgmii_ecp5sll_core|-top|work.sgmii_ecp5rsl_core|-mpparams|/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/_mh_params|-layerid|1|-orig_srs|/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/|-I|/home/soft/lattice/diamond/3.10_x64/synpbase/lib|-v2001|-devicelib|/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v|-devicelib|/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_ver":1542167761
+#CUR:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/_verilog_hintfile":1557731344
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v":1542167595
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v":1542167597
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v":1542167630
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v":1542167630
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v":1542167630
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh":1542167630
+#CUR:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1557731342
+#numinternalfiles:6
+#defaultlanguage:verilog
+0                      "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v" verilog
+#Dependency Lists(Uses List)
+0 -1
+#Dependency Lists(Users Of)
+0 -1
+#Design Unit to File Association
+module work sgmii_ecp5rsl_core 0
+module work sync 0
+module work sgmii_ecp5sll_core 0
+#Unbound instances to file Association.

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer1.fdepxmr b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer1.fdepxmr
new file mode 100644 (file)
index 0000000..37d628b
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer1.fdepxmr
@@ -0,0 +1 @@
+#XMR Information

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer1.info b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer1.info
new file mode 100644 (file)
index 0000000..ddcec68
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer1.info
@@ -0,0 +1,2 @@
+|work.sgmii_ecp5rsl_core|parameter pnum_channels 1;,parameter pprotocol "GBE";,parameter pserdes_mode "RX AND TX";,parameter pport_tx_rdy "ENABLED";,parameter pwait_tx_rdy 3000;,parameter pport_rx_rdy "ENABLED";,parameter pwait_rx_rdy 3000;|
+|work.sgmii_ecp5sll_core|parameter PPROTOCOL "GBE";,parameter PLOL_SETTING 0;,parameter PDYN_RATE_CTRL "DISABLED";,parameter PPCIE_MAX_RATE "2.5";,parameter PDIFF_VAL_LOCK 39;,parameter PDIFF_VAL_UNLOCK 78;,parameter PPCLK_TC 131072;,parameter PDIFF_DIV11_VAL_LOCK 0;,parameter PDIFF_DIV11_VAL_UNLOCK 0;,parameter PPCLK_DIV11_TC 0;|

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer1.srs b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer1.srs
new file mode 100644 (file)
index 0000000..c419557
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer1.srs differ

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer1.tlg b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer1.tlg
new file mode 100644 (file)
index 0000000..f6f3666
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer1.tlg
@@ -0,0 +1,252 @@
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work.
+
+       PDATA_RST_VAL=32'b00000000000000000000000000000000
+   Generated name = sync_0s
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work.
+
+       PPROTOCOL=24'b010001110100001001000101
+       PLOL_SETTING=32'b00000000000000000000000000000000
+       PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100
+       PPCIE_MAX_RATE=24'b001100100010111000110101
+       PDIFF_VAL_LOCK=32'b00000000000000000000000000100111
+       PDIFF_VAL_UNLOCK=32'b00000000000000000000000001001110
+       PPCLK_TC=32'b00000000000000100000000000000000
+       PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000
+       PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000
+       PPCLK_DIV11_TC=32'b00000000000000000000000000000000
+       LPLL_LOSS_ST=2'b00
+       LPLL_PRELOSS_ST=2'b01
+       LPLL_PRELOCK_ST=2'b10
+       LPLL_LOCK_ST=2'b11
+       LRCLK_TC=16'b1111111111111111
+       LRCLK_TC_PUL_WIDTH=16'b0000000000110010
+       LHB_WAIT_CNT=8'b11111111
+       LPCLK_TC_0=32'b00000000000000001000000000000000
+       LPCLK_TC_1=32'b00000000000000010000000000000000
+       LPCLK_TC_2=32'b00000000000000100000000000000000
+       LPCLK_TC_3=32'b00000000000000101000000000000000
+       LPCLK_TC_4=32'b00000000000000010000000000000000
+       LPDIFF_LOCK_00=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_10=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_20=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_30=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_40=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_01=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_11=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_21=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_31=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_41=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_02=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_12=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_22=32'b00000000000000000000000011000100
+       LPDIFF_LOCK_32=32'b00000000000000000000000011110101
+       LPDIFF_LOCK_42=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_03=32'b00000000000000000000000010000011
+       LPDIFF_LOCK_13=32'b00000000000000000000000100000110
+       LPDIFF_LOCK_23=32'b00000000000000000000001000001100
+       LPDIFF_LOCK_33=32'b00000000000000000000001010001111
+       LPDIFF_LOCK_43=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011
+       LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110
+       LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010
+       LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001
+       LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111
+       LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000
+       LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000
+       LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000
+       LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100
+       LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001
+       LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010
+       LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111
+       LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001
+   Generated name = sgmii_ecp5sll_core_Z1_layer1
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment.
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work.
+
+       pnum_channels=32'b00000000000000000000000000000001
+       pprotocol=24'b010001110100001001000101
+       pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
+       pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_tx_rdy=32'b00000000000000000000101110111000
+       pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_rx_rdy=32'b00000000000000000000101110111000
+       wa_num_cycles=32'b00000000000000000000010000000000
+       dac_num_cycles=32'b00000000000000000000000000000011
+       lreset_pwidth=32'b00000000000000000000000000000011
+       lwait_b4_trst=32'b00000000000010111110101111000010
+       lwait_b4_trst_s=32'b00000000000000000000001100001101
+       lplol_cnt_width=32'b00000000000000000000000000010100
+       lwait_after_plol0=32'b00000000000000000000000000000100
+       lwait_b4_rrst=32'b00000000000000101100000000000000
+       lrrst_wait_width=32'b00000000000000000000000000010100
+       lwait_after_rrst=32'b00000000000011000011010100000000
+       lwait_b4_rrst_s=32'b00000000000000000000000111001100
+       lrlol_cnt_width=32'b00000000000000000000000000010011
+       lwait_after_lols=32'b00000000000000001100010000000000
+       lwait_after_lols_s=32'b00000000000000000000000010010110
+       llols_cnt_width=32'b00000000000000000000000000010010
+       lrdb_max=32'b00000000000000000000000000001111
+       ltxr_wait_width=32'b00000000000000000000000000001100
+       lrxr_wait_width=32'b00000000000000000000000000001100
+   Generated name = sgmii_ecp5rsl_core_Z2_layer1
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers.
+@N: CL201 :"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state.
+Extracted state machine for register sll_state
+State machine has 4 reachable states with original encodings of:
+   00
+   01
+   10
+   11

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer1.tlg.db b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/layer1.tlg.db
new file mode 100644 (file)
index 0000000..35d1d75
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diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/modulechange.db b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/modulechange.db
new file mode 100644 (file)
index 0000000..643f565
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diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/modulechange_mixhdl/layer0/modulechange.db b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/modulechange_mixhdl/layer0/modulechange.db
new file mode 100644 (file)
index 0000000..9273fb0
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diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/modulechange_mixhdl/layer1/modulechange.db b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/modulechange_mixhdl/layer1/modulechange.db
new file mode 100644 (file)
index 0000000..aa64eba
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/modulechange_mixhdl/layer1/modulechange.db differ

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.fdep b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.fdep
new file mode 100644 (file)
index 0000000..d5d82d6
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.fdep
@@ -0,0 +1,37 @@
+#OPTIONS:"|-mixedhdl|-top|sgmii_ecp5|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610
+#CUR:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd":1557731342
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599
+#OPTIONS:"|-mixedhdl|-modhint|/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/_verilog_hintfile|-top|work.sgmii_ecp5sll_core|-top|work.sgmii_ecp5rsl_core|-mpparams|/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/_mh_params|-layerid|1|-orig_srs|/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/|-I|/home/soft/lattice/diamond/3.10_x64/synpbase/lib|-v2001|-devicelib|/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v|-devicelib|/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_ver":1542167761
+#CUR:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/_verilog_hintfile":1557731344
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v":1542167595
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v":1542167597
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v":1542167630
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v":1542167630
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v":1542167630
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh":1542167630
+#CUR:"/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v":1557731342
+0                      "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd" vhdl
+1                      "/home/adrian/git/trb5sc/template/project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5_softlogic.v" verilog
+#Dependency Lists(Uses List)
+0 1
+1 -1
+#Dependency Lists(Users Of)
+0 -1
+1 0
+#Design Unit to File Association
+module work sgmii_ecp5sll_core 1
+module work sync 1
+module work sgmii_ecp5rsl_core 1
+module work sgmii_ecp5 0
+arch work sgmii_ecp5 v1 0

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.linkerlog b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.linkerlog
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs
new file mode 100644 (file)
index 0000000..1ea88e6
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diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm
new file mode 100644 (file)
index 0000000..c431948
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diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m_srm/1.srm b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m_srm/1.srm
new file mode 100644 (file)
index 0000000..ae1d255
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diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m_srm/fileinfo.srm b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m_srm/fileinfo.srm
new file mode 100644 (file)
index 0000000..0c85cba
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diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult.srs b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult.srs
new file mode 100644 (file)
index 0000000..f5b5ff0
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diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult_srs/1.srs b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult_srs/1.srs
new file mode 100644 (file)
index 0000000..e8ec546
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult_srs/1.srs differ

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult_srs/fileinfo.srs b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult_srs/fileinfo.srs
new file mode 100644 (file)
index 0000000..e700287
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult_srs/fileinfo.srs differ

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult_srs/skeleton.srs b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult_srs/skeleton.srs
new file mode 100644 (file)
index 0000000..2603804
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult_srs/skeleton.srs differ

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_prem.fse b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_prem.fse
new file mode 100644 (file)
index 0000000..cc147f0
--- /dev/null
+++ b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_prem.fse
@@ -0,0 +1,12 @@
+
+fsm_encoding {61801018011} sequential
+
+fsm_state_encoding {61801018011} LPLL_LOSS_ST {00}
+
+fsm_state_encoding {61801018011} LPLL_PRELOSS_ST {01}
+
+fsm_state_encoding {61801018011} LPLL_PRELOCK_ST {10}
+
+fsm_state_encoding {61801018011} LPLL_LOCK_ST {11}
+
+fsm_registers {61801018011} {sll_state[1]}  {sll_state[0]} 

diff --git a/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_prem.srd b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_prem.srd
new file mode 100644 (file)
index 0000000..bde5be5
Binary files /dev/null and b/gbe/cores/GbePcsExtrefclk/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_prem.srd differ

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.cmd b/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.cmd
new file mode 100644 (file)
index 0000000..441173e
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.cmd
@@ -0,0 +1,18 @@
+PROJECT: pll_200_125_100
+               working_path: "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results"
+               module: pll_200_125_100
+               verilog_file_list: "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd"
+               vlog_std_v2001: true
+               constraint_file_name: "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc"
+               suffix_name: edn
+               output_file_name: pll_200_125_100
+               write_prf: true
+               disable_io_insertion: true
+               force_gsr: false
+               frequency: 100
+               fanout_limit: 50
+               retiming: false
+               pipe: false
+               part: LFE5UM-85F
+               speed_grade: 8
+               

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.cst b/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.cst
new file mode 100644 (file)
index 0000000..36253a2
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.cst
@@ -0,0 +1,3 @@
+Date=05/10/2019
+Time=14:33:07
+

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc b/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc
new file mode 100644 (file)
index 0000000..6fbcac9
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc
@@ -0,0 +1,2 @@
+###==== Start Configuration
+

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.lpc b/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.lpc
new file mode 100644 (file)
index 0000000..bedc69e
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.lpc
@@ -0,0 +1,93 @@
+[Device]
+Family=ecp5um
+PartType=LFE5UM-85F
+PartName=LFE5UM-85F-8BG756C
+SpeedGrade=8
+Package=CABGA756
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.8
+ModuleName=pll_200_125_100
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=05/10/2019
+Time=14:33:07
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+CLKI_FREQ=200
+CLKI_DIV=2
+ENABLE_HBW=DISABLED
+REFERENCE=0
+IOBUF=LVDS
+CLKOP_FREQ=200
+CLKOP_TOL=0.0
+CLKOP_DIV=1
+CLKOP_ACTUAL_FREQ=200.000000
+CLKOP_MUXA=ENABLED
+CLKOS_Enable=ENABLED
+CLKOS_FREQ=100.00
+CLKOS_TOL=0.0
+CLKOS_DIV=5
+CLKOS_ACTUAL_FREQ=100.000000
+CLKOS_MUXB=DISABLED
+CLKOS2_Enable=ENABLED
+CLKOS2_FREQ=125.00
+CLKOS2_TOL=0.0
+CLKOS2_DIV=4
+CLKOS2_ACTUAL_FREQ=125.000000
+CLKOS2_MUXC=DISABLED
+CLKOS3_Enable=DISABLED
+CLKOS3_FREQ=125.00
+CLKOS3_TOL=0.0
+CLKOS3_DIV=1
+CLKOS3_ACTUAL_FREQ=0.000000
+CLKOS3_MUXD=DISABLED
+FEEDBK_PATH=INT_OS
+CLKFB_DIV=1
+FRACN_ENABLE=DISABLED
+FRACN_DIV=
+VCO_RATE=500.000
+PLL_BW=10.695
+CLKOP_DPHASE=0
+CLKOP_APHASE=0.00
+CLKOP_TRIM_POL=Rising
+CLKOP_TRIM_DELAY=0
+CLKOS_DPHASE=0
+CLKOS_APHASE=0.00
+CLKOS_TRIM_POL=Rising
+CLKOS_TRIM_DELAY=0
+CLKOS2_DPHASE=0
+CLKOS2_APHASE=0.00
+CLKOS2_TRIM_POL=Rising
+CLKOS2_TRIM_DELAY=0
+CLKOS3_DPHASE=0
+CLKOS3_APHASE=0.00
+CLKOS3_TRIM_POL=Rising
+CLKOS3_TRIM_DELAY=0
+CLKSEL_ENA=DISABLED
+DPHASE_SOURCE=STATIC
+ENABLE_CLKOP=DISABLED
+ENABLE_CLKOS=DISABLED
+ENABLE_CLKOS2=DISABLED
+ENABLE_CLKOS3=DISABLED
+STDBY_ENABLE=DISABLED
+PLLRST_ENA=DISABLED
+PLL_LOCK_MODE=ENABLED
+PLL_LOCK_STK=DISABLED
+PLL_USE_SMI=DISABLED
+
+[Command]
+cmd_line= -w -n pll_200_125_100 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -bypassp -fclkos 100.00 -fclkos_tol 0.0 -fclkos2 125.00 -fclkos2_tol 0.0 -phases2 0 -phase_cntl STATIC -lock -fb_mode 6

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.ngd b/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.ngd
new file mode 100644 (file)
index 0000000..5e49660
Binary files /dev/null and b/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.ngd differ

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.ngo b/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.ngo
new file mode 100644 (file)
index 0000000..8065b78
Binary files /dev/null and b/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.ngo differ

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd b/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd
new file mode 100644 (file)
index 0000000..0b816a7
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd
@@ -0,0 +1,82 @@
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.3.144
+-- Module  Version: 5.7
+--/home/soft/lattice/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n pll_200_125_100 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -bypassp -fclkos 100.00 -fclkos_tol 0.0 -fclkos2 125.00 -fclkos2_tol 0.0 -phases2 0 -phase_cntl STATIC -lock -fb_mode 6 -fdc /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc 
+
+-- Fri May 10 14:33:09 2019
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity pll_200_125_100 is
+    port (
+        CLKI: in  std_logic; 
+        CLKOP: out  std_logic; 
+        CLKOS: out  std_logic; 
+        CLKOS2: out  std_logic; 
+        LOCK: out  std_logic);
+end pll_200_125_100;
+
+architecture Structure of pll_200_125_100 is
+
+    -- internal signal declarations
+    signal REFCLK: std_logic;
+    signal CLKOS2_t: std_logic;
+    signal CLKOS_t: std_logic;
+    signal CLKOP_t: std_logic;
+    signal CLKFB_t: std_logic;
+    signal scuba_vhi: std_logic;
+    signal scuba_vlo: std_logic;
+
+    attribute FREQUENCY_PIN_CLKOS2 : string; 
+    attribute FREQUENCY_PIN_CLKOS : string; 
+    attribute FREQUENCY_PIN_CLKOP : string; 
+    attribute FREQUENCY_PIN_CLKI : string; 
+    attribute ICP_CURRENT : string; 
+    attribute LPF_RESISTOR : string; 
+    attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "125.000000";
+    attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "100.000000";
+    attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "200.000000";
+    attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
+    attribute ICP_CURRENT of PLLInst_0 : label is "13";
+    attribute LPF_RESISTOR of PLLInst_0 : label is "24";
+    attribute syn_keep : boolean;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    PLLInst_0: EHXPLLL
+        generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", 
+        STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", 
+        CLKOS3_FPHASE=>  0, CLKOS3_CPHASE=>  0, CLKOS2_FPHASE=>  0, 
+        CLKOS2_CPHASE=>  3, CLKOS_FPHASE=>  0, CLKOS_CPHASE=>  4, 
+        CLKOP_FPHASE=>  0, CLKOP_CPHASE=>  0, PLL_LOCK_MODE=>  0, 
+        CLKOS_TRIM_DELAY=>  0, CLKOS_TRIM_POL=> "FALLING", 
+        CLKOP_TRIM_DELAY=>  0, CLKOP_TRIM_POL=> "FALLING", 
+        OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED", 
+        OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "ENABLED", 
+        OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "ENABLED", 
+        OUTDIVIDER_MUXA=> "REFCLK", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=>  1, 
+        CLKOS2_DIV=>  4, CLKOS_DIV=>  5, CLKOP_DIV=>  1, CLKFB_DIV=>  1, 
+        CLKI_DIV=>  2, FEEDBK_PATH=> "INT_OS")
+        port map (CLKI=>CLKI, CLKFB=>CLKFB_t, PHASESEL1=>scuba_vlo, 
+            PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, 
+            PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo, 
+            STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, 
+            ENCLKOP=>scuba_vlo, ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, 
+            ENCLKOS3=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t, 
+            CLKOS2=>CLKOS2_t, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open, 
+            REFCLK=>REFCLK, CLKINTFB=>CLKFB_t);
+
+    CLKOS2 <= CLKOS2_t;
+    CLKOS <= CLKOS_t;
+    CLKOP <= CLKOP_t;
+end Structure;

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100_ngd.asd b/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100_ngd.asd
new file mode 100644 (file)
index 0000000..c265c78
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100_ngd.asd
@@ -0,0 +1 @@
+[ActiveSupport NGD]

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_240_100.lpc b/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_240_100.lpc
new file mode 100644 (file)
index 0000000..ffe81c0
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/pll_240_100.lpc
@@ -0,0 +1,93 @@
+[Device]
+Family=ecp5um
+PartType=LFE5UM-85F
+PartName=LFE5UM-85F-8BG381C
+SpeedGrade=8
+Package=CABGA381
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.8
+ModuleName=pll_240_100
+SourceFormat=vhdl
+ParameterFileVersion=1.0
+Date=07/11/2016
+Time=18:43:16
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+CLKI_FREQ=200
+CLKI_DIV=2
+ENABLE_HBW=DISABLED
+REFERENCE=0
+IOBUF=LVDS
+CLKOP_FREQ=200
+CLKOP_TOL=0.0
+CLKOP_DIV=1
+CLKOP_ACTUAL_FREQ=200.000000
+CLKOP_MUXA=ENABLED
+CLKOS_Enable=ENABLED
+CLKOS_FREQ=100.00
+CLKOS_TOL=0.0
+CLKOS_DIV=6
+CLKOS_ACTUAL_FREQ=100.000000
+CLKOS_MUXB=DISABLED
+CLKOS2_Enable=ENABLED
+CLKOS2_FREQ=200
+CLKOS2_TOL=0.0
+CLKOS2_DIV=3
+CLKOS2_ACTUAL_FREQ=200.000000
+CLKOS2_MUXC=DISABLED
+CLKOS3_Enable=ENABLED
+CLKOS3_FREQ=120.00
+CLKOS3_TOL=0.0
+CLKOS3_DIV=5
+CLKOS3_ACTUAL_FREQ=120.000000
+CLKOS3_MUXD=DISABLED
+FEEDBK_PATH=INT_OS
+CLKFB_DIV=1
+FRACN_ENABLE=DISABLED
+FRACN_DIV=
+VCO_RATE=600.000
+PLL_BW=8.185
+CLKOP_DPHASE=0
+CLKOP_APHASE=0.00
+CLKOP_TRIM_POL=Rising
+CLKOP_TRIM_DELAY=0
+CLKOS_DPHASE=0
+CLKOS_APHASE=0.00
+CLKOS_TRIM_POL=Rising
+CLKOS_TRIM_DELAY=0
+CLKOS2_DPHASE=0
+CLKOS2_APHASE=0.00
+CLKOS2_TRIM_POL=Rising
+CLKOS2_TRIM_DELAY=0
+CLKOS3_DPHASE=0
+CLKOS3_APHASE=0.00
+CLKOS3_TRIM_POL=Rising
+CLKOS3_TRIM_DELAY=0
+CLKSEL_ENA=DISABLED
+DPHASE_SOURCE=STATIC
+ENABLE_CLKOP=DISABLED
+ENABLE_CLKOS=DISABLED
+ENABLE_CLKOS2=DISABLED
+ENABLE_CLKOS3=DISABLED
+STDBY_ENABLE=DISABLED
+PLLRST_ENA=DISABLED
+PLL_LOCK_MODE=ENABLED
+PLL_LOCK_STK=DISABLED
+PLL_USE_SMI=DISABLED
+
+[Command]
+cmd_line= -w -n pll_240_100 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -bypassp -fclkos 100.00 -fclkos_tol 0.0 -fclkos2 200 -fclkos2_tol 0.0 -phases2 0 -fclkos3 120.00 -fclkos3_tol 0.0 -phases3 0 -phase_cntl STATIC -lock -fb_mode 6

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/.recordref b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/.recordref
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/_CMD_.CML b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/_CMD_.CML
new file mode 100644 (file)
index 0000000..98806d1
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/_CMD_.CML
@@ -0,0 +1 @@
+ -osyn  /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_comp.srs  -top  pll_200_125_100  -hdllog  /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_compiler.srr  -encrypt  -mp  4  -verification_mode 0  -vhdl  -prodtype  synplify_pro  -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver  -encrypt  -pro  -dmgen  /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/dm  -lite -ui -fid2 -ram -sharing on -ll 2000 -autosm  -ignore_undefined_lib  -lib work /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd  -jobname  "compiler" 
\ No newline at end of file

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/_cmd._cml b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/_cmd._cml
new file mode 100644 (file)
index 0000000..60abe88
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/_cmd._cml
@@ -0,0 +1 @@
+-link    -encrypt        -top pll_200_125_100 -osyn /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_comp.srs /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/layer0.srs   
\ No newline at end of file

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/dm/layer0.xdm b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/dm/layer0.xdm
new file mode 100644 (file)
index 0000000..8d0ce64
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/dm/layer0.xdm
@@ -0,0 +1,163 @@
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+@

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.areasrr b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.areasrr
new file mode 100644 (file)
index 0000000..9d560b3
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.areasrr
@@ -0,0 +1,15 @@
+----------------------------------------------------------------------
+Report for cell pll_200_125_100.structure
+
+Register bits: 0 of 24288 (0%)
+PIC Latch:       0
+I/O cells:       0
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                            EHXPLLL        1       100.0
+                                GSR        1       100.0
+                                PUR        1       100.0
+                                VHI        1       100.0
+                                VLO        1       100.0
+                            
+                         TOTAL             5           

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.fse b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.fse
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.htm b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.htm
new file mode 100644 (file)
index 0000000..a052015
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.htm
@@ -0,0 +1,9 @@
+<html>
+ <head>
+ <title>syntmp/pll_200_125_100_srr.htm log file</title>
+ </head>
+ <frameset cols="20%, 80%">
+ <frame src="syntmp/pll_200_125_100_toc.htm" name="tocFrame" />
+                                <frame src="syntmp/pll_200_125_100_srr.htm" name="srrFrame"/>
+</frameset>
+ </html>

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.prj b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.prj
new file mode 100644 (file)
index 0000000..63c7206
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.prj
@@ -0,0 +1,46 @@
+#-- Lattice Semiconductor Corporation Ltd.
+#-- Synplify OEM project file /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.prj
+#-- Written on Fri May 10 14:33:10 2019
+
+
+#device options
+set_option -technology ecp5um
+set_option -part LFE5UM-85F
+set_option -speed_grade 8
+
+#use verilog 2001 standard option
+set_option -vlog_std v2001
+
+#map options
+set_option -frequency 100
+set_option -fanout_limit 50
+set_option -disable_io_insertion true
+set_option -retiming false
+set_option -pipe false
+set_option -pipe false
+set_option -force_gsr false
+
+#simulation options
+set_option -write_verilog true
+set_option -write_vhdl true
+
+#timing analysis options
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#-- add_file options
+add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd"
+add_file -constraint {"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc"}
+
+#-- top module name
+set_option -top_module pll_200_125_100
+
+#-- set result format/file last
+project -result_file "pll_200_125_100.edn"
+
+#-- error message log file
+project -log_file pll_200_125_100.srf
+
+#-- run Synplify with 'arrange VHDL file'
+project -run

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srd b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srd
new file mode 100644 (file)
index 0000000..c0e0a02
Binary files /dev/null and b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srd differ

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srf b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srf
new file mode 100644 (file)
index 0000000..dac1f38
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srf
@@ -0,0 +1,403 @@
+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
+#install: /home/soft/lattice/diamond/3.10_x64/synpbase
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Fri May 10 14:33:10 2019
+
+#Implementation: syn_results
+
+Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":12:7:12:21|Top entity is set to pll_200_125_100.
+VHDL syntax check successful!
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":12:7:12:21|Synthesizing work.pll_200_125_100.structure.
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2083:10:2083:16|Synthesizing ecp5um.ehxplll.syn_black_box.
+Post processing for ecp5um.ehxplll.syn_black_box
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":832:10:832:12|Synthesizing ecp5um.vlo.syn_black_box.
+Post processing for ecp5um.vlo.syn_black_box
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":825:10:825:12|Synthesizing ecp5um.vhi.syn_black_box.
+Post processing for ecp5um.vhi.syn_black_box
+Post processing for work.pll_200_125_100.structure
+@W: CL168 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":50:4:50:17|Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 14:33:11 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 14:33:11 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 14:33:11 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 14:33:12 2019
+
+###########################################################]
+Pre-mapping Report
+
+# Fri May 10 14:33:12 2019
+
+Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc
+@L: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt 
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt" file 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB)
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist pll_200_125_100
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+
+Clock Summary
+******************
+
+          Start      Requested     Requested     Clock      Clock               Clock
+Level     Clock      Frequency     Period        Type       Group               Load 
+-------------------------------------------------------------------------------------
+0 -       System     100.0 MHz     10.000        system     system_clkgroup     0    
+=====================================================================================
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 143MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Fri May 10 14:33:13 2019
+
+###########################################################]
+Map & Optimize Report
+
+# Fri May 10 14:33:13 2019
+
+Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.edn
+M-2017.03L-SP1-1
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
+
+@W: MT246 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":56:4:56:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Fri May 10 14:33:15 2019
+#
+
+
+Top view:               pll_200_125_100
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 10.000
+
+@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
+                   Requested     Estimated     Requested     Estimated                Clock      Clock          
+Starting Clock     Frequency     Frequency     Period        Period        Slack      Type       Group          
+----------------------------------------------------------------------------------------------------------------
+System             100.0 MHz     NA            10.000        0.000         10.000     system     system_clkgroup
+================================================================================================================
+Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks            |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+---------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
+---------------------------------------------------------------------------------------------------------
+System    System  |  10.000      10.000  |  No paths    -      |  No paths    -      |  No paths    -    
+=========================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                           Arrival           
+Instance      Reference     Type        Pin          Net         Time        Slack 
+              Clock                                                                
+-----------------------------------------------------------------------------------
+PLLInst_0     System        EHXPLLL     CLKINTFB     CLKFB_t     0.000       10.000
+===================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+              Starting                                        Required           
+Instance      Reference     Type        Pin       Net         Time         Slack 
+              Clock                                                              
+---------------------------------------------------------------------------------
+PLLInst_0     System        EHXPLLL     CLKFB     CLKFB_t     10.000       10.000
+=================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.000
+    + Clock delay at ending point:           0.000 (ideal)
+    + Estimated clock delay at ending point: 0.000
+    = Required time:                         10.000
+
+    - Propagation time:                      0.000
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (critical) :                     10.000
+
+    Number of logic level(s):                0
+    Starting point:                          PLLInst_0 / CLKINTFB
+    Ending point:                            PLLInst_0 / CLKFB
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            System [rising]
+
+Instance / Net                 Pin          Pin               Arrival     No. of    
+Name               Type        Name         Dir     Delay     Time        Fan Out(s)
+------------------------------------------------------------------------------------
+PLLInst_0          EHXPLLL     CLKINTFB     Out     0.000     0.000       -         
+CLKFB_t            Net         -            -       -         -           1         
+PLLInst_0          EHXPLLL     CLKFB        In      0.000     0.000       -         
+====================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 0 of 24288 (0%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+EHXPLLL:        1
+GSR:            1
+PUR:            1
+VHI:            1
+VLO:            1
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 146MB)
+
+Process took 0h:00m:02s realtime, 0h:00m:02s cputime
+# Fri May 10 14:33:15 2019
+
+###########################################################]

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srm b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srm
new file mode 100644 (file)
index 0000000..cbb05bb
Binary files /dev/null and b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srm differ

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srr b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srr
new file mode 100644 (file)
index 0000000..dac1f38
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srr
@@ -0,0 +1,403 @@
+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
+#install: /home/soft/lattice/diamond/3.10_x64/synpbase
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Fri May 10 14:33:10 2019
+
+#Implementation: syn_results
+
+Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":12:7:12:21|Top entity is set to pll_200_125_100.
+VHDL syntax check successful!
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":12:7:12:21|Synthesizing work.pll_200_125_100.structure.
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2083:10:2083:16|Synthesizing ecp5um.ehxplll.syn_black_box.
+Post processing for ecp5um.ehxplll.syn_black_box
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":832:10:832:12|Synthesizing ecp5um.vlo.syn_black_box.
+Post processing for ecp5um.vlo.syn_black_box
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":825:10:825:12|Synthesizing ecp5um.vhi.syn_black_box.
+Post processing for ecp5um.vhi.syn_black_box
+Post processing for work.pll_200_125_100.structure
+@W: CL168 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":50:4:50:17|Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 14:33:11 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 14:33:11 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 14:33:11 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 14:33:12 2019
+
+###########################################################]
+Pre-mapping Report
+
+# Fri May 10 14:33:12 2019
+
+Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc
+@L: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt 
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt" file 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB)
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist pll_200_125_100
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+
+Clock Summary
+******************
+
+          Start      Requested     Requested     Clock      Clock               Clock
+Level     Clock      Frequency     Period        Type       Group               Load 
+-------------------------------------------------------------------------------------
+0 -       System     100.0 MHz     10.000        system     system_clkgroup     0    
+=====================================================================================
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 143MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Fri May 10 14:33:13 2019
+
+###########################################################]
+Map & Optimize Report
+
+# Fri May 10 14:33:13 2019
+
+Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.edn
+M-2017.03L-SP1-1
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
+
+@W: MT246 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":56:4:56:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Fri May 10 14:33:15 2019
+#
+
+
+Top view:               pll_200_125_100
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 10.000
+
+@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
+                   Requested     Estimated     Requested     Estimated                Clock      Clock          
+Starting Clock     Frequency     Frequency     Period        Period        Slack      Type       Group          
+----------------------------------------------------------------------------------------------------------------
+System             100.0 MHz     NA            10.000        0.000         10.000     system     system_clkgroup
+================================================================================================================
+Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks            |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+---------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
+---------------------------------------------------------------------------------------------------------
+System    System  |  10.000      10.000  |  No paths    -      |  No paths    -      |  No paths    -    
+=========================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                           Arrival           
+Instance      Reference     Type        Pin          Net         Time        Slack 
+              Clock                                                                
+-----------------------------------------------------------------------------------
+PLLInst_0     System        EHXPLLL     CLKINTFB     CLKFB_t     0.000       10.000
+===================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+              Starting                                        Required           
+Instance      Reference     Type        Pin       Net         Time         Slack 
+              Clock                                                              
+---------------------------------------------------------------------------------
+PLLInst_0     System        EHXPLLL     CLKFB     CLKFB_t     10.000       10.000
+=================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.000
+    + Clock delay at ending point:           0.000 (ideal)
+    + Estimated clock delay at ending point: 0.000
+    = Required time:                         10.000
+
+    - Propagation time:                      0.000
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (critical) :                     10.000
+
+    Number of logic level(s):                0
+    Starting point:                          PLLInst_0 / CLKINTFB
+    Ending point:                            PLLInst_0 / CLKFB
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            System [rising]
+
+Instance / Net                 Pin          Pin               Arrival     No. of    
+Name               Type        Name         Dir     Delay     Time        Fan Out(s)
+------------------------------------------------------------------------------------
+PLLInst_0          EHXPLLL     CLKINTFB     Out     0.000     0.000       -         
+CLKFB_t            Net         -            -       -         -           1         
+PLLInst_0          EHXPLLL     CLKFB        In      0.000     0.000       -         
+====================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 0 of 24288 (0%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+EHXPLLL:        1
+GSR:            1
+PUR:            1
+VHI:            1
+VLO:            1
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 146MB)
+
+Process took 0h:00m:02s realtime, 0h:00m:02s cputime
+# Fri May 10 14:33:15 2019
+
+###########################################################]

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srr.db b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srr.db
new file mode 100644 (file)
index 0000000..beb0f08
Binary files /dev/null and b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srr.db differ

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srs b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srs
new file mode 100644 (file)
index 0000000..a7fea3b
Binary files /dev/null and b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srs differ

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.vhm b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.vhm
new file mode 100644 (file)
index 0000000..6274441
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.vhm
@@ -0,0 +1,108 @@
+--
+-- Written by Synplicity
+-- Product Version "M-2017.03L-SP1-1"
+-- Program "Synplify Pro", Mapper "maplat, Build 1796R"
+-- Fri May 10 14:33:15 2019
+--
+
+--
+-- Written by Synplify Pro version Build 1796R
+-- Fri May 10 14:33:15 2019
+--
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library synplify;
+use synplify.components.all;
+library pmi;
+use pmi.pmi_components.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity pll_200_125_100 is
+port(
+  CLKI :  in std_logic;
+  CLKOP :  out std_logic;
+  CLKOS :  out std_logic;
+  CLKOS2 :  out std_logic;
+  LOCK :  out std_logic);
+end pll_200_125_100;
+
+architecture beh of pll_200_125_100 is
+  signal CLKOS3 : std_logic ;
+  signal INTLOCK : std_logic ;
+  signal CLKFB_T : std_logic ;
+  signal REFCLK : std_logic ;
+  signal GND : std_logic ;
+  signal VCC : std_logic ;
+begin
+GND_0: VLO port map (
+    Z => GND);
+VCC_0: VHI port map (
+    Z => VCC);
+PUR_INST: PUR port map (
+    PUR => VCC);
+GSR_INST: GSR port map (
+    GSR => VCC);
+PLLINST_0: EHXPLLL 
+  generic map( 
+    CLKI_DIV => 2, 
+    CLKFB_DIV => 1, 
+    CLKOP_DIV => 1, 
+    CLKOS_DIV => 5, 
+    CLKOS2_DIV => 4, 
+    CLKOS3_DIV => 1, 
+    CLKOP_ENABLE => "ENABLED", 
+    CLKOS_ENABLE => "ENABLED", 
+    CLKOS2_ENABLE => "ENABLED", 
+    CLKOS3_ENABLE => "DISABLED", 
+    CLKOP_CPHASE => 0, 
+    CLKOS_CPHASE => 4, 
+    CLKOS2_CPHASE => 3, 
+    CLKOS3_CPHASE => 0, 
+    CLKOP_FPHASE => 0, 
+    CLKOS_FPHASE => 0, 
+    CLKOS2_FPHASE => 0, 
+    CLKOS3_FPHASE => 0, 
+    FEEDBK_PATH => "INT_OS", 
+    CLKOP_TRIM_POL => "FALLING", 
+    CLKOP_TRIM_DELAY => 0, 
+    CLKOS_TRIM_POL => "FALLING", 
+    CLKOS_TRIM_DELAY => 0, 
+    OUTDIVIDER_MUXA => "REFCLK", 
+    OUTDIVIDER_MUXB => "DIVB", 
+    OUTDIVIDER_MUXC => "DIVC", 
+    OUTDIVIDER_MUXD => "DIVD", 
+    PLL_LOCK_MODE => 0, 
+    STDBY_ENABLE => "DISABLED", 
+    DPHASE_SOURCE => "DISABLED", 
+    PLLRST_ENA => "DISABLED", 
+    INTFB_WAKE => "DISABLED"
+  ) 
+  port map (
+    CLKI => CLKI,
+    CLKFB => CLKFB_T,
+    PHASESEL1 => GND,
+    PHASESEL0 => GND,
+    PHASEDIR => GND,
+    PHASESTEP => GND,
+    PHASELOADREG => GND,
+    STDBY => GND,
+    PLLWAKESYNC => GND,
+    RST => GND,
+    ENCLKOP => GND,
+    ENCLKOS => GND,
+    ENCLKOS2 => GND,
+    ENCLKOS3 => GND,
+    CLKOP => CLKOP,
+    CLKOS => CLKOS,
+    CLKOS2 => CLKOS2,
+    CLKOS3 => CLKOS3,
+    LOCK => LOCK,
+    INTLOCK => INTLOCK,
+    REFCLK => REFCLK,
+    CLKINTFB => CLKFB_T);
+end beh;
+

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.vm b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.vm
new file mode 100644 (file)
index 0000000..bae9f65
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.vm
@@ -0,0 +1,117 @@
+//
+// Written by Synplify Pro 
+// Product Version "M-2017.03L-SP1-1"
+// Program "Synplify Pro", Mapper "maplat, Build 1796R"
+// Fri May 10 14:33:14 2019
+//
+// Source file index table:
+// Object locations will have the form <file>:<line>
+// file 0 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd "
+// file 1 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd "
+// file 2 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd "
+// file 3 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd "
+// file 4 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd "
+// file 5 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd "
+// file 6 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd "
+// file 7 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd "
+// file 8 "\/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd "
+// file 9 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd "
+// file 10 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/nlconst.dat "
+// file 11 "\/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc "
+
+`timescale 100 ps/100 ps
+(* NGD_DRC_MASK=1 *)module pll_200_125_100 (
+  CLKI,
+  CLKOP,
+  CLKOS,
+  CLKOS2,
+  LOCK
+)
+;
+input CLKI ;
+output CLKOP ;
+output CLKOS ;
+output CLKOS2 ;
+output LOCK ;
+wire CLKI ;
+wire CLKOP ;
+wire CLKOS ;
+wire CLKOS2 ;
+wire LOCK ;
+wire CLKOS3 ;
+wire INTLOCK ;
+wire CLKFB_t ;
+wire REFCLK ;
+wire GND ;
+wire VCC ;
+  VLO GND_0 (
+       .Z(GND)
+);
+  VHI VCC_0 (
+       .Z(VCC)
+);
+  PUR PUR_INST (
+       .PUR(VCC)
+);
+  GSR GSR_INST (
+       .GSR(VCC)
+);
+// @8:56
+(* LPF_RESISTOR="24" , ICP_CURRENT="13" , FREQUENCY_PIN_CLKI="200.000000" , FREQUENCY_PIN_CLKOP="200.000000" , FREQUENCY_PIN_CLKOS="100.000000" , FREQUENCY_PIN_CLKOS2="125.000000" *)  EHXPLLL PLLInst_0 (
+       .CLKI(CLKI),
+       .CLKFB(CLKFB_t),
+       .PHASESEL1(GND),
+       .PHASESEL0(GND),
+       .PHASEDIR(GND),
+       .PHASESTEP(GND),
+       .PHASELOADREG(GND),
+       .STDBY(GND),
+       .PLLWAKESYNC(GND),
+       .RST(GND),
+       .ENCLKOP(GND),
+       .ENCLKOS(GND),
+       .ENCLKOS2(GND),
+       .ENCLKOS3(GND),
+       .CLKOP(CLKOP),
+       .CLKOS(CLKOS),
+       .CLKOS2(CLKOS2),
+       .CLKOS3(CLKOS3),
+       .LOCK(LOCK),
+       .INTLOCK(INTLOCK),
+       .REFCLK(REFCLK),
+       .CLKINTFB(CLKFB_t)
+);
+defparam PLLInst_0.CLKI_DIV = 2;
+defparam PLLInst_0.CLKFB_DIV = 1;
+defparam PLLInst_0.CLKOP_DIV = 1;
+defparam PLLInst_0.CLKOS_DIV = 5;
+defparam PLLInst_0.CLKOS2_DIV = 4;
+defparam PLLInst_0.CLKOS3_DIV = 1;
+defparam PLLInst_0.CLKOP_ENABLE = "ENABLED";
+defparam PLLInst_0.CLKOS_ENABLE = "ENABLED";
+defparam PLLInst_0.CLKOS2_ENABLE = "ENABLED";
+defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED";
+defparam PLLInst_0.CLKOP_CPHASE = 0;
+defparam PLLInst_0.CLKOS_CPHASE = 4;
+defparam PLLInst_0.CLKOS2_CPHASE = 3;
+defparam PLLInst_0.CLKOS3_CPHASE = 0;
+defparam PLLInst_0.CLKOP_FPHASE = 0;
+defparam PLLInst_0.CLKOS_FPHASE = 0;
+defparam PLLInst_0.CLKOS2_FPHASE = 0;
+defparam PLLInst_0.CLKOS3_FPHASE = 0;
+defparam PLLInst_0.FEEDBK_PATH = "INT_OS";
+defparam PLLInst_0.CLKOP_TRIM_POL = "FALLING";
+defparam PLLInst_0.CLKOP_TRIM_DELAY = 0;
+defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING";
+defparam PLLInst_0.CLKOS_TRIM_DELAY = 0;
+defparam PLLInst_0.OUTDIVIDER_MUXA = "REFCLK";
+defparam PLLInst_0.OUTDIVIDER_MUXB = "DIVB";
+defparam PLLInst_0.OUTDIVIDER_MUXC = "DIVC";
+defparam PLLInst_0.OUTDIVIDER_MUXD = "DIVD";
+defparam PLLInst_0.PLL_LOCK_MODE = 0;
+defparam PLLInst_0.STDBY_ENABLE = "DISABLED";
+defparam PLLInst_0.DPHASE_SOURCE = "DISABLED";
+defparam PLLInst_0.PLLRST_ENA = "DISABLED";
+defparam PLLInst_0.INTFB_WAKE = "DISABLED";
+endmodule /* pll_200_125_100 */
+

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_cck.rpt.db b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_cck.rpt.db
new file mode 100644 (file)
index 0000000..029fa7a
Binary files /dev/null and b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_cck.rpt.db differ

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt.db b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt.db
new file mode 100644 (file)
index 0000000..029fa7a
Binary files /dev/null and b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt.db differ

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_synplify.lpf b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_synplify.lpf
new file mode 100644 (file)
index 0000000..8e445e1
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_synplify.lpf
@@ -0,0 +1,20 @@
+#
+# Logical Preferences generated for Lattice by Synplify maplat, Build 1796R.
+#
+
+# Period Constraints 
+
+
+# Output Constraints 
+
+# Input Constraints 
+
+# Point-to-point Delay Constraints 
+
+
+
+# Block Path Constraints 
+
+BLOCK ASYNCPATHS;
+
+# End of generated Logical Preferences.

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_synplify_tmp2.lpf b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_synplify_tmp2.lpf
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_synplify_tmp4.lpf b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_synplify_tmp4.lpf
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_synplify_tmp8.lpf b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_synplify_tmp8.lpf
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/run_options.txt b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/run_options.txt
new file mode 100644 (file)
index 0000000..f45a913
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/run_options.txt
@@ -0,0 +1,75 @@
+#--  Synopsys, Inc.
+#--  Version M-2017.03L-SP1-1
+#--  Project file /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/run_options.txt
+#--  Written on Fri May 10 14:33:10 2019
+
+
+#project files
+add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd"
+add_file -fpga_constraint "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc"
+
+
+
+#implementation: "syn_results"
+impl -add syn_results -type fpga
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+
+#device options
+set_option -technology ecp5um
+set_option -part LFE5UM_25F
+set_option -package MG285C
+set_option -speed_grade -6
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -top_module "pll_200_125_100"
+
+# hdl_compiler_options
+set_option -distributed_compile 0
+
+# mapper_without_write_options
+set_option -frequency 100
+set_option -srs_instrumentation 1
+
+# mapper_options
+set_option -write_verilog 1
+set_option -write_vhdl 1
+
+# Lattice XP
+set_option -maxfan 50
+set_option -disable_io_insertion 1
+set_option -retiming 0
+set_option -pipe 0
+set_option -forcegsr false
+set_option -fix_gated_and_generated_clocks 1
+set_option -rw_check_on_ram 1
+set_option -update_models_cp 0
+set_option -syn_edif_array_rename 1
+set_option -Write_declared_clocks_only 1
+
+# NFilter
+set_option -no_sequential_opt 0
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "./pll_200_125_100.edn"
+
+#set log file 
+set_option log_file "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srf" 
+impl -active "syn_results"

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/scemi_cfg.txt b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/scemi_cfg.txt
new file mode 100644 (file)
index 0000000..868d437
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/scemi_cfg.txt
@@ -0,0 +1,3 @@
+## UMR3 MESSAGE PORT CONFIGURATION FILE
+## ************************************
+XTOR_DPI_MSG_PORT_UMR_ADDR_VERSION=0

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/scratchproject.prs b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/scratchproject.prs
new file mode 100644 (file)
index 0000000..6e19e6b
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/scratchproject.prs
@@ -0,0 +1,73 @@
+#--  Synopsys, Inc.
+#--  Version M-2017.03L-SP1-1
+#--  Project file /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/scratchproject.prs
+
+#project files
+add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd"
+add_file -fpga_constraint "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc"
+
+
+
+#implementation: "syn_results"
+impl -add /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results -type fpga
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+
+#device options
+set_option -technology ecp5um
+set_option -part LFE5UM_25F
+set_option -package MG285C
+set_option -speed_grade -6
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -top_module "pll_200_125_100"
+
+# hdl_compiler_options
+set_option -distributed_compile 0
+
+# mapper_without_write_options
+set_option -frequency 100
+set_option -srs_instrumentation 1
+
+# mapper_options
+set_option -write_verilog 1
+set_option -write_vhdl 1
+
+# Lattice XP
+set_option -maxfan 50
+set_option -disable_io_insertion 1
+set_option -retiming 0
+set_option -pipe 0
+set_option -forcegsr false
+set_option -fix_gated_and_generated_clocks 1
+set_option -rw_check_on_ram 1
+set_option -update_models_cp 0
+set_option -syn_edif_array_rename 1
+set_option -Write_declared_clocks_only 1
+
+# NFilter
+set_option -no_sequential_opt 0
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.edn"
+
+#set log file 
+set_option log_file "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srf" 
+impl -active "syn_results"

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/layer0.tlg.rptmap b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/layer0.tlg.rptmap
new file mode 100644 (file)
index 0000000..3910cac
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/layer0.tlg.rptmap
@@ -0,0 +1 @@
+./synwork/layer0.tlg,layer0.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages.

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_compiler.srr b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_compiler.srr
new file mode 100644 (file)
index 0000000..4501cf1
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_compiler.srr
@@ -0,0 +1,51 @@
+Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":12:7:12:21|Top entity is set to pll_200_125_100.
+VHDL syntax check successful!
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":12:7:12:21|Synthesizing work.pll_200_125_100.structure.
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2083:10:2083:16|Synthesizing ecp5um.ehxplll.syn_black_box.
+Post processing for ecp5um.ehxplll.syn_black_box
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":832:10:832:12|Synthesizing ecp5um.vlo.syn_black_box.
+Post processing for ecp5um.vlo.syn_black_box
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":825:10:825:12|Synthesizing ecp5um.vhi.syn_black_box.
+Post processing for ecp5um.vhi.syn_black_box
+Post processing for work.pll_200_125_100.structure
+@W: CL168 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":50:4:50:17|Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 14:33:11 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 14:33:11 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 14:33:11 2019
+
+###########################################################]

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_compiler.srr.db b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_compiler.srr.db
new file mode 100644 (file)
index 0000000..b43ab41
Binary files /dev/null and b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_compiler.srr.db differ

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_compiler.srr.rptmap b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_compiler.srr.rptmap
new file mode 100644 (file)
index 0000000..4edadfd
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_compiler.srr.rptmap
@@ -0,0 +1 @@
+./synlog/pll_200_125_100_compiler.srr,pll_200_125_100_compiler.srr,Compile Log

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_fpga_mapper.srr b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_fpga_mapper.srr
new file mode 100644 (file)
index 0000000..fbbc4b8
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_fpga_mapper.srr
@@ -0,0 +1,265 @@
+# Fri May 10 14:33:13 2019
+
+Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.edn
+M-2017.03L-SP1-1
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
+
+@W: MT246 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":56:4:56:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Fri May 10 14:33:15 2019
+#
+
+
+Top view:               pll_200_125_100
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 10.000
+
+@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
+                   Requested     Estimated     Requested     Estimated                Clock      Clock          
+Starting Clock     Frequency     Frequency     Period        Period        Slack      Type       Group          
+----------------------------------------------------------------------------------------------------------------
+System             100.0 MHz     NA            10.000        0.000         10.000     system     system_clkgroup
+================================================================================================================
+Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks            |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+---------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
+---------------------------------------------------------------------------------------------------------
+System    System  |  10.000      10.000  |  No paths    -      |  No paths    -      |  No paths    -    
+=========================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                           Arrival           
+Instance      Reference     Type        Pin          Net         Time        Slack 
+              Clock                                                                
+-----------------------------------------------------------------------------------
+PLLInst_0     System        EHXPLLL     CLKINTFB     CLKFB_t     0.000       10.000
+===================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+              Starting                                        Required           
+Instance      Reference     Type        Pin       Net         Time         Slack 
+              Clock                                                              
+---------------------------------------------------------------------------------
+PLLInst_0     System        EHXPLLL     CLKFB     CLKFB_t     10.000       10.000
+=================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.000
+    + Clock delay at ending point:           0.000 (ideal)
+    + Estimated clock delay at ending point: 0.000
+    = Required time:                         10.000
+
+    - Propagation time:                      0.000
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (critical) :                     10.000
+
+    Number of logic level(s):                0
+    Starting point:                          PLLInst_0 / CLKINTFB
+    Ending point:                            PLLInst_0 / CLKFB
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            System [rising]
+
+Instance / Net                 Pin          Pin               Arrival     No. of    
+Name               Type        Name         Dir     Delay     Time        Fan Out(s)
+------------------------------------------------------------------------------------
+PLLInst_0          EHXPLLL     CLKINTFB     Out     0.000     0.000       -         
+CLKFB_t            Net         -            -       -         -           1         
+PLLInst_0          EHXPLLL     CLKFB        In      0.000     0.000       -         
+====================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 0 of 24288 (0%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+EHXPLLL:        1
+GSR:            1
+PUR:            1
+VHI:            1
+VLO:            1
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 146MB)
+
+Process took 0h:00m:02s realtime, 0h:00m:02s cputime
+# Fri May 10 14:33:15 2019
+
+###########################################################]

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_fpga_mapper.srr.db b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_fpga_mapper.srr.db
new file mode 100644 (file)
index 0000000..b870b13
Binary files /dev/null and b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_fpga_mapper.srr.db differ

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_fpga_mapper.szr b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_fpga_mapper.szr
new file mode 100644 (file)
index 0000000..1d25a89
Binary files /dev/null and b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_fpga_mapper.szr differ

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_multi_srs_gen.srr b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_multi_srs_gen.srr
new file mode 100644 (file)
index 0000000..667ebaf
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_multi_srs_gen.srr
@@ -0,0 +1,11 @@
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 14:33:12 2019
+
+###########################################################]

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_multi_srs_gen.srr.db b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_multi_srs_gen.srr.db
new file mode 100644 (file)
index 0000000..029fa7a
Binary files /dev/null and b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_multi_srs_gen.srr.db differ

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_premap.srr b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_premap.srr
new file mode 100644 (file)
index 0000000..889cbd5
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_premap.srr
@@ -0,0 +1,63 @@
+# Fri May 10 14:33:12 2019
+
+Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc
+@L: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt 
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt" file 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB)
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist pll_200_125_100
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+
+Clock Summary
+******************
+
+          Start      Requested     Requested     Clock      Clock               Clock
+Level     Clock      Frequency     Period        Type       Group               Load 
+-------------------------------------------------------------------------------------
+0 -       System     100.0 MHz     10.000        system     system_clkgroup     0    
+=====================================================================================
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 143MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Fri May 10 14:33:13 2019
+
+###########################################################]

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_premap.srr.db b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_premap.srr.db
new file mode 100644 (file)
index 0000000..d3d49fb
Binary files /dev/null and b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_premap.srr.db differ

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_premap.szr b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_premap.szr
new file mode 100644 (file)
index 0000000..54c5e81
Binary files /dev/null and b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_premap.szr differ

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/metrics.db b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/metrics.db
new file mode 100644 (file)
index 0000000..96e5995
Binary files /dev/null and b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/metrics.db differ

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_compiler_notes.txt b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_compiler_notes.txt
new file mode 100644 (file)
index 0000000..38e4cd2
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_compiler_notes.txt
@@ -0,0 +1,10 @@
+@N|Running in 64-bit mode
+@N|Running in 64-bit mode
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":12:7:12:21|Top entity is set to pll_200_125_100.
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":12:7:12:21|Synthesizing work.pll_200_125_100.structure.
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2083:10:2083:16|Synthesizing ecp5um.ehxplll.syn_black_box.
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":832:10:832:12|Synthesizing ecp5um.vlo.syn_black_box.
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":825:10:825:12|Synthesizing ecp5um.vhi.syn_black_box.
+@N|Running in 64-bit mode
+

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_compiler_runstatus.xml b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_compiler_runstatus.xml
new file mode 100644 (file)
index 0000000..e391e16
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_compiler_runstatus.xml
@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the job information from compiler to be displayed as part of the summary report.
+*******************************************************************************************-->
+
+<job_run_status name="compiler"> 
+  <report_link name="Detailed report">
+    <data>/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_compiler.srr</data>
+    <title>Synopsys HDL Compiler</title>
+  </report_link> 
+  <job_status>
+    <data>Completed    </data>
+  </job_status>
+<job_info> 
+                       <info name="Notes">
+  <data>9</data>
+  <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_compiler_notes.txt</data></report_link>
+  </info>
+                       <info name="Warnings">
+  <data>1</data>
+  <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_compiler_warnings.txt</data></report_link>
+  </info>
+                       <info name="Errors">
+  <data>0</data>
+  <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_compiler_errors.txt</data></report_link>
+  </info>
+                       <info name="CPU Time">
+  <data>-</data>
+  </info>
+                       <info name="Real Time">
+  <data>00h:00m:01s</data>
+  </info>
+                       <info name="Peak Memory">
+  <data>-</data>
+  </info>
+                       <info name="Date &amp;Time">
+  <data type="timestamp">1557491591</data>
+  </info>
+                       </job_info>
+</job_run_status>
\ No newline at end of file

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_compiler_warnings.txt b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_compiler_warnings.txt
new file mode 100644 (file)
index 0000000..25c435b
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_compiler_warnings.txt
@@ -0,0 +1,2 @@
+@W: CL168 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":50:4:50:17|Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
+

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_area_report.xml b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_area_report.xml
new file mode 100644 (file)
index 0000000..243c347
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_area_report.xml
@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the area information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<report_table display_priority="1" name="Area Summary">
+<report_link name="Detailed report">
+<data>/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_resourceusage.rpt</data>
+<title>Resource Usage</title>
+</report_link>
+<parameter tooltip="Total Register bits used" name="Register bits">
+<data>0</data>
+</parameter>
+<parameter tooltip="Total I/O cells used" name="I/O cells">
+<data>0</data>
+</parameter>
+<parameter tcl_name="v_ram" tooltip="Total Block RAMs used" name="Block RAMs">
+<data>0</data>
+</parameter>
+<parameter tcl_name="dsp_used" tooltip="Total DSPs used" name="DSPs">
+<data>0</data>
+</parameter>
+<parameter tcl_name="total_luts" tooltip="Total ORCA LUTs used" name="ORCA LUTs">
+<data>0</data>
+</parameter>
+</report_table>

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_errors.txt b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_errors.txt
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_notes.txt b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_notes.txt
new file mode 100644 (file)
index 0000000..5e801a0
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_notes.txt
@@ -0,0 +1,8 @@
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.edn
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_opt_report.xml b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_opt_report.xml
new file mode 100644 (file)
index 0000000..7832235
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_opt_report.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the optimization information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<report_table display_priority="3" name="Optimizations Summary">
+<parameter tooltip="Non-gated/non-generated clock trees / Gated/generated clock trees" name="Combined Clock Conversion">
+<data>0 / 0</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_combined_clk.rpt</data>
+<title>START OF CLOCK OPTIMIZATION REPORT</title>
+</report_link>
+</parameter>
+</report_table>

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_runstatus.xml b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_runstatus.xml
new file mode 100644 (file)
index 0000000..b0bf07a
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_runstatus.xml
@@ -0,0 +1,46 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the job information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<job_run_status name="Mapper">
+<report_link name="Detailed report">
+<data>/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_fpga_mapper.srr</data>
+<title>Synopsys Lattice Technology Mapper</title>
+</report_link>
+<job_status>
+<data>Completed</data>
+</job_status>
+<job_info>
+<info name="Notes">
+<data>8</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_notes.txt</data>
+</report_link>
+</info>
+<info name="Warnings">
+<data>1</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_warnings.txt</data>
+</report_link>
+</info>
+<info name="Errors">
+<data>0</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_errors.txt</data>
+</report_link>
+</info>
+<info name="CPU Time">
+<data>0h:00m:02s</data>
+</info>
+<info name="Real Time">
+<data>0h:00m:02s</data>
+</info>
+<info name="Peak Memory">
+<data>146MB</data>
+</info>
+<info name="Date &amp; Time">
+<data type="timestamp">1557491595</data>
+</info>
+</job_info>
+</job_run_status>

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_timing_report.xml b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_timing_report.xml
new file mode 100644 (file)
index 0000000..60b8b51
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_timing_report.xml
@@ -0,0 +1,23 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+Max Top 5 critical clocks will be reported. For rest user needs to refer to Detailed report
+*******************************************************************************************-->
+<report_table display_priority="2" name="Timing Summary">
+<report_link name="Detailed report">
+<data>/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_fpga_mapper.srr</data>
+<title>START OF TIMING REPORT</title>
+</report_link>
+<row>
+<data tcl_name="clock_name">Clock Name</data>
+<data tcl_name="req_freq">Req Freq</data>
+<data tcl_name="est_freq">Est Freq</data>
+<data tcl_name="slack">Slack</data>
+</row>
+<row>
+<data>System</data>
+<data>100.0 MHz</data>
+<data>NA</data>
+<data>10.000</data>
+</row>
+</report_table>

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_warnings.txt b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_warnings.txt
new file mode 100644 (file)
index 0000000..ebff314
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_fpga_mapper_warnings.txt
@@ -0,0 +1 @@
+@W: MT246 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":56:4:56:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_errors.txt b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_errors.txt
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_notes.txt b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_notes.txt
new file mode 100644 (file)
index 0000000..eed8756
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_notes.txt
@@ -0,0 +1,2 @@
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_runstatus.xml b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_runstatus.xml
new file mode 100644 (file)
index 0000000..00fedf8
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_runstatus.xml
@@ -0,0 +1,46 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the job information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<job_run_status name="Mapper">
+<report_link name="Detailed report">
+<data>/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/pll_200_125_100_premap.srr</data>
+<title>Synopsys Lattice Technology Pre-mapping</title>
+</report_link>
+<job_status>
+<data>Completed</data>
+</job_status>
+<job_info>
+<info name="Notes">
+<data>2</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_notes.txt</data>
+</report_link>
+</info>
+<info name="Warnings">
+<data>0</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_warnings.txt</data>
+</report_link>
+</info>
+<info name="Errors">
+<data>0</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_errors.txt</data>
+</report_link>
+</info>
+<info name="CPU Time">
+<data>0h:00m:00s</data>
+</info>
+<info name="Real Time">
+<data>0h:00m:00s</data>
+</info>
+<info name="Peak Memory">
+<data>143MB</data>
+</info>
+<info name="Date &amp; Time">
+<data type="timestamp">1557491593</data>
+</info>
+</job_info>
+</job_run_status>

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_warnings.txt b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/report/pll_200_125_100_premap_warnings.txt
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/syntax_constraint_check.rpt.rptmap b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/syntax_constraint_check.rpt.rptmap
new file mode 100644 (file)
index 0000000..0213fed
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synlog/syntax_constraint_check.rpt.rptmap
@@ -0,0 +1 @@
+./pll_200_125_100_scck.rpt,syntax_constraint_check.rpt,Syntax Constraint Check Report

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/closed.png b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/closed.png
new file mode 100644 (file)
index 0000000..0d78634
Binary files /dev/null and b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/closed.png differ

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/open.png b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/open.png
new file mode 100644 (file)
index 0000000..a227005
Binary files /dev/null and b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/open.png differ

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100.plg b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100.plg
new file mode 100644 (file)
index 0000000..bba9612
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100.plg
@@ -0,0 +1,8 @@
+@P:  Worst Slack : 10.000
+@P:  System - Estimated Frequency : NA
+@P:  System - Requested Frequency : 100.0 MHz
+@P:  System - Estimated Period : 0.000
+@P:  System - Requested Period : 10.000
+@P:  System - Slack : 10.000
+@P:  Total Area : 0.0
+@P:  CPU Time : 0h:00m:02s

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_srr.htm b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_srr.htm
new file mode 100644 (file)
index 0000000..2d8be4d
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_srr.htm
@@ -0,0 +1,428 @@
+<html><body><samp><pre>
+<!@TC:1557491590>
+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
+#install: /home/soft/lattice/diamond/3.10_x64/synpbase
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Fri May 10 14:33:10 2019
+
+#Implementation: syn_results
+
+<a name=compilerReport1></a>Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1557491591> | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+<a name=compilerReport2></a>Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1557491591> | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1557491591> | Setting time resolution to ps
+@N: : <a href="/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd:12:7:12:22:@N::@XP_MSG">pll_200_125_100.vhd(12)</a><!@TM:1557491591> | Top entity is set to pll_200_125_100.
+VHDL syntax check successful!
+@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd:12:7:12:22:@N:CD630:@XP_MSG">pll_200_125_100.vhd(12)</a><!@TM:1557491591> | Synthesizing work.pll_200_125_100.structure.
+@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd:2083:10:2083:17:@N:CD630:@XP_MSG">ecp5um.vhd(2083)</a><!@TM:1557491591> | Synthesizing ecp5um.ehxplll.syn_black_box.
+Post processing for ecp5um.ehxplll.syn_black_box
+@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd:832:10:832:13:@N:CD630:@XP_MSG">ecp5um.vhd(832)</a><!@TM:1557491591> | Synthesizing ecp5um.vlo.syn_black_box.
+Post processing for ecp5um.vlo.syn_black_box
+@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd:825:10:825:13:@N:CD630:@XP_MSG">ecp5um.vhd(825)</a><!@TM:1557491591> | Synthesizing ecp5um.vhi.syn_black_box.
+Post processing for ecp5um.vhi.syn_black_box
+Post processing for work.pll_200_125_100.structure
+<font color=#A52A2A>@W:<a href="@W:CL168:@XP_HELP">CL168</a> : <a href="/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd:50:4:50:18:@W:CL168:@XP_MSG">pll_200_125_100.vhd(50)</a><!@TM:1557491591> | Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.</font>
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 14:33:11 2019
+
+###########################################################]
+<a name=compilerReport3></a>Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1557491591> | Running in 64-bit mode 
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 14:33:11 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 14:33:11 2019
+
+###########################################################]
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1557491590>
+<a name=compilerReport4></a>Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1557491592> | Running in 64-bit mode 
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 14:33:12 2019
+
+###########################################################]
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1557491590>
+Pre-mapping Report
+
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1557491590>
+# Fri May 10 14:33:12 2019
+
+<a name=mapperReport5></a>Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35</a>
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc
+Linked File: <a href="/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt:@XP_FILE">pll_200_125_100_scck.rpt</a>
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_scck.rpt" file 
+@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1557491593> | Running in 64-bit mode. 
+@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1557491593> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB)
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist pll_200_125_100
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+
+<a name=mapperReport6></a>Clock Summary</a>
+******************
+
+          Start      Requested     Requested     Clock      Clock               Clock
+Level     Clock      Frequency     Period        Type       Group               Load 
+-------------------------------------------------------------------------------------
+0 -       System     100.0 MHz     10.000        system     system_clkgroup     0    
+=====================================================================================
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 143MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Fri May 10 14:33:13 2019
+
+###########################################################]
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1557491590>
+Map & Optimize Report
+
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1557491590>
+# Fri May 10 14:33:13 2019
+
+<a name=mapperReport7></a>Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35</a>
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1557491595> | Running in 64-bit mode. 
+@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1557491595> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1557491595> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+<a name=clockReport8></a>#### START OF CLOCK OPTIMIZATION REPORT #####[</a>
+
+0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+Writing EDIF Netlist and constraint files
+@N:<a href="@N:FX1056:@XP_HELP">FX1056</a> : <!@TM:1557491595> | Writing EDF file: /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.edn 
+M-2017.03L-SP1-1
+@N:<a href="@N:BW106:@XP_HELP">BW106</a> : <!@TM:1557491595> | Synplicity Constraint File capacitance units using default value of 1pF  
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
+
+<font color=#A52A2A>@W:<a href="@W:MT246:@XP_HELP">MT246</a> : <a href="/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd:56:4:56:13:@W:MT246:@XP_MSG">pll_200_125_100.vhd(56)</a><!@TM:1557491595> | Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) </font>
+
+
+<a name=timingReport9></a>##### START OF TIMING REPORT #####[</a>
+# Timing Report written on Fri May 10 14:33:15 2019
+#
+
+
+Top view:               pll_200_125_100
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.fdc
+                       
+@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1557491595> | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 
+
+@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1557491595> | Clock constraints include only register-to-register paths associated with each individual clock. 
+
+
+
+<a name=performanceSummary10></a>Performance Summary</a>
+*******************
+
+
+Worst slack in design: 10.000
+
+@N:<a href="@N:MT286:@XP_HELP">MT286</a> : <!@TM:1557491595> | System clock period 0.000 stretches to negative invalid value -- ignoring stretching. 
+                   Requested     Estimated     Requested     Estimated                Clock      Clock          
+Starting Clock     Frequency     Frequency     Period        Period        Slack      Type       Group          
+----------------------------------------------------------------------------------------------------------------
+System             100.0 MHz     NA            10.000        0.000         10.000     system     system_clkgroup
+================================================================================================================
+Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
+
+
+
+
+
+<a name=clockRelationships11></a>Clock Relationships</a>
+*******************
+
+Clocks            |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+---------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
+---------------------------------------------------------------------------------------------------------
+System    System  |  10.000      10.000  |  No paths    -      |  No paths    -      |  No paths    -    
+=========================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+<a name=interfaceInfo12></a>Interface Information </a>
+*********************
+
+No IO constraint found
+
+
+
+====================================
+<a name=clockReport13></a>Detailed Report for Clock: System</a>
+====================================
+
+
+
+<a name=startingSlack14></a>Starting Points with Worst Slack</a>
+********************************
+
+              Starting                                           Arrival           
+Instance      Reference     Type        Pin          Net         Time        Slack 
+              Clock                                                                
+-----------------------------------------------------------------------------------
+PLLInst_0     System        EHXPLLL     CLKINTFB     CLKFB_t     0.000       10.000
+===================================================================================
+
+
+<a name=endingSlack15></a>Ending Points with Worst Slack</a>
+******************************
+
+              Starting                                        Required           
+Instance      Reference     Type        Pin       Net         Time         Slack 
+              Clock                                                              
+---------------------------------------------------------------------------------
+PLLInst_0     System        EHXPLLL     CLKFB     CLKFB_t     10.000       10.000
+=================================================================================
+
+
+
+<a name=worstPaths16></a>Worst Path Information</a>
+<a href="/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srr:srsf/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100.srs:fp:17491:17746:@XP_NAMES_GATE">View Worst Path in Analyst</a>
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.000
+    + Clock delay at ending point:           0.000 (ideal)
+    + Estimated clock delay at ending point: 0.000
+    = Required time:                         10.000
+
+    - Propagation time:                      0.000
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (critical) :                     10.000
+
+    Number of logic level(s):                0
+    Starting point:                          PLLInst_0 / CLKINTFB
+    Ending point:                            PLLInst_0 / CLKFB
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            System [rising]
+
+Instance / Net                 Pin          Pin               Arrival     No. of    
+Name               Type        Name         Dir     Delay     Time        Fan Out(s)
+------------------------------------------------------------------------------------
+PLLInst_0          EHXPLLL     CLKINTFB     Out     0.000     0.000       -         
+CLKFB_t            Net         -            -       -         -           1         
+PLLInst_0          EHXPLLL     CLKFB        In      0.000     0.000       -         
+====================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB)
+
+---------------------------------------
+<a name=resourceUsage17></a>Resource Usage Report</a>
+Part: lfe5um_25f-6
+
+Register bits: 0 of 24288 (0%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+EHXPLLL:        1
+GSR:            1
+PUR:            1
+VHI:            1
+VLO:            1
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 146MB)
+
+Process took 0h:00m:02s realtime, 0h:00m:02s cputime
+# Fri May 10 14:33:15 2019
+
+###########################################################]
+
+</pre></samp></body></html>

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_toc.htm b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_toc.htm
new file mode 100644 (file)
index 0000000..75d317d
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_toc.htm
@@ -0,0 +1,45 @@
+ <html> 
+  <head>
+    <script type="text/javascript" src="file:///home/soft/lattice/diamond/3.10_x64/synpbase/lib/report/reportlog_tree.js"></script>
+    <link rel="stylesheet" type="text/css" href="file:///home/soft/lattice/diamond/3.10_x64/synpbase/lib/report/reportlog_tree.css" />  
+  </head> 
+
+  <body style="background-color:#e0e0ff;">
+   <script type="text/javascript"> reportLogObj.loadImage("closed.png", "open.png")</script>
+    <ul id="syn_results-menu" class="treeview" style="padding-left:12;">
+        <li style="font-size:12; font-style:normal"> <b style="background-color:#a2bff0; font-weight:bold">pll_200_125_100 (syn_results)</b> 
+         <ul rel="open" style="font-size:small;">
+
+<li style="font-size:12; font-style:normal"><b style="background-color:#a2bff0; font-weight:bold">Synthesis -  </b> 
+<ul rel="open">
+<li><a href="file:///home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_srr.htm#compilerReport1" target="srrFrame" title="">Compiler Report</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_srr.htm#compilerReport3" target="srrFrame" title="">Compiler Constraint Applicator</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_srr.htm#mapperReport5" target="srrFrame" title="">Pre-mapping Report</a>  
+<ul rel="open" >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_srr.htm#mapperReport6" target="srrFrame" title="">Clock Summary</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_srr.htm#mapperReport7" target="srrFrame" title="">Mapper Report</a>  
+<ul rel="open" >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_srr.htm#clockReport8" target="srrFrame" title="">Clock Conversion</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_srr.htm#timingReport9" target="srrFrame" title="">Timing Report</a>  
+<ul rel="open" >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_srr.htm#performanceSummary10" target="srrFrame" title="">Performance Summary</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_srr.htm#clockRelationships11" target="srrFrame" title="">Clock Relationships</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_srr.htm#interfaceInfo12" target="srrFrame" title="">Interface Information</a>  </li>
+<li><a href="file://#" target="srrFrame" title="">Detailed Report for Clocks</a>  
+<ul  >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_srr.htm#clockReport13" target="srrFrame" title="">Clock: System</a>  
+<ul  >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_srr.htm#startingSlack14" target="srrFrame" title="">Starting Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_srr.htm#endingSlack15" target="srrFrame" title="">Ending Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_srr.htm#worstPaths16" target="srrFrame" title="">Worst Path Information</a>  </li></ul></li></ul></li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/pll_200_125_100_srr.htm#resourceUsage17" target="srrFrame" title="">Resource Utilization</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/pll_200_125_100_cck.rpt" target="srrFrame" title="">Constraint Checker Report (14:33 10-May)</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/stdout.log" target="srrFrame" title="">Session Log (14:33 10-May)</a>  
+<ul  ></ul></li>         </ul>
+        </li>
+   </ul>
+
+   <script type="text/javascript"> reportLogObj.generateLog("syn_results-menu")</script>
+
+  </body>
+ </html>
\ No newline at end of file

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/run_option.xml b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/run_option.xml
new file mode 100644 (file)
index 0000000..35a3688
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/run_option.xml
@@ -0,0 +1,24 @@
+<?xml version="1.0" encoding="utf-8"?> 
+<!-- 
+  Synopsys, Inc.
+  Version M-2017.03L-SP1-1
+  Project file /home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/run_option.xml
+  Written on Fri May 10 14:33:10 2019
+
+
+--> 
+<project_attribute_list name="Project Settings"> 
+     <option name="project_name" display_name="Project Name">pll_200_125_100</option>
+     <option name="device_name" display_name="Device Name">syn_results: Lattice ECP5UM : LFE5UM_25F</option>
+     <option name="impl_name" display_name="Implementation Name">syn_results</option>
+     <option name="top_module" display_name="Top Module">pll_200_125_100</option>
+     <option name="pipe" display_name="Pipelining">0</option>
+     <option name="retiming" display_name="Retiming">0</option>
+     <option name="resource_sharing" display_name="Resource Sharing">1</option>
+     <option name="maxfan" display_name="Fanout Guide">50</option>
+     <option name="disable_io_insertion" display_name="Disable I/O Insertion">1</option>
+     <option name="no_sequential_opt" display_name="Disable Sequential Optimizations">0</option>
+     <option name="fix_gated_and_generated_clocks" display_name="Clock Conversion">1</option>
+     <option name="symbolic_fsm_compiler" display_name="FSM Compiler">1</option>
+</project_attribute_list>
+

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/statusReport.html b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/statusReport.html
new file mode 100644 (file)
index 0000000..c4d093f
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/syntmp/statusReport.html
@@ -0,0 +1,112 @@
+<html> 
+                       <head>                  <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1" />
+                       <title>Project Status Summary Page</title>
+                       <link rel="stylesheet" type="text/css" href="projectstatuspage.css" />
+                       <script type = "text/javascript" src="projectstatuspage.js"></script>
+                       </head>
+
+                       <body style="background-color:#f0f0ff;">
+                       
+<table style="border:none;" width="100%" ><tr> <td class="outline">
+<table width="100%" border="0" cellspacing="0" cellpadding="0">             <thead class="tablehead"><tr><th colspan="4">Project Settings</th><tr> 
+ <tr> <td class="optionTitle" align="left"> Project Name</td> <td> pll_200_125_100</td> <td class="optionTitle" align="left"> Device Name</td> <td> syn_results: Lattice ECP5UM : LFE5UM_25F</td> </tr>
+<tr> <td class="optionTitle" align="left"> Implementation Name</td> <td> syn_results</td> <td class="optionTitle" align="left"> Top Module</td> <td> pll_200_125_100</td> </tr>
+                </thead> 
+                <tbody> <tr> <td class="optionTitle" align="left"> Pipelining</td> <td> 0</td> <td class="optionTitle" align="left"> Retiming</td> <td> 0</td> </tr>
+<tr> <td class="optionTitle" align="left"> Resource Sharing</td> <td> 1</td> <td class="optionTitle" align="left"> Fanout Guide</td> <td> 50</td> </tr>
+<tr> <td class="optionTitle" align="left"> Disable I/O Insertion</td> <td> 1</td> <td class="optionTitle" align="left"> Disable Sequential Optimizations</td> <td> 0</td> </tr>
+<tr> <td class="optionTitle" align="left"> Clock Conversion</td> <td> 1</td> <td class="optionTitle" align="left"> FSM Compiler</td> <td> 1</td> </tr>
+ 
+</tbody> 
+  </table><br>  <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
+                                  <thead class="tablehead"><tr><th   colspan="9">Run Status</th></tr></thead>
+         <tbody>
+               <tr>
+                       <th align="left" width="17%">Job Name</th>
+                       <th align="left">Status</th>
+                       <td class="lnote" align="center" title="Notes"></td>
+                       <td class="lwarn" align="center" title="Warnings"></td>
+                       <td class="lerror" align="center" title="Errors"></td>
+                       <th align="left">CPU Time</th>
+                       <th align="left">Real Time</th>
+                       <th align="left">Memory</th>
+                       <th align="left">Date/Time</th>
+         </tr>
+  <tr>
+  <td class="optionTitle"> (compiler)</td><td>Complete</td>
+ <td>9</td>
+ <td>1</td>
+<td>0</td>
+<td>-</td>
+<td>00m:01s</td>
+<td>-</td>
+<td><font size="-1">5/10/19</font><br/><font size="-2">2:33 PM</font></td>
+</tr> 
+
+ <tr>
+  <td class="optionTitle"> (premap)</td><td>Complete</td>
+ <td>2</td>
+<td>0</td>
+<td>0</td>
+<td>0m:00s</td>
+<td>0m:00s</td>
+<td>143MB</td>
+<td><font size="-1">5/10/19</font><br/><font size="-2">2:33 PM</font></td>
+</tr> 
+
+ <tr>
+  <td class="optionTitle"> (fpga_mapper)</td><td>Complete</td>
+ <td>8</td>
+ <td>1</td>
+<td>0</td>
+<td>0m:02s</td>
+<td>0m:02s</td>
+<td>146MB</td>
+<td><font size="-1">5/10/19</font><br/><font size="-2">2:33 PM</font></td>
+</tr> 
+
+<tr>
+  <td class="optionTitle">Multi-srs Generator</td>
+  <td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td></td><td class="empty"></td><td class="empty"></td><td><font size="-1">5/10/19</font><br/><font size="-2">2:33 PM</font></td>              </tbody>
+     </table>
+ <br> 
+ <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
+                                  <thead class="tablehead"><tr><th   colspan="4">Area Summary</th></tr></thead>
+<tfoot> <tr> <td class="optionTitle" colspan="4"></td></tr> 
+ </tfoot> 
+ <tbody> <tr> 
+<td title ="Total Register bits used" class="optionTitle" align="left">Register bits</td> <td>0</td>
+<td title ="Total I/O cells used" class="optionTitle" align="left">I/O cells</td> <td>0</td>
+</tr>
+<tr> 
+<td title ="Total Block RAMs used" class="optionTitle" align="left">Block RAMs
+(v_ram)</td> <td>0</td>
+<td title ="Total DSPs used" class="optionTitle" align="left">DSPs
+(dsp_used)</td> <td>0</td>
+</tr>
+<tr> 
+<td title ="Total ORCA LUTs used" class="optionTitle" align="left">ORCA LUTs
+(total_luts)</td> <td>0</td>
+<td class="optionTitle"></td><td></td></tr> 
+</tbody>
+    </table><br>
+ <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
+                                  <thead class="tablehead"><tr><th   colspan="4">Timing Summary</th></tr></thead>
+<tfoot> <tr> <td class="optionTitle" colspan="2"></td></tr> 
+ </tfoot> 
+<tbody> 
+   <tr><th class="optionTitle" align= "left ">Clock Name</th><th class="optionTitle" align= "left ">Req Freq</th><th class="optionTitle" align= "left ">Est Freq</th><th class="optionTitle" align= "left ">Slack</th></tr> 
+<tr> <td  align="left">System</td><td  align="left">100.0 MHz</td><td  align="left">NA</td><td  align="left">10.000</td></tr> 
+</tbody> 
+ </table>
+<br>
+ <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
+                                  <thead class="tablehead"><tr><th   colspan="4">Optimizations Summary</th></tr></thead>
+ <tbody> <tr> 
+<td title ="Non-gated/non-generated clock trees / Gated/generated clock trees" class="optionTitle" align="left">Combined Clock Conversion</td> <td>0 / 0</td>
+<td class="optionTitle"></td><td></td></tr> 
+</tbody>
+    </table><br>
+<br> 
+</td></tr></table></body> 
+ </html>
\ No newline at end of file

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/.cckTransfer b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/.cckTransfer
new file mode 100644 (file)
index 0000000..8d68b51
Binary files /dev/null and b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/.cckTransfer differ

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/_mh_info b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/_mh_info
new file mode 100644 (file)
index 0000000..37bc105
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/_mh_info
@@ -0,0 +1 @@
+|1|

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/layer0.fdep b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/layer0.fdep
new file mode 100644 (file)
index 0000000..0d906a3
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/layer0.fdep
@@ -0,0 +1,28 @@
+#defaultlanguage:vhdl
+#OPTIONS:"|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_comp.srs|-top|pll_200_125_100|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610
+#CUR:"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":1557491589
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599
+0 "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd" vhdl
+
+# Dependency Lists (Uses list)
+0 -1
+
+# Dependency Lists (Users Of)
+0 -1
+
+# Design Unit to File Association
+arch work pll_200_125_100 structure 0
+module work pll_200_125_100 0
+
+
+# Configuration files used

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/layer0.fdeporig b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/layer0.fdeporig
new file mode 100644 (file)
index 0000000..7b38ff3
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/layer0.fdeporig
@@ -0,0 +1,24 @@
+#defaultlanguage:vhdl
+#OPTIONS:"|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_comp.srs|-top|pll_200_125_100|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610
+#CUR:"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":1557491589
+0 "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd" vhdl
+
+# Dependency Lists (Uses list)
+0 -1
+
+# Dependency Lists (Users Of)
+0 -1
+
+# Design Unit to File Association
+arch work pll_200_125_100 structure 0
+module work pll_200_125_100 0

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/layer0.srs b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/layer0.srs
new file mode 100644 (file)
index 0000000..b9cb7b8
Binary files /dev/null and b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/layer0.srs differ

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/layer0.tlg b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/layer0.tlg
new file mode 100644 (file)
index 0000000..5b9fa01
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/layer0.tlg
@@ -0,0 +1,9 @@
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":12:7:12:21|Synthesizing work.pll_200_125_100.structure.
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2083:10:2083:16|Synthesizing ecp5um.ehxplll.syn_black_box.
+Post processing for ecp5um.ehxplll.syn_black_box
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":832:10:832:12|Synthesizing ecp5um.vlo.syn_black_box.
+Post processing for ecp5um.vlo.syn_black_box
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":825:10:825:12|Synthesizing ecp5um.vhi.syn_black_box.
+Post processing for ecp5um.vhi.syn_black_box
+Post processing for work.pll_200_125_100.structure
+@W: CL168 :"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":50:4:50:17|Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/layer0.tlg.db b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/layer0.tlg.db
new file mode 100644 (file)
index 0000000..ad02b69
Binary files /dev/null and b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/layer0.tlg.db differ

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/modulechange.db b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/modulechange.db
new file mode 100644 (file)
index 0000000..e1d5313
Binary files /dev/null and b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/modulechange.db differ

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_comp.fdep b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_comp.fdep
new file mode 100644 (file)
index 0000000..fcced78
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_comp.fdep
@@ -0,0 +1,21 @@
+#OPTIONS:"|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_comp.srs|-top|pll_200_125_100|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610
+#CUR:"/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd":1557491589
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599
+0                      "/home/adrian/git/trb5sc/template/project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd" vhdl
+#Dependency Lists(Uses List)
+0 -1
+#Dependency Lists(Users Of)
+0 -1
+#Design Unit to File Association
+module work pll_200_125_100 0
+arch work pll_200_125_100 structure 0

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_comp.srs b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_comp.srs
new file mode 100644 (file)
index 0000000..4c5eb1b
Binary files /dev/null and b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_comp.srs differ

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_m.srm b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_m.srm
new file mode 100644 (file)
index 0000000..cbb05bb
Binary files /dev/null and b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_m.srm differ

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_m_srm/fileinfo.srm b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_m_srm/fileinfo.srm
new file mode 100644 (file)
index 0000000..81ac158
Binary files /dev/null and b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_m_srm/fileinfo.srm differ

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_mult.srs b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_mult.srs
new file mode 100644 (file)
index 0000000..a7fea3b
Binary files /dev/null and b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_mult.srs differ

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_mult_srs/fileinfo.srs b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_mult_srs/fileinfo.srs
new file mode 100644 (file)
index 0000000..473d9a8
Binary files /dev/null and b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_mult_srs/fileinfo.srs differ

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_mult_srs/skeleton.srs b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_mult_srs/skeleton.srs
new file mode 100644 (file)
index 0000000..99ef1b9
Binary files /dev/null and b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_mult_srs/skeleton.srs differ

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_prem.fse b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_prem.fse
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_prem.srd b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_prem.srd
new file mode 100644 (file)
index 0000000..9e1c93b
Binary files /dev/null and b/gbe/cores/pll_200_200_125_100/pll_200_125_100/syn_results/synwork/pll_200_125_100_prem.srd differ

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_200_125_100.sbx b/gbe/cores/pll_200_200_125_100/pll_200_200_125_100.sbx
new file mode 100644 (file)
index 0000000..e683721
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_200_125_100.sbx
@@ -0,0 +1,617 @@
+<!DOCTYPE pll_200_200_125_100>
+<lattice:project>
+    <spirit:component>
+        <spirit:vendor>LATTICE</spirit:vendor>
+        <spirit:library>LOCAL</spirit:library>
+        <spirit:name>pll_200_200_125_100</spirit:name>
+        <spirit:version>1.0</spirit:version>
+        <spirit:fileSets>
+            <spirit:fileset>
+                <spirit:name>Diamond_Synthesis</spirit:name>
+                <spirit:group>synthesis</spirit:group>
+                <spirit:file>
+                    <spirit:name>./pll_200_200_125_100.vhd</spirit:name>
+                    <spirit:fileType>vhdlSource</spirit:fileType>
+                </spirit:file>
+            </spirit:fileset>
+            <spirit:fileset>
+                <spirit:name>Diamond_Simulation</spirit:name>
+                <spirit:group>simulation</spirit:group>
+                <spirit:file>
+                    <spirit:name>./pll_200_200_125_100.vhd</spirit:name>
+                    <spirit:fileType>vhdlSource</spirit:fileType>
+                </spirit:file>
+            </spirit:fileset>
+        </spirit:fileSets>
+        <spirit:componentGenerators/>
+        <spirit:model>
+            <spirit:views/>
+            <spirit:ports>
+                <spirit:port>
+                    <spirit:name>pll_200_125_100_CLKI</spirit:name>
+                    <spirit:displayName>pll_200_125_100_CLKI</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">pll_200_125_100.CLKI</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>pll_200_125_100_CLKOP</spirit:name>
+                    <spirit:displayName>pll_200_125_100_CLKOP</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">pll_200_125_100.CLKOP</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>pll_200_125_100_CLKOS</spirit:name>
+                    <spirit:displayName>pll_200_125_100_CLKOS</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">pll_200_125_100.CLKOS</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>pll_200_125_100_CLKOS2</spirit:name>
+                    <spirit:displayName>pll_200_125_100_CLKOS2</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">pll_200_125_100.CLKOS2</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>pll_200_125_100_LOCK</spirit:name>
+                    <spirit:displayName>pll_200_125_100_LOCK</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">pll_200_125_100.LOCK</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+            </spirit:ports>
+        </spirit:model>
+        <spirit:vendorExtensions>
+            <lattice:device>LFE5UM-85F-8BG756C</lattice:device>
+            <lattice:synthesis>synplify</lattice:synthesis>
+            <lattice:date>2019-05-10.02:28:17 PM</lattice:date>
+            <lattice:modified>2019-05-10.02:38:07 PM</lattice:modified>
+            <lattice:diamond>3.10.3.144</lattice:diamond>
+            <lattice:language>VHDL</lattice:language>
+            <lattice:attributes>
+                <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+                <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+                <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+                <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+            </lattice:attributes>
+            <lattice:elements/>
+            <lattice:lpc/>
+            <lattice:groups/>
+        </spirit:vendorExtensions>
+    </spirit:component>
+    <spirit:design>
+        <spirit:vendor>LATTICE</spirit:vendor>
+        <spirit:library>LOCAL</spirit:library>
+        <spirit:name>pll_200_200_125_100</spirit:name>
+        <spirit:version>1.0</spirit:version>
+        <spirit:componentInstances>
+            <spirit:componentInstance>
+                <spirit:instanceName>pll_200_125_100</spirit:instanceName>
+                <spirit:componentRef>
+                    <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
+                    <spirit:library>LEGACY</spirit:library>
+                    <spirit:name>PLL</spirit:name>
+                    <spirit:version>5.8</spirit:version>
+                    <spirit:fileSets>
+                        <spirit:fileset>
+                            <spirit:name>Diamond_Simulation</spirit:name>
+                            <spirit:group>simulation</spirit:group>
+                            <spirit:file>
+                                <spirit:name>./pll_200_125_100/pll_200_125_100.vhd</spirit:name>
+                                <spirit:fileType>vhdlSource</spirit:fileType>
+                            </spirit:file>
+                        </spirit:fileset>
+                        <spirit:fileset>
+                            <spirit:name>Diamond_Synthesis</spirit:name>
+                            <spirit:group>synthesis</spirit:group>
+                            <spirit:file>
+                                <spirit:name>./pll_200_125_100/pll_200_125_100.vhd</spirit:name>
+                                <spirit:fileType>vhdlSource</spirit:fileType>
+                            </spirit:file>
+                        </spirit:fileset>
+                    </spirit:fileSets>
+                    <spirit:componentGenerators>
+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>Configuration</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
+                            <spirit:group>CONFIG</spirit:group>
+                        </spirit:componentGenerator>
+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>CreateNGD</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_ngd.tcl</spirit:generatorExe>
+                            <spirit:group>CONFIG</spirit:group>
+                        </spirit:componentGenerator>
+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>Generation</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
+                            <spirit:group>GENERATE</spirit:group>
+                        </spirit:componentGenerator>
+                    </spirit:componentGenerators>
+                    <spirit:model>
+                        <spirit:views/>
+                        <spirit:ports>
+                            <spirit:port>
+                                <spirit:name>CLKI</spirit:name>
+                                <spirit:displayName>CLKI</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>CLKOP</spirit:name>
+                                <spirit:displayName>CLKOP</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>CLKOS</spirit:name>
+                                <spirit:displayName>CLKOS</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>CLKOS2</spirit:name>
+                                <spirit:displayName>CLKOS2</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>LOCK</spirit:name>
+                                <spirit:displayName>LOCK</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                        </spirit:ports>
+                    </spirit:model>
+                    <spirit:vendorExtensions>
+                        <lattice:synthesis>synplify</lattice:synthesis>
+                        <lattice:modified>2019-05-10.02:38:07 PM</lattice:modified>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+                            <lattice:attribute lattice:name="BBox">false</lattice:attribute>
+                            <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+                            <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute>
+                            <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute>
+                            <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute>
+                            <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+                            <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+                        </lattice:attributes>
+                        <lattice:elements/>
+                        <lattice:lpc>
+                            <lattice:lpcsection lattice:name="Device"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Family</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">ecp5um</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>OperatingCondition</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Package</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">CABGA756</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PartName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F-8BG756C</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PartType</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SpeedGrade</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Status</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">P</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="IP"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">PLL</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreRevision</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">5.8</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreStatus</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreType</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Date</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">05/10/2019</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ModuleName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">pll_200_125_100</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SourceFormat</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">VHDL</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Time</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">14:33:07</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>VendorName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="Parameters"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKFB_DIV</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKI_DIV</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">2</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKI_FREQ</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">200</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOP_ACTUAL_FREQ</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">200.000000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOP_APHASE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOP_DIV</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOP_DPHASE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOP_FREQ</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">200</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOP_MUXA</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">ENABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOP_TOL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0.0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOP_TRIM_DELAY</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOP_TRIM_POL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS2_ACTUAL_FREQ</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">125.000000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS2_APHASE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS2_DIV</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">4</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS2_DPHASE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS2_Enable</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">ENABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS2_FREQ</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">125.00</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS2_MUXC</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS2_TOL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0.0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS2_TRIM_DELAY</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS2_TRIM_POL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS3_ACTUAL_FREQ</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0.000000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS3_APHASE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS3_DIV</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS3_DPHASE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS3_Enable</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS3_FREQ</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">125.00</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS3_MUXD</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS3_TOL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0.0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS3_TRIM_DELAY</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS3_TRIM_POL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS_ACTUAL_FREQ</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">100.000000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS_APHASE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS_DIV</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">5</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS_DPHASE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS_Enable</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">ENABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS_FREQ</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">100.00</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS_MUXB</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS_TOL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0.0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS_TRIM_DELAY</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS_TRIM_POL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKSEL_ENA</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>DPHASE_SOURCE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">STATIC</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Destination</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>EDIF</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ENABLE_CLKOP</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ENABLE_CLKOS</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ENABLE_CLKOS2</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ENABLE_CLKOS3</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ENABLE_HBW</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Expression</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">BusA(0 to 7)</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>FEEDBK_PATH</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">INT_OS</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>FRACN_DIV</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>FRACN_ENABLE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>IO</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>IOBUF</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LVDS</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Order</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PLLRST_ENA</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PLL_BW</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">10.695</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PLL_LOCK_MODE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">ENABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PLL_LOCK_STK</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PLL_USE_SMI</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>REFERENCE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>STDBY_ENABLE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>VCO_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">500.000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>VHDL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Verilog</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="Command"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>cmd_line</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">-w -n pll_200_125_100 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -bypassp -fclkos 100.00 -fclkos_tol 0.0 -fclkos2 125.00 -fclkos2_tol 0.0 -phases2 0 -phase_cntl STATIC -lock -fb_mode 6</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                        </lattice:lpc>
+                        <lattice:groups/>
+                    </spirit:vendorExtensions>
+                </spirit:componentRef>
+            </spirit:componentInstance>
+        </spirit:componentInstances>
+        <spirit:adHocConnections>
+            <spirit:adHocConnection>
+                <spirit:name>pll_200_125_100_CLKI</spirit:name>
+                <spirit:displayName>pll_200_125_100_CLKI</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="CLKI" spirit:componentRef="pll_200_125_100"/>
+                <spirit:externalPortReference spirit:portRef="pll_200_125_100_CLKI"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>pll_200_125_100_CLKOP</spirit:name>
+                <spirit:displayName>pll_200_125_100_CLKOP</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="CLKOP" spirit:componentRef="pll_200_125_100"/>
+                <spirit:externalPortReference spirit:portRef="pll_200_125_100_CLKOP"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>pll_200_125_100_CLKOS</spirit:name>
+                <spirit:displayName>pll_200_125_100_CLKOS</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="CLKOS" spirit:componentRef="pll_200_125_100"/>
+                <spirit:externalPortReference spirit:portRef="pll_200_125_100_CLKOS"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>pll_200_125_100_CLKOS2</spirit:name>
+                <spirit:displayName>pll_200_125_100_CLKOS2</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="CLKOS2" spirit:componentRef="pll_200_125_100"/>
+                <spirit:externalPortReference spirit:portRef="pll_200_125_100_CLKOS2"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>pll_200_125_100_LOCK</spirit:name>
+                <spirit:displayName>pll_200_125_100_LOCK</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="LOCK" spirit:componentRef="pll_200_125_100"/>
+                <spirit:externalPortReference spirit:portRef="pll_200_125_100_LOCK"/>
+            </spirit:adHocConnection>
+        </spirit:adHocConnections>
+    </spirit:design>
+</lattice:project>

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_200_125_100.vhd b/gbe/cores/pll_200_200_125_100/pll_200_200_125_100.vhd
new file mode 100644 (file)
index 0000000..4d11d32
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_200_125_100.vhd
@@ -0,0 +1,39 @@
+
+
+--
+-- Verific VHDL Description of module pll_200_200_125_100
+--
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+entity pll_200_200_125_100 is
+    port (pll_200_125_100_CLKI: in std_logic;
+        pll_200_125_100_CLKOP: out std_logic;
+        pll_200_125_100_CLKOS: out std_logic;
+        pll_200_125_100_CLKOS2: out std_logic;
+        pll_200_125_100_LOCK: out std_logic
+    );
+    
+end entity pll_200_200_125_100; -- sbp_module=true 
+
+architecture pll_200_200_125_100 of pll_200_200_125_100 is 
+    component pll_200_125_100 is
+        port (CLKI: in std_logic;
+            CLKOP: out std_logic;
+            CLKOS: out std_logic;
+            CLKOS2: out std_logic;
+            LOCK: out std_logic
+        );
+        
+    end component pll_200_125_100; -- not_need_bbox=true 
+    
+    
+    
+begin
+    pll_200_125_100_inst: component pll_200_125_100 port map (CLKI=>pll_200_125_100_CLKI,
+            CLKOP=>pll_200_125_100_CLKOP,CLKOS=>pll_200_125_100_CLKOS,CLKOS2=>pll_200_125_100_CLKOS2,
+            LOCK=>pll_200_125_100_LOCK);
+    
+end architecture pll_200_200_125_100; -- sbp_module=true 
+

diff --git a/gbe/cores/pll_200_200_125_100/pll_200_200_125_100_tmpl.v b/gbe/cores/pll_200_200_125_100/pll_200_200_125_100_tmpl.v
new file mode 100644 (file)
index 0000000..b457271
--- /dev/null
+++ b/gbe/cores/pll_200_200_125_100/pll_200_200_125_100_tmpl.v
@@ -0,0 +1,4 @@
+//Verilog instantiation template
+
+pll_200_200_125_100 _inst (.pll_200_125_100_CLKI(), .pll_200_125_100_CLKOP(), 
+            .pll_200_125_100_CLKOS(), .pll_200_125_100_CLKOS2(), .pll_200_125_100_LOCK());
\ No newline at end of file

diff --git a/gbe/cores/sgmii/PCSD/PCSD.cmd b/gbe/cores/sgmii/PCSD/PCSD.cmd
new file mode 100644 (file)
index 0000000..3271b96
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/PCSD.cmd
@@ -0,0 +1,18 @@
+PROJECT: PCSD
+               working_path: "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results"
+               module: PCSD
+               verilog_file_list: "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd" "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v"
+               vlog_std_v2001: true
+               constraint_file_name: "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc"
+               suffix_name: edn
+               output_file_name: PCSD
+               write_prf: true
+               disable_io_insertion: true
+               force_gsr: false
+               frequency: 100
+               fanout_limit: 50
+               retiming: false
+               pipe: false
+               part: LFE5UM-85F
+               speed_grade: 8
+               

diff --git a/gbe/cores/sgmii/PCSD/PCSD.cst b/gbe/cores/sgmii/PCSD/PCSD.cst
new file mode 100644 (file)
index 0000000..d8a88c1
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/PCSD.cst
@@ -0,0 +1,3 @@
+Date=04/29/2019
+Time=14:57:43
+

diff --git a/gbe/cores/sgmii/PCSD/PCSD.fdc b/gbe/cores/sgmii/PCSD/PCSD.fdc
new file mode 100644 (file)
index 0000000..c667056
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/PCSD.fdc
@@ -0,0 +1,3 @@
+###==== Start Generation
+
+define_attribute  {i:Lane0} {loc} {DCU0_CH1}

diff --git a/gbe/cores/sgmii/PCSD/PCSD.lpc b/gbe/cores/sgmii/PCSD/PCSD.lpc
new file mode 100644 (file)
index 0000000..5b775f6
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/PCSD.lpc
@@ -0,0 +1,97 @@
+[Device]
+Family=ecp5um
+OperatingCondition=COM
+Package=CABGA756
+PartName=LFE5UM-85F-8BG756C
+PartType=LFE5UM-85F
+SpeedGrade=8
+Status=P
+[IP]
+CoreName=PCS
+CoreRevision=8.2
+CoreStatus=Demo
+CoreType=LPM
+Date=04/29/2019
+ModuleName=PCSD
+ParameterFileVersion=1.0
+SourceFormat=vhdl
+Time=14:57:43
+VendorName=Lattice Semiconductor Corporation
+[Parameters]
+;ACHARA=0 00H
+;ACHARB=0 00H
+;ACHARM=0 00H
+;RXMCAENABLE=Disabled
+CDRLOLACTION=Full Recalibration
+CDRLOLRANGE=0
+CDR_MAX_RATE=1.25
+CDR_MULT=10X
+CDR_REF_RATE=125.0000
+CH_MODE=Rx and Tx
+Destination=Synplicity
+EDIF=1
+Expression=BusA(0 to 7)
+IO=0
+IO_TYPE=GbE
+LEQ=0
+LOOPBACK=Disabled
+LOSPORT=Enabled
+NUM_CHS=1
+Order=Big Endian [MSB:LSB]
+PPORT_RX_RDY=Disabled
+PPORT_TX_RDY=Disabled
+PROTOCOL=GbE
+PWAIT_RX_RDY=3000
+PWAIT_TX_RDY=3000
+RCSRC=Disabled
+REFCLK_RATE=125.0000
+RSTSEQSEL=Enabled
+RX8B10B=Enabled
+RXCOMMAA=1010000011
+RXCOMMAB=0101111100
+RXCOMMAM=1111111111
+RXCOUPLING=AC
+RXCTC=Enabled
+RXCTCBYTEN=0 00H
+RXCTCBYTEN1=0 00H
+RXCTCBYTEN2=1 BCH
+RXCTCBYTEN3=0 50H
+RXCTCMATCHPATTERN=M2-S2
+RXDIFFTERM=50 ohms
+RXFIFO_ENABLE=Enabled
+RXINVPOL=Non-invert
+RXLDR=Off
+RXLOSTHRESHOLD=2
+RXLSM=Enabled
+RXSC=K28P5
+RXWA=Barrel Shift
+RX_DATA_WIDTH=8/10-Bit
+RX_FICLK_RATE=125.0000
+RX_LINE_RATE=1.2500
+RX_RATE_DIV=Full Rate
+SCIPORT=Disabled
+SOFTLOL=Disabled
+TX8B10B=Enabled
+TXAMPLITUDE=1100
+TXDEPOST=Disabled
+TXDEPRE=Disabled
+TXDIFFTERM=50 ohms
+TXFIFO_ENABLE=Enabled
+TXINVPOL=Non-invert
+TXLDR=Off
+TXPLLLOLTHRESHOLD=0
+TXPLLMULT=10X
+TX_DATA_WIDTH=8/10-Bit
+TX_FICLK_RATE=125.0000
+TX_LINE_RATE=1.2500
+TX_MAX_RATE=1.25
+TX_RATE_DIV=Full Rate
+VHDL=1
+Verilog=0
+[FilesGenerated]
+PCSD.pp=pp
+PCSD.sym=sym
+PCSD.tft=tft
+PCSD.txt=pcs_module
+[SYSTEMPNR]
+LN0=DCU0_CH1

diff --git a/gbe/cores/sgmii/PCSD/PCSD.ngd b/gbe/cores/sgmii/PCSD/PCSD.ngd
new file mode 100644 (file)
index 0000000..29ceb75
Binary files /dev/null and b/gbe/cores/sgmii/PCSD/PCSD.ngd differ

diff --git a/gbe/cores/sgmii/PCSD/PCSD.ngo b/gbe/cores/sgmii/PCSD/PCSD.ngo
new file mode 100644 (file)
index 0000000..161655b
Binary files /dev/null and b/gbe/cores/sgmii/PCSD/PCSD.ngo differ

diff --git a/gbe/cores/sgmii/PCSD/PCSD.vhd b/gbe/cores/sgmii/PCSD/PCSD.vhd
new file mode 100644 (file)
index 0000000..f76fbb9
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/PCSD.vhd
@@ -0,0 +1,390 @@
+
+--
+-- Verific VHDL Description of module DCUA
+--
+
+-- DCUA is a black-box. Cannot print a valid VHDL entity description for it
+
+--
+-- Verific VHDL Description of module PCSDrsl_core
+--
+
+-- PCSDrsl_core is a black-box. Cannot print a valid VHDL entity description for it
+
+--
+-- Verific VHDL Description of module PCSD
+--
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+library ecp5um ;
+use ecp5um.components.all ;
+
+entity PCSD is
+    port (hdoutp: out std_logic;
+        hdoutn: out std_logic;
+        hdinp: in std_logic;
+        hdinn: in std_logic;
+        rxrefclk: in std_logic;
+        tx_pclk: out std_logic;
+        txi_clk: in std_logic;
+        txdata: in std_logic_vector(7 downto 0);
+        tx_k: in std_logic_vector(0 downto 0);
+        xmit: in std_logic_vector(0 downto 0);
+        tx_disp_correct: in std_logic_vector(0 downto 0);
+        rxdata: out std_logic_vector(7 downto 0);
+        rx_k: out std_logic_vector(0 downto 0);
+        rx_disp_err: out std_logic_vector(0 downto 0);
+        rx_cv_err: out std_logic_vector(0 downto 0);
+        signal_detect_c: in std_logic;
+        rx_los_low_s: out std_logic;
+        lsm_status_s: out std_logic;
+        ctc_urun_s: out std_logic;
+        ctc_orun_s: out std_logic;
+        rx_cdr_lol_s: out std_logic;
+        ctc_ins_s: out std_logic;
+        ctc_del_s: out std_logic;
+        tx_pwrup_c: in std_logic;
+        rx_pwrup_c: in std_logic;
+        serdes_pdb: in std_logic;
+        pll_refclki: in std_logic;
+        rsl_disable: in std_logic;
+        rsl_rst: in std_logic;
+        serdes_rst_dual_c: in std_logic;
+        rst_dual_c: in std_logic;
+        tx_serdes_rst_c: in std_logic;
+        tx_pcs_rst_c: in std_logic;
+        pll_lol: in std_logic;
+        rx_serdes_rst_c: in std_logic;
+        rx_pcs_rst_c: in std_logic
+    );
+    
+end entity PCSD;
+
+architecture v1 of PCSD is 
+    component PCSDrsl_core is
+        generic (pnum_channels: integer := 1;
+            pprotocol: string := "GBE";
+            pserdes_mode: string := "RX AND TX";
+            pport_tx_rdy: string := "DISABLED";
+            pwait_tx_rdy: integer := 3000;
+            pport_rx_rdy: string := "DISABLED";
+            pwait_rx_rdy: integer := 3000);
+        port (rui_rst: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(132)
+            rui_serdes_rst_dual_c: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(133)
+            rui_rst_dual_c: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(134)
+            rui_rsl_disable: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(135)
+            rui_tx_ref_clk: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(137)
+            rui_tx_serdes_rst_c: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(138)
+            rui_tx_pcs_rst_c: in std_logic_vector(3 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(139)
+            rdi_pll_lol: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(140)
+            rui_rx_ref_clk: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(142)
+            rui_rx_serdes_rst_c: in std_logic_vector(3 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(143)
+            rui_rx_pcs_rst_c: in std_logic_vector(3 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(144)
+            rdi_rx_los_low_s: in std_logic_vector(3 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(145)
+            rdi_rx_cdr_lol_s: in std_logic_vector(3 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(146)
+            rdo_serdes_rst_dual_c: out std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(149)
+            rdo_rst_dual_c: out std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(150)
+            ruo_tx_rdy: out std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(152)
+            rdo_tx_serdes_rst_c: out std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(153)
+            rdo_tx_pcs_rst_c: out std_logic_vector(3 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(154)
+            ruo_rx_rdy: out std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(156)
+            rdo_rx_serdes_rst_c: out std_logic_vector(3 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(157)
+            rdo_rx_pcs_rst_c: out std_logic_vector(3 downto 0)   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(158)
+        );
+        
+    end component PCSDrsl_core; -- syn_black_box=1    -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(88)
+    signal n45,n44,n1,n2,n3,n4,tx_pclk_c,n5,n6,n7,n8,n9,n10,n11,
+        n12,n13,rx_los_low_s_c,n14,n15,rx_cdr_lol_s_c,rsl_tx_pcs_rst_c,
+        rsl_rx_pcs_rst_c,rsl_rx_serdes_rst_c,rsl_rst_dual_c,rsl_serdes_rst_dual_c,
+        rsl_tx_serdes_rst_c,n16,n17,n18,n19,n20,n21,n22,n23,n24,n25,
+        n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37,n38,n39,
+        n40,n41,n42,n43,n46,n112,n111,n47,n48,n49,n50,n51,n52,n53,
+        n54,n55,n56,n57,n58,n59,n60,n61,n62,n63,n64,n65,n66,n67,
+        n68,n69,n70,n71,n72,n73,n74,n75,n76,n77,n78,n79,n80,n81,
+        n82,n83,n84,n85,n86,n87,n88,n89,n90,n91,n92,n93,n94,n95,
+        n96,n97,n98,n99,n100,n101,n102,n103,n104,n105,n106,n107,
+        n108,n109,n110,n121,n120,n119,gnd,pwr,n122,n123,n124,n125,
+        n126,n127,n128,n129,n130,n131,\_Z\ : std_logic; 
+    attribute LOC : string;
+    attribute LOC of DCU0_inst : label is "DCU0";
+    attribute CHAN : string;
+    attribute CHAN of DCU0_inst : label is "CH1";
+begin
+    tx_pclk <= tx_pclk_c;
+    rx_los_low_s <= rx_los_low_s_c;
+    rx_cdr_lol_s <= rx_cdr_lol_s_c;
+    DCU0_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1",
+        D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0",
+        D_CDR_LOL_SET=>"0b00",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1",
+        D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1",
+        D_SYNC_ND_EN=>"0b0",CH1_UC_MODE=>"0b0",CH1_PCIE_MODE=>"0b0",CH1_RIO_MODE=>"0b0",
+        CH1_WA_MODE=>"0b0",CH1_INVERT_RX=>"0b0",CH1_INVERT_TX=>"0b0",CH1_PRBS_SELECTION=>"0b0",
+        CH1_GE_AN_ENABLE=>"0b0",CH1_PRBS_LOCK=>"0b0",CH1_PRBS_ENABLE=>"0b0",
+        CH1_ENABLE_CG_ALIGN=>"0b1",CH1_TX_GEAR_MODE=>"0b0",CH1_RX_GEAR_MODE=>"0b0",
+        CH1_PCS_DET_TIME_SEL=>"0b00",CH1_PCIE_EI_EN=>"0b0",CH1_TX_GEAR_BYPASS=>"0b0",
+        CH1_ENC_BYPASS=>"0b0",CH1_SB_BYPASS=>"0b0",CH1_RX_SB_BYPASS=>"0b0",
+        CH1_WA_BYPASS=>"0b0",CH1_DEC_BYPASS=>"0b0",CH1_CTC_BYPASS=>"0b0",
+        CH1_RX_GEAR_BYPASS=>"0b0",CH1_LSM_DISABLE=>"0b0",CH1_MATCH_2_ENABLE=>"0b1",
+        CH1_MATCH_4_ENABLE=>"0b0",CH1_MIN_IPG_CNT=>"0b11",CH1_CC_MATCH_1=>"0x000",
+        CH1_CC_MATCH_2=>"0x000",CH1_CC_MATCH_3=>"0x1BC",CH1_CC_MATCH_4=>"0x050",
+        CH1_UDF_COMMA_MASK=>"0x3ff",CH1_UDF_COMMA_A=>"0x283",CH1_UDF_COMMA_B=>"0x17C",
+        CH1_RX_DCO_CK_DIV=>"0b010",CH1_RCV_DCC_EN=>"0b0",CH1_TPWDNB=>"0b1",
+        CH1_RATE_MODE_TX=>"0b0",CH1_RTERM_TX=>"0d19",CH1_TX_CM_SEL=>"0b00",
+        CH1_TDRV_PRE_EN=>"0b0",CH1_TDRV_SLICE0_SEL=>"0b01",CH1_TDRV_SLICE1_SEL=>"0b00",
+        CH1_TDRV_SLICE2_SEL=>"0b01",CH1_TDRV_SLICE3_SEL=>"0b01",CH1_TDRV_SLICE4_SEL=>"0b01",
+        CH1_TDRV_SLICE5_SEL=>"0b01",CH1_TDRV_SLICE0_CUR=>"0b101",CH1_TDRV_SLICE1_CUR=>"0b000",
+        CH1_TDRV_SLICE2_CUR=>"0b11",CH1_TDRV_SLICE3_CUR=>"0b11",CH1_TDRV_SLICE4_CUR=>"0b11",
+        CH1_TDRV_SLICE5_CUR=>"0b00",CH1_TDRV_DAT_SEL=>"0b00",CH1_TX_DIV11_SEL=>"0b0",
+        CH1_RPWDNB=>"0b1",CH1_RATE_MODE_RX=>"0b0",CH1_RX_DIV11_SEL=>"0b0",
+        CH1_SEL_SD_RX_CLK=>"0b0",CH1_FF_RX_H_CLK_EN=>"0b0",CH1_FF_RX_F_CLK_DIS=>"0b0",
+        CH1_FF_TX_H_CLK_EN=>"0b0",CH1_FF_TX_F_CLK_DIS=>"0b0",CH1_TDRV_POST_EN=>"0b0",
+        CH1_TX_POST_SIGN=>"0b0",CH1_TX_PRE_SIGN=>"0b0",CH1_REQ_LVL_SET=>"0b00",
+        CH1_REQ_EN=>"0b1",CH1_RTERM_RX=>"0d22",CH1_RXTERM_CM=>"0b11",CH1_PDEN_SEL=>"0b1",
+        CH1_RXIN_CM=>"0b11",CH1_LEQ_OFFSET_SEL=>"0b0",CH1_LEQ_OFFSET_TRIM=>"0b000",
+        CH1_RLOS_SEL=>"0b1",CH1_RX_LOS_LVL=>"0b010",CH1_RX_LOS_CEQ=>"0b11",
+        CH1_RX_LOS_HYST_EN=>"0b0",CH1_RX_LOS_EN=>"0b1",CH1_LDR_RX2CORE_SEL=>"0b0",
+        CH1_LDR_CORE2TX_SEL=>"0b0",D_TX_MAX_RATE=>"1.25",CH1_CDR_MAX_RATE=>"1.25",
+        CH1_TXAMPLITUDE=>"0d1100",CH1_TXDEPRE=>"DISABLED",CH1_TXDEPOST=>"DISABLED",
+        CH1_PROTOCOL=>"GBE",D_ISETLOS=>"0d0",D_SETIRPOLY_AUX=>"0b00",D_SETICONST_AUX=>"0b00",
+        D_SETIRPOLY_CH=>"0b00",D_SETICONST_CH=>"0b00",D_REQ_ISET=>"0b000",
+        D_PD_ISET=>"0b00",D_DCO_CALIB_TIME_SEL=>"0b00",CH1_CDR_CNT4SEL=>"0b00",
+        CH1_CDR_CNT8SEL=>"0b00",CH1_DCOATDCFG=>"0b00",CH1_DCOATDDLY=>"0b00",
+        CH1_DCOBYPSATD=>"0b1",CH1_DCOCALDIV=>"0b001",CH1_DCOCTLGI=>"0b010",
+        CH1_DCODISBDAVOID=>"0b0",CH1_DCOFLTDAC=>"0b01",CH1_DCOFTNRG=>"0b110",
+        CH1_DCOIOSTUNE=>"0b000",CH1_DCOITUNE=>"0b00",CH1_DCOITUNE4LSB=>"0b111",
+        CH1_DCOIUPDNX2=>"0b1",CH1_DCONUOFLSB=>"0b101",CH1_DCOSCALEI=>"0b00",
+        CH1_DCOSTARTVAL=>"0b000",CH1_DCOSTEP=>"0b00",CH1_BAND_THRESHOLD=>"0d0",
+        CH1_AUTO_FACQ_EN=>"0b1",CH1_AUTO_CALIB_EN=>"0b1",CH1_CALIB_CK_MODE=>"0b0",
+        CH1_REG_BAND_OFFSET=>"0d0",CH1_REG_BAND_SEL=>"0d0",CH1_REG_IDAC_SEL=>"0d0",
+        CH1_REG_IDAC_EN=>"0b0",D_CMUSETISCL4VCO=>"0b000",D_CMUSETI4VCO=>"0b00",
+        D_CMUSETINITVCT=>"0b00",D_CMUSETZGM=>"0b000",D_CMUSETP2AGM=>"0b000",
+        D_CMUSETP1GM=>"0b000",D_CMUSETI4CPZ=>"0d3",D_CMUSETI4CPP=>"0d3",D_CMUSETICP4Z=>"0b101",
+        D_CMUSETICP4P=>"0b01",D_CMUSETBIASI=>"0b00",D_SETPLLRC=>"0d1",CH1_RX_RATE_SEL=>"0d8",
+        D_REFCK_MODE=>"0b001",D_TX_VCO_CK_DIV=>"0b010",D_PLL_LOL_SET=>"0b00",
+        D_RG_EN=>"0b0",D_RG_SET=>"0b00")
+     port map (CH0_HDINP=>n112,CH1_HDINP=>hdinp,CH0_HDINN=>n112,CH1_HDINN=>hdinn,
+    D_TXBIT_CLKP_FROM_ND=>n44,D_TXBIT_CLKN_FROM_ND=>n44,D_SYNC_ND=>n44,D_TXPLL_LOL_FROM_ND=>n44,
+    CH0_RX_REFCLK=>n112,CH1_RX_REFCLK=>rxrefclk,CH0_FF_RXI_CLK=>n111,CH1_FF_RXI_CLK=>tx_pclk_c,
+    CH0_FF_TXI_CLK=>n111,CH1_FF_TXI_CLK=>txi_clk,CH0_FF_EBRD_CLK=>n111,CH1_FF_EBRD_CLK=>tx_pclk_c,
+    CH0_FF_TX_D_0=>n112,CH1_FF_TX_D_0=>txdata(0),CH0_FF_TX_D_1=>n112,CH1_FF_TX_D_1=>txdata(1),
+    CH0_FF_TX_D_2=>n112,CH1_FF_TX_D_2=>txdata(2),CH0_FF_TX_D_3=>n112,CH1_FF_TX_D_3=>txdata(3),
+    CH0_FF_TX_D_4=>n112,CH1_FF_TX_D_4=>txdata(4),CH0_FF_TX_D_5=>n112,CH1_FF_TX_D_5=>txdata(5),
+    CH0_FF_TX_D_6=>n112,CH1_FF_TX_D_6=>txdata(6),CH0_FF_TX_D_7=>n112,CH1_FF_TX_D_7=>txdata(7),
+    CH0_FF_TX_D_8=>n112,CH1_FF_TX_D_8=>tx_k(0),CH0_FF_TX_D_9=>n112,CH1_FF_TX_D_9=>n44,
+    CH0_FF_TX_D_10=>n112,CH1_FF_TX_D_10=>xmit(0),CH0_FF_TX_D_11=>n112,CH1_FF_TX_D_11=>tx_disp_correct(0),
+    CH0_FF_TX_D_12=>n112,CH1_FF_TX_D_12=>n112,CH0_FF_TX_D_13=>n112,CH1_FF_TX_D_13=>n112,
+    CH0_FF_TX_D_14=>n112,CH1_FF_TX_D_14=>n112,CH0_FF_TX_D_15=>n112,CH1_FF_TX_D_15=>n112,
+    CH0_FF_TX_D_16=>n112,CH1_FF_TX_D_16=>n112,CH0_FF_TX_D_17=>n112,CH1_FF_TX_D_17=>n112,
+    CH0_FF_TX_D_18=>n112,CH1_FF_TX_D_18=>n112,CH0_FF_TX_D_19=>n112,CH1_FF_TX_D_19=>n112,
+    CH0_FF_TX_D_20=>n112,CH1_FF_TX_D_20=>n112,CH0_FF_TX_D_21=>n112,CH1_FF_TX_D_21=>n44,
+    CH0_FF_TX_D_22=>n112,CH1_FF_TX_D_22=>n112,CH0_FF_TX_D_23=>n112,CH1_FF_TX_D_23=>n112,
+    CH0_FFC_EI_EN=>n112,CH1_FFC_EI_EN=>n44,CH0_FFC_PCIE_DET_EN=>n112,CH1_FFC_PCIE_DET_EN=>n44,
+    CH0_FFC_PCIE_CT=>n112,CH1_FFC_PCIE_CT=>n44,CH0_FFC_SB_INV_RX=>n112,CH1_FFC_SB_INV_RX=>n112,
+    CH0_FFC_ENABLE_CGALIGN=>n112,CH1_FFC_ENABLE_CGALIGN=>n112,CH0_FFC_SIGNAL_DETECT=>n112,
+    CH1_FFC_SIGNAL_DETECT=>signal_detect_c,CH0_FFC_FB_LOOPBACK=>n112,CH1_FFC_FB_LOOPBACK=>n44,
+    CH0_FFC_SB_PFIFO_LP=>n112,CH1_FFC_SB_PFIFO_LP=>n44,CH0_FFC_PFIFO_CLR=>n112,
+    CH1_FFC_PFIFO_CLR=>n44,CH0_FFC_RATE_MODE_RX=>n112,CH1_FFC_RATE_MODE_RX=>n44,
+    CH0_FFC_RATE_MODE_TX=>n112,CH1_FFC_RATE_MODE_TX=>n44,CH0_FFC_DIV11_MODE_RX=>n112,
+    CH1_FFC_DIV11_MODE_RX=>n44,CH0_FFC_DIV11_MODE_TX=>n112,CH1_FFC_DIV11_MODE_TX=>n44,
+    CH0_FFC_RX_GEAR_MODE=>n112,CH1_FFC_RX_GEAR_MODE=>n44,CH0_FFC_TX_GEAR_MODE=>n112,
+    CH1_FFC_TX_GEAR_MODE=>n44,CH0_FFC_LDR_CORE2TX_EN=>n112,CH1_FFC_LDR_CORE2TX_EN=>n112,
+    CH0_FFC_LANE_TX_RST=>n112,CH1_FFC_LANE_TX_RST=>rsl_tx_pcs_rst_c,CH0_FFC_LANE_RX_RST=>n112,
+    CH1_FFC_LANE_RX_RST=>rsl_rx_pcs_rst_c,CH0_FFC_RRST=>n112,CH1_FFC_RRST=>rsl_rx_serdes_rst_c,
+    CH0_FFC_TXPWDNB=>n112,CH1_FFC_TXPWDNB=>tx_pwrup_c,CH0_FFC_RXPWDNB=>n112,
+    CH1_FFC_RXPWDNB=>rx_pwrup_c,CH0_LDR_CORE2TX=>n112,CH1_LDR_CORE2TX=>n112,
+    D_SCIWDATA0=>n112,D_SCIWDATA1=>n112,D_SCIWDATA2=>n112,D_SCIWDATA3=>n112,
+    D_SCIWDATA4=>n112,D_SCIWDATA5=>n112,D_SCIWDATA6=>n112,D_SCIWDATA7=>n112,
+    D_SCIADDR0=>n112,D_SCIADDR1=>n112,D_SCIADDR2=>n112,D_SCIADDR3=>n112,
+    D_SCIADDR4=>n112,D_SCIADDR5=>n112,D_SCIENAUX=>n112,D_SCISELAUX=>n112,
+    CH0_SCIEN=>n112,CH1_SCIEN=>n112,CH0_SCISEL=>n112,CH1_SCISEL=>n112,D_SCIRD=>n112,
+    D_SCIWSTN=>n112,D_CYAWSTN=>n112,D_FFC_SYNC_TOGGLE=>n112,D_FFC_DUAL_RST=>rsl_rst_dual_c,
+    D_FFC_MACRO_RST=>rsl_serdes_rst_dual_c,D_FFC_MACROPDB=>serdes_pdb,D_FFC_TRST=>rsl_tx_serdes_rst_c,
+    CH0_FFC_CDR_EN_BITSLIP=>n112,CH1_FFC_CDR_EN_BITSLIP=>n44,D_SCAN_ENABLE=>n44,
+    D_SCAN_IN_0=>n44,D_SCAN_IN_1=>n44,D_SCAN_IN_2=>n44,D_SCAN_IN_3=>n44,
+    D_SCAN_IN_4=>n44,D_SCAN_IN_5=>n44,D_SCAN_IN_6=>n44,D_SCAN_IN_7=>n44,
+    D_SCAN_MODE=>n44,D_SCAN_RESET=>n44,D_CIN0=>n44,D_CIN1=>n44,D_CIN2=>n44,
+    D_CIN3=>n44,D_CIN4=>n44,D_CIN5=>n44,D_CIN6=>n44,D_CIN7=>n44,D_CIN8=>n44,
+    D_CIN9=>n44,D_CIN10=>n44,D_CIN11=>n44,CH0_HDOUTP=>n47,CH1_HDOUTP=>hdoutp,
+    CH0_HDOUTN=>n48,CH1_HDOUTN=>hdoutn,D_TXBIT_CLKP_TO_ND=>n1,D_TXBIT_CLKN_TO_ND=>n2,
+    D_SYNC_PULSE2ND=>n3,D_TXPLL_LOL_TO_ND=>n4,CH0_FF_RX_F_CLK=>n49,CH1_FF_RX_F_CLK=>n5,
+    CH0_FF_RX_H_CLK=>n50,CH1_FF_RX_H_CLK=>n6,CH0_FF_TX_F_CLK=>n51,CH1_FF_TX_F_CLK=>n7,
+    CH0_FF_TX_H_CLK=>n52,CH1_FF_TX_H_CLK=>n8,CH0_FF_RX_PCLK=>n53,CH1_FF_RX_PCLK=>n9,
+    CH0_FF_TX_PCLK=>n54,CH1_FF_TX_PCLK=>tx_pclk_c,CH0_FF_RX_D_0=>n55,CH1_FF_RX_D_0=>rxdata(0),
+    CH0_FF_RX_D_1=>n56,CH1_FF_RX_D_1=>rxdata(1),CH0_FF_RX_D_2=>n57,CH1_FF_RX_D_2=>rxdata(2),
+    CH0_FF_RX_D_3=>n58,CH1_FF_RX_D_3=>rxdata(3),CH0_FF_RX_D_4=>n59,CH1_FF_RX_D_4=>rxdata(4),
+    CH0_FF_RX_D_5=>n60,CH1_FF_RX_D_5=>rxdata(5),CH0_FF_RX_D_6=>n61,CH1_FF_RX_D_6=>rxdata(6),
+    CH0_FF_RX_D_7=>n62,CH1_FF_RX_D_7=>rxdata(7),CH0_FF_RX_D_8=>n63,CH1_FF_RX_D_8=>rx_k(0),
+    CH0_FF_RX_D_9=>n64,CH1_FF_RX_D_9=>rx_disp_err(0),CH0_FF_RX_D_10=>n65,
+    CH1_FF_RX_D_10=>rx_cv_err(0),CH0_FF_RX_D_11=>n66,CH1_FF_RX_D_11=>n10,
+    CH0_FF_RX_D_12=>n67,CH1_FF_RX_D_12=>n68,CH0_FF_RX_D_13=>n69,CH1_FF_RX_D_13=>n70,
+    CH0_FF_RX_D_14=>n71,CH1_FF_RX_D_14=>n72,CH0_FF_RX_D_15=>n73,CH1_FF_RX_D_15=>n74,
+    CH0_FF_RX_D_16=>n75,CH1_FF_RX_D_16=>n76,CH0_FF_RX_D_17=>n77,CH1_FF_RX_D_17=>n78,
+    CH0_FF_RX_D_18=>n79,CH1_FF_RX_D_18=>n80,CH0_FF_RX_D_19=>n81,CH1_FF_RX_D_19=>n82,
+    CH0_FF_RX_D_20=>n83,CH1_FF_RX_D_20=>n84,CH0_FF_RX_D_21=>n85,CH1_FF_RX_D_21=>n86,
+    CH0_FF_RX_D_22=>n87,CH1_FF_RX_D_22=>n88,CH0_FF_RX_D_23=>n89,CH1_FF_RX_D_23=>n11,
+    CH0_FFS_PCIE_DONE=>n90,CH1_FFS_PCIE_DONE=>n12,CH0_FFS_PCIE_CON=>n91,CH1_FFS_PCIE_CON=>n13,
+    CH0_FFS_RLOS=>n92,CH1_FFS_RLOS=>rx_los_low_s_c,CH0_FFS_LS_SYNC_STATUS=>n93,
+    CH1_FFS_LS_SYNC_STATUS=>lsm_status_s,CH0_FFS_CC_UNDERRUN=>n94,CH1_FFS_CC_UNDERRUN=>ctc_urun_s,
+    CH0_FFS_CC_OVERRUN=>n95,CH1_FFS_CC_OVERRUN=>ctc_orun_s,CH0_FFS_RXFBFIFO_ERROR=>n96,
+    CH1_FFS_RXFBFIFO_ERROR=>n14,CH0_FFS_TXFBFIFO_ERROR=>n97,CH1_FFS_TXFBFIFO_ERROR=>n15,
+    CH0_FFS_RLOL=>n98,CH1_FFS_RLOL=>rx_cdr_lol_s_c,CH0_FFS_SKP_ADDED=>n99,
+    CH1_FFS_SKP_ADDED=>ctc_ins_s,CH0_FFS_SKP_DELETED=>n100,CH1_FFS_SKP_DELETED=>ctc_del_s,
+    CH0_LDR_RX2CORE=>n101,CH1_LDR_RX2CORE=>n102,D_SCIRDATA0=>n103,D_SCIRDATA1=>n104,
+    D_SCIRDATA2=>n105,D_SCIRDATA3=>n106,D_SCIRDATA4=>n107,D_SCIRDATA5=>n108,
+    D_SCIRDATA6=>n109,D_SCIRDATA7=>n110,D_SCIINT=>n121,D_SCAN_OUT_0=>n16,
+    D_SCAN_OUT_1=>n17,D_SCAN_OUT_2=>n18,D_SCAN_OUT_3=>n19,D_SCAN_OUT_4=>n20,
+    D_SCAN_OUT_5=>n21,D_SCAN_OUT_6=>n22,D_SCAN_OUT_7=>n23,D_COUT0=>n24,D_COUT1=>n25,
+    D_COUT2=>n26,D_COUT3=>n27,D_COUT4=>n28,D_COUT5=>n29,D_COUT6=>n30,D_COUT7=>n31,
+    D_COUT8=>n32,D_COUT9=>n33,D_COUT10=>n34,D_COUT11=>n35,D_COUT12=>n36,
+    D_COUT13=>n37,D_COUT14=>n38,D_COUT15=>n39,D_COUT16=>n40,D_COUT17=>n41,
+    D_COUT18=>n42,D_COUT19=>n43,D_REFCLKI=>pll_refclki,D_FFS_PLOL=>n46);
+    n45 <= '1' ;
+    n44 <= '0' ;
+    n1 <= 'Z' ;
+    n2 <= 'Z' ;
+    n3 <= 'Z' ;
+    n4 <= 'Z' ;
+    n5 <= 'Z' ;
+    n6 <= 'Z' ;
+    n7 <= 'Z' ;
+    n8 <= 'Z' ;
+    n9 <= 'Z' ;
+    n10 <= 'Z' ;
+    n11 <= 'Z' ;
+    n12 <= 'Z' ;
+    n13 <= 'Z' ;
+    n14 <= 'Z' ;
+    n15 <= 'Z' ;
+    n16 <= 'Z' ;
+    n17 <= 'Z' ;
+    n18 <= 'Z' ;
+    n19 <= 'Z' ;
+    n20 <= 'Z' ;
+    n21 <= 'Z' ;
+    n22 <= 'Z' ;
+    n23 <= 'Z' ;
+    n24 <= 'Z' ;
+    n25 <= 'Z' ;
+    n26 <= 'Z' ;
+    n27 <= 'Z' ;
+    n28 <= 'Z' ;
+    n29 <= 'Z' ;
+    n30 <= 'Z' ;
+    n31 <= 'Z' ;
+    n32 <= 'Z' ;
+    n33 <= 'Z' ;
+    n34 <= 'Z' ;
+    n35 <= 'Z' ;
+    n36 <= 'Z' ;
+    n37 <= 'Z' ;
+    n38 <= 'Z' ;
+    n39 <= 'Z' ;
+    n40 <= 'Z' ;
+    n41 <= 'Z' ;
+    n42 <= 'Z' ;
+    n43 <= 'Z' ;
+    n46 <= 'Z' ;
+    n112 <= '0' ;
+    n111 <= '1' ;
+    n47 <= 'Z' ;
+    n48 <= 'Z' ;
+    n49 <= 'Z' ;
+    n50 <= 'Z' ;
+    n51 <= 'Z' ;
+    n52 <= 'Z' ;
+    n53 <= 'Z' ;
+    n54 <= 'Z' ;
+    n55 <= 'Z' ;
+    n56 <= 'Z' ;
+    n57 <= 'Z' ;
+    n58 <= 'Z' ;
+    n59 <= 'Z' ;
+    n60 <= 'Z' ;
+    n61 <= 'Z' ;
+    n62 <= 'Z' ;
+    n63 <= 'Z' ;
+    n64 <= 'Z' ;
+    n65 <= 'Z' ;
+    n66 <= 'Z' ;
+    n67 <= 'Z' ;
+    n68 <= 'Z' ;
+    n69 <= 'Z' ;
+    n70 <= 'Z' ;
+    n71 <= 'Z' ;
+    n72 <= 'Z' ;
+    n73 <= 'Z' ;
+    n74 <= 'Z' ;
+    n75 <= 'Z' ;
+    n76 <= 'Z' ;
+    n77 <= 'Z' ;
+    n78 <= 'Z' ;
+    n79 <= 'Z' ;
+    n80 <= 'Z' ;
+    n81 <= 'Z' ;
+    n82 <= 'Z' ;
+    n83 <= 'Z' ;
+    n84 <= 'Z' ;
+    n85 <= 'Z' ;
+    n86 <= 'Z' ;
+    n87 <= 'Z' ;
+    n88 <= 'Z' ;
+    n89 <= 'Z' ;
+    n90 <= 'Z' ;
+    n91 <= 'Z' ;
+    n92 <= 'Z' ;
+    n93 <= 'Z' ;
+    n94 <= 'Z' ;
+    n95 <= 'Z' ;
+    n96 <= 'Z' ;
+    n97 <= 'Z' ;
+    n98 <= 'Z' ;
+    n99 <= 'Z' ;
+    n100 <= 'Z' ;
+    n101 <= 'Z' ;
+    n102 <= 'Z' ;
+    n103 <= 'Z' ;
+    n104 <= 'Z' ;
+    n105 <= 'Z' ;
+    n106 <= 'Z' ;
+    n107 <= 'Z' ;
+    n108 <= 'Z' ;
+    n109 <= 'Z' ;
+    n110 <= 'Z' ;
+    n121 <= 'Z' ;
+    rsl_inst: component PCSDrsl_core port map (rui_rst=>rsl_rst,rui_serdes_rst_dual_c=>serdes_rst_dual_c,
+            rui_rst_dual_c=>rst_dual_c,rui_rsl_disable=>rsl_disable,rui_tx_ref_clk=>pll_refclki,
+            rui_tx_serdes_rst_c=>tx_serdes_rst_c,rui_tx_pcs_rst_c(3)=>gnd,
+            rui_tx_pcs_rst_c(2)=>gnd,rui_tx_pcs_rst_c(1)=>gnd,rui_tx_pcs_rst_c(0)=>tx_pcs_rst_c,
+            rdi_pll_lol=>pll_lol,rui_rx_ref_clk=>rxrefclk,rui_rx_serdes_rst_c(3)=>gnd,
+            rui_rx_serdes_rst_c(2)=>gnd,rui_rx_serdes_rst_c(1)=>gnd,rui_rx_serdes_rst_c(0)=>rx_serdes_rst_c,
+            rui_rx_pcs_rst_c(3)=>gnd,rui_rx_pcs_rst_c(2)=>gnd,rui_rx_pcs_rst_c(1)=>gnd,
+            rui_rx_pcs_rst_c(0)=>rx_pcs_rst_c,rdi_rx_los_low_s(3)=>gnd,rdi_rx_los_low_s(2)=>gnd,
+            rdi_rx_los_low_s(1)=>gnd,rdi_rx_los_low_s(0)=>rx_los_low_s_c,rdi_rx_cdr_lol_s(3)=>gnd,
+            rdi_rx_cdr_lol_s(2)=>gnd,rdi_rx_cdr_lol_s(1)=>gnd,rdi_rx_cdr_lol_s(0)=>rx_cdr_lol_s_c,
+            rdo_serdes_rst_dual_c=>rsl_serdes_rst_dual_c,rdo_rst_dual_c=>rsl_rst_dual_c,
+            ruo_tx_rdy=>n122,rdo_tx_serdes_rst_c=>rsl_tx_serdes_rst_c,rdo_tx_pcs_rst_c(3)=>n123,
+            rdo_tx_pcs_rst_c(2)=>n124,rdo_tx_pcs_rst_c(1)=>n125,rdo_tx_pcs_rst_c(0)=>rsl_tx_pcs_rst_c,
+            ruo_rx_rdy=>n126,rdo_rx_serdes_rst_c(3)=>n127,rdo_rx_serdes_rst_c(2)=>n128,
+            rdo_rx_serdes_rst_c(1)=>n129,rdo_rx_serdes_rst_c(0)=>rsl_rx_serdes_rst_c,
+            rdo_rx_pcs_rst_c(3)=>n130,rdo_rx_pcs_rst_c(2)=>n131,rdo_rx_pcs_rst_c(1)=>\_Z\,
+            rdo_rx_pcs_rst_c(0)=>rsl_rx_pcs_rst_c);
+    n120 <= '1' ;
+    n119 <= '0' ;
+    gnd <= '0' ;
+    pwr <= '1' ;
+    n122 <= 'Z' ;
+    n123 <= 'Z' ;
+    n124 <= 'Z' ;
+    n125 <= 'Z' ;
+    n126 <= 'Z' ;
+    n127 <= 'Z' ;
+    n128 <= 'Z' ;
+    n129 <= 'Z' ;
+    n130 <= 'Z' ;
+    n131 <= 'Z' ;
+    \_Z\ <= 'Z' ;
+    
+end architecture v1;
+

diff --git a/gbe/cores/sgmii/PCSD/PCSD_ngd.asd b/gbe/cores/sgmii/PCSD/PCSD_ngd.asd
new file mode 100644 (file)
index 0000000..c265c78
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/PCSD_ngd.asd
@@ -0,0 +1 @@
+[ActiveSupport NGD]

diff --git a/gbe/cores/sgmii/PCSD/PCSD_softlogic.v b/gbe/cores/sgmii/PCSD/PCSD_softlogic.v
new file mode 100644 (file)
index 0000000..fa4373f
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/PCSD_softlogic.v
@@ -0,0 +1,943 @@
+
+
+//   ===========================================================================
+//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
+//   ---------------------------------------------------------------------------
+//   Copyright (c) 2016 by Lattice Semiconductor Corporation
+//   ALL RIGHTS RESERVED
+//   ------------------------------------------------------------------
+//
+//   Permission:
+//
+//      Lattice SG Pte. Ltd. grants permission to use this code
+//      pursuant to the terms of the Lattice Reference Design License Agreement.
+//
+//
+//   Disclaimer:
+//
+//      This VHDL or Verilog source code is intended as a design reference
+//      which illustrates how these types of functions can be implemented.
+//      It is the user's responsibility to verify their design for
+//      consistency and functionality through the use of formal
+//      verification methods.  Lattice provides no warranty
+//      regarding the use or functionality of this code.
+//
+//   ---------------------------------------------------------------------------
+//
+//                  Lattice SG Pte. Ltd.
+//                  101 Thomson Road, United Square #07-02
+//                  Singapore 307591
+//
+//
+//                  TEL: 1-800-Lattice (USA and Canada)
+//                       +65-6631-2000 (Singapore)
+//                       +1-503-268-8001 (other locations)
+//
+//                  web: http://www.latticesemi.com/
+//                  email: techsupport@latticesemi.com
+//
+//   ---------------------------------------------------------------------------
+//
+// =============================================================================
+//                         FILE DETAILS
+// Project               : RSL- Reset Sequence Logic
+// File                  : rsl_core.v
+// Title                 : Top-level file for RSL
+// Dependencies          : 1.
+//                       : 2.
+// Description           :
+// =============================================================================
+//                        REVISION HISTORY
+// Version               : 1.0
+// Author(s)             : BM
+// Mod. Date             : October 28, 2013
+// Changes Made          : Initial Creation
+// -----------------------------------------------------------------------------
+// Version               : 1.1
+// Author(s)             : BM
+// Mod. Date             : November 06, 2013
+// Changes Made          : Tx/Rx separation, ready port code exclusion
+// -----------------------------------------------------------------------------
+// Version               : 1.2
+// Author(s)             : BM
+// Mod. Date             : June 13, 2014
+// Changes Made          : Updated Rx PCS reset method
+// -----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
+// Version               : 1.3
+// Author(s)             : UA
+// Mod. Date             : Dec 19, 2014
+// Changes Made          : Added new parameter fro PCIE
+// -----------------------------------------------------------------------------
+// Version               : 1.31
+// Author(s)             : BM/UM
+// Mod. Date             : Feb 23, 2016
+// Changes Made          : Behavior of rx_rdy output modified. The output rx_rdy
+//                         and the rx_rdy wait counter are reset to zero on
+//                         LOL or LOS. Reverted back the counter value change for PCIE.
+// -----------------------------------------------------------------------------
+// Version               : 1.4
+// Author(s)             : EB
+// Mod. Date:            : March 21, 2017
+// Changes Made          :
+// -----------------------------------------------------------------------------
+// Version               : 1.5
+// Author(s)             : ES
+// Mod. Date:            : May 8, 2017
+// Changes Made          : Implemented common RSL behaviour as proposed by BM.
+// =============================================================================
+
+`timescale 1ns/10ps
+
+module PCSDrsl_core (
+      // ------------ Inputs
+      // Common
+      rui_rst,               // Active high reset for the RSL module
+      rui_serdes_rst_dual_c, // SERDES macro reset user command
+      rui_rst_dual_c,        // PCS dual reset user command
+      rui_rsl_disable,       // Active high signal that disables all reset outputs of RSL
+      // Tx
+      rui_tx_ref_clk,        // Tx reference clock
+      rui_tx_serdes_rst_c,   // Tx SERDES reset user command
+      rui_tx_pcs_rst_c,      // Tx lane reset user command
+      rdi_pll_lol,           // Tx PLL Loss of Lock status input from the SERDES
+      // Rx
+      rui_rx_ref_clk,        // Rx reference clock
+      rui_rx_serdes_rst_c,   // SERDES Receive channel reset user command
+      rui_rx_pcs_rst_c,      // Rx lane reset user command
+      rdi_rx_los_low_s,      // Receive loss of signal status input from SERDES
+      rdi_rx_cdr_lol_s,      // Receive CDR loss of lock status input from SERDES
+
+      // ------------ Outputs
+      // Common
+      rdo_serdes_rst_dual_c, // SERDES macro reset command output
+      rdo_rst_dual_c,        // PCS dual reset command output
+      // Tx
+      ruo_tx_rdy,            // Tx lane ready status output
+      rdo_tx_serdes_rst_c,   // SERDES Tx reset command output
+      rdo_tx_pcs_rst_c,      // PCS Tx lane reset command output
+      // Rx
+      ruo_rx_rdy,            // Rx lane ready status output
+      rdo_rx_serdes_rst_c,   // SERDES Rx channel reset command output
+      rdo_rx_pcs_rst_c       // PCS Rx lane reset command output
+      );
+
+// ------------ Module parameters
+`ifdef NUM_CHANNELS
+   parameter pnum_channels = `NUM_CHANNELS;    // 1,2,4
+`else
+   parameter pnum_channels = 1;
+`endif
+
+`ifdef PCIE
+   parameter pprotocol    = "PCIE";
+`else
+   parameter pprotocol    = "";
+`endif
+
+`ifdef RX_ONLY
+   parameter pserdes_mode    = "RX ONLY";
+`else
+   `ifdef TX_ONLY
+      parameter pserdes_mode = "TX ONLY";
+   `else
+      parameter pserdes_mode = "RX AND TX";
+   `endif
+`endif
+
+`ifdef PORT_TX_RDY
+   parameter pport_tx_rdy = "ENABLED";
+`else
+   parameter pport_tx_rdy = "DISABLED";
+`endif
+
+`ifdef WAIT_TX_RDY
+   parameter pwait_tx_rdy = `WAIT_TX_RDY;
+`else
+   parameter pwait_tx_rdy = 3000;
+`endif
+
+`ifdef PORT_RX_RDY
+   parameter pport_rx_rdy = "ENABLED";
+`else
+   parameter pport_rx_rdy = "DISABLED";
+`endif
+
+`ifdef WAIT_RX_RDY
+   parameter pwait_rx_rdy = `WAIT_RX_RDY;
+`else
+   parameter pwait_rx_rdy = 3000;
+`endif
+
+// ------------ Local parameters
+   localparam wa_num_cycles      = 1024;
+   localparam dac_num_cycles     = 3;
+   localparam lreset_pwidth      = 3;      // reset pulse width-1, default=4-1=3
+   localparam lwait_b4_trst      = 781250; // 5ms wait with worst-case Fmax=156 MHz
+   localparam lwait_b4_trst_s    = 781;    // for simulation
+   localparam lplol_cnt_width    = 20;     // width for lwait_b4_trst
+   localparam lwait_after_plol0  = 4;
+   localparam lwait_b4_rrst      = 180224; // total calibration time
+   localparam lrrst_wait_width   = 20;
+   localparam lwait_after_rrst   = 800000; // For CPRI- unused
+   localparam lwait_b4_rrst_s    = 460;    // wait cycles provided by design team
+   localparam lrlol_cnt_width    = 19;     // width for lwait_b4_rrst
+   localparam lwait_after_lols   = (16384 * dac_num_cycles) + wa_num_cycles;  // 16384 cycles * dac_num_cycles + 1024 cycles
+   localparam lwait_after_lols_s = 150;    // wait cycles provided by design team
+   localparam llols_cnt_width    = 18;     // lols count width
+   localparam lrdb_max           = 15;     // maximum debounce count
+   localparam ltxr_wait_width    = 12;     // width of tx ready wait counter
+   localparam lrxr_wait_width    = 12;     // width of tx ready wait counter
+
+// ------------ input ports
+   input                         rui_rst;
+   input                         rui_serdes_rst_dual_c;
+   input                         rui_rst_dual_c;
+   input                         rui_rsl_disable;
+
+   input                         rui_tx_ref_clk;
+   input                         rui_tx_serdes_rst_c;
+   input  [3:0]                  rui_tx_pcs_rst_c;
+   input                         rdi_pll_lol;
+
+   input                         rui_rx_ref_clk;
+   input  [3:0]                  rui_rx_serdes_rst_c;
+   input  [3:0]                  rui_rx_pcs_rst_c;
+   input  [3:0]                  rdi_rx_los_low_s;
+   input  [3:0]                  rdi_rx_cdr_lol_s;
+
+// ------------ output ports
+   output                        rdo_serdes_rst_dual_c;
+   output                        rdo_rst_dual_c;
+
+   output                        ruo_tx_rdy;
+   output                        rdo_tx_serdes_rst_c;
+   output [3:0]                  rdo_tx_pcs_rst_c;
+
+   output                        ruo_rx_rdy;
+   output [3:0]                  rdo_rx_serdes_rst_c;
+   output [3:0]                  rdo_rx_pcs_rst_c;
+
+// ------------ Internal registers and wires
+   // inputs
+   wire                          rui_rst;
+   wire                          rui_serdes_rst_dual_c;
+   wire                          rui_rst_dual_c;
+   wire                          rui_rsl_disable;
+   wire                          rui_tx_ref_clk;
+   wire                          rui_tx_serdes_rst_c;
+   wire   [3:0]                  rui_tx_pcs_rst_c;
+   wire                          rdi_pll_lol;
+   wire                          rui_rx_ref_clk;
+   wire   [3:0]                  rui_rx_serdes_rst_c;
+   wire   [3:0]                  rui_rx_pcs_rst_c;
+   wire   [3:0]                  rdi_rx_los_low_s;
+   wire   [3:0]                  rdi_rx_cdr_lol_s;
+
+   // outputs
+   wire                          rdo_serdes_rst_dual_c;
+   wire                          rdo_rst_dual_c;
+   wire                          ruo_tx_rdy;
+   wire                          rdo_tx_serdes_rst_c;
+   wire   [3:0]                  rdo_tx_pcs_rst_c;
+   wire                          ruo_rx_rdy;
+   wire   [3:0]                  rdo_rx_serdes_rst_c;
+   wire   [3:0]                  rdo_rx_pcs_rst_c;
+
+   // internal signals
+   // common
+   wire                          rsl_enable;
+   wire   [lplol_cnt_width-1:0]  wait_b4_trst;
+   wire   [lrlol_cnt_width-1:0]  wait_b4_rrst;
+   wire   [llols_cnt_width-1:0]  wait_after_lols;
+   reg                           pll_lol_p1;
+   reg                           pll_lol_p2;
+   reg                           pll_lol_p3;
+   // ------------ Tx
+   // rdo_tx_serdes_rst_c
+   reg    [lplol_cnt_width-1:0]  plol_cnt;
+   wire                          plol_cnt_tc;
+
+   reg    [2:0]                  txs_cnt;
+   reg                           txs_rst;
+   wire                          txs_cnt_tc;
+   // rdo_tx_pcs_rst_c
+   wire                          plol_fedge;
+   wire                          plol_redge;
+   reg                           waita_plol0;
+   reg    [2:0]                  plol0_cnt;
+   wire                          plol0_cnt_tc;
+   reg    [2:0]                  txp_cnt;
+   reg                           txp_rst;
+   wire                          txp_cnt_tc;
+   // ruo_tx_rdy
+   wire                          dual_or_serd_rst;
+   wire                          tx_any_pcs_rst;
+   wire                          tx_any_rst;
+   reg                           txsr_appd /* synthesis syn_keep=1 */;
+   reg                           txdpr_appd;
+   reg    [pnum_channels-1:0]    txpr_appd;
+   reg                           txr_wt_en;
+   reg    [ltxr_wait_width-1:0]  txr_wt_cnt;
+   wire                          txr_wt_tc;
+   reg                           ruo_tx_rdyr;
+
+   // ------------ Rx
+   wire                          comb_rlos;
+   wire                          comb_rlol;
+   //wire                          rlols;
+   wire                          rx_all_well;
+
+   //reg                           rlols_p1;
+   //reg                           rlols_p2;
+   //reg                           rlols_p3;
+
+   reg                           rlol_p1;
+   reg                           rlol_p2;
+   reg                           rlol_p3;
+   reg                           rlos_p1;
+   reg                           rlos_p2;
+   reg                           rlos_p3;
+
+   //reg    [3:0]                  rdb_cnt;
+   //wire                          rdb_cnt_max;
+   //wire                          rdb_cnt_zero;
+   //reg                           rlols_db;
+   //reg                           rlols_db_p1;
+
+   reg    [3:0]                  rlol_db_cnt;
+   wire                          rlol_db_cnt_max;
+   wire                          rlol_db_cnt_zero;
+   reg                           rlol_db;
+   reg                                  rlol_db_p1;
+
+   reg    [3:0]                  rlos_db_cnt;
+   wire                          rlos_db_cnt_max;
+   wire                          rlos_db_cnt_zero;
+   reg                           rlos_db;
+   reg                                  rlos_db_p1;
+
+   // rdo_rx_serdes_rst_c
+   reg    [lrlol_cnt_width-1:0]  rlol1_cnt;
+   wire                          rlol1_cnt_tc;
+   reg    [2:0]                  rxs_cnt;
+   reg                           rxs_rst;
+   wire                          rxs_cnt_tc;
+   reg    [lrrst_wait_width-1:0] rrst_cnt;
+   wire                          rrst_cnt_tc;
+   reg                           rrst_wait;
+   // rdo_rx_pcs_rst_c
+   //wire                          rlols_fedge;
+   //wire                          rlols_redge;
+   wire                          rlol_fedge;
+   wire                          rlol_redge;
+   wire                          rlos_fedge;
+   wire                          rlos_redge;
+
+   reg                           wait_calib;
+   reg                           waita_rlols0;
+   reg    [llols_cnt_width-1:0]  rlols0_cnt;
+   wire                          rlols0_cnt_tc;
+   reg    [2:0]                  rxp_cnt;
+   reg                           rxp_rst;
+   wire                          rxp_cnt_tc;
+
+   wire                          rx_any_serd_rst;
+   reg    [llols_cnt_width-1:0]  rlolsz_cnt;
+   wire                          rlolsz_cnt_tc;
+   reg [2:0]                    rxp_cnt2;
+   reg                           rxp_rst2;
+   wire                          rxp_cnt2_tc;
+   reg [15:0]                    data_loop_b_cnt;
+   reg                           data_loop_b;
+   wire                          data_loop_b_tc;
+
+   // ruo_rx_rdy
+   reg    [pnum_channels-1:0]    rxsr_appd;
+   reg    [pnum_channels-1:0]    rxpr_appd;
+   reg                           rxsdr_appd /* synthesis syn_keep=1 */;
+   reg                           rxdpr_appd;
+   wire                          rxsdr_or_sr_appd;
+   wire                          dual_or_rserd_rst;
+   wire                          rx_any_pcs_rst;
+   wire                          rx_any_rst;
+   reg                           rxr_wt_en;
+   reg    [lrxr_wait_width-1:0]  rxr_wt_cnt;
+   wire                          rxr_wt_tc;
+   reg                           ruo_rx_rdyr;
+
+// ==================================================================
+//                          Start of code
+// ==================================================================
+   assign rsl_enable = ~rui_rsl_disable;
+
+// ------------ rdo_serdes_rst_dual_c
+   assign rdo_serdes_rst_dual_c = (rui_rst&rsl_enable) | rui_serdes_rst_dual_c;
+
+// ------------ rdo_rst_dual_c
+   assign rdo_rst_dual_c = rui_rst_dual_c;
+
+// ------------ Setting counter values for RSL_SIM_MODE
+   `ifdef RSL_SIM_MODE
+      assign wait_b4_trst    = lwait_b4_trst_s;
+      assign wait_b4_rrst    = lwait_b4_rrst_s;
+      assign wait_after_lols = lwait_after_lols_s;
+   `else
+      assign wait_b4_trst    = lwait_b4_trst;
+      assign wait_b4_rrst    = lwait_b4_rrst;
+      assign wait_after_lols = lwait_after_lols;
+   `endif
+
+// ==================================================================
+//                                 Tx
+// ==================================================================
+   generate
+   if((pserdes_mode=="RX AND TX")||(pserdes_mode=="TX ONLY")) begin
+
+// ------------ Synchronizing pll_lol to the tx clock
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) begin
+         pll_lol_p1 <= 1'd0;
+         pll_lol_p2 <= 1'd0;
+         pll_lol_p3 <= 1'd0;
+      end
+      else begin
+         pll_lol_p1 <= rdi_pll_lol;
+         pll_lol_p2 <= pll_lol_p1;
+         pll_lol_p3 <= pll_lol_p2;
+      end
+   end
+
+// ------------ rdo_tx_serdes_rst_c
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         plol_cnt    <= 'd0;
+      else if((pll_lol_p2==0)||(plol_cnt_tc==1)||(rdo_tx_serdes_rst_c==1))
+         plol_cnt    <= 'd0;
+      else
+         plol_cnt    <= plol_cnt+1;
+   end
+   assign plol_cnt_tc = (plol_cnt==wait_b4_trst)?1'b1:1'b0;
+
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) begin
+         txs_cnt  <= 'd0;   // tx serdes reset pulse count
+         txs_rst  <= 1'b0;  // tx serdes reset
+      end
+      else if(plol_cnt_tc==1)
+         txs_rst  <= 1'b1;
+      else if(txs_cnt_tc==1) begin
+         txs_cnt  <= 'd0;
+         txs_rst  <= 1'b0;
+      end
+      else if(txs_rst==1)
+         txs_cnt  <= txs_cnt+1;
+   end
+   assign txs_cnt_tc = (txs_cnt==lreset_pwidth)?1'b1:1'b0;
+
+   assign rdo_tx_serdes_rst_c = (rsl_enable&txs_rst)| rui_tx_serdes_rst_c;
+
+// ------------ rdo_tx_pcs_rst_c
+   assign plol_fedge = ~pll_lol_p2 & pll_lol_p3;
+   assign plol_redge = pll_lol_p2 & ~pll_lol_p3;
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         waita_plol0  <= 1'd0;
+      else if(plol_fedge==1'b1)
+         waita_plol0  <= 1'b1;
+      else if((plol0_cnt_tc==1)||(plol_redge==1))
+         waita_plol0  <= 1'd0;
+   end
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         plol0_cnt    <= 'd0;
+      else if((pll_lol_p2==1)||(plol0_cnt_tc==1))
+         plol0_cnt    <= 'd0;
+      else if(waita_plol0==1'b1)
+         plol0_cnt    <= plol0_cnt+1;
+   end
+   assign plol0_cnt_tc = (plol0_cnt==lwait_after_plol0)?1'b1:1'b0;
+
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) begin
+         txp_cnt  <= 'd0;   // tx serdes reset pulse count
+         txp_rst  <= 1'b0;  // tx serdes reset
+      end
+      else if(plol0_cnt_tc==1)
+         txp_rst  <= 1'b1;
+      else if(txp_cnt_tc==1) begin
+         txp_cnt  <= 'd0;
+         txp_rst  <= 1'b0;
+      end
+      else if(txp_rst==1)
+         txp_cnt  <= txp_cnt+1;
+   end
+   assign txp_cnt_tc = (txp_cnt==lreset_pwidth)?1'b1:1'b0;
+
+   genvar i;
+   for(i=0;i<pnum_channels;i=i+1) begin : ifor
+      assign rdo_tx_pcs_rst_c[i] = (rsl_enable&txp_rst)| rui_tx_pcs_rst_c[i];
+   end
+   if(pnum_channels==1)
+      assign rdo_tx_pcs_rst_c[3:1] = 3'b000;
+   else if(pnum_channels==2)
+      assign rdo_tx_pcs_rst_c[3:2] = 2'b00;
+
+   // ------------ ruo_tx_rdy
+   if(pport_tx_rdy=="ENABLED") begin
+   assign dual_or_serd_rst = rdo_serdes_rst_dual_c|rdo_tx_serdes_rst_c;
+   assign tx_any_pcs_rst = rdo_rst_dual_c|(|rdo_tx_pcs_rst_c[pnum_channels-1:0]);
+   assign tx_any_rst = dual_or_serd_rst | tx_any_pcs_rst;
+
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         txsr_appd <= 1'b1; // tx serdes reset applied
+      else if(dual_or_serd_rst==1)
+         txsr_appd <= 1'b1;
+   end
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         txdpr_appd <= 1'b0; // tx dual (pcs) reset applied
+      else if(pll_lol_p2|rdo_serdes_rst_dual_c|rdo_tx_serdes_rst_c)
+         txdpr_appd <= 1'b0;
+      else if(rdo_rst_dual_c==1)
+         txdpr_appd <= 1'b1;
+   end
+
+   genvar m;
+   for(m=0;m<pnum_channels;m=m+1) begin :mfor
+      always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         txpr_appd[m] <= 1'b0; // tx pcs reset applied
+      else if(pll_lol_p2|rdo_serdes_rst_dual_c|rdo_tx_serdes_rst_c)
+         txpr_appd[m] <= 1'b0;
+      else if(txsr_appd&(rdo_tx_pcs_rst_c[m]|txdpr_appd))
+         txpr_appd[m] <= 1'b1;
+      end
+   end
+
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         txr_wt_en  <= 0;  // tx ready wait counter enable
+      else if((txr_wt_tc==1)||(dual_or_serd_rst==1))
+         txr_wt_en  <= 0;
+      else if((~ruo_tx_rdyr)&(~pll_lol_p2)&(&txpr_appd))
+         txr_wt_en  <= 1;
+   end
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         txr_wt_cnt  <= 'd0;  // tx ready wait count
+      else if((txr_wt_tc==1)||(tx_any_rst==1))
+         txr_wt_cnt  <= 'd0;
+      else if(txr_wt_en==1)
+         txr_wt_cnt  <= txr_wt_cnt+1;
+   end
+   assign txr_wt_tc = (txr_wt_cnt==pwait_tx_rdy)?1'b1:1'b0;
+
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         ruo_tx_rdyr <= 1'b0; // tx serdes reset applied
+      else if((tx_any_rst==1)||(pll_lol_p2==1))
+         ruo_tx_rdyr <= 1'b0;
+      else if(txr_wt_tc==1)
+         ruo_tx_rdyr <= 1'b1;
+   end
+   assign ruo_tx_rdy = ruo_tx_rdyr;
+   end         // if pport_tx_rdy
+   else
+      assign ruo_tx_rdy = 1'b0;
+   end         // generate if(Rx and Tx) or (Tx only)
+   else begin  // generate else (Rx only)
+      assign rdo_tx_serdes_rst_c = 1'b0;
+      assign rdo_tx_pcs_rst_c = 4'd0;
+      assign ruo_tx_rdy = 1'b0;
+   end
+   endgenerate
+
+// ==================================================================
+//                                 Rx
+// ==================================================================
+   generate
+   if((pserdes_mode=="RX AND TX")||(pserdes_mode=="RX ONLY")) begin
+   assign comb_rlos = |rdi_rx_los_low_s[pnum_channels-1:0];
+   assign comb_rlol = |rdi_rx_cdr_lol_s[pnum_channels-1:0];
+   //assign rlols     = comb_rlos|comb_rlol;
+
+   // ------------ Synchronizing rlols to the rx ref clock
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) begin
+        //rlols_p1    <= 1'd0;
+        //rlols_p2    <= 1'd0;
+        //rlols_p3    <= 1'd0;
+        //rlols_db_p1 <= 1'd1;
+
+        rlol_p1     <= 1'd0;
+        rlol_p2     <= 1'd0;
+        rlol_p3     <= 1'd0;
+        rlol_db_p1  <= 1'd1;
+
+        rlos_p1    <= 1'd0;
+        rlos_p2    <= 1'd0;
+        rlos_p3    <= 1'd0;
+        rlos_db_p1 <= 1'd1;
+      end
+      else begin
+        //rlols_p1    <= rlols;
+        //rlols_p2    <= rlols_p1;
+        //rlols_p3    <= rlols_p2;
+        //rlols_db_p1 <= rlols_db;
+
+        rlol_p1     <= comb_rlol;
+        rlol_p2     <= rlol_p1;
+        rlol_p3     <= rlol_p2;
+       rlol_db_p1  <= rlol_db;
+
+        rlos_p1    <= comb_rlos;
+        rlos_p2    <= rlos_p1;
+        rlos_p3    <= rlos_p2;
+        rlos_db_p1 <= rlos_db;
+      end
+   end
+   assign rx_all_well = ~rlol_db && ~rlos_db;
+
+//******************************************************************************
+// [ES:05.03.17] Unused registers for clean-up
+//------------------------------------------------------------------------------
+// ------------ Debouncing rlols
+//   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+//      if(rui_rst==1'b1) rdb_cnt  <= lrdb_max;
+//      else if(rlols_p2==1) begin
+//         if(!rdb_cnt_max) rdb_cnt <= rdb_cnt+1;
+//      end
+//      else if(!rdb_cnt_zero) rdb_cnt <= rdb_cnt-1;
+//   end
+//   assign rdb_cnt_max  = (rdb_cnt==lrdb_max);
+//   assign rdb_cnt_zero = (rdb_cnt==0);
+//   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+//      if(rui_rst==1'b1) rlols_db <= 1;
+//      else if(rdb_cnt_max)  rlols_db <= 1;
+//      else if(rdb_cnt_zero) rlols_db <= 0;
+//   end
+//******************************************************************************
+
+// ------------ Debouncing rlol
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) rlol_db_cnt  <= lrdb_max;
+      else if(rlol_p2==1) begin
+         if(!rlol_db_cnt_max) rlol_db_cnt <= rlol_db_cnt+1;
+      end
+      else if(!rlol_db_cnt_zero) rlol_db_cnt <= rlol_db_cnt-1;
+   end
+   assign rlol_db_cnt_max  = (rlol_db_cnt==lrdb_max);
+   assign rlol_db_cnt_zero = (rlol_db_cnt==0);
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) rlol_db <= 1;
+      else if(rlol_db_cnt_max)  rlol_db <= 1;
+      else if(rlol_db_cnt_zero) rlol_db <= 0;
+   end
+
+// ------------ Debouncing rlos
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) rlos_db_cnt  <= lrdb_max;
+      else if(rlos_p2==1) begin
+         if(!rlos_db_cnt_max) rlos_db_cnt <= rlos_db_cnt+1;
+      end
+      else if(!rlos_db_cnt_zero) rlos_db_cnt <= rlos_db_cnt-1;
+   end
+   assign rlos_db_cnt_max  = (rlos_db_cnt==lrdb_max);
+   assign rlos_db_cnt_zero = (rlos_db_cnt==0);
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) rlos_db <= 1;
+      else if(rlos_db_cnt_max)  rlos_db <= 1;
+      else if(rlos_db_cnt_zero) rlos_db <= 0;
+   end
+
+// ------------ Calib time trigger
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+     if (rui_rst==1'b1) begin
+       wait_calib <= 1'd1;
+     end
+     else begin
+       if (rlol1_cnt_tc) begin
+         if (rlol_db)
+           wait_calib <= 1'd1;
+         else
+           wait_calib <= 1'd0;
+       end
+       else if (rlos_redge)
+         wait_calib <= 1'd0;
+       else if (rlos_fedge) begin
+         wait_calib <= 1'd1;
+       end
+     end
+   end
+
+   //***************************************************************************
+   // Total calibration time counter
+   // - this covers the band calibration time (256 cycles * 64) and
+   //   DAC calibration time (16384 cycles * 10 bits)
+   //---------------------------------------------------------------------------
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+     if (rui_rst==1'b1) begin
+       rlol1_cnt  <= 'd0;  // Counting when Rx LOL is 1 and Rx LOS is 0
+     end
+     else begin
+       if(rxs_rst || rlol1_cnt_tc || rlos_redge)
+         rlol1_cnt  <= 'd0;
+       else if (wait_calib)
+         rlol1_cnt <= rlol1_cnt+1;
+     end
+   end
+   assign rlol1_cnt_tc = (rlol1_cnt==wait_b4_rrst);
+
+// ------------ rdo_rx_serdes_rst_c
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+     if (rui_rst==1'b1) begin
+       rxs_cnt  <= 'd0;   // rx serdes reset pulse count
+       rxs_rst  <= 1'b0;  // rx serdes reset
+     end
+     else begin
+       if (rlos_db)
+         rxs_rst <= 1'b0;
+       else if (rlol1_cnt_tc && rlol_db)
+         rxs_rst <= 1'b1;
+       else if (rxs_cnt_tc==1) begin
+         rxs_rst  <= 1'b0;
+       end
+
+       if (rxs_cnt_tc)
+         rxs_cnt <= 'd0;
+       else
+         if (rxs_rst==1)
+           rxs_cnt <= rxs_cnt+1;
+     end
+   end
+   assign rxs_cnt_tc  = (rxs_cnt==lreset_pwidth)?1'b1:1'b0;
+
+   //***************************************************************************
+   // [ES:05.03.17] Unused logic from CPRI rrst_wait
+   //---------------------------------------------------------------------------
+   // always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+   //    if(rui_rst==1'b1)
+   //       rrst_cnt    <= 'd0;
+   //    else if(rlol1_cnt_tc)
+   //       rrst_cnt    <= 'd0;
+   //    else if(rrst_wait)
+   //       rrst_cnt    <= rrst_cnt+1;
+   // end
+   // assign rrst_cnt_tc = (rrst_cnt==lwait_after_rrst) ? 1'b1 : 1'b0;
+   // always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+   //    if(rui_rst==1'b1)
+   //       rrst_wait    <= 0;
+   //    else if(pprotocol != "CPRI")
+   //       rrst_wait    <= 0;
+   //    else if(rlol1_cnt_tc)
+   //       rrst_wait    <= 1;
+   //    else if(rrst_cnt_tc==1)
+   //       rrst_wait    <= 0;
+   // end
+   //***************************************************************************
+
+   genvar j;
+   for(j=0;j<pnum_channels;j=j+1) begin :jfor
+      assign rdo_rx_serdes_rst_c[j] = (rsl_enable&rxs_rst)| rui_rx_serdes_rst_c[j];
+   end
+   if(pnum_channels==1)
+      assign rdo_rx_serdes_rst_c[3:1] = 3'b000;
+   else if(pnum_channels==2)
+      assign rdo_rx_serdes_rst_c[3:2] = 2'b00;
+
+// ------------ rdo_rx_pcs_rst_c
+   //assign rlols_fedge = ~rlols_db & rlols_db_p1;
+   //assign rlols_redge = rlols_db & ~rlols_db_p1;
+
+   assign rlol_fedge  = ~rlol_db & rlol_db_p1;
+   assign rlol_redge  = rlol_db & ~rlol_db_p1;
+   assign rlos_fedge  = ~rlos_db & rlos_db_p1;
+   assign rlos_redge  = rlos_db & ~rlos_db_p1;
+
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if (rui_rst==1'b1) begin
+        waita_rlols0 <= 1'd0;
+      end
+      else begin
+        if ((rlos_fedge && ~rlol_db) || (rlol_fedge && ~rlos_db))
+          waita_rlols0 <= 1'b1;
+        else if (rlos_redge || rlol_redge)
+          waita_rlols0 <= 1'd0;
+        else if (rlols0_cnt_tc==1)
+          waita_rlols0 <= 1'd0;
+      end
+   end
+
+   //***************************************************************************
+   // Post RLOL check before pcs_rst deassertion
+   // - allowance of 2-4 DAC calibration cycles + 1024 cycles for WA module
+   //   (word alignment).
+   //---------------------------------------------------------------------------
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+     if (rui_rst==1'b1) begin
+       rlols0_cnt <= 'd0;
+     end
+     else begin
+       if (rlol_redge || rlos_redge || rlols0_cnt_tc)
+         rlols0_cnt <= 'd0;
+       else if (waita_rlols0==1)
+         rlols0_cnt <= rlols0_cnt+1;
+     end
+   end
+   assign rlols0_cnt_tc   = (rlols0_cnt == wait_after_lols);
+   assign rx_any_serd_rst = rdo_serdes_rst_dual_c|(|rdo_rx_serdes_rst_c);
+
+   //***************************************************************************
+   // [ES:05.03.17] Unused registers for clean-up
+   //---------------------------------------------------------------------------
+   // always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+   //    if(rui_rst==1'b1)
+   //       rlolsz_cnt  <= 'd0;  // Counting when both Rx LOL is 0 and Rx LOS is 0
+   //    else if((rlol_db|rx_any_serd_rst)||(rlolsz_cnt_tc==1))
+   //       rlolsz_cnt  <= 'd0;
+   //    else if((rlolsz_cnt_tc==0)&&(rlol_db==0))
+   //       rlolsz_cnt  <= rlolsz_cnt+1;
+   // end
+   // assign rlolsz_cnt_tc = (rlolsz_cnt==wait_after_lols);
+   //***************************************************************************
+
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+     if (rui_rst==1'b1) begin
+       rxp_cnt2  <= 'd0;   // pcs serdes reset pulse count
+       rxp_rst2  <= 1'b1;  // rx pcs reset
+     end
+     else begin
+       if (rx_any_serd_rst || rlos_redge) begin
+         rxp_rst2 <= 1'b1;
+       end
+       else if (rlols0_cnt_tc) begin
+         rxp_rst2 <= 1'b0;
+       end
+       //***********************************************************************
+       // [ES:05.03.17] No need for pulse width
+       //-----------------------------------------------------------------------
+       // else if(rxp_cnt2_tc==1) begin
+       //   rxp_cnt2  <= 'd0;
+       //   rxp_rst2  <= 1'b0;
+       // end
+       //***********************************************************************
+       // [ES:05.03.17] No need for pulse width
+       //-----------------------------------------------------------------------
+       // else if (rxp_rst2==1)
+       //   rxp_cnt2 <= rxp_cnt2+1;
+       //***********************************************************************
+     end // else: !if(rui_rst==1'b1)
+   end // always @ (posedge rui_rx_ref_clk or posedge rui_rst)
+   //assign rxp_cnt2_tc = (rxp_cnt2==lreset_pwidth)?1'b1:1'b0;
+
+   //***************************************************************************
+   // [ES:05.03.17] No need for pulse width
+   //---------------------------------------------------------------------------
+   //else begin
+   //   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+   //      if(rui_rst==1'b1)
+   //         rxp_rst2  <= 1'b1;  // rx pcs reset
+   //      else if(rx_any_serd_rst)
+   //         rxp_rst2  <= 1'b1;
+   //      else if(rlolsz_cnt_tc==1)
+   //         rxp_rst2  <= 1'b0;
+   //   end
+   //end
+   //***************************************************************************
+
+   genvar k;
+   for(k=0;k<pnum_channels;k=k+1) begin: kfor
+      assign rdo_rx_pcs_rst_c[k] = (rsl_enable&rxp_rst2)| rui_rx_pcs_rst_c[k];
+   end
+   if(pnum_channels==1)
+      assign rdo_rx_pcs_rst_c[3:1] = 3'b000;
+   else if(pnum_channels==2)
+      assign rdo_rx_pcs_rst_c[3:2] = 2'b00;
+
+// ------------ ruo_rx_rdy
+   if(pport_rx_rdy=="ENABLED") begin
+   assign dual_or_rserd_rst = rdo_serdes_rst_dual_c|(|rdo_rx_serdes_rst_c[pnum_channels-1:0]);
+   assign rx_any_pcs_rst = rdo_rst_dual_c|(|rdo_rx_pcs_rst_c[pnum_channels-1:0]);
+   assign rx_any_rst = dual_or_rserd_rst | rx_any_pcs_rst;
+
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         rxsdr_appd <= 1'b1;  // Serdes dual reset (macro reset) applied
+      else if(rdo_serdes_rst_dual_c==1)
+         rxsdr_appd <= 1'b1;
+   end
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         rxdpr_appd <= 1'b0;  // Rx dual PCS reset (dual reset) applied
+      else if(~rx_all_well|dual_or_rserd_rst)
+         rxdpr_appd <= 1'b0;
+      else if(rdo_rst_dual_c==1)
+         rxdpr_appd <= 1'b1;
+   end
+
+   genvar l;
+   for(l=0;l<pnum_channels;l=l+1) begin : lfor
+      always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+         if(rui_rst==1'b1)
+            rxsr_appd[l] <= 1'b0; // rx serdes reset applied
+         else if(rdo_rx_serdes_rst_c[l]==1)
+            rxsr_appd[l] <= 1'b1;
+      end
+      always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         rxpr_appd[l] <= 1'b0; // rx pcs reset applied
+      else if(rdi_rx_los_low_s[l]|rdi_rx_cdr_lol_s[l]|rdo_serdes_rst_dual_c|rdo_rx_serdes_rst_c[l])
+         rxpr_appd[l] <= 1'b0;
+      else if(rxsdr_or_sr_appd&(~rx_all_well)&rdo_rx_pcs_rst_c[l])
+         rxpr_appd[l] <= 1'b1;
+      end
+   end
+
+   assign rxsdr_or_sr_appd = rxsdr_appd|(&rxsr_appd);
+
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         rxr_wt_en  <= 0;  // rx ready wait counter enable
+      //else if((rxr_wt_tc==1)||(dual_or_rserd_rst==1))
+      else if((rxr_wt_tc==1)||(dual_or_rserd_rst==1)||(rx_all_well==0)) // BM, 2/4/16
+         rxr_wt_en  <= 0;
+      else if(~ruo_rx_rdyr&rx_all_well&((&rxpr_appd)|rxdpr_appd))
+         rxr_wt_en  <= 1;
+   end
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         rxr_wt_cnt  <= 'd0;  // rx ready wait count
+      //else if((rxr_wt_tc==1)||(rx_any_rst==1))
+      else if((rxr_wt_tc==1)||(rx_any_rst==1)||(rx_all_well==0)) // BM, 2/4/16
+         rxr_wt_cnt  <= 'd0;
+      else if(rxr_wt_en==1)
+         rxr_wt_cnt  <= rxr_wt_cnt+1;
+   end
+   assign rxr_wt_tc = (rxr_wt_cnt==pwait_rx_rdy)?1'b1:1'b0;
+
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         ruo_rx_rdyr <= 1'b0; // rx serdes reset applied
+      else if((rx_any_rst==1)||(rx_all_well==0))
+         ruo_rx_rdyr <= 1'b0;
+      else if(rxr_wt_tc==1)
+         ruo_rx_rdyr <= 1'b1;
+   end
+   assign ruo_rx_rdy = ruo_rx_rdyr;
+   end         // if pport_rx_rdy
+   else
+      assign ruo_rx_rdy = 1'b0;
+   end // if ((pserdes_mode=="RX AND TX")||(pserdes_mode=="RX ONLY"))
+
+   else begin  // generate else (Tx only)
+      assign rdo_rx_serdes_rst_c = 4'd0;
+      assign rdo_rx_pcs_rst_c = 4'd0;
+      assign ruo_rx_rdy = 1'b0;
+   end // else: !if((pserdes_mode=="RX AND TX")||(pserdes_mode=="RX ONLY"))
+
+   endgenerate
+
+endmodule
+

diff --git a/gbe/cores/sgmii/PCSD/stdout.log.bak.1 b/gbe/cores/sgmii/PCSD/stdout.log.bak.1
new file mode 100644 (file)
index 0000000..36ecb2d
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/stdout.log.bak.1
@@ -0,0 +1,75 @@
+Running in Lattice mode
+
+Starting:    /home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/mbin/synbatch
+Install:     /home/soft/lattice/diamond/3.10_x64/synpbase
+Hostname:    lxhadeb07
+Date:        Mon Apr 29 14:56:30 2019
+Version:     M-2017.03L-SP1-1
+
+Arguments:   -product synplify_pro -batch /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.prj
+ProductType: synplify_pro
+
+
+
+
+log file: "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.srr"
+Running: syn_results in foreground
+
+Running PCSD|syn_results
+
+Running: compile (Compile) on PCSD|syn_results
+# Mon Apr 29 14:56:30 2019
+
+Running: compile_flow (Compile Process) on PCSD|syn_results
+# Mon Apr 29 14:56:30 2019
+
+Running: compiler (Compile Input) on PCSD|syn_results
+# Mon Apr 29 14:56:30 2019
+Copied /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.srs to /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.srs
+
+compiler completed
+# Mon Apr 29 14:56:32 2019
+
+Return Code: 0
+Run Time:00h:00m:02s
+
+Running: multi_srs_gen (Multi-srs Generator) on PCSD|syn_results
+# Mon Apr 29 14:56:32 2019
+
+multi_srs_gen completed
+# Mon Apr 29 14:56:32 2019
+
+Return Code: 0
+Run Time:00h:00m:00s
+Copied /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_mult.srs to /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.srs
+Copied /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.srr to /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.srf
+Complete: Compile Process on PCSD|syn_results
+
+Running: premap (Pre-mapping) on PCSD|syn_results
+# Mon Apr 29 14:56:32 2019
+
+premap completed with warnings
+# Mon Apr 29 14:56:33 2019
+
+Return Code: 1
+Run Time:00h:00m:01s
+Complete: Compile on PCSD|syn_results
+
+Running: map (Map) on PCSD|syn_results
+# Mon Apr 29 14:56:33 2019
+License granted for 4 parallel jobs
+
+Running: fpga_mapper (Map & Optimize) on PCSD|syn_results
+# Mon Apr 29 14:56:33 2019
+Copied /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_m.srm to /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.srm
+
+fpga_mapper completed with warnings
+# Mon Apr 29 14:56:37 2019
+
+Return Code: 1
+Run Time:00h:00m:04s
+Complete: Map on PCSD|syn_results
+Copied /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.srr to /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.srf
+Complete: Logic Synthesis on PCSD|syn_results
+exit status=0
+exit status=0

diff --git a/gbe/cores/sgmii/PCSD/syn_results/.recordref b/gbe/cores/sgmii/PCSD/syn_results/.recordref
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/sgmii/PCSD/syn_results/PCSD.areasrr b/gbe/cores/sgmii/PCSD/syn_results/PCSD.areasrr
new file mode 100644 (file)
index 0000000..a7afb40
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/PCSD.areasrr
@@ -0,0 +1,40 @@
+----------------------------------------------------------------------
+Report for cell PCSD.v1
+
+Register bits: 92 of 24288 (0%)
+PIC Latch:       0
+I/O cells:       0
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                              CCU2C       37       100.0
+                               DCUA        1       100.0
+                            FD1P3BX        4       100.0
+                            FD1P3DX       42       100.0
+                            FD1S3BX       10       100.0
+                            FD1S3DX       36       100.0
+                                GSR        1       100.0
+                           ORCALUT4       63       100.0
+                              PFUMX        2       100.0
+                                PUR        1       100.0
+                                VHI        2       100.0
+                                VLO        2       100.0
+SUB MODULES 
+             PCSDrsl_core_Z1_layer1        1       100.0
+                            
+                         TOTAL           202           
+----------------------------------------------------------------------
+Report for cell PCSDrsl_core_Z1_layer1.netlist
+     Instance path:  rsl_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                              CCU2C       37       100.0
+                            FD1P3BX        4       100.0
+                            FD1P3DX       42       100.0
+                            FD1S3BX       10       100.0
+                            FD1S3DX       36       100.0
+                           ORCALUT4       63       100.0
+                              PFUMX        2       100.0
+                                VHI        1        50.0
+                                VLO        1        50.0
+                            
+                         TOTAL           196           

diff --git a/gbe/cores/sgmii/PCSD/syn_results/PCSD.fse b/gbe/cores/sgmii/PCSD/syn_results/PCSD.fse
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/sgmii/PCSD/syn_results/PCSD.htm b/gbe/cores/sgmii/PCSD/syn_results/PCSD.htm
new file mode 100644 (file)
index 0000000..9b16c86
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/PCSD.htm
@@ -0,0 +1,9 @@
+<html>
+ <head>
+ <title>syntmp/PCSD_srr.htm log file</title>
+ </head>
+ <frameset cols="20%, 80%">
+ <frame src="syntmp/PCSD_toc.htm" name="tocFrame" />
+                                <frame src="syntmp/PCSD_srr.htm" name="srrFrame"/>
+</frameset>
+ </html>

diff --git a/gbe/cores/sgmii/PCSD/syn_results/PCSD.prj b/gbe/cores/sgmii/PCSD/syn_results/PCSD.prj
new file mode 100644 (file)
index 0000000..a95f061
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/PCSD.prj
@@ -0,0 +1,47 @@
+#-- Lattice Semiconductor Corporation Ltd.
+#-- Synplify OEM project file /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.prj
+#-- Written on Tue Apr 30 12:09:44 2019
+
+
+#device options
+set_option -technology ecp5um
+set_option -part LFE5UM-85F
+set_option -speed_grade 8
+
+#use verilog 2001 standard option
+set_option -vlog_std v2001
+
+#map options
+set_option -frequency 100
+set_option -fanout_limit 50
+set_option -disable_io_insertion true
+set_option -retiming false
+set_option -pipe false
+set_option -pipe false
+set_option -force_gsr false
+
+#simulation options
+set_option -write_verilog true
+set_option -write_vhdl true
+
+#timing analysis options
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#-- add_file options
+add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd"
+add_file -verilog -lib work "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v"
+add_file -constraint {"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc"}
+
+#-- top module name
+set_option -top_module PCSD
+
+#-- set result format/file last
+project -result_file "PCSD.edn"
+
+#-- error message log file
+project -log_file PCSD.srf
+
+#-- run Synplify with 'arrange VHDL file'
+project -run

diff --git a/gbe/cores/sgmii/PCSD/syn_results/PCSD.srd b/gbe/cores/sgmii/PCSD/syn_results/PCSD.srd
new file mode 100644 (file)
index 0000000..dc4f84c
Binary files /dev/null and b/gbe/cores/sgmii/PCSD/syn_results/PCSD.srd differ

diff --git a/gbe/cores/sgmii/PCSD/syn_results/PCSD.srf b/gbe/cores/sgmii/PCSD/syn_results/PCSD.srf
new file mode 100644 (file)
index 0000000..6d9a5e2
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/PCSD.srf
@@ -0,0 +1,829 @@
+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
+#install: /home/soft/lattice/diamond/3.10_x64/synpbase
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Tue Apr 30 12:09:44 2019
+
+#Implementation: syn_results
+
+Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Top entity is set to PCSD.
+VHDL syntax check successful!
+File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd changed - recompiling
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 72MB)
+
+
+Process completed successfully.
+# Tue Apr 30 12:09:44 2019
+
+###########################################################]
+Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v" (library work)
+Verilog syntax check successful!
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Tue Apr 30 12:09:45 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Top entity is set to PCSD.
+File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd changed - recompiling
+File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling
+VHDL syntax check successful!
+File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd changed - recompiling
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Synthesizing work.pcsd.v1.
+Post processing for work.pcsd.v1
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB)
+
+
+Process completed successfully.
+# Tue Apr 30 12:09:45 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v" (library work)
+Verilog syntax check successful!
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":92:7:92:18|Synthesizing module PCSDrsl_core in library work.
+
+       pnum_channels=32'b00000000000000000000000000000001
+       pprotocol=24'b010001110100001001000101
+       pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
+       pport_tx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100
+       pwait_tx_rdy=32'b00000000000000000000101110111000
+       pport_rx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100
+       pwait_rx_rdy=32'b00000000000000000000101110111000
+       wa_num_cycles=32'b00000000000000000000010000000000
+       dac_num_cycles=32'b00000000000000000000000000000011
+       lreset_pwidth=32'b00000000000000000000000000000011
+       lwait_b4_trst=32'b00000000000010111110101111000010
+       lwait_b4_trst_s=32'b00000000000000000000001100001101
+       lplol_cnt_width=32'b00000000000000000000000000010100
+       lwait_after_plol0=32'b00000000000000000000000000000100
+       lwait_b4_rrst=32'b00000000000000101100000000000000
+       lrrst_wait_width=32'b00000000000000000000000000010100
+       lwait_after_rrst=32'b00000000000011000011010100000000
+       lwait_b4_rrst_s=32'b00000000000000000000000111001100
+       lrlol_cnt_width=32'b00000000000000000000000000010011
+       lwait_after_lols=32'b00000000000000001100010000000000
+       lwait_after_lols_s=32'b00000000000000000000000010010110
+       llols_cnt_width=32'b00000000000000000000000000010010
+       lrdb_max=32'b00000000000000000000000000001111
+       ltxr_wait_width=32'b00000000000000000000000000001100
+       lrxr_wait_width=32'b00000000000000000000000000001100
+   Generated name = PCSDrsl_core_Z1_layer1
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":274:33:274:48|Removing wire dual_or_serd_rst, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":275:33:275:46|Removing wire tx_any_pcs_rst, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":276:33:276:42|Removing wire tx_any_rst, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":277:33:277:41|Object txsr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":278:33:278:42|Object txdpr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":279:33:279:41|Object txpr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":280:33:280:41|Object txr_wt_en is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":281:33:281:42|Object txr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":282:33:282:41|Removing wire txr_wt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":283:33:283:43|Object ruo_tx_rdyr is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":356:33:356:41|Object rxsr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":357:33:357:41|Object rxpr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":358:33:358:42|Object rxsdr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":359:33:359:42|Object rxdpr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":360:33:360:48|Removing wire rxsdr_or_sr_appd, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":361:33:361:49|Removing wire dual_or_rserd_rst, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":362:33:362:46|Removing wire rx_any_pcs_rst, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":363:33:363:42|Removing wire rx_any_rst, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":364:33:364:41|Object rxr_wt_en is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":365:33:365:42|Object rxr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":366:33:366:41|Removing wire rxr_wt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":367:33:367:43|Object ruo_rx_rdyr is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":507:10:507:10|Object m is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":880:10:880:10|Object l is declared but not assigned. Either assign a value or remove the declaration.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 75MB)
+
+
+Process completed successfully.
+# Tue Apr 30 12:09:45 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/layer0.srs changed - recompiling
+File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/layer1.srs changed - recompiling
+
+=======================================================================================
+For a summary of linker messages for components that did not bind, please see log file:
+@L: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.linkerlog
+=======================================================================================
+
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Tue Apr 30 12:09:46 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Tue Apr 30 12:09:46 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Tue Apr 30 12:09:47 2019
+
+###########################################################]
+# Tue Apr 30 12:09:47 2019
+
+Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc
+@L: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD_scck.rpt 
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD_scck.rpt" file 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist PCSD
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+
+Clock Summary
+******************
+
+          Start                Requested     Requested     Clock        Clock                   Clock
+Level     Clock                Frequency     Period        Type         Group                   Load 
+-----------------------------------------------------------------------------------------------------
+0 -       System               100.0 MHz     10.000        system       system_clkgroup         0    
+                                                                                                     
+0 -       PCSD|rxrefclk        100.0 MHz     10.000        inferred     Inferred_clkgroup_1     59   
+                                                                                                     
+0 -       PCSD|pll_refclki     100.0 MHz     10.000        inferred     Inferred_clkgroup_0     33   
+=====================================================================================================
+
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":412:3:412:8|Found inferred clock PCSD|pll_refclki which controls 33 sequential elements including rsl_inst.genblk1\.plol_cnt[19:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Found inferred clock PCSD|rxrefclk which controls 59 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Apr 30 12:09:48 2019
+
+###########################################################]
+# Tue Apr 30 12:09:48 2019
+
+Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":412:3:412:8|Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk1\.plol_cnt[19:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":778:3:778:8|Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":680:3:680:8|Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] 
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+   1           0h:00m:00s                   5.36ns               63 /        92
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+2 non-gated/non-generated clock tree(s) driving 92 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+=================================== Non-Gated/Non-Generated Clocks ====================================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                
+-------------------------------------------------------------------------------------------------------
+@K:CKID0001       rxrefclk            port                   59         rsl_inst.genblk2\.rlol1_cnt[18]
+@K:CKID0002       pll_refclki         port                   33         rsl_inst.genblk1\.pll_lol_p1   
+=======================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 107MB peak: 144MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.edn
+M-2017.03L-SP1-1
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 148MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 148MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB)
+
+@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":118:4:118:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+@W: MT420 |Found inferred clock PCSD|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"
+@W: MT420 |Found inferred clock PCSD|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Tue Apr 30 12:09:50 2019
+#
+
+
+Top view:               PCSD
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 4.079
+
+@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
+                     Requested     Estimated       Requested     Estimated               Clock        Clock              
+Starting Clock       Frequency     Frequency       Period        Period        Slack     Type         Group              
+-------------------------------------------------------------------------------------------------------------------------
+PCSD|pll_refclki     100.0 MHz     168.9 MHz       10.000        5.921         4.079     inferred     Inferred_clkgroup_0
+PCSD|rxrefclk        100.0 MHz     170.5 MHz       10.000        5.864         4.136     inferred     Inferred_clkgroup_1
+System               100.0 MHz     18518.5 MHz     10.000        0.054         9.946     system       system_clkgroup    
+=========================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                              |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+---------------------------------------------------------------------------------------------------------------------------
+Starting          Ending            |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
+---------------------------------------------------------------------------------------------------------------------------
+System            System            |  10.000      10.000  |  No paths    -      |  No paths    -      |  No paths    -    
+System            PCSD|rxrefclk     |  10.000      9.946   |  No paths    -      |  No paths    -      |  No paths    -    
+PCSD|pll_refclki  System            |  10.000      8.385   |  No paths    -      |  No paths    -      |  No paths    -    
+PCSD|pll_refclki  PCSD|pll_refclki  |  10.000      4.079   |  No paths    -      |  No paths    -      |  No paths    -    
+PCSD|rxrefclk     System            |  10.000      8.283   |  No paths    -      |  No paths    -      |  No paths    -    
+PCSD|rxrefclk     PCSD|rxrefclk     |  10.000      4.136   |  No paths    -      |  No paths    -      |  No paths    -    
+===========================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: PCSD|pll_refclki
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                   Starting                                                  Arrival          
+Instance                           Reference            Type        Pin     Net              Time        Slack
+                                   Clock                                                                      
+--------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[1]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[1]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[6]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[6]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[7]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[7]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[12]     PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[12]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[2]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[2]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[3]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[3]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[4]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[4]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[5]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[5]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[8]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[8]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[9]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[9]      0.907       4.684
+==============================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                   Starting                                                    Required          
+Instance                           Reference            Type        Pin     Net                Time         Slack
+                                   Clock                                                                         
+-----------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[19]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[19]     9.946        4.079
+rsl_inst.genblk1\.plol_cnt[17]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[17]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[18]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[18]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[15]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[15]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[16]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[16]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[13]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[13]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[14]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[14]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[11]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[11]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[12]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[12]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[9]      PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[9]      9.946        4.383
+=================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.867
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     4.079
+
+    Number of logic level(s):                15
+    Starting point:                          rsl_inst.genblk1\.plol_cnt[1] / Q
+    Ending point:                            rsl_inst.genblk1\.plol_cnt[19] / D
+    The start point is clocked by            PCSD|pll_refclki [rising] on pin CK
+    The end   point is clocked by            PCSD|pll_refclki [rising] on pin CK
+
+Instance / Net                                        Pin      Pin               Arrival     No. of    
+Name                                     Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[1]            FD1S3DX      Q        Out     0.907     0.907       -         
+plol_cnt[1]                              Net          -        -       -         -           2         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     Z        Out     0.606     1.513       -         
+un1_plol_cnt_tc_10                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     Z        Out     0.606     2.119       -         
+un1_plol_cnt_tc_14                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     Z        Out     0.762     2.881       -         
+un1_plol_cnt_tc                          Net          -        -       -         -           5         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     B        In      0.000     2.881       -         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     Z        Out     0.840     3.721       -         
+plol_cnt                                 Net          -        -       -         -           21        
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.721       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.621       -         
+plol_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.621       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.682       -         
+plol_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.682       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.743       -         
+plol_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.743       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.804       -         
+plol_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.804       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.865       -         
+plol_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.865       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.926       -         
+plol_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.926       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.987       -         
+plol_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.987       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.048       -         
+plol_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.048       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.109       -         
+plol_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.109       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        COUT     Out     0.061     5.170       -         
+plol_cnt_cry[18]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        CIN      In      0.000     5.170       -         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        S0       Out     0.698     5.867       -         
+plol_cnt_s[19]                           Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt[19]           FD1S3DX      D        In      0.000     5.867       -         
+=======================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: PCSD|rxrefclk
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                     Starting                                                 Arrival          
+Instance                             Reference         Type        Pin     Net                Time        Slack
+                                     Clock                                                                     
+---------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[14]      PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[14]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[15]      PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[15]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[16]      PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[16]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[17]      PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[17]      0.907       4.136
+rsl_inst.genblk2\.rlols0_cnt[10]     PCSD|rxrefclk     FD1P3DX     Q       rlols0_cnt[10]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[14]     PCSD|rxrefclk     FD1P3DX     Q       rlols0_cnt[14]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[16]     PCSD|rxrefclk     FD1P3DX     Q       rlols0_cnt[16]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[17]     PCSD|rxrefclk     FD1P3DX     Q       rlols0_cnt[17]     0.907       4.170
+rsl_inst.genblk2\.rlol1_cnt[0]       PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[0]       0.907       4.742
+rsl_inst.genblk2\.rlol1_cnt[1]       PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[1]       0.907       4.742
+===============================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                     Starting                                                   Required          
+Instance                             Reference         Type        Pin     Net                  Time         Slack
+                                     Clock                                                                        
+------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[17]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[17]      9.946        4.136
+rsl_inst.genblk2\.rlol1_cnt[18]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[18]      9.946        4.136
+rsl_inst.genblk2\.rlols0_cnt[17]     PCSD|rxrefclk     FD1P3DX     D       rlols0_cnt_s[17]     9.946        4.170
+rsl_inst.genblk2\.rlol1_cnt[15]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[15]      9.946        4.197
+rsl_inst.genblk2\.rlol1_cnt[16]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[16]      9.946        4.197
+rsl_inst.genblk2\.rlols0_cnt[15]     PCSD|rxrefclk     FD1P3DX     D       rlols0_cnt_s[15]     9.946        4.231
+rsl_inst.genblk2\.rlols0_cnt[16]     PCSD|rxrefclk     FD1P3DX     D       rlols0_cnt_s[16]     9.946        4.231
+rsl_inst.genblk2\.rlol1_cnt[13]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[13]      9.946        4.258
+rsl_inst.genblk2\.rlol1_cnt[14]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[14]      9.946        4.258
+rsl_inst.genblk2\.rlols0_cnt[13]     PCSD|rxrefclk     FD1P3DX     D       rlols0_cnt_s[13]     9.946        4.292
+==================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.809
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.136
+
+    Number of logic level(s):                14
+    Starting point:                          rsl_inst.genblk2\.rlol1_cnt[14] / Q
+    Ending point:                            rsl_inst.genblk2\.rlol1_cnt[18] / D
+    The start point is clocked by            PCSD|rxrefclk [rising] on pin CK
+    The end   point is clocked by            PCSD|rxrefclk [rising] on pin CK
+
+Instance / Net                                         Pin      Pin               Arrival     No. of    
+Name                                      Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[14]           FD1P3DX      Q        Out     0.907     0.907       -         
+rlol1_cnt[14]                             Net          -        -       -         -           2         
+rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     Z        Out     0.606     1.513       -         
+rlol1_cnt_tc_1_10                         Net          -        -       -         -           1         
+rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     Z        Out     0.606     2.119       -         
+rlol1_cnt_tc_1_14                         Net          -        -       -         -           1         
+rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     Z        Out     0.768     2.887       -         
+rlol1_cnt_tc_1                            Net          -        -       -         -           6         
+rsl_inst.genblk2\.rxs_rst_RNIS0OP         ORCALUT4     A        In      0.000     2.887       -         
+rsl_inst.genblk2\.rxs_rst_RNIS0OP         ORCALUT4     Z        Out     0.837     3.724       -         
+rlol1_cnt                                 Net          -        -       -         -           20        
+rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.724       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.624       -         
+rlol1_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.624       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.685       -         
+rlol1_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.685       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.746       -         
+rlol1_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.746       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.807       -         
+rlol1_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.807       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.868       -         
+rlol1_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.868       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.929       -         
+rlol1_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.929       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.990       -         
+rlol1_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.990       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.051       -         
+rlol1_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.051       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.112       -         
+rlol1_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.112       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        S1       Out     0.698     5.809       -         
+rlol1_cnt_s[18]                           Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt[18]           FD1P3DX      D        In      0.000     5.809       -         
+========================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                                   Arrival           
+Instance      Reference     Type     Pin                Net              Time        Slack 
+              Clock                                                                        
+-------------------------------------------------------------------------------------------
+DCU0_inst     System        DCUA     CH0_FFS_RLOL       rx_cdr_lol_s     0.000       9.946 
+DCU0_inst     System        DCUA     CH0_FFS_RLOS       rx_los_low_s     0.000       9.946 
+DCU0_inst     System        DCUA     CH0_FF_TX_PCLK     tx_pclk          0.000       10.000
+===========================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                              Starting                                                       Required           
+Instance                      Reference     Type        Pin                 Net              Time         Slack 
+                              Clock                                                                             
+----------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol_p1     System        FD1S3DX     D                   rx_cdr_lol_s     9.946        9.946 
+rsl_inst.genblk2\.rlos_p1     System        FD1S3DX     D                   rx_los_low_s     9.946        9.946 
+DCU0_inst                     System        DCUA        CH0_FF_EBRD_CLK     tx_pclk          10.000       10.000
+DCU0_inst                     System        DCUA        CH0_FF_RXI_CLK      tx_pclk          10.000       10.000
+================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      0.000
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 9.946
+
+    Number of logic level(s):                0
+    Starting point:                          DCU0_inst / CH0_FFS_RLOL
+    Ending point:                            rsl_inst.genblk2\.rlol_p1 / D
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            PCSD|rxrefclk [rising] on pin CK
+
+Instance / Net                            Pin              Pin               Arrival     No. of    
+Name                          Type        Name             Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------------------
+DCU0_inst                     DCUA        CH0_FFS_RLOL     Out     0.000     0.000       -         
+rx_cdr_lol_s                  Net         -                -       -         -           2         
+rsl_inst.genblk2\.rlol_p1     FD1S3DX     D                In      0.000     0.000       -         
+===================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 92 of 24288 (0%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+CCU2C:          37
+DCUA:           1
+FD1P3BX:        4
+FD1P3DX:        42
+FD1S3BX:        10
+FD1S3DX:        36
+GSR:            1
+ORCALUT4:       63
+PFUMX:          2
+PUR:            1
+VHI:            2
+VLO:            2
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 32MB peak: 148MB)
+
+Process took 0h:00m:02s realtime, 0h:00m:02s cputime
+# Tue Apr 30 12:09:51 2019
+
+###########################################################]

diff --git a/gbe/cores/sgmii/PCSD/syn_results/PCSD.srm b/gbe/cores/sgmii/PCSD/syn_results/PCSD.srm
new file mode 100644 (file)
index 0000000..ad3a4ed
Binary files /dev/null and b/gbe/cores/sgmii/PCSD/syn_results/PCSD.srm differ

diff --git a/gbe/cores/sgmii/PCSD/syn_results/PCSD.srr b/gbe/cores/sgmii/PCSD/syn_results/PCSD.srr
new file mode 100644 (file)
index 0000000..6d9a5e2
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/PCSD.srr
@@ -0,0 +1,829 @@
+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
+#install: /home/soft/lattice/diamond/3.10_x64/synpbase
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Tue Apr 30 12:09:44 2019
+
+#Implementation: syn_results
+
+Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Top entity is set to PCSD.
+VHDL syntax check successful!
+File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd changed - recompiling
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 72MB)
+
+
+Process completed successfully.
+# Tue Apr 30 12:09:44 2019
+
+###########################################################]
+Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v" (library work)
+Verilog syntax check successful!
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Tue Apr 30 12:09:45 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Top entity is set to PCSD.
+File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd changed - recompiling
+File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling
+VHDL syntax check successful!
+File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd changed - recompiling
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Synthesizing work.pcsd.v1.
+Post processing for work.pcsd.v1
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB)
+
+
+Process completed successfully.
+# Tue Apr 30 12:09:45 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v" (library work)
+Verilog syntax check successful!
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":92:7:92:18|Synthesizing module PCSDrsl_core in library work.
+
+       pnum_channels=32'b00000000000000000000000000000001
+       pprotocol=24'b010001110100001001000101
+       pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
+       pport_tx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100
+       pwait_tx_rdy=32'b00000000000000000000101110111000
+       pport_rx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100
+       pwait_rx_rdy=32'b00000000000000000000101110111000
+       wa_num_cycles=32'b00000000000000000000010000000000
+       dac_num_cycles=32'b00000000000000000000000000000011
+       lreset_pwidth=32'b00000000000000000000000000000011
+       lwait_b4_trst=32'b00000000000010111110101111000010
+       lwait_b4_trst_s=32'b00000000000000000000001100001101
+       lplol_cnt_width=32'b00000000000000000000000000010100
+       lwait_after_plol0=32'b00000000000000000000000000000100
+       lwait_b4_rrst=32'b00000000000000101100000000000000
+       lrrst_wait_width=32'b00000000000000000000000000010100
+       lwait_after_rrst=32'b00000000000011000011010100000000
+       lwait_b4_rrst_s=32'b00000000000000000000000111001100
+       lrlol_cnt_width=32'b00000000000000000000000000010011
+       lwait_after_lols=32'b00000000000000001100010000000000
+       lwait_after_lols_s=32'b00000000000000000000000010010110
+       llols_cnt_width=32'b00000000000000000000000000010010
+       lrdb_max=32'b00000000000000000000000000001111
+       ltxr_wait_width=32'b00000000000000000000000000001100
+       lrxr_wait_width=32'b00000000000000000000000000001100
+   Generated name = PCSDrsl_core_Z1_layer1
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":274:33:274:48|Removing wire dual_or_serd_rst, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":275:33:275:46|Removing wire tx_any_pcs_rst, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":276:33:276:42|Removing wire tx_any_rst, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":277:33:277:41|Object txsr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":278:33:278:42|Object txdpr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":279:33:279:41|Object txpr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":280:33:280:41|Object txr_wt_en is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":281:33:281:42|Object txr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":282:33:282:41|Removing wire txr_wt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":283:33:283:43|Object ruo_tx_rdyr is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":356:33:356:41|Object rxsr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":357:33:357:41|Object rxpr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":358:33:358:42|Object rxsdr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":359:33:359:42|Object rxdpr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":360:33:360:48|Removing wire rxsdr_or_sr_appd, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":361:33:361:49|Removing wire dual_or_rserd_rst, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":362:33:362:46|Removing wire rx_any_pcs_rst, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":363:33:363:42|Removing wire rx_any_rst, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":364:33:364:41|Object rxr_wt_en is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":365:33:365:42|Object rxr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":366:33:366:41|Removing wire rxr_wt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":367:33:367:43|Object ruo_rx_rdyr is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":507:10:507:10|Object m is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":880:10:880:10|Object l is declared but not assigned. Either assign a value or remove the declaration.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 75MB)
+
+
+Process completed successfully.
+# Tue Apr 30 12:09:45 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/layer0.srs changed - recompiling
+File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/layer1.srs changed - recompiling
+
+=======================================================================================
+For a summary of linker messages for components that did not bind, please see log file:
+@L: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.linkerlog
+=======================================================================================
+
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Tue Apr 30 12:09:46 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Tue Apr 30 12:09:46 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Tue Apr 30 12:09:47 2019
+
+###########################################################]
+# Tue Apr 30 12:09:47 2019
+
+Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc
+@L: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD_scck.rpt 
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD_scck.rpt" file 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist PCSD
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+
+Clock Summary
+******************
+
+          Start                Requested     Requested     Clock        Clock                   Clock
+Level     Clock                Frequency     Period        Type         Group                   Load 
+-----------------------------------------------------------------------------------------------------
+0 -       System               100.0 MHz     10.000        system       system_clkgroup         0    
+                                                                                                     
+0 -       PCSD|rxrefclk        100.0 MHz     10.000        inferred     Inferred_clkgroup_1     59   
+                                                                                                     
+0 -       PCSD|pll_refclki     100.0 MHz     10.000        inferred     Inferred_clkgroup_0     33   
+=====================================================================================================
+
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":412:3:412:8|Found inferred clock PCSD|pll_refclki which controls 33 sequential elements including rsl_inst.genblk1\.plol_cnt[19:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Found inferred clock PCSD|rxrefclk which controls 59 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Apr 30 12:09:48 2019
+
+###########################################################]
+# Tue Apr 30 12:09:48 2019
+
+Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":412:3:412:8|Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk1\.plol_cnt[19:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":778:3:778:8|Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":680:3:680:8|Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] 
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+   1           0h:00m:00s                   5.36ns               63 /        92
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+2 non-gated/non-generated clock tree(s) driving 92 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+=================================== Non-Gated/Non-Generated Clocks ====================================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                
+-------------------------------------------------------------------------------------------------------
+@K:CKID0001       rxrefclk            port                   59         rsl_inst.genblk2\.rlol1_cnt[18]
+@K:CKID0002       pll_refclki         port                   33         rsl_inst.genblk1\.pll_lol_p1   
+=======================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 107MB peak: 144MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.edn
+M-2017.03L-SP1-1
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 148MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 148MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB)
+
+@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":118:4:118:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+@W: MT420 |Found inferred clock PCSD|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"
+@W: MT420 |Found inferred clock PCSD|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Tue Apr 30 12:09:50 2019
+#
+
+
+Top view:               PCSD
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 4.079
+
+@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
+                     Requested     Estimated       Requested     Estimated               Clock        Clock              
+Starting Clock       Frequency     Frequency       Period        Period        Slack     Type         Group              
+-------------------------------------------------------------------------------------------------------------------------
+PCSD|pll_refclki     100.0 MHz     168.9 MHz       10.000        5.921         4.079     inferred     Inferred_clkgroup_0
+PCSD|rxrefclk        100.0 MHz     170.5 MHz       10.000        5.864         4.136     inferred     Inferred_clkgroup_1
+System               100.0 MHz     18518.5 MHz     10.000        0.054         9.946     system       system_clkgroup    
+=========================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                              |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+---------------------------------------------------------------------------------------------------------------------------
+Starting          Ending            |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
+---------------------------------------------------------------------------------------------------------------------------
+System            System            |  10.000      10.000  |  No paths    -      |  No paths    -      |  No paths    -    
+System            PCSD|rxrefclk     |  10.000      9.946   |  No paths    -      |  No paths    -      |  No paths    -    
+PCSD|pll_refclki  System            |  10.000      8.385   |  No paths    -      |  No paths    -      |  No paths    -    
+PCSD|pll_refclki  PCSD|pll_refclki  |  10.000      4.079   |  No paths    -      |  No paths    -      |  No paths    -    
+PCSD|rxrefclk     System            |  10.000      8.283   |  No paths    -      |  No paths    -      |  No paths    -    
+PCSD|rxrefclk     PCSD|rxrefclk     |  10.000      4.136   |  No paths    -      |  No paths    -      |  No paths    -    
+===========================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: PCSD|pll_refclki
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                   Starting                                                  Arrival          
+Instance                           Reference            Type        Pin     Net              Time        Slack
+                                   Clock                                                                      
+--------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[1]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[1]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[6]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[6]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[7]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[7]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[12]     PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[12]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[2]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[2]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[3]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[3]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[4]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[4]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[5]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[5]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[8]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[8]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[9]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[9]      0.907       4.684
+==============================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                   Starting                                                    Required          
+Instance                           Reference            Type        Pin     Net                Time         Slack
+                                   Clock                                                                         
+-----------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[19]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[19]     9.946        4.079
+rsl_inst.genblk1\.plol_cnt[17]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[17]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[18]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[18]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[15]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[15]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[16]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[16]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[13]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[13]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[14]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[14]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[11]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[11]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[12]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[12]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[9]      PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[9]      9.946        4.383
+=================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.867
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     4.079
+
+    Number of logic level(s):                15
+    Starting point:                          rsl_inst.genblk1\.plol_cnt[1] / Q
+    Ending point:                            rsl_inst.genblk1\.plol_cnt[19] / D
+    The start point is clocked by            PCSD|pll_refclki [rising] on pin CK
+    The end   point is clocked by            PCSD|pll_refclki [rising] on pin CK
+
+Instance / Net                                        Pin      Pin               Arrival     No. of    
+Name                                     Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[1]            FD1S3DX      Q        Out     0.907     0.907       -         
+plol_cnt[1]                              Net          -        -       -         -           2         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     Z        Out     0.606     1.513       -         
+un1_plol_cnt_tc_10                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     Z        Out     0.606     2.119       -         
+un1_plol_cnt_tc_14                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     Z        Out     0.762     2.881       -         
+un1_plol_cnt_tc                          Net          -        -       -         -           5         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     B        In      0.000     2.881       -         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     Z        Out     0.840     3.721       -         
+plol_cnt                                 Net          -        -       -         -           21        
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.721       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.621       -         
+plol_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.621       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.682       -         
+plol_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.682       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.743       -         
+plol_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.743       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.804       -         
+plol_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.804       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.865       -         
+plol_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.865       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.926       -         
+plol_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.926       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.987       -         
+plol_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.987       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.048       -         
+plol_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.048       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.109       -         
+plol_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.109       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        COUT     Out     0.061     5.170       -         
+plol_cnt_cry[18]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        CIN      In      0.000     5.170       -         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        S0       Out     0.698     5.867       -         
+plol_cnt_s[19]                           Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt[19]           FD1S3DX      D        In      0.000     5.867       -         
+=======================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: PCSD|rxrefclk
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                     Starting                                                 Arrival          
+Instance                             Reference         Type        Pin     Net                Time        Slack
+                                     Clock                                                                     
+---------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[14]      PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[14]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[15]      PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[15]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[16]      PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[16]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[17]      PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[17]      0.907       4.136
+rsl_inst.genblk2\.rlols0_cnt[10]     PCSD|rxrefclk     FD1P3DX     Q       rlols0_cnt[10]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[14]     PCSD|rxrefclk     FD1P3DX     Q       rlols0_cnt[14]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[16]     PCSD|rxrefclk     FD1P3DX     Q       rlols0_cnt[16]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[17]     PCSD|rxrefclk     FD1P3DX     Q       rlols0_cnt[17]     0.907       4.170
+rsl_inst.genblk2\.rlol1_cnt[0]       PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[0]       0.907       4.742
+rsl_inst.genblk2\.rlol1_cnt[1]       PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[1]       0.907       4.742
+===============================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                     Starting                                                   Required          
+Instance                             Reference         Type        Pin     Net                  Time         Slack
+                                     Clock                                                                        
+------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[17]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[17]      9.946        4.136
+rsl_inst.genblk2\.rlol1_cnt[18]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[18]      9.946        4.136
+rsl_inst.genblk2\.rlols0_cnt[17]     PCSD|rxrefclk     FD1P3DX     D       rlols0_cnt_s[17]     9.946        4.170
+rsl_inst.genblk2\.rlol1_cnt[15]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[15]      9.946        4.197
+rsl_inst.genblk2\.rlol1_cnt[16]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[16]      9.946        4.197
+rsl_inst.genblk2\.rlols0_cnt[15]     PCSD|rxrefclk     FD1P3DX     D       rlols0_cnt_s[15]     9.946        4.231
+rsl_inst.genblk2\.rlols0_cnt[16]     PCSD|rxrefclk     FD1P3DX     D       rlols0_cnt_s[16]     9.946        4.231
+rsl_inst.genblk2\.rlol1_cnt[13]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[13]      9.946        4.258
+rsl_inst.genblk2\.rlol1_cnt[14]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[14]      9.946        4.258
+rsl_inst.genblk2\.rlols0_cnt[13]     PCSD|rxrefclk     FD1P3DX     D       rlols0_cnt_s[13]     9.946        4.292
+==================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.809
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.136
+
+    Number of logic level(s):                14
+    Starting point:                          rsl_inst.genblk2\.rlol1_cnt[14] / Q
+    Ending point:                            rsl_inst.genblk2\.rlol1_cnt[18] / D
+    The start point is clocked by            PCSD|rxrefclk [rising] on pin CK
+    The end   point is clocked by            PCSD|rxrefclk [rising] on pin CK
+
+Instance / Net                                         Pin      Pin               Arrival     No. of    
+Name                                      Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[14]           FD1P3DX      Q        Out     0.907     0.907       -         
+rlol1_cnt[14]                             Net          -        -       -         -           2         
+rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     Z        Out     0.606     1.513       -         
+rlol1_cnt_tc_1_10                         Net          -        -       -         -           1         
+rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     Z        Out     0.606     2.119       -         
+rlol1_cnt_tc_1_14                         Net          -        -       -         -           1         
+rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     Z        Out     0.768     2.887       -         
+rlol1_cnt_tc_1                            Net          -        -       -         -           6         
+rsl_inst.genblk2\.rxs_rst_RNIS0OP         ORCALUT4     A        In      0.000     2.887       -         
+rsl_inst.genblk2\.rxs_rst_RNIS0OP         ORCALUT4     Z        Out     0.837     3.724       -         
+rlol1_cnt                                 Net          -        -       -         -           20        
+rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.724       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.624       -         
+rlol1_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.624       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.685       -         
+rlol1_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.685       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.746       -         
+rlol1_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.746       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.807       -         
+rlol1_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.807       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.868       -         
+rlol1_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.868       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.929       -         
+rlol1_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.929       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.990       -         
+rlol1_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.990       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.051       -         
+rlol1_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.051       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.112       -         
+rlol1_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.112       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        S1       Out     0.698     5.809       -         
+rlol1_cnt_s[18]                           Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt[18]           FD1P3DX      D        In      0.000     5.809       -         
+========================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                                   Arrival           
+Instance      Reference     Type     Pin                Net              Time        Slack 
+              Clock                                                                        
+-------------------------------------------------------------------------------------------
+DCU0_inst     System        DCUA     CH0_FFS_RLOL       rx_cdr_lol_s     0.000       9.946 
+DCU0_inst     System        DCUA     CH0_FFS_RLOS       rx_los_low_s     0.000       9.946 
+DCU0_inst     System        DCUA     CH0_FF_TX_PCLK     tx_pclk          0.000       10.000
+===========================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                              Starting                                                       Required           
+Instance                      Reference     Type        Pin                 Net              Time         Slack 
+                              Clock                                                                             
+----------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol_p1     System        FD1S3DX     D                   rx_cdr_lol_s     9.946        9.946 
+rsl_inst.genblk2\.rlos_p1     System        FD1S3DX     D                   rx_los_low_s     9.946        9.946 
+DCU0_inst                     System        DCUA        CH0_FF_EBRD_CLK     tx_pclk          10.000       10.000
+DCU0_inst                     System        DCUA        CH0_FF_RXI_CLK      tx_pclk          10.000       10.000
+================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      0.000
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 9.946
+
+    Number of logic level(s):                0
+    Starting point:                          DCU0_inst / CH0_FFS_RLOL
+    Ending point:                            rsl_inst.genblk2\.rlol_p1 / D
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            PCSD|rxrefclk [rising] on pin CK
+
+Instance / Net                            Pin              Pin               Arrival     No. of    
+Name                          Type        Name             Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------------------
+DCU0_inst                     DCUA        CH0_FFS_RLOL     Out     0.000     0.000       -         
+rx_cdr_lol_s                  Net         -                -       -         -           2         
+rsl_inst.genblk2\.rlol_p1     FD1S3DX     D                In      0.000     0.000       -         
+===================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 92 of 24288 (0%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+CCU2C:          37
+DCUA:           1
+FD1P3BX:        4
+FD1P3DX:        42
+FD1S3BX:        10
+FD1S3DX:        36
+GSR:            1
+ORCALUT4:       63
+PFUMX:          2
+PUR:            1
+VHI:            2
+VLO:            2
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 32MB peak: 148MB)
+
+Process took 0h:00m:02s realtime, 0h:00m:02s cputime
+# Tue Apr 30 12:09:51 2019
+
+###########################################################]

diff --git a/gbe/cores/sgmii/PCSD/syn_results/PCSD.srr.db b/gbe/cores/sgmii/PCSD/syn_results/PCSD.srr.db
new file mode 100644 (file)
index 0000000..147c921
Binary files /dev/null and b/gbe/cores/sgmii/PCSD/syn_results/PCSD.srr.db differ

diff --git a/gbe/cores/sgmii/PCSD/syn_results/PCSD.srs b/gbe/cores/sgmii/PCSD/syn_results/PCSD.srs
new file mode 100644 (file)
index 0000000..a26742c
Binary files /dev/null and b/gbe/cores/sgmii/PCSD/syn_results/PCSD.srs differ

diff --git a/gbe/cores/sgmii/PCSD/syn_results/PCSD.vhm b/gbe/cores/sgmii/PCSD/syn_results/PCSD.vhm
new file mode 100644 (file)
index 0000000..6ce80ea
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/PCSD.vhm
@@ -0,0 +1,2765 @@
+--
+-- Written by Synplicity
+-- Product Version "M-2017.03L-SP1-1"
+-- Program "Synplify Pro", Mapper "maplat, Build 1796R"
+-- Tue Apr 30 12:09:50 2019
+--
+
+--
+-- Written by Synplify Pro version Build 1796R
+-- Tue Apr 30 12:09:50 2019
+--
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library synplify;
+use synplify.components.all;
+library pmi;
+use pmi.pmi_components.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity PCSDrsl_core_Z1_layer1 is
+port(
+  serdes_rst_dual_c :  in std_logic;
+  rx_serdes_rst_c :  in std_logic;
+  tx_serdes_rst_c :  in std_logic;
+  rsl_rx_pcs_rst_c :  out std_logic;
+  rx_pcs_rst_c :  in std_logic;
+  rsl_tx_pcs_rst_c :  out std_logic;
+  tx_pcs_rst_c :  in std_logic;
+  rsl_disable :  in std_logic;
+  rsl_tx_serdes_rst_c :  out std_logic;
+  pll_lol :  in std_logic;
+  pll_refclki :  in std_logic;
+  rx_cdr_lol_s :  in std_logic;
+  rx_los_low_s :  in std_logic;
+  rsl_rst :  in std_logic;
+  rxrefclk :  in std_logic;
+  rsl_rx_serdes_rst_c :  out std_logic;
+  rsl_serdes_rst_dual_c :  out std_logic);
+end PCSDrsl_core_Z1_layer1;
+
+architecture beh of PCSDrsl_core_Z1_layer1 is
+  signal PLOL0_CNT : std_logic_vector(2 downto 0);
+  signal PLOL0_CNT_3 : std_logic_vector(2 downto 0);
+  signal RXS_CNT_3 : std_logic_vector(1 downto 0);
+  signal RXS_CNT : std_logic_vector(1 downto 0);
+  signal RXS_CNT_QN : std_logic_vector(1 downto 0);
+  signal RLOS_DB_CNT : std_logic_vector(3 downto 0);
+  signal RLOS_DB_CNT_QN : std_logic_vector(3 downto 0);
+  signal RLOLS0_CNT_S : std_logic_vector(17 downto 0);
+  signal RLOLS0_CNT : std_logic_vector(17 downto 0);
+  signal RLOLS0_CNT_QN : std_logic_vector(17 downto 0);
+  signal RLOL_DB_CNT : std_logic_vector(3 downto 0);
+  signal RLOL_DB_CNT_QN : std_logic_vector(3 downto 0);
+  signal RLOL1_CNT_S : std_logic_vector(18 downto 0);
+  signal RLOL1_CNT : std_logic_vector(18 downto 0);
+  signal RLOL1_CNT_QN : std_logic_vector(18 downto 0);
+  signal TXS_CNT : std_logic_vector(1 downto 0);
+  signal TXS_CNT_QN : std_logic_vector(1 downto 0);
+  signal TXS_CNT_RNO : std_logic_vector(1 to 1);
+  signal TXP_CNT : std_logic_vector(1 downto 0);
+  signal TXP_CNT_QN : std_logic_vector(1 downto 0);
+  signal TXP_CNT_RNO : std_logic_vector(1 to 1);
+  signal PLOL_CNT_S : std_logic_vector(19 downto 0);
+  signal PLOL_CNT : std_logic_vector(19 downto 0);
+  signal PLOL_CNT_QN : std_logic_vector(19 downto 0);
+  signal PLOL0_CNT_QN : std_logic_vector(2 downto 0);
+  signal UN1_RLOL_DB_CNT_ZERO : std_logic_vector(0 to 0);
+  signal UN1_RLOS_DB_CNT_ZERO : std_logic_vector(0 to 0);
+  signal UN1_RLOL_DB_CNT_ZERO_BM : std_logic_vector(0 to 0);
+  signal UN1_RLOL_DB_CNT_ZERO_AM : std_logic_vector(0 to 0);
+  signal UN1_RLOS_DB_CNT_ZERO_BM : std_logic_vector(0 to 0);
+  signal UN1_RLOS_DB_CNT_ZERO_AM : std_logic_vector(0 to 0);
+  signal RLOL1_CNT_CRY : std_logic_vector(16 downto 0);
+  signal RLOL1_CNT_CRY_0_S0 : std_logic_vector(0 to 0);
+  signal RLOL1_CNT_CRY_0_COUT : std_logic_vector(17 to 17);
+  signal RLOLS0_CNT_CRY : std_logic_vector(16 downto 0);
+  signal RLOLS0_CNT_CRY_0_S0 : std_logic_vector(0 to 0);
+  signal RLOLS0_CNT_S_0_COUT : std_logic_vector(17 to 17);
+  signal RLOLS0_CNT_S_0_S1 : std_logic_vector(17 to 17);
+  signal PLOL_CNT_CRY : std_logic_vector(18 downto 0);
+  signal PLOL_CNT_CRY_0_S0 : std_logic_vector(0 to 0);
+  signal PLOL_CNT_S_0_COUT : std_logic_vector(19 to 19);
+  signal PLOL_CNT_S_0_S1 : std_logic_vector(19 to 19);
+  signal RSL_SERDES_RST_DUAL_C_6 : std_logic ;
+  signal RSL_RX_SERDES_RST_C_5 : std_logic ;
+  signal RLOS_DB_P1 : std_logic ;
+  signal RLOS_DB : std_logic ;
+  signal RXP_RST25 : std_logic ;
+  signal PLOL0_CNT9 : std_logic ;
+  signal WAITA_PLOL0 : std_logic ;
+  signal RLOL1_CNT_TC_1 : std_logic ;
+  signal RXS_RST : std_logic ;
+  signal \RLOL1_CNT_\ : std_logic ;
+  signal WAITA_RLOLS06 : std_logic ;
+  signal UN1_RLOLS0_CNT_TC : std_logic ;
+  signal WAITA_RLOLS0 : std_logic ;
+  signal WAITA_RLOLS0_QN : std_logic ;
+  signal VCC : std_logic ;
+  signal WAIT_CALIB_RNO : std_logic ;
+  signal UN1_RLOS_FEDGE_1 : std_logic ;
+  signal WAIT_CALIB : std_logic ;
+  signal WAIT_CALIB_QN : std_logic ;
+  signal RXS_RST6 : std_logic ;
+  signal UN1_RXS_CNT_TC : std_logic ;
+  signal RXS_RST_QN : std_logic ;
+  signal UN2_RLOS_REDGE_1_I : std_logic ;
+  signal RXP_RST2 : std_logic ;
+  signal RXP_RST2_QN : std_logic ;
+  signal RLOS_P1 : std_logic ;
+  signal RLOS_P2 : std_logic ;
+  signal RLOS_P2_QN : std_logic ;
+  signal RLOS_P1_QN : std_logic ;
+  signal RLOS_DB_P1_QN : std_logic ;
+  signal RLOS_DB_CNT_AXB_0 : std_logic ;
+  signal RLOS_DB_CNT_CRY_1_0_S0 : std_logic ;
+  signal RLOS_DB_CNT_CRY_1_0_S1 : std_logic ;
+  signal RLOS_DB_CNT_S_3_0_S0 : std_logic ;
+  signal UN1_RLOS_DB_CNT_MAX : std_logic ;
+  signal RLOS_DB_QN : std_logic ;
+  signal RLOLS0_CNTE : std_logic ;
+  signal RLOL_P1 : std_logic ;
+  signal RLOL_P2 : std_logic ;
+  signal RLOL_P2_QN : std_logic ;
+  signal RLOL_P1_QN : std_logic ;
+  signal RLOL_DB : std_logic ;
+  signal RLOL_DB_P1 : std_logic ;
+  signal RLOL_DB_P1_QN : std_logic ;
+  signal RLOL_DB_CNT_AXB_0 : std_logic ;
+  signal RLOL_DB_CNT_CRY_1_0_S0 : std_logic ;
+  signal RLOL_DB_CNT_CRY_1_0_S1 : std_logic ;
+  signal RLOL_DB_CNT_S_3_0_S0 : std_logic ;
+  signal UN1_RLOL_DB_CNT_MAX : std_logic ;
+  signal RLOL_DB_QN : std_logic ;
+  signal RLOL1_CNTE : std_logic ;
+  signal PLOL_FEDGE : std_logic ;
+  signal UN1_PLOL0_CNT_TC_1_I : std_logic ;
+  signal WAITA_PLOL0_QN : std_logic ;
+  signal UN1_PLOL_CNT_TC : std_logic ;
+  signal UN2_PLOL_CNT_TC : std_logic ;
+  signal TXS_RST : std_logic ;
+  signal TXS_RST_QN : std_logic ;
+  signal N_12_I : std_logic ;
+  signal UN9_PLOL0_CNT_TC : std_logic ;
+  signal UN1_PLOL0_CNT_TC_1 : std_logic ;
+  signal TXP_RST : std_logic ;
+  signal TXP_RST_QN : std_logic ;
+  signal N_13_I : std_logic ;
+  signal PLL_LOL_P2 : std_logic ;
+  signal PLL_LOL_P3 : std_logic ;
+  signal PLL_LOL_P3_QN : std_logic ;
+  signal PLL_LOL_P1 : std_logic ;
+  signal PLL_LOL_P2_QN : std_logic ;
+  signal PLL_LOL_P1_QN : std_logic ;
+  signal RLOLS0_CNT_TC_1 : std_logic ;
+  signal RLOS_REDGE : std_logic ;
+  signal RLOLS0_CNT11_0 : std_logic ;
+  signal RSL_TX_SERDES_RST_C_4 : std_logic ;
+  signal \PLOL_CNT_\ : std_logic ;
+  signal \RLOLS0_CNT_\ : std_logic ;
+  signal UN8_RXS_CNT_TC : std_logic ;
+  signal UN1_PLOL_CNT_TC_11 : std_logic ;
+  signal UN1_PLOL_CNT_TC_12 : std_logic ;
+  signal UN1_PLOL_CNT_TC_13 : std_logic ;
+  signal UN1_PLOL_CNT_TC_14 : std_logic ;
+  signal RLOLS0_CNT_TC_1_10 : std_logic ;
+  signal RLOLS0_CNT_TC_1_11 : std_logic ;
+  signal RLOLS0_CNT_TC_1_12 : std_logic ;
+  signal RLOLS0_CNT_TC_1_13 : std_logic ;
+  signal RLOL1_CNT_TC_1_11 : std_logic ;
+  signal RLOL1_CNT_TC_1_12 : std_logic ;
+  signal RLOL1_CNT_TC_1_13 : std_logic ;
+  signal RLOL1_CNT_TC_1_14 : std_logic ;
+  signal CO0_2 : std_logic ;
+  signal RLOLS0_CNT_TC_1_9 : std_logic ;
+  signal UN1_PLOL_CNT_TC_10 : std_logic ;
+  signal RLOL1_CNT_TC_1_10 : std_logic ;
+  signal RLOS_DB_CNT_CRY_0 : std_logic ;
+  signal RLOS_DB_CNT_CRY_0_0_S0 : std_logic ;
+  signal RLOS_DB_CNT_CRY_0_0_S1 : std_logic ;
+  signal RLOS_DB_CNT_CRY_2 : std_logic ;
+  signal RLOS_DB_CNT_S_3_0_COUT : std_logic ;
+  signal RLOS_DB_CNT_S_3_0_S1 : std_logic ;
+  signal RLOL_DB_CNT_CRY_0 : std_logic ;
+  signal RLOL_DB_CNT_CRY_0_0_S0 : std_logic ;
+  signal RLOL_DB_CNT_CRY_0_0_S1 : std_logic ;
+  signal RLOL_DB_CNT_CRY_2 : std_logic ;
+  signal RLOL_DB_CNT_S_3_0_COUT : std_logic ;
+  signal RLOL_DB_CNT_S_3_0_S1 : std_logic ;
+  signal GND : std_logic ;
+  signal N_1 : std_logic ;
+  signal N_2 : std_logic ;
+  signal N_3 : std_logic ;
+  signal N_4 : std_logic ;
+  signal N_5 : std_logic ;
+begin
+\GENBLK2.RXP_RST2_RNO\: LUT4 
+generic map(
+  init => X"EFEE"
+)
+port map (
+  A => RSL_SERDES_RST_DUAL_C_6,
+  B => RSL_RX_SERDES_RST_C_5,
+  C => RLOS_DB_P1,
+  D => RLOS_DB,
+  Z => RXP_RST25);
+\GENBLK1.PLOL0_CNT_RNO[1]\: LUT4 
+generic map(
+  init => X"1222"
+)
+port map (
+  A => PLOL0_CNT(1),
+  B => PLOL0_CNT9,
+  C => WAITA_PLOL0,
+  D => PLOL0_CNT(0),
+  Z => PLOL0_CNT_3(1));
+\GENBLK2.RXS_RST_RNIS0OP\: LUT4 
+generic map(
+  init => X"1011"
+)
+port map (
+  A => RLOL1_CNT_TC_1,
+  B => RXS_RST,
+  C => RLOS_DB_P1,
+  D => RLOS_DB,
+  Z => \RLOL1_CNT_\);
+\GENBLK2.WAITA_RLOLS0_REG_Z428\: FD1P3DX port map (
+    D => WAITA_RLOLS06,
+    SP => UN1_RLOLS0_CNT_TC,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => WAITA_RLOLS0);
+\GENBLK2.WAIT_CALIB_REG_Z430\: FD1P3BX port map (
+    D => WAIT_CALIB_RNO,
+    SP => UN1_RLOS_FEDGE_1,
+    CK => rxrefclk,
+    PD => rsl_rst,
+    Q => WAIT_CALIB);
+\GENBLK2.RXS_RST_REG_Z432\: FD1P3DX port map (
+    D => RXS_RST6,
+    SP => UN1_RXS_CNT_TC,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RXS_RST);
+\GENBLK2.RXS_CNT[0]_REG_Z434\: FD1S3DX port map (
+    D => RXS_CNT_3(0),
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RXS_CNT(0));
+\GENBLK2.RXS_CNT[1]_REG_Z436\: FD1S3DX port map (
+    D => RXS_CNT_3(1),
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RXS_CNT(1));
+\GENBLK2.RXP_RST2_REG_Z438\: FD1P3BX port map (
+    D => RXP_RST25,
+    SP => UN2_RLOS_REDGE_1_I,
+    CK => rxrefclk,
+    PD => rsl_rst,
+    Q => RXP_RST2);
+\GENBLK2.RLOS_P2_REG_Z440\: FD1S3DX port map (
+    D => RLOS_P1,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOS_P2);
+\GENBLK2.RLOS_P1_REG_Z442\: FD1S3DX port map (
+    D => rx_los_low_s,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOS_P1);
+\GENBLK2.RLOS_DB_P1_REG_Z444\: FD1S3BX port map (
+    D => RLOS_DB,
+    CK => rxrefclk,
+    PD => rsl_rst,
+    Q => RLOS_DB_P1);
+\GENBLK2.RLOS_DB_CNT[0]_REG_Z446\: FD1S3BX port map (
+    D => RLOS_DB_CNT_AXB_0,
+    CK => rxrefclk,
+    PD => rsl_rst,
+    Q => RLOS_DB_CNT(0));
+\GENBLK2.RLOS_DB_CNT[1]_REG_Z448\: FD1S3BX port map (
+    D => RLOS_DB_CNT_CRY_1_0_S0,
+    CK => rxrefclk,
+    PD => rsl_rst,
+    Q => RLOS_DB_CNT(1));
+\GENBLK2.RLOS_DB_CNT[2]_REG_Z450\: FD1S3BX port map (
+    D => RLOS_DB_CNT_CRY_1_0_S1,
+    CK => rxrefclk,
+    PD => rsl_rst,
+    Q => RLOS_DB_CNT(2));
+\GENBLK2.RLOS_DB_CNT[3]_REG_Z452\: FD1S3BX port map (
+    D => RLOS_DB_CNT_S_3_0_S0,
+    CK => rxrefclk,
+    PD => rsl_rst,
+    Q => RLOS_DB_CNT(3));
+\GENBLK2.RLOS_DB_REG_Z454\: FD1P3BX port map (
+    D => RLOS_DB_CNT(3),
+    SP => UN1_RLOS_DB_CNT_MAX,
+    CK => rxrefclk,
+    PD => rsl_rst,
+    Q => RLOS_DB);
+\GENBLK2.RLOLS0_CNT[0]_REG_Z456\: FD1P3DX port map (
+    D => RLOLS0_CNT_S(0),
+    SP => RLOLS0_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOLS0_CNT(0));
+\GENBLK2.RLOLS0_CNT[1]_REG_Z458\: FD1P3DX port map (
+    D => RLOLS0_CNT_S(1),
+    SP => RLOLS0_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOLS0_CNT(1));
+\GENBLK2.RLOLS0_CNT[2]_REG_Z460\: FD1P3DX port map (
+    D => RLOLS0_CNT_S(2),
+    SP => RLOLS0_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOLS0_CNT(2));
+\GENBLK2.RLOLS0_CNT[3]_REG_Z462\: FD1P3DX port map (
+    D => RLOLS0_CNT_S(3),
+    SP => RLOLS0_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOLS0_CNT(3));
+\GENBLK2.RLOLS0_CNT[4]_REG_Z464\: FD1P3DX port map (
+    D => RLOLS0_CNT_S(4),
+    SP => RLOLS0_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOLS0_CNT(4));
+\GENBLK2.RLOLS0_CNT[5]_REG_Z466\: FD1P3DX port map (
+    D => RLOLS0_CNT_S(5),
+    SP => RLOLS0_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOLS0_CNT(5));
+\GENBLK2.RLOLS0_CNT[6]_REG_Z468\: FD1P3DX port map (
+    D => RLOLS0_CNT_S(6),
+    SP => RLOLS0_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOLS0_CNT(6));
+\GENBLK2.RLOLS0_CNT[7]_REG_Z470\: FD1P3DX port map (
+    D => RLOLS0_CNT_S(7),
+    SP => RLOLS0_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOLS0_CNT(7));
+\GENBLK2.RLOLS0_CNT[8]_REG_Z472\: FD1P3DX port map (
+    D => RLOLS0_CNT_S(8),
+    SP => RLOLS0_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOLS0_CNT(8));
+\GENBLK2.RLOLS0_CNT[9]_REG_Z474\: FD1P3DX port map (
+    D => RLOLS0_CNT_S(9),
+    SP => RLOLS0_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOLS0_CNT(9));
+\GENBLK2.RLOLS0_CNT[10]_REG_Z476\: FD1P3DX port map (
+    D => RLOLS0_CNT_S(10),
+    SP => RLOLS0_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOLS0_CNT(10));
+\GENBLK2.RLOLS0_CNT[11]_REG_Z478\: FD1P3DX port map (
+    D => RLOLS0_CNT_S(11),
+    SP => RLOLS0_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOLS0_CNT(11));
+\GENBLK2.RLOLS0_CNT[12]_REG_Z480\: FD1P3DX port map (
+    D => RLOLS0_CNT_S(12),
+    SP => RLOLS0_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOLS0_CNT(12));
+\GENBLK2.RLOLS0_CNT[13]_REG_Z482\: FD1P3DX port map (
+    D => RLOLS0_CNT_S(13),
+    SP => RLOLS0_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOLS0_CNT(13));
+\GENBLK2.RLOLS0_CNT[14]_REG_Z484\: FD1P3DX port map (
+    D => RLOLS0_CNT_S(14),
+    SP => RLOLS0_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOLS0_CNT(14));
+\GENBLK2.RLOLS0_CNT[15]_REG_Z486\: FD1P3DX port map (
+    D => RLOLS0_CNT_S(15),
+    SP => RLOLS0_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOLS0_CNT(15));
+\GENBLK2.RLOLS0_CNT[16]_REG_Z488\: FD1P3DX port map (
+    D => RLOLS0_CNT_S(16),
+    SP => RLOLS0_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOLS0_CNT(16));
+\GENBLK2.RLOLS0_CNT[17]_REG_Z490\: FD1P3DX port map (
+    D => RLOLS0_CNT_S(17),
+    SP => RLOLS0_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOLS0_CNT(17));
+\GENBLK2.RLOL_P2_REG_Z492\: FD1S3DX port map (
+    D => RLOL_P1,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOL_P2);
+\GENBLK2.RLOL_P1_REG_Z494\: FD1S3DX port map (
+    D => rx_cdr_lol_s,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOL_P1);
+\GENBLK2.RLOL_DB_P1_REG_Z496\: FD1S3BX port map (
+    D => RLOL_DB,
+    CK => rxrefclk,
+    PD => rsl_rst,
+    Q => RLOL_DB_P1);
+\GENBLK2.RLOL_DB_CNT[0]_REG_Z498\: FD1S3BX port map (
+    D => RLOL_DB_CNT_AXB_0,
+    CK => rxrefclk,
+    PD => rsl_rst,
+    Q => RLOL_DB_CNT(0));
+\GENBLK2.RLOL_DB_CNT[1]_REG_Z500\: FD1S3BX port map (
+    D => RLOL_DB_CNT_CRY_1_0_S0,
+    CK => rxrefclk,
+    PD => rsl_rst,
+    Q => RLOL_DB_CNT(1));
+\GENBLK2.RLOL_DB_CNT[2]_REG_Z502\: FD1S3BX port map (
+    D => RLOL_DB_CNT_CRY_1_0_S1,
+    CK => rxrefclk,
+    PD => rsl_rst,
+    Q => RLOL_DB_CNT(2));
+\GENBLK2.RLOL_DB_CNT[3]_REG_Z504\: FD1S3BX port map (
+    D => RLOL_DB_CNT_S_3_0_S0,
+    CK => rxrefclk,
+    PD => rsl_rst,
+    Q => RLOL_DB_CNT(3));
+\GENBLK2.RLOL_DB_REG_Z506\: FD1P3BX port map (
+    D => RLOL_DB_CNT(3),
+    SP => UN1_RLOL_DB_CNT_MAX,
+    CK => rxrefclk,
+    PD => rsl_rst,
+    Q => RLOL_DB);
+\GENBLK2.RLOL1_CNT[0]_REG_Z508\: FD1P3DX port map (
+    D => RLOL1_CNT_S(0),
+    SP => RLOL1_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOL1_CNT(0));
+\GENBLK2.RLOL1_CNT[1]_REG_Z510\: FD1P3DX port map (
+    D => RLOL1_CNT_S(1),
+    SP => RLOL1_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOL1_CNT(1));
+\GENBLK2.RLOL1_CNT[2]_REG_Z512\: FD1P3DX port map (
+    D => RLOL1_CNT_S(2),
+    SP => RLOL1_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOL1_CNT(2));
+\GENBLK2.RLOL1_CNT[3]_REG_Z514\: FD1P3DX port map (
+    D => RLOL1_CNT_S(3),
+    SP => RLOL1_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOL1_CNT(3));
+\GENBLK2.RLOL1_CNT[4]_REG_Z516\: FD1P3DX port map (
+    D => RLOL1_CNT_S(4),
+    SP => RLOL1_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOL1_CNT(4));
+\GENBLK2.RLOL1_CNT[5]_REG_Z518\: FD1P3DX port map (
+    D => RLOL1_CNT_S(5),
+    SP => RLOL1_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOL1_CNT(5));
+\GENBLK2.RLOL1_CNT[6]_REG_Z520\: FD1P3DX port map (
+    D => RLOL1_CNT_S(6),
+    SP => RLOL1_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOL1_CNT(6));
+\GENBLK2.RLOL1_CNT[7]_REG_Z522\: FD1P3DX port map (
+    D => RLOL1_CNT_S(7),
+    SP => RLOL1_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOL1_CNT(7));
+\GENBLK2.RLOL1_CNT[8]_REG_Z524\: FD1P3DX port map (
+    D => RLOL1_CNT_S(8),
+    SP => RLOL1_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOL1_CNT(8));
+\GENBLK2.RLOL1_CNT[9]_REG_Z526\: FD1P3DX port map (
+    D => RLOL1_CNT_S(9),
+    SP => RLOL1_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOL1_CNT(9));
+\GENBLK2.RLOL1_CNT[10]_REG_Z528\: FD1P3DX port map (
+    D => RLOL1_CNT_S(10),
+    SP => RLOL1_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOL1_CNT(10));
+\GENBLK2.RLOL1_CNT[11]_REG_Z530\: FD1P3DX port map (
+    D => RLOL1_CNT_S(11),
+    SP => RLOL1_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOL1_CNT(11));
+\GENBLK2.RLOL1_CNT[12]_REG_Z532\: FD1P3DX port map (
+    D => RLOL1_CNT_S(12),
+    SP => RLOL1_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOL1_CNT(12));
+\GENBLK2.RLOL1_CNT[13]_REG_Z534\: FD1P3DX port map (
+    D => RLOL1_CNT_S(13),
+    SP => RLOL1_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOL1_CNT(13));
+\GENBLK2.RLOL1_CNT[14]_REG_Z536\: FD1P3DX port map (
+    D => RLOL1_CNT_S(14),
+    SP => RLOL1_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOL1_CNT(14));
+\GENBLK2.RLOL1_CNT[15]_REG_Z538\: FD1P3DX port map (
+    D => RLOL1_CNT_S(15),
+    SP => RLOL1_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOL1_CNT(15));
+\GENBLK2.RLOL1_CNT[16]_REG_Z540\: FD1P3DX port map (
+    D => RLOL1_CNT_S(16),
+    SP => RLOL1_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOL1_CNT(16));
+\GENBLK2.RLOL1_CNT[17]_REG_Z542\: FD1P3DX port map (
+    D => RLOL1_CNT_S(17),
+    SP => RLOL1_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOL1_CNT(17));
+\GENBLK2.RLOL1_CNT[18]_REG_Z544\: FD1P3DX port map (
+    D => RLOL1_CNT_S(18),
+    SP => RLOL1_CNTE,
+    CK => rxrefclk,
+    CD => rsl_rst,
+    Q => RLOL1_CNT(18));
+\GENBLK1.WAITA_PLOL0_REG_Z546\: FD1P3DX port map (
+    D => PLOL_FEDGE,
+    SP => UN1_PLOL0_CNT_TC_1_I,
+    CK => pll_refclki,
+    CD => rsl_rst,
+    Q => WAITA_PLOL0);
+\GENBLK1.TXS_RST_REG_Z548\: FD1P3DX port map (
+    D => UN1_PLOL_CNT_TC,
+    SP => UN2_PLOL_CNT_TC,
+    CK => pll_refclki,
+    CD => rsl_rst,
+    Q => TXS_RST);
+\GENBLK1.TXS_CNT[0]_REG_Z550\: FD1S3DX port map (
+    D => N_12_I,
+    CK => pll_refclki,
+    CD => rsl_rst,
+    Q => TXS_CNT(0));
+\GENBLK1.TXS_CNT[1]_REG_Z552\: FD1S3DX port map (
+    D => TXS_CNT_RNO(1),
+    CK => pll_refclki,
+    CD => rsl_rst,
+    Q => TXS_CNT(1));
+\GENBLK1.TXP_RST_REG_Z554\: FD1P3DX port map (
+    D => UN9_PLOL0_CNT_TC,
+    SP => UN1_PLOL0_CNT_TC_1,
+    CK => pll_refclki,
+    CD => rsl_rst,
+    Q => TXP_RST);
+\GENBLK1.TXP_CNT[0]_REG_Z556\: FD1S3DX port map (
+    D => N_13_I,
+    CK => pll_refclki,
+    CD => rsl_rst,
+    Q => TXP_CNT(0));
+\GENBLK1.TXP_CNT[1]_REG_Z558\: FD1S3DX port map (
+    D => TXP_CNT_RNO(1),
+    CK => pll_refclki,
+    CD => rsl_rst,
+    Q => TXP_CNT(1));
+\GENBLK1.PLOL_CNT[0]_REG_Z560\: FD1S3DX port map (
+    D => PLOL_CNT_S(0),
+    CK => pll_refclki,
+    CD => rsl_rst,
+    Q => PLOL_CNT(0));
+\GENBLK1.PLOL_CNT[1]_REG_Z562\: FD1S3DX port map (
+    D => PLOL_CNT_S(1),
+    CK => pll_refclki,
+    CD => rsl_rst,
+    Q => PLOL_CNT(1));
+\GENBLK1.PLOL_CNT[2]_REG_Z564\: FD1S3DX port map (
+    D => PLOL_CNT_S(2),
+    CK => pll_refclki,
+    CD => rsl_rst,
+    Q => PLOL_CNT(2));
+\GENBLK1.PLOL_CNT[3]_REG_Z566\: FD1S3DX port map (
+    D => PLOL_CNT_S(3),
+    CK => pll_refclki,
+    CD => rsl_rst,
+    Q => PLOL_CNT(3));
+\GENBLK1.PLOL_CNT[4]_REG_Z568\: FD1S3DX port map (
+    D => PLOL_CNT_S(4),
+    CK => pll_refclki,
+    CD => rsl_rst,
+    Q => PLOL_CNT(4));
+\GENBLK1.PLOL_CNT[5]_REG_Z570\: FD1S3DX port map (
+    D => PLOL_CNT_S(5),
+    CK => pll_refclki,
+    CD => rsl_rst,
+    Q => PLOL_CNT(5));
+\GENBLK1.PLOL_CNT[6]_REG_Z572\: FD1S3DX port map (
+    D => PLOL_CNT_S(6),
+    CK => pll_refclki,
+    CD => rsl_rst,
+    Q => PLOL_CNT(6));
+\GENBLK1.PLOL_CNT[7]_REG_Z574\: FD1S3DX port map (
+    D => PLOL_CNT_S(7),
+    CK => pll_refclki,
+    CD => rsl_rst,
+    Q => PLOL_CNT(7));
+\GENBLK1.PLOL_CNT[8]_REG_Z576\: FD1S3DX port map (
+    D => PLOL_CNT_S(8),
+    CK => pll_refclki,
+    CD => rsl_rst,
+    Q => PLOL_CNT(8));
+\GENBLK1.PLOL_CNT[9]_REG_Z578\: FD1S3DX port map (
+    D => PLOL_CNT_S(9),
+    CK => pll_refclki,
+    CD => rsl_rst,
+    Q => PLOL_CNT(9));
+\GENBLK1.PLOL_CNT[10]_REG_Z580\: FD1S3DX port map (
+    D => PLOL_CNT_S(10),
+    CK => pll_refclki,
+    CD => rsl_rst,
+    Q => PLOL_CNT(10));
+\GENBLK1.PLOL_CNT[11]_REG_Z582\: FD1S3DX port map (
+    D => PLOL_CNT_S(11),
+    CK => pll_refclki,
+    CD => rsl_rst,
+    Q => PLOL_CNT(11));
+\GENBLK1.PLOL_CNT[12]_REG_Z584\: FD1S3DX port map (
+    D => PLOL_CNT_S(12),
+    CK => pll_refclki,
+    CD => rsl_rst,
+    Q => PLOL_CNT(12));
+\GENBLK1.PLOL_CNT[13]_REG_Z586\: FD1S3DX port map (
+    D => PLOL_CNT_S(13),
+    CK => pll_refclki,
+    CD => rsl_rst,
+    Q => PLOL_CNT(13));
+\GENBLK1.PLOL_CNT[14]_REG_Z588\: FD1S3DX port map (
+    D => PLOL_CNT_S(14),
+    CK => pll_refclki,
+    CD => rsl_rst,
+    Q => PLOL_CNT(14));
+\GENBLK1.PLOL_CNT[15]_REG_Z590\: FD1S3DX port map (
+    D => PLOL_CNT_S(15),
+    CK => pll_refclki,
+    CD => rsl_rst,
+    Q => PLOL_CNT(15));
+\GENBLK1.PLOL_CNT[16]_REG_Z592\: FD1S3DX port map (
+    D => PLOL_CNT_S(16),
+    CK => pll_refclki,
+    CD => rsl_rst,
+    Q => PLOL_CNT(16));
+\GENBLK1.PLOL_CNT[17]_REG_Z594\: FD1S3DX port map (
+    D => PLOL_CNT_S(17),
+    CK => pll_refclki,
+    CD => rsl_rst,
+    Q => PLOL_CNT(17));
+\GENBLK1.PLOL_CNT[18]_REG_Z596\: FD1S3DX port map (
+    D => PLOL_CNT_S(18),
+    CK => pll_refclki,
+    CD => rsl_rst,
+    Q => PLOL_CNT(18));
+\GENBLK1.PLOL_CNT[19]_REG_Z598\: FD1S3DX port map (
+    D => PLOL_CNT_S(19),
+    CK => pll_refclki,
+    CD => rsl_rst,
+    Q => PLOL_CNT(19));
+\GENBLK1.PLOL0_CNT[0]_REG_Z600\: FD1S3DX port map (
+    D => PLOL0_CNT_3(0),
+    CK => pll_refclki,
+    CD => rsl_rst,
+    Q => PLOL0_CNT(0));
+\GENBLK1.PLOL0_CNT[1]_REG_Z602\: FD1S3DX port map (
+    D => PLOL0_CNT_3(1),
+    CK => pll_refclki,
+    CD => rsl_rst,
+    Q => PLOL0_CNT(1));
+\GENBLK1.PLOL0_CNT[2]_REG_Z604\: FD1S3DX port map (
+    D => PLOL0_CNT_3(2),
+    CK => pll_refclki,
+    CD => rsl_rst,
+    Q => PLOL0_CNT(2));
+\GENBLK1.PLL_LOL_P3_REG_Z606\: FD1S3DX port map (
+    D => PLL_LOL_P2,
+    CK => pll_refclki,
+    CD => rsl_rst,
+    Q => PLL_LOL_P3);
+\GENBLK1.PLL_LOL_P2_REG_Z608\: FD1S3DX port map (
+    D => PLL_LOL_P1,
+    CK => pll_refclki,
+    CD => rsl_rst,
+    Q => PLL_LOL_P2);
+\GENBLK1.PLL_LOL_P1_REG_Z610\: FD1S3DX port map (
+    D => pll_lol,
+    CK => pll_refclki,
+    CD => rsl_rst,
+    Q => PLL_LOL_P1);
+\GENBLK1.TXS_CNT_RNO[0]\: LUT4 
+generic map(
+  init => X"A6A6"
+)
+port map (
+  A => TXS_CNT(0),
+  B => TXS_RST,
+  C => UN1_PLOL_CNT_TC,
+  D => VCC,
+  Z => N_12_I);
+\GENBLK1.TXS_CNT_RNO[1]\: LUT4 
+generic map(
+  init => X"CC6C"
+)
+port map (
+  A => TXS_CNT(0),
+  B => TXS_CNT(1),
+  C => TXS_RST,
+  D => UN1_PLOL_CNT_TC,
+  Z => TXS_CNT_RNO(1));
+\GENBLK2.RXP_RST2_RNO_0\: LUT4 
+generic map(
+  init => X"FFFE"
+)
+port map (
+  A => RLOLS0_CNT_TC_1,
+  B => RLOS_REDGE,
+  C => RSL_RX_SERDES_RST_C_5,
+  D => RSL_SERDES_RST_DUAL_C_6,
+  Z => UN2_RLOS_REDGE_1_I);
+\GENBLK2.WAITA_RLOLS0_RNI266C\: LUT4 
+generic map(
+  init => X"FEFE"
+)
+port map (
+  A => RLOLS0_CNT11_0,
+  B => WAITA_RLOLS0,
+  C => RLOLS0_CNT_TC_1,
+  D => VCC,
+  Z => RLOLS0_CNTE);
+\GENBLK2.WAIT_CALIB_RNIKRP81\: LUT4 
+generic map(
+  init => X"FFFE"
+)
+port map (
+  A => RXS_RST,
+  B => WAIT_CALIB,
+  C => RLOL1_CNT_TC_1,
+  D => RLOS_REDGE,
+  Z => RLOL1_CNTE);
+\GENBLK2.RXS_RST6\: LUT4 
+generic map(
+  init => X"2020"
+)
+port map (
+  A => RLOL_DB,
+  B => RLOS_DB,
+  C => RLOL1_CNT_TC_1,
+  D => VCC,
+  Z => RXS_RST6);
+\GENBLK1.PLOL_CNT11_I\: LUT4 
+generic map(
+  init => X"0202"
+)
+port map (
+  A => PLL_LOL_P2,
+  B => UN1_PLOL_CNT_TC,
+  C => RSL_TX_SERDES_RST_C_4,
+  D => VCC,
+  Z => \PLOL_CNT_\);
+\GENBLK2.RLOLS0_CNT11_I\: LUT4 
+generic map(
+  init => X"1111"
+)
+port map (
+  A => RLOLS0_CNT11_0,
+  B => RLOLS0_CNT_TC_1,
+  C => VCC,
+  D => VCC,
+  Z => \RLOLS0_CNT_\);
+\GENBLK2.UN1_RXS_CNT_TC\: LUT4 
+generic map(
+  init => X"FEFC"
+)
+port map (
+  A => RLOL_DB,
+  B => RLOS_DB,
+  C => UN8_RXS_CNT_TC,
+  D => RLOL1_CNT_TC_1,
+  Z => UN1_RXS_CNT_TC);
+\GENBLK2.WAIT_CALIB_RNO\: LUT4 
+generic map(
+  init => X"A3A3"
+)
+port map (
+  A => RLOL_DB,
+  B => RLOS_DB,
+  C => RLOL1_CNT_TC_1,
+  D => VCC,
+  Z => WAIT_CALIB_RNO);
+\GENBLK1.UN2_PLOL_CNT_TC\: LUT4 
+generic map(
+  init => X"F8F8"
+)
+port map (
+  A => TXS_CNT(0),
+  B => TXS_CNT(1),
+  C => UN1_PLOL_CNT_TC,
+  D => VCC,
+  Z => UN2_PLOL_CNT_TC);
+\GENBLK2.UN1_RLOLS0_CNT_TC\: LUT4 
+generic map(
+  init => X"FEFE"
+)
+port map (
+  A => RLOLS0_CNT11_0,
+  B => WAITA_RLOLS06,
+  C => RLOLS0_CNT_TC_1,
+  D => VCC,
+  Z => UN1_RLOLS0_CNT_TC);
+\GENBLK2.UN1_RLOS_FEDGE_1\: LUT4 
+generic map(
+  init => X"F6F6"
+)
+port map (
+  A => RLOS_DB,
+  B => RLOS_DB_P1,
+  C => RLOL1_CNT_TC_1,
+  D => VCC,
+  Z => UN1_RLOS_FEDGE_1);
+\GENBLK1.TXP_CNT_RNO[0]\: LUT4 
+generic map(
+  init => X"A6A6"
+)
+port map (
+  A => TXP_CNT(0),
+  B => TXP_RST,
+  C => UN9_PLOL0_CNT_TC,
+  D => VCC,
+  Z => N_13_I);
+\GENBLK1.TXP_CNT_RNO[1]\: LUT4 
+generic map(
+  init => X"CC6C"
+)
+port map (
+  A => TXP_CNT(0),
+  B => TXP_CNT(1),
+  C => TXP_RST,
+  D => UN9_PLOL0_CNT_TC,
+  Z => TXP_CNT_RNO(1));
+\GENBLK1.UN1_PLOL_CNT_TC\: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+  A => UN1_PLOL_CNT_TC_11,
+  B => UN1_PLOL_CNT_TC_12,
+  C => UN1_PLOL_CNT_TC_13,
+  D => UN1_PLOL_CNT_TC_14,
+  Z => UN1_PLOL_CNT_TC);
+RLOLS0_CNT_TC_1_Z627: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+  A => RLOLS0_CNT_TC_1_10,
+  B => RLOLS0_CNT_TC_1_11,
+  C => RLOLS0_CNT_TC_1_12,
+  D => RLOLS0_CNT_TC_1_13,
+  Z => RLOLS0_CNT_TC_1);
+RLOL1_CNT_TC_1_Z628: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+  A => RLOL1_CNT_TC_1_11,
+  B => RLOL1_CNT_TC_1_12,
+  C => RLOL1_CNT_TC_1_13,
+  D => RLOL1_CNT_TC_1_14,
+  Z => RLOL1_CNT_TC_1);
+\UN1_GENBLK2.RLOL_DB_CNT_AXB_0\: LUT4 
+generic map(
+  init => X"9999"
+)
+port map (
+  A => RLOL_DB_CNT(0),
+  B => UN1_RLOL_DB_CNT_ZERO(0),
+  C => VCC,
+  D => VCC,
+  Z => RLOL_DB_CNT_AXB_0);
+\UN1_GENBLK2.RLOS_DB_CNT_AXB_0\: LUT4 
+generic map(
+  init => X"9999"
+)
+port map (
+  A => RLOS_DB_CNT(0),
+  B => UN1_RLOS_DB_CNT_ZERO(0),
+  C => VCC,
+  D => VCC,
+  Z => RLOS_DB_CNT_AXB_0);
+\GENBLK1.WAITA_PLOL0_RNO\: LUT4 
+generic map(
+  init => X"F6F6"
+)
+port map (
+  A => PLL_LOL_P2,
+  B => PLL_LOL_P3,
+  C => UN9_PLOL0_CNT_TC,
+  D => VCC,
+  Z => UN1_PLOL0_CNT_TC_1_I);
+\GENBLK1.PLOL0_CNT_3[2]\: LUT4 
+generic map(
+  init => X"1320"
+)
+port map (
+  A => CO0_2,
+  B => PLOL0_CNT9,
+  C => PLOL0_CNT(1),
+  D => PLOL0_CNT(2),
+  Z => PLOL0_CNT_3(2));
+\GENBLK1.PLOL0_CNT_3[0]\: LUT4 
+generic map(
+  init => X"1414"
+)
+port map (
+  A => PLOL0_CNT9,
+  B => PLOL0_CNT(0),
+  C => WAITA_PLOL0,
+  D => VCC,
+  Z => PLOL0_CNT_3(0));
+\UN1_RLOL_DB_CNT_ZERO_BM[0]_Z634\: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+  A => RLOL_DB_CNT(0),
+  B => RLOL_DB_CNT(1),
+  C => RLOL_DB_CNT(2),
+  D => RLOL_DB_CNT(3),
+  Z => UN1_RLOL_DB_CNT_ZERO_BM(0));
+\UN1_RLOL_DB_CNT_ZERO[0]_Z635\: PFUMX port map (
+    ALUT => UN1_RLOL_DB_CNT_ZERO_BM(0),
+    BLUT => UN1_RLOL_DB_CNT_ZERO_AM(0),
+    C0 => RLOL_P2,
+    Z => UN1_RLOL_DB_CNT_ZERO(0));
+\UN1_RLOS_DB_CNT_ZERO_BM[0]_Z636\: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+  A => RLOS_DB_CNT(0),
+  B => RLOS_DB_CNT(1),
+  C => RLOS_DB_CNT(2),
+  D => RLOS_DB_CNT(3),
+  Z => UN1_RLOS_DB_CNT_ZERO_BM(0));
+\UN1_RLOS_DB_CNT_ZERO[0]_Z637\: PFUMX port map (
+    ALUT => UN1_RLOS_DB_CNT_ZERO_BM(0),
+    BLUT => UN1_RLOS_DB_CNT_ZERO_AM(0),
+    C0 => RLOS_P2,
+    Z => UN1_RLOS_DB_CNT_ZERO(0));
+\GENBLK1.UN1_PLOL0_CNT_TC_1\: LUT4 
+generic map(
+  init => X"F8F8"
+)
+port map (
+  A => TXP_CNT(0),
+  B => TXP_CNT(1),
+  C => UN9_PLOL0_CNT_TC,
+  D => VCC,
+  Z => UN1_PLOL0_CNT_TC_1);
+\RXS_CNT_3[1]_Z639\: LUT4 
+generic map(
+  init => X"6464"
+)
+port map (
+  A => RXS_CNT(0),
+  B => RXS_CNT(1),
+  C => RXS_RST,
+  D => VCC,
+  Z => RXS_CNT_3(1));
+\GENBLK2.WAITA_RLOLS06\: LUT4 
+generic map(
+  init => X"0504"
+)
+port map (
+  A => RLOL_DB,
+  B => RLOL_DB_P1,
+  C => RLOS_DB,
+  D => RLOS_DB_P1,
+  Z => WAITA_RLOLS06);
+\GENBLK2.UN1_RLOL_DB_CNT_MAX\: LUT4 
+generic map(
+  init => X"8001"
+)
+port map (
+  A => RLOL_DB_CNT(0),
+  B => RLOL_DB_CNT(1),
+  C => RLOL_DB_CNT(2),
+  D => RLOL_DB_CNT(3),
+  Z => UN1_RLOL_DB_CNT_MAX);
+\GENBLK2.UN1_RLOS_DB_CNT_MAX\: LUT4 
+generic map(
+  init => X"8001"
+)
+port map (
+  A => RLOS_DB_CNT(0),
+  B => RLOS_DB_CNT(1),
+  C => RLOS_DB_CNT(2),
+  D => RLOS_DB_CNT(3),
+  Z => UN1_RLOS_DB_CNT_MAX);
+RLOLS0_CNT_TC_1_13_Z643: LUT4 
+generic map(
+  init => X"1010"
+)
+port map (
+  A => RLOLS0_CNT(12),
+  B => RLOLS0_CNT(13),
+  C => RLOLS0_CNT_TC_1_9,
+  D => VCC,
+  Z => RLOLS0_CNT_TC_1_13);
+\GENBLK1.UN1_PLOL_CNT_TC_14\: LUT4 
+generic map(
+  init => X"0100"
+)
+port map (
+  A => PLOL_CNT(5),
+  B => PLOL_CNT(10),
+  C => PLOL_CNT(18),
+  D => UN1_PLOL_CNT_TC_10,
+  Z => UN1_PLOL_CNT_TC_14);
+RLOL1_CNT_TC_1_14_Z645: LUT4 
+generic map(
+  init => X"0100"
+)
+port map (
+  A => RLOL1_CNT(12),
+  B => RLOL1_CNT(13),
+  C => RLOL1_CNT(18),
+  D => RLOL1_CNT_TC_1_10,
+  Z => RLOL1_CNT_TC_1_14);
+\RDO_TX_PCS_RST_C_1[0]\: LUT4 
+generic map(
+  init => X"F4F4"
+)
+port map (
+  A => rsl_disable,
+  B => TXP_RST,
+  C => tx_pcs_rst_c,
+  D => VCC,
+  Z => rsl_tx_pcs_rst_c);
+\RDO_RX_PCS_RST_C_1[0]\: LUT4 
+generic map(
+  init => X"F4F4"
+)
+port map (
+  A => rsl_disable,
+  B => RXP_RST2,
+  C => rx_pcs_rst_c,
+  D => VCC,
+  Z => rsl_rx_pcs_rst_c);
+RDO_TX_SERDES_RST_C: LUT4 
+generic map(
+  init => X"F4F4"
+)
+port map (
+  A => rsl_disable,
+  B => TXS_RST,
+  C => tx_serdes_rst_c,
+  D => VCC,
+  Z => RSL_TX_SERDES_RST_C_4);
+\RXS_CNT_3[0]_Z649\: LUT4 
+generic map(
+  init => X"5252"
+)
+port map (
+  A => RXS_CNT(0),
+  B => RXS_CNT(1),
+  C => RXS_RST,
+  D => VCC,
+  Z => RXS_CNT_3(0));
+\RDO_RX_SERDES_RST_C_1[0]\: LUT4 
+generic map(
+  init => X"F4F4"
+)
+port map (
+  A => rsl_disable,
+  B => RXS_RST,
+  C => rx_serdes_rst_c,
+  D => VCC,
+  Z => RSL_RX_SERDES_RST_C_5);
+RDO_SERDES_RST_DUAL_C: LUT4 
+generic map(
+  init => X"F4F4"
+)
+port map (
+  A => rsl_disable,
+  B => rsl_rst,
+  C => serdes_rst_dual_c,
+  D => VCC,
+  Z => RSL_SERDES_RST_DUAL_C_6);
+\GENBLK1.UN9_PLOL0_CNT_TC\: LUT4 
+generic map(
+  init => X"1010"
+)
+port map (
+  A => PLOL0_CNT(0),
+  B => PLOL0_CNT(1),
+  C => PLOL0_CNT(2),
+  D => VCC,
+  Z => UN9_PLOL0_CNT_TC);
+RLOLS0_CNT_TC_1_9_Z653: LUT4 
+generic map(
+  init => X"0008"
+)
+port map (
+  A => RLOLS0_CNT(10),
+  B => RLOLS0_CNT(14),
+  C => RLOLS0_CNT(16),
+  D => RLOLS0_CNT(17),
+  Z => RLOLS0_CNT_TC_1_9);
+RLOLS0_CNT_TC_1_10_Z654: LUT4 
+generic map(
+  init => X"0100"
+)
+port map (
+  A => RLOLS0_CNT(0),
+  B => RLOLS0_CNT(1),
+  C => RLOLS0_CNT(2),
+  D => RLOLS0_CNT(15),
+  Z => RLOLS0_CNT_TC_1_10);
+RLOLS0_CNT_TC_1_11_Z655: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+  A => RLOLS0_CNT(3),
+  B => RLOLS0_CNT(4),
+  C => RLOLS0_CNT(5),
+  D => RLOLS0_CNT(6),
+  Z => RLOLS0_CNT_TC_1_11);
+RLOLS0_CNT_TC_1_12_Z656: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+  A => RLOLS0_CNT(7),
+  B => RLOLS0_CNT(8),
+  C => RLOLS0_CNT(9),
+  D => RLOLS0_CNT(11),
+  Z => RLOLS0_CNT_TC_1_12);
+\GENBLK1.UN1_PLOL_CNT_TC_10\: LUT4 
+generic map(
+  init => X"0080"
+)
+port map (
+  A => PLOL_CNT(1),
+  B => PLOL_CNT(6),
+  C => PLOL_CNT(7),
+  D => PLOL_CNT(12),
+  Z => UN1_PLOL_CNT_TC_10);
+\GENBLK1.UN1_PLOL_CNT_TC_11\: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+  A => PLOL_CNT(8),
+  B => PLOL_CNT(9),
+  C => PLOL_CNT(11),
+  D => PLOL_CNT(13),
+  Z => UN1_PLOL_CNT_TC_11);
+\GENBLK1.UN1_PLOL_CNT_TC_12\: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+  A => PLOL_CNT(14),
+  B => PLOL_CNT(15),
+  C => PLOL_CNT(16),
+  D => PLOL_CNT(17),
+  Z => UN1_PLOL_CNT_TC_12);
+\GENBLK1.UN1_PLOL_CNT_TC_13\: LUT4 
+generic map(
+  init => X"0100"
+)
+port map (
+  A => PLOL_CNT(2),
+  B => PLOL_CNT(3),
+  C => PLOL_CNT(4),
+  D => PLOL_CNT(19),
+  Z => UN1_PLOL_CNT_TC_13);
+RLOL1_CNT_TC_1_10_Z661: LUT4 
+generic map(
+  init => X"0800"
+)
+port map (
+  A => RLOL1_CNT(14),
+  B => RLOL1_CNT(15),
+  C => RLOL1_CNT(16),
+  D => RLOL1_CNT(17),
+  Z => RLOL1_CNT_TC_1_10);
+RLOL1_CNT_TC_1_11_Z662: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+  A => RLOL1_CNT(0),
+  B => RLOL1_CNT(1),
+  C => RLOL1_CNT(2),
+  D => RLOL1_CNT(3),
+  Z => RLOL1_CNT_TC_1_11);
+RLOL1_CNT_TC_1_12_Z663: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+  A => RLOL1_CNT(4),
+  B => RLOL1_CNT(5),
+  C => RLOL1_CNT(6),
+  D => RLOL1_CNT(7),
+  Z => RLOL1_CNT_TC_1_12);
+RLOL1_CNT_TC_1_13_Z664: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+  A => RLOL1_CNT(8),
+  B => RLOL1_CNT(9),
+  C => RLOL1_CNT(10),
+  D => RLOL1_CNT(11),
+  Z => RLOL1_CNT_TC_1_13);
+\GENBLK1.PLOL0_CNT_3_RNO[2]\: LUT4 
+generic map(
+  init => X"8888"
+)
+port map (
+  A => PLOL0_CNT(0),
+  B => WAITA_PLOL0,
+  C => VCC,
+  D => VCC,
+  Z => CO0_2);
+PLOL_FEDGE_Z666: LUT4 
+generic map(
+  init => X"4444"
+)
+port map (
+  A => PLL_LOL_P2,
+  B => PLL_LOL_P3,
+  C => VCC,
+  D => VCC,
+  Z => PLOL_FEDGE);
+RLOS_REDGE_Z667: LUT4 
+generic map(
+  init => X"2222"
+)
+port map (
+  A => RLOS_DB,
+  B => RLOS_DB_P1,
+  C => VCC,
+  D => VCC,
+  Z => RLOS_REDGE);
+\GENBLK2.UN8_RXS_CNT_TC\: LUT4 
+generic map(
+  init => X"8888"
+)
+port map (
+  A => RXS_CNT(0),
+  B => RXS_CNT(1),
+  C => VCC,
+  D => VCC,
+  Z => UN8_RXS_CNT_TC);
+\UN1_RLOS_DB_CNT_ZERO_AM[0]_Z669\: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+  A => RLOS_DB_CNT(0),
+  B => RLOS_DB_CNT(1),
+  C => RLOS_DB_CNT(2),
+  D => RLOS_DB_CNT(3),
+  Z => UN1_RLOS_DB_CNT_ZERO_AM(0));
+\UN1_RLOL_DB_CNT_ZERO_AM[0]_Z670\: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+  A => RLOL_DB_CNT(0),
+  B => RLOL_DB_CNT(1),
+  C => RLOL_DB_CNT(2),
+  D => RLOL_DB_CNT(3),
+  Z => UN1_RLOL_DB_CNT_ZERO_AM(0));
+\GENBLK1.PLOL0_CNT9\: LUT4 
+generic map(
+  init => X"AAAE"
+)
+port map (
+  A => PLL_LOL_P2,
+  B => PLOL0_CNT(2),
+  C => PLOL0_CNT(1),
+  D => PLOL0_CNT(0),
+  Z => PLOL0_CNT9);
+\GENBLK2.RLOLS0_CNT11_0\: LUT4 
+generic map(
+  init => X"4F44"
+)
+port map (
+  A => RLOL_DB_P1,
+  B => RLOL_DB,
+  C => RLOS_DB_P1,
+  D => RLOS_DB,
+  Z => RLOLS0_CNT11_0);
+\GENBLK2.RLOL1_CNT_CRY_0[0]\: CCU2C 
+generic map(
+  INIT0 => X"500c",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => VCC,
+  B0 => \RLOL1_CNT_\,
+  C0 => VCC,
+  D0 => VCC,
+  A1 => \RLOL1_CNT_\,
+  B1 => RLOL1_CNT(0),
+  C1 => VCC,
+  D1 => VCC,
+  CIN => N_5,
+  COUT => RLOL1_CNT_CRY(0),
+  S0 => RLOL1_CNT_CRY_0_S0(0),
+  S1 => RLOL1_CNT_S(0));
+\GENBLK2.RLOL1_CNT_CRY_0[1]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => \RLOL1_CNT_\,
+  B0 => RLOL1_CNT(1),
+  C0 => VCC,
+  D0 => VCC,
+  A1 => \RLOL1_CNT_\,
+  B1 => RLOL1_CNT(2),
+  C1 => VCC,
+  D1 => VCC,
+  CIN => RLOL1_CNT_CRY(0),
+  COUT => RLOL1_CNT_CRY(2),
+  S0 => RLOL1_CNT_S(1),
+  S1 => RLOL1_CNT_S(2));
+\GENBLK2.RLOL1_CNT_CRY_0[3]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => \RLOL1_CNT_\,
+  B0 => RLOL1_CNT(3),
+  C0 => VCC,
+  D0 => VCC,
+  A1 => \RLOL1_CNT_\,
+  B1 => RLOL1_CNT(4),
+  C1 => VCC,
+  D1 => VCC,
+  CIN => RLOL1_CNT_CRY(2),
+  COUT => RLOL1_CNT_CRY(4),
+  S0 => RLOL1_CNT_S(3),
+  S1 => RLOL1_CNT_S(4));
+\GENBLK2.RLOL1_CNT_CRY_0[5]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => \RLOL1_CNT_\,
+  B0 => RLOL1_CNT(5),
+  C0 => VCC,
+  D0 => VCC,
+  A1 => \RLOL1_CNT_\,
+  B1 => RLOL1_CNT(6),
+  C1 => VCC,
+  D1 => VCC,
+  CIN => RLOL1_CNT_CRY(4),
+  COUT => RLOL1_CNT_CRY(6),
+  S0 => RLOL1_CNT_S(5),
+  S1 => RLOL1_CNT_S(6));
+\GENBLK2.RLOL1_CNT_CRY_0[7]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => \RLOL1_CNT_\,
+  B0 => RLOL1_CNT(7),
+  C0 => VCC,
+  D0 => VCC,
+  A1 => \RLOL1_CNT_\,
+  B1 => RLOL1_CNT(8),
+  C1 => VCC,
+  D1 => VCC,
+  CIN => RLOL1_CNT_CRY(6),
+  COUT => RLOL1_CNT_CRY(8),
+  S0 => RLOL1_CNT_S(7),
+  S1 => RLOL1_CNT_S(8));
+\GENBLK2.RLOL1_CNT_CRY_0[9]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => \RLOL1_CNT_\,
+  B0 => RLOL1_CNT(9),
+  C0 => VCC,
+  D0 => VCC,
+  A1 => \RLOL1_CNT_\,
+  B1 => RLOL1_CNT(10),
+  C1 => VCC,
+  D1 => VCC,
+  CIN => RLOL1_CNT_CRY(8),
+  COUT => RLOL1_CNT_CRY(10),
+  S0 => RLOL1_CNT_S(9),
+  S1 => RLOL1_CNT_S(10));
+\GENBLK2.RLOL1_CNT_CRY_0[11]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => \RLOL1_CNT_\,
+  B0 => RLOL1_CNT(11),
+  C0 => VCC,
+  D0 => VCC,
+  A1 => \RLOL1_CNT_\,
+  B1 => RLOL1_CNT(12),
+  C1 => VCC,
+  D1 => VCC,
+  CIN => RLOL1_CNT_CRY(10),
+  COUT => RLOL1_CNT_CRY(12),
+  S0 => RLOL1_CNT_S(11),
+  S1 => RLOL1_CNT_S(12));
+\GENBLK2.RLOL1_CNT_CRY_0[13]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => \RLOL1_CNT_\,
+  B0 => RLOL1_CNT(13),
+  C0 => VCC,
+  D0 => VCC,
+  A1 => \RLOL1_CNT_\,
+  B1 => RLOL1_CNT(14),
+  C1 => VCC,
+  D1 => VCC,
+  CIN => RLOL1_CNT_CRY(12),
+  COUT => RLOL1_CNT_CRY(14),
+  S0 => RLOL1_CNT_S(13),
+  S1 => RLOL1_CNT_S(14));
+\GENBLK2.RLOL1_CNT_CRY_0[15]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => \RLOL1_CNT_\,
+  B0 => RLOL1_CNT(15),
+  C0 => VCC,
+  D0 => VCC,
+  A1 => \RLOL1_CNT_\,
+  B1 => RLOL1_CNT(16),
+  C1 => VCC,
+  D1 => VCC,
+  CIN => RLOL1_CNT_CRY(14),
+  COUT => RLOL1_CNT_CRY(16),
+  S0 => RLOL1_CNT_S(15),
+  S1 => RLOL1_CNT_S(16));
+\GENBLK2.RLOL1_CNT_CRY_0[17]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"800a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => \RLOL1_CNT_\,
+  B0 => RLOL1_CNT(17),
+  C0 => VCC,
+  D0 => VCC,
+  A1 => \RLOL1_CNT_\,
+  B1 => RLOL1_CNT(18),
+  C1 => VCC,
+  D1 => VCC,
+  CIN => RLOL1_CNT_CRY(16),
+  COUT => RLOL1_CNT_CRY_0_COUT(17),
+  S0 => RLOL1_CNT_S(17),
+  S1 => RLOL1_CNT_S(18));
+\GENBLK2.RLOLS0_CNT_CRY_0[0]\: CCU2C 
+generic map(
+  INIT0 => X"500c",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => VCC,
+  B0 => \RLOLS0_CNT_\,
+  C0 => VCC,
+  D0 => VCC,
+  A1 => \RLOLS0_CNT_\,
+  B1 => RLOLS0_CNT(0),
+  C1 => VCC,
+  D1 => VCC,
+  CIN => N_4,
+  COUT => RLOLS0_CNT_CRY(0),
+  S0 => RLOLS0_CNT_CRY_0_S0(0),
+  S1 => RLOLS0_CNT_S(0));
+\GENBLK2.RLOLS0_CNT_CRY_0[1]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => \RLOLS0_CNT_\,
+  B0 => RLOLS0_CNT(1),
+  C0 => VCC,
+  D0 => VCC,
+  A1 => \RLOLS0_CNT_\,
+  B1 => RLOLS0_CNT(2),
+  C1 => VCC,
+  D1 => VCC,
+  CIN => RLOLS0_CNT_CRY(0),
+  COUT => RLOLS0_CNT_CRY(2),
+  S0 => RLOLS0_CNT_S(1),
+  S1 => RLOLS0_CNT_S(2));
+\GENBLK2.RLOLS0_CNT_CRY_0[3]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => \RLOLS0_CNT_\,
+  B0 => RLOLS0_CNT(3),
+  C0 => VCC,
+  D0 => VCC,
+  A1 => \RLOLS0_CNT_\,
+  B1 => RLOLS0_CNT(4),
+  C1 => VCC,
+  D1 => VCC,
+  CIN => RLOLS0_CNT_CRY(2),
+  COUT => RLOLS0_CNT_CRY(4),
+  S0 => RLOLS0_CNT_S(3),
+  S1 => RLOLS0_CNT_S(4));
+\GENBLK2.RLOLS0_CNT_CRY_0[5]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => \RLOLS0_CNT_\,
+  B0 => RLOLS0_CNT(5),
+  C0 => VCC,
+  D0 => VCC,
+  A1 => \RLOLS0_CNT_\,
+  B1 => RLOLS0_CNT(6),
+  C1 => VCC,
+  D1 => VCC,
+  CIN => RLOLS0_CNT_CRY(4),
+  COUT => RLOLS0_CNT_CRY(6),
+  S0 => RLOLS0_CNT_S(5),
+  S1 => RLOLS0_CNT_S(6));
+\GENBLK2.RLOLS0_CNT_CRY_0[7]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => \RLOLS0_CNT_\,
+  B0 => RLOLS0_CNT(7),
+  C0 => VCC,
+  D0 => VCC,
+  A1 => \RLOLS0_CNT_\,
+  B1 => RLOLS0_CNT(8),
+  C1 => VCC,
+  D1 => VCC,
+  CIN => RLOLS0_CNT_CRY(6),
+  COUT => RLOLS0_CNT_CRY(8),
+  S0 => RLOLS0_CNT_S(7),
+  S1 => RLOLS0_CNT_S(8));
+\GENBLK2.RLOLS0_CNT_CRY_0[9]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => \RLOLS0_CNT_\,
+  B0 => RLOLS0_CNT(9),
+  C0 => VCC,
+  D0 => VCC,
+  A1 => \RLOLS0_CNT_\,
+  B1 => RLOLS0_CNT(10),
+  C1 => VCC,
+  D1 => VCC,
+  CIN => RLOLS0_CNT_CRY(8),
+  COUT => RLOLS0_CNT_CRY(10),
+  S0 => RLOLS0_CNT_S(9),
+  S1 => RLOLS0_CNT_S(10));
+\GENBLK2.RLOLS0_CNT_CRY_0[11]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => \RLOLS0_CNT_\,
+  B0 => RLOLS0_CNT(11),
+  C0 => VCC,
+  D0 => VCC,
+  A1 => \RLOLS0_CNT_\,
+  B1 => RLOLS0_CNT(12),
+  C1 => VCC,
+  D1 => VCC,
+  CIN => RLOLS0_CNT_CRY(10),
+  COUT => RLOLS0_CNT_CRY(12),
+  S0 => RLOLS0_CNT_S(11),
+  S1 => RLOLS0_CNT_S(12));
+\GENBLK2.RLOLS0_CNT_CRY_0[13]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => \RLOLS0_CNT_\,
+  B0 => RLOLS0_CNT(13),
+  C0 => VCC,
+  D0 => VCC,
+  A1 => \RLOLS0_CNT_\,
+  B1 => RLOLS0_CNT(14),
+  C1 => VCC,
+  D1 => VCC,
+  CIN => RLOLS0_CNT_CRY(12),
+  COUT => RLOLS0_CNT_CRY(14),
+  S0 => RLOLS0_CNT_S(13),
+  S1 => RLOLS0_CNT_S(14));
+\GENBLK2.RLOLS0_CNT_CRY_0[15]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => \RLOLS0_CNT_\,
+  B0 => RLOLS0_CNT(15),
+  C0 => VCC,
+  D0 => VCC,
+  A1 => \RLOLS0_CNT_\,
+  B1 => RLOLS0_CNT(16),
+  C1 => VCC,
+  D1 => VCC,
+  CIN => RLOLS0_CNT_CRY(14),
+  COUT => RLOLS0_CNT_CRY(16),
+  S0 => RLOLS0_CNT_S(15),
+  S1 => RLOLS0_CNT_S(16));
+\GENBLK2.RLOLS0_CNT_S_0[17]\: CCU2C 
+generic map(
+  INIT0 => X"800a",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => \RLOLS0_CNT_\,
+  B0 => RLOLS0_CNT(17),
+  C0 => VCC,
+  D0 => VCC,
+  A1 => VCC,
+  B1 => VCC,
+  C1 => VCC,
+  D1 => VCC,
+  CIN => RLOLS0_CNT_CRY(16),
+  COUT => RLOLS0_CNT_S_0_COUT(17),
+  S0 => RLOLS0_CNT_S(17),
+  S1 => RLOLS0_CNT_S_0_S1(17));
+\GENBLK1.PLOL_CNT_CRY_0[0]\: CCU2C 
+generic map(
+  INIT0 => X"500c",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => VCC,
+  B0 => \PLOL_CNT_\,
+  C0 => VCC,
+  D0 => VCC,
+  A1 => \PLOL_CNT_\,
+  B1 => PLOL_CNT(0),
+  C1 => VCC,
+  D1 => VCC,
+  CIN => N_3,
+  COUT => PLOL_CNT_CRY(0),
+  S0 => PLOL_CNT_CRY_0_S0(0),
+  S1 => PLOL_CNT_S(0));
+\GENBLK1.PLOL_CNT_CRY_0[1]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => \PLOL_CNT_\,
+  B0 => PLOL_CNT(1),
+  C0 => VCC,
+  D0 => VCC,
+  A1 => \PLOL_CNT_\,
+  B1 => PLOL_CNT(2),
+  C1 => VCC,
+  D1 => VCC,
+  CIN => PLOL_CNT_CRY(0),
+  COUT => PLOL_CNT_CRY(2),
+  S0 => PLOL_CNT_S(1),
+  S1 => PLOL_CNT_S(2));
+\GENBLK1.PLOL_CNT_CRY_0[3]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => \PLOL_CNT_\,
+  B0 => PLOL_CNT(3),
+  C0 => VCC,
+  D0 => VCC,
+  A1 => \PLOL_CNT_\,
+  B1 => PLOL_CNT(4),
+  C1 => VCC,
+  D1 => VCC,
+  CIN => PLOL_CNT_CRY(2),
+  COUT => PLOL_CNT_CRY(4),
+  S0 => PLOL_CNT_S(3),
+  S1 => PLOL_CNT_S(4));
+\GENBLK1.PLOL_CNT_CRY_0[5]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => \PLOL_CNT_\,
+  B0 => PLOL_CNT(5),
+  C0 => VCC,
+  D0 => VCC,
+  A1 => \PLOL_CNT_\,
+  B1 => PLOL_CNT(6),
+  C1 => VCC,
+  D1 => VCC,
+  CIN => PLOL_CNT_CRY(4),
+  COUT => PLOL_CNT_CRY(6),
+  S0 => PLOL_CNT_S(5),
+  S1 => PLOL_CNT_S(6));
+\GENBLK1.PLOL_CNT_CRY_0[7]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => \PLOL_CNT_\,
+  B0 => PLOL_CNT(7),
+  C0 => VCC,
+  D0 => VCC,
+  A1 => \PLOL_CNT_\,
+  B1 => PLOL_CNT(8),
+  C1 => VCC,
+  D1 => VCC,
+  CIN => PLOL_CNT_CRY(6),
+  COUT => PLOL_CNT_CRY(8),
+  S0 => PLOL_CNT_S(7),
+  S1 => PLOL_CNT_S(8));
+\GENBLK1.PLOL_CNT_CRY_0[9]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => \PLOL_CNT_\,
+  B0 => PLOL_CNT(9),
+  C0 => VCC,
+  D0 => VCC,
+  A1 => \PLOL_CNT_\,
+  B1 => PLOL_CNT(10),
+  C1 => VCC,
+  D1 => VCC,
+  CIN => PLOL_CNT_CRY(8),
+  COUT => PLOL_CNT_CRY(10),
+  S0 => PLOL_CNT_S(9),
+  S1 => PLOL_CNT_S(10));
+\GENBLK1.PLOL_CNT_CRY_0[11]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => \PLOL_CNT_\,
+  B0 => PLOL_CNT(11),
+  C0 => VCC,
+  D0 => VCC,
+  A1 => \PLOL_CNT_\,
+  B1 => PLOL_CNT(12),
+  C1 => VCC,
+  D1 => VCC,
+  CIN => PLOL_CNT_CRY(10),
+  COUT => PLOL_CNT_CRY(12),
+  S0 => PLOL_CNT_S(11),
+  S1 => PLOL_CNT_S(12));
+\GENBLK1.PLOL_CNT_CRY_0[13]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => \PLOL_CNT_\,
+  B0 => PLOL_CNT(13),
+  C0 => VCC,
+  D0 => VCC,
+  A1 => \PLOL_CNT_\,
+  B1 => PLOL_CNT(14),
+  C1 => VCC,
+  D1 => VCC,
+  CIN => PLOL_CNT_CRY(12),
+  COUT => PLOL_CNT_CRY(14),
+  S0 => PLOL_CNT_S(13),
+  S1 => PLOL_CNT_S(14));
+\GENBLK1.PLOL_CNT_CRY_0[15]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => \PLOL_CNT_\,
+  B0 => PLOL_CNT(15),
+  C0 => VCC,
+  D0 => VCC,
+  A1 => \PLOL_CNT_\,
+  B1 => PLOL_CNT(16),
+  C1 => VCC,
+  D1 => VCC,
+  CIN => PLOL_CNT_CRY(14),
+  COUT => PLOL_CNT_CRY(16),
+  S0 => PLOL_CNT_S(15),
+  S1 => PLOL_CNT_S(16));
+\GENBLK1.PLOL_CNT_CRY_0[17]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => \PLOL_CNT_\,
+  B0 => PLOL_CNT(17),
+  C0 => VCC,
+  D0 => VCC,
+  A1 => \PLOL_CNT_\,
+  B1 => PLOL_CNT(18),
+  C1 => VCC,
+  D1 => VCC,
+  CIN => PLOL_CNT_CRY(16),
+  COUT => PLOL_CNT_CRY(18),
+  S0 => PLOL_CNT_S(17),
+  S1 => PLOL_CNT_S(18));
+\GENBLK1.PLOL_CNT_S_0[19]\: CCU2C 
+generic map(
+  INIT0 => X"800a",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => \PLOL_CNT_\,
+  B0 => PLOL_CNT(19),
+  C0 => VCC,
+  D0 => VCC,
+  A1 => VCC,
+  B1 => VCC,
+  C1 => VCC,
+  D1 => VCC,
+  CIN => PLOL_CNT_CRY(18),
+  COUT => PLOL_CNT_S_0_COUT(19),
+  S0 => PLOL_CNT_S(19),
+  S1 => PLOL_CNT_S_0_S1(19));
+\UN1_GENBLK2.RLOS_DB_CNT_CRY_0_0\: CCU2C 
+generic map(
+  INIT0 => X"5003",
+  INIT1 => X"900a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => VCC,
+  B0 => VCC,
+  C0 => VCC,
+  D0 => VCC,
+  A1 => RLOS_DB_CNT(0),
+  B1 => UN1_RLOS_DB_CNT_ZERO(0),
+  C1 => VCC,
+  D1 => VCC,
+  CIN => N_2,
+  COUT => RLOS_DB_CNT_CRY_0,
+  S0 => RLOS_DB_CNT_CRY_0_0_S0,
+  S1 => RLOS_DB_CNT_CRY_0_0_S1);
+\UN1_GENBLK2.RLOS_DB_CNT_CRY_1_0\: CCU2C 
+generic map(
+  INIT0 => X"e101",
+  INIT1 => X"e101",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => UN1_RLOS_DB_CNT_ZERO(0),
+  B0 => RLOS_P2,
+  C0 => RLOS_DB_CNT(1),
+  D0 => VCC,
+  A1 => UN1_RLOS_DB_CNT_ZERO(0),
+  B1 => RLOS_P2,
+  C1 => RLOS_DB_CNT(2),
+  D1 => VCC,
+  CIN => RLOS_DB_CNT_CRY_0,
+  COUT => RLOS_DB_CNT_CRY_2,
+  S0 => RLOS_DB_CNT_CRY_1_0_S0,
+  S1 => RLOS_DB_CNT_CRY_1_0_S1);
+\UN1_GENBLK2.RLOS_DB_CNT_S_3_0\: CCU2C 
+generic map(
+  INIT0 => X"a90a",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => RLOS_DB_CNT(3),
+  B0 => RLOS_P2,
+  C0 => UN1_RLOS_DB_CNT_ZERO(0),
+  D0 => VCC,
+  A1 => VCC,
+  B1 => VCC,
+  C1 => VCC,
+  D1 => VCC,
+  CIN => RLOS_DB_CNT_CRY_2,
+  COUT => RLOS_DB_CNT_S_3_0_COUT,
+  S0 => RLOS_DB_CNT_S_3_0_S0,
+  S1 => RLOS_DB_CNT_S_3_0_S1);
+\UN1_GENBLK2.RLOL_DB_CNT_CRY_0_0\: CCU2C 
+generic map(
+  INIT0 => X"5003",
+  INIT1 => X"900a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => VCC,
+  B0 => VCC,
+  C0 => VCC,
+  D0 => VCC,
+  A1 => RLOL_DB_CNT(0),
+  B1 => UN1_RLOL_DB_CNT_ZERO(0),
+  C1 => VCC,
+  D1 => VCC,
+  CIN => N_1,
+  COUT => RLOL_DB_CNT_CRY_0,
+  S0 => RLOL_DB_CNT_CRY_0_0_S0,
+  S1 => RLOL_DB_CNT_CRY_0_0_S1);
+\UN1_GENBLK2.RLOL_DB_CNT_CRY_1_0\: CCU2C 
+generic map(
+  INIT0 => X"e101",
+  INIT1 => X"e101",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => UN1_RLOL_DB_CNT_ZERO(0),
+  B0 => RLOL_P2,
+  C0 => RLOL_DB_CNT(1),
+  D0 => VCC,
+  A1 => UN1_RLOL_DB_CNT_ZERO(0),
+  B1 => RLOL_P2,
+  C1 => RLOL_DB_CNT(2),
+  D1 => VCC,
+  CIN => RLOL_DB_CNT_CRY_0,
+  COUT => RLOL_DB_CNT_CRY_2,
+  S0 => RLOL_DB_CNT_CRY_1_0_S0,
+  S1 => RLOL_DB_CNT_CRY_1_0_S1);
+\UN1_GENBLK2.RLOL_DB_CNT_S_3_0\: CCU2C 
+generic map(
+  INIT0 => X"a90a",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+  A0 => RLOL_DB_CNT(3),
+  B0 => RLOL_P2,
+  C0 => UN1_RLOL_DB_CNT_ZERO(0),
+  D0 => VCC,
+  A1 => VCC,
+  B1 => VCC,
+  C1 => VCC,
+  D1 => VCC,
+  CIN => RLOL_DB_CNT_CRY_2,
+  COUT => RLOL_DB_CNT_S_3_0_COUT,
+  S0 => RLOL_DB_CNT_S_3_0_S0,
+  S1 => RLOL_DB_CNT_S_3_0_S1);
+VCC_0: VHI port map (
+    Z => VCC);
+II_GND: VLO port map (
+    Z => GND);
+rsl_tx_serdes_rst_c <= RSL_TX_SERDES_RST_C_4;
+rsl_rx_serdes_rst_c <= RSL_RX_SERDES_RST_C_5;
+rsl_serdes_rst_dual_c <= RSL_SERDES_RST_DUAL_C_6;
+end beh;
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library synplify;
+use synplify.components.all;
+library pmi;
+use pmi.pmi_components.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity PCSD is
+port(
+hdoutp :  out std_logic;
+hdoutn :  out std_logic;
+hdinp :  in std_logic;
+hdinn :  in std_logic;
+rxrefclk :  in std_logic;
+tx_pclk :  out std_logic;
+txi_clk :  in std_logic;
+txdata : in std_logic_vector(7 downto 0);
+tx_k : in std_logic_vector(0 downto 0);
+xmit : in std_logic_vector(0 downto 0);
+tx_disp_correct : in std_logic_vector(0 downto 0);
+rxdata : out std_logic_vector(7 downto 0);
+rx_k : out std_logic_vector(0 downto 0);
+rx_disp_err : out std_logic_vector(0 downto 0);
+rx_cv_err : out std_logic_vector(0 downto 0);
+signal_detect_c :  in std_logic;
+rx_los_low_s :  out std_logic;
+lsm_status_s :  out std_logic;
+ctc_urun_s :  out std_logic;
+ctc_orun_s :  out std_logic;
+rx_cdr_lol_s :  out std_logic;
+ctc_ins_s :  out std_logic;
+ctc_del_s :  out std_logic;
+tx_pwrup_c :  in std_logic;
+rx_pwrup_c :  in std_logic;
+serdes_pdb :  in std_logic;
+pll_refclki :  in std_logic;
+rsl_disable :  in std_logic;
+rsl_rst :  in std_logic;
+serdes_rst_dual_c :  in std_logic;
+rst_dual_c :  in std_logic;
+tx_serdes_rst_c :  in std_logic;
+tx_pcs_rst_c :  in std_logic;
+pll_lol :  in std_logic;
+rx_serdes_rst_c :  in std_logic;
+rx_pcs_rst_c :  in std_logic);
+end PCSD;
+
+architecture beh of PCSD is
+signal TX_PCLK_7 : std_logic ;
+signal RX_LOS_LOW_S_8 : std_logic ;
+signal RX_CDR_LOL_S_9 : std_logic ;
+signal RSL_TX_PCS_RST_C : std_logic ;
+signal RSL_RX_PCS_RST_C : std_logic ;
+signal RSL_RX_SERDES_RST_C : std_logic ;
+signal RSL_SERDES_RST_DUAL_C : std_logic ;
+signal RSL_TX_SERDES_RST_C : std_logic ;
+signal N47_1 : std_logic ;
+signal N48_1 : std_logic ;
+signal N1_1 : std_logic ;
+signal N2_1 : std_logic ;
+signal N3_1 : std_logic ;
+signal N4_1 : std_logic ;
+signal N5_1 : std_logic ;
+signal N49_1 : std_logic ;
+signal N6_1 : std_logic ;
+signal N50_1 : std_logic ;
+signal N7_1 : std_logic ;
+signal N51_1 : std_logic ;
+signal N8_1 : std_logic ;
+signal N52_1 : std_logic ;
+signal N9_1 : std_logic ;
+signal N53_1 : std_logic ;
+signal N54_1 : std_logic ;
+signal N55_1 : std_logic ;
+signal N56_1 : std_logic ;
+signal N57_1 : std_logic ;
+signal N58_1 : std_logic ;
+signal N59_1 : std_logic ;
+signal N60_1 : std_logic ;
+signal N61_1 : std_logic ;
+signal N62_1 : std_logic ;
+signal N63_1 : std_logic ;
+signal N64_1 : std_logic ;
+signal N65_1 : std_logic ;
+signal N10_1 : std_logic ;
+signal N66_1 : std_logic ;
+signal N67_1 : std_logic ;
+signal N68_1 : std_logic ;
+signal N69_1 : std_logic ;
+signal N70_1 : std_logic ;
+signal N71_1 : std_logic ;
+signal N72_1 : std_logic ;
+signal N73_1 : std_logic ;
+signal N74_1 : std_logic ;
+signal N75_1 : std_logic ;
+signal N76_1 : std_logic ;
+signal N77_1 : std_logic ;
+signal N78_1 : std_logic ;
+signal N79_1 : std_logic ;
+signal N80_1 : std_logic ;
+signal N81_1 : std_logic ;
+signal N82_1 : std_logic ;
+signal N83_1 : std_logic ;
+signal N84_1 : std_logic ;
+signal N85_1 : std_logic ;
+signal N86_1 : std_logic ;
+signal N87_1 : std_logic ;
+signal N88_1 : std_logic ;
+signal N11_1 : std_logic ;
+signal N89_1 : std_logic ;
+signal N12_1 : std_logic ;
+signal N90_1 : std_logic ;
+signal N13_1 : std_logic ;
+signal N91_1 : std_logic ;
+signal N92_1 : std_logic ;
+signal N93_1 : std_logic ;
+signal N94_1 : std_logic ;
+signal N95_1 : std_logic ;
+signal N14_1 : std_logic ;
+signal N96_1 : std_logic ;
+signal N15_1 : std_logic ;
+signal N97_1 : std_logic ;
+signal N98_1 : std_logic ;
+signal N99_1 : std_logic ;
+signal N100_1 : std_logic ;
+signal N101_1 : std_logic ;
+signal N102_1 : std_logic ;
+signal N103_1 : std_logic ;
+signal N104_1 : std_logic ;
+signal N105_1 : std_logic ;
+signal N106_1 : std_logic ;
+signal N107_1 : std_logic ;
+signal N108_1 : std_logic ;
+signal N109_1 : std_logic ;
+signal N110_1 : std_logic ;
+signal N121_1 : std_logic ;
+signal N16_1 : std_logic ;
+signal N17_1 : std_logic ;
+signal N18_1 : std_logic ;
+signal N19_1 : std_logic ;
+signal N20_1 : std_logic ;
+signal N21_1 : std_logic ;
+signal N22_1 : std_logic ;
+signal N23_1 : std_logic ;
+signal N24_1 : std_logic ;
+signal N25_1 : std_logic ;
+signal N26_1 : std_logic ;
+signal N27_1 : std_logic ;
+signal N28_1 : std_logic ;
+signal N29_1 : std_logic ;
+signal N30_1 : std_logic ;
+signal N31_1 : std_logic ;
+signal N32_1 : std_logic ;
+signal N33_1 : std_logic ;
+signal N34_1 : std_logic ;
+signal N35_1 : std_logic ;
+signal N36_1 : std_logic ;
+signal N37_1 : std_logic ;
+signal N38_1 : std_logic ;
+signal N39_1 : std_logic ;
+signal N40_1 : std_logic ;
+signal N41_1 : std_logic ;
+signal N42_1 : std_logic ;
+signal N43_1 : std_logic ;
+signal N46_1 : std_logic ;
+signal GND : std_logic ;
+signal VCC : std_logic ;
+component PCSDrsl_core_Z1_layer1
+  port(
+    serdes_rst_dual_c :  in std_logic;
+    rx_serdes_rst_c :  in std_logic;
+    tx_serdes_rst_c :  in std_logic;
+    rsl_rx_pcs_rst_c :  out std_logic;
+    rx_pcs_rst_c :  in std_logic;
+    rsl_tx_pcs_rst_c :  out std_logic;
+    tx_pcs_rst_c :  in std_logic;
+    rsl_disable :  in std_logic;
+    rsl_tx_serdes_rst_c :  out std_logic;
+    pll_lol :  in std_logic;
+    pll_refclki :  in std_logic;
+    rx_cdr_lol_s :  in std_logic;
+    rx_los_low_s :  in std_logic;
+    rsl_rst :  in std_logic;
+    rxrefclk :  in std_logic;
+    rsl_rx_serdes_rst_c :  out std_logic;
+    rsl_serdes_rst_dual_c :  out std_logic  );
+end component;
+begin
+GND_0: VLO port map (
+  Z => GND);
+VCC_0: VHI port map (
+  Z => VCC);
+PUR_INST: PUR port map (
+  PUR => VCC);
+GSR_INST: GSR port map (
+  GSR => VCC);
+DCU0_INST: DCUA 
+generic map( 
+  D_MACROPDB => "0b1", 
+  D_IB_PWDNB => "0b1", 
+  D_XGE_MODE => "0b0", 
+  D_LOW_MARK => "0d4", 
+  D_HIGH_MARK => "0d12", 
+  D_BUS8BIT_SEL => "0b0", 
+  D_CDR_LOL_SET => "0b00", 
+  D_BITCLK_LOCAL_EN => "0b1", 
+  D_BITCLK_ND_EN => "0b0", 
+  D_BITCLK_FROM_ND_EN => "0b0", 
+  D_SYNC_LOCAL_EN => "0b1", 
+  D_SYNC_ND_EN => "0b0", 
+  CH0_UC_MODE => "0b0", 
+  CH0_PCIE_MODE => "0b0", 
+  CH0_RIO_MODE => "0b0", 
+  CH0_WA_MODE => "0b0", 
+  CH0_INVERT_RX => "0b0", 
+  CH0_INVERT_TX => "0b0", 
+  CH0_PRBS_SELECTION => "0b0", 
+  CH0_GE_AN_ENABLE => "0b0", 
+  CH0_PRBS_LOCK => "0b0", 
+  CH0_PRBS_ENABLE => "0b0", 
+  CH0_ENABLE_CG_ALIGN => "0b1", 
+  CH0_TX_GEAR_MODE => "0b0", 
+  CH0_RX_GEAR_MODE => "0b0", 
+  CH0_PCS_DET_TIME_SEL => "0b00", 
+  CH0_PCIE_EI_EN => "0b0", 
+  CH0_TX_GEAR_BYPASS => "0b0", 
+  CH0_ENC_BYPASS => "0b0", 
+  CH0_SB_BYPASS => "0b0", 
+  CH0_RX_SB_BYPASS => "0b0", 
+  CH0_WA_BYPASS => "0b0", 
+  CH0_DEC_BYPASS => "0b0", 
+  CH0_CTC_BYPASS => "0b0", 
+  CH0_RX_GEAR_BYPASS => "0b0", 
+  CH0_LSM_DISABLE => "0b0", 
+  CH0_MATCH_2_ENABLE => "0b1", 
+  CH0_MATCH_4_ENABLE => "0b0", 
+  CH0_MIN_IPG_CNT => "0b11", 
+  CH0_CC_MATCH_1 => "0x000", 
+  CH0_CC_MATCH_2 => "0x000", 
+  CH0_CC_MATCH_3 => "0x1BC", 
+  CH0_CC_MATCH_4 => "0x050", 
+  CH0_UDF_COMMA_MASK => "0x3ff", 
+  CH0_UDF_COMMA_A => "0x283", 
+  CH0_UDF_COMMA_B => "0x17C", 
+  CH0_RX_DCO_CK_DIV => "0b010", 
+  CH0_RCV_DCC_EN => "0b0", 
+  CH0_REQ_LVL_SET => "0b00", 
+  CH0_REQ_EN => "0b1", 
+  CH0_RTERM_RX => "0d22", 
+  CH0_PDEN_SEL => "0b1", 
+  CH0_LDR_RX2CORE_SEL => "0b0", 
+  CH0_LDR_CORE2TX_SEL => "0b0", 
+  CH0_TPWDNB => "0b1", 
+  CH0_RATE_MODE_TX => "0b0", 
+  CH0_RTERM_TX => "0d19", 
+  CH0_TX_CM_SEL => "0b00", 
+  CH0_TDRV_PRE_EN => "0b0", 
+  CH0_TDRV_SLICE0_SEL => "0b01", 
+  CH0_TDRV_SLICE1_SEL => "0b00", 
+  CH0_TDRV_SLICE2_SEL => "0b01", 
+  CH0_TDRV_SLICE3_SEL => "0b01", 
+  CH0_TDRV_SLICE4_SEL => "0b01", 
+  CH0_TDRV_SLICE5_SEL => "0b01", 
+  CH0_TDRV_SLICE0_CUR => "0b101", 
+  CH0_TDRV_SLICE1_CUR => "0b000", 
+  CH0_TDRV_SLICE2_CUR => "0b11", 
+  CH0_TDRV_SLICE3_CUR => "0b11", 
+  CH0_TDRV_SLICE4_CUR => "0b11", 
+  CH0_TDRV_SLICE5_CUR => "0b00", 
+  CH0_TDRV_DAT_SEL => "0b00", 
+  CH0_TX_DIV11_SEL => "0b0", 
+  CH0_RPWDNB => "0b1", 
+  CH0_RATE_MODE_RX => "0b0", 
+  CH0_RLOS_SEL => "0b1", 
+  CH0_RX_LOS_LVL => "0b010", 
+  CH0_RX_LOS_CEQ => "0b11", 
+  CH0_RX_LOS_HYST_EN => "0b0", 
+  CH0_RX_LOS_EN => "0b1", 
+  CH0_RX_DIV11_SEL => "0b0", 
+  CH0_SEL_SD_RX_CLK => "0b0", 
+  CH0_FF_RX_H_CLK_EN => "0b0", 
+  CH0_FF_RX_F_CLK_DIS => "0b0", 
+  CH0_FF_TX_H_CLK_EN => "0b0", 
+  CH0_FF_TX_F_CLK_DIS => "0b0", 
+  CH0_RX_RATE_SEL => "0d8", 
+  CH0_TDRV_POST_EN => "0b0", 
+  CH0_TX_POST_SIGN => "0b0", 
+  CH0_TX_PRE_SIGN => "0b0", 
+  CH0_RXTERM_CM => "0b11", 
+  CH0_RXIN_CM => "0b11", 
+  CH0_LEQ_OFFSET_SEL => "0b0", 
+  CH0_LEQ_OFFSET_TRIM => "0b000", 
+  D_TX_MAX_RATE => "1.25", 
+  CH0_CDR_MAX_RATE => "1.25", 
+  CH0_TXAMPLITUDE => "0d1100", 
+  CH0_TXDEPRE => "DISABLED", 
+  CH0_TXDEPOST => "DISABLED", 
+  CH0_PROTOCOL => "GBE", 
+  D_ISETLOS => "0d0", 
+  D_SETIRPOLY_AUX => "0b00", 
+  D_SETICONST_AUX => "0b00", 
+  D_SETIRPOLY_CH => "0b00", 
+  D_SETICONST_CH => "0b00", 
+  D_REQ_ISET => "0b000", 
+  D_PD_ISET => "0b00", 
+  D_DCO_CALIB_TIME_SEL => "0b00", 
+  CH0_DCOCTLGI => "0b010", 
+  CH0_DCOATDDLY => "0b00", 
+  CH0_DCOATDCFG => "0b00", 
+  CH0_DCOBYPSATD => "0b1", 
+  CH0_DCOSCALEI => "0b00", 
+  CH0_DCOITUNE4LSB => "0b111", 
+  CH0_DCOIOSTUNE => "0b000", 
+  CH0_DCODISBDAVOID => "0b0", 
+  CH0_DCOCALDIV => "0b001", 
+  CH0_DCONUOFLSB => "0b101", 
+  CH0_DCOIUPDNX2 => "0b1", 
+  CH0_DCOSTEP => "0b00", 
+  CH0_DCOSTARTVAL => "0b000", 
+  CH0_DCOFLTDAC => "0b01", 
+  CH0_DCOITUNE => "0b00", 
+  CH0_DCOFTNRG => "0b110", 
+  CH0_CDR_CNT4SEL => "0b00", 
+  CH0_CDR_CNT8SEL => "0b00", 
+  CH0_BAND_THRESHOLD => "0d0", 
+  CH0_AUTO_FACQ_EN => "0b1", 
+  CH0_AUTO_CALIB_EN => "0b1", 
+  CH0_CALIB_CK_MODE => "0b0", 
+  CH0_REG_BAND_OFFSET => "0d0", 
+  CH0_REG_BAND_SEL => "0d0", 
+  CH0_REG_IDAC_SEL => "0d0", 
+  CH0_REG_IDAC_EN => "0b0", 
+  D_TXPLL_PWDNB => "0b1", 
+  D_SETPLLRC => "0d1", 
+  D_REFCK_MODE => "0b001", 
+  D_TX_VCO_CK_DIV => "0b010", 
+  D_PLL_LOL_SET => "0b00", 
+  D_RG_EN => "0b0", 
+  D_RG_SET => "0b00", 
+  D_CMUSETISCL4VCO => "0b000", 
+  D_CMUSETI4VCO => "0b00", 
+  D_CMUSETINITVCT => "0b00", 
+  D_CMUSETZGM => "0b000", 
+  D_CMUSETP2AGM => "0b000", 
+  D_CMUSETP1GM => "0b000", 
+  D_CMUSETI4CPZ => "0d3", 
+  D_CMUSETI4CPP => "0d3", 
+  D_CMUSETICP4Z => "0b101", 
+  D_CMUSETICP4P => "0b01", 
+  D_CMUSETBIASI => "0b00"
+) 
+port map (
+  CH0_HDINP => hdinp,
+  CH1_HDINP => GND,
+  CH0_HDINN => hdinn,
+  CH1_HDINN => GND,
+  D_TXBIT_CLKP_FROM_ND => GND,
+  D_TXBIT_CLKN_FROM_ND => GND,
+  D_SYNC_ND => GND,
+  D_TXPLL_LOL_FROM_ND => GND,
+  CH0_RX_REFCLK => rxrefclk,
+  CH1_RX_REFCLK => GND,
+  CH0_FF_RXI_CLK => TX_PCLK_7,
+  CH1_FF_RXI_CLK => VCC,
+  CH0_FF_TXI_CLK => txi_clk,
+  CH1_FF_TXI_CLK => VCC,
+  CH0_FF_EBRD_CLK => TX_PCLK_7,
+  CH1_FF_EBRD_CLK => VCC,
+  CH0_FF_TX_D_0 => txdata(0),
+  CH1_FF_TX_D_0 => GND,
+  CH0_FF_TX_D_1 => txdata(1),
+  CH1_FF_TX_D_1 => GND,
+  CH0_FF_TX_D_2 => txdata(2),
+  CH1_FF_TX_D_2 => GND,
+  CH0_FF_TX_D_3 => txdata(3),
+  CH1_FF_TX_D_3 => GND,
+  CH0_FF_TX_D_4 => txdata(4),
+  CH1_FF_TX_D_4 => GND,
+  CH0_FF_TX_D_5 => txdata(5),
+  CH1_FF_TX_D_5 => GND,
+  CH0_FF_TX_D_6 => txdata(6),
+  CH1_FF_TX_D_6 => GND,
+  CH0_FF_TX_D_7 => txdata(7),
+  CH1_FF_TX_D_7 => GND,
+  CH0_FF_TX_D_8 => tx_k(0),
+  CH1_FF_TX_D_8 => GND,
+  CH0_FF_TX_D_9 => GND,
+  CH1_FF_TX_D_9 => GND,
+  CH0_FF_TX_D_10 => xmit(0),
+  CH1_FF_TX_D_10 => GND,
+  CH0_FF_TX_D_11 => tx_disp_correct(0),
+  CH1_FF_TX_D_11 => GND,
+  CH0_FF_TX_D_12 => GND,
+  CH1_FF_TX_D_12 => GND,
+  CH0_FF_TX_D_13 => GND,
+  CH1_FF_TX_D_13 => GND,
+  CH0_FF_TX_D_14 => GND,
+  CH1_FF_TX_D_14 => GND,
+  CH0_FF_TX_D_15 => GND,
+  CH1_FF_TX_D_15 => GND,
+  CH0_FF_TX_D_16 => GND,
+  CH1_FF_TX_D_16 => GND,
+  CH0_FF_TX_D_17 => GND,
+  CH1_FF_TX_D_17 => GND,
+  CH0_FF_TX_D_18 => GND,
+  CH1_FF_TX_D_18 => GND,
+  CH0_FF_TX_D_19 => GND,
+  CH1_FF_TX_D_19 => GND,
+  CH0_FF_TX_D_20 => GND,
+  CH1_FF_TX_D_20 => GND,
+  CH0_FF_TX_D_21 => GND,
+  CH1_FF_TX_D_21 => GND,
+  CH0_FF_TX_D_22 => GND,
+  CH1_FF_TX_D_22 => GND,
+  CH0_FF_TX_D_23 => GND,
+  CH1_FF_TX_D_23 => GND,
+  CH0_FFC_EI_EN => GND,
+  CH1_FFC_EI_EN => GND,
+  CH0_FFC_PCIE_DET_EN => GND,
+  CH1_FFC_PCIE_DET_EN => GND,
+  CH0_FFC_PCIE_CT => GND,
+  CH1_FFC_PCIE_CT => GND,
+  CH0_FFC_SB_INV_RX => GND,
+  CH1_FFC_SB_INV_RX => GND,
+  CH0_FFC_ENABLE_CGALIGN => GND,
+  CH1_FFC_ENABLE_CGALIGN => GND,
+  CH0_FFC_SIGNAL_DETECT => signal_detect_c,
+  CH1_FFC_SIGNAL_DETECT => GND,
+  CH0_FFC_FB_LOOPBACK => GND,
+  CH1_FFC_FB_LOOPBACK => GND,
+  CH0_FFC_SB_PFIFO_LP => GND,
+  CH1_FFC_SB_PFIFO_LP => GND,
+  CH0_FFC_PFIFO_CLR => GND,
+  CH1_FFC_PFIFO_CLR => GND,
+  CH0_FFC_RATE_MODE_RX => GND,
+  CH1_FFC_RATE_MODE_RX => GND,
+  CH0_FFC_RATE_MODE_TX => GND,
+  CH1_FFC_RATE_MODE_TX => GND,
+  CH0_FFC_DIV11_MODE_RX => GND,
+  CH1_FFC_DIV11_MODE_RX => GND,
+  CH0_FFC_RX_GEAR_MODE => GND,
+  CH1_FFC_RX_GEAR_MODE => GND,
+  CH0_FFC_TX_GEAR_MODE => GND,
+  CH1_FFC_TX_GEAR_MODE => GND,
+  CH0_FFC_DIV11_MODE_TX => GND,
+  CH1_FFC_DIV11_MODE_TX => GND,
+  CH0_FFC_LDR_CORE2TX_EN => GND,
+  CH1_FFC_LDR_CORE2TX_EN => GND,
+  CH0_FFC_LANE_TX_RST => RSL_TX_PCS_RST_C,
+  CH1_FFC_LANE_TX_RST => GND,
+  CH0_FFC_LANE_RX_RST => RSL_RX_PCS_RST_C,
+  CH1_FFC_LANE_RX_RST => GND,
+  CH0_FFC_RRST => RSL_RX_SERDES_RST_C,
+  CH1_FFC_RRST => GND,
+  CH0_FFC_TXPWDNB => tx_pwrup_c,
+  CH1_FFC_TXPWDNB => GND,
+  CH0_FFC_RXPWDNB => rx_pwrup_c,
+  CH1_FFC_RXPWDNB => GND,
+  CH0_LDR_CORE2TX => GND,
+  CH1_LDR_CORE2TX => GND,
+  D_SCIWDATA0 => GND,
+  D_SCIWDATA1 => GND,
+  D_SCIWDATA2 => GND,
+  D_SCIWDATA3 => GND,
+  D_SCIWDATA4 => GND,
+  D_SCIWDATA5 => GND,
+  D_SCIWDATA6 => GND,
+  D_SCIWDATA7 => GND,
+  D_SCIADDR0 => GND,
+  D_SCIADDR1 => GND,
+  D_SCIADDR2 => GND,
+  D_SCIADDR3 => GND,
+  D_SCIADDR4 => GND,
+  D_SCIADDR5 => GND,
+  D_SCIENAUX => GND,
+  D_SCISELAUX => GND,
+  CH0_SCIEN => GND,
+  CH1_SCIEN => GND,
+  CH0_SCISEL => GND,
+  CH1_SCISEL => GND,
+  D_SCIRD => GND,
+  D_SCIWSTN => GND,
+  D_CYAWSTN => GND,
+  D_FFC_SYNC_TOGGLE => GND,
+  D_FFC_DUAL_RST => rst_dual_c,
+  D_FFC_MACRO_RST => RSL_SERDES_RST_DUAL_C,
+  D_FFC_MACROPDB => serdes_pdb,
+  D_FFC_TRST => RSL_TX_SERDES_RST_C,
+  CH0_FFC_CDR_EN_BITSLIP => GND,
+  CH1_FFC_CDR_EN_BITSLIP => GND,
+  D_SCAN_ENABLE => GND,
+  D_SCAN_IN_0 => GND,
+  D_SCAN_IN_1 => GND,
+  D_SCAN_IN_2 => GND,
+  D_SCAN_IN_3 => GND,
+  D_SCAN_IN_4 => GND,
+  D_SCAN_IN_5 => GND,
+  D_SCAN_IN_6 => GND,
+  D_SCAN_IN_7 => GND,
+  D_SCAN_MODE => GND,
+  D_SCAN_RESET => GND,
+  D_CIN0 => GND,
+  D_CIN1 => GND,
+  D_CIN2 => GND,
+  D_CIN3 => GND,
+  D_CIN4 => GND,
+  D_CIN5 => GND,
+  D_CIN6 => GND,
+  D_CIN7 => GND,
+  D_CIN8 => GND,
+  D_CIN9 => GND,
+  D_CIN10 => GND,
+  D_CIN11 => GND,
+  CH0_HDOUTP => hdoutp,
+  CH1_HDOUTP => N47_1,
+  CH0_HDOUTN => hdoutn,
+  CH1_HDOUTN => N48_1,
+  D_TXBIT_CLKP_TO_ND => N1_1,
+  D_TXBIT_CLKN_TO_ND => N2_1,
+  D_SYNC_PULSE2ND => N3_1,
+  D_TXPLL_LOL_TO_ND => N4_1,
+  CH0_FF_RX_F_CLK => N5_1,
+  CH1_FF_RX_F_CLK => N49_1,
+  CH0_FF_RX_H_CLK => N6_1,
+  CH1_FF_RX_H_CLK => N50_1,
+  CH0_FF_TX_F_CLK => N7_1,
+  CH1_FF_TX_F_CLK => N51_1,
+  CH0_FF_TX_H_CLK => N8_1,
+  CH1_FF_TX_H_CLK => N52_1,
+  CH0_FF_RX_PCLK => N9_1,
+  CH1_FF_RX_PCLK => N53_1,
+  CH0_FF_TX_PCLK => TX_PCLK_7,
+  CH1_FF_TX_PCLK => N54_1,
+  CH0_FF_RX_D_0 => rxdata(0),
+  CH1_FF_RX_D_0 => N55_1,
+  CH0_FF_RX_D_1 => rxdata(1),
+  CH1_FF_RX_D_1 => N56_1,
+  CH0_FF_RX_D_2 => rxdata(2),
+  CH1_FF_RX_D_2 => N57_1,
+  CH0_FF_RX_D_3 => rxdata(3),
+  CH1_FF_RX_D_3 => N58_1,
+  CH0_FF_RX_D_4 => rxdata(4),
+  CH1_FF_RX_D_4 => N59_1,
+  CH0_FF_RX_D_5 => rxdata(5),
+  CH1_FF_RX_D_5 => N60_1,
+  CH0_FF_RX_D_6 => rxdata(6),
+  CH1_FF_RX_D_6 => N61_1,
+  CH0_FF_RX_D_7 => rxdata(7),
+  CH1_FF_RX_D_7 => N62_1,
+  CH0_FF_RX_D_8 => rx_k(0),
+  CH1_FF_RX_D_8 => N63_1,
+  CH0_FF_RX_D_9 => rx_disp_err(0),
+  CH1_FF_RX_D_9 => N64_1,
+  CH0_FF_RX_D_10 => rx_cv_err(0),
+  CH1_FF_RX_D_10 => N65_1,
+  CH0_FF_RX_D_11 => N10_1,
+  CH1_FF_RX_D_11 => N66_1,
+  CH0_FF_RX_D_12 => N67_1,
+  CH1_FF_RX_D_12 => N68_1,
+  CH0_FF_RX_D_13 => N69_1,
+  CH1_FF_RX_D_13 => N70_1,
+  CH0_FF_RX_D_14 => N71_1,
+  CH1_FF_RX_D_14 => N72_1,
+  CH0_FF_RX_D_15 => N73_1,
+  CH1_FF_RX_D_15 => N74_1,
+  CH0_FF_RX_D_16 => N75_1,
+  CH1_FF_RX_D_16 => N76_1,
+  CH0_FF_RX_D_17 => N77_1,
+  CH1_FF_RX_D_17 => N78_1,
+  CH0_FF_RX_D_18 => N79_1,
+  CH1_FF_RX_D_18 => N80_1,
+  CH0_FF_RX_D_19 => N81_1,
+  CH1_FF_RX_D_19 => N82_1,
+  CH0_FF_RX_D_20 => N83_1,
+  CH1_FF_RX_D_20 => N84_1,
+  CH0_FF_RX_D_21 => N85_1,
+  CH1_FF_RX_D_21 => N86_1,
+  CH0_FF_RX_D_22 => N87_1,
+  CH1_FF_RX_D_22 => N88_1,
+  CH0_FF_RX_D_23 => N11_1,
+  CH1_FF_RX_D_23 => N89_1,
+  CH0_FFS_PCIE_DONE => N12_1,
+  CH1_FFS_PCIE_DONE => N90_1,
+  CH0_FFS_PCIE_CON => N13_1,
+  CH1_FFS_PCIE_CON => N91_1,
+  CH0_FFS_RLOS => RX_LOS_LOW_S_8,
+  CH1_FFS_RLOS => N92_1,
+  CH0_FFS_LS_SYNC_STATUS => lsm_status_s,
+  CH1_FFS_LS_SYNC_STATUS => N93_1,
+  CH0_FFS_CC_UNDERRUN => ctc_urun_s,
+  CH1_FFS_CC_UNDERRUN => N94_1,
+  CH0_FFS_CC_OVERRUN => ctc_orun_s,
+  CH1_FFS_CC_OVERRUN => N95_1,
+  CH0_FFS_RXFBFIFO_ERROR => N14_1,
+  CH1_FFS_RXFBFIFO_ERROR => N96_1,
+  CH0_FFS_TXFBFIFO_ERROR => N15_1,
+  CH1_FFS_TXFBFIFO_ERROR => N97_1,
+  CH0_FFS_RLOL => RX_CDR_LOL_S_9,
+  CH1_FFS_RLOL => N98_1,
+  CH0_FFS_SKP_ADDED => ctc_ins_s,
+  CH1_FFS_SKP_ADDED => N99_1,
+  CH0_FFS_SKP_DELETED => ctc_del_s,
+  CH1_FFS_SKP_DELETED => N100_1,
+  CH0_LDR_RX2CORE => N101_1,
+  CH1_LDR_RX2CORE => N102_1,
+  D_SCIRDATA0 => N103_1,
+  D_SCIRDATA1 => N104_1,
+  D_SCIRDATA2 => N105_1,
+  D_SCIRDATA3 => N106_1,
+  D_SCIRDATA4 => N107_1,
+  D_SCIRDATA5 => N108_1,
+  D_SCIRDATA6 => N109_1,
+  D_SCIRDATA7 => N110_1,
+  D_SCIINT => N121_1,
+  D_SCAN_OUT_0 => N16_1,
+  D_SCAN_OUT_1 => N17_1,
+  D_SCAN_OUT_2 => N18_1,
+  D_SCAN_OUT_3 => N19_1,
+  D_SCAN_OUT_4 => N20_1,
+  D_SCAN_OUT_5 => N21_1,
+  D_SCAN_OUT_6 => N22_1,
+  D_SCAN_OUT_7 => N23_1,
+  D_COUT0 => N24_1,
+  D_COUT1 => N25_1,
+  D_COUT2 => N26_1,
+  D_COUT3 => N27_1,
+  D_COUT4 => N28_1,
+  D_COUT5 => N29_1,
+  D_COUT6 => N30_1,
+  D_COUT7 => N31_1,
+  D_COUT8 => N32_1,
+  D_COUT9 => N33_1,
+  D_COUT10 => N34_1,
+  D_COUT11 => N35_1,
+  D_COUT12 => N36_1,
+  D_COUT13 => N37_1,
+  D_COUT14 => N38_1,
+  D_COUT15 => N39_1,
+  D_COUT16 => N40_1,
+  D_COUT17 => N41_1,
+  D_COUT18 => N42_1,
+  D_COUT19 => N43_1,
+  D_REFCLKI => pll_refclki,
+  D_FFS_PLOL => N46_1);
+RSL_INST: PCSDrsl_core_Z1_layer1 port map (
+  serdes_rst_dual_c => serdes_rst_dual_c,
+  rx_serdes_rst_c => rx_serdes_rst_c,
+  tx_serdes_rst_c => tx_serdes_rst_c,
+  rsl_rx_pcs_rst_c => RSL_RX_PCS_RST_C,
+  rx_pcs_rst_c => rx_pcs_rst_c,
+  rsl_tx_pcs_rst_c => RSL_TX_PCS_RST_C,
+  tx_pcs_rst_c => tx_pcs_rst_c,
+  rsl_disable => rsl_disable,
+  rsl_tx_serdes_rst_c => RSL_TX_SERDES_RST_C,
+  pll_lol => pll_lol,
+  pll_refclki => pll_refclki,
+  rx_cdr_lol_s => RX_CDR_LOL_S_9,
+  rx_los_low_s => RX_LOS_LOW_S_8,
+  rsl_rst => rsl_rst,
+  rxrefclk => rxrefclk,
+  rsl_rx_serdes_rst_c => RSL_RX_SERDES_RST_C,
+  rsl_serdes_rst_dual_c => RSL_SERDES_RST_DUAL_C);
+tx_pclk <= TX_PCLK_7;
+rx_los_low_s <= RX_LOS_LOW_S_8;
+rx_cdr_lol_s <= RX_CDR_LOL_S_9;
+end beh;
+

diff --git a/gbe/cores/sgmii/PCSD/syn_results/PCSD.vm b/gbe/cores/sgmii/PCSD/syn_results/PCSD.vm
new file mode 100644 (file)
index 0000000..0a8dd16
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/PCSD.vm
@@ -0,0 +1,2907 @@
+//
+// Written by Synplify Pro 
+// Product Version "M-2017.03L-SP1-1"
+// Program "Synplify Pro", Mapper "maplat, Build 1796R"
+// Tue Apr 30 12:09:50 2019
+//
+// Source file index table:
+// Object locations will have the form <file>:<line>
+// file 0 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd "
+// file 1 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd "
+// file 2 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd "
+// file 3 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd "
+// file 4 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd "
+// file 5 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd "
+// file 6 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd "
+// file 7 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd "
+// file 8 "\/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd "
+// file 9 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd "
+// file 10 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v "
+// file 11 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v "
+// file 12 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v "
+// file 13 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v "
+// file 14 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v "
+// file 15 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh "
+// file 16 "\/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v "
+// file 17 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/nlconst.dat "
+// file 18 "\/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc "
+
+`timescale 100 ps/100 ps
+module PCSDrsl_core_Z1_layer1 (
+  serdes_rst_dual_c,
+  rx_serdes_rst_c,
+  tx_serdes_rst_c,
+  rsl_rx_pcs_rst_c,
+  rx_pcs_rst_c,
+  rsl_tx_pcs_rst_c,
+  tx_pcs_rst_c,
+  rsl_disable,
+  rsl_tx_serdes_rst_c,
+  pll_lol,
+  pll_refclki,
+  rx_cdr_lol_s,
+  rx_los_low_s,
+  rsl_rst,
+  rxrefclk,
+  rsl_rx_serdes_rst_c,
+  rsl_serdes_rst_dual_c
+)
+;
+input serdes_rst_dual_c ;
+input rx_serdes_rst_c ;
+input tx_serdes_rst_c ;
+output rsl_rx_pcs_rst_c ;
+input rx_pcs_rst_c ;
+output rsl_tx_pcs_rst_c ;
+input tx_pcs_rst_c ;
+input rsl_disable ;
+output rsl_tx_serdes_rst_c ;
+input pll_lol ;
+input pll_refclki ;
+input rx_cdr_lol_s ;
+input rx_los_low_s ;
+input rsl_rst ;
+input rxrefclk ;
+output rsl_rx_serdes_rst_c ;
+output rsl_serdes_rst_dual_c ;
+wire serdes_rst_dual_c ;
+wire rx_serdes_rst_c ;
+wire tx_serdes_rst_c ;
+wire rsl_rx_pcs_rst_c ;
+wire rx_pcs_rst_c ;
+wire rsl_tx_pcs_rst_c ;
+wire tx_pcs_rst_c ;
+wire rsl_disable ;
+wire rsl_tx_serdes_rst_c ;
+wire pll_lol ;
+wire pll_refclki ;
+wire rx_cdr_lol_s ;
+wire rx_los_low_s ;
+wire rsl_rst ;
+wire rxrefclk ;
+wire rsl_rx_serdes_rst_c ;
+wire rsl_serdes_rst_dual_c ;
+wire [2:0] plol0_cnt;
+wire [2:0] plol0_cnt_3;
+wire [1:0] rxs_cnt_3;
+wire [1:0] rxs_cnt;
+wire [1:0] rxs_cnt_QN;
+wire [3:0] rlos_db_cnt;
+wire [3:0] rlos_db_cnt_QN;
+wire [17:0] rlols0_cnt_s;
+wire [17:0] rlols0_cnt;
+wire [17:0] rlols0_cnt_QN;
+wire [3:0] rlol_db_cnt;
+wire [3:0] rlol_db_cnt_QN;
+wire [18:0] rlol1_cnt_s;
+wire [18:0] rlol1_cnt;
+wire [18:0] rlol1_cnt_QN;
+wire [1:0] txs_cnt;
+wire [1:0] txs_cnt_QN;
+wire [1:1] txs_cnt_RNO;
+wire [1:0] txp_cnt;
+wire [1:0] txp_cnt_QN;
+wire [1:1] txp_cnt_RNO;
+wire [19:0] plol_cnt_s;
+wire [19:0] plol_cnt;
+wire [19:0] plol_cnt_QN;
+wire [2:0] plol0_cnt_QN;
+wire [0:0] un1_rlol_db_cnt_zero;
+wire [0:0] un1_rlos_db_cnt_zero;
+wire [0:0] un1_rlol_db_cnt_zero_bm;
+wire [0:0] un1_rlol_db_cnt_zero_am;
+wire [0:0] un1_rlos_db_cnt_zero_bm;
+wire [0:0] un1_rlos_db_cnt_zero_am;
+wire [16:0] rlol1_cnt_cry;
+wire [0:0] rlol1_cnt_cry_0_S0;
+wire [17:17] rlol1_cnt_cry_0_COUT;
+wire [16:0] rlols0_cnt_cry;
+wire [0:0] rlols0_cnt_cry_0_S0;
+wire [17:17] rlols0_cnt_s_0_COUT;
+wire [17:17] rlols0_cnt_s_0_S1;
+wire [18:0] plol_cnt_cry;
+wire [0:0] plol_cnt_cry_0_S0;
+wire [19:19] plol_cnt_s_0_COUT;
+wire [19:19] plol_cnt_s_0_S1;
+wire rlos_db_p1 ;
+wire rlos_db ;
+wire rxp_rst25 ;
+wire plol0_cnt9 ;
+wire waita_plol0 ;
+wire rlol1_cnt_tc_1 ;
+wire rxs_rst ;
+wire rlol1_cnt_scalar ;
+wire waita_rlols06 ;
+wire un1_rlols0_cnt_tc ;
+wire waita_rlols0 ;
+wire waita_rlols0_QN ;
+wire VCC ;
+wire wait_calib_RNO ;
+wire un1_rlos_fedge_1 ;
+wire wait_calib ;
+wire wait_calib_QN ;
+wire rxs_rst6 ;
+wire un1_rxs_cnt_tc ;
+wire rxs_rst_QN ;
+wire un2_rlos_redge_1_i ;
+wire rxp_rst2 ;
+wire rxp_rst2_QN ;
+wire rlos_p1 ;
+wire rlos_p2 ;
+wire rlos_p2_QN ;
+wire rlos_p1_QN ;
+wire rlos_db_p1_QN ;
+wire rlos_db_cnt_axb_0 ;
+wire rlos_db_cnt_cry_1_0_S0 ;
+wire rlos_db_cnt_cry_1_0_S1 ;
+wire rlos_db_cnt_s_3_0_S0 ;
+wire un1_rlos_db_cnt_max ;
+wire rlos_db_QN ;
+wire rlols0_cnte ;
+wire rlol_p1 ;
+wire rlol_p2 ;
+wire rlol_p2_QN ;
+wire rlol_p1_QN ;
+wire rlol_db ;
+wire rlol_db_p1 ;
+wire rlol_db_p1_QN ;
+wire rlol_db_cnt_axb_0 ;
+wire rlol_db_cnt_cry_1_0_S0 ;
+wire rlol_db_cnt_cry_1_0_S1 ;
+wire rlol_db_cnt_s_3_0_S0 ;
+wire un1_rlol_db_cnt_max ;
+wire rlol_db_QN ;
+wire rlol1_cnte ;
+wire plol_fedge ;
+wire un1_plol0_cnt_tc_1_i ;
+wire waita_plol0_QN ;
+wire un1_plol_cnt_tc ;
+wire un2_plol_cnt_tc ;
+wire txs_rst ;
+wire txs_rst_QN ;
+wire N_12_i ;
+wire un9_plol0_cnt_tc ;
+wire un1_plol0_cnt_tc_1 ;
+wire txp_rst ;
+wire txp_rst_QN ;
+wire N_13_i ;
+wire pll_lol_p2 ;
+wire pll_lol_p3 ;
+wire pll_lol_p3_QN ;
+wire pll_lol_p1 ;
+wire pll_lol_p2_QN ;
+wire pll_lol_p1_QN ;
+wire rlols0_cnt_tc_1 ;
+wire rlos_redge ;
+wire rlols0_cnt11_0 ;
+wire plol_cnt_scalar ;
+wire rlols0_cnt_scalar ;
+wire un8_rxs_cnt_tc ;
+wire un1_plol_cnt_tc_11 ;
+wire un1_plol_cnt_tc_12 ;
+wire un1_plol_cnt_tc_13 ;
+wire un1_plol_cnt_tc_14 ;
+wire rlols0_cnt_tc_1_10 ;
+wire rlols0_cnt_tc_1_11 ;
+wire rlols0_cnt_tc_1_12 ;
+wire rlols0_cnt_tc_1_13 ;
+wire rlol1_cnt_tc_1_11 ;
+wire rlol1_cnt_tc_1_12 ;
+wire rlol1_cnt_tc_1_13 ;
+wire rlol1_cnt_tc_1_14 ;
+wire CO0_2 ;
+wire rlols0_cnt_tc_1_9 ;
+wire un1_plol_cnt_tc_10 ;
+wire rlol1_cnt_tc_1_10 ;
+wire rlos_db_cnt_cry_0 ;
+wire rlos_db_cnt_cry_0_0_S0 ;
+wire rlos_db_cnt_cry_0_0_S1 ;
+wire rlos_db_cnt_cry_2 ;
+wire rlos_db_cnt_s_3_0_COUT ;
+wire rlos_db_cnt_s_3_0_S1 ;
+wire rlol_db_cnt_cry_0 ;
+wire rlol_db_cnt_cry_0_0_S0 ;
+wire rlol_db_cnt_cry_0_0_S1 ;
+wire rlol_db_cnt_cry_2 ;
+wire rlol_db_cnt_s_3_0_COUT ;
+wire rlol_db_cnt_s_3_0_S1 ;
+wire GND ;
+wire N_1 ;
+wire N_2 ;
+wire N_3 ;
+wire N_4 ;
+wire N_5 ;
+  LUT4 \genblk2.rxp_rst2_RNO  (
+       .A(rsl_serdes_rst_dual_c),
+       .B(rsl_rx_serdes_rst_c),
+       .C(rlos_db_p1),
+       .D(rlos_db),
+       .Z(rxp_rst25)
+);
+defparam \genblk2.rxp_rst2_RNO .init=16'hEFEE;
+  LUT4 \genblk1.plol0_cnt_RNO[1]  (
+       .A(plol0_cnt[1]),
+       .B(plol0_cnt9),
+       .C(waita_plol0),
+       .D(plol0_cnt[0]),
+       .Z(plol0_cnt_3[1])
+);
+defparam \genblk1.plol0_cnt_RNO[1] .init=16'h1222;
+  LUT4 \genblk2.rxs_rst_RNIS0OP  (
+       .A(rlol1_cnt_tc_1),
+       .B(rxs_rst),
+       .C(rlos_db_p1),
+       .D(rlos_db),
+       .Z(rlol1_cnt_scalar)
+);
+defparam \genblk2.rxs_rst_RNIS0OP .init=16'h1011;
+// @16:759
+  FD1P3DX \genblk2.waita_rlols0  (
+       .D(waita_rlols06),
+       .SP(un1_rlols0_cnt_tc),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(waita_rlols0)
+);
+// @16:656
+  FD1P3BX \genblk2.wait_calib  (
+       .D(wait_calib_RNO),
+       .SP(un1_rlos_fedge_1),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(wait_calib)
+);
+// @16:694
+  FD1P3DX \genblk2.rxs_rst  (
+       .D(rxs_rst6),
+       .SP(un1_rxs_cnt_tc),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxs_rst)
+);
+// @16:694
+  FD1S3DX \genblk2.rxs_cnt[0]  (
+       .D(rxs_cnt_3[0]),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxs_cnt[0])
+);
+// @16:694
+  FD1S3DX \genblk2.rxs_cnt[1]  (
+       .D(rxs_cnt_3[1]),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxs_cnt[1])
+);
+// @16:806
+  FD1P3BX \genblk2.rxp_rst2  (
+       .D(rxp_rst25),
+       .SP(un2_rlos_redge_1_i),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rxp_rst2)
+);
+// @16:567
+  FD1S3DX \genblk2.rlos_p2  (
+       .D(rlos_p1),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlos_p2)
+);
+// @16:567
+  FD1S3DX \genblk2.rlos_p1  (
+       .D(rx_los_low_s),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlos_p1)
+);
+// @16:567
+  FD1S3BX \genblk2.rlos_db_p1  (
+       .D(rlos_db),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlos_db_p1)
+);
+// @16:640
+  FD1S3BX \genblk2.rlos_db_cnt[0]  (
+       .D(rlos_db_cnt_axb_0),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlos_db_cnt[0])
+);
+// @16:640
+  FD1S3BX \genblk2.rlos_db_cnt[1]  (
+       .D(rlos_db_cnt_cry_1_0_S0),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlos_db_cnt[1])
+);
+// @16:640
+  FD1S3BX \genblk2.rlos_db_cnt[2]  (
+       .D(rlos_db_cnt_cry_1_0_S1),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlos_db_cnt[2])
+);
+// @16:640
+  FD1S3BX \genblk2.rlos_db_cnt[3]  (
+       .D(rlos_db_cnt_s_3_0_S0),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlos_db_cnt[3])
+);
+// @16:649
+  FD1P3BX \genblk2.rlos_db  (
+       .D(rlos_db_cnt[3]),
+       .SP(un1_rlos_db_cnt_max),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlos_db)
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[0]  (
+       .D(rlols0_cnt_s[0]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[0])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[1]  (
+       .D(rlols0_cnt_s[1]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[1])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[2]  (
+       .D(rlols0_cnt_s[2]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[2])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[3]  (
+       .D(rlols0_cnt_s[3]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[3])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[4]  (
+       .D(rlols0_cnt_s[4]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[4])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[5]  (
+       .D(rlols0_cnt_s[5]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[5])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[6]  (
+       .D(rlols0_cnt_s[6]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[6])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[7]  (
+       .D(rlols0_cnt_s[7]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[7])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[8]  (
+       .D(rlols0_cnt_s[8]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[8])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[9]  (
+       .D(rlols0_cnt_s[9]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[9])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[10]  (
+       .D(rlols0_cnt_s[10]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[10])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[11]  (
+       .D(rlols0_cnt_s[11]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[11])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[12]  (
+       .D(rlols0_cnt_s[12]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[12])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[13]  (
+       .D(rlols0_cnt_s[13]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[13])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[14]  (
+       .D(rlols0_cnt_s[14]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[14])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[15]  (
+       .D(rlols0_cnt_s[15]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[15])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[16]  (
+       .D(rlols0_cnt_s[16]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[16])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[17]  (
+       .D(rlols0_cnt_s[17]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[17])
+);
+// @16:567
+  FD1S3DX \genblk2.rlol_p2  (
+       .D(rlol_p1),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol_p2)
+);
+// @16:567
+  FD1S3DX \genblk2.rlol_p1  (
+       .D(rx_cdr_lol_s),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol_p1)
+);
+// @16:567
+  FD1S3BX \genblk2.rlol_db_p1  (
+       .D(rlol_db),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlol_db_p1)
+);
+// @16:624
+  FD1S3BX \genblk2.rlol_db_cnt[0]  (
+       .D(rlol_db_cnt_axb_0),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlol_db_cnt[0])
+);
+// @16:624
+  FD1S3BX \genblk2.rlol_db_cnt[1]  (
+       .D(rlol_db_cnt_cry_1_0_S0),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlol_db_cnt[1])
+);
+// @16:624
+  FD1S3BX \genblk2.rlol_db_cnt[2]  (
+       .D(rlol_db_cnt_cry_1_0_S1),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlol_db_cnt[2])
+);
+// @16:624
+  FD1S3BX \genblk2.rlol_db_cnt[3]  (
+       .D(rlol_db_cnt_s_3_0_S0),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlol_db_cnt[3])
+);
+// @16:633
+  FD1P3BX \genblk2.rlol_db  (
+       .D(rlol_db_cnt[3]),
+       .SP(un1_rlol_db_cnt_max),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlol_db)
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[0]  (
+       .D(rlol1_cnt_s[0]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[0])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[1]  (
+       .D(rlol1_cnt_s[1]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[1])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[2]  (
+       .D(rlol1_cnt_s[2]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[2])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[3]  (
+       .D(rlol1_cnt_s[3]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[3])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[4]  (
+       .D(rlol1_cnt_s[4]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[4])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[5]  (
+       .D(rlol1_cnt_s[5]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[5])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[6]  (
+       .D(rlol1_cnt_s[6]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[6])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[7]  (
+       .D(rlol1_cnt_s[7]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[7])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[8]  (
+       .D(rlol1_cnt_s[8]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[8])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[9]  (
+       .D(rlol1_cnt_s[9]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[9])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[10]  (
+       .D(rlol1_cnt_s[10]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[10])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[11]  (
+       .D(rlol1_cnt_s[11]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[11])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[12]  (
+       .D(rlol1_cnt_s[12]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[12])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[13]  (
+       .D(rlol1_cnt_s[13]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[13])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[14]  (
+       .D(rlol1_cnt_s[14]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[14])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[15]  (
+       .D(rlol1_cnt_s[15]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[15])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[16]  (
+       .D(rlol1_cnt_s[16]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[16])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[17]  (
+       .D(rlol1_cnt_s[17]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[17])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[18]  (
+       .D(rlol1_cnt_s[18]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[18])
+);
+// @16:443
+  FD1P3DX \genblk1.waita_plol0  (
+       .D(plol_fedge),
+       .SP(un1_plol0_cnt_tc_1_i),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(waita_plol0)
+);
+// @16:422
+  FD1P3DX \genblk1.txs_rst  (
+       .D(un1_plol_cnt_tc),
+       .SP(un2_plol_cnt_tc),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txs_rst)
+);
+// @16:422
+  FD1S3DX \genblk1.txs_cnt[0]  (
+       .D(N_12_i),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txs_cnt[0])
+);
+// @16:422
+  FD1S3DX \genblk1.txs_cnt[1]  (
+       .D(txs_cnt_RNO[1]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txs_cnt[1])
+);
+// @16:461
+  FD1P3DX \genblk1.txp_rst  (
+       .D(un9_plol0_cnt_tc),
+       .SP(un1_plol0_cnt_tc_1),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txp_rst)
+);
+// @16:461
+  FD1S3DX \genblk1.txp_cnt[0]  (
+       .D(N_13_i),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txp_cnt[0])
+);
+// @16:461
+  FD1S3DX \genblk1.txp_cnt[1]  (
+       .D(txp_cnt_RNO[1]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txp_cnt[1])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[0]  (
+       .D(plol_cnt_s[0]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[0])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[1]  (
+       .D(plol_cnt_s[1]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[1])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[2]  (
+       .D(plol_cnt_s[2]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[2])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[3]  (
+       .D(plol_cnt_s[3]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[3])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[4]  (
+       .D(plol_cnt_s[4]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[4])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[5]  (
+       .D(plol_cnt_s[5]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[5])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[6]  (
+       .D(plol_cnt_s[6]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[6])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[7]  (
+       .D(plol_cnt_s[7]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[7])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[8]  (
+       .D(plol_cnt_s[8]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[8])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[9]  (
+       .D(plol_cnt_s[9]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[9])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[10]  (
+       .D(plol_cnt_s[10]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[10])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[11]  (
+       .D(plol_cnt_s[11]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[11])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[12]  (
+       .D(plol_cnt_s[12]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[12])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[13]  (
+       .D(plol_cnt_s[13]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[13])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[14]  (
+       .D(plol_cnt_s[14]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[14])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[15]  (
+       .D(plol_cnt_s[15]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[15])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[16]  (
+       .D(plol_cnt_s[16]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[16])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[17]  (
+       .D(plol_cnt_s[17]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[17])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[18]  (
+       .D(plol_cnt_s[18]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[18])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[19]  (
+       .D(plol_cnt_s[19]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[19])
+);
+// @16:451
+  FD1S3DX \genblk1.plol0_cnt[0]  (
+       .D(plol0_cnt_3[0]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol0_cnt[0])
+);
+// @16:451
+  FD1S3DX \genblk1.plol0_cnt[1]  (
+       .D(plol0_cnt_3[1]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol0_cnt[1])
+);
+// @16:451
+  FD1S3DX \genblk1.plol0_cnt[2]  (
+       .D(plol0_cnt_3[2]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol0_cnt[2])
+);
+// @16:398
+  FD1S3DX \genblk1.pll_lol_p3  (
+       .D(pll_lol_p2),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(pll_lol_p3)
+);
+// @16:398
+  FD1S3DX \genblk1.pll_lol_p2  (
+       .D(pll_lol_p1),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(pll_lol_p2)
+);
+// @16:398
+  FD1S3DX \genblk1.pll_lol_p1  (
+       .D(pll_lol),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(pll_lol_p1)
+);
+// @16:422
+  LUT4 \genblk1.txs_cnt_RNO[0]  (
+       .A(txs_cnt[0]),
+       .B(txs_rst),
+       .C(un1_plol_cnt_tc),
+       .D(VCC),
+       .Z(N_12_i)
+);
+defparam \genblk1.txs_cnt_RNO[0] .init=16'hA6A6;
+// @16:434
+  LUT4 \genblk1.txs_cnt_RNO[1]  (
+       .A(txs_cnt[0]),
+       .B(txs_cnt[1]),
+       .C(txs_rst),
+       .D(un1_plol_cnt_tc),
+       .Z(txs_cnt_RNO[1])
+);
+defparam \genblk1.txs_cnt_RNO[1] .init=16'hCC6C;
+// @16:806
+  LUT4 \genblk2.rxp_rst2_RNO_0  (
+       .A(rlols0_cnt_tc_1),
+       .B(rlos_redge),
+       .C(rsl_rx_serdes_rst_c),
+       .D(rsl_serdes_rst_dual_c),
+       .Z(un2_rlos_redge_1_i)
+);
+defparam \genblk2.rxp_rst2_RNO_0 .init=16'hFFFE;
+// @8:357
+  LUT4 \genblk2.waita_rlols0_RNI266C  (
+       .A(rlols0_cnt11_0),
+       .B(waita_rlols0),
+       .C(rlols0_cnt_tc_1),
+       .D(VCC),
+       .Z(rlols0_cnte)
+);
+defparam \genblk2.waita_rlols0_RNI266C .init=16'hFEFE;
+// @8:357
+  LUT4 \genblk2.wait_calib_RNIKRP81  (
+       .A(rxs_rst),
+       .B(wait_calib),
+       .C(rlol1_cnt_tc_1),
+       .D(rlos_redge),
+       .Z(rlol1_cnte)
+);
+defparam \genblk2.wait_calib_RNIKRP81 .init=16'hFFFE;
+// @16:317
+  LUT4 \genblk2.rxs_rst6  (
+       .A(rlol_db),
+       .B(rlos_db),
+       .C(rlol1_cnt_tc_1),
+       .D(VCC),
+       .Z(rxs_rst6)
+);
+defparam \genblk2.rxs_rst6 .init=16'h2020;
+// @16:412
+  LUT4 \genblk1.plol_cnt11_i  (
+       .A(pll_lol_p2),
+       .B(un1_plol_cnt_tc),
+       .C(rsl_tx_serdes_rst_c),
+       .D(VCC),
+       .Z(plol_cnt_scalar)
+);
+defparam \genblk1.plol_cnt11_i .init=16'h0202;
+// @16:778
+  LUT4 \genblk2.rlols0_cnt11_i  (
+       .A(rlols0_cnt11_0),
+       .B(rlols0_cnt_tc_1),
+       .C(VCC),
+       .D(VCC),
+       .Z(rlols0_cnt_scalar)
+);
+defparam \genblk2.rlols0_cnt11_i .init=16'h1111;
+// @16:317
+  LUT4 \genblk2.un1_rxs_cnt_tc  (
+       .A(rlol_db),
+       .B(rlos_db),
+       .C(un8_rxs_cnt_tc),
+       .D(rlol1_cnt_tc_1),
+       .Z(un1_rxs_cnt_tc)
+);
+defparam \genblk2.un1_rxs_cnt_tc .init=16'hFEFC;
+// @8:357
+  LUT4 \genblk2.wait_calib_RNO  (
+       .A(rlol_db),
+       .B(rlos_db),
+       .C(rlol1_cnt_tc_1),
+       .D(VCC),
+       .Z(wait_calib_RNO)
+);
+defparam \genblk2.wait_calib_RNO .init=16'hA3A3;
+// @16:259
+  LUT4 \genblk1.un2_plol_cnt_tc  (
+       .A(txs_cnt[0]),
+       .B(txs_cnt[1]),
+       .C(un1_plol_cnt_tc),
+       .D(VCC),
+       .Z(un2_plol_cnt_tc)
+);
+defparam \genblk1.un2_plol_cnt_tc .init=16'hF8F8;
+// @16:340
+  LUT4 \genblk2.un1_rlols0_cnt_tc  (
+       .A(rlols0_cnt11_0),
+       .B(waita_rlols06),
+       .C(rlols0_cnt_tc_1),
+       .D(VCC),
+       .Z(un1_rlols0_cnt_tc)
+);
+defparam \genblk2.un1_rlols0_cnt_tc .init=16'hFEFE;
+// @16:322
+  LUT4 \genblk2.un1_rlos_fedge_1  (
+       .A(rlos_db),
+       .B(rlos_db_p1),
+       .C(rlol1_cnt_tc_1),
+       .D(VCC),
+       .Z(un1_rlos_fedge_1)
+);
+defparam \genblk2.un1_rlos_fedge_1 .init=16'hF6F6;
+// @16:461
+  LUT4 \genblk1.txp_cnt_RNO[0]  (
+       .A(txp_cnt[0]),
+       .B(txp_rst),
+       .C(un9_plol0_cnt_tc),
+       .D(VCC),
+       .Z(N_13_i)
+);
+defparam \genblk1.txp_cnt_RNO[0] .init=16'hA6A6;
+// @16:473
+  LUT4 \genblk1.txp_cnt_RNO[1]  (
+       .A(txp_cnt[0]),
+       .B(txp_cnt[1]),
+       .C(txp_rst),
+       .D(un9_plol0_cnt_tc),
+       .Z(txp_cnt_RNO[1])
+);
+defparam \genblk1.txp_cnt_RNO[1] .init=16'hCC6C;
+// @16:386
+  LUT4 \genblk1.un1_plol_cnt_tc  (
+       .A(un1_plol_cnt_tc_11),
+       .B(un1_plol_cnt_tc_12),
+       .C(un1_plol_cnt_tc_13),
+       .D(un1_plol_cnt_tc_14),
+       .Z(un1_plol_cnt_tc)
+);
+defparam \genblk1.un1_plol_cnt_tc .init=16'h8000;
+// @16:388
+  LUT4 rlols0_cnt_tc_1_cZ (
+       .A(rlols0_cnt_tc_1_10),
+       .B(rlols0_cnt_tc_1_11),
+       .C(rlols0_cnt_tc_1_12),
+       .D(rlols0_cnt_tc_1_13),
+       .Z(rlols0_cnt_tc_1)
+);
+defparam rlols0_cnt_tc_1_cZ.init=16'h8000;
+// @16:387
+  LUT4 rlol1_cnt_tc_1_cZ (
+       .A(rlol1_cnt_tc_1_11),
+       .B(rlol1_cnt_tc_1_12),
+       .C(rlol1_cnt_tc_1_13),
+       .D(rlol1_cnt_tc_1_14),
+       .Z(rlol1_cnt_tc_1)
+);
+defparam rlol1_cnt_tc_1_cZ.init=16'h8000;
+// @16:625
+  LUT4 \un1_genblk2.rlol_db_cnt_axb_0  (
+       .A(rlol_db_cnt[0]),
+       .B(un1_rlol_db_cnt_zero[0]),
+       .C(VCC),
+       .D(VCC),
+       .Z(rlol_db_cnt_axb_0)
+);
+defparam \un1_genblk2.rlol_db_cnt_axb_0 .init=16'h9999;
+// @16:641
+  LUT4 \un1_genblk2.rlos_db_cnt_axb_0  (
+       .A(rlos_db_cnt[0]),
+       .B(un1_rlos_db_cnt_zero[0]),
+       .C(VCC),
+       .D(VCC),
+       .Z(rlos_db_cnt_axb_0)
+);
+defparam \un1_genblk2.rlos_db_cnt_axb_0 .init=16'h9999;
+// @16:443
+  LUT4 \genblk1.waita_plol0_RNO  (
+       .A(pll_lol_p2),
+       .B(pll_lol_p3),
+       .C(un9_plol0_cnt_tc),
+       .D(VCC),
+       .Z(un1_plol0_cnt_tc_1_i)
+);
+defparam \genblk1.waita_plol0_RNO .init=16'hF6F6;
+// @16:452
+  LUT4 \genblk1.plol0_cnt_3[2]  (
+       .A(CO0_2),
+       .B(plol0_cnt9),
+       .C(plol0_cnt[1]),
+       .D(plol0_cnt[2]),
+       .Z(plol0_cnt_3[2])
+);
+defparam \genblk1.plol0_cnt_3[2] .init=16'h1320;
+// @16:452
+  LUT4 \genblk1.plol0_cnt_3[0]  (
+       .A(plol0_cnt9),
+       .B(plol0_cnt[0]),
+       .C(waita_plol0),
+       .D(VCC),
+       .Z(plol0_cnt_3[0])
+);
+defparam \genblk1.plol0_cnt_3[0] .init=16'h1414;
+// @16:219
+  LUT4 \un1_rlol_db_cnt_zero_bm_cZ[0]  (
+       .A(rlol_db_cnt[0]),
+       .B(rlol_db_cnt[1]),
+       .C(rlol_db_cnt[2]),
+       .D(rlol_db_cnt[3]),
+       .Z(un1_rlol_db_cnt_zero_bm[0])
+);
+defparam \un1_rlol_db_cnt_zero_bm_cZ[0] .init=16'h8000;
+// @16:219
+  PFUMX \un1_rlol_db_cnt_zero_cZ[0]  (
+       .ALUT(un1_rlol_db_cnt_zero_bm[0]),
+       .BLUT(un1_rlol_db_cnt_zero_am[0]),
+       .C0(rlol_p2),
+       .Z(un1_rlol_db_cnt_zero[0])
+);
+// @16:219
+  LUT4 \un1_rlos_db_cnt_zero_bm_cZ[0]  (
+       .A(rlos_db_cnt[0]),
+       .B(rlos_db_cnt[1]),
+       .C(rlos_db_cnt[2]),
+       .D(rlos_db_cnt[3]),
+       .Z(un1_rlos_db_cnt_zero_bm[0])
+);
+defparam \un1_rlos_db_cnt_zero_bm_cZ[0] .init=16'h8000;
+// @16:219
+  PFUMX \un1_rlos_db_cnt_zero_cZ[0]  (
+       .ALUT(un1_rlos_db_cnt_zero_bm[0]),
+       .BLUT(un1_rlos_db_cnt_zero_am[0]),
+       .C0(rlos_p2),
+       .Z(un1_rlos_db_cnt_zero[0])
+);
+// @16:269
+  LUT4 \genblk1.un1_plol0_cnt_tc_1  (
+       .A(txp_cnt[0]),
+       .B(txp_cnt[1]),
+       .C(un9_plol0_cnt_tc),
+       .D(VCC),
+       .Z(un1_plol0_cnt_tc_1)
+);
+defparam \genblk1.un1_plol0_cnt_tc_1 .init=16'hF8F8;
+// @16:708
+  LUT4 \rxs_cnt_3_cZ[1]  (
+       .A(rxs_cnt[0]),
+       .B(rxs_cnt[1]),
+       .C(rxs_rst),
+       .D(VCC),
+       .Z(rxs_cnt_3[1])
+);
+defparam \rxs_cnt_3_cZ[1] .init=16'h6464;
+// @16:764
+  LUT4 \genblk2.waita_rlols06  (
+       .A(rlol_db),
+       .B(rlol_db_p1),
+       .C(rlos_db),
+       .D(rlos_db_p1),
+       .Z(waita_rlols06)
+);
+defparam \genblk2.waita_rlols06 .init=16'h0504;
+// @16:309
+  LUT4 \genblk2.un1_rlol_db_cnt_max  (
+       .A(rlol_db_cnt[0]),
+       .B(rlol_db_cnt[1]),
+       .C(rlol_db_cnt[2]),
+       .D(rlol_db_cnt[3]),
+       .Z(un1_rlol_db_cnt_max)
+);
+defparam \genblk2.un1_rlol_db_cnt_max .init=16'h8001;
+// @16:315
+  LUT4 \genblk2.un1_rlos_db_cnt_max  (
+       .A(rlos_db_cnt[0]),
+       .B(rlos_db_cnt[1]),
+       .C(rlos_db_cnt[2]),
+       .D(rlos_db_cnt[3]),
+       .Z(un1_rlos_db_cnt_max)
+);
+defparam \genblk2.un1_rlos_db_cnt_max .init=16'h8001;
+// @16:388
+  LUT4 rlols0_cnt_tc_1_13_cZ (
+       .A(rlols0_cnt[12]),
+       .B(rlols0_cnt[13]),
+       .C(rlols0_cnt_tc_1_9),
+       .D(VCC),
+       .Z(rlols0_cnt_tc_1_13)
+);
+defparam rlols0_cnt_tc_1_13_cZ.init=16'h1010;
+// @16:386
+  LUT4 \genblk1.un1_plol_cnt_tc_14  (
+       .A(plol_cnt[5]),
+       .B(plol_cnt[10]),
+       .C(plol_cnt[18]),
+       .D(un1_plol_cnt_tc_10),
+       .Z(un1_plol_cnt_tc_14)
+);
+defparam \genblk1.un1_plol_cnt_tc_14 .init=16'h0100;
+// @16:387
+  LUT4 rlol1_cnt_tc_1_14_cZ (
+       .A(rlol1_cnt[12]),
+       .B(rlol1_cnt[13]),
+       .C(rlol1_cnt[18]),
+       .D(rlol1_cnt_tc_1_10),
+       .Z(rlol1_cnt_tc_1_14)
+);
+defparam rlol1_cnt_tc_1_14_cZ.init=16'h0100;
+// @16:479
+  LUT4 \rdo_tx_pcs_rst_c_1[0]  (
+       .A(rsl_disable),
+       .B(txp_rst),
+       .C(tx_pcs_rst_c),
+       .D(VCC),
+       .Z(rsl_tx_pcs_rst_c)
+);
+defparam \rdo_tx_pcs_rst_c_1[0] .init=16'hF4F4;
+// @16:852
+  LUT4 \rdo_rx_pcs_rst_c_1[0]  (
+       .A(rsl_disable),
+       .B(rxp_rst2),
+       .C(rx_pcs_rst_c),
+       .D(VCC),
+       .Z(rsl_rx_pcs_rst_c)
+);
+defparam \rdo_rx_pcs_rst_c_1[0] .init=16'hF4F4;
+// @16:438
+  LUT4 rdo_tx_serdes_rst_c (
+       .A(rsl_disable),
+       .B(txs_rst),
+       .C(tx_serdes_rst_c),
+       .D(VCC),
+       .Z(rsl_tx_serdes_rst_c)
+);
+defparam rdo_tx_serdes_rst_c.init=16'hF4F4;
+// @16:708
+  LUT4 \rxs_cnt_3_cZ[0]  (
+       .A(rxs_cnt[0]),
+       .B(rxs_cnt[1]),
+       .C(rxs_rst),
+       .D(VCC),
+       .Z(rxs_cnt_3[0])
+);
+defparam \rxs_cnt_3_cZ[0] .init=16'h5252;
+// @16:743
+  LUT4 \rdo_rx_serdes_rst_c_1[0]  (
+       .A(rsl_disable),
+       .B(rxs_rst),
+       .C(rx_serdes_rst_c),
+       .D(VCC),
+       .Z(rsl_rx_serdes_rst_c)
+);
+defparam \rdo_rx_serdes_rst_c_1[0] .init=16'hF4F4;
+// @16:375
+  LUT4 rdo_serdes_rst_dual_c (
+       .A(rsl_disable),
+       .B(rsl_rst),
+       .C(serdes_rst_dual_c),
+       .D(VCC),
+       .Z(rsl_serdes_rst_dual_c)
+);
+defparam rdo_serdes_rst_dual_c.init=16'hF4F4;
+// @16:459
+  LUT4 \genblk1.un9_plol0_cnt_tc  (
+       .A(plol0_cnt[0]),
+       .B(plol0_cnt[1]),
+       .C(plol0_cnt[2]),
+       .D(VCC),
+       .Z(un9_plol0_cnt_tc)
+);
+defparam \genblk1.un9_plol0_cnt_tc .init=16'h1010;
+// @16:388
+  LUT4 rlols0_cnt_tc_1_9_cZ (
+       .A(rlols0_cnt[10]),
+       .B(rlols0_cnt[14]),
+       .C(rlols0_cnt[16]),
+       .D(rlols0_cnt[17]),
+       .Z(rlols0_cnt_tc_1_9)
+);
+defparam rlols0_cnt_tc_1_9_cZ.init=16'h0008;
+// @16:388
+  LUT4 rlols0_cnt_tc_1_10_cZ (
+       .A(rlols0_cnt[0]),
+       .B(rlols0_cnt[1]),
+       .C(rlols0_cnt[2]),
+       .D(rlols0_cnt[15]),
+       .Z(rlols0_cnt_tc_1_10)
+);
+defparam rlols0_cnt_tc_1_10_cZ.init=16'h0100;
+// @16:388
+  LUT4 rlols0_cnt_tc_1_11_cZ (
+       .A(rlols0_cnt[3]),
+       .B(rlols0_cnt[4]),
+       .C(rlols0_cnt[5]),
+       .D(rlols0_cnt[6]),
+       .Z(rlols0_cnt_tc_1_11)
+);
+defparam rlols0_cnt_tc_1_11_cZ.init=16'h0001;
+// @16:388
+  LUT4 rlols0_cnt_tc_1_12_cZ (
+       .A(rlols0_cnt[7]),
+       .B(rlols0_cnt[8]),
+       .C(rlols0_cnt[9]),
+       .D(rlols0_cnt[11]),
+       .Z(rlols0_cnt_tc_1_12)
+);
+defparam rlols0_cnt_tc_1_12_cZ.init=16'h0001;
+// @16:386
+  LUT4 \genblk1.un1_plol_cnt_tc_10  (
+       .A(plol_cnt[1]),
+       .B(plol_cnt[6]),
+       .C(plol_cnt[7]),
+       .D(plol_cnt[12]),
+       .Z(un1_plol_cnt_tc_10)
+);
+defparam \genblk1.un1_plol_cnt_tc_10 .init=16'h0080;
+// @16:386
+  LUT4 \genblk1.un1_plol_cnt_tc_11  (
+       .A(plol_cnt[8]),
+       .B(plol_cnt[9]),
+       .C(plol_cnt[11]),
+       .D(plol_cnt[13]),
+       .Z(un1_plol_cnt_tc_11)
+);
+defparam \genblk1.un1_plol_cnt_tc_11 .init=16'h8000;
+// @16:386
+  LUT4 \genblk1.un1_plol_cnt_tc_12  (
+       .A(plol_cnt[14]),
+       .B(plol_cnt[15]),
+       .C(plol_cnt[16]),
+       .D(plol_cnt[17]),
+       .Z(un1_plol_cnt_tc_12)
+);
+defparam \genblk1.un1_plol_cnt_tc_12 .init=16'h8000;
+// @16:386
+  LUT4 \genblk1.un1_plol_cnt_tc_13  (
+       .A(plol_cnt[2]),
+       .B(plol_cnt[3]),
+       .C(plol_cnt[4]),
+       .D(plol_cnt[19]),
+       .Z(un1_plol_cnt_tc_13)
+);
+defparam \genblk1.un1_plol_cnt_tc_13 .init=16'h0100;
+// @16:387
+  LUT4 rlol1_cnt_tc_1_10_cZ (
+       .A(rlol1_cnt[14]),
+       .B(rlol1_cnt[15]),
+       .C(rlol1_cnt[16]),
+       .D(rlol1_cnt[17]),
+       .Z(rlol1_cnt_tc_1_10)
+);
+defparam rlol1_cnt_tc_1_10_cZ.init=16'h0800;
+// @16:387
+  LUT4 rlol1_cnt_tc_1_11_cZ (
+       .A(rlol1_cnt[0]),
+       .B(rlol1_cnt[1]),
+       .C(rlol1_cnt[2]),
+       .D(rlol1_cnt[3]),
+       .Z(rlol1_cnt_tc_1_11)
+);
+defparam rlol1_cnt_tc_1_11_cZ.init=16'h0001;
+// @16:387
+  LUT4 rlol1_cnt_tc_1_12_cZ (
+       .A(rlol1_cnt[4]),
+       .B(rlol1_cnt[5]),
+       .C(rlol1_cnt[6]),
+       .D(rlol1_cnt[7]),
+       .Z(rlol1_cnt_tc_1_12)
+);
+defparam rlol1_cnt_tc_1_12_cZ.init=16'h0001;
+// @16:387
+  LUT4 rlol1_cnt_tc_1_13_cZ (
+       .A(rlol1_cnt[8]),
+       .B(rlol1_cnt[9]),
+       .C(rlol1_cnt[10]),
+       .D(rlol1_cnt[11]),
+       .Z(rlol1_cnt_tc_1_13)
+);
+defparam rlol1_cnt_tc_1_13_cZ.init=16'h0001;
+// @16:457
+  LUT4 \genblk1.plol0_cnt_3_RNO[2]  (
+       .A(plol0_cnt[0]),
+       .B(waita_plol0),
+       .C(VCC),
+       .D(VCC),
+       .Z(CO0_2)
+);
+defparam \genblk1.plol0_cnt_3_RNO[2] .init=16'h8888;
+// @16:441
+  LUT4 plol_fedge_cZ (
+       .A(pll_lol_p2),
+       .B(pll_lol_p3),
+       .C(VCC),
+       .D(VCC),
+       .Z(plol_fedge)
+);
+defparam plol_fedge_cZ.init=16'h4444;
+// @16:757
+  LUT4 rlos_redge_cZ (
+       .A(rlos_db),
+       .B(rlos_db_p1),
+       .C(VCC),
+       .D(VCC),
+       .Z(rlos_redge)
+);
+defparam rlos_redge_cZ.init=16'h2222;
+// @16:436
+  LUT4 \genblk2.un8_rxs_cnt_tc  (
+       .A(rxs_cnt[0]),
+       .B(rxs_cnt[1]),
+       .C(VCC),
+       .D(VCC),
+       .Z(un8_rxs_cnt_tc)
+);
+defparam \genblk2.un8_rxs_cnt_tc .init=16'h8888;
+// @16:219
+  LUT4 \un1_rlos_db_cnt_zero_am_cZ[0]  (
+       .A(rlos_db_cnt[0]),
+       .B(rlos_db_cnt[1]),
+       .C(rlos_db_cnt[2]),
+       .D(rlos_db_cnt[3]),
+       .Z(un1_rlos_db_cnt_zero_am[0])
+);
+defparam \un1_rlos_db_cnt_zero_am_cZ[0] .init=16'h0001;
+// @16:219
+  LUT4 \un1_rlol_db_cnt_zero_am_cZ[0]  (
+       .A(rlol_db_cnt[0]),
+       .B(rlol_db_cnt[1]),
+       .C(rlol_db_cnt[2]),
+       .D(rlol_db_cnt[3]),
+       .Z(un1_rlol_db_cnt_zero_am[0])
+);
+defparam \un1_rlol_db_cnt_zero_am_cZ[0] .init=16'h0001;
+// @16:454
+  LUT4 \genblk1.plol0_cnt9  (
+       .A(pll_lol_p2),
+       .B(plol0_cnt[2]),
+       .C(plol0_cnt[1]),
+       .D(plol0_cnt[0]),
+       .Z(plol0_cnt9)
+);
+defparam \genblk1.plol0_cnt9 .init=16'hAAAE;
+// @16:783
+  LUT4 \genblk2.rlols0_cnt11_0  (
+       .A(rlol_db_p1),
+       .B(rlol_db),
+       .C(rlos_db_p1),
+       .D(rlos_db),
+       .Z(rlols0_cnt11_0)
+);
+defparam \genblk2.rlols0_cnt11_0 .init=16'h4F44;
+  CCU2C \genblk2.rlol1_cnt_cry_0[0]  (
+       .A0(VCC),
+       .B0(rlol1_cnt_scalar),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_5),
+       .COUT(rlol1_cnt_cry[0]),
+       .S0(rlol1_cnt_cry_0_S0[0]),
+       .S1(rlol1_cnt_s[0])
+);
+defparam \genblk2.rlol1_cnt_cry_0[0] .INIT0=16'h500c;
+defparam \genblk2.rlol1_cnt_cry_0[0] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[0] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[0] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[1]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[1]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[0]),
+       .COUT(rlol1_cnt_cry[2]),
+       .S0(rlol1_cnt_s[1]),
+       .S1(rlol1_cnt_s[2])
+);
+defparam \genblk2.rlol1_cnt_cry_0[1] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[1] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[1] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[1] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[3]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[3]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[4]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[2]),
+       .COUT(rlol1_cnt_cry[4]),
+       .S0(rlol1_cnt_s[3]),
+       .S1(rlol1_cnt_s[4])
+);
+defparam \genblk2.rlol1_cnt_cry_0[3] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[3] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[3] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[3] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[5]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[5]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[6]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[4]),
+       .COUT(rlol1_cnt_cry[6]),
+       .S0(rlol1_cnt_s[5]),
+       .S1(rlol1_cnt_s[6])
+);
+defparam \genblk2.rlol1_cnt_cry_0[5] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[5] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[5] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[5] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[7]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[7]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[8]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[6]),
+       .COUT(rlol1_cnt_cry[8]),
+       .S0(rlol1_cnt_s[7]),
+       .S1(rlol1_cnt_s[8])
+);
+defparam \genblk2.rlol1_cnt_cry_0[7] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[7] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[7] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[7] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[9]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[9]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[10]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[8]),
+       .COUT(rlol1_cnt_cry[10]),
+       .S0(rlol1_cnt_s[9]),
+       .S1(rlol1_cnt_s[10])
+);
+defparam \genblk2.rlol1_cnt_cry_0[9] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[9] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[9] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[9] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[11]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[11]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[12]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[10]),
+       .COUT(rlol1_cnt_cry[12]),
+       .S0(rlol1_cnt_s[11]),
+       .S1(rlol1_cnt_s[12])
+);
+defparam \genblk2.rlol1_cnt_cry_0[11] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[11] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[11] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[11] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[13]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[13]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[14]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[12]),
+       .COUT(rlol1_cnt_cry[14]),
+       .S0(rlol1_cnt_s[13]),
+       .S1(rlol1_cnt_s[14])
+);
+defparam \genblk2.rlol1_cnt_cry_0[13] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[13] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[13] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[13] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[15]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[15]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[16]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[14]),
+       .COUT(rlol1_cnt_cry[16]),
+       .S0(rlol1_cnt_s[15]),
+       .S1(rlol1_cnt_s[16])
+);
+defparam \genblk2.rlol1_cnt_cry_0[15] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[15] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[15] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[15] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[17]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[17]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[18]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[16]),
+       .COUT(rlol1_cnt_cry_0_COUT[17]),
+       .S0(rlol1_cnt_s[17]),
+       .S1(rlol1_cnt_s[18])
+);
+defparam \genblk2.rlol1_cnt_cry_0[17] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[17] .INIT1=16'h800a;
+defparam \genblk2.rlol1_cnt_cry_0[17] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[17] .INJECT1_1="NO";
+  CCU2C \genblk2.rlols0_cnt_cry_0[0]  (
+       .A0(VCC),
+       .B0(rlols0_cnt_scalar),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_4),
+       .COUT(rlols0_cnt_cry[0]),
+       .S0(rlols0_cnt_cry_0_S0[0]),
+       .S1(rlols0_cnt_s[0])
+);
+defparam \genblk2.rlols0_cnt_cry_0[0] .INIT0=16'h500c;
+defparam \genblk2.rlols0_cnt_cry_0[0] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[0] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[0] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[1]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[1]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[0]),
+       .COUT(rlols0_cnt_cry[2]),
+       .S0(rlols0_cnt_s[1]),
+       .S1(rlols0_cnt_s[2])
+);
+defparam \genblk2.rlols0_cnt_cry_0[1] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[1] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[1] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[1] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[3]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[3]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[4]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[2]),
+       .COUT(rlols0_cnt_cry[4]),
+       .S0(rlols0_cnt_s[3]),
+       .S1(rlols0_cnt_s[4])
+);
+defparam \genblk2.rlols0_cnt_cry_0[3] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[3] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[3] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[3] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[5]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[5]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[6]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[4]),
+       .COUT(rlols0_cnt_cry[6]),
+       .S0(rlols0_cnt_s[5]),
+       .S1(rlols0_cnt_s[6])
+);
+defparam \genblk2.rlols0_cnt_cry_0[5] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[5] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[5] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[5] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[7]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[7]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[8]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[6]),
+       .COUT(rlols0_cnt_cry[8]),
+       .S0(rlols0_cnt_s[7]),
+       .S1(rlols0_cnt_s[8])
+);
+defparam \genblk2.rlols0_cnt_cry_0[7] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[7] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[7] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[7] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[9]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[9]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[10]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[8]),
+       .COUT(rlols0_cnt_cry[10]),
+       .S0(rlols0_cnt_s[9]),
+       .S1(rlols0_cnt_s[10])
+);
+defparam \genblk2.rlols0_cnt_cry_0[9] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[9] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[9] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[9] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[11]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[11]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[12]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[10]),
+       .COUT(rlols0_cnt_cry[12]),
+       .S0(rlols0_cnt_s[11]),
+       .S1(rlols0_cnt_s[12])
+);
+defparam \genblk2.rlols0_cnt_cry_0[11] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[11] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[11] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[11] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[13]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[13]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[14]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[12]),
+       .COUT(rlols0_cnt_cry[14]),
+       .S0(rlols0_cnt_s[13]),
+       .S1(rlols0_cnt_s[14])
+);
+defparam \genblk2.rlols0_cnt_cry_0[13] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[13] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[13] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[13] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[15]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[15]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[16]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[14]),
+       .COUT(rlols0_cnt_cry[16]),
+       .S0(rlols0_cnt_s[15]),
+       .S1(rlols0_cnt_s[16])
+);
+defparam \genblk2.rlols0_cnt_cry_0[15] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[15] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[15] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[15] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_s_0[17]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[17]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[16]),
+       .COUT(rlols0_cnt_s_0_COUT[17]),
+       .S0(rlols0_cnt_s[17]),
+       .S1(rlols0_cnt_s_0_S1[17])
+);
+defparam \genblk2.rlols0_cnt_s_0[17] .INIT0=16'h800a;
+defparam \genblk2.rlols0_cnt_s_0[17] .INIT1=16'h5003;
+defparam \genblk2.rlols0_cnt_s_0[17] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_s_0[17] .INJECT1_1="NO";
+  CCU2C \genblk1.plol_cnt_cry_0[0]  (
+       .A0(VCC),
+       .B0(plol_cnt_scalar),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_3),
+       .COUT(plol_cnt_cry[0]),
+       .S0(plol_cnt_cry_0_S0[0]),
+       .S1(plol_cnt_s[0])
+);
+defparam \genblk1.plol_cnt_cry_0[0] .INIT0=16'h500c;
+defparam \genblk1.plol_cnt_cry_0[0] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[0] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[0] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[1]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[1]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[0]),
+       .COUT(plol_cnt_cry[2]),
+       .S0(plol_cnt_s[1]),
+       .S1(plol_cnt_s[2])
+);
+defparam \genblk1.plol_cnt_cry_0[1] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[1] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[1] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[1] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[3]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[3]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[4]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[2]),
+       .COUT(plol_cnt_cry[4]),
+       .S0(plol_cnt_s[3]),
+       .S1(plol_cnt_s[4])
+);
+defparam \genblk1.plol_cnt_cry_0[3] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[3] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[3] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[3] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[5]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[5]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[6]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[4]),
+       .COUT(plol_cnt_cry[6]),
+       .S0(plol_cnt_s[5]),
+       .S1(plol_cnt_s[6])
+);
+defparam \genblk1.plol_cnt_cry_0[5] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[5] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[5] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[5] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[7]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[7]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[8]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[6]),
+       .COUT(plol_cnt_cry[8]),
+       .S0(plol_cnt_s[7]),
+       .S1(plol_cnt_s[8])
+);
+defparam \genblk1.plol_cnt_cry_0[7] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[7] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[7] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[7] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[9]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[9]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[10]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[8]),
+       .COUT(plol_cnt_cry[10]),
+       .S0(plol_cnt_s[9]),
+       .S1(plol_cnt_s[10])
+);
+defparam \genblk1.plol_cnt_cry_0[9] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[9] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[9] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[9] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[11]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[11]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[12]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[10]),
+       .COUT(plol_cnt_cry[12]),
+       .S0(plol_cnt_s[11]),
+       .S1(plol_cnt_s[12])
+);
+defparam \genblk1.plol_cnt_cry_0[11] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[11] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[11] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[11] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[13]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[13]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[14]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[12]),
+       .COUT(plol_cnt_cry[14]),
+       .S0(plol_cnt_s[13]),
+       .S1(plol_cnt_s[14])
+);
+defparam \genblk1.plol_cnt_cry_0[13] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[13] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[13] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[13] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[15]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[15]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[16]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[14]),
+       .COUT(plol_cnt_cry[16]),
+       .S0(plol_cnt_s[15]),
+       .S1(plol_cnt_s[16])
+);
+defparam \genblk1.plol_cnt_cry_0[15] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[15] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[15] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[15] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[17]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[17]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[18]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[16]),
+       .COUT(plol_cnt_cry[18]),
+       .S0(plol_cnt_s[17]),
+       .S1(plol_cnt_s[18])
+);
+defparam \genblk1.plol_cnt_cry_0[17] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[17] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[17] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[17] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_s_0[19]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[19]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[18]),
+       .COUT(plol_cnt_s_0_COUT[19]),
+       .S0(plol_cnt_s[19]),
+       .S1(plol_cnt_s_0_S1[19])
+);
+defparam \genblk1.plol_cnt_s_0[19] .INIT0=16'h800a;
+defparam \genblk1.plol_cnt_s_0[19] .INIT1=16'h5003;
+defparam \genblk1.plol_cnt_s_0[19] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_s_0[19] .INJECT1_1="NO";
+  CCU2C \un1_genblk2.rlos_db_cnt_cry_0_0  (
+       .A0(VCC),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlos_db_cnt[0]),
+       .B1(un1_rlos_db_cnt_zero[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_2),
+       .COUT(rlos_db_cnt_cry_0),
+       .S0(rlos_db_cnt_cry_0_0_S0),
+       .S1(rlos_db_cnt_cry_0_0_S1)
+);
+defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INIT0=16'h5003;
+defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INIT1=16'h900a;
+defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INJECT1_0="NO";
+defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INJECT1_1="NO";
+// @16:641
+  CCU2C \un1_genblk2.rlos_db_cnt_cry_1_0  (
+       .A0(un1_rlos_db_cnt_zero[0]),
+       .B0(rlos_p2),
+       .C0(rlos_db_cnt[1]),
+       .D0(VCC),
+       .A1(un1_rlos_db_cnt_zero[0]),
+       .B1(rlos_p2),
+       .C1(rlos_db_cnt[2]),
+       .D1(VCC),
+       .CIN(rlos_db_cnt_cry_0),
+       .COUT(rlos_db_cnt_cry_2),
+       .S0(rlos_db_cnt_cry_1_0_S0),
+       .S1(rlos_db_cnt_cry_1_0_S1)
+);
+defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INIT0=16'he101;
+defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INIT1=16'he101;
+defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INJECT1_0="NO";
+defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INJECT1_1="NO";
+// @16:641
+  CCU2C \un1_genblk2.rlos_db_cnt_s_3_0  (
+       .A0(rlos_db_cnt[3]),
+       .B0(rlos_p2),
+       .C0(un1_rlos_db_cnt_zero[0]),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlos_db_cnt_cry_2),
+       .COUT(rlos_db_cnt_s_3_0_COUT),
+       .S0(rlos_db_cnt_s_3_0_S0),
+       .S1(rlos_db_cnt_s_3_0_S1)
+);
+defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INIT0=16'ha90a;
+defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INIT1=16'h5003;
+defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INJECT1_0="NO";
+defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INJECT1_1="NO";
+  CCU2C \un1_genblk2.rlol_db_cnt_cry_0_0  (
+       .A0(VCC),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol_db_cnt[0]),
+       .B1(un1_rlol_db_cnt_zero[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_1),
+       .COUT(rlol_db_cnt_cry_0),
+       .S0(rlol_db_cnt_cry_0_0_S0),
+       .S1(rlol_db_cnt_cry_0_0_S1)
+);
+defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INIT0=16'h5003;
+defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INIT1=16'h900a;
+defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INJECT1_0="NO";
+defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INJECT1_1="NO";
+// @16:625
+  CCU2C \un1_genblk2.rlol_db_cnt_cry_1_0  (
+       .A0(un1_rlol_db_cnt_zero[0]),
+       .B0(rlol_p2),
+       .C0(rlol_db_cnt[1]),
+       .D0(VCC),
+       .A1(un1_rlol_db_cnt_zero[0]),
+       .B1(rlol_p2),
+       .C1(rlol_db_cnt[2]),
+       .D1(VCC),
+       .CIN(rlol_db_cnt_cry_0),
+       .COUT(rlol_db_cnt_cry_2),
+       .S0(rlol_db_cnt_cry_1_0_S0),
+       .S1(rlol_db_cnt_cry_1_0_S1)
+);
+defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INIT0=16'he101;
+defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INIT1=16'he101;
+defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INJECT1_0="NO";
+defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INJECT1_1="NO";
+// @16:625
+  CCU2C \un1_genblk2.rlol_db_cnt_s_3_0  (
+       .A0(rlol_db_cnt[3]),
+       .B0(rlol_p2),
+       .C0(un1_rlol_db_cnt_zero[0]),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol_db_cnt_cry_2),
+       .COUT(rlol_db_cnt_s_3_0_COUT),
+       .S0(rlol_db_cnt_s_3_0_S0),
+       .S1(rlol_db_cnt_s_3_0_S1)
+);
+defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INIT0=16'ha90a;
+defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INIT1=16'h5003;
+defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INJECT1_0="NO";
+defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INJECT1_1="NO";
+  VHI VCC_0 (
+       .Z(VCC)
+);
+  VLO GND_cZ (
+       .Z(GND)
+);
+endmodule /* PCSDrsl_core_Z1_layer1 */
+
+module PCSD (
+  hdoutp,
+  hdoutn,
+  hdinp,
+  hdinn,
+  rxrefclk,
+  tx_pclk,
+  txi_clk,
+  txdata,
+  tx_k,
+  xmit,
+  tx_disp_correct,
+  rxdata,
+  rx_k,
+  rx_disp_err,
+  rx_cv_err,
+  signal_detect_c,
+  rx_los_low_s,
+  lsm_status_s,
+  ctc_urun_s,
+  ctc_orun_s,
+  rx_cdr_lol_s,
+  ctc_ins_s,
+  ctc_del_s,
+  tx_pwrup_c,
+  rx_pwrup_c,
+  serdes_pdb,
+  pll_refclki,
+  rsl_disable,
+  rsl_rst,
+  serdes_rst_dual_c,
+  rst_dual_c,
+  tx_serdes_rst_c,
+  tx_pcs_rst_c,
+  pll_lol,
+  rx_serdes_rst_c,
+  rx_pcs_rst_c
+)
+;
+output hdoutp ;
+output hdoutn ;
+input hdinp ;
+input hdinn ;
+input rxrefclk ;
+output tx_pclk ;
+input txi_clk ;
+input [7:0] txdata ;
+input [0:0] tx_k ;
+input [0:0] xmit ;
+input [0:0] tx_disp_correct ;
+output [7:0] rxdata ;
+output [0:0] rx_k ;
+output [0:0] rx_disp_err ;
+output [0:0] rx_cv_err ;
+input signal_detect_c ;
+output rx_los_low_s ;
+output lsm_status_s ;
+output ctc_urun_s ;
+output ctc_orun_s ;
+output rx_cdr_lol_s ;
+output ctc_ins_s ;
+output ctc_del_s ;
+input tx_pwrup_c ;
+input rx_pwrup_c ;
+input serdes_pdb ;
+input pll_refclki ;
+input rsl_disable ;
+input rsl_rst ;
+input serdes_rst_dual_c ;
+input rst_dual_c ;
+input tx_serdes_rst_c ;
+input tx_pcs_rst_c ;
+input pll_lol ;
+input rx_serdes_rst_c ;
+input rx_pcs_rst_c ;
+wire hdoutp ;
+wire hdoutn ;
+wire hdinp ;
+wire hdinn ;
+wire rxrefclk ;
+wire tx_pclk ;
+wire txi_clk ;
+wire signal_detect_c ;
+wire rx_los_low_s ;
+wire lsm_status_s ;
+wire ctc_urun_s ;
+wire ctc_orun_s ;
+wire rx_cdr_lol_s ;
+wire ctc_ins_s ;
+wire ctc_del_s ;
+wire tx_pwrup_c ;
+wire rx_pwrup_c ;
+wire serdes_pdb ;
+wire pll_refclki ;
+wire rsl_disable ;
+wire rsl_rst ;
+wire serdes_rst_dual_c ;
+wire rst_dual_c ;
+wire tx_serdes_rst_c ;
+wire tx_pcs_rst_c ;
+wire pll_lol ;
+wire rx_serdes_rst_c ;
+wire rx_pcs_rst_c ;
+wire rsl_tx_pcs_rst_c ;
+wire rsl_rx_pcs_rst_c ;
+wire rsl_rx_serdes_rst_c ;
+wire rsl_serdes_rst_dual_c ;
+wire rsl_tx_serdes_rst_c ;
+wire n47_1 ;
+wire n48_1 ;
+wire n1_1 ;
+wire n2_1 ;
+wire n3_1 ;
+wire n4_1 ;
+wire n5_1 ;
+wire n49_1 ;
+wire n6_1 ;
+wire n50_1 ;
+wire n7_1 ;
+wire n51_1 ;
+wire n8_1 ;
+wire n52_1 ;
+wire n9_1 ;
+wire n53_1 ;
+wire n54_1 ;
+wire n55_1 ;
+wire n56_1 ;
+wire n57_1 ;
+wire n58_1 ;
+wire n59_1 ;
+wire n60_1 ;
+wire n61_1 ;
+wire n62_1 ;
+wire n63_1 ;
+wire n64_1 ;
+wire n65_1 ;
+wire n10_1 ;
+wire n66_1 ;
+wire n67_1 ;
+wire n68_1 ;
+wire n69_1 ;
+wire n70_1 ;
+wire n71_1 ;
+wire n72_1 ;
+wire n73_1 ;
+wire n74_1 ;
+wire n75_1 ;
+wire n76_1 ;
+wire n77_1 ;
+wire n78_1 ;
+wire n79_1 ;
+wire n80_1 ;
+wire n81_1 ;
+wire n82_1 ;
+wire n83_1 ;
+wire n84_1 ;
+wire n85_1 ;
+wire n86_1 ;
+wire n87_1 ;
+wire n88_1 ;
+wire n11_1 ;
+wire n89_1 ;
+wire n12_1 ;
+wire n90_1 ;
+wire n13_1 ;
+wire n91_1 ;
+wire n92_1 ;
+wire n93_1 ;
+wire n94_1 ;
+wire n95_1 ;
+wire n14_1 ;
+wire n96_1 ;
+wire n15_1 ;
+wire n97_1 ;
+wire n98_1 ;
+wire n99_1 ;
+wire n100_1 ;
+wire n101_1 ;
+wire n102_1 ;
+wire n103_1 ;
+wire n104_1 ;
+wire n105_1 ;
+wire n106_1 ;
+wire n107_1 ;
+wire n108_1 ;
+wire n109_1 ;
+wire n110_1 ;
+wire n121_1 ;
+wire n16_1 ;
+wire n17_1 ;
+wire n18_1 ;
+wire n19_1 ;
+wire n20_1 ;
+wire n21_1 ;
+wire n22_1 ;
+wire n23_1 ;
+wire n24_1 ;
+wire n25_1 ;
+wire n26_1 ;
+wire n27_1 ;
+wire n28_1 ;
+wire n29_1 ;
+wire n30_1 ;
+wire n31_1 ;
+wire n32_1 ;
+wire n33_1 ;
+wire n34_1 ;
+wire n35_1 ;
+wire n36_1 ;
+wire n37_1 ;
+wire n38_1 ;
+wire n39_1 ;
+wire n40_1 ;
+wire n41_1 ;
+wire n42_1 ;
+wire n43_1 ;
+wire n46_1 ;
+wire GND ;
+wire VCC ;
+  VLO GND_0 (
+       .Z(GND)
+);
+  VHI VCC_0 (
+       .Z(VCC)
+);
+  PUR PUR_INST (
+       .PUR(VCC)
+);
+  GSR GSR_INST (
+       .GSR(VCC)
+);
+// @8:118
+(* CHAN="CH0" *)  DCUA DCU0_inst (
+       .CH0_HDINP(hdinp),
+       .CH1_HDINP(GND),
+       .CH0_HDINN(hdinn),
+       .CH1_HDINN(GND),
+       .D_TXBIT_CLKP_FROM_ND(GND),
+       .D_TXBIT_CLKN_FROM_ND(GND),
+       .D_SYNC_ND(GND),
+       .D_TXPLL_LOL_FROM_ND(GND),
+       .CH0_RX_REFCLK(rxrefclk),
+       .CH1_RX_REFCLK(GND),
+       .CH0_FF_RXI_CLK(tx_pclk),
+       .CH1_FF_RXI_CLK(VCC),
+       .CH0_FF_TXI_CLK(txi_clk),
+       .CH1_FF_TXI_CLK(VCC),
+       .CH0_FF_EBRD_CLK(tx_pclk),
+       .CH1_FF_EBRD_CLK(VCC),
+       .CH0_FF_TX_D_0(txdata[0]),
+       .CH1_FF_TX_D_0(GND),
+       .CH0_FF_TX_D_1(txdata[1]),
+       .CH1_FF_TX_D_1(GND),
+       .CH0_FF_TX_D_2(txdata[2]),
+       .CH1_FF_TX_D_2(GND),
+       .CH0_FF_TX_D_3(txdata[3]),
+       .CH1_FF_TX_D_3(GND),
+       .CH0_FF_TX_D_4(txdata[4]),
+       .CH1_FF_TX_D_4(GND),
+       .CH0_FF_TX_D_5(txdata[5]),
+       .CH1_FF_TX_D_5(GND),
+       .CH0_FF_TX_D_6(txdata[6]),
+       .CH1_FF_TX_D_6(GND),
+       .CH0_FF_TX_D_7(txdata[7]),
+       .CH1_FF_TX_D_7(GND),
+       .CH0_FF_TX_D_8(tx_k[0]),
+       .CH1_FF_TX_D_8(GND),
+       .CH0_FF_TX_D_9(GND),
+       .CH1_FF_TX_D_9(GND),
+       .CH0_FF_TX_D_10(xmit[0]),
+       .CH1_FF_TX_D_10(GND),
+       .CH0_FF_TX_D_11(tx_disp_correct[0]),
+       .CH1_FF_TX_D_11(GND),
+       .CH0_FF_TX_D_12(GND),
+       .CH1_FF_TX_D_12(GND),
+       .CH0_FF_TX_D_13(GND),
+       .CH1_FF_TX_D_13(GND),
+       .CH0_FF_TX_D_14(GND),
+       .CH1_FF_TX_D_14(GND),
+       .CH0_FF_TX_D_15(GND),
+       .CH1_FF_TX_D_15(GND),
+       .CH0_FF_TX_D_16(GND),
+       .CH1_FF_TX_D_16(GND),
+       .CH0_FF_TX_D_17(GND),
+       .CH1_FF_TX_D_17(GND),
+       .CH0_FF_TX_D_18(GND),
+       .CH1_FF_TX_D_18(GND),
+       .CH0_FF_TX_D_19(GND),
+       .CH1_FF_TX_D_19(GND),
+       .CH0_FF_TX_D_20(GND),
+       .CH1_FF_TX_D_20(GND),
+       .CH0_FF_TX_D_21(GND),
+       .CH1_FF_TX_D_21(GND),
+       .CH0_FF_TX_D_22(GND),
+       .CH1_FF_TX_D_22(GND),
+       .CH0_FF_TX_D_23(GND),
+       .CH1_FF_TX_D_23(GND),
+       .CH0_FFC_EI_EN(GND),
+       .CH1_FFC_EI_EN(GND),
+       .CH0_FFC_PCIE_DET_EN(GND),
+       .CH1_FFC_PCIE_DET_EN(GND),
+       .CH0_FFC_PCIE_CT(GND),
+       .CH1_FFC_PCIE_CT(GND),
+       .CH0_FFC_SB_INV_RX(GND),
+       .CH1_FFC_SB_INV_RX(GND),
+       .CH0_FFC_ENABLE_CGALIGN(GND),
+       .CH1_FFC_ENABLE_CGALIGN(GND),
+       .CH0_FFC_SIGNAL_DETECT(signal_detect_c),
+       .CH1_FFC_SIGNAL_DETECT(GND),
+       .CH0_FFC_FB_LOOPBACK(GND),
+       .CH1_FFC_FB_LOOPBACK(GND),
+       .CH0_FFC_SB_PFIFO_LP(GND),
+       .CH1_FFC_SB_PFIFO_LP(GND),
+       .CH0_FFC_PFIFO_CLR(GND),
+       .CH1_FFC_PFIFO_CLR(GND),
+       .CH0_FFC_RATE_MODE_RX(GND),
+       .CH1_FFC_RATE_MODE_RX(GND),
+       .CH0_FFC_RATE_MODE_TX(GND),
+       .CH1_FFC_RATE_MODE_TX(GND),
+       .CH0_FFC_DIV11_MODE_RX(GND),
+       .CH1_FFC_DIV11_MODE_RX(GND),
+       .CH0_FFC_RX_GEAR_MODE(GND),
+       .CH1_FFC_RX_GEAR_MODE(GND),
+       .CH0_FFC_TX_GEAR_MODE(GND),
+       .CH1_FFC_TX_GEAR_MODE(GND),
+       .CH0_FFC_DIV11_MODE_TX(GND),
+       .CH1_FFC_DIV11_MODE_TX(GND),
+       .CH0_FFC_LDR_CORE2TX_EN(GND),
+       .CH1_FFC_LDR_CORE2TX_EN(GND),
+       .CH0_FFC_LANE_TX_RST(rsl_tx_pcs_rst_c),
+       .CH1_FFC_LANE_TX_RST(GND),
+       .CH0_FFC_LANE_RX_RST(rsl_rx_pcs_rst_c),
+       .CH1_FFC_LANE_RX_RST(GND),
+       .CH0_FFC_RRST(rsl_rx_serdes_rst_c),
+       .CH1_FFC_RRST(GND),
+       .CH0_FFC_TXPWDNB(tx_pwrup_c),
+       .CH1_FFC_TXPWDNB(GND),
+       .CH0_FFC_RXPWDNB(rx_pwrup_c),
+       .CH1_FFC_RXPWDNB(GND),
+       .CH0_LDR_CORE2TX(GND),
+       .CH1_LDR_CORE2TX(GND),
+       .D_SCIWDATA0(GND),
+       .D_SCIWDATA1(GND),
+       .D_SCIWDATA2(GND),
+       .D_SCIWDATA3(GND),
+       .D_SCIWDATA4(GND),
+       .D_SCIWDATA5(GND),
+       .D_SCIWDATA6(GND),
+       .D_SCIWDATA7(GND),
+       .D_SCIADDR0(GND),
+       .D_SCIADDR1(GND),
+       .D_SCIADDR2(GND),
+       .D_SCIADDR3(GND),
+       .D_SCIADDR4(GND),
+       .D_SCIADDR5(GND),
+       .D_SCIENAUX(GND),
+       .D_SCISELAUX(GND),
+       .CH0_SCIEN(GND),
+       .CH1_SCIEN(GND),
+       .CH0_SCISEL(GND),
+       .CH1_SCISEL(GND),
+       .D_SCIRD(GND),
+       .D_SCIWSTN(GND),
+       .D_CYAWSTN(GND),
+       .D_FFC_SYNC_TOGGLE(GND),
+       .D_FFC_DUAL_RST(rst_dual_c),
+       .D_FFC_MACRO_RST(rsl_serdes_rst_dual_c),
+       .D_FFC_MACROPDB(serdes_pdb),
+       .D_FFC_TRST(rsl_tx_serdes_rst_c),
+       .CH0_FFC_CDR_EN_BITSLIP(GND),
+       .CH1_FFC_CDR_EN_BITSLIP(GND),
+       .D_SCAN_ENABLE(GND),
+       .D_SCAN_IN_0(GND),
+       .D_SCAN_IN_1(GND),
+       .D_SCAN_IN_2(GND),
+       .D_SCAN_IN_3(GND),
+       .D_SCAN_IN_4(GND),
+       .D_SCAN_IN_5(GND),
+       .D_SCAN_IN_6(GND),
+       .D_SCAN_IN_7(GND),
+       .D_SCAN_MODE(GND),
+       .D_SCAN_RESET(GND),
+       .D_CIN0(GND),
+       .D_CIN1(GND),
+       .D_CIN2(GND),
+       .D_CIN3(GND),
+       .D_CIN4(GND),
+       .D_CIN5(GND),
+       .D_CIN6(GND),
+       .D_CIN7(GND),
+       .D_CIN8(GND),
+       .D_CIN9(GND),
+       .D_CIN10(GND),
+       .D_CIN11(GND),
+       .CH0_HDOUTP(hdoutp),
+       .CH1_HDOUTP(n47_1),
+       .CH0_HDOUTN(hdoutn),
+       .CH1_HDOUTN(n48_1),
+       .D_TXBIT_CLKP_TO_ND(n1_1),
+       .D_TXBIT_CLKN_TO_ND(n2_1),
+       .D_SYNC_PULSE2ND(n3_1),
+       .D_TXPLL_LOL_TO_ND(n4_1),
+       .CH0_FF_RX_F_CLK(n5_1),
+       .CH1_FF_RX_F_CLK(n49_1),
+       .CH0_FF_RX_H_CLK(n6_1),
+       .CH1_FF_RX_H_CLK(n50_1),
+       .CH0_FF_TX_F_CLK(n7_1),
+       .CH1_FF_TX_F_CLK(n51_1),
+       .CH0_FF_TX_H_CLK(n8_1),
+       .CH1_FF_TX_H_CLK(n52_1),
+       .CH0_FF_RX_PCLK(n9_1),
+       .CH1_FF_RX_PCLK(n53_1),
+       .CH0_FF_TX_PCLK(tx_pclk),
+       .CH1_FF_TX_PCLK(n54_1),
+       .CH0_FF_RX_D_0(rxdata[0]),
+       .CH1_FF_RX_D_0(n55_1),
+       .CH0_FF_RX_D_1(rxdata[1]),
+       .CH1_FF_RX_D_1(n56_1),
+       .CH0_FF_RX_D_2(rxdata[2]),
+       .CH1_FF_RX_D_2(n57_1),
+       .CH0_FF_RX_D_3(rxdata[3]),
+       .CH1_FF_RX_D_3(n58_1),
+       .CH0_FF_RX_D_4(rxdata[4]),
+       .CH1_FF_RX_D_4(n59_1),
+       .CH0_FF_RX_D_5(rxdata[5]),
+       .CH1_FF_RX_D_5(n60_1),
+       .CH0_FF_RX_D_6(rxdata[6]),
+       .CH1_FF_RX_D_6(n61_1),
+       .CH0_FF_RX_D_7(rxdata[7]),
+       .CH1_FF_RX_D_7(n62_1),
+       .CH0_FF_RX_D_8(rx_k[0]),
+       .CH1_FF_RX_D_8(n63_1),
+       .CH0_FF_RX_D_9(rx_disp_err[0]),
+       .CH1_FF_RX_D_9(n64_1),
+       .CH0_FF_RX_D_10(rx_cv_err[0]),
+       .CH1_FF_RX_D_10(n65_1),
+       .CH0_FF_RX_D_11(n10_1),
+       .CH1_FF_RX_D_11(n66_1),
+       .CH0_FF_RX_D_12(n67_1),
+       .CH1_FF_RX_D_12(n68_1),
+       .CH0_FF_RX_D_13(n69_1),
+       .CH1_FF_RX_D_13(n70_1),
+       .CH0_FF_RX_D_14(n71_1),
+       .CH1_FF_RX_D_14(n72_1),
+       .CH0_FF_RX_D_15(n73_1),
+       .CH1_FF_RX_D_15(n74_1),
+       .CH0_FF_RX_D_16(n75_1),
+       .CH1_FF_RX_D_16(n76_1),
+       .CH0_FF_RX_D_17(n77_1),
+       .CH1_FF_RX_D_17(n78_1),
+       .CH0_FF_RX_D_18(n79_1),
+       .CH1_FF_RX_D_18(n80_1),
+       .CH0_FF_RX_D_19(n81_1),
+       .CH1_FF_RX_D_19(n82_1),
+       .CH0_FF_RX_D_20(n83_1),
+       .CH1_FF_RX_D_20(n84_1),
+       .CH0_FF_RX_D_21(n85_1),
+       .CH1_FF_RX_D_21(n86_1),
+       .CH0_FF_RX_D_22(n87_1),
+       .CH1_FF_RX_D_22(n88_1),
+       .CH0_FF_RX_D_23(n11_1),
+       .CH1_FF_RX_D_23(n89_1),
+       .CH0_FFS_PCIE_DONE(n12_1),
+       .CH1_FFS_PCIE_DONE(n90_1),
+       .CH0_FFS_PCIE_CON(n13_1),
+       .CH1_FFS_PCIE_CON(n91_1),
+       .CH0_FFS_RLOS(rx_los_low_s),
+       .CH1_FFS_RLOS(n92_1),
+       .CH0_FFS_LS_SYNC_STATUS(lsm_status_s),
+       .CH1_FFS_LS_SYNC_STATUS(n93_1),
+       .CH0_FFS_CC_UNDERRUN(ctc_urun_s),
+       .CH1_FFS_CC_UNDERRUN(n94_1),
+       .CH0_FFS_CC_OVERRUN(ctc_orun_s),
+       .CH1_FFS_CC_OVERRUN(n95_1),
+       .CH0_FFS_RXFBFIFO_ERROR(n14_1),
+       .CH1_FFS_RXFBFIFO_ERROR(n96_1),
+       .CH0_FFS_TXFBFIFO_ERROR(n15_1),
+       .CH1_FFS_TXFBFIFO_ERROR(n97_1),
+       .CH0_FFS_RLOL(rx_cdr_lol_s),
+       .CH1_FFS_RLOL(n98_1),
+       .CH0_FFS_SKP_ADDED(ctc_ins_s),
+       .CH1_FFS_SKP_ADDED(n99_1),
+       .CH0_FFS_SKP_DELETED(ctc_del_s),
+       .CH1_FFS_SKP_DELETED(n100_1),
+       .CH0_LDR_RX2CORE(n101_1),
+       .CH1_LDR_RX2CORE(n102_1),
+       .D_SCIRDATA0(n103_1),
+       .D_SCIRDATA1(n104_1),
+       .D_SCIRDATA2(n105_1),
+       .D_SCIRDATA3(n106_1),
+       .D_SCIRDATA4(n107_1),
+       .D_SCIRDATA5(n108_1),
+       .D_SCIRDATA6(n109_1),
+       .D_SCIRDATA7(n110_1),
+       .D_SCIINT(n121_1),
+       .D_SCAN_OUT_0(n16_1),
+       .D_SCAN_OUT_1(n17_1),
+       .D_SCAN_OUT_2(n18_1),
+       .D_SCAN_OUT_3(n19_1),
+       .D_SCAN_OUT_4(n20_1),
+       .D_SCAN_OUT_5(n21_1),
+       .D_SCAN_OUT_6(n22_1),
+       .D_SCAN_OUT_7(n23_1),
+       .D_COUT0(n24_1),
+       .D_COUT1(n25_1),
+       .D_COUT2(n26_1),
+       .D_COUT3(n27_1),
+       .D_COUT4(n28_1),
+       .D_COUT5(n29_1),
+       .D_COUT6(n30_1),
+       .D_COUT7(n31_1),
+       .D_COUT8(n32_1),
+       .D_COUT9(n33_1),
+       .D_COUT10(n34_1),
+       .D_COUT11(n35_1),
+       .D_COUT12(n36_1),
+       .D_COUT13(n37_1),
+       .D_COUT14(n38_1),
+       .D_COUT15(n39_1),
+       .D_COUT16(n40_1),
+       .D_COUT17(n41_1),
+       .D_COUT18(n42_1),
+       .D_COUT19(n43_1),
+       .D_REFCLKI(pll_refclki),
+       .D_FFS_PLOL(n46_1)
+);
+defparam DCU0_inst.D_MACROPDB = "0b1";
+defparam DCU0_inst.D_IB_PWDNB = "0b1";
+defparam DCU0_inst.D_XGE_MODE = "0b0";
+defparam DCU0_inst.D_LOW_MARK = "0d4";
+defparam DCU0_inst.D_HIGH_MARK = "0d12";
+defparam DCU0_inst.D_BUS8BIT_SEL = "0b0";
+defparam DCU0_inst.D_CDR_LOL_SET = "0b00";
+defparam DCU0_inst.D_BITCLK_LOCAL_EN = "0b1";
+defparam DCU0_inst.D_BITCLK_ND_EN = "0b0";
+defparam DCU0_inst.D_BITCLK_FROM_ND_EN = "0b0";
+defparam DCU0_inst.D_SYNC_LOCAL_EN = "0b1";
+defparam DCU0_inst.D_SYNC_ND_EN = "0b0";
+defparam DCU0_inst.CH0_UC_MODE = "0b0";
+defparam DCU0_inst.CH0_PCIE_MODE = "0b0";
+defparam DCU0_inst.CH0_RIO_MODE = "0b0";
+defparam DCU0_inst.CH0_WA_MODE = "0b0";
+defparam DCU0_inst.CH0_INVERT_RX = "0b0";
+defparam DCU0_inst.CH0_INVERT_TX = "0b0";
+defparam DCU0_inst.CH0_PRBS_SELECTION = "0b0";
+defparam DCU0_inst.CH0_GE_AN_ENABLE = "0b0";
+defparam DCU0_inst.CH0_PRBS_LOCK = "0b0";
+defparam DCU0_inst.CH0_PRBS_ENABLE = "0b0";
+defparam DCU0_inst.CH0_ENABLE_CG_ALIGN = "0b1";
+defparam DCU0_inst.CH0_TX_GEAR_MODE = "0b0";
+defparam DCU0_inst.CH0_RX_GEAR_MODE = "0b0";
+defparam DCU0_inst.CH0_PCS_DET_TIME_SEL = "0b00";
+defparam DCU0_inst.CH0_PCIE_EI_EN = "0b0";
+defparam DCU0_inst.CH0_TX_GEAR_BYPASS = "0b0";
+defparam DCU0_inst.CH0_ENC_BYPASS = "0b0";
+defparam DCU0_inst.CH0_SB_BYPASS = "0b0";
+defparam DCU0_inst.CH0_RX_SB_BYPASS = "0b0";
+defparam DCU0_inst.CH0_WA_BYPASS = "0b0";
+defparam DCU0_inst.CH0_DEC_BYPASS = "0b0";
+defparam DCU0_inst.CH0_CTC_BYPASS = "0b0";
+defparam DCU0_inst.CH0_RX_GEAR_BYPASS = "0b0";
+defparam DCU0_inst.CH0_LSM_DISABLE = "0b0";
+defparam DCU0_inst.CH0_MATCH_2_ENABLE = "0b1";
+defparam DCU0_inst.CH0_MATCH_4_ENABLE = "0b0";
+defparam DCU0_inst.CH0_MIN_IPG_CNT = "0b11";
+defparam DCU0_inst.CH0_CC_MATCH_1 = "0x000";
+defparam DCU0_inst.CH0_CC_MATCH_2 = "0x000";
+defparam DCU0_inst.CH0_CC_MATCH_3 = "0x1BC";
+defparam DCU0_inst.CH0_CC_MATCH_4 = "0x050";
+defparam DCU0_inst.CH0_UDF_COMMA_MASK = "0x3ff";
+defparam DCU0_inst.CH0_UDF_COMMA_A = "0x283";
+defparam DCU0_inst.CH0_UDF_COMMA_B = "0x17C";
+defparam DCU0_inst.CH0_RX_DCO_CK_DIV = "0b010";
+defparam DCU0_inst.CH0_RCV_DCC_EN = "0b0";
+defparam DCU0_inst.CH0_REQ_LVL_SET = "0b00";
+defparam DCU0_inst.CH0_REQ_EN = "0b1";
+defparam DCU0_inst.CH0_RTERM_RX = "0d22";
+defparam DCU0_inst.CH0_PDEN_SEL = "0b1";
+defparam DCU0_inst.CH0_LDR_RX2CORE_SEL = "0b0";
+defparam DCU0_inst.CH0_LDR_CORE2TX_SEL = "0b0";
+defparam DCU0_inst.CH0_TPWDNB = "0b1";
+defparam DCU0_inst.CH0_RATE_MODE_TX = "0b0";
+defparam DCU0_inst.CH0_RTERM_TX = "0d19";
+defparam DCU0_inst.CH0_TX_CM_SEL = "0b00";
+defparam DCU0_inst.CH0_TDRV_PRE_EN = "0b0";
+defparam DCU0_inst.CH0_TDRV_SLICE0_SEL = "0b01";
+defparam DCU0_inst.CH0_TDRV_SLICE1_SEL = "0b00";
+defparam DCU0_inst.CH0_TDRV_SLICE2_SEL = "0b01";
+defparam DCU0_inst.CH0_TDRV_SLICE3_SEL = "0b01";
+defparam DCU0_inst.CH0_TDRV_SLICE4_SEL = "0b01";
+defparam DCU0_inst.CH0_TDRV_SLICE5_SEL = "0b01";
+defparam DCU0_inst.CH0_TDRV_SLICE0_CUR = "0b101";
+defparam DCU0_inst.CH0_TDRV_SLICE1_CUR = "0b000";
+defparam DCU0_inst.CH0_TDRV_SLICE2_CUR = "0b11";
+defparam DCU0_inst.CH0_TDRV_SLICE3_CUR = "0b11";
+defparam DCU0_inst.CH0_TDRV_SLICE4_CUR = "0b11";
+defparam DCU0_inst.CH0_TDRV_SLICE5_CUR = "0b00";
+defparam DCU0_inst.CH0_TDRV_DAT_SEL = "0b00";
+defparam DCU0_inst.CH0_TX_DIV11_SEL = "0b0";
+defparam DCU0_inst.CH0_RPWDNB = "0b1";
+defparam DCU0_inst.CH0_RATE_MODE_RX = "0b0";
+defparam DCU0_inst.CH0_RLOS_SEL = "0b1";
+defparam DCU0_inst.CH0_RX_LOS_LVL = "0b010";
+defparam DCU0_inst.CH0_RX_LOS_CEQ = "0b11";
+defparam DCU0_inst.CH0_RX_LOS_HYST_EN = "0b0";
+defparam DCU0_inst.CH0_RX_LOS_EN = "0b1";
+defparam DCU0_inst.CH0_RX_DIV11_SEL = "0b0";
+defparam DCU0_inst.CH0_SEL_SD_RX_CLK = "0b0";
+defparam DCU0_inst.CH0_FF_RX_H_CLK_EN = "0b0";
+defparam DCU0_inst.CH0_FF_RX_F_CLK_DIS = "0b0";
+defparam DCU0_inst.CH0_FF_TX_H_CLK_EN = "0b0";
+defparam DCU0_inst.CH0_FF_TX_F_CLK_DIS = "0b0";
+defparam DCU0_inst.CH0_RX_RATE_SEL = "0d8";
+defparam DCU0_inst.CH0_TDRV_POST_EN = "0b0";
+defparam DCU0_inst.CH0_TX_POST_SIGN = "0b0";
+defparam DCU0_inst.CH0_TX_PRE_SIGN = "0b0";
+defparam DCU0_inst.CH0_RXTERM_CM = "0b11";
+defparam DCU0_inst.CH0_RXIN_CM = "0b11";
+defparam DCU0_inst.CH0_LEQ_OFFSET_SEL = "0b0";
+defparam DCU0_inst.CH0_LEQ_OFFSET_TRIM = "0b000";
+defparam DCU0_inst.D_TX_MAX_RATE = "1.25";
+defparam DCU0_inst.CH0_CDR_MAX_RATE = "1.25";
+defparam DCU0_inst.CH0_TXAMPLITUDE = "0d1100";
+defparam DCU0_inst.CH0_TXDEPRE = "DISABLED";
+defparam DCU0_inst.CH0_TXDEPOST = "DISABLED";
+defparam DCU0_inst.CH0_PROTOCOL = "GBE";
+defparam DCU0_inst.D_ISETLOS = "0d0";
+defparam DCU0_inst.D_SETIRPOLY_AUX = "0b00";
+defparam DCU0_inst.D_SETICONST_AUX = "0b00";
+defparam DCU0_inst.D_SETIRPOLY_CH = "0b00";
+defparam DCU0_inst.D_SETICONST_CH = "0b00";
+defparam DCU0_inst.D_REQ_ISET = "0b000";
+defparam DCU0_inst.D_PD_ISET = "0b00";
+defparam DCU0_inst.D_DCO_CALIB_TIME_SEL = "0b00";
+defparam DCU0_inst.CH0_DCOCTLGI = "0b010";
+defparam DCU0_inst.CH0_DCOATDDLY = "0b00";
+defparam DCU0_inst.CH0_DCOATDCFG = "0b00";
+defparam DCU0_inst.CH0_DCOBYPSATD = "0b1";
+defparam DCU0_inst.CH0_DCOSCALEI = "0b00";
+defparam DCU0_inst.CH0_DCOITUNE4LSB = "0b111";
+defparam DCU0_inst.CH0_DCOIOSTUNE = "0b000";
+defparam DCU0_inst.CH0_DCODISBDAVOID = "0b0";
+defparam DCU0_inst.CH0_DCOCALDIV = "0b001";
+defparam DCU0_inst.CH0_DCONUOFLSB = "0b101";
+defparam DCU0_inst.CH0_DCOIUPDNX2 = "0b1";
+defparam DCU0_inst.CH0_DCOSTEP = "0b00";
+defparam DCU0_inst.CH0_DCOSTARTVAL = "0b000";
+defparam DCU0_inst.CH0_DCOFLTDAC = "0b01";
+defparam DCU0_inst.CH0_DCOITUNE = "0b00";
+defparam DCU0_inst.CH0_DCOFTNRG = "0b110";
+defparam DCU0_inst.CH0_CDR_CNT4SEL = "0b00";
+defparam DCU0_inst.CH0_CDR_CNT8SEL = "0b00";
+defparam DCU0_inst.CH0_BAND_THRESHOLD = "0d0";
+defparam DCU0_inst.CH0_AUTO_FACQ_EN = "0b1";
+defparam DCU0_inst.CH0_AUTO_CALIB_EN = "0b1";
+defparam DCU0_inst.CH0_CALIB_CK_MODE = "0b0";
+defparam DCU0_inst.CH0_REG_BAND_OFFSET = "0d0";
+defparam DCU0_inst.CH0_REG_BAND_SEL = "0d0";
+defparam DCU0_inst.CH0_REG_IDAC_SEL = "0d0";
+defparam DCU0_inst.CH0_REG_IDAC_EN = "0b0";
+defparam DCU0_inst.D_TXPLL_PWDNB = "0b1";
+defparam DCU0_inst.D_SETPLLRC = "0d1";
+defparam DCU0_inst.D_REFCK_MODE = "0b001";
+defparam DCU0_inst.D_TX_VCO_CK_DIV = "0b010";
+defparam DCU0_inst.D_PLL_LOL_SET = "0b00";
+defparam DCU0_inst.D_RG_EN = "0b0";
+defparam DCU0_inst.D_RG_SET = "0b00";
+defparam DCU0_inst.D_CMUSETISCL4VCO = "0b000";
+defparam DCU0_inst.D_CMUSETI4VCO = "0b00";
+defparam DCU0_inst.D_CMUSETINITVCT = "0b00";
+defparam DCU0_inst.D_CMUSETZGM = "0b000";
+defparam DCU0_inst.D_CMUSETP2AGM = "0b000";
+defparam DCU0_inst.D_CMUSETP1GM = "0b000";
+defparam DCU0_inst.D_CMUSETI4CPZ = "0d3";
+defparam DCU0_inst.D_CMUSETI4CPP = "0d3";
+defparam DCU0_inst.D_CMUSETICP4Z = "0b101";
+defparam DCU0_inst.D_CMUSETICP4P = "0b01";
+defparam DCU0_inst.D_CMUSETBIASI = "0b00";
+// @8:357
+  PCSDrsl_core_Z1_layer1 rsl_inst (
+       .serdes_rst_dual_c(serdes_rst_dual_c),
+       .rx_serdes_rst_c(rx_serdes_rst_c),
+       .tx_serdes_rst_c(tx_serdes_rst_c),
+       .rsl_rx_pcs_rst_c(rsl_rx_pcs_rst_c),
+       .rx_pcs_rst_c(rx_pcs_rst_c),
+       .rsl_tx_pcs_rst_c(rsl_tx_pcs_rst_c),
+       .tx_pcs_rst_c(tx_pcs_rst_c),
+       .rsl_disable(rsl_disable),
+       .rsl_tx_serdes_rst_c(rsl_tx_serdes_rst_c),
+       .pll_lol(pll_lol),
+       .pll_refclki(pll_refclki),
+       .rx_cdr_lol_s(rx_cdr_lol_s),
+       .rx_los_low_s(rx_los_low_s),
+       .rsl_rst(rsl_rst),
+       .rxrefclk(rxrefclk),
+       .rsl_rx_serdes_rst_c(rsl_rx_serdes_rst_c),
+       .rsl_serdes_rst_dual_c(rsl_serdes_rst_dual_c)
+);
+endmodule /* PCSD */
+

diff --git a/gbe/cores/sgmii/PCSD/syn_results/PCSD_cck.rpt.db b/gbe/cores/sgmii/PCSD/syn_results/PCSD_cck.rpt.db
new file mode 100644 (file)
index 0000000..029fa7a
Binary files /dev/null and b/gbe/cores/sgmii/PCSD/syn_results/PCSD_cck.rpt.db differ

diff --git a/gbe/cores/sgmii/PCSD/syn_results/PCSD_scck.rpt.db b/gbe/cores/sgmii/PCSD/syn_results/PCSD_scck.rpt.db
new file mode 100644 (file)
index 0000000..029fa7a
Binary files /dev/null and b/gbe/cores/sgmii/PCSD/syn_results/PCSD_scck.rpt.db differ

diff --git a/gbe/cores/sgmii/PCSD/syn_results/PCSD_synplify.lpf b/gbe/cores/sgmii/PCSD/syn_results/PCSD_synplify.lpf
new file mode 100644 (file)
index 0000000..a0470d8
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/PCSD_synplify.lpf
@@ -0,0 +1,24 @@
+#
+# Logical Preferences generated for Lattice by Synplify maplat, Build 1796R.
+#
+
+# Period Constraints 
+#FREQUENCY PORT "pll_refclki" 100.0 MHz;
+#FREQUENCY PORT "rxrefclk" 100.0 MHz;
+
+
+# Output Constraints 
+
+# Input Constraints 
+
+# Point-to-point Delay Constraints 
+
+
+
+# Block Path Constraints 
+#BLOCK PATH FROM CLKNET "rxrefclk" TO CLKNET "pll_refclki";
+#BLOCK PATH FROM CLKNET "pll_refclki" TO CLKNET "rxrefclk";
+
+BLOCK ASYNCPATHS;
+
+# End of generated Logical Preferences.

diff --git a/gbe/cores/sgmii/PCSD/syn_results/PCSD_synplify_tmp2.lpf b/gbe/cores/sgmii/PCSD/syn_results/PCSD_synplify_tmp2.lpf
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/sgmii/PCSD/syn_results/PCSD_synplify_tmp4.lpf b/gbe/cores/sgmii/PCSD/syn_results/PCSD_synplify_tmp4.lpf
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/sgmii/PCSD/syn_results/PCSD_synplify_tmp8.lpf b/gbe/cores/sgmii/PCSD/syn_results/PCSD_synplify_tmp8.lpf
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/sgmii/PCSD/syn_results/_CMD_.CML b/gbe/cores/sgmii/PCSD/syn_results/_CMD_.CML
new file mode 100644 (file)
index 0000000..c760b6f
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/_CMD_.CML
@@ -0,0 +1 @@
+ -osyn  /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.srs  -top  PCSD  -hdllog  /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/PCSD_compiler.srr  -encrypt  -mp  4  -verification_mode 0  -vhdl  -prodtype  synplify_pro  -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver  -encrypt  -pro  -dmgen  /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/dm  -lite -ui -fid2 -ram -sharing on -ll 2000 -autosm  -ignore_undefined_lib  -lib work /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd  -verilog  -prodtype  synplify_pro  -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver   -I /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/  -I /home/soft/lattice/diamond/3.10_x64/synpbase/lib   -v2001  -devicelib  /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v  -devicelib  /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v  -encrypt  -pro  -dmgen  /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/dm  -ui -fid2 -ram -sharing on -ll 2000 -autosm  -lib work /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v  -jobname  "compiler" 
\ No newline at end of file

diff --git a/gbe/cores/sgmii/PCSD/syn_results/_cmd._cml b/gbe/cores/sgmii/PCSD/syn_results/_cmd._cml
new file mode 100644 (file)
index 0000000..a2a52c2
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/_cmd._cml
@@ -0,0 +1 @@
+-link    -encrypt        -top PCSD -osyn /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.srs /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/layer0.srs /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/layer1.srs   
\ No newline at end of file

diff --git a/gbe/cores/sgmii/PCSD/syn_results/backup/PCSD.srr b/gbe/cores/sgmii/PCSD/syn_results/backup/PCSD.srr
new file mode 100644 (file)
index 0000000..20082f7
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/backup/PCSD.srr
@@ -0,0 +1,1157 @@
+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
+#install: /home/soft/lattice/diamond/3.10_x64/synpbase
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Mon Apr 29 14:56:30 2019
+
+#Implementation: syn_results
+
+Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":30:7:30:10|Top entity is set to PCSD.
+VHDL syntax check successful!
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Mon Apr 29 14:56:30 2019
+
+###########################################################]
+Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v" (library work)
+Verilog syntax check successful!
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Mon Apr 29 14:56:30 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":30:7:30:10|Top entity is set to PCSD.
+VHDL syntax check successful!
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":30:7:30:10|Synthesizing work.pcsd.v1.
+Post processing for work.pcsd.v1
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB)
+
+
+Process completed successfully.
+# Mon Apr 29 14:56:31 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v" (library work)
+Verilog syntax check successful!
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
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+Could not match passed parameter, trying a case insensitive search ...
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+Could not match passed parameter, trying a case insensitive search ...
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+Could not match passed parameter, trying a case insensitive search ...
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+Could not match passed parameter, trying a case insensitive search ...
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+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
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+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
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+Could not match passed parameter, trying a case insensitive search ...
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+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
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+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
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+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work.
+
+       PDATA_RST_VAL=32'b00000000000000000000000000000000
+   Generated name = sync_0s
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1051:7:1051:18|Synthesizing module PCSDsll_core in library work.
+
+       PPROTOCOL=24'b010001110100001001000101
+       PLOL_SETTING=32'b00000000000000000000000000000000
+       PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100
+       PPCIE_MAX_RATE=24'b001100100010111000110101
+       PDIFF_VAL_LOCK=32'b00000000000000000000000000100111
+       PDIFF_VAL_UNLOCK=32'b00000000000000000000000001001110
+       PPCLK_TC=32'b00000000000000100000000000000000
+       PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000
+       PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000
+       PPCLK_DIV11_TC=32'b00000000000000000000000000000000
+       LPLL_LOSS_ST=2'b00
+       LPLL_PRELOSS_ST=2'b01
+       LPLL_PRELOCK_ST=2'b10
+       LPLL_LOCK_ST=2'b11
+       LRCLK_TC=16'b1111111111111111
+       LRCLK_TC_PUL_WIDTH=16'b0000000000110010
+       LHB_WAIT_CNT=8'b11111111
+       LPCLK_TC_0=32'b00000000000000001000000000000000
+       LPCLK_TC_1=32'b00000000000000010000000000000000
+       LPCLK_TC_2=32'b00000000000000100000000000000000
+       LPCLK_TC_3=32'b00000000000000101000000000000000
+       LPCLK_TC_4=32'b00000000000000010000000000000000
+       LPDIFF_LOCK_00=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_10=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_20=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_30=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_40=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_01=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_11=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_21=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_31=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_41=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_02=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_12=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_22=32'b00000000000000000000000011000100
+       LPDIFF_LOCK_32=32'b00000000000000000000000011110101
+       LPDIFF_LOCK_42=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_03=32'b00000000000000000000000010000011
+       LPDIFF_LOCK_13=32'b00000000000000000000000100000110
+       LPDIFF_LOCK_23=32'b00000000000000000000001000001100
+       LPDIFF_LOCK_33=32'b00000000000000000000001010001111
+       LPDIFF_LOCK_43=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011
+       LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110
+       LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010
+       LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001
+       LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111
+       LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000
+       LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000
+       LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000
+       LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100
+       LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001
+       LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010
+       LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111
+       LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001
+   Generated name = PCSDsll_core_Z1_layer1
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1287:54:1287:59|Removing redundant assignment.
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1293:52:1293:55|Removing redundant assignment.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":92:7:92:18|Synthesizing module PCSDrsl_core in library work.
+
+       pnum_channels=32'b00000000000000000000000000000001
+       pprotocol=24'b010001110100001001000101
+       pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
+       pport_tx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100
+       pwait_tx_rdy=32'b00000000000000000000101110111000
+       pport_rx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100
+       pwait_rx_rdy=32'b00000000000000000000101110111000
+       wa_num_cycles=32'b00000000000000000000010000000000
+       dac_num_cycles=32'b00000000000000000000000000000011
+       lreset_pwidth=32'b00000000000000000000000000000011
+       lwait_b4_trst=32'b00000000000010111110101111000010
+       lwait_b4_trst_s=32'b00000000000000000000001100001101
+       lplol_cnt_width=32'b00000000000000000000000000010100
+       lwait_after_plol0=32'b00000000000000000000000000000100
+       lwait_b4_rrst=32'b00000000000000101100000000000000
+       lrrst_wait_width=32'b00000000000000000000000000010100
+       lwait_after_rrst=32'b00000000000011000011010100000000
+       lwait_b4_rrst_s=32'b00000000000000000000000111001100
+       lrlol_cnt_width=32'b00000000000000000000000000010011
+       lwait_after_lols=32'b00000000000000001100010000000000
+       lwait_after_lols_s=32'b00000000000000000000000010010110
+       llols_cnt_width=32'b00000000000000000000000000010010
+       lrdb_max=32'b00000000000000000000000000001111
+       ltxr_wait_width=32'b00000000000000000000000000001100
+       lrxr_wait_width=32'b00000000000000000000000000001100
+   Generated name = PCSDrsl_core_Z2_layer1
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":274:33:274:48|Removing wire dual_or_serd_rst, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":275:33:275:46|Removing wire tx_any_pcs_rst, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":276:33:276:42|Removing wire tx_any_rst, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":277:33:277:41|Object txsr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":278:33:278:42|Object txdpr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":279:33:279:41|Object txpr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":280:33:280:41|Object txr_wt_en is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":281:33:281:42|Object txr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":282:33:282:41|Removing wire txr_wt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":283:33:283:43|Object ruo_tx_rdyr is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":356:33:356:41|Object rxsr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":357:33:357:41|Object rxpr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":358:33:358:42|Object rxsdr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":359:33:359:42|Object rxdpr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":360:33:360:48|Removing wire rxsdr_or_sr_appd, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":361:33:361:49|Removing wire dual_or_rserd_rst, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":362:33:362:46|Removing wire rx_any_pcs_rst, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":363:33:363:42|Removing wire rx_any_rst, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":364:33:364:41|Object rxr_wt_en is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":365:33:365:42|Object rxr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":366:33:366:41|Removing wire rxr_wt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":367:33:367:43|Object ruo_rx_rdyr is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":507:10:507:10|Object m is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":880:10:880:10|Object l is declared but not assigned. Either assign a value or remove the declaration.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers.
+@N: CL201 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state.
+Extracted state machine for register sll_state
+State machine has 4 reachable states with original encodings of:
+   00
+   01
+   10
+   11
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 76MB)
+
+
+Process completed successfully.
+# Mon Apr 29 14:56:31 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+
+=======================================================================================
+For a summary of linker messages for components that did not bind, please see log file:
+@L: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.linkerlog
+=======================================================================================
+
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon Apr 29 14:56:31 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon Apr 29 14:56:31 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Mon Apr 29 14:56:32 2019
+
+###########################################################]
+Pre-mapping Report
+
+# Mon Apr 29 14:56:33 2019
+
+Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc
+@L: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD_scck.rpt 
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD_scck.rpt" file 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)
+
+@N: BN362 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.PCSDsll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.PCSDsll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.PCSDsll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.PCSDsll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.PCSDsll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.PCSDsll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances.
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist PCSD
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+
+Clock Summary
+******************
+
+          Start                           Requested     Requested     Clock        Clock                   Clock
+Level     Clock                           Frequency     Period        Type         Group                   Load 
+----------------------------------------------------------------------------------------------------------------
+0 -       System                          100.0 MHz     10.000        system       system_clkgroup         0    
+                                                                                                                
+0 -       PCSD|pll_refclki                100.0 MHz     10.000        inferred     Inferred_clkgroup_0     76   
+                                                                                                                
+0 -       PCSD|rxrefclk                   100.0 MHz     10.000        inferred     Inferred_clkgroup_1     59   
+                                                                                                                
+0 -       PCSD|tx_pclk_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_2     53   
+================================================================================================================
+
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1988:0:1988:5|Found inferred clock PCSD|pll_refclki which controls 76 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Found inferred clock PCSD|rxrefclk which controls 59 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1988:0:1988:5|Found inferred clock PCSD|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[3:0] (in view: work.PCSDsll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   10 -> 10
+   11 -> 11
+@N: MO225 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.PCSDsll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 144MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Mon Apr 29 14:56:33 2019
+
+###########################################################]
+Map & Optimize Report
+
+# Mon Apr 29 14:56:33 2019
+
+Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB)
+
+Encoding state machine sll_state[3:0] (in view: work.PCSDsll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   10 -> 10
+   11 -> 11
+@N: MO225 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.PCSDsll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1350:0:1350:5|Found counter in view:work.PCSDsll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1304:0:1304:5|Found counter in view:work.PCSDsll_core_Z1_layer1(verilog) instance rcount[15:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1759:0:1759:5|Found counter in view:work.PCSDsll_core_Z1_layer1(verilog) instance pcount[21:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":412:3:412:8|Found counter in view:work.PCSDrsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":778:3:778:8|Found counter in view:work.PCSDrsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":680:3:680:8|Found counter in view:work.PCSDrsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] 
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 146MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.PCSD(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.PCSD(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.PCSD(v1)).
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+   1           0h:00m:01s                   5.36ns              118 /       186
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.PCSD(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.PCSD(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.PCSD(v1)).
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+3 non-gated/non-generated clock tree(s) driving 186 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+=================================== Non-Gated/Non-Generated Clocks ====================================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                
+-------------------------------------------------------------------------------------------------------
+@K:CKID0001       pll_refclki         port                   74         rsl_inst.genblk1\.pll_lol_p1   
+@K:CKID0002       rxrefclk            port                   59         rsl_inst.genblk2\.rlol1_cnt[18]
+@K:CKID0003       DCU0_inst           DCUA                   53         sll_inst.pcount[21]            
+=======================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 109MB peak: 146MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.edn
+M-2017.03L-SP1-1
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 148MB peak: 150MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 148MB peak: 150MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 148MB peak: 150MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 149MB peak: 150MB)
+
+@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":150:4:150:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+@W: MT420 |Found inferred clock PCSD|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"
+@W: MT420 |Found inferred clock PCSD|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"
+@W: MT420 |Found inferred clock PCSD|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk"
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Mon Apr 29 14:56:37 2019
+#
+
+
+Top view:               PCSD
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 4.079
+
+                                Requested     Estimated       Requested     Estimated               Clock        Clock              
+Starting Clock                  Frequency     Frequency       Period        Period        Slack     Type         Group              
+------------------------------------------------------------------------------------------------------------------------------------
+PCSD|pll_refclki                100.0 MHz     168.9 MHz       10.000        5.921         4.079     inferred     Inferred_clkgroup_0
+PCSD|rxrefclk                   100.0 MHz     170.5 MHz       10.000        5.864         4.136     inferred     Inferred_clkgroup_1
+PCSD|tx_pclk_inferred_clock     100.0 MHz     237.5 MHz       10.000        4.211         5.789     inferred     Inferred_clkgroup_2
+System                          100.0 MHz     18518.5 MHz     10.000        0.054         9.946     system       system_clkgroup    
+====================================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                                                    |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+------------------------------------------------------------------------------------------------------------------------------------------------
+Starting                     Ending                       |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
+------------------------------------------------------------------------------------------------------------------------------------------------
+System                       PCSD|rxrefclk                |  10.000      9.946  |  No paths    -      |  No paths    -      |  No paths    -    
+PCSD|pll_refclki             System                       |  10.000      8.385  |  No paths    -      |  No paths    -      |  No paths    -    
+PCSD|pll_refclki             PCSD|pll_refclki             |  10.000      4.079  |  No paths    -      |  No paths    -      |  No paths    -    
+PCSD|pll_refclki             PCSD|tx_pclk_inferred_clock  |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
+PCSD|rxrefclk                System                       |  10.000      8.283  |  No paths    -      |  No paths    -      |  No paths    -    
+PCSD|rxrefclk                PCSD|rxrefclk                |  10.000      4.136  |  No paths    -      |  No paths    -      |  No paths    -    
+PCSD|tx_pclk_inferred_clock  PCSD|pll_refclki             |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
+PCSD|tx_pclk_inferred_clock  PCSD|tx_pclk_inferred_clock  |  10.000      5.789  |  No paths    -      |  No paths    -      |  No paths    -    
+================================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: PCSD|pll_refclki
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                   Starting                                                  Arrival          
+Instance                           Reference            Type        Pin     Net              Time        Slack
+                                   Clock                                                                      
+--------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[1]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[1]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[6]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[6]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[7]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[7]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[12]     PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[12]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[2]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[2]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[3]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[3]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[4]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[4]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[5]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[5]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[8]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[8]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[9]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[9]      0.907       4.684
+==============================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                   Starting                                                    Required          
+Instance                           Reference            Type        Pin     Net                Time         Slack
+                                   Clock                                                                         
+-----------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[19]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[19]     9.946        4.079
+rsl_inst.genblk1\.plol_cnt[17]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[17]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[18]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[18]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[15]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[15]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[16]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[16]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[13]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[13]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[14]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[14]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[11]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[11]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[12]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[12]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[9]      PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[9]      9.946        4.383
+=================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.867
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     4.079
+
+    Number of logic level(s):                15
+    Starting point:                          rsl_inst.genblk1\.plol_cnt[1] / Q
+    Ending point:                            rsl_inst.genblk1\.plol_cnt[19] / D
+    The start point is clocked by            PCSD|pll_refclki [rising] on pin CK
+    The end   point is clocked by            PCSD|pll_refclki [rising] on pin CK
+
+Instance / Net                                        Pin      Pin               Arrival     No. of    
+Name                                     Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[1]            FD1S3DX      Q        Out     0.907     0.907       -         
+plol_cnt[1]                              Net          -        -       -         -           2         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     Z        Out     0.606     1.513       -         
+un1_plol_cnt_tc_10                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     Z        Out     0.606     2.119       -         
+un1_plol_cnt_tc_14                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     Z        Out     0.762     2.881       -         
+un1_plol_cnt_tc                          Net          -        -       -         -           5         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     B        In      0.000     2.881       -         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     Z        Out     0.840     3.721       -         
+plol_cnt                                 Net          -        -       -         -           21        
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.721       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.621       -         
+plol_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.621       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.682       -         
+plol_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.682       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.743       -         
+plol_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.743       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.804       -         
+plol_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.804       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.865       -         
+plol_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.865       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.926       -         
+plol_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.926       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.987       -         
+plol_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.987       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.048       -         
+plol_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.048       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.109       -         
+plol_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.109       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        COUT     Out     0.061     5.170       -         
+plol_cnt_cry[18]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        CIN      In      0.000     5.170       -         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        S0       Out     0.698     5.867       -         
+plol_cnt_s[19]                           Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt[19]           FD1S3DX      D        In      0.000     5.867       -         
+=======================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: PCSD|rxrefclk
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                     Starting                                                 Arrival          
+Instance                             Reference         Type        Pin     Net                Time        Slack
+                                     Clock                                                                     
+---------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[14]      PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[14]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[15]      PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[15]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[16]      PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[16]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[17]      PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[17]      0.907       4.136
+rsl_inst.genblk2\.rlols0_cnt[7]      PCSD|rxrefclk     FD1P3DX     Q       rlols0_cnt[7]      0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[8]      PCSD|rxrefclk     FD1P3DX     Q       rlols0_cnt[8]      0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[9]      PCSD|rxrefclk     FD1P3DX     Q       rlols0_cnt[9]      0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[10]     PCSD|rxrefclk     FD1P3DX     Q       rlols0_cnt[10]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[11]     PCSD|rxrefclk     FD1P3DX     Q       rlols0_cnt[11]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[14]     PCSD|rxrefclk     FD1P3DX     Q       rlols0_cnt[14]     0.907       4.170
+===============================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                     Starting                                                   Required          
+Instance                             Reference         Type        Pin     Net                  Time         Slack
+                                     Clock                                                                        
+------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[17]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[17]      9.946        4.136
+rsl_inst.genblk2\.rlol1_cnt[18]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[18]      9.946        4.136
+rsl_inst.genblk2\.rlols0_cnt[17]     PCSD|rxrefclk     FD1P3DX     D       rlols0_cnt_s[17]     9.946        4.170
+rsl_inst.genblk2\.rlol1_cnt[15]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[15]      9.946        4.197
+rsl_inst.genblk2\.rlol1_cnt[16]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[16]      9.946        4.197
+rsl_inst.genblk2\.rlols0_cnt[15]     PCSD|rxrefclk     FD1P3DX     D       rlols0_cnt_s[15]     9.946        4.231
+rsl_inst.genblk2\.rlols0_cnt[16]     PCSD|rxrefclk     FD1P3DX     D       rlols0_cnt_s[16]     9.946        4.231
+rsl_inst.genblk2\.rlol1_cnt[13]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[13]      9.946        4.258
+rsl_inst.genblk2\.rlol1_cnt[14]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[14]      9.946        4.258
+rsl_inst.genblk2\.rlols0_cnt[13]     PCSD|rxrefclk     FD1P3DX     D       rlols0_cnt_s[13]     9.946        4.292
+==================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.809
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.136
+
+    Number of logic level(s):                14
+    Starting point:                          rsl_inst.genblk2\.rlol1_cnt[14] / Q
+    Ending point:                            rsl_inst.genblk2\.rlol1_cnt[18] / D
+    The start point is clocked by            PCSD|rxrefclk [rising] on pin CK
+    The end   point is clocked by            PCSD|rxrefclk [rising] on pin CK
+
+Instance / Net                                         Pin      Pin               Arrival     No. of    
+Name                                      Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[14]           FD1P3DX      Q        Out     0.907     0.907       -         
+rlol1_cnt[14]                             Net          -        -       -         -           2         
+rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     Z        Out     0.606     1.513       -         
+rlol1_cnt_tc_1_10                         Net          -        -       -         -           1         
+rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     Z        Out     0.606     2.119       -         
+rlol1_cnt_tc_1_14                         Net          -        -       -         -           1         
+rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     Z        Out     0.768     2.887       -         
+rlol1_cnt_tc_1                            Net          -        -       -         -           6         
+rsl_inst.genblk2\.rlos_db_p1_RNIS0OP      ORCALUT4     A        In      0.000     2.887       -         
+rsl_inst.genblk2\.rlos_db_p1_RNIS0OP      ORCALUT4     Z        Out     0.837     3.724       -         
+rlol1_cnt                                 Net          -        -       -         -           20        
+rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.724       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.624       -         
+rlol1_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.624       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.685       -         
+rlol1_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.685       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.746       -         
+rlol1_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.746       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.807       -         
+rlol1_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.807       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.868       -         
+rlol1_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.868       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.929       -         
+rlol1_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.929       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.990       -         
+rlol1_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.990       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.051       -         
+rlol1_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.051       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.112       -         
+rlol1_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.112       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        S1       Out     0.698     5.809       -         
+rlol1_cnt_s[18]                           Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt[18]           FD1P3DX      D        In      0.000     5.809       -         
+========================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: PCSD|tx_pclk_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                            Starting                                                             Arrival          
+Instance                    Reference                       Type        Pin     Net              Time        Slack
+                            Clock                                                                                 
+------------------------------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1       PCSD|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p1     1.098       5.789
+sll_inst.ppul_sync_p2       PCSD|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p2     1.098       5.789
+sll_inst.pcount_diff[0]     PCSD|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_0      0.985       6.147
+sll_inst.pcount[0]          PCSD|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[0]        0.955       6.178
+sll_inst.pcount_diff[1]     PCSD|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_1      0.955       6.239
+sll_inst.pcount_diff[2]     PCSD|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_2      0.955       6.239
+sll_inst.pcount[1]          PCSD|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[1]        0.907       6.287
+sll_inst.pcount[2]          PCSD|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[2]        0.907       6.287
+sll_inst.pcount_diff[3]     PCSD|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_3      0.955       6.300
+sll_inst.pcount_diff[4]     PCSD|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_4      0.955       6.300
+==================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                             Starting                                                                            Required          
+Instance                     Reference                       Type        Pin     Net                             Time         Slack
+                             Clock                                                                                                 
+-----------------------------------------------------------------------------------------------------------------------------------
+sll_inst.pcount[21]          PCSD|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[21]                    9.946        5.789
+sll_inst.pcount[19]          PCSD|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[19]                    9.946        5.850
+sll_inst.pcount[20]          PCSD|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[20]                    9.946        5.850
+sll_inst.pcount[17]          PCSD|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[17]                    9.946        5.911
+sll_inst.pcount[18]          PCSD|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[18]                    9.946        5.911
+sll_inst.pcount[15]          PCSD|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[15]                    9.946        5.972
+sll_inst.pcount[16]          PCSD|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[16]                    9.946        5.972
+sll_inst.pcount[13]          PCSD|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[13]                    9.946        6.033
+sll_inst.pcount[14]          PCSD|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[14]                    9.946        6.033
+sll_inst.pcount_diff[21]     PCSD|tx_pclk_inferred_clock     FD1P3DX     D       un1_pcount_diff_1_s_21_0_S0     9.946        6.034
+===================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      4.157
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 5.789
+
+    Number of logic level(s):                13
+    Starting point:                          sll_inst.ppul_sync_p1 / Q
+    Ending point:                            sll_inst.pcount[21] / D
+    The start point is clocked by            PCSD|tx_pclk_inferred_clock [rising] on pin CK
+    The end   point is clocked by            PCSD|tx_pclk_inferred_clock [rising] on pin CK
+
+Instance / Net                             Pin      Pin               Arrival     No. of    
+Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1         FD1S3DX      Q        Out     1.098     1.098       -         
+ppul_sync_p1                  Net          -        -       -         -           25        
+sll_inst.pcount10_0_o3        ORCALUT4     A        In      0.000     1.098       -         
+sll_inst.pcount10_0_o3        ORCALUT4     Z        Out     0.851     1.950       -         
+N_8                           Net          -        -       -         -           25        
+sll_inst.pcount_cry_0[0]      CCU2C        A1       In      0.000     1.950       -         
+sll_inst.pcount_cry_0[0]      CCU2C        COUT     Out     0.900     2.850       -         
+pcount_cry[0]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[1]      CCU2C        CIN      In      0.000     2.850       -         
+sll_inst.pcount_cry_0[1]      CCU2C        COUT     Out     0.061     2.911       -         
+pcount_cry[2]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[3]      CCU2C        CIN      In      0.000     2.911       -         
+sll_inst.pcount_cry_0[3]      CCU2C        COUT     Out     0.061     2.972       -         
+pcount_cry[4]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[5]      CCU2C        CIN      In      0.000     2.972       -         
+sll_inst.pcount_cry_0[5]      CCU2C        COUT     Out     0.061     3.033       -         
+pcount_cry[6]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[7]      CCU2C        CIN      In      0.000     3.033       -         
+sll_inst.pcount_cry_0[7]      CCU2C        COUT     Out     0.061     3.094       -         
+pcount_cry[8]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[9]      CCU2C        CIN      In      0.000     3.094       -         
+sll_inst.pcount_cry_0[9]      CCU2C        COUT     Out     0.061     3.155       -         
+pcount_cry[10]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[11]     CCU2C        CIN      In      0.000     3.155       -         
+sll_inst.pcount_cry_0[11]     CCU2C        COUT     Out     0.061     3.216       -         
+pcount_cry[12]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[13]     CCU2C        CIN      In      0.000     3.216       -         
+sll_inst.pcount_cry_0[13]     CCU2C        COUT     Out     0.061     3.277       -         
+pcount_cry[14]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[15]     CCU2C        CIN      In      0.000     3.277       -         
+sll_inst.pcount_cry_0[15]     CCU2C        COUT     Out     0.061     3.338       -         
+pcount_cry[16]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[17]     CCU2C        CIN      In      0.000     3.338       -         
+sll_inst.pcount_cry_0[17]     CCU2C        COUT     Out     0.061     3.399       -         
+pcount_cry[18]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[19]     CCU2C        CIN      In      0.000     3.399       -         
+sll_inst.pcount_cry_0[19]     CCU2C        COUT     Out     0.061     3.460       -         
+pcount_cry[20]                Net          -        -       -         -           1         
+sll_inst.pcount_s_0[21]       CCU2C        CIN      In      0.000     3.460       -         
+sll_inst.pcount_s_0[21]       CCU2C        S0       Out     0.698     4.157       -         
+pcount_s[21]                  Net          -        -       -         -           1         
+sll_inst.pcount[21]           FD1S3DX      D        In      0.000     4.157       -         
+============================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                                 Arrival          
+Instance      Reference     Type     Pin              Net              Time        Slack
+              Clock                                                                     
+----------------------------------------------------------------------------------------
+DCU0_inst     System        DCUA     CH0_FFS_RLOL     rx_cdr_lol_s     0.000       9.946
+DCU0_inst     System        DCUA     CH0_FFS_RLOS     rx_los_low_s     0.000       9.946
+========================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                              Starting                                           Required          
+Instance                      Reference     Type        Pin     Net              Time         Slack
+                              Clock                                                                
+---------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol_p1     System        FD1S3DX     D       rx_cdr_lol_s     9.946        9.946
+rsl_inst.genblk2\.rlos_p1     System        FD1S3DX     D       rx_los_low_s     9.946        9.946
+===================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      0.000
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 9.946
+
+    Number of logic level(s):                0
+    Starting point:                          DCU0_inst / CH0_FFS_RLOL
+    Ending point:                            rsl_inst.genblk2\.rlol_p1 / D
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            PCSD|rxrefclk [rising] on pin CK
+
+Instance / Net                            Pin              Pin               Arrival     No. of    
+Name                          Type        Name             Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------------------
+DCU0_inst                     DCUA        CH0_FFS_RLOL     Out     0.000     0.000       -         
+rx_cdr_lol_s                  Net         -                -       -         -           2         
+rsl_inst.genblk2\.rlol_p1     FD1S3DX     D                In      0.000     0.000       -         
+===================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 149MB peak: 150MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 149MB peak: 150MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 186 of 24288 (1%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+CCU2C:          99
+DCUA:           1
+FD1P3BX:        20
+FD1P3DX:        60
+FD1S3BX:        10
+FD1S3DX:        96
+GSR:            1
+INV:            3
+ORCALUT4:       116
+PFUMX:          2
+PUR:            1
+VHI:            6
+VLO:            6
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 34MB peak: 150MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Mon Apr 29 14:56:37 2019
+
+###########################################################]

diff --git a/gbe/cores/sgmii/PCSD/syn_results/dm/layer0.xdm b/gbe/cores/sgmii/PCSD/syn_results/dm/layer0.xdm
new file mode 100644 (file)
index 0000000..b88dcd9
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/dm/layer0.xdm
@@ -0,0 +1,513 @@
+%%% protect protected_file
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diff --git a/gbe/cores/sgmii/PCSD/syn_results/run_options.txt b/gbe/cores/sgmii/PCSD/syn_results/run_options.txt
new file mode 100644 (file)
index 0000000..9fc0ce0
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/run_options.txt
@@ -0,0 +1,76 @@
+#--  Synopsys, Inc.
+#--  Version M-2017.03L-SP1-1
+#--  Project file /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/run_options.txt
+#--  Written on Tue Apr 30 12:09:44 2019
+
+
+#project files
+add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd"
+add_file -verilog "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v"
+add_file -fpga_constraint "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc"
+
+
+
+#implementation: "syn_results"
+impl -add syn_results -type fpga
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+
+#device options
+set_option -technology ecp5um
+set_option -part LFE5UM_25F
+set_option -package MG285C
+set_option -speed_grade -6
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -top_module "PCSD"
+
+# hdl_compiler_options
+set_option -distributed_compile 0
+
+# mapper_without_write_options
+set_option -frequency 100
+set_option -srs_instrumentation 1
+
+# mapper_options
+set_option -write_verilog 1
+set_option -write_vhdl 1
+
+# Lattice XP
+set_option -maxfan 50
+set_option -disable_io_insertion 1
+set_option -retiming 0
+set_option -pipe 0
+set_option -forcegsr false
+set_option -fix_gated_and_generated_clocks 1
+set_option -rw_check_on_ram 1
+set_option -update_models_cp 0
+set_option -syn_edif_array_rename 1
+set_option -Write_declared_clocks_only 1
+
+# NFilter
+set_option -no_sequential_opt 0
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "./PCSD.edn"
+
+#set log file 
+set_option log_file "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.srf" 
+impl -active "syn_results"

diff --git a/gbe/cores/sgmii/PCSD/syn_results/scemi_cfg.txt b/gbe/cores/sgmii/PCSD/syn_results/scemi_cfg.txt
new file mode 100644 (file)
index 0000000..868d437
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/scemi_cfg.txt
@@ -0,0 +1,3 @@
+## UMR3 MESSAGE PORT CONFIGURATION FILE
+## ************************************
+XTOR_DPI_MSG_PORT_UMR_ADDR_VERSION=0

diff --git a/gbe/cores/sgmii/PCSD/syn_results/scratchproject.prs b/gbe/cores/sgmii/PCSD/syn_results/scratchproject.prs
new file mode 100644 (file)
index 0000000..1a2e57f
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/scratchproject.prs
@@ -0,0 +1,74 @@
+#--  Synopsys, Inc.
+#--  Version M-2017.03L-SP1-1
+#--  Project file /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/scratchproject.prs
+
+#project files
+add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd"
+add_file -verilog "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v"
+add_file -fpga_constraint "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc"
+
+
+
+#implementation: "syn_results"
+impl -add /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results -type fpga
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+
+#device options
+set_option -technology ecp5um
+set_option -part LFE5UM_25F
+set_option -package MG285C
+set_option -speed_grade -6
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -top_module "PCSD"
+
+# hdl_compiler_options
+set_option -distributed_compile 0
+
+# mapper_without_write_options
+set_option -frequency 100
+set_option -srs_instrumentation 1
+
+# mapper_options
+set_option -write_verilog 1
+set_option -write_vhdl 1
+
+# Lattice XP
+set_option -maxfan 50
+set_option -disable_io_insertion 1
+set_option -retiming 0
+set_option -pipe 0
+set_option -forcegsr false
+set_option -fix_gated_and_generated_clocks 1
+set_option -rw_check_on_ram 1
+set_option -update_models_cp 0
+set_option -syn_edif_array_rename 1
+set_option -Write_declared_clocks_only 1
+
+# NFilter
+set_option -no_sequential_opt 0
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.edn"
+
+#set log file 
+set_option log_file "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.srf" 
+impl -active "syn_results"

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_compiler.srr b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_compiler.srr
new file mode 100644 (file)
index 0000000..cd2e67c
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_compiler.srr
@@ -0,0 +1,201 @@
+Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Top entity is set to PCSD.
+VHDL syntax check successful!
+File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd changed - recompiling
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 72MB)
+
+
+Process completed successfully.
+# Tue Apr 30 12:09:44 2019
+
+###########################################################]
+Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v" (library work)
+Verilog syntax check successful!
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Tue Apr 30 12:09:45 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Top entity is set to PCSD.
+File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd changed - recompiling
+File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling
+VHDL syntax check successful!
+File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd changed - recompiling
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Synthesizing work.pcsd.v1.
+Post processing for work.pcsd.v1
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB)
+
+
+Process completed successfully.
+# Tue Apr 30 12:09:45 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v" (library work)
+Verilog syntax check successful!
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":92:7:92:18|Synthesizing module PCSDrsl_core in library work.
+
+       pnum_channels=32'b00000000000000000000000000000001
+       pprotocol=24'b010001110100001001000101
+       pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
+       pport_tx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100
+       pwait_tx_rdy=32'b00000000000000000000101110111000
+       pport_rx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100
+       pwait_rx_rdy=32'b00000000000000000000101110111000
+       wa_num_cycles=32'b00000000000000000000010000000000
+       dac_num_cycles=32'b00000000000000000000000000000011
+       lreset_pwidth=32'b00000000000000000000000000000011
+       lwait_b4_trst=32'b00000000000010111110101111000010
+       lwait_b4_trst_s=32'b00000000000000000000001100001101
+       lplol_cnt_width=32'b00000000000000000000000000010100
+       lwait_after_plol0=32'b00000000000000000000000000000100
+       lwait_b4_rrst=32'b00000000000000101100000000000000
+       lrrst_wait_width=32'b00000000000000000000000000010100
+       lwait_after_rrst=32'b00000000000011000011010100000000
+       lwait_b4_rrst_s=32'b00000000000000000000000111001100
+       lrlol_cnt_width=32'b00000000000000000000000000010011
+       lwait_after_lols=32'b00000000000000001100010000000000
+       lwait_after_lols_s=32'b00000000000000000000000010010110
+       llols_cnt_width=32'b00000000000000000000000000010010
+       lrdb_max=32'b00000000000000000000000000001111
+       ltxr_wait_width=32'b00000000000000000000000000001100
+       lrxr_wait_width=32'b00000000000000000000000000001100
+   Generated name = PCSDrsl_core_Z1_layer1
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":274:33:274:48|Removing wire dual_or_serd_rst, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":275:33:275:46|Removing wire tx_any_pcs_rst, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":276:33:276:42|Removing wire tx_any_rst, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":277:33:277:41|Object txsr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":278:33:278:42|Object txdpr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":279:33:279:41|Object txpr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":280:33:280:41|Object txr_wt_en is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":281:33:281:42|Object txr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":282:33:282:41|Removing wire txr_wt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":283:33:283:43|Object ruo_tx_rdyr is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":356:33:356:41|Object rxsr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":357:33:357:41|Object rxpr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":358:33:358:42|Object rxsdr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":359:33:359:42|Object rxdpr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":360:33:360:48|Removing wire rxsdr_or_sr_appd, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":361:33:361:49|Removing wire dual_or_rserd_rst, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":362:33:362:46|Removing wire rx_any_pcs_rst, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":363:33:363:42|Removing wire rx_any_rst, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":364:33:364:41|Object rxr_wt_en is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":365:33:365:42|Object rxr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":366:33:366:41|Removing wire rxr_wt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":367:33:367:43|Object ruo_rx_rdyr is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":507:10:507:10|Object m is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":880:10:880:10|Object l is declared but not assigned. Either assign a value or remove the declaration.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 75MB)
+
+
+Process completed successfully.
+# Tue Apr 30 12:09:45 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/layer0.srs changed - recompiling
+File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/layer1.srs changed - recompiling
+
+=======================================================================================
+For a summary of linker messages for components that did not bind, please see log file:
+@L: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.linkerlog
+=======================================================================================
+
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Tue Apr 30 12:09:46 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Tue Apr 30 12:09:46 2019
+
+###########################################################]

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_compiler.srr.db b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_compiler.srr.db
new file mode 100644 (file)
index 0000000..64aab84
Binary files /dev/null and b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_compiler.srr.db differ

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_compiler.srr.rptmap b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_compiler.srr.rptmap
new file mode 100644 (file)
index 0000000..0168f12
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_compiler.srr.rptmap
@@ -0,0 +1 @@
+./synlog/PCSD_compiler.srr,PCSD_compiler.srr,Compile Log

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_fpga_mapper.srr b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_fpga_mapper.srr
new file mode 100644 (file)
index 0000000..da6761e
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_fpga_mapper.srr
@@ -0,0 +1,537 @@
+# Tue Apr 30 12:09:48 2019
+
+Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":412:3:412:8|Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk1\.plol_cnt[19:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":778:3:778:8|Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":680:3:680:8|Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] 
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+   1           0h:00m:00s                   5.36ns               63 /        92
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+2 non-gated/non-generated clock tree(s) driving 92 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+=================================== Non-Gated/Non-Generated Clocks ====================================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                
+-------------------------------------------------------------------------------------------------------
+@K:CKID0001       rxrefclk            port                   59         rsl_inst.genblk2\.rlol1_cnt[18]
+@K:CKID0002       pll_refclki         port                   33         rsl_inst.genblk1\.pll_lol_p1   
+=======================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 107MB peak: 144MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.edn
+M-2017.03L-SP1-1
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 148MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 148MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB)
+
+@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":118:4:118:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+@W: MT420 |Found inferred clock PCSD|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"
+@W: MT420 |Found inferred clock PCSD|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Tue Apr 30 12:09:50 2019
+#
+
+
+Top view:               PCSD
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 4.079
+
+@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
+                     Requested     Estimated       Requested     Estimated               Clock        Clock              
+Starting Clock       Frequency     Frequency       Period        Period        Slack     Type         Group              
+-------------------------------------------------------------------------------------------------------------------------
+PCSD|pll_refclki     100.0 MHz     168.9 MHz       10.000        5.921         4.079     inferred     Inferred_clkgroup_0
+PCSD|rxrefclk        100.0 MHz     170.5 MHz       10.000        5.864         4.136     inferred     Inferred_clkgroup_1
+System               100.0 MHz     18518.5 MHz     10.000        0.054         9.946     system       system_clkgroup    
+=========================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                              |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+---------------------------------------------------------------------------------------------------------------------------
+Starting          Ending            |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
+---------------------------------------------------------------------------------------------------------------------------
+System            System            |  10.000      10.000  |  No paths    -      |  No paths    -      |  No paths    -    
+System            PCSD|rxrefclk     |  10.000      9.946   |  No paths    -      |  No paths    -      |  No paths    -    
+PCSD|pll_refclki  System            |  10.000      8.385   |  No paths    -      |  No paths    -      |  No paths    -    
+PCSD|pll_refclki  PCSD|pll_refclki  |  10.000      4.079   |  No paths    -      |  No paths    -      |  No paths    -    
+PCSD|rxrefclk     System            |  10.000      8.283   |  No paths    -      |  No paths    -      |  No paths    -    
+PCSD|rxrefclk     PCSD|rxrefclk     |  10.000      4.136   |  No paths    -      |  No paths    -      |  No paths    -    
+===========================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: PCSD|pll_refclki
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                   Starting                                                  Arrival          
+Instance                           Reference            Type        Pin     Net              Time        Slack
+                                   Clock                                                                      
+--------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[1]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[1]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[6]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[6]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[7]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[7]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[12]     PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[12]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[2]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[2]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[3]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[3]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[4]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[4]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[5]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[5]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[8]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[8]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[9]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[9]      0.907       4.684
+==============================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                   Starting                                                    Required          
+Instance                           Reference            Type        Pin     Net                Time         Slack
+                                   Clock                                                                         
+-----------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[19]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[19]     9.946        4.079
+rsl_inst.genblk1\.plol_cnt[17]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[17]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[18]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[18]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[15]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[15]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[16]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[16]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[13]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[13]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[14]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[14]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[11]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[11]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[12]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[12]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[9]      PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[9]      9.946        4.383
+=================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.867
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     4.079
+
+    Number of logic level(s):                15
+    Starting point:                          rsl_inst.genblk1\.plol_cnt[1] / Q
+    Ending point:                            rsl_inst.genblk1\.plol_cnt[19] / D
+    The start point is clocked by            PCSD|pll_refclki [rising] on pin CK
+    The end   point is clocked by            PCSD|pll_refclki [rising] on pin CK
+
+Instance / Net                                        Pin      Pin               Arrival     No. of    
+Name                                     Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[1]            FD1S3DX      Q        Out     0.907     0.907       -         
+plol_cnt[1]                              Net          -        -       -         -           2         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     Z        Out     0.606     1.513       -         
+un1_plol_cnt_tc_10                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     Z        Out     0.606     2.119       -         
+un1_plol_cnt_tc_14                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     Z        Out     0.762     2.881       -         
+un1_plol_cnt_tc                          Net          -        -       -         -           5         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     B        In      0.000     2.881       -         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     Z        Out     0.840     3.721       -         
+plol_cnt                                 Net          -        -       -         -           21        
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.721       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.621       -         
+plol_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.621       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.682       -         
+plol_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.682       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.743       -         
+plol_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.743       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.804       -         
+plol_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.804       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.865       -         
+plol_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.865       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.926       -         
+plol_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.926       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.987       -         
+plol_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.987       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.048       -         
+plol_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.048       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.109       -         
+plol_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.109       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        COUT     Out     0.061     5.170       -         
+plol_cnt_cry[18]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        CIN      In      0.000     5.170       -         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        S0       Out     0.698     5.867       -         
+plol_cnt_s[19]                           Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt[19]           FD1S3DX      D        In      0.000     5.867       -         
+=======================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: PCSD|rxrefclk
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                     Starting                                                 Arrival          
+Instance                             Reference         Type        Pin     Net                Time        Slack
+                                     Clock                                                                     
+---------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[14]      PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[14]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[15]      PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[15]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[16]      PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[16]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[17]      PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[17]      0.907       4.136
+rsl_inst.genblk2\.rlols0_cnt[10]     PCSD|rxrefclk     FD1P3DX     Q       rlols0_cnt[10]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[14]     PCSD|rxrefclk     FD1P3DX     Q       rlols0_cnt[14]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[16]     PCSD|rxrefclk     FD1P3DX     Q       rlols0_cnt[16]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[17]     PCSD|rxrefclk     FD1P3DX     Q       rlols0_cnt[17]     0.907       4.170
+rsl_inst.genblk2\.rlol1_cnt[0]       PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[0]       0.907       4.742
+rsl_inst.genblk2\.rlol1_cnt[1]       PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[1]       0.907       4.742
+===============================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                     Starting                                                   Required          
+Instance                             Reference         Type        Pin     Net                  Time         Slack
+                                     Clock                                                                        
+------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[17]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[17]      9.946        4.136
+rsl_inst.genblk2\.rlol1_cnt[18]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[18]      9.946        4.136
+rsl_inst.genblk2\.rlols0_cnt[17]     PCSD|rxrefclk     FD1P3DX     D       rlols0_cnt_s[17]     9.946        4.170
+rsl_inst.genblk2\.rlol1_cnt[15]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[15]      9.946        4.197
+rsl_inst.genblk2\.rlol1_cnt[16]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[16]      9.946        4.197
+rsl_inst.genblk2\.rlols0_cnt[15]     PCSD|rxrefclk     FD1P3DX     D       rlols0_cnt_s[15]     9.946        4.231
+rsl_inst.genblk2\.rlols0_cnt[16]     PCSD|rxrefclk     FD1P3DX     D       rlols0_cnt_s[16]     9.946        4.231
+rsl_inst.genblk2\.rlol1_cnt[13]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[13]      9.946        4.258
+rsl_inst.genblk2\.rlol1_cnt[14]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[14]      9.946        4.258
+rsl_inst.genblk2\.rlols0_cnt[13]     PCSD|rxrefclk     FD1P3DX     D       rlols0_cnt_s[13]     9.946        4.292
+==================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.809
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.136
+
+    Number of logic level(s):                14
+    Starting point:                          rsl_inst.genblk2\.rlol1_cnt[14] / Q
+    Ending point:                            rsl_inst.genblk2\.rlol1_cnt[18] / D
+    The start point is clocked by            PCSD|rxrefclk [rising] on pin CK
+    The end   point is clocked by            PCSD|rxrefclk [rising] on pin CK
+
+Instance / Net                                         Pin      Pin               Arrival     No. of    
+Name                                      Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[14]           FD1P3DX      Q        Out     0.907     0.907       -         
+rlol1_cnt[14]                             Net          -        -       -         -           2         
+rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     Z        Out     0.606     1.513       -         
+rlol1_cnt_tc_1_10                         Net          -        -       -         -           1         
+rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     Z        Out     0.606     2.119       -         
+rlol1_cnt_tc_1_14                         Net          -        -       -         -           1         
+rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     Z        Out     0.768     2.887       -         
+rlol1_cnt_tc_1                            Net          -        -       -         -           6         
+rsl_inst.genblk2\.rxs_rst_RNIS0OP         ORCALUT4     A        In      0.000     2.887       -         
+rsl_inst.genblk2\.rxs_rst_RNIS0OP         ORCALUT4     Z        Out     0.837     3.724       -         
+rlol1_cnt                                 Net          -        -       -         -           20        
+rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.724       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.624       -         
+rlol1_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.624       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.685       -         
+rlol1_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.685       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.746       -         
+rlol1_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.746       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.807       -         
+rlol1_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.807       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.868       -         
+rlol1_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.868       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.929       -         
+rlol1_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.929       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.990       -         
+rlol1_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.990       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.051       -         
+rlol1_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.051       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.112       -         
+rlol1_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.112       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        S1       Out     0.698     5.809       -         
+rlol1_cnt_s[18]                           Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt[18]           FD1P3DX      D        In      0.000     5.809       -         
+========================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                                   Arrival           
+Instance      Reference     Type     Pin                Net              Time        Slack 
+              Clock                                                                        
+-------------------------------------------------------------------------------------------
+DCU0_inst     System        DCUA     CH0_FFS_RLOL       rx_cdr_lol_s     0.000       9.946 
+DCU0_inst     System        DCUA     CH0_FFS_RLOS       rx_los_low_s     0.000       9.946 
+DCU0_inst     System        DCUA     CH0_FF_TX_PCLK     tx_pclk          0.000       10.000
+===========================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                              Starting                                                       Required           
+Instance                      Reference     Type        Pin                 Net              Time         Slack 
+                              Clock                                                                             
+----------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol_p1     System        FD1S3DX     D                   rx_cdr_lol_s     9.946        9.946 
+rsl_inst.genblk2\.rlos_p1     System        FD1S3DX     D                   rx_los_low_s     9.946        9.946 
+DCU0_inst                     System        DCUA        CH0_FF_EBRD_CLK     tx_pclk          10.000       10.000
+DCU0_inst                     System        DCUA        CH0_FF_RXI_CLK      tx_pclk          10.000       10.000
+================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      0.000
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 9.946
+
+    Number of logic level(s):                0
+    Starting point:                          DCU0_inst / CH0_FFS_RLOL
+    Ending point:                            rsl_inst.genblk2\.rlol_p1 / D
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            PCSD|rxrefclk [rising] on pin CK
+
+Instance / Net                            Pin              Pin               Arrival     No. of    
+Name                          Type        Name             Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------------------
+DCU0_inst                     DCUA        CH0_FFS_RLOL     Out     0.000     0.000       -         
+rx_cdr_lol_s                  Net         -                -       -         -           2         
+rsl_inst.genblk2\.rlol_p1     FD1S3DX     D                In      0.000     0.000       -         
+===================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 92 of 24288 (0%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+CCU2C:          37
+DCUA:           1
+FD1P3BX:        4
+FD1P3DX:        42
+FD1S3BX:        10
+FD1S3DX:        36
+GSR:            1
+ORCALUT4:       63
+PFUMX:          2
+PUR:            1
+VHI:            2
+VLO:            2
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 32MB peak: 148MB)
+
+Process took 0h:00m:02s realtime, 0h:00m:02s cputime
+# Tue Apr 30 12:09:51 2019
+
+###########################################################]

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_fpga_mapper.srr.db b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_fpga_mapper.srr.db
new file mode 100644 (file)
index 0000000..b2fe294
Binary files /dev/null and b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_fpga_mapper.srr.db differ

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_fpga_mapper.szr b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_fpga_mapper.szr
new file mode 100644 (file)
index 0000000..77cff04
Binary files /dev/null and b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_fpga_mapper.szr differ

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_fpga_mapper.xck b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_fpga_mapper.xck
new file mode 100644 (file)
index 0000000..090e73d
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_fpga_mapper.xck
@@ -0,0 +1,2 @@
+CKID0001:@|S:rxrefclk@|E:rsl_inst.genblk2\.rlol1_cnt[18]@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001 
+CKID0002:@|S:pll_refclki@|E:rsl_inst.genblk1\.pll_lol_p1@|F:@syn_sample_clock_path==CKID0002@|M:ClockId0002 

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_multi_srs_gen.srr b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_multi_srs_gen.srr
new file mode 100644 (file)
index 0000000..fc78ac1
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_multi_srs_gen.srr
@@ -0,0 +1,12 @@
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Tue Apr 30 12:09:47 2019
+
+###########################################################]

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_multi_srs_gen.srr.db b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_multi_srs_gen.srr.db
new file mode 100644 (file)
index 0000000..029fa7a
Binary files /dev/null and b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_multi_srs_gen.srr.db differ

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_premap.srr b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_premap.srr
new file mode 100644 (file)
index 0000000..fe3b5ab
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_premap.srr
@@ -0,0 +1,70 @@
+# Tue Apr 30 12:09:47 2019
+
+Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc
+@L: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD_scck.rpt 
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD_scck.rpt" file 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist PCSD
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+
+Clock Summary
+******************
+
+          Start                Requested     Requested     Clock        Clock                   Clock
+Level     Clock                Frequency     Period        Type         Group                   Load 
+-----------------------------------------------------------------------------------------------------
+0 -       System               100.0 MHz     10.000        system       system_clkgroup         0    
+                                                                                                     
+0 -       PCSD|rxrefclk        100.0 MHz     10.000        inferred     Inferred_clkgroup_1     59   
+                                                                                                     
+0 -       PCSD|pll_refclki     100.0 MHz     10.000        inferred     Inferred_clkgroup_0     33   
+=====================================================================================================
+
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":412:3:412:8|Found inferred clock PCSD|pll_refclki which controls 33 sequential elements including rsl_inst.genblk1\.plol_cnt[19:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Found inferred clock PCSD|rxrefclk which controls 59 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Apr 30 12:09:48 2019
+
+###########################################################]

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_premap.srr.db b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_premap.srr.db
new file mode 100644 (file)
index 0000000..46a9c99
Binary files /dev/null and b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_premap.srr.db differ

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_premap.szr b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_premap.szr
new file mode 100644 (file)
index 0000000..a26d510
Binary files /dev/null and b/gbe/cores/sgmii/PCSD/syn_results/synlog/PCSD_premap.szr differ

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/layer0.tlg.rptmap b/gbe/cores/sgmii/PCSD/syn_results/synlog/layer0.tlg.rptmap
new file mode 100644 (file)
index 0000000..3910cac
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/layer0.tlg.rptmap
@@ -0,0 +1 @@
+./synwork/layer0.tlg,layer0.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages.

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/layer1.tlg.rptmap b/gbe/cores/sgmii/PCSD/syn_results/synlog/layer1.tlg.rptmap
new file mode 100644 (file)
index 0000000..af92e0b
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/layer1.tlg.rptmap
@@ -0,0 +1 @@
+./synwork/layer1.tlg,layer1.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages.

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/linker.rpt.rptmap b/gbe/cores/sgmii/PCSD/syn_results/synlog/linker.rpt.rptmap
new file mode 100644 (file)
index 0000000..e21637c
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/linker.rpt.rptmap
@@ -0,0 +1 @@
+./synwork/PCSD_comp.linkerlog,linker.rpt,Summary of linker messages for components that did not bind

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_notes.txt b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_notes.txt
new file mode 100644 (file)
index 0000000..64eb40e
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_notes.txt
@@ -0,0 +1,11 @@
+@N|Running in 64-bit mode
+@N|Running in 64-bit mode
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Top entity is set to PCSD.
+@N|Running in 64-bit mode
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Top entity is set to PCSD.
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Synthesizing work.pcsd.v1.
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":92:7:92:18|Synthesizing module PCSDrsl_core in library work.
+@N|Running in 64-bit mode
+

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_runstatus.xml b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_runstatus.xml
new file mode 100644 (file)
index 0000000..5ab9b80
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_runstatus.xml
@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the job information from compiler to be displayed as part of the summary report.
+*******************************************************************************************-->
+
+<job_run_status name="compiler"> 
+  <report_link name="Detailed report">
+    <data>/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/PCSD_compiler.srr</data>
+    <title>Synopsys HDL Compiler</title>
+  </report_link> 
+  <job_status>
+    <data>Completed    </data>
+  </job_status>
+<job_info> 
+                       <info name="Notes">
+  <data>10</data>
+  <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_notes.txt</data></report_link>
+  </info>
+                       <info name="Warnings">
+  <data>50</data>
+  <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_warnings.txt</data></report_link>
+  </info>
+                       <info name="Errors">
+  <data>0</data>
+  <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_errors.txt</data></report_link>
+  </info>
+                       <info name="CPU Time">
+  <data>-</data>
+  </info>
+                       <info name="Real Time">
+  <data>00h:00m:02s</data>
+  </info>
+                       <info name="Peak Memory">
+  <data>-</data>
+  </info>
+                       <info name="Date &amp;Time">
+  <data type="timestamp">1556618986</data>
+  </info>
+                       </job_info>
+</job_run_status>
\ No newline at end of file

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_warnings.txt b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_warnings.txt
new file mode 100644 (file)
index 0000000..664f602
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_compiler_warnings.txt
@@ -0,0 +1,51 @@
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":274:33:274:48|Removing wire dual_or_serd_rst, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":275:33:275:46|Removing wire tx_any_pcs_rst, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":276:33:276:42|Removing wire tx_any_rst, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":277:33:277:41|Object txsr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":278:33:278:42|Object txdpr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":279:33:279:41|Object txpr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":280:33:280:41|Object txr_wt_en is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":281:33:281:42|Object txr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":282:33:282:41|Removing wire txr_wt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":283:33:283:43|Object ruo_tx_rdyr is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":356:33:356:41|Object rxsr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":357:33:357:41|Object rxpr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":358:33:358:42|Object rxsdr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":359:33:359:42|Object rxdpr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":360:33:360:48|Removing wire rxsdr_or_sr_appd, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":361:33:361:49|Removing wire dual_or_rserd_rst, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":362:33:362:46|Removing wire rx_any_pcs_rst, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":363:33:363:42|Removing wire rx_any_rst, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":364:33:364:41|Object rxr_wt_en is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":365:33:365:42|Object rxr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":366:33:366:41|Removing wire rxr_wt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":367:33:367:43|Object ruo_rx_rdyr is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":507:10:507:10|Object m is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":880:10:880:10|Object l is declared but not assigned. Either assign a value or remove the declaration.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_area_report.xml b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_area_report.xml
new file mode 100644 (file)
index 0000000..194415f
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_area_report.xml
@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the area information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<report_table display_priority="1" name="Area Summary">
+<report_link name="Detailed report">
+<data>/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_resourceusage.rpt</data>
+<title>Resource Usage</title>
+</report_link>
+<parameter tooltip="Total Register bits used" name="Register bits">
+<data>92</data>
+</parameter>
+<parameter tooltip="Total I/O cells used" name="I/O cells">
+<data>0</data>
+</parameter>
+<parameter tcl_name="v_ram" tooltip="Total Block RAMs used" name="Block RAMs">
+<data>0</data>
+</parameter>
+<parameter tcl_name="dsp_used" tooltip="Total DSPs used" name="DSPs">
+<data>0</data>
+</parameter>
+<parameter tcl_name="total_luts" tooltip="Total ORCA LUTs used" name="ORCA LUTs">
+<data>63</data>
+</parameter>
+</report_table>

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_errors.txt b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_errors.txt
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_notes.txt b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_notes.txt
new file mode 100644 (file)
index 0000000..b4c4fcb
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_notes.txt
@@ -0,0 +1,11 @@
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":412:3:412:8|Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk1\.plol_cnt[19:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":778:3:778:8|Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":680:3:680:8|Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] 
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.edn
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_opt_report.xml b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_opt_report.xml
new file mode 100644 (file)
index 0000000..2e79d15
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_opt_report.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the optimization information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<report_table display_priority="3" name="Optimizations Summary">
+<parameter tooltip="Non-gated/non-generated clock trees / Gated/generated clock trees" name="Combined Clock Conversion">
+<data>2 / 0</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_combined_clk.rpt</data>
+<title>START OF CLOCK OPTIMIZATION REPORT</title>
+</report_link>
+</parameter>
+</report_table>

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_runstatus.xml b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_runstatus.xml
new file mode 100644 (file)
index 0000000..f5531ea
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_runstatus.xml
@@ -0,0 +1,46 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the job information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<job_run_status name="Mapper">
+<report_link name="Detailed report">
+<data>/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/PCSD_fpga_mapper.srr</data>
+<title>Synopsys Lattice Technology Mapper</title>
+</report_link>
+<job_status>
+<data>Completed</data>
+</job_status>
+<job_info>
+<info name="Notes">
+<data>11</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_notes.txt</data>
+</report_link>
+</info>
+<info name="Warnings">
+<data>3</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_warnings.txt</data>
+</report_link>
+</info>
+<info name="Errors">
+<data>0</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_errors.txt</data>
+</report_link>
+</info>
+<info name="CPU Time">
+<data>0h:00m:02s</data>
+</info>
+<info name="Real Time">
+<data>0h:00m:02s</data>
+</info>
+<info name="Peak Memory">
+<data>148MB</data>
+</info>
+<info name="Date &amp; Time">
+<data type="timestamp">1556618991</data>
+</info>
+</job_info>
+</job_run_status>

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_timing_report.xml b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_timing_report.xml
new file mode 100644 (file)
index 0000000..04932ce
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_timing_report.xml
@@ -0,0 +1,35 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+Max Top 5 critical clocks will be reported. For rest user needs to refer to Detailed report
+*******************************************************************************************-->
+<report_table display_priority="2" name="Timing Summary">
+<report_link name="Detailed report">
+<data>/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/PCSD_fpga_mapper.srr</data>
+<title>START OF TIMING REPORT</title>
+</report_link>
+<row>
+<data tcl_name="clock_name">Clock Name</data>
+<data tcl_name="req_freq">Req Freq</data>
+<data tcl_name="est_freq">Est Freq</data>
+<data tcl_name="slack">Slack</data>
+</row>
+<row>
+<data>PCSD|pll_refclki</data>
+<data>100.0 MHz</data>
+<data>168.9 MHz</data>
+<data>4.079</data>
+</row>
+<row>
+<data>PCSD|rxrefclk</data>
+<data>100.0 MHz</data>
+<data>170.5 MHz</data>
+<data>4.136</data>
+</row>
+<row>
+<data>System</data>
+<data>100.0 MHz</data>
+<data>18518.5 MHz</data>
+<data>9.946</data>
+</row>
+</report_table>

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_warnings.txt b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_warnings.txt
new file mode 100644 (file)
index 0000000..5df4948
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_fpga_mapper_warnings.txt
@@ -0,0 +1,3 @@
+@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":118:4:118:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+@W: MT420 |Found inferred clock PCSD|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"
+@W: MT420 |Found inferred clock PCSD|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_errors.txt b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_errors.txt
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_notes.txt b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_notes.txt
new file mode 100644 (file)
index 0000000..eed8756
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_notes.txt
@@ -0,0 +1,2 @@
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_runstatus.xml b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_runstatus.xml
new file mode 100644 (file)
index 0000000..3302c41
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_runstatus.xml
@@ -0,0 +1,46 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the job information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<job_run_status name="Mapper">
+<report_link name="Detailed report">
+<data>/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/PCSD_premap.srr</data>
+<title>Synopsys Lattice Technology Pre-mapping</title>
+</report_link>
+<job_status>
+<data>Completed</data>
+</job_status>
+<job_info>
+<info name="Notes">
+<data>2</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_notes.txt</data>
+</report_link>
+</info>
+<info name="Warnings">
+<data>2</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_warnings.txt</data>
+</report_link>
+</info>
+<info name="Errors">
+<data>0</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_errors.txt</data>
+</report_link>
+</info>
+<info name="CPU Time">
+<data>0h:00m:00s</data>
+</info>
+<info name="Real Time">
+<data>0h:00m:00s</data>
+</info>
+<info name="Peak Memory">
+<data>143MB</data>
+</info>
+<info name="Date &amp; Time">
+<data type="timestamp">1556618988</data>
+</info>
+</job_info>
+</job_run_status>

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_warnings.txt b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_warnings.txt
new file mode 100644 (file)
index 0000000..22d5ea5
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/PCSD_premap_warnings.txt
@@ -0,0 +1,2 @@
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":412:3:412:8|Found inferred clock PCSD|pll_refclki which controls 33 sequential elements including rsl_inst.genblk1\.plol_cnt[19:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Found inferred clock PCSD|rxrefclk which controls 59 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/report/metrics.db b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/metrics.db
new file mode 100644 (file)
index 0000000..3d974e4
Binary files /dev/null and b/gbe/cores/sgmii/PCSD/syn_results/synlog/report/metrics.db differ

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synlog/syntax_constraint_check.rpt.rptmap b/gbe/cores/sgmii/PCSD/syn_results/synlog/syntax_constraint_check.rpt.rptmap
new file mode 100644 (file)
index 0000000..947df5a
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/synlog/syntax_constraint_check.rpt.rptmap
@@ -0,0 +1 @@
+./PCSD_scck.rpt,syntax_constraint_check.rpt,Syntax Constraint Check Report

diff --git a/gbe/cores/sgmii/PCSD/syn_results/syntmp/PCSD.plg b/gbe/cores/sgmii/PCSD/syn_results/syntmp/PCSD.plg
new file mode 100644 (file)
index 0000000..822a386
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/syntmp/PCSD.plg
@@ -0,0 +1,19 @@
+@P:  Worst Slack : 4.079
+@P:  PCSD|pll_refclki - Estimated Frequency : 168.9 MHz
+@P:  PCSD|pll_refclki - Requested Frequency : 100.0 MHz
+@P:  PCSD|pll_refclki - Estimated Period : 5.921
+@P:  PCSD|pll_refclki - Requested Period : 10.000
+@P:  PCSD|pll_refclki - Slack : 4.079
+@P:  PCSD|rxrefclk - Estimated Frequency : 170.5 MHz
+@P:  PCSD|rxrefclk - Requested Frequency : 100.0 MHz
+@P:  PCSD|rxrefclk - Estimated Period : 5.864
+@P:  PCSD|rxrefclk - Requested Period : 10.000
+@P:  PCSD|rxrefclk - Slack : 4.136
+@P:  System - Estimated Frequency : 18518.5 MHz
+@P:  System - Requested Frequency : 100.0 MHz
+@P:  System - Estimated Period : 0.054
+@P:  System - Requested Period : 10.000
+@P:  System - Slack : 9.946
+@P:  Total Area : 63.0
+@P:  Total Area : 0.0
+@P:  CPU Time : 0h:00m:02s

diff --git a/gbe/cores/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm b/gbe/cores/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm
new file mode 100644 (file)
index 0000000..bf0c410
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm
@@ -0,0 +1,848 @@
+<html><body><samp><pre>
+<!@TC:1556618984>
+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
+#install: /home/soft/lattice/diamond/3.10_x64/synpbase
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Tue Apr 30 12:09:44 2019
+
+#Implementation: syn_results
+
+<a name=compilerReport1></a>Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1556618986> | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+<a name=compilerReport2></a>Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1556618986> | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1556618986> | Setting time resolution to ps
+@N: : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd:24:7:24:11:@N::@XP_MSG">PCSD.vhd(24)</a><!@TM:1556618986> | Top entity is set to PCSD.
+VHDL syntax check successful!
+File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd changed - recompiling
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 72MB)
+
+
+Process completed successfully.
+# Tue Apr 30 12:09:44 2019
+
+###########################################################]
+<a name=compilerReport3></a>Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1556618986> | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v" (library work)
+Verilog syntax check successful!
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Tue Apr 30 12:09:45 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1556618986> | Setting time resolution to ps
+@N: : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd:24:7:24:11:@N::@XP_MSG">PCSD.vhd(24)</a><!@TM:1556618986> | Top entity is set to PCSD.
+File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd changed - recompiling
+File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling
+VHDL syntax check successful!
+File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd changed - recompiling
+@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd:24:7:24:11:@N:CD630:@XP_MSG">PCSD.vhd(24)</a><!@TM:1556618986> | Synthesizing work.pcsd.v1.
+Post processing for work.pcsd.v1
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB)
+
+
+Process completed successfully.
+# Tue Apr 30 12:09:45 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v" (library work)
+Verilog syntax check successful!
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:92:7:92:19:@N:CG364:@XP_MSG">PCSD_softlogic.v(92)</a><!@TM:1556618986> | Synthesizing module PCSDrsl_core in library work.
+
+       pnum_channels=32'b00000000000000000000000000000001
+       pprotocol=24'b010001110100001001000101
+       pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
+       pport_tx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100
+       pwait_tx_rdy=32'b00000000000000000000101110111000
+       pport_rx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100
+       pwait_rx_rdy=32'b00000000000000000000101110111000
+       wa_num_cycles=32'b00000000000000000000010000000000
+       dac_num_cycles=32'b00000000000000000000000000000011
+       lreset_pwidth=32'b00000000000000000000000000000011
+       lwait_b4_trst=32'b00000000000010111110101111000010
+       lwait_b4_trst_s=32'b00000000000000000000001100001101
+       lplol_cnt_width=32'b00000000000000000000000000010100
+       lwait_after_plol0=32'b00000000000000000000000000000100
+       lwait_b4_rrst=32'b00000000000000101100000000000000
+       lrrst_wait_width=32'b00000000000000000000000000010100
+       lwait_after_rrst=32'b00000000000011000011010100000000
+       lwait_b4_rrst_s=32'b00000000000000000000000111001100
+       lrlol_cnt_width=32'b00000000000000000000000000010011
+       lwait_after_lols=32'b00000000000000001100010000000000
+       lwait_after_lols_s=32'b00000000000000000000000010010110
+       llols_cnt_width=32'b00000000000000000000000000010010
+       lrdb_max=32'b00000000000000000000000000001111
+       ltxr_wait_width=32'b00000000000000000000000000001100
+       lrxr_wait_width=32'b00000000000000000000000000001100
+   Generated name = PCSDrsl_core_Z1_layer1
+<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:274:33:274:49:@W:CG360:@XP_MSG">PCSD_softlogic.v(274)</a><!@TM:1556618986> | Removing wire dual_or_serd_rst, as there is no assignment to it.</font>
+<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:275:33:275:47:@W:CG360:@XP_MSG">PCSD_softlogic.v(275)</a><!@TM:1556618986> | Removing wire tx_any_pcs_rst, as there is no assignment to it.</font>
+<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:276:33:276:43:@W:CG360:@XP_MSG">PCSD_softlogic.v(276)</a><!@TM:1556618986> | Removing wire tx_any_rst, as there is no assignment to it.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:277:33:277:42:@W:CG133:@XP_MSG">PCSD_softlogic.v(277)</a><!@TM:1556618986> | Object txsr_appd is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:278:33:278:43:@W:CG133:@XP_MSG">PCSD_softlogic.v(278)</a><!@TM:1556618986> | Object txdpr_appd is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:279:33:279:42:@W:CG133:@XP_MSG">PCSD_softlogic.v(279)</a><!@TM:1556618986> | Object txpr_appd is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:280:33:280:42:@W:CG133:@XP_MSG">PCSD_softlogic.v(280)</a><!@TM:1556618986> | Object txr_wt_en is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:281:33:281:43:@W:CG133:@XP_MSG">PCSD_softlogic.v(281)</a><!@TM:1556618986> | Object txr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:282:33:282:42:@W:CG360:@XP_MSG">PCSD_softlogic.v(282)</a><!@TM:1556618986> | Removing wire txr_wt_tc, as there is no assignment to it.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:283:33:283:44:@W:CG133:@XP_MSG">PCSD_softlogic.v(283)</a><!@TM:1556618986> | Object ruo_tx_rdyr is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:326:33:326:41:@W:CG133:@XP_MSG">PCSD_softlogic.v(326)</a><!@TM:1556618986> | Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:327:33:327:44:@W:CG360:@XP_MSG">PCSD_softlogic.v(327)</a><!@TM:1556618986> | Removing wire rrst_cnt_tc, as there is no assignment to it.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:328:33:328:42:@W:CG133:@XP_MSG">PCSD_softlogic.v(328)</a><!@TM:1556618986> | Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:341:33:341:40:@W:CG133:@XP_MSG">PCSD_softlogic.v(341)</a><!@TM:1556618986> | Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:342:33:342:40:@W:CG133:@XP_MSG">PCSD_softlogic.v(342)</a><!@TM:1556618986> | Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:343:33:343:43:@W:CG360:@XP_MSG">PCSD_softlogic.v(343)</a><!@TM:1556618986> | Removing wire rxp_cnt_tc, as there is no assignment to it.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:346:33:346:43:@W:CG133:@XP_MSG">PCSD_softlogic.v(346)</a><!@TM:1556618986> | Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:347:33:347:46:@W:CG360:@XP_MSG">PCSD_softlogic.v(347)</a><!@TM:1556618986> | Removing wire rlolsz_cnt_tc, as there is no assignment to it.</font>
+<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:350:33:350:44:@W:CG360:@XP_MSG">PCSD_softlogic.v(350)</a><!@TM:1556618986> | Removing wire rxp_cnt2_tc, as there is no assignment to it.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:351:33:351:48:@W:CG133:@XP_MSG">PCSD_softlogic.v(351)</a><!@TM:1556618986> | Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:352:33:352:44:@W:CG133:@XP_MSG">PCSD_softlogic.v(352)</a><!@TM:1556618986> | Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:353:33:353:47:@W:CG360:@XP_MSG">PCSD_softlogic.v(353)</a><!@TM:1556618986> | Removing wire data_loop_b_tc, as there is no assignment to it.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:356:33:356:42:@W:CG133:@XP_MSG">PCSD_softlogic.v(356)</a><!@TM:1556618986> | Object rxsr_appd is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:357:33:357:42:@W:CG133:@XP_MSG">PCSD_softlogic.v(357)</a><!@TM:1556618986> | Object rxpr_appd is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:358:33:358:43:@W:CG133:@XP_MSG">PCSD_softlogic.v(358)</a><!@TM:1556618986> | Object rxsdr_appd is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:359:33:359:43:@W:CG133:@XP_MSG">PCSD_softlogic.v(359)</a><!@TM:1556618986> | Object rxdpr_appd is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:360:33:360:49:@W:CG360:@XP_MSG">PCSD_softlogic.v(360)</a><!@TM:1556618986> | Removing wire rxsdr_or_sr_appd, as there is no assignment to it.</font>
+<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:361:33:361:50:@W:CG360:@XP_MSG">PCSD_softlogic.v(361)</a><!@TM:1556618986> | Removing wire dual_or_rserd_rst, as there is no assignment to it.</font>
+<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:362:33:362:47:@W:CG360:@XP_MSG">PCSD_softlogic.v(362)</a><!@TM:1556618986> | Removing wire rx_any_pcs_rst, as there is no assignment to it.</font>
+<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:363:33:363:43:@W:CG360:@XP_MSG">PCSD_softlogic.v(363)</a><!@TM:1556618986> | Removing wire rx_any_rst, as there is no assignment to it.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:364:33:364:42:@W:CG133:@XP_MSG">PCSD_softlogic.v(364)</a><!@TM:1556618986> | Object rxr_wt_en is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:365:33:365:43:@W:CG133:@XP_MSG">PCSD_softlogic.v(365)</a><!@TM:1556618986> | Object rxr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:366:33:366:42:@W:CG360:@XP_MSG">PCSD_softlogic.v(366)</a><!@TM:1556618986> | Removing wire rxr_wt_tc, as there is no assignment to it.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:367:33:367:44:@W:CG133:@XP_MSG">PCSD_softlogic.v(367)</a><!@TM:1556618986> | Object ruo_rx_rdyr is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:507:10:507:11:@W:CG133:@XP_MSG">PCSD_softlogic.v(507)</a><!@TM:1556618986> | Object m is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:880:10:880:11:@W:CG133:@XP_MSG">PCSD_softlogic.v(880)</a><!@TM:1556618986> | Object l is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:806:3:806:9:@W:CL169:@XP_MSG">PCSD_softlogic.v(806)</a><!@TM:1556618986> | Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.</font>
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:567:3:567:9:@W:CL169:@XP_MSG">PCSD_softlogic.v(567)</a><!@TM:1556618986> | Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.</font>
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:567:3:567:9:@W:CL169:@XP_MSG">PCSD_softlogic.v(567)</a><!@TM:1556618986> | Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.</font>
+<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:694:3:694:9:@W:CL190:@XP_MSG">PCSD_softlogic.v(694)</a><!@TM:1556618986> | Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
+<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:461:3:461:9:@W:CL190:@XP_MSG">PCSD_softlogic.v(461)</a><!@TM:1556618986> | Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
+<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:422:3:422:9:@W:CL190:@XP_MSG">PCSD_softlogic.v(422)</a><!@TM:1556618986> | Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
+<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:422:3:422:9:@W:CL260:@XP_MSG">PCSD_softlogic.v(422)</a><!@TM:1556618986> | Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
+<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:461:3:461:9:@W:CL260:@XP_MSG">PCSD_softlogic.v(461)</a><!@TM:1556618986> | Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
+<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:694:3:694:9:@W:CL260:@XP_MSG">PCSD_softlogic.v(694)</a><!@TM:1556618986> | Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
+<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:200:33:200:49:@W:CL246:@XP_MSG">PCSD_softlogic.v(200)</a><!@TM:1556618986> | Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.</font>
+<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:204:33:204:52:@W:CL246:@XP_MSG">PCSD_softlogic.v(204)</a><!@TM:1556618986> | Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.</font>
+<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:205:33:205:49:@W:CL246:@XP_MSG">PCSD_softlogic.v(205)</a><!@TM:1556618986> | Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.</font>
+<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:206:33:206:49:@W:CL246:@XP_MSG">PCSD_softlogic.v(206)</a><!@TM:1556618986> | Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.</font>
+<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:207:33:207:49:@W:CL246:@XP_MSG">PCSD_softlogic.v(207)</a><!@TM:1556618986> | Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.</font>
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 75MB)
+
+
+Process completed successfully.
+# Tue Apr 30 12:09:45 2019
+
+###########################################################]
+<a name=compilerReport4></a>Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1556618986> | Running in 64-bit mode 
+File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/layer0.srs changed - recompiling
+File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/layer1.srs changed - recompiling
+
+=======================================================================================
+For a summary of linker messages for components that did not bind, please see log file:
+Linked File: <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.linkerlog:@XP_FILE">PCSD_comp.linkerlog</a>
+=======================================================================================
+
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Tue Apr 30 12:09:46 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Tue Apr 30 12:09:46 2019
+
+###########################################################]
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1556618984>
+<a name=compilerReport5></a>Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1556618987> | Running in 64-bit mode 
+File /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Tue Apr 30 12:09:47 2019
+
+###########################################################]
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1556618984>
+# Tue Apr 30 12:09:47 2019
+
+<a name=mapperReport6></a>Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35</a>
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc
+Linked File: <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD_scck.rpt:@XP_FILE">PCSD_scck.rpt</a>
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD_scck.rpt" file 
+@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1556618988> | Running in 64-bit mode. 
+@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1556618988> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist PCSD
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+
+<a name=mapperReport7></a>Clock Summary</a>
+******************
+
+          Start                Requested     Requested     Clock        Clock                   Clock
+Level     Clock                Frequency     Period        Type         Group                   Load 
+-----------------------------------------------------------------------------------------------------
+0 -       System               100.0 MHz     10.000        system       system_clkgroup         0    
+                                                                                                     
+0 -       PCSD|rxrefclk        100.0 MHz     10.000        inferred     Inferred_clkgroup_1     59   
+                                                                                                     
+0 -       PCSD|pll_refclki     100.0 MHz     10.000        inferred     Inferred_clkgroup_0     33   
+=====================================================================================================
+
+<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:412:3:412:9:@W:MT529:@XP_MSG">PCSD_softlogic.v(412)</a><!@TM:1556618988> | Found inferred clock PCSD|pll_refclki which controls 33 sequential elements including rsl_inst.genblk1\.plol_cnt[19:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
+<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:567:3:567:9:@W:MT529:@XP_MSG">PCSD_softlogic.v(567)</a><!@TM:1556618988> | Found inferred clock PCSD|rxrefclk which controls 59 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Tue Apr 30 12:09:48 2019
+
+###########################################################]
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1556618984>
+# Tue Apr 30 12:09:48 2019
+
+<a name=mapperReport8></a>Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35</a>
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1556618991> | Running in 64-bit mode. 
+@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1556618991> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:412:3:412:9:@N:MO231:@XP_MSG">PCSD_softlogic.v(412)</a><!@TM:1556618991> | Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk1\.plol_cnt[19:0] 
+@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:778:3:778:9:@N:MO231:@XP_MSG">PCSD_softlogic.v(778)</a><!@TM:1556618991> | Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] 
+@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v:680:3:680:9:@N:MO231:@XP_MSG">PCSD_softlogic.v(680)</a><!@TM:1556618991> | Found counter in view:work.PCSDrsl_core_Z1_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] 
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+   1           0h:00m:00s                   5.36ns               63 /        92
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1556618991> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+<a name=clockReport9></a>#### START OF CLOCK OPTIMIZATION REPORT #####[</a>
+
+2 non-gated/non-generated clock tree(s) driving 92 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+=================================== Non-Gated/Non-Generated Clocks ====================================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                
+-------------------------------------------------------------------------------------------------------
+<a href="@|S:rxrefclk@|E:rsl_inst.genblk2\.rlol1_cnt[18]@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001  @XP_NAMES_BY_PROP">ClockId0001 </a>       rxrefclk            port                   59         rsl_inst.genblk2\.rlol1_cnt[18]
+<a href="@|S:pll_refclki@|E:rsl_inst.genblk1\.pll_lol_p1@|F:@syn_sample_clock_path==CKID0002@|M:ClockId0002  @XP_NAMES_BY_PROP">ClockId0002 </a>       pll_refclki         port                   33         rsl_inst.genblk1\.pll_lol_p1   
+=======================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 107MB peak: 144MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB)
+
+Writing EDIF Netlist and constraint files
+@N:<a href="@N:FX1056:@XP_HELP">FX1056</a> : <!@TM:1556618991> | Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.edn 
+M-2017.03L-SP1-1
+@N:<a href="@N:BW106:@XP_HELP">BW106</a> : <!@TM:1556618991> | Synplicity Constraint File capacitance units using default value of 1pF  
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 148MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 148MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB)
+
+<font color=#A52A2A>@W:<a href="@W:MT246:@XP_HELP">MT246</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd:118:4:118:13:@W:MT246:@XP_MSG">PCSD.vhd(118)</a><!@TM:1556618991> | Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) </font>
+<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1556618991> | Found inferred clock PCSD|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"</font> 
+<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1556618991> | Found inferred clock PCSD|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"</font> 
+
+
+<a name=timingReport10></a>##### START OF TIMING REPORT #####[</a>
+# Timing Report written on Tue Apr 30 12:09:50 2019
+#
+
+
+Top view:               PCSD
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.fdc
+                       
+@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1556618991> | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 
+
+@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1556618991> | Clock constraints include only register-to-register paths associated with each individual clock. 
+
+
+
+<a name=performanceSummary11></a>Performance Summary</a>
+*******************
+
+
+Worst slack in design: 4.079
+
+@N:<a href="@N:MT286:@XP_HELP">MT286</a> : <!@TM:1556618991> | System clock period 0.000 stretches to negative invalid value -- ignoring stretching. 
+                     Requested     Estimated       Requested     Estimated               Clock        Clock              
+Starting Clock       Frequency     Frequency       Period        Period        Slack     Type         Group              
+-------------------------------------------------------------------------------------------------------------------------
+PCSD|pll_refclki     100.0 MHz     168.9 MHz       10.000        5.921         4.079     inferred     Inferred_clkgroup_0
+PCSD|rxrefclk        100.0 MHz     170.5 MHz       10.000        5.864         4.136     inferred     Inferred_clkgroup_1
+System               100.0 MHz     18518.5 MHz     10.000        0.054         9.946     system       system_clkgroup    
+=========================================================================================================================
+
+
+
+
+
+<a name=clockRelationships12></a>Clock Relationships</a>
+*******************
+
+Clocks                              |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+---------------------------------------------------------------------------------------------------------------------------
+Starting          Ending            |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
+---------------------------------------------------------------------------------------------------------------------------
+System            System            |  10.000      10.000  |  No paths    -      |  No paths    -      |  No paths    -    
+System            PCSD|rxrefclk     |  10.000      9.946   |  No paths    -      |  No paths    -      |  No paths    -    
+PCSD|pll_refclki  System            |  10.000      8.385   |  No paths    -      |  No paths    -      |  No paths    -    
+PCSD|pll_refclki  PCSD|pll_refclki  |  10.000      4.079   |  No paths    -      |  No paths    -      |  No paths    -    
+PCSD|rxrefclk     System            |  10.000      8.283   |  No paths    -      |  No paths    -      |  No paths    -    
+PCSD|rxrefclk     PCSD|rxrefclk     |  10.000      4.136   |  No paths    -      |  No paths    -      |  No paths    -    
+===========================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+<a name=interfaceInfo13></a>Interface Information </a>
+*********************
+
+No IO constraint found
+
+
+
+====================================
+<a name=clockReport14></a>Detailed Report for Clock: PCSD|pll_refclki</a>
+====================================
+
+
+
+<a name=startingSlack15></a>Starting Points with Worst Slack</a>
+********************************
+
+                                   Starting                                                  Arrival          
+Instance                           Reference            Type        Pin     Net              Time        Slack
+                                   Clock                                                                      
+--------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[1]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[1]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[6]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[6]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[7]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[7]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[12]     PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[12]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[2]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[2]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[3]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[3]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[4]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[4]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[5]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[5]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[8]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[8]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[9]      PCSD|pll_refclki     FD1S3DX     Q       plol_cnt[9]      0.907       4.684
+==============================================================================================================
+
+
+<a name=endingSlack16></a>Ending Points with Worst Slack</a>
+******************************
+
+                                   Starting                                                    Required          
+Instance                           Reference            Type        Pin     Net                Time         Slack
+                                   Clock                                                                         
+-----------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[19]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[19]     9.946        4.079
+rsl_inst.genblk1\.plol_cnt[17]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[17]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[18]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[18]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[15]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[15]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[16]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[16]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[13]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[13]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[14]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[14]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[11]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[11]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[12]     PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[12]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[9]      PCSD|pll_refclki     FD1S3DX     D       plol_cnt_s[9]      9.946        4.383
+=================================================================================================================
+
+
+
+<a name=worstPaths17></a>Worst Path Information</a>
+<a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.srr:srsf/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.srs:fp:38560:43552:@XP_NAMES_GATE">View Worst Path in Analyst</a>
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.867
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     4.079
+
+    Number of logic level(s):                15
+    Starting point:                          rsl_inst.genblk1\.plol_cnt[1] / Q
+    Ending point:                            rsl_inst.genblk1\.plol_cnt[19] / D
+    The start point is clocked by            PCSD|pll_refclki [rising] on pin CK
+    The end   point is clocked by            PCSD|pll_refclki [rising] on pin CK
+
+Instance / Net                                        Pin      Pin               Arrival     No. of    
+Name                                     Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[1]            FD1S3DX      Q        Out     0.907     0.907       -         
+plol_cnt[1]                              Net          -        -       -         -           2         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     Z        Out     0.606     1.513       -         
+un1_plol_cnt_tc_10                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     Z        Out     0.606     2.119       -         
+un1_plol_cnt_tc_14                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     Z        Out     0.762     2.881       -         
+un1_plol_cnt_tc                          Net          -        -       -         -           5         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     B        In      0.000     2.881       -         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     Z        Out     0.840     3.721       -         
+plol_cnt                                 Net          -        -       -         -           21        
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.721       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.621       -         
+plol_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.621       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.682       -         
+plol_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.682       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.743       -         
+plol_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.743       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.804       -         
+plol_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.804       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.865       -         
+plol_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.865       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.926       -         
+plol_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.926       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.987       -         
+plol_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.987       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.048       -         
+plol_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.048       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.109       -         
+plol_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.109       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        COUT     Out     0.061     5.170       -         
+plol_cnt_cry[18]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        CIN      In      0.000     5.170       -         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        S0       Out     0.698     5.867       -         
+plol_cnt_s[19]                           Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt[19]           FD1S3DX      D        In      0.000     5.867       -         
+=======================================================================================================
+
+
+
+
+====================================
+<a name=clockReport18></a>Detailed Report for Clock: PCSD|rxrefclk</a>
+====================================
+
+
+
+<a name=startingSlack19></a>Starting Points with Worst Slack</a>
+********************************
+
+                                     Starting                                                 Arrival          
+Instance                             Reference         Type        Pin     Net                Time        Slack
+                                     Clock                                                                     
+---------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[14]      PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[14]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[15]      PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[15]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[16]      PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[16]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[17]      PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[17]      0.907       4.136
+rsl_inst.genblk2\.rlols0_cnt[10]     PCSD|rxrefclk     FD1P3DX     Q       rlols0_cnt[10]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[14]     PCSD|rxrefclk     FD1P3DX     Q       rlols0_cnt[14]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[16]     PCSD|rxrefclk     FD1P3DX     Q       rlols0_cnt[16]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[17]     PCSD|rxrefclk     FD1P3DX     Q       rlols0_cnt[17]     0.907       4.170
+rsl_inst.genblk2\.rlol1_cnt[0]       PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[0]       0.907       4.742
+rsl_inst.genblk2\.rlol1_cnt[1]       PCSD|rxrefclk     FD1P3DX     Q       rlol1_cnt[1]       0.907       4.742
+===============================================================================================================
+
+
+<a name=endingSlack20></a>Ending Points with Worst Slack</a>
+******************************
+
+                                     Starting                                                   Required          
+Instance                             Reference         Type        Pin     Net                  Time         Slack
+                                     Clock                                                                        
+------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[17]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[17]      9.946        4.136
+rsl_inst.genblk2\.rlol1_cnt[18]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[18]      9.946        4.136
+rsl_inst.genblk2\.rlols0_cnt[17]     PCSD|rxrefclk     FD1P3DX     D       rlols0_cnt_s[17]     9.946        4.170
+rsl_inst.genblk2\.rlol1_cnt[15]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[15]      9.946        4.197
+rsl_inst.genblk2\.rlol1_cnt[16]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[16]      9.946        4.197
+rsl_inst.genblk2\.rlols0_cnt[15]     PCSD|rxrefclk     FD1P3DX     D       rlols0_cnt_s[15]     9.946        4.231
+rsl_inst.genblk2\.rlols0_cnt[16]     PCSD|rxrefclk     FD1P3DX     D       rlols0_cnt_s[16]     9.946        4.231
+rsl_inst.genblk2\.rlol1_cnt[13]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[13]      9.946        4.258
+rsl_inst.genblk2\.rlol1_cnt[14]      PCSD|rxrefclk     FD1P3DX     D       rlol1_cnt_s[14]      9.946        4.258
+rsl_inst.genblk2\.rlols0_cnt[13]     PCSD|rxrefclk     FD1P3DX     D       rlols0_cnt_s[13]     9.946        4.292
+==================================================================================================================
+
+
+
+<a name=worstPaths21></a>Worst Path Information</a>
+<a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.srr:srsf/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.srs:fp:48462:53187:@XP_NAMES_GATE">View Worst Path in Analyst</a>
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.809
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.136
+
+    Number of logic level(s):                14
+    Starting point:                          rsl_inst.genblk2\.rlol1_cnt[14] / Q
+    Ending point:                            rsl_inst.genblk2\.rlol1_cnt[18] / D
+    The start point is clocked by            PCSD|rxrefclk [rising] on pin CK
+    The end   point is clocked by            PCSD|rxrefclk [rising] on pin CK
+
+Instance / Net                                         Pin      Pin               Arrival     No. of    
+Name                                      Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[14]           FD1P3DX      Q        Out     0.907     0.907       -         
+rlol1_cnt[14]                             Net          -        -       -         -           2         
+rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     Z        Out     0.606     1.513       -         
+rlol1_cnt_tc_1_10                         Net          -        -       -         -           1         
+rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     Z        Out     0.606     2.119       -         
+rlol1_cnt_tc_1_14                         Net          -        -       -         -           1         
+rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     Z        Out     0.768     2.887       -         
+rlol1_cnt_tc_1                            Net          -        -       -         -           6         
+rsl_inst.genblk2\.rxs_rst_RNIS0OP         ORCALUT4     A        In      0.000     2.887       -         
+rsl_inst.genblk2\.rxs_rst_RNIS0OP         ORCALUT4     Z        Out     0.837     3.724       -         
+rlol1_cnt                                 Net          -        -       -         -           20        
+rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.724       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.624       -         
+rlol1_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.624       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.685       -         
+rlol1_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.685       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.746       -         
+rlol1_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.746       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.807       -         
+rlol1_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.807       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.868       -         
+rlol1_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.868       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.929       -         
+rlol1_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.929       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.990       -         
+rlol1_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.990       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.051       -         
+rlol1_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.051       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.112       -         
+rlol1_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.112       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        S1       Out     0.698     5.809       -         
+rlol1_cnt_s[18]                           Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt[18]           FD1P3DX      D        In      0.000     5.809       -         
+========================================================================================================
+
+
+
+
+====================================
+<a name=clockReport22></a>Detailed Report for Clock: System</a>
+====================================
+
+
+
+<a name=startingSlack23></a>Starting Points with Worst Slack</a>
+********************************
+
+              Starting                                                   Arrival           
+Instance      Reference     Type     Pin                Net              Time        Slack 
+              Clock                                                                        
+-------------------------------------------------------------------------------------------
+DCU0_inst     System        DCUA     CH0_FFS_RLOL       rx_cdr_lol_s     0.000       9.946 
+DCU0_inst     System        DCUA     CH0_FFS_RLOS       rx_los_low_s     0.000       9.946 
+DCU0_inst     System        DCUA     CH0_FF_TX_PCLK     tx_pclk          0.000       10.000
+===========================================================================================
+
+
+<a name=endingSlack24></a>Ending Points with Worst Slack</a>
+******************************
+
+                              Starting                                                       Required           
+Instance                      Reference     Type        Pin                 Net              Time         Slack 
+                              Clock                                                                             
+----------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol_p1     System        FD1S3DX     D                   rx_cdr_lol_s     9.946        9.946 
+rsl_inst.genblk2\.rlos_p1     System        FD1S3DX     D                   rx_los_low_s     9.946        9.946 
+DCU0_inst                     System        DCUA        CH0_FF_EBRD_CLK     tx_pclk          10.000       10.000
+DCU0_inst                     System        DCUA        CH0_FF_RXI_CLK      tx_pclk          10.000       10.000
+================================================================================================================
+
+
+
+<a name=worstPaths25></a>Worst Path Information</a>
+<a href="/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.srr:srsf/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD.srs:fp:56441:56741:@XP_NAMES_GATE">View Worst Path in Analyst</a>
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      0.000
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 9.946
+
+    Number of logic level(s):                0
+    Starting point:                          DCU0_inst / CH0_FFS_RLOL
+    Ending point:                            rsl_inst.genblk2\.rlol_p1 / D
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            PCSD|rxrefclk [rising] on pin CK
+
+Instance / Net                            Pin              Pin               Arrival     No. of    
+Name                          Type        Name             Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------------------
+DCU0_inst                     DCUA        CH0_FFS_RLOL     Out     0.000     0.000       -         
+rx_cdr_lol_s                  Net         -                -       -         -           2         
+rsl_inst.genblk2\.rlol_p1     FD1S3DX     D                In      0.000     0.000       -         
+===================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 147MB peak: 148MB)
+
+---------------------------------------
+<a name=resourceUsage26></a>Resource Usage Report</a>
+Part: lfe5um_25f-6
+
+Register bits: 92 of 24288 (0%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+CCU2C:          37
+DCUA:           1
+FD1P3BX:        4
+FD1P3DX:        42
+FD1S3BX:        10
+FD1S3DX:        36
+GSR:            1
+ORCALUT4:       63
+PFUMX:          2
+PUR:            1
+VHI:            2
+VLO:            2
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 32MB peak: 148MB)
+
+Process took 0h:00m:02s realtime, 0h:00m:02s cputime
+# Tue Apr 30 12:09:51 2019
+
+###########################################################]
+
+</pre></samp></body></html>

diff --git a/gbe/cores/sgmii/PCSD/syn_results/syntmp/PCSD_toc.htm b/gbe/cores/sgmii/PCSD/syn_results/syntmp/PCSD_toc.htm
new file mode 100644 (file)
index 0000000..9a28325
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/syntmp/PCSD_toc.htm
@@ -0,0 +1,55 @@
+ <html> 
+  <head>
+    <script type="text/javascript" src="file:///home/soft/lattice/diamond/3.10_x64/synpbase/lib/report/reportlog_tree.js"></script>
+    <link rel="stylesheet" type="text/css" href="file:///home/soft/lattice/diamond/3.10_x64/synpbase/lib/report/reportlog_tree.css" />  
+  </head> 
+
+  <body style="background-color:#e0e0ff;">
+   <script type="text/javascript"> reportLogObj.loadImage("closed.png", "open.png")</script>
+    <ul id="syn_results-menu" class="treeview" style="padding-left:12;">
+        <li style="font-size:12; font-style:normal"> <b style="background-color:#a2bff0; font-weight:bold">PCSD (syn_results)</b> 
+         <ul rel="open" style="font-size:small;">
+
+<li style="font-size:12; font-style:normal"><b style="background-color:#a2bff0; font-weight:bold">Synthesis -  </b> 
+<ul rel="open">
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#compilerReport1" target="srrFrame" title="">Compiler Report</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#compilerReport4" target="srrFrame" title="">Compiler Constraint Applicator</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#mapperReport6" target="srrFrame" title="">Pre-mapping Report</a>  
+<ul rel="open" >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#mapperReport7" target="srrFrame" title="">Clock Summary</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#mapperReport8" target="srrFrame" title="">Mapper Report</a>  
+<ul rel="open" >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#clockReport9" target="srrFrame" title="">Clock Conversion</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#timingReport10" target="srrFrame" title="">Timing Report</a>  
+<ul rel="open" >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#performanceSummary11" target="srrFrame" title="">Performance Summary</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#clockRelationships12" target="srrFrame" title="">Clock Relationships</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#interfaceInfo13" target="srrFrame" title="">Interface Information</a>  </li>
+<li><a href="file://#" target="srrFrame" title="">Detailed Report for Clocks</a>  
+<ul  >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#clockReport14" target="srrFrame" title="">Clock: PCSD|pll_refclki</a>  
+<ul  >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#startingSlack15" target="srrFrame" title="">Starting Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#endingSlack16" target="srrFrame" title="">Ending Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#worstPaths17" target="srrFrame" title="">Worst Path Information</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#clockReport18" target="srrFrame" title="">Clock: PCSD|rxrefclk</a>  
+<ul  >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#startingSlack19" target="srrFrame" title="">Starting Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#endingSlack20" target="srrFrame" title="">Ending Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#worstPaths21" target="srrFrame" title="">Worst Path Information</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#clockReport22" target="srrFrame" title="">Clock: System</a>  
+<ul  >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#startingSlack23" target="srrFrame" title="">Starting Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#endingSlack24" target="srrFrame" title="">Ending Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#worstPaths25" target="srrFrame" title="">Worst Path Information</a>  </li></ul></li></ul></li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/PCSD_srr.htm#resourceUsage26" target="srrFrame" title="">Resource Utilization</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/PCSD_cck.rpt" target="srrFrame" title="">Constraint Checker Report (12:09 30-Apr)</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/PCSD/stdout.log" target="srrFrame" title="">Session Log (12:09 30-Apr)</a>  
+<ul  ></ul></li>         </ul>
+        </li>
+   </ul>
+
+   <script type="text/javascript"> reportLogObj.generateLog("syn_results-menu")</script>
+
+  </body>
+ </html>
\ No newline at end of file

diff --git a/gbe/cores/sgmii/PCSD/syn_results/syntmp/closed.png b/gbe/cores/sgmii/PCSD/syn_results/syntmp/closed.png
new file mode 100644 (file)
index 0000000..0d78634
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diff --git a/gbe/cores/sgmii/PCSD/syn_results/syntmp/open.png b/gbe/cores/sgmii/PCSD/syn_results/syntmp/open.png
new file mode 100644 (file)
index 0000000..a227005
Binary files /dev/null and b/gbe/cores/sgmii/PCSD/syn_results/syntmp/open.png differ

diff --git a/gbe/cores/sgmii/PCSD/syn_results/syntmp/run_option.xml b/gbe/cores/sgmii/PCSD/syn_results/syntmp/run_option.xml
new file mode 100644 (file)
index 0000000..b616b1f
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/syntmp/run_option.xml
@@ -0,0 +1,24 @@
+<?xml version="1.0" encoding="utf-8"?> 
+<!-- 
+  Synopsys, Inc.
+  Version M-2017.03L-SP1-1
+  Project file /home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/syntmp/run_option.xml
+  Written on Tue Apr 30 12:09:44 2019
+
+
+--> 
+<project_attribute_list name="Project Settings"> 
+     <option name="project_name" display_name="Project Name">PCSD</option>
+     <option name="device_name" display_name="Device Name">syn_results: Lattice ECP5UM : LFE5UM_25F</option>
+     <option name="impl_name" display_name="Implementation Name">syn_results</option>
+     <option name="top_module" display_name="Top Module">PCSD</option>
+     <option name="pipe" display_name="Pipelining">0</option>
+     <option name="retiming" display_name="Retiming">0</option>
+     <option name="resource_sharing" display_name="Resource Sharing">1</option>
+     <option name="maxfan" display_name="Fanout Guide">50</option>
+     <option name="disable_io_insertion" display_name="Disable I/O Insertion">1</option>
+     <option name="no_sequential_opt" display_name="Disable Sequential Optimizations">0</option>
+     <option name="fix_gated_and_generated_clocks" display_name="Clock Conversion">1</option>
+     <option name="symbolic_fsm_compiler" display_name="FSM Compiler">1</option>
+</project_attribute_list>
+

diff --git a/gbe/cores/sgmii/PCSD/syn_results/syntmp/statusReport.html b/gbe/cores/sgmii/PCSD/syn_results/syntmp/statusReport.html
new file mode 100644 (file)
index 0000000..b48fd55
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/syntmp/statusReport.html
@@ -0,0 +1,114 @@
+<html> 
+                       <head>                  <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1" />
+                       <title>Project Status Summary Page</title>
+                       <link rel="stylesheet" type="text/css" href="projectstatuspage.css" />
+                       <script type = "text/javascript" src="projectstatuspage.js"></script>
+                       </head>
+
+                       <body style="background-color:#f0f0ff;">
+                       
+<table style="border:none;" width="100%" ><tr> <td class="outline">
+<table width="100%" border="0" cellspacing="0" cellpadding="0">             <thead class="tablehead"><tr><th colspan="4">Project Settings</th><tr> 
+ <tr> <td class="optionTitle" align="left"> Project Name</td> <td> PCSD</td> <td class="optionTitle" align="left"> Device Name</td> <td> syn_results: Lattice ECP5UM : LFE5UM_25F</td> </tr>
+<tr> <td class="optionTitle" align="left"> Implementation Name</td> <td> syn_results</td> <td class="optionTitle" align="left"> Top Module</td> <td> PCSD</td> </tr>
+                </thead> 
+                <tbody> <tr> <td class="optionTitle" align="left"> Pipelining</td> <td> 0</td> <td class="optionTitle" align="left"> Retiming</td> <td> 0</td> </tr>
+<tr> <td class="optionTitle" align="left"> Resource Sharing</td> <td> 1</td> <td class="optionTitle" align="left"> Fanout Guide</td> <td> 50</td> </tr>
+<tr> <td class="optionTitle" align="left"> Disable I/O Insertion</td> <td> 1</td> <td class="optionTitle" align="left"> Disable Sequential Optimizations</td> <td> 0</td> </tr>
+<tr> <td class="optionTitle" align="left"> Clock Conversion</td> <td> 1</td> <td class="optionTitle" align="left"> FSM Compiler</td> <td> 1</td> </tr>
+ 
+</tbody> 
+  </table><br>  <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
+                                  <thead class="tablehead"><tr><th   colspan="9">Run Status</th></tr></thead>
+         <tbody>
+               <tr>
+                       <th align="left" width="17%">Job Name</th>
+                       <th align="left">Status</th>
+                       <td class="lnote" align="center" title="Notes"></td>
+                       <td class="lwarn" align="center" title="Warnings"></td>
+                       <td class="lerror" align="center" title="Errors"></td>
+                       <th align="left">CPU Time</th>
+                       <th align="left">Real Time</th>
+                       <th align="left">Memory</th>
+                       <th align="left">Date/Time</th>
+         </tr>
+  <tr>
+  <td class="optionTitle"> (compiler)</td><td>Complete</td>
+ <td>10</td>
+ <td>50</td>
+<td>0</td>
+<td>-</td>
+<td>00m:02s</td>
+<td>-</td>
+<td><font size="-1">4/30/19</font><br/><font size="-2">12:09 PM</font></td>
+</tr> 
+
+ <tr>
+  <td class="optionTitle"> (premap)</td><td>Complete</td>
+ <td>2</td>
+ <td>2</td>
+<td>0</td>
+<td>0m:00s</td>
+<td>0m:00s</td>
+<td>143MB</td>
+<td><font size="-1">4/30/19</font><br/><font size="-2">12:09 PM</font></td>
+</tr> 
+
+ <tr>
+  <td class="optionTitle"> (fpga_mapper)</td><td>Complete</td>
+ <td>11</td>
+ <td>3</td>
+<td>0</td>
+<td>0m:02s</td>
+<td>0m:02s</td>
+<td>148MB</td>
+<td><font size="-1">4/30/19</font><br/><font size="-2">12:09 PM</font></td>
+</tr> 
+
+<tr>
+  <td class="optionTitle">Multi-srs Generator</td>
+  <td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td></td><td class="empty"></td><td class="empty"></td><td><font size="-1">4/30/19</font><br/><font size="-2">12:09 PM</font></td>             </tbody>
+     </table>
+ <br> 
+ <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
+                                  <thead class="tablehead"><tr><th   colspan="4">Area Summary</th></tr></thead>
+<tfoot> <tr> <td class="optionTitle" colspan="4"></td></tr> 
+ </tfoot> 
+ <tbody> <tr> 
+<td title ="Total Register bits used" class="optionTitle" align="left">Register bits</td> <td>92</td>
+<td title ="Total I/O cells used" class="optionTitle" align="left">I/O cells</td> <td>0</td>
+</tr>
+<tr> 
+<td title ="Total Block RAMs used" class="optionTitle" align="left">Block RAMs
+(v_ram)</td> <td>0</td>
+<td title ="Total DSPs used" class="optionTitle" align="left">DSPs
+(dsp_used)</td> <td>0</td>
+</tr>
+<tr> 
+<td title ="Total ORCA LUTs used" class="optionTitle" align="left">ORCA LUTs
+(total_luts)</td> <td>63</td>
+<td class="optionTitle"></td><td></td></tr> 
+</tbody>
+    </table><br>
+ <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
+                                  <thead class="tablehead"><tr><th   colspan="4">Timing Summary</th></tr></thead>
+<tfoot> <tr> <td class="optionTitle" colspan="2"></td></tr> 
+ </tfoot> 
+<tbody> 
+   <tr><th class="optionTitle" align= "left ">Clock Name</th><th class="optionTitle" align= "left ">Req Freq</th><th class="optionTitle" align= "left ">Est Freq</th><th class="optionTitle" align= "left ">Slack</th></tr> 
+<tr> <td  align="left">PCSD|pll_refclki</td><td  align="left">100.0 MHz</td><td  align="left">168.9 MHz</td><td  align="left">4.079</td></tr> 
+<tr> <td  align="left">PCSD|rxrefclk</td><td  align="left">100.0 MHz</td><td  align="left">170.5 MHz</td><td  align="left">4.136</td></tr> 
+<tr> <td  align="left">System</td><td  align="left">100.0 MHz</td><td  align="left">18518.5 MHz</td><td  align="left">9.946</td></tr> 
+</tbody> 
+ </table>
+<br>
+ <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
+                                  <thead class="tablehead"><tr><th   colspan="4">Optimizations Summary</th></tr></thead>
+ <tbody> <tr> 
+<td title ="Non-gated/non-generated clock trees / Gated/generated clock trees" class="optionTitle" align="left">Combined Clock Conversion</td> <td>2 / 0</td>
+<td class="optionTitle"></td><td></td></tr> 
+</tbody>
+    </table><br>
+<br> 
+</td></tr></table></body> 
+ </html>
\ No newline at end of file

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/.cckTransfer b/gbe/cores/sgmii/PCSD/syn_results/synwork/.cckTransfer
new file mode 100644 (file)
index 0000000..1106516
Binary files /dev/null and b/gbe/cores/sgmii/PCSD/syn_results/synwork/.cckTransfer differ

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_comp.fdep b/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_comp.fdep
new file mode 100644 (file)
index 0000000..48777ad
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_comp.fdep
@@ -0,0 +1,35 @@
+#OPTIONS:"|-mixedhdl|-top|PCSD|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610
+#CUR:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":1556618983
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599
+#OPTIONS:"|-mixedhdl|-modhint|/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/_verilog_hintfile|-top|work.PCSDrsl_core|-mpparams|/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/_mh_params|-layerid|1|-orig_srs|/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/|-I|/home/soft/lattice/diamond/3.10_x64/synpbase/lib|-v2001|-devicelib|/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v|-devicelib|/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_ver":1542167761
+#CUR:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/_verilog_hintfile":1556618984
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v":1542167595
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v":1542167597
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v":1542167630
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v":1542167630
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v":1542167630
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh":1542167630
+#CUR:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1556618983
+0                      "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd" vhdl
+1                      "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v" verilog
+#Dependency Lists(Uses List)
+0 1
+1 -1
+#Dependency Lists(Users Of)
+0 -1
+1 0
+#Design Unit to File Association
+module work PCSDrsl_core 1
+module work pcsd 0
+arch work pcsd v1 0

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_comp.linkerlog b/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_comp.linkerlog
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_comp.srs b/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_comp.srs
new file mode 100644 (file)
index 0000000..c237416
Binary files /dev/null and b/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_comp.srs differ

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_m.srm b/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_m.srm
new file mode 100644 (file)
index 0000000..ad3a4ed
Binary files /dev/null and b/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_m.srm differ

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_m_srm/1.srm b/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_m_srm/1.srm
new file mode 100644 (file)
index 0000000..635a948
Binary files /dev/null and b/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_m_srm/1.srm differ

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_m_srm/fileinfo.srm b/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_m_srm/fileinfo.srm
new file mode 100644 (file)
index 0000000..e391b1c
Binary files /dev/null and b/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_m_srm/fileinfo.srm differ

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_mult.srs b/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_mult.srs
new file mode 100644 (file)
index 0000000..a26742c
Binary files /dev/null and b/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_mult.srs differ

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_mult_srs/1.srs b/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_mult_srs/1.srs
new file mode 100644 (file)
index 0000000..77b4f44
Binary files /dev/null and b/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_mult_srs/1.srs differ

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_mult_srs/fileinfo.srs b/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_mult_srs/fileinfo.srs
new file mode 100644 (file)
index 0000000..1f3fbca
Binary files /dev/null and b/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_mult_srs/fileinfo.srs differ

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_mult_srs/skeleton.srs b/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_mult_srs/skeleton.srs
new file mode 100644 (file)
index 0000000..a3a2fba
Binary files /dev/null and b/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_mult_srs/skeleton.srs differ

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_prem.fse b/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_prem.fse
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_prem.srd b/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_prem.srd
new file mode 100644 (file)
index 0000000..061b989
Binary files /dev/null and b/gbe/cores/sgmii/PCSD/syn_results/synwork/PCSD_prem.srd differ

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/_mh_info b/gbe/cores/sgmii/PCSD/syn_results/synwork/_mh_info
new file mode 100644 (file)
index 0000000..206dc98
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/synwork/_mh_info
@@ -0,0 +1,2 @@
+|/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/layer1.info|
+|2|

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/_verilog_hintfile b/gbe/cores/sgmii/PCSD/syn_results/synwork/_verilog_hintfile
new file mode 100644 (file)
index 0000000..fe902b6
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/synwork/_verilog_hintfile
@@ -0,0 +1,54 @@
+%%% protect protected_file
+#OPTIONS:"|-bldtbl|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
+#CUR:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":1556618983
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599
+@E8lFkRDCu7B1
+LDHs$NsRsIF    k
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+kk0b0GRs_#DF_IDF_4#R
+0FkbRk0D_#l#00Nk##_RF4
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+HbRk0sbG_Ibsk_4OR
+bHMk#0RCCs8#8_bL
+R4HkMb0DRbDC_sV        ODH
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+R4HkMb0#RsD#_s0
+R4HkMb0CR#s#8C_0s#_N8kDR_O4M
+HbRk0s_#08DkN_4OR
+bHMk00RGC_#s#8C_0s#_4OR
+bHMk00RGO_b##_s0R_O4M
+HbRk0b_DDDRFD4M
+HbRk0s#G_CCs8##_s0R_O4M
+HbRk0sbG_Os#_#O0_RC4
+MF8l8CkD
+
+@ 

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/layer0.fdep b/gbe/cores/sgmii/PCSD/syn_results/synwork/layer0.fdep
new file mode 100644 (file)
index 0000000..b533443
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/synwork/layer0.fdep
@@ -0,0 +1,32 @@
+#defaultlanguage:vhdl
+#OPTIONS:"|-mixedhdl|-top|PCSD|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610
+#CUR:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":1556618983
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599
+0 "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd" vhdl
+
+# Dependency Lists (Uses list)
+0 -1
+
+# Dependency Lists (Users Of)
+0 -1
+
+# Design Unit to File Association
+arch work pcsd v1 0
+module work pcsd 0
+
+# Unbound Instances to File Association
+inst work pcsd pcsdrsl_core 0
+inst work pcsd dcua 0
+
+
+# Configuration files used

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/layer0.fdeporig b/gbe/cores/sgmii/PCSD/syn_results/synwork/layer0.fdeporig
new file mode 100644 (file)
index 0000000..41b0e30
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/synwork/layer0.fdeporig
@@ -0,0 +1,28 @@
+#defaultlanguage:vhdl
+#OPTIONS:"|-mixedhdl|-top|PCSD|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610
+#CUR:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":1556618983
+0 "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd" vhdl
+
+# Dependency Lists (Uses list)
+0 -1
+
+# Dependency Lists (Users Of)
+0 -1
+
+# Design Unit to File Association
+arch work pcsd v1 0
+module work pcsd 0
+
+# Unbound Instances to File Association
+inst work pcsd pcsdrsl_core 0
+inst work pcsd dcua 0

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/layer0.srs b/gbe/cores/sgmii/PCSD/syn_results/synwork/layer0.srs
new file mode 100644 (file)
index 0000000..6422805
Binary files /dev/null and b/gbe/cores/sgmii/PCSD/syn_results/synwork/layer0.srs differ

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/layer0.tlg b/gbe/cores/sgmii/PCSD/syn_results/synwork/layer0.tlg
new file mode 100644 (file)
index 0000000..8313fad
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/synwork/layer0.tlg
@@ -0,0 +1,2 @@
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD.vhd":24:7:24:10|Synthesizing work.pcsd.v1.
+Post processing for work.pcsd.v1

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/layer0.tlg.db b/gbe/cores/sgmii/PCSD/syn_results/synwork/layer0.tlg.db
new file mode 100644 (file)
index 0000000..8c34ade
Binary files /dev/null and b/gbe/cores/sgmii/PCSD/syn_results/synwork/layer0.tlg.db differ

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/layer1.fdep b/gbe/cores/sgmii/PCSD/syn_results/synwork/layer1.fdep
new file mode 100644 (file)
index 0000000..f0b8e36
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/synwork/layer1.fdep
@@ -0,0 +1,20 @@
+#OPTIONS:"|-mixedhdl|-modhint|/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/_verilog_hintfile|-top|work.PCSDrsl_core|-mpparams|/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/_mh_params|-layerid|1|-orig_srs|/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/PCSD_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/|-I|/home/soft/lattice/diamond/3.10_x64/synpbase/lib|-v2001|-devicelib|/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v|-devicelib|/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_ver":1542167761
+#CUR:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/syn_results/synwork/_verilog_hintfile":1556618984
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v":1542167595
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v":1542167597
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v":1542167630
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v":1542167630
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v":1542167630
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh":1542167630
+#CUR:"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":1556618983
+#numinternalfiles:6
+#defaultlanguage:verilog
+0                      "/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v" verilog
+#Dependency Lists(Uses List)
+0 -1
+#Dependency Lists(Users Of)
+0 -1
+#Design Unit to File Association
+module work PCSDrsl_core 0
+#Unbound instances to file Association.

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/layer1.fdepxmr b/gbe/cores/sgmii/PCSD/syn_results/synwork/layer1.fdepxmr
new file mode 100644 (file)
index 0000000..37d628b
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/synwork/layer1.fdepxmr
@@ -0,0 +1 @@
+#XMR Information

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/layer1.info b/gbe/cores/sgmii/PCSD/syn_results/synwork/layer1.info
new file mode 100644 (file)
index 0000000..25166f8
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/synwork/layer1.info
@@ -0,0 +1 @@
+|work.PCSDrsl_core|parameter pnum_channels 1;,parameter pprotocol "GBE";,parameter pserdes_mode "RX AND TX";,parameter pport_tx_rdy "DISABLED";,parameter pwait_tx_rdy 3000;,parameter pport_rx_rdy "DISABLED";,parameter pwait_rx_rdy 3000;|

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/layer1.srs b/gbe/cores/sgmii/PCSD/syn_results/synwork/layer1.srs
new file mode 100644 (file)
index 0000000..695bd25
Binary files /dev/null and b/gbe/cores/sgmii/PCSD/syn_results/synwork/layer1.srs differ

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/layer1.tlg b/gbe/cores/sgmii/PCSD/syn_results/synwork/layer1.tlg
new file mode 100644 (file)
index 0000000..52e3197
--- /dev/null
+++ b/gbe/cores/sgmii/PCSD/syn_results/synwork/layer1.tlg
@@ -0,0 +1,96 @@
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":92:7:92:18|Synthesizing module PCSDrsl_core in library work.
+
+       pnum_channels=32'b00000000000000000000000000000001
+       pprotocol=24'b010001110100001001000101
+       pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
+       pport_tx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100
+       pwait_tx_rdy=32'b00000000000000000000101110111000
+       pport_rx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100
+       pwait_rx_rdy=32'b00000000000000000000101110111000
+       wa_num_cycles=32'b00000000000000000000010000000000
+       dac_num_cycles=32'b00000000000000000000000000000011
+       lreset_pwidth=32'b00000000000000000000000000000011
+       lwait_b4_trst=32'b00000000000010111110101111000010
+       lwait_b4_trst_s=32'b00000000000000000000001100001101
+       lplol_cnt_width=32'b00000000000000000000000000010100
+       lwait_after_plol0=32'b00000000000000000000000000000100
+       lwait_b4_rrst=32'b00000000000000101100000000000000
+       lrrst_wait_width=32'b00000000000000000000000000010100
+       lwait_after_rrst=32'b00000000000011000011010100000000
+       lwait_b4_rrst_s=32'b00000000000000000000000111001100
+       lrlol_cnt_width=32'b00000000000000000000000000010011
+       lwait_after_lols=32'b00000000000000001100010000000000
+       lwait_after_lols_s=32'b00000000000000000000000010010110
+       llols_cnt_width=32'b00000000000000000000000000010010
+       lrdb_max=32'b00000000000000000000000000001111
+       ltxr_wait_width=32'b00000000000000000000000000001100
+       lrxr_wait_width=32'b00000000000000000000000000001100
+   Generated name = PCSDrsl_core_Z1_layer1
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":274:33:274:48|Removing wire dual_or_serd_rst, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":275:33:275:46|Removing wire tx_any_pcs_rst, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":276:33:276:42|Removing wire tx_any_rst, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":277:33:277:41|Object txsr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":278:33:278:42|Object txdpr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":279:33:279:41|Object txpr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":280:33:280:41|Object txr_wt_en is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":281:33:281:42|Object txr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":282:33:282:41|Removing wire txr_wt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":283:33:283:43|Object ruo_tx_rdyr is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":356:33:356:41|Object rxsr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":357:33:357:41|Object rxpr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":358:33:358:42|Object rxsdr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":359:33:359:42|Object rxdpr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":360:33:360:48|Removing wire rxsdr_or_sr_appd, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":361:33:361:49|Removing wire dual_or_rserd_rst, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":362:33:362:46|Removing wire rx_any_pcs_rst, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":363:33:363:42|Removing wire rx_any_rst, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":364:33:364:41|Object rxr_wt_en is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":365:33:365:42|Object rxr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":366:33:366:41|Removing wire rxr_wt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":367:33:367:43|Object ruo_rx_rdyr is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":507:10:507:10|Object m is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":880:10:880:10|Object l is declared but not assigned. Either assign a value or remove the declaration.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/PCSD/PCSD_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/layer1.tlg.db b/gbe/cores/sgmii/PCSD/syn_results/synwork/layer1.tlg.db
new file mode 100644 (file)
index 0000000..88572b9
Binary files /dev/null and b/gbe/cores/sgmii/PCSD/syn_results/synwork/layer1.tlg.db differ

diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/modulechange.db b/gbe/cores/sgmii/PCSD/syn_results/synwork/modulechange.db
new file mode 100644 (file)
index 0000000..52e085b
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diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/modulechange_mixhdl/layer0/modulechange.db b/gbe/cores/sgmii/PCSD/syn_results/synwork/modulechange_mixhdl/layer0/modulechange.db
new file mode 100644 (file)
index 0000000..e272838
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diff --git a/gbe/cores/sgmii/PCSD/syn_results/synwork/modulechange_mixhdl/layer1/modulechange.db b/gbe/cores/sgmii/PCSD/syn_results/synwork/modulechange_mixhdl/layer1/modulechange.db
new file mode 100644 (file)
index 0000000..0bd78ff
Binary files /dev/null and b/gbe/cores/sgmii/PCSD/syn_results/synwork/modulechange_mixhdl/layer1/modulechange.db differ

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.cmd b/gbe/cores/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.cmd
new file mode 100644 (file)
index 0000000..ac77ef0
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.cmd
@@ -0,0 +1,18 @@
+PROJECT: pll_in125_out125_out33
+               working_path: "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results"
+               module: pll_in125_out125_out33
+               verilog_file_list: "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd"
+               vlog_std_v2001: true
+               constraint_file_name: "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc"
+               suffix_name: edn
+               output_file_name: pll_in125_out125_out33
+               write_prf: true
+               disable_io_insertion: true
+               force_gsr: false
+               frequency: 100
+               fanout_limit: 50
+               retiming: false
+               pipe: false
+               part: LFE5UM-85F
+               speed_grade: 8
+               

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.cst b/gbe/cores/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.cst
new file mode 100644 (file)
index 0000000..20b51c3
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.cst
@@ -0,0 +1,3 @@
+Date=05/10/2019
+Time=15:07:09
+

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc b/gbe/cores/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc
new file mode 100644 (file)
index 0000000..6fbcac9
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc
@@ -0,0 +1,2 @@
+###==== Start Configuration
+

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.lpc b/gbe/cores/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.lpc
new file mode 100644 (file)
index 0000000..8d42cb1
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.lpc
@@ -0,0 +1,93 @@
+[Device]
+Family=ecp5um
+PartType=LFE5UM-85F
+PartName=LFE5UM-85F-8BG756C
+SpeedGrade=8
+Package=CABGA756
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.8
+ModuleName=pll_in125_out125_out33
+SourceFormat=vhdl
+ParameterFileVersion=1.0
+Date=05/10/2019
+Time=15:07:09
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+CLKI_FREQ=125
+CLKI_DIV=15
+ENABLE_HBW=DISABLED
+REFERENCE=0
+IOBUF=LVDS
+CLKOP_FREQ=125
+CLKOP_TOL=0.0
+CLKOP_DIV=1
+CLKOP_ACTUAL_FREQ=125.000000
+CLKOP_MUXA=ENABLED
+CLKOS_Enable=ENABLED
+CLKOS_FREQ=33.3333333333
+CLKOS_TOL=0.1
+CLKOS_DIV=18
+CLKOS_ACTUAL_FREQ=33.333333
+CLKOS_MUXB=DISABLED
+CLKOS2_Enable=DISABLED
+CLKOS2_FREQ=100.00
+CLKOS2_TOL=0.0
+CLKOS2_DIV=1
+CLKOS2_ACTUAL_FREQ=
+CLKOS2_MUXC=DISABLED
+CLKOS3_Enable=DISABLED
+CLKOS3_FREQ=100.00
+CLKOS3_TOL=0.0
+CLKOS3_DIV=1
+CLKOS3_ACTUAL_FREQ=
+CLKOS3_MUXD=DISABLED
+FEEDBK_PATH=INT_OS
+CLKFB_DIV=4
+FRACN_ENABLE=DISABLED
+FRACN_DIV=
+VCO_RATE=600.000
+PLL_BW=0.955
+CLKOP_DPHASE=0
+CLKOP_APHASE=0.00
+CLKOP_TRIM_POL=Rising
+CLKOP_TRIM_DELAY=0
+CLKOS_DPHASE=0
+CLKOS_APHASE=0.00
+CLKOS_TRIM_POL=Rising
+CLKOS_TRIM_DELAY=0
+CLKOS2_DPHASE=0
+CLKOS2_APHASE=0.00
+CLKOS2_TRIM_POL=Rising
+CLKOS2_TRIM_DELAY=0
+CLKOS3_DPHASE=0
+CLKOS3_APHASE=0.00
+CLKOS3_TRIM_POL=Rising
+CLKOS3_TRIM_DELAY=0
+CLKSEL_ENA=DISABLED
+DPHASE_SOURCE=STATIC
+ENABLE_CLKOP=DISABLED
+ENABLE_CLKOS=DISABLED
+ENABLE_CLKOS2=DISABLED
+ENABLE_CLKOS3=DISABLED
+STDBY_ENABLE=DISABLED
+PLLRST_ENA=DISABLED
+PLL_LOCK_MODE=ENABLED
+PLL_LOCK_STK=DISABLED
+PLL_USE_SMI=DISABLED
+
+[Command]
+cmd_line= -w -n pll_in125_out125_out33 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 125 -bypassp -fclkos 33.3333333333 -fclkos_tol 0.1 -phase_cntl STATIC -lock -fb_mode 6

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.ngd b/gbe/cores/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.ngd
new file mode 100644 (file)
index 0000000..60a2e0c
Binary files /dev/null and b/gbe/cores/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.ngd differ

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.ngo b/gbe/cores/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.ngo
new file mode 100644 (file)
index 0000000..06d355e
Binary files /dev/null and b/gbe/cores/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.ngo differ

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd b/gbe/cores/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd
new file mode 100644 (file)
index 0000000..74d2eff
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd
@@ -0,0 +1,77 @@
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.3.144
+-- Module  Version: 5.7
+--/home/soft/lattice/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n pll_in125_out125_out33 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 125 -bypassp -fclkos 33.3333333333 -fclkos_tol 0.1 -phase_cntl STATIC -lock -fb_mode 6 -fdc /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc 
+
+-- Fri May 10 15:07:24 2019
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity pll_in125_out125_out33 is
+    port (
+        CLKI: in  std_logic; 
+        CLKOP: out  std_logic; 
+        CLKOS: out  std_logic; 
+        LOCK: out  std_logic);
+end pll_in125_out125_out33;
+
+architecture Structure of pll_in125_out125_out33 is
+
+    -- internal signal declarations
+    signal REFCLK: std_logic;
+    signal CLKOS_t: std_logic;
+    signal CLKOP_t: std_logic;
+    signal CLKFB_t: std_logic;
+    signal scuba_vhi: std_logic;
+    signal scuba_vlo: std_logic;
+
+    attribute FREQUENCY_PIN_CLKOS : string; 
+    attribute FREQUENCY_PIN_CLKOP : string; 
+    attribute FREQUENCY_PIN_CLKI : string; 
+    attribute ICP_CURRENT : string; 
+    attribute LPF_RESISTOR : string; 
+    attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "33.333333";
+    attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "125.000000";
+    attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "125.000000";
+    attribute ICP_CURRENT of PLLInst_0 : label is "5";
+    attribute LPF_RESISTOR of PLLInst_0 : label is "16";
+    attribute syn_keep : boolean;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    PLLInst_0: EHXPLLL
+        generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", 
+        STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", 
+        CLKOS3_FPHASE=>  0, CLKOS3_CPHASE=>  0, CLKOS2_FPHASE=>  0, 
+        CLKOS2_CPHASE=>  0, CLKOS_FPHASE=>  0, CLKOS_CPHASE=>  17, 
+        CLKOP_FPHASE=>  0, CLKOP_CPHASE=>  0, PLL_LOCK_MODE=>  0, 
+        CLKOS_TRIM_DELAY=>  0, CLKOS_TRIM_POL=> "FALLING", 
+        CLKOP_TRIM_DELAY=>  0, CLKOP_TRIM_POL=> "FALLING", 
+        OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED", 
+        OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED", 
+        OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "ENABLED", 
+        OUTDIVIDER_MUXA=> "REFCLK", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=>  1, 
+        CLKOS2_DIV=>  1, CLKOS_DIV=>  18, CLKOP_DIV=>  1, CLKFB_DIV=>  4, 
+        CLKI_DIV=>  15, FEEDBK_PATH=> "INT_OS")
+        port map (CLKI=>CLKI, CLKFB=>CLKFB_t, PHASESEL1=>scuba_vlo, 
+            PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, 
+            PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo, 
+            STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, 
+            ENCLKOP=>scuba_vlo, ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, 
+            ENCLKOS3=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t, 
+            CLKOS2=>open, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open, 
+            REFCLK=>REFCLK, CLKINTFB=>CLKFB_t);
+
+    CLKOS <= CLKOS_t;
+    CLKOP <= CLKOP_t;
+end Structure;

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/pll_in125_out125_out33_ngd.asd b/gbe/cores/sgmii/pll_in125_out125_out33/pll_in125_out125_out33_ngd.asd
new file mode 100644 (file)
index 0000000..c265c78
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/pll_in125_out125_out33_ngd.asd
@@ -0,0 +1 @@
+[ActiveSupport NGD]

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/.recordref b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/.recordref
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/_CMD_.CML b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/_CMD_.CML
new file mode 100644 (file)
index 0000000..3410943
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/_CMD_.CML
@@ -0,0 +1 @@
+ -osyn  /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_comp.srs  -top  pll_in125_out125_out33  -hdllog  /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_compiler.srr  -encrypt  -mp  4  -verification_mode 0  -vhdl  -prodtype  synplify_pro  -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver  -encrypt  -pro  -dmgen  /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/dm  -lite -ui -fid2 -ram -sharing on -ll 2000 -autosm  -ignore_undefined_lib  -lib work /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd  -jobname  "compiler" 
\ No newline at end of file

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/_cmd._cml b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/_cmd._cml
new file mode 100644 (file)
index 0000000..63c1e88
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/_cmd._cml
@@ -0,0 +1 @@
+-link    -encrypt        -top pll_in125_out125_out33 -osyn /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_comp.srs /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/layer0.srs   
\ No newline at end of file

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/backup/pll_in125_out125_out33.srr b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/backup/pll_in125_out125_out33.srr
new file mode 100644 (file)
index 0000000..febff8d
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/backup/pll_in125_out125_out33.srr
@@ -0,0 +1,403 @@
+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
+#install: /home/soft/lattice/diamond/3.10_x64/synpbase
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Thu May  9 10:42:24 2019
+
+#Implementation: syn_results
+
+Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":12:7:12:28|Top entity is set to pll_in125_out125_out33.
+VHDL syntax check successful!
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":12:7:12:28|Synthesizing work.pll_in125_out125_out33.structure.
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2083:10:2083:16|Synthesizing ecp5um.ehxplll.syn_black_box.
+Post processing for ecp5um.ehxplll.syn_black_box
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":832:10:832:12|Synthesizing ecp5um.vlo.syn_black_box.
+Post processing for ecp5um.vlo.syn_black_box
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":825:10:825:12|Synthesizing ecp5um.vhi.syn_black_box.
+Post processing for ecp5um.vhi.syn_black_box
+Post processing for work.pll_in125_out125_out33.structure
+@W: CL168 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":45:4:45:17|Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Thu May  9 10:42:24 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Thu May  9 10:42:24 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Thu May  9 10:42:24 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Thu May  9 10:42:26 2019
+
+###########################################################]
+Pre-mapping Report
+
+# Thu May  9 10:42:26 2019
+
+Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc
+@L: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_scck.rpt 
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_scck.rpt" file 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB)
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist pll_in125_out125_out33
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+
+Clock Summary
+******************
+
+          Start      Requested     Requested     Clock      Clock               Clock
+Level     Clock      Frequency     Period        Type       Group               Load 
+-------------------------------------------------------------------------------------
+0 -       System     100.0 MHz     10.000        system     system_clkgroup     0    
+=====================================================================================
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 143MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Thu May  9 10:42:26 2019
+
+###########################################################]
+Map & Optimize Report
+
+# Thu May  9 10:42:26 2019
+
+Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.edn
+M-2017.03L-SP1-1
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
+
+@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":51:4:51:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Thu May  9 10:42:29 2019
+#
+
+
+Top view:               pll_in125_out125_out33
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 10.000
+
+@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
+                   Requested     Estimated     Requested     Estimated                Clock      Clock          
+Starting Clock     Frequency     Frequency     Period        Period        Slack      Type       Group          
+----------------------------------------------------------------------------------------------------------------
+System             100.0 MHz     NA            10.000        0.000         10.000     system     system_clkgroup
+================================================================================================================
+Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks            |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+---------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
+---------------------------------------------------------------------------------------------------------
+System    System  |  10.000      10.000  |  No paths    -      |  No paths    -      |  No paths    -    
+=========================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                      Arrival           
+Instance      Reference     Type        Pin       Net       Time        Slack 
+              Clock                                                           
+------------------------------------------------------------------------------
+PLLInst_0     System        EHXPLLL     CLKOP     CLKOP     0.000       10.000
+==============================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+              Starting                                      Required           
+Instance      Reference     Type        Pin       Net       Time         Slack 
+              Clock                                                            
+-------------------------------------------------------------------------------
+PLLInst_0     System        EHXPLLL     CLKFB     CLKOP     10.000       10.000
+===============================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.000
+    + Clock delay at ending point:           0.000 (ideal)
+    + Estimated clock delay at ending point: 0.000
+    = Required time:                         10.000
+
+    - Propagation time:                      0.000
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (critical) :                     10.000
+
+    Number of logic level(s):                0
+    Starting point:                          PLLInst_0 / CLKOP
+    Ending point:                            PLLInst_0 / CLKFB
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            System [rising]
+
+Instance / Net                 Pin       Pin               Arrival     No. of    
+Name               Type        Name      Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------
+PLLInst_0          EHXPLLL     CLKOP     Out     0.000     0.000       -         
+CLKOP              Net         -         -       -         -           2         
+PLLInst_0          EHXPLLL     CLKFB     In      0.000     0.000       -         
+=================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 0 of 24288 (0%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+EHXPLLL:        1
+GSR:            1
+PUR:            1
+VHI:            1
+VLO:            1
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 146MB)
+
+Process took 0h:00m:02s realtime, 0h:00m:02s cputime
+# Thu May  9 10:42:29 2019
+
+###########################################################]

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/dm/layer0.xdm b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/dm/layer0.xdm
new file mode 100644 (file)
index 0000000..d3eb144
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/dm/layer0.xdm
@@ -0,0 +1,164 @@
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+

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.areasrr b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.areasrr
new file mode 100644 (file)
index 0000000..5d28e26
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.areasrr
@@ -0,0 +1,15 @@
+----------------------------------------------------------------------
+Report for cell pll_in125_out125_out33.structure
+
+Register bits: 0 of 24288 (0%)
+PIC Latch:       0
+I/O cells:       0
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                            EHXPLLL        1       100.0
+                                GSR        1       100.0
+                                PUR        1       100.0
+                                VHI        1       100.0
+                                VLO        1       100.0
+                            
+                         TOTAL             5           

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.fse b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.fse
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.htm b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.htm
new file mode 100644 (file)
index 0000000..43c5f13
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.htm
@@ -0,0 +1,9 @@
+<html>
+ <head>
+ <title>syntmp/pll_in125_out125_out33_srr.htm log file</title>
+ </head>
+ <frameset cols="20%, 80%">
+ <frame src="syntmp/pll_in125_out125_out33_toc.htm" name="tocFrame" />
+                                <frame src="syntmp/pll_in125_out125_out33_srr.htm" name="srrFrame"/>
+</frameset>
+ </html>

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.prj b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.prj
new file mode 100644 (file)
index 0000000..133a2cb
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.prj
@@ -0,0 +1,46 @@
+#-- Lattice Semiconductor Corporation Ltd.
+#-- Synplify OEM project file /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.prj
+#-- Written on Fri May 10 15:07:25 2019
+
+
+#device options
+set_option -technology ecp5um
+set_option -part LFE5UM-85F
+set_option -speed_grade 8
+
+#use verilog 2001 standard option
+set_option -vlog_std v2001
+
+#map options
+set_option -frequency 100
+set_option -fanout_limit 50
+set_option -disable_io_insertion true
+set_option -retiming false
+set_option -pipe false
+set_option -pipe false
+set_option -force_gsr false
+
+#simulation options
+set_option -write_verilog true
+set_option -write_vhdl true
+
+#timing analysis options
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#-- add_file options
+add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd"
+add_file -constraint {"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc"}
+
+#-- top module name
+set_option -top_module pll_in125_out125_out33
+
+#-- set result format/file last
+project -result_file "pll_in125_out125_out33.edn"
+
+#-- error message log file
+project -log_file pll_in125_out125_out33.srf
+
+#-- run Synplify with 'arrange VHDL file'
+project -run

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.srd b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.srd
new file mode 100644 (file)
index 0000000..d5fd4e6
Binary files /dev/null and b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.srd differ

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.srf b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.srf
new file mode 100644 (file)
index 0000000..2ad892a
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.srf
@@ -0,0 +1,404 @@
+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
+#install: /home/soft/lattice/diamond/3.10_x64/synpbase
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Fri May 10 15:07:25 2019
+
+#Implementation: syn_results
+
+Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":12:7:12:28|Top entity is set to pll_in125_out125_out33.
+File /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd changed - recompiling
+File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling
+VHDL syntax check successful!
+File /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd changed - recompiling
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":12:7:12:28|Synthesizing work.pll_in125_out125_out33.structure.
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2083:10:2083:16|Synthesizing ecp5um.ehxplll.syn_black_box.
+Post processing for ecp5um.ehxplll.syn_black_box
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":832:10:832:12|Synthesizing ecp5um.vlo.syn_black_box.
+Post processing for ecp5um.vlo.syn_black_box
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":825:10:825:12|Synthesizing ecp5um.vhi.syn_black_box.
+Post processing for ecp5um.vhi.syn_black_box
+Post processing for work.pll_in125_out125_out33.structure
+@W: CL168 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":46:4:46:17|Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 15:07:25 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+File /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/layer0.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 15:07:26 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 15:07:26 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+File /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 15:07:27 2019
+
+###########################################################]
+# Fri May 10 15:07:27 2019
+
+Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc
+@L: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_scck.rpt 
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_scck.rpt" file 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB)
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist pll_in125_out125_out33
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+
+Clock Summary
+******************
+
+          Start      Requested     Requested     Clock      Clock               Clock
+Level     Clock      Frequency     Period        Type       Group               Load 
+-------------------------------------------------------------------------------------
+0 -       System     100.0 MHz     10.000        system     system_clkgroup     0    
+=====================================================================================
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 143MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Fri May 10 15:07:28 2019
+
+###########################################################]
+# Fri May 10 15:07:28 2019
+
+Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.edn
+M-2017.03L-SP1-1
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
+
+@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":52:4:52:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Fri May 10 15:07:30 2019
+#
+
+
+Top view:               pll_in125_out125_out33
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 10.000
+
+@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
+                   Requested     Estimated     Requested     Estimated                Clock      Clock          
+Starting Clock     Frequency     Frequency     Period        Period        Slack      Type       Group          
+----------------------------------------------------------------------------------------------------------------
+System             100.0 MHz     NA            10.000        0.000         10.000     system     system_clkgroup
+================================================================================================================
+Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks            |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+---------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
+---------------------------------------------------------------------------------------------------------
+System    System  |  10.000      10.000  |  No paths    -      |  No paths    -      |  No paths    -    
+=========================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                           Arrival           
+Instance      Reference     Type        Pin          Net         Time        Slack 
+              Clock                                                                
+-----------------------------------------------------------------------------------
+PLLInst_0     System        EHXPLLL     CLKINTFB     CLKFB_t     0.000       10.000
+===================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+              Starting                                        Required           
+Instance      Reference     Type        Pin       Net         Time         Slack 
+              Clock                                                              
+---------------------------------------------------------------------------------
+PLLInst_0     System        EHXPLLL     CLKFB     CLKFB_t     10.000       10.000
+=================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.000
+    + Clock delay at ending point:           0.000 (ideal)
+    + Estimated clock delay at ending point: 0.000
+    = Required time:                         10.000
+
+    - Propagation time:                      0.000
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (critical) :                     10.000
+
+    Number of logic level(s):                0
+    Starting point:                          PLLInst_0 / CLKINTFB
+    Ending point:                            PLLInst_0 / CLKFB
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            System [rising]
+
+Instance / Net                 Pin          Pin               Arrival     No. of    
+Name               Type        Name         Dir     Delay     Time        Fan Out(s)
+------------------------------------------------------------------------------------
+PLLInst_0          EHXPLLL     CLKINTFB     Out     0.000     0.000       -         
+CLKFB_t            Net         -            -       -         -           1         
+PLLInst_0          EHXPLLL     CLKFB        In      0.000     0.000       -         
+====================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 0 of 24288 (0%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+EHXPLLL:        1
+GSR:            1
+PUR:            1
+VHI:            1
+VLO:            1
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 146MB)
+
+Process took 0h:00m:02s realtime, 0h:00m:02s cputime
+# Fri May 10 15:07:30 2019
+
+###########################################################]

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.srm b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.srm
new file mode 100644 (file)
index 0000000..15fc0b0
Binary files /dev/null and b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.srm differ

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.srr b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.srr
new file mode 100644 (file)
index 0000000..2ad892a
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.srr
@@ -0,0 +1,404 @@
+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
+#install: /home/soft/lattice/diamond/3.10_x64/synpbase
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Fri May 10 15:07:25 2019
+
+#Implementation: syn_results
+
+Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":12:7:12:28|Top entity is set to pll_in125_out125_out33.
+File /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd changed - recompiling
+File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling
+VHDL syntax check successful!
+File /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd changed - recompiling
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":12:7:12:28|Synthesizing work.pll_in125_out125_out33.structure.
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2083:10:2083:16|Synthesizing ecp5um.ehxplll.syn_black_box.
+Post processing for ecp5um.ehxplll.syn_black_box
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":832:10:832:12|Synthesizing ecp5um.vlo.syn_black_box.
+Post processing for ecp5um.vlo.syn_black_box
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":825:10:825:12|Synthesizing ecp5um.vhi.syn_black_box.
+Post processing for ecp5um.vhi.syn_black_box
+Post processing for work.pll_in125_out125_out33.structure
+@W: CL168 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":46:4:46:17|Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 15:07:25 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+File /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/layer0.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 15:07:26 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 15:07:26 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+File /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 15:07:27 2019
+
+###########################################################]
+# Fri May 10 15:07:27 2019
+
+Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc
+@L: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_scck.rpt 
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_scck.rpt" file 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB)
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist pll_in125_out125_out33
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+
+Clock Summary
+******************
+
+          Start      Requested     Requested     Clock      Clock               Clock
+Level     Clock      Frequency     Period        Type       Group               Load 
+-------------------------------------------------------------------------------------
+0 -       System     100.0 MHz     10.000        system     system_clkgroup     0    
+=====================================================================================
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 143MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Fri May 10 15:07:28 2019
+
+###########################################################]
+# Fri May 10 15:07:28 2019
+
+Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.edn
+M-2017.03L-SP1-1
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
+
+@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":52:4:52:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Fri May 10 15:07:30 2019
+#
+
+
+Top view:               pll_in125_out125_out33
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 10.000
+
+@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
+                   Requested     Estimated     Requested     Estimated                Clock      Clock          
+Starting Clock     Frequency     Frequency     Period        Period        Slack      Type       Group          
+----------------------------------------------------------------------------------------------------------------
+System             100.0 MHz     NA            10.000        0.000         10.000     system     system_clkgroup
+================================================================================================================
+Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks            |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+---------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
+---------------------------------------------------------------------------------------------------------
+System    System  |  10.000      10.000  |  No paths    -      |  No paths    -      |  No paths    -    
+=========================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                           Arrival           
+Instance      Reference     Type        Pin          Net         Time        Slack 
+              Clock                                                                
+-----------------------------------------------------------------------------------
+PLLInst_0     System        EHXPLLL     CLKINTFB     CLKFB_t     0.000       10.000
+===================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+              Starting                                        Required           
+Instance      Reference     Type        Pin       Net         Time         Slack 
+              Clock                                                              
+---------------------------------------------------------------------------------
+PLLInst_0     System        EHXPLLL     CLKFB     CLKFB_t     10.000       10.000
+=================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.000
+    + Clock delay at ending point:           0.000 (ideal)
+    + Estimated clock delay at ending point: 0.000
+    = Required time:                         10.000
+
+    - Propagation time:                      0.000
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (critical) :                     10.000
+
+    Number of logic level(s):                0
+    Starting point:                          PLLInst_0 / CLKINTFB
+    Ending point:                            PLLInst_0 / CLKFB
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            System [rising]
+
+Instance / Net                 Pin          Pin               Arrival     No. of    
+Name               Type        Name         Dir     Delay     Time        Fan Out(s)
+------------------------------------------------------------------------------------
+PLLInst_0          EHXPLLL     CLKINTFB     Out     0.000     0.000       -         
+CLKFB_t            Net         -            -       -         -           1         
+PLLInst_0          EHXPLLL     CLKFB        In      0.000     0.000       -         
+====================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 0 of 24288 (0%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+EHXPLLL:        1
+GSR:            1
+PUR:            1
+VHI:            1
+VLO:            1
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 146MB)
+
+Process took 0h:00m:02s realtime, 0h:00m:02s cputime
+# Fri May 10 15:07:30 2019
+
+###########################################################]

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.srr.db b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.srr.db
new file mode 100644 (file)
index 0000000..5279189
Binary files /dev/null and b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.srr.db differ

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.srs b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.srs
new file mode 100644 (file)
index 0000000..1303ca7
Binary files /dev/null and b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.srs differ

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.vhm b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.vhm
new file mode 100644 (file)
index 0000000..57f03c8
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.vhm
@@ -0,0 +1,108 @@
+--
+-- Written by Synplicity
+-- Product Version "M-2017.03L-SP1-1"
+-- Program "Synplify Pro", Mapper "maplat, Build 1796R"
+-- Fri May 10 15:07:29 2019
+--
+
+--
+-- Written by Synplify Pro version Build 1796R
+-- Fri May 10 15:07:29 2019
+--
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library synplify;
+use synplify.components.all;
+library pmi;
+use pmi.pmi_components.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity pll_in125_out125_out33 is
+port(
+  CLKI :  in std_logic;
+  CLKOP :  out std_logic;
+  CLKOS :  out std_logic;
+  LOCK :  out std_logic);
+end pll_in125_out125_out33;
+
+architecture beh of pll_in125_out125_out33 is
+  signal CLKOS2 : std_logic ;
+  signal CLKOS3 : std_logic ;
+  signal INTLOCK : std_logic ;
+  signal CLKFB_T : std_logic ;
+  signal REFCLK : std_logic ;
+  signal GND : std_logic ;
+  signal VCC : std_logic ;
+begin
+GND_0: VLO port map (
+    Z => GND);
+VCC_0: VHI port map (
+    Z => VCC);
+PUR_INST: PUR port map (
+    PUR => VCC);
+GSR_INST: GSR port map (
+    GSR => VCC);
+PLLINST_0: EHXPLLL 
+  generic map( 
+    CLKI_DIV => 15, 
+    CLKFB_DIV => 4, 
+    CLKOP_DIV => 1, 
+    CLKOS_DIV => 18, 
+    CLKOS2_DIV => 1, 
+    CLKOS3_DIV => 1, 
+    CLKOP_ENABLE => "ENABLED", 
+    CLKOS_ENABLE => "ENABLED", 
+    CLKOS2_ENABLE => "DISABLED", 
+    CLKOS3_ENABLE => "DISABLED", 
+    CLKOP_CPHASE => 0, 
+    CLKOS_CPHASE => 17, 
+    CLKOS2_CPHASE => 0, 
+    CLKOS3_CPHASE => 0, 
+    CLKOP_FPHASE => 0, 
+    CLKOS_FPHASE => 0, 
+    CLKOS2_FPHASE => 0, 
+    CLKOS3_FPHASE => 0, 
+    FEEDBK_PATH => "INT_OS", 
+    CLKOP_TRIM_POL => "FALLING", 
+    CLKOP_TRIM_DELAY => 0, 
+    CLKOS_TRIM_POL => "FALLING", 
+    CLKOS_TRIM_DELAY => 0, 
+    OUTDIVIDER_MUXA => "REFCLK", 
+    OUTDIVIDER_MUXB => "DIVB", 
+    OUTDIVIDER_MUXC => "DIVC", 
+    OUTDIVIDER_MUXD => "DIVD", 
+    PLL_LOCK_MODE => 0, 
+    STDBY_ENABLE => "DISABLED", 
+    DPHASE_SOURCE => "DISABLED", 
+    PLLRST_ENA => "DISABLED", 
+    INTFB_WAKE => "DISABLED"
+  ) 
+  port map (
+    CLKI => CLKI,
+    CLKFB => CLKFB_T,
+    PHASESEL1 => GND,
+    PHASESEL0 => GND,
+    PHASEDIR => GND,
+    PHASESTEP => GND,
+    PHASELOADREG => GND,
+    STDBY => GND,
+    PLLWAKESYNC => GND,
+    RST => GND,
+    ENCLKOP => GND,
+    ENCLKOS => GND,
+    ENCLKOS2 => GND,
+    ENCLKOS3 => GND,
+    CLKOP => CLKOP,
+    CLKOS => CLKOS,
+    CLKOS2 => CLKOS2,
+    CLKOS3 => CLKOS3,
+    LOCK => LOCK,
+    INTLOCK => INTLOCK,
+    REFCLK => REFCLK,
+    CLKINTFB => CLKFB_T);
+end beh;
+

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.vm b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.vm
new file mode 100644 (file)
index 0000000..653411d
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.vm
@@ -0,0 +1,115 @@
+//
+// Written by Synplify Pro 
+// Product Version "M-2017.03L-SP1-1"
+// Program "Synplify Pro", Mapper "maplat, Build 1796R"
+// Fri May 10 15:07:29 2019
+//
+// Source file index table:
+// Object locations will have the form <file>:<line>
+// file 0 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd "
+// file 1 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd "
+// file 2 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd "
+// file 3 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd "
+// file 4 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd "
+// file 5 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd "
+// file 6 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd "
+// file 7 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd "
+// file 8 "\/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd "
+// file 9 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd "
+// file 10 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/nlconst.dat "
+// file 11 "\/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc "
+
+`timescale 100 ps/100 ps
+(* NGD_DRC_MASK=1 *)module pll_in125_out125_out33 (
+  CLKI,
+  CLKOP,
+  CLKOS,
+  LOCK
+)
+;
+input CLKI ;
+output CLKOP ;
+output CLKOS ;
+output LOCK ;
+wire CLKI ;
+wire CLKOP ;
+wire CLKOS ;
+wire LOCK ;
+wire CLKOS2 ;
+wire CLKOS3 ;
+wire INTLOCK ;
+wire CLKFB_t ;
+wire REFCLK ;
+wire GND ;
+wire VCC ;
+  VLO GND_0 (
+       .Z(GND)
+);
+  VHI VCC_0 (
+       .Z(VCC)
+);
+  PUR PUR_INST (
+       .PUR(VCC)
+);
+  GSR GSR_INST (
+       .GSR(VCC)
+);
+// @8:52
+(* LPF_RESISTOR="16" , ICP_CURRENT="5" , FREQUENCY_PIN_CLKI="125.000000" , FREQUENCY_PIN_CLKOP="125.000000" , FREQUENCY_PIN_CLKOS="33.333333" *)  EHXPLLL PLLInst_0 (
+       .CLKI(CLKI),
+       .CLKFB(CLKFB_t),
+       .PHASESEL1(GND),
+       .PHASESEL0(GND),
+       .PHASEDIR(GND),
+       .PHASESTEP(GND),
+       .PHASELOADREG(GND),
+       .STDBY(GND),
+       .PLLWAKESYNC(GND),
+       .RST(GND),
+       .ENCLKOP(GND),
+       .ENCLKOS(GND),
+       .ENCLKOS2(GND),
+       .ENCLKOS3(GND),
+       .CLKOP(CLKOP),
+       .CLKOS(CLKOS),
+       .CLKOS2(CLKOS2),
+       .CLKOS3(CLKOS3),
+       .LOCK(LOCK),
+       .INTLOCK(INTLOCK),
+       .REFCLK(REFCLK),
+       .CLKINTFB(CLKFB_t)
+);
+defparam PLLInst_0.CLKI_DIV = 15;
+defparam PLLInst_0.CLKFB_DIV = 4;
+defparam PLLInst_0.CLKOP_DIV = 1;
+defparam PLLInst_0.CLKOS_DIV = 18;
+defparam PLLInst_0.CLKOS2_DIV = 1;
+defparam PLLInst_0.CLKOS3_DIV = 1;
+defparam PLLInst_0.CLKOP_ENABLE = "ENABLED";
+defparam PLLInst_0.CLKOS_ENABLE = "ENABLED";
+defparam PLLInst_0.CLKOS2_ENABLE = "DISABLED";
+defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED";
+defparam PLLInst_0.CLKOP_CPHASE = 0;
+defparam PLLInst_0.CLKOS_CPHASE = 17;
+defparam PLLInst_0.CLKOS2_CPHASE = 0;
+defparam PLLInst_0.CLKOS3_CPHASE = 0;
+defparam PLLInst_0.CLKOP_FPHASE = 0;
+defparam PLLInst_0.CLKOS_FPHASE = 0;
+defparam PLLInst_0.CLKOS2_FPHASE = 0;
+defparam PLLInst_0.CLKOS3_FPHASE = 0;
+defparam PLLInst_0.FEEDBK_PATH = "INT_OS";
+defparam PLLInst_0.CLKOP_TRIM_POL = "FALLING";
+defparam PLLInst_0.CLKOP_TRIM_DELAY = 0;
+defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING";
+defparam PLLInst_0.CLKOS_TRIM_DELAY = 0;
+defparam PLLInst_0.OUTDIVIDER_MUXA = "REFCLK";
+defparam PLLInst_0.OUTDIVIDER_MUXB = "DIVB";
+defparam PLLInst_0.OUTDIVIDER_MUXC = "DIVC";
+defparam PLLInst_0.OUTDIVIDER_MUXD = "DIVD";
+defparam PLLInst_0.PLL_LOCK_MODE = 0;
+defparam PLLInst_0.STDBY_ENABLE = "DISABLED";
+defparam PLLInst_0.DPHASE_SOURCE = "DISABLED";
+defparam PLLInst_0.PLLRST_ENA = "DISABLED";
+defparam PLLInst_0.INTFB_WAKE = "DISABLED";
+endmodule /* pll_in125_out125_out33 */
+

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_cck.rpt.db b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_cck.rpt.db
new file mode 100644 (file)
index 0000000..029fa7a
Binary files /dev/null and b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_cck.rpt.db differ

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_scck.rpt.db b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_scck.rpt.db
new file mode 100644 (file)
index 0000000..029fa7a
Binary files /dev/null and b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_scck.rpt.db differ

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_synplify.lpf b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_synplify.lpf
new file mode 100644 (file)
index 0000000..8e445e1
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_synplify.lpf
@@ -0,0 +1,20 @@
+#
+# Logical Preferences generated for Lattice by Synplify maplat, Build 1796R.
+#
+
+# Period Constraints 
+
+
+# Output Constraints 
+
+# Input Constraints 
+
+# Point-to-point Delay Constraints 
+
+
+
+# Block Path Constraints 
+
+BLOCK ASYNCPATHS;
+
+# End of generated Logical Preferences.

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_synplify_tmp2.lpf b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_synplify_tmp2.lpf
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_synplify_tmp4.lpf b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_synplify_tmp4.lpf
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_synplify_tmp8.lpf b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_synplify_tmp8.lpf
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/run_options.txt b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/run_options.txt
new file mode 100644 (file)
index 0000000..b19e59a
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/run_options.txt
@@ -0,0 +1,75 @@
+#--  Synopsys, Inc.
+#--  Version M-2017.03L-SP1-1
+#--  Project file /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/run_options.txt
+#--  Written on Fri May 10 15:07:25 2019
+
+
+#project files
+add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd"
+add_file -fpga_constraint "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc"
+
+
+
+#implementation: "syn_results"
+impl -add syn_results -type fpga
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+
+#device options
+set_option -technology ecp5um
+set_option -part LFE5UM_25F
+set_option -package MG285C
+set_option -speed_grade -6
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -top_module "pll_in125_out125_out33"
+
+# hdl_compiler_options
+set_option -distributed_compile 0
+
+# mapper_without_write_options
+set_option -frequency 100
+set_option -srs_instrumentation 1
+
+# mapper_options
+set_option -write_verilog 1
+set_option -write_vhdl 1
+
+# Lattice XP
+set_option -maxfan 50
+set_option -disable_io_insertion 1
+set_option -retiming 0
+set_option -pipe 0
+set_option -forcegsr false
+set_option -fix_gated_and_generated_clocks 1
+set_option -rw_check_on_ram 1
+set_option -update_models_cp 0
+set_option -syn_edif_array_rename 1
+set_option -Write_declared_clocks_only 1
+
+# NFilter
+set_option -no_sequential_opt 0
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "./pll_in125_out125_out33.edn"
+
+#set log file 
+set_option log_file "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.srf" 
+impl -active "syn_results"

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/scemi_cfg.txt b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/scemi_cfg.txt
new file mode 100644 (file)
index 0000000..868d437
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/scemi_cfg.txt
@@ -0,0 +1,3 @@
+## UMR3 MESSAGE PORT CONFIGURATION FILE
+## ************************************
+XTOR_DPI_MSG_PORT_UMR_ADDR_VERSION=0

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/scratchproject.prs b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/scratchproject.prs
new file mode 100644 (file)
index 0000000..dccd7f3
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/scratchproject.prs
@@ -0,0 +1,73 @@
+#--  Synopsys, Inc.
+#--  Version M-2017.03L-SP1-1
+#--  Project file /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/scratchproject.prs
+
+#project files
+add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd"
+add_file -fpga_constraint "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc"
+
+
+
+#implementation: "syn_results"
+impl -add /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results -type fpga
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+
+#device options
+set_option -technology ecp5um
+set_option -part LFE5UM_25F
+set_option -package MG285C
+set_option -speed_grade -6
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -top_module "pll_in125_out125_out33"
+
+# hdl_compiler_options
+set_option -distributed_compile 0
+
+# mapper_without_write_options
+set_option -frequency 100
+set_option -srs_instrumentation 1
+
+# mapper_options
+set_option -write_verilog 1
+set_option -write_vhdl 1
+
+# Lattice XP
+set_option -maxfan 50
+set_option -disable_io_insertion 1
+set_option -retiming 0
+set_option -pipe 0
+set_option -forcegsr false
+set_option -fix_gated_and_generated_clocks 1
+set_option -rw_check_on_ram 1
+set_option -update_models_cp 0
+set_option -syn_edif_array_rename 1
+set_option -Write_declared_clocks_only 1
+
+# NFilter
+set_option -no_sequential_opt 0
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.edn"
+
+#set log file 
+set_option log_file "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.srf" 
+impl -active "syn_results"

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/layer0.tlg.rptmap b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/layer0.tlg.rptmap
new file mode 100644 (file)
index 0000000..3910cac
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/layer0.tlg.rptmap
@@ -0,0 +1 @@
+./synwork/layer0.tlg,layer0.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages.

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_compiler.srr b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_compiler.srr
new file mode 100644 (file)
index 0000000..b343684
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_compiler.srr
@@ -0,0 +1,55 @@
+Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":12:7:12:28|Top entity is set to pll_in125_out125_out33.
+File /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd changed - recompiling
+File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling
+VHDL syntax check successful!
+File /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd changed - recompiling
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":12:7:12:28|Synthesizing work.pll_in125_out125_out33.structure.
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2083:10:2083:16|Synthesizing ecp5um.ehxplll.syn_black_box.
+Post processing for ecp5um.ehxplll.syn_black_box
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":832:10:832:12|Synthesizing ecp5um.vlo.syn_black_box.
+Post processing for ecp5um.vlo.syn_black_box
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":825:10:825:12|Synthesizing ecp5um.vhi.syn_black_box.
+Post processing for ecp5um.vhi.syn_black_box
+Post processing for work.pll_in125_out125_out33.structure
+@W: CL168 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":46:4:46:17|Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 15:07:25 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+File /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/layer0.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 15:07:26 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 15:07:26 2019
+
+###########################################################]

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_compiler.srr.db b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_compiler.srr.db
new file mode 100644 (file)
index 0000000..ab34322
Binary files /dev/null and b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_compiler.srr.db differ

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_compiler.srr.rptmap b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_compiler.srr.rptmap
new file mode 100644 (file)
index 0000000..1ce0348
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_compiler.srr.rptmap
@@ -0,0 +1 @@
+./synlog/pll_in125_out125_out33_compiler.srr,pll_in125_out125_out33_compiler.srr,Compile Log

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_fpga_mapper.srr b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_fpga_mapper.srr
new file mode 100644 (file)
index 0000000..2b5185d
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_fpga_mapper.srr
@@ -0,0 +1,265 @@
+# Fri May 10 15:07:28 2019
+
+Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.edn
+M-2017.03L-SP1-1
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
+
+@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":52:4:52:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Fri May 10 15:07:30 2019
+#
+
+
+Top view:               pll_in125_out125_out33
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 10.000
+
+@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
+                   Requested     Estimated     Requested     Estimated                Clock      Clock          
+Starting Clock     Frequency     Frequency     Period        Period        Slack      Type       Group          
+----------------------------------------------------------------------------------------------------------------
+System             100.0 MHz     NA            10.000        0.000         10.000     system     system_clkgroup
+================================================================================================================
+Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks            |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+---------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
+---------------------------------------------------------------------------------------------------------
+System    System  |  10.000      10.000  |  No paths    -      |  No paths    -      |  No paths    -    
+=========================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                           Arrival           
+Instance      Reference     Type        Pin          Net         Time        Slack 
+              Clock                                                                
+-----------------------------------------------------------------------------------
+PLLInst_0     System        EHXPLLL     CLKINTFB     CLKFB_t     0.000       10.000
+===================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+              Starting                                        Required           
+Instance      Reference     Type        Pin       Net         Time         Slack 
+              Clock                                                              
+---------------------------------------------------------------------------------
+PLLInst_0     System        EHXPLLL     CLKFB     CLKFB_t     10.000       10.000
+=================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.000
+    + Clock delay at ending point:           0.000 (ideal)
+    + Estimated clock delay at ending point: 0.000
+    = Required time:                         10.000
+
+    - Propagation time:                      0.000
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (critical) :                     10.000
+
+    Number of logic level(s):                0
+    Starting point:                          PLLInst_0 / CLKINTFB
+    Ending point:                            PLLInst_0 / CLKFB
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            System [rising]
+
+Instance / Net                 Pin          Pin               Arrival     No. of    
+Name               Type        Name         Dir     Delay     Time        Fan Out(s)
+------------------------------------------------------------------------------------
+PLLInst_0          EHXPLLL     CLKINTFB     Out     0.000     0.000       -         
+CLKFB_t            Net         -            -       -         -           1         
+PLLInst_0          EHXPLLL     CLKFB        In      0.000     0.000       -         
+====================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 0 of 24288 (0%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+EHXPLLL:        1
+GSR:            1
+PUR:            1
+VHI:            1
+VLO:            1
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 146MB)
+
+Process took 0h:00m:02s realtime, 0h:00m:02s cputime
+# Fri May 10 15:07:30 2019
+
+###########################################################]

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_fpga_mapper.srr.db b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_fpga_mapper.srr.db
new file mode 100644 (file)
index 0000000..d0f80ff
Binary files /dev/null and b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_fpga_mapper.srr.db differ

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_fpga_mapper.szr b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_fpga_mapper.szr
new file mode 100644 (file)
index 0000000..353b988
Binary files /dev/null and b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_fpga_mapper.szr differ

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_multi_srs_gen.srr b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_multi_srs_gen.srr
new file mode 100644 (file)
index 0000000..787b33e
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_multi_srs_gen.srr
@@ -0,0 +1,12 @@
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+File /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 15:07:27 2019
+
+###########################################################]

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_multi_srs_gen.srr.db b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_multi_srs_gen.srr.db
new file mode 100644 (file)
index 0000000..029fa7a
Binary files /dev/null and b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_multi_srs_gen.srr.db differ

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_premap.srr b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_premap.srr
new file mode 100644 (file)
index 0000000..ea5d1e9
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_premap.srr
@@ -0,0 +1,63 @@
+# Fri May 10 15:07:27 2019
+
+Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc
+@L: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_scck.rpt 
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_scck.rpt" file 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB)
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist pll_in125_out125_out33
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+
+Clock Summary
+******************
+
+          Start      Requested     Requested     Clock      Clock               Clock
+Level     Clock      Frequency     Period        Type       Group               Load 
+-------------------------------------------------------------------------------------
+0 -       System     100.0 MHz     10.000        system     system_clkgroup     0    
+=====================================================================================
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 143MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Fri May 10 15:07:28 2019
+
+###########################################################]

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_premap.srr.db b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_premap.srr.db
new file mode 100644 (file)
index 0000000..e1a8837
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diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_premap.szr b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_premap.szr
new file mode 100644 (file)
index 0000000..0f8bbfc
Binary files /dev/null and b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_premap.szr differ

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/metrics.db b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/metrics.db
new file mode 100644 (file)
index 0000000..7be9186
Binary files /dev/null and b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/metrics.db differ

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_compiler_notes.txt b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_compiler_notes.txt
new file mode 100644 (file)
index 0000000..ac6999c
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_compiler_notes.txt
@@ -0,0 +1,10 @@
+@N|Running in 64-bit mode
+@N|Running in 64-bit mode
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":12:7:12:28|Top entity is set to pll_in125_out125_out33.
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":12:7:12:28|Synthesizing work.pll_in125_out125_out33.structure.
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2083:10:2083:16|Synthesizing ecp5um.ehxplll.syn_black_box.
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":832:10:832:12|Synthesizing ecp5um.vlo.syn_black_box.
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":825:10:825:12|Synthesizing ecp5um.vhi.syn_black_box.
+@N|Running in 64-bit mode
+

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_compiler_runstatus.xml b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_compiler_runstatus.xml
new file mode 100644 (file)
index 0000000..f51b60b
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_compiler_runstatus.xml
@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the job information from compiler to be displayed as part of the summary report.
+*******************************************************************************************-->
+
+<job_run_status name="compiler"> 
+  <report_link name="Detailed report">
+    <data>/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_compiler.srr</data>
+    <title>Synopsys HDL Compiler</title>
+  </report_link> 
+  <job_status>
+    <data>Completed    </data>
+  </job_status>
+<job_info> 
+                       <info name="Notes">
+  <data>9</data>
+  <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_compiler_notes.txt</data></report_link>
+  </info>
+                       <info name="Warnings">
+  <data>1</data>
+  <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_compiler_warnings.txt</data></report_link>
+  </info>
+                       <info name="Errors">
+  <data>0</data>
+  <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_compiler_errors.txt</data></report_link>
+  </info>
+                       <info name="CPU Time">
+  <data>-</data>
+  </info>
+                       <info name="Real Time">
+  <data>00h:00m:01s</data>
+  </info>
+                       <info name="Peak Memory">
+  <data>-</data>
+  </info>
+                       <info name="Date &amp;Time">
+  <data type="timestamp">1557493646</data>
+  </info>
+                       </job_info>
+</job_run_status>
\ No newline at end of file

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_compiler_warnings.txt b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_compiler_warnings.txt
new file mode 100644 (file)
index 0000000..7ae12f2
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_compiler_warnings.txt
@@ -0,0 +1,2 @@
+@W: CL168 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":46:4:46:17|Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
+

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_area_report.xml b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_area_report.xml
new file mode 100644 (file)
index 0000000..c6fedcf
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_area_report.xml
@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the area information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<report_table display_priority="1" name="Area Summary">
+<report_link name="Detailed report">
+<data>/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_resourceusage.rpt</data>
+<title>Resource Usage</title>
+</report_link>
+<parameter tooltip="Total Register bits used" name="Register bits">
+<data>0</data>
+</parameter>
+<parameter tooltip="Total I/O cells used" name="I/O cells">
+<data>0</data>
+</parameter>
+<parameter tcl_name="v_ram" tooltip="Total Block RAMs used" name="Block RAMs">
+<data>0</data>
+</parameter>
+<parameter tcl_name="dsp_used" tooltip="Total DSPs used" name="DSPs">
+<data>0</data>
+</parameter>
+<parameter tcl_name="total_luts" tooltip="Total ORCA LUTs used" name="ORCA LUTs">
+<data>0</data>
+</parameter>
+</report_table>

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_errors.txt b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_errors.txt
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_notes.txt b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_notes.txt
new file mode 100644 (file)
index 0000000..ad96549
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_notes.txt
@@ -0,0 +1,8 @@
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.edn
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_opt_report.xml b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_opt_report.xml
new file mode 100644 (file)
index 0000000..a39ddc1
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_opt_report.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the optimization information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<report_table display_priority="3" name="Optimizations Summary">
+<parameter tooltip="Non-gated/non-generated clock trees / Gated/generated clock trees" name="Combined Clock Conversion">
+<data>0 / 0</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_combined_clk.rpt</data>
+<title>START OF CLOCK OPTIMIZATION REPORT</title>
+</report_link>
+</parameter>
+</report_table>

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_runstatus.xml b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_runstatus.xml
new file mode 100644 (file)
index 0000000..f7bd0c8
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_runstatus.xml
@@ -0,0 +1,46 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the job information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<job_run_status name="Mapper">
+<report_link name="Detailed report">
+<data>/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_fpga_mapper.srr</data>
+<title>Synopsys Lattice Technology Mapper</title>
+</report_link>
+<job_status>
+<data>Completed</data>
+</job_status>
+<job_info>
+<info name="Notes">
+<data>8</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_notes.txt</data>
+</report_link>
+</info>
+<info name="Warnings">
+<data>1</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_warnings.txt</data>
+</report_link>
+</info>
+<info name="Errors">
+<data>0</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_errors.txt</data>
+</report_link>
+</info>
+<info name="CPU Time">
+<data>0h:00m:02s</data>
+</info>
+<info name="Real Time">
+<data>0h:00m:02s</data>
+</info>
+<info name="Peak Memory">
+<data>146MB</data>
+</info>
+<info name="Date &amp; Time">
+<data type="timestamp">1557493650</data>
+</info>
+</job_info>
+</job_run_status>

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_timing_report.xml b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_timing_report.xml
new file mode 100644 (file)
index 0000000..b33a877
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_timing_report.xml
@@ -0,0 +1,23 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+Max Top 5 critical clocks will be reported. For rest user needs to refer to Detailed report
+*******************************************************************************************-->
+<report_table display_priority="2" name="Timing Summary">
+<report_link name="Detailed report">
+<data>/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_fpga_mapper.srr</data>
+<title>START OF TIMING REPORT</title>
+</report_link>
+<row>
+<data tcl_name="clock_name">Clock Name</data>
+<data tcl_name="req_freq">Req Freq</data>
+<data tcl_name="est_freq">Est Freq</data>
+<data tcl_name="slack">Slack</data>
+</row>
+<row>
+<data>System</data>
+<data>100.0 MHz</data>
+<data>NA</data>
+<data>10.000</data>
+</row>
+</report_table>

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_warnings.txt b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_warnings.txt
new file mode 100644 (file)
index 0000000..61d4bc9
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_fpga_mapper_warnings.txt
@@ -0,0 +1 @@
+@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":52:4:52:12|Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_errors.txt b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_errors.txt
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_notes.txt b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_notes.txt
new file mode 100644 (file)
index 0000000..eed8756
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_notes.txt
@@ -0,0 +1,2 @@
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_runstatus.xml b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_runstatus.xml
new file mode 100644 (file)
index 0000000..503e067
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_runstatus.xml
@@ -0,0 +1,46 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the job information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<job_run_status name="Mapper">
+<report_link name="Detailed report">
+<data>/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/pll_in125_out125_out33_premap.srr</data>
+<title>Synopsys Lattice Technology Pre-mapping</title>
+</report_link>
+<job_status>
+<data>Completed</data>
+</job_status>
+<job_info>
+<info name="Notes">
+<data>2</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_notes.txt</data>
+</report_link>
+</info>
+<info name="Warnings">
+<data>0</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_warnings.txt</data>
+</report_link>
+</info>
+<info name="Errors">
+<data>0</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_errors.txt</data>
+</report_link>
+</info>
+<info name="CPU Time">
+<data>0h:00m:00s</data>
+</info>
+<info name="Real Time">
+<data>0h:00m:00s</data>
+</info>
+<info name="Peak Memory">
+<data>143MB</data>
+</info>
+<info name="Date &amp; Time">
+<data type="timestamp">1557493648</data>
+</info>
+</job_info>
+</job_run_status>

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_warnings.txt b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/report/pll_in125_out125_out33_premap_warnings.txt
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/syntax_constraint_check.rpt.rptmap b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/syntax_constraint_check.rpt.rptmap
new file mode 100644 (file)
index 0000000..dd09adb
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synlog/syntax_constraint_check.rpt.rptmap
@@ -0,0 +1 @@
+./pll_in125_out125_out33_scck.rpt,syntax_constraint_check.rpt,Syntax Constraint Check Report

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/syntmp/closed.png b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/syntmp/closed.png
new file mode 100644 (file)
index 0000000..0d78634
Binary files /dev/null and b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/syntmp/closed.png differ

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/syntmp/open.png b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/syntmp/open.png
new file mode 100644 (file)
index 0000000..a227005
Binary files /dev/null and b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/syntmp/open.png differ

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/syntmp/pll_in125_out125_out33.plg b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/syntmp/pll_in125_out125_out33.plg
new file mode 100644 (file)
index 0000000..bba9612
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/syntmp/pll_in125_out125_out33.plg
@@ -0,0 +1,8 @@
+@P:  Worst Slack : 10.000
+@P:  System - Estimated Frequency : NA
+@P:  System - Requested Frequency : 100.0 MHz
+@P:  System - Estimated Period : 0.000
+@P:  System - Requested Period : 10.000
+@P:  System - Slack : 10.000
+@P:  Total Area : 0.0
+@P:  CPU Time : 0h:00m:02s

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/syntmp/pll_in125_out125_out33_srr.htm b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/syntmp/pll_in125_out125_out33_srr.htm
new file mode 100644 (file)
index 0000000..7b4d05f
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/syntmp/pll_in125_out125_out33_srr.htm
@@ -0,0 +1,421 @@
+<html><body><samp><pre>
+<!@TC:1557493645>
+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
+#install: /home/soft/lattice/diamond/3.10_x64/synpbase
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Fri May 10 15:07:25 2019
+
+#Implementation: syn_results
+
+<a name=compilerReport1></a>Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1557493646> | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+<a name=compilerReport2></a>Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1557493646> | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1557493646> | Setting time resolution to ps
+@N: : <a href="/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd:12:7:12:29:@N::@XP_MSG">pll_in125_out125_out33.vhd(12)</a><!@TM:1557493646> | Top entity is set to pll_in125_out125_out33.
+File /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd changed - recompiling
+File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling
+VHDL syntax check successful!
+File /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd changed - recompiling
+@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd:12:7:12:29:@N:CD630:@XP_MSG">pll_in125_out125_out33.vhd(12)</a><!@TM:1557493646> | Synthesizing work.pll_in125_out125_out33.structure.
+@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd:2083:10:2083:17:@N:CD630:@XP_MSG">ecp5um.vhd(2083)</a><!@TM:1557493646> | Synthesizing ecp5um.ehxplll.syn_black_box.
+Post processing for ecp5um.ehxplll.syn_black_box
+@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd:832:10:832:13:@N:CD630:@XP_MSG">ecp5um.vhd(832)</a><!@TM:1557493646> | Synthesizing ecp5um.vlo.syn_black_box.
+Post processing for ecp5um.vlo.syn_black_box
+@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd:825:10:825:13:@N:CD630:@XP_MSG">ecp5um.vhd(825)</a><!@TM:1557493646> | Synthesizing ecp5um.vhi.syn_black_box.
+Post processing for ecp5um.vhi.syn_black_box
+Post processing for work.pll_in125_out125_out33.structure
+<font color=#A52A2A>@W:<a href="@W:CL168:@XP_HELP">CL168</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd:46:4:46:18:@W:CL168:@XP_MSG">pll_in125_out125_out33.vhd(46)</a><!@TM:1557493646> | Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.</font>
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 15:07:25 2019
+
+###########################################################]
+<a name=compilerReport3></a>Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1557493646> | Running in 64-bit mode 
+File /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/layer0.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 15:07:26 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 15:07:26 2019
+
+###########################################################]
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1557493645>
+<a name=compilerReport4></a>Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1557493647> | Running in 64-bit mode 
+File /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 15:07:27 2019
+
+###########################################################]
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1557493645>
+# Fri May 10 15:07:27 2019
+
+<a name=mapperReport5></a>Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35</a>
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc
+Linked File: <a href="/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_scck.rpt:@XP_FILE">pll_in125_out125_out33_scck.rpt</a>
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_scck.rpt" file 
+@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1557493648> | Running in 64-bit mode. 
+@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1557493648> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 116MB)
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist pll_in125_out125_out33
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+
+<a name=mapperReport6></a>Clock Summary</a>
+******************
+
+          Start      Requested     Requested     Clock      Clock               Clock
+Level     Clock      Frequency     Period        Type       Group               Load 
+-------------------------------------------------------------------------------------
+0 -       System     100.0 MHz     10.000        system     system_clkgroup     0    
+=====================================================================================
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 143MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Fri May 10 15:07:28 2019
+
+###########################################################]
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1557493645>
+# Fri May 10 15:07:28 2019
+
+<a name=mapperReport7></a>Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35</a>
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1557493650> | Running in 64-bit mode. 
+@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1557493650> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1557493650> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+<a name=clockReport8></a>#### START OF CLOCK OPTIMIZATION REPORT #####[</a>
+
+0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 143MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB)
+
+Writing EDIF Netlist and constraint files
+@N:<a href="@N:FX1056:@XP_HELP">FX1056</a> : <!@TM:1557493650> | Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.edn 
+M-2017.03L-SP1-1
+@N:<a href="@N:BW106:@XP_HELP">BW106</a> : <!@TM:1557493650> | Synplicity Constraint File capacitance units using default value of 1pF  
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 146MB)
+
+<font color=#A52A2A>@W:<a href="@W:MT246:@XP_HELP">MT246</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd:52:4:52:13:@W:MT246:@XP_MSG">pll_in125_out125_out33.vhd(52)</a><!@TM:1557493650> | Blackbox EHXPLLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) </font>
+
+
+<a name=timingReport9></a>##### START OF TIMING REPORT #####[</a>
+# Timing Report written on Fri May 10 15:07:30 2019
+#
+
+
+Top view:               pll_in125_out125_out33
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.fdc
+                       
+@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1557493650> | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 
+
+@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1557493650> | Clock constraints include only register-to-register paths associated with each individual clock. 
+
+
+
+<a name=performanceSummary10></a>Performance Summary</a>
+*******************
+
+
+Worst slack in design: 10.000
+
+@N:<a href="@N:MT286:@XP_HELP">MT286</a> : <!@TM:1557493650> | System clock period 0.000 stretches to negative invalid value -- ignoring stretching. 
+                   Requested     Estimated     Requested     Estimated                Clock      Clock          
+Starting Clock     Frequency     Frequency     Period        Period        Slack      Type       Group          
+----------------------------------------------------------------------------------------------------------------
+System             100.0 MHz     NA            10.000        0.000         10.000     system     system_clkgroup
+================================================================================================================
+Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
+
+
+
+
+
+<a name=clockRelationships11></a>Clock Relationships</a>
+*******************
+
+Clocks            |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+---------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
+---------------------------------------------------------------------------------------------------------
+System    System  |  10.000      10.000  |  No paths    -      |  No paths    -      |  No paths    -    
+=========================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+<a name=interfaceInfo12></a>Interface Information </a>
+*********************
+
+No IO constraint found
+
+
+
+====================================
+<a name=clockReport13></a>Detailed Report for Clock: System</a>
+====================================
+
+
+
+<a name=startingSlack14></a>Starting Points with Worst Slack</a>
+********************************
+
+              Starting                                           Arrival           
+Instance      Reference     Type        Pin          Net         Time        Slack 
+              Clock                                                                
+-----------------------------------------------------------------------------------
+PLLInst_0     System        EHXPLLL     CLKINTFB     CLKFB_t     0.000       10.000
+===================================================================================
+
+
+<a name=endingSlack15></a>Ending Points with Worst Slack</a>
+******************************
+
+              Starting                                        Required           
+Instance      Reference     Type        Pin       Net         Time         Slack 
+              Clock                                                              
+---------------------------------------------------------------------------------
+PLLInst_0     System        EHXPLLL     CLKFB     CLKFB_t     10.000       10.000
+=================================================================================
+
+
+
+<a name=worstPaths16></a>Worst Path Information</a>
+<a href="/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.srr:srsf/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33.srs:fp:18102:18357:@XP_NAMES_GATE">View Worst Path in Analyst</a>
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.000
+    + Clock delay at ending point:           0.000 (ideal)
+    + Estimated clock delay at ending point: 0.000
+    = Required time:                         10.000
+
+    - Propagation time:                      0.000
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (critical) :                     10.000
+
+    Number of logic level(s):                0
+    Starting point:                          PLLInst_0 / CLKINTFB
+    Ending point:                            PLLInst_0 / CLKFB
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            System [rising]
+
+Instance / Net                 Pin          Pin               Arrival     No. of    
+Name               Type        Name         Dir     Delay     Time        Fan Out(s)
+------------------------------------------------------------------------------------
+PLLInst_0          EHXPLLL     CLKINTFB     Out     0.000     0.000       -         
+CLKFB_t            Net         -            -       -         -           1         
+PLLInst_0          EHXPLLL     CLKFB        In      0.000     0.000       -         
+====================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 146MB)
+
+---------------------------------------
+<a name=resourceUsage17></a>Resource Usage Report</a>
+Part: lfe5um_25f-6
+
+Register bits: 0 of 24288 (0%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+EHXPLLL:        1
+GSR:            1
+PUR:            1
+VHI:            1
+VLO:            1
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 146MB)
+
+Process took 0h:00m:02s realtime, 0h:00m:02s cputime
+# Fri May 10 15:07:30 2019
+
+###########################################################]
+
+</pre></samp></body></html>

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/syntmp/pll_in125_out125_out33_toc.htm b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/syntmp/pll_in125_out125_out33_toc.htm
new file mode 100644 (file)
index 0000000..0e7c50e
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/syntmp/pll_in125_out125_out33_toc.htm
@@ -0,0 +1,45 @@
+ <html> 
+  <head>
+    <script type="text/javascript" src="file:///home/soft/lattice/diamond/3.10_x64/synpbase/lib/report/reportlog_tree.js"></script>
+    <link rel="stylesheet" type="text/css" href="file:///home/soft/lattice/diamond/3.10_x64/synpbase/lib/report/reportlog_tree.css" />  
+  </head> 
+
+  <body style="background-color:#e0e0ff;">
+   <script type="text/javascript"> reportLogObj.loadImage("closed.png", "open.png")</script>
+    <ul id="syn_results-menu" class="treeview" style="padding-left:12;">
+        <li style="font-size:12; font-style:normal"> <b style="background-color:#a2bff0; font-weight:bold">pll_in125_out125_out33 (syn_results)</b> 
+         <ul rel="open" style="font-size:small;">
+
+<li style="font-size:12; font-style:normal"><b style="background-color:#a2bff0; font-weight:bold">Synthesis -  </b> 
+<ul rel="open">
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/syntmp/pll_in125_out125_out33_srr.htm#compilerReport1" target="srrFrame" title="">Compiler Report</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/syntmp/pll_in125_out125_out33_srr.htm#compilerReport3" target="srrFrame" title="">Compiler Constraint Applicator</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/syntmp/pll_in125_out125_out33_srr.htm#mapperReport5" target="srrFrame" title="">Pre-mapping Report</a>  
+<ul rel="open" >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/syntmp/pll_in125_out125_out33_srr.htm#mapperReport6" target="srrFrame" title="">Clock Summary</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/syntmp/pll_in125_out125_out33_srr.htm#mapperReport7" target="srrFrame" title="">Mapper Report</a>  
+<ul rel="open" >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/syntmp/pll_in125_out125_out33_srr.htm#clockReport8" target="srrFrame" title="">Clock Conversion</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/syntmp/pll_in125_out125_out33_srr.htm#timingReport9" target="srrFrame" title="">Timing Report</a>  
+<ul rel="open" >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/syntmp/pll_in125_out125_out33_srr.htm#performanceSummary10" target="srrFrame" title="">Performance Summary</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/syntmp/pll_in125_out125_out33_srr.htm#clockRelationships11" target="srrFrame" title="">Clock Relationships</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/syntmp/pll_in125_out125_out33_srr.htm#interfaceInfo12" target="srrFrame" title="">Interface Information</a>  </li>
+<li><a href="file://#" target="srrFrame" title="">Detailed Report for Clocks</a>  
+<ul  >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/syntmp/pll_in125_out125_out33_srr.htm#clockReport13" target="srrFrame" title="">Clock: System</a>  
+<ul  >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/syntmp/pll_in125_out125_out33_srr.htm#startingSlack14" target="srrFrame" title="">Starting Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/syntmp/pll_in125_out125_out33_srr.htm#endingSlack15" target="srrFrame" title="">Ending Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/syntmp/pll_in125_out125_out33_srr.htm#worstPaths16" target="srrFrame" title="">Worst Path Information</a>  </li></ul></li></ul></li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/syntmp/pll_in125_out125_out33_srr.htm#resourceUsage17" target="srrFrame" title="">Resource Utilization</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/pll_in125_out125_out33_cck.rpt" target="srrFrame" title="">Constraint Checker Report (15:07 10-May)</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/stdout.log" target="srrFrame" title="">Session Log (15:07 10-May)</a>  
+<ul  ></ul></li>         </ul>
+        </li>
+   </ul>
+
+   <script type="text/javascript"> reportLogObj.generateLog("syn_results-menu")</script>
+
+  </body>
+ </html>
\ No newline at end of file

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/syntmp/run_option.xml b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/syntmp/run_option.xml
new file mode 100644 (file)
index 0000000..4eb904e
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/syntmp/run_option.xml
@@ -0,0 +1,24 @@
+<?xml version="1.0" encoding="utf-8"?> 
+<!-- 
+  Synopsys, Inc.
+  Version M-2017.03L-SP1-1
+  Project file /home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/syntmp/run_option.xml
+  Written on Fri May 10 15:07:25 2019
+
+
+--> 
+<project_attribute_list name="Project Settings"> 
+     <option name="project_name" display_name="Project Name">pll_in125_out125_out33</option>
+     <option name="device_name" display_name="Device Name">syn_results: Lattice ECP5UM : LFE5UM_25F</option>
+     <option name="impl_name" display_name="Implementation Name">syn_results</option>
+     <option name="top_module" display_name="Top Module">pll_in125_out125_out33</option>
+     <option name="pipe" display_name="Pipelining">0</option>
+     <option name="retiming" display_name="Retiming">0</option>
+     <option name="resource_sharing" display_name="Resource Sharing">1</option>
+     <option name="maxfan" display_name="Fanout Guide">50</option>
+     <option name="disable_io_insertion" display_name="Disable I/O Insertion">1</option>
+     <option name="no_sequential_opt" display_name="Disable Sequential Optimizations">0</option>
+     <option name="fix_gated_and_generated_clocks" display_name="Clock Conversion">1</option>
+     <option name="symbolic_fsm_compiler" display_name="FSM Compiler">1</option>
+</project_attribute_list>
+

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/syntmp/statusReport.html b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/syntmp/statusReport.html
new file mode 100644 (file)
index 0000000..c558da4
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/syntmp/statusReport.html
@@ -0,0 +1,112 @@
+<html> 
+                       <head>                  <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1" />
+                       <title>Project Status Summary Page</title>
+                       <link rel="stylesheet" type="text/css" href="projectstatuspage.css" />
+                       <script type = "text/javascript" src="projectstatuspage.js"></script>
+                       </head>
+
+                       <body style="background-color:#f0f0ff;">
+                       
+<table style="border:none;" width="100%" ><tr> <td class="outline">
+<table width="100%" border="0" cellspacing="0" cellpadding="0">             <thead class="tablehead"><tr><th colspan="4">Project Settings</th><tr> 
+ <tr> <td class="optionTitle" align="left"> Project Name</td> <td> pll_in125_out125_out33</td> <td class="optionTitle" align="left"> Device Name</td> <td> syn_results: Lattice ECP5UM : LFE5UM_25F</td> </tr>
+<tr> <td class="optionTitle" align="left"> Implementation Name</td> <td> syn_results</td> <td class="optionTitle" align="left"> Top Module</td> <td> pll_in125_out125_out33</td> </tr>
+                </thead> 
+                <tbody> <tr> <td class="optionTitle" align="left"> Pipelining</td> <td> 0</td> <td class="optionTitle" align="left"> Retiming</td> <td> 0</td> </tr>
+<tr> <td class="optionTitle" align="left"> Resource Sharing</td> <td> 1</td> <td class="optionTitle" align="left"> Fanout Guide</td> <td> 50</td> </tr>
+<tr> <td class="optionTitle" align="left"> Disable I/O Insertion</td> <td> 1</td> <td class="optionTitle" align="left"> Disable Sequential Optimizations</td> <td> 0</td> </tr>
+<tr> <td class="optionTitle" align="left"> Clock Conversion</td> <td> 1</td> <td class="optionTitle" align="left"> FSM Compiler</td> <td> 1</td> </tr>
+ 
+</tbody> 
+  </table><br>  <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
+                                  <thead class="tablehead"><tr><th   colspan="9">Run Status</th></tr></thead>
+         <tbody>
+               <tr>
+                       <th align="left" width="17%">Job Name</th>
+                       <th align="left">Status</th>
+                       <td class="lnote" align="center" title="Notes"></td>
+                       <td class="lwarn" align="center" title="Warnings"></td>
+                       <td class="lerror" align="center" title="Errors"></td>
+                       <th align="left">CPU Time</th>
+                       <th align="left">Real Time</th>
+                       <th align="left">Memory</th>
+                       <th align="left">Date/Time</th>
+         </tr>
+  <tr>
+  <td class="optionTitle"> (compiler)</td><td>Complete</td>
+ <td>9</td>
+ <td>1</td>
+<td>0</td>
+<td>-</td>
+<td>00m:01s</td>
+<td>-</td>
+<td><font size="-1">5/10/19</font><br/><font size="-2">3:07 PM</font></td>
+</tr> 
+
+ <tr>
+  <td class="optionTitle"> (premap)</td><td>Complete</td>
+ <td>2</td>
+<td>0</td>
+<td>0</td>
+<td>0m:00s</td>
+<td>0m:00s</td>
+<td>143MB</td>
+<td><font size="-1">5/10/19</font><br/><font size="-2">3:07 PM</font></td>
+</tr> 
+
+ <tr>
+  <td class="optionTitle"> (fpga_mapper)</td><td>Complete</td>
+ <td>8</td>
+ <td>1</td>
+<td>0</td>
+<td>0m:02s</td>
+<td>0m:02s</td>
+<td>146MB</td>
+<td><font size="-1">5/10/19</font><br/><font size="-2">3:07 PM</font></td>
+</tr> 
+
+<tr>
+  <td class="optionTitle">Multi-srs Generator</td>
+  <td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td></td><td class="empty"></td><td class="empty"></td><td><font size="-1">5/10/19</font><br/><font size="-2">3:07 PM</font></td>              </tbody>
+     </table>
+ <br> 
+ <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
+                                  <thead class="tablehead"><tr><th   colspan="4">Area Summary</th></tr></thead>
+<tfoot> <tr> <td class="optionTitle" colspan="4"></td></tr> 
+ </tfoot> 
+ <tbody> <tr> 
+<td title ="Total Register bits used" class="optionTitle" align="left">Register bits</td> <td>0</td>
+<td title ="Total I/O cells used" class="optionTitle" align="left">I/O cells</td> <td>0</td>
+</tr>
+<tr> 
+<td title ="Total Block RAMs used" class="optionTitle" align="left">Block RAMs
+(v_ram)</td> <td>0</td>
+<td title ="Total DSPs used" class="optionTitle" align="left">DSPs
+(dsp_used)</td> <td>0</td>
+</tr>
+<tr> 
+<td title ="Total ORCA LUTs used" class="optionTitle" align="left">ORCA LUTs
+(total_luts)</td> <td>0</td>
+<td class="optionTitle"></td><td></td></tr> 
+</tbody>
+    </table><br>
+ <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
+                                  <thead class="tablehead"><tr><th   colspan="4">Timing Summary</th></tr></thead>
+<tfoot> <tr> <td class="optionTitle" colspan="2"></td></tr> 
+ </tfoot> 
+<tbody> 
+   <tr><th class="optionTitle" align= "left ">Clock Name</th><th class="optionTitle" align= "left ">Req Freq</th><th class="optionTitle" align= "left ">Est Freq</th><th class="optionTitle" align= "left ">Slack</th></tr> 
+<tr> <td  align="left">System</td><td  align="left">100.0 MHz</td><td  align="left">NA</td><td  align="left">10.000</td></tr> 
+</tbody> 
+ </table>
+<br>
+ <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
+                                  <thead class="tablehead"><tr><th   colspan="4">Optimizations Summary</th></tr></thead>
+ <tbody> <tr> 
+<td title ="Non-gated/non-generated clock trees / Gated/generated clock trees" class="optionTitle" align="left">Combined Clock Conversion</td> <td>0 / 0</td>
+<td class="optionTitle"></td><td></td></tr> 
+</tbody>
+    </table><br>
+<br> 
+</td></tr></table></body> 
+ </html>
\ No newline at end of file

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/.cckTransfer b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/.cckTransfer
new file mode 100644 (file)
index 0000000..85a9594
Binary files /dev/null and b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/.cckTransfer differ

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/_mh_info b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/_mh_info
new file mode 100644 (file)
index 0000000..37bc105
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/_mh_info
@@ -0,0 +1 @@
+|1|

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/layer0.fdep b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/layer0.fdep
new file mode 100644 (file)
index 0000000..09b34f8
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/layer0.fdep
@@ -0,0 +1,28 @@
+#defaultlanguage:vhdl
+#OPTIONS:"|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_comp.srs|-top|pll_in125_out125_out33|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610
+#CUR:"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":1557493644
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599
+0 "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd" vhdl
+
+# Dependency Lists (Uses list)
+0 -1
+
+# Dependency Lists (Users Of)
+0 -1
+
+# Design Unit to File Association
+arch work pll_in125_out125_out33 structure 0
+module work pll_in125_out125_out33 0
+
+
+# Configuration files used

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/layer0.fdeporig b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/layer0.fdeporig
new file mode 100644 (file)
index 0000000..9af575e
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/layer0.fdeporig
@@ -0,0 +1,24 @@
+#defaultlanguage:vhdl
+#OPTIONS:"|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_comp.srs|-top|pll_in125_out125_out33|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610
+#CUR:"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":1557493644
+0 "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd" vhdl
+
+# Dependency Lists (Uses list)
+0 -1
+
+# Dependency Lists (Users Of)
+0 -1
+
+# Design Unit to File Association
+arch work pll_in125_out125_out33 structure 0
+module work pll_in125_out125_out33 0

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/layer0.srs b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/layer0.srs
new file mode 100644 (file)
index 0000000..0e9ebe9
Binary files /dev/null and b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/layer0.srs differ

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/layer0.tlg b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/layer0.tlg
new file mode 100644 (file)
index 0000000..27d3bb9
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/layer0.tlg
@@ -0,0 +1,9 @@
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":12:7:12:28|Synthesizing work.pll_in125_out125_out33.structure.
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":2083:10:2083:16|Synthesizing ecp5um.ehxplll.syn_black_box.
+Post processing for ecp5um.ehxplll.syn_black_box
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":832:10:832:12|Synthesizing ecp5um.vlo.syn_black_box.
+Post processing for ecp5um.vlo.syn_black_box
+@N: CD630 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":825:10:825:12|Synthesizing ecp5um.vhi.syn_black_box.
+Post processing for ecp5um.vhi.syn_black_box
+Post processing for work.pll_in125_out125_out33.structure
+@W: CL168 :"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":46:4:46:17|Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/layer0.tlg.db b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/layer0.tlg.db
new file mode 100644 (file)
index 0000000..c899ed0
Binary files /dev/null and b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/layer0.tlg.db differ

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/modulechange.db b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/modulechange.db
new file mode 100644 (file)
index 0000000..d39d6dc
Binary files /dev/null and b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/modulechange.db differ

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_comp.fdep b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_comp.fdep
new file mode 100644 (file)
index 0000000..a5607af
--- /dev/null
+++ b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_comp.fdep
@@ -0,0 +1,21 @@
+#OPTIONS:"|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_comp.srs|-top|pll_in125_out125_out33|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610
+#CUR:"/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd":1557493644
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599
+0                      "/home/adrian/git/trb5sc/template/project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd" vhdl
+#Dependency Lists(Uses List)
+0 -1
+#Dependency Lists(Users Of)
+0 -1
+#Design Unit to File Association
+module work pll_in125_out125_out33 0
+arch work pll_in125_out125_out33 structure 0

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_comp.srs b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_comp.srs
new file mode 100644 (file)
index 0000000..2f8e0e3
Binary files /dev/null and b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_comp.srs differ

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_m.srm b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_m.srm
new file mode 100644 (file)
index 0000000..15fc0b0
Binary files /dev/null and b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_m.srm differ

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_m_srm/fileinfo.srm b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_m_srm/fileinfo.srm
new file mode 100644 (file)
index 0000000..c1e1fe7
Binary files /dev/null and b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_m_srm/fileinfo.srm differ

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_mult.srs b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_mult.srs
new file mode 100644 (file)
index 0000000..1303ca7
Binary files /dev/null and b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_mult.srs differ

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_mult_srs/fileinfo.srs b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_mult_srs/fileinfo.srs
new file mode 100644 (file)
index 0000000..88e21eb
Binary files /dev/null and b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_mult_srs/fileinfo.srs differ

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_mult_srs/skeleton.srs b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_mult_srs/skeleton.srs
new file mode 100644 (file)
index 0000000..2fd7036
Binary files /dev/null and b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_mult_srs/skeleton.srs differ

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_prem.fse b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_prem.fse
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_prem.srd b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_prem.srd
new file mode 100644 (file)
index 0000000..b644ad5
Binary files /dev/null and b/gbe/cores/sgmii/pll_in125_out125_out33/syn_results/synwork/pll_in125_out125_out33_prem.srd differ

diff --git a/gbe/cores/sgmii/sgmii.sbx b/gbe/cores/sgmii/sgmii.sbx
new file mode 100644 (file)
index 0000000..c3bcc48
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii.sbx
@@ -0,0 +1,3805 @@
+<!DOCTYPE sgmii>
+<lattice:project>
+    <spirit:component>
+        <spirit:vendor>LATTICE</spirit:vendor>
+        <spirit:library>LOCAL</spirit:library>
+        <spirit:name>sgmii</spirit:name>
+        <spirit:version>1.0</spirit:version>
+        <spirit:fileSets>
+            <spirit:fileset>
+                <spirit:name>Diamond_Synthesis</spirit:name>
+                <spirit:group>synthesis</spirit:group>
+                <spirit:file>
+                    <spirit:name>./sgmii.vhd</spirit:name>
+                    <spirit:fileType>vhdlSource</spirit:fileType>
+                </spirit:file>
+            </spirit:fileset>
+            <spirit:fileset>
+                <spirit:name>Diamond_Simulation</spirit:name>
+                <spirit:group>simulation</spirit:group>
+                <spirit:file>
+                    <spirit:name>./sgmii.vhd</spirit:name>
+                    <spirit:fileType>vhdlSource</spirit:fileType>
+                </spirit:file>
+            </spirit:fileset>
+        </spirit:fileSets>
+        <spirit:componentGenerators/>
+        <spirit:model>
+            <spirit:views/>
+            <spirit:ports>
+                <spirit:port>
+                    <spirit:name>PCSD_hdinn</spirit:name>
+                    <spirit:displayName>PCSD_hdinn</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">PCSD.hdinn</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>PCSD_hdinp</spirit:name>
+                    <spirit:displayName>PCSD_hdinp</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">PCSD.hdinp</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>PCSD_hdoutn</spirit:name>
+                    <spirit:displayName>PCSD_hdoutn</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">PCSD.hdoutn</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>PCSD_hdoutp</spirit:name>
+                    <spirit:displayName>PCSD_hdoutp</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">PCSD.hdoutp</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>pll_in125_out125_out33_CLKI</spirit:name>
+                    <spirit:displayName>pll_in125_out125_out33_CLKI</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">pll_in125_out125_out33.CLKI</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>pll_in125_out125_out33_CLKOP</spirit:name>
+                    <spirit:displayName>pll_in125_out125_out33_CLKOP</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">pll_in125_out125_out33.CLKOP</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>pll_in125_out125_out33_CLKOS</spirit:name>
+                    <spirit:displayName>pll_in125_out125_out33_CLKOS</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">pll_in125_out125_out33.CLKOS</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>pll_in125_out125_out33_LOCK</spirit:name>
+                    <spirit:displayName>pll_in125_out125_out33_LOCK</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">pll_in125_out125_out33.LOCK</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_hdinn</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_hdinn</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.hdinn</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_hdinp</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_hdinp</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.hdinp</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_hdoutn</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_hdoutn</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.hdoutn</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_hdoutp</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_hdoutp</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.hdoutp</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+            </spirit:ports>
+        </spirit:model>
+        <spirit:vendorExtensions>
+            <lattice:device>LFE5UM-85F-8BG756C</lattice:device>
+            <lattice:synthesis>synplify</lattice:synthesis>
+            <lattice:date>2019-04-24.09:28:38 AM</lattice:date>
+            <lattice:modified>2019-05-10.04:50:40 PM</lattice:modified>
+            <lattice:diamond>3.10.3.144</lattice:diamond>
+            <lattice:language>VHDL</lattice:language>
+            <lattice:attributes>
+                <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+                <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+                <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+                <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+            </lattice:attributes>
+            <lattice:elements/>
+            <lattice:lpc/>
+            <lattice:groups/>
+        </spirit:vendorExtensions>
+    </spirit:component>
+    <spirit:design>
+        <spirit:vendor>LATTICE</spirit:vendor>
+        <spirit:library>LOCAL</spirit:library>
+        <spirit:name>sgmii</spirit:name>
+        <spirit:version>1.0</spirit:version>
+        <spirit:componentInstances>
+            <spirit:componentInstance>
+                <spirit:instanceName>PCSD</spirit:instanceName>
+                <spirit:componentRef>
+                    <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
+                    <spirit:library>LEGACY</spirit:library>
+                    <spirit:name>PCS</spirit:name>
+                    <spirit:version>8.2</spirit:version>
+                    <spirit:fileSets>
+                        <spirit:fileset>
+                            <spirit:name>Diamond_Simulation</spirit:name>
+                            <spirit:group>simulation</spirit:group>
+                            <spirit:file>
+                                <spirit:name>./PCSD/PCSD_softlogic.v</spirit:name>
+                                <spirit:fileType>verilogSource</spirit:fileType>
+                            </spirit:file>
+                            <spirit:file>
+                                <spirit:name>./PCSD/PCSD.vhd</spirit:name>
+                                <spirit:fileType>vhdlSource</spirit:fileType>
+                            </spirit:file>
+                        </spirit:fileset>
+                        <spirit:fileset>
+                            <spirit:name>Diamond_Synthesis</spirit:name>
+                            <spirit:group>synthesis</spirit:group>
+                            <spirit:file>
+                                <spirit:name>./PCSD/PCSD_softlogic.v</spirit:name>
+                                <spirit:fileType>verilogSource</spirit:fileType>
+                            </spirit:file>
+                            <spirit:file>
+                                <spirit:name>./PCSD/PCSD.vhd</spirit:name>
+                                <spirit:fileType>vhdlSource</spirit:fileType>
+                            </spirit:file>
+                        </spirit:fileset>
+                    </spirit:fileSets>
+                    <spirit:componentGenerators>
+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>Configuration</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
+                            <spirit:group>CONFIG</spirit:group>
+                        </spirit:componentGenerator>
+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>CreateNGD</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_ngd.tcl</spirit:generatorExe>
+                            <spirit:group>CONFIG</spirit:group>
+                        </spirit:componentGenerator>
+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>Generation</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
+                            <spirit:group>GENERATE</spirit:group>
+                        </spirit:componentGenerator>
+                    </spirit:componentGenerators>
+                    <spirit:model>
+                        <spirit:views/>
+                        <spirit:ports>
+                            <spirit:port>
+                                <spirit:name>ctc_del_s</spirit:name>
+                                <spirit:displayName>ctc_del_s</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>ctc_ins_s</spirit:name>
+                                <spirit:displayName>ctc_ins_s</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>ctc_orun_s</spirit:name>
+                                <spirit:displayName>ctc_orun_s</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>ctc_urun_s</spirit:name>
+                                <spirit:displayName>ctc_urun_s</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>hdinn</spirit:name>
+                                <spirit:displayName>hdinn</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                                <spirit:vendorExtensions>
+                                    <lattice:attributes>
+                                        <lattice:attribute lattice:name="PadPin">true</lattice:attribute>
+                                    </lattice:attributes>
+                                </spirit:vendorExtensions>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>hdinp</spirit:name>
+                                <spirit:displayName>hdinp</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                                <spirit:vendorExtensions>
+                                    <lattice:attributes>
+                                        <lattice:attribute lattice:name="PadPin">true</lattice:attribute>
+                                    </lattice:attributes>
+                                </spirit:vendorExtensions>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>hdoutn</spirit:name>
+                                <spirit:displayName>hdoutn</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                                <spirit:vendorExtensions>
+                                    <lattice:attributes>
+                                        <lattice:attribute lattice:name="PadPin">true</lattice:attribute>
+                                    </lattice:attributes>
+                                </spirit:vendorExtensions>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>hdoutp</spirit:name>
+                                <spirit:displayName>hdoutp</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                                <spirit:vendorExtensions>
+                                    <lattice:attributes>
+                                        <lattice:attribute lattice:name="PadPin">true</lattice:attribute>
+                                    </lattice:attributes>
+                                </spirit:vendorExtensions>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>lsm_status_s</spirit:name>
+                                <spirit:displayName>lsm_status_s</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>pll_lol</spirit:name>
+                                <spirit:displayName>pll_lol</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>pll_refclki</spirit:name>
+                                <spirit:displayName>pll_refclki</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rsl_disable</spirit:name>
+                                <spirit:displayName>rsl_disable</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rsl_rst</spirit:name>
+                                <spirit:displayName>rsl_rst</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rst_dual_c</spirit:name>
+                                <spirit:displayName>rst_dual_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_cdr_lol_s</spirit:name>
+                                <spirit:displayName>rx_cdr_lol_s</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_los_low_s</spirit:name>
+                                <spirit:displayName>rx_los_low_s</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_pcs_rst_c</spirit:name>
+                                <spirit:displayName>rx_pcs_rst_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_pwrup_c</spirit:name>
+                                <spirit:displayName>rx_pwrup_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_serdes_rst_c</spirit:name>
+                                <spirit:displayName>rx_serdes_rst_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rxrefclk</spirit:name>
+                                <spirit:displayName>rxrefclk</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>serdes_pdb</spirit:name>
+                                <spirit:displayName>serdes_pdb</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>serdes_rst_dual_c</spirit:name>
+                                <spirit:displayName>serdes_rst_dual_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>signal_detect_c</spirit:name>
+                                <spirit:displayName>signal_detect_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_pclk</spirit:name>
+                                <spirit:displayName>tx_pclk</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_pcs_rst_c</spirit:name>
+                                <spirit:displayName>tx_pcs_rst_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_pwrup_c</spirit:name>
+                                <spirit:displayName>tx_pwrup_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_serdes_rst_c</spirit:name>
+                                <spirit:displayName>tx_serdes_rst_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>txi_clk</spirit:name>
+                                <spirit:displayName>txi_clk</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_cv_err</spirit:name>
+                                <spirit:displayName>rx_cv_err</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>0</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_disp_err</spirit:name>
+                                <spirit:displayName>rx_disp_err</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>0</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_k</spirit:name>
+                                <spirit:displayName>rx_k</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>0</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rxdata</spirit:name>
+                                <spirit:displayName>rxdata</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>7</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_disp_correct</spirit:name>
+                                <spirit:displayName>tx_disp_correct</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>0</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_k</spirit:name>
+                                <spirit:displayName>tx_k</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>0</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>txdata</spirit:name>
+                                <spirit:displayName>txdata</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>7</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>xmit</spirit:name>
+                                <spirit:displayName>xmit</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>0</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                        </spirit:ports>
+                    </spirit:model>
+                    <spirit:vendorExtensions>
+                        <lattice:synthesis>synplify</lattice:synthesis>
+                        <lattice:modified>2019-05-10.04:50:40 PM</lattice:modified>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+                            <lattice:attribute lattice:name="BBox">false</lattice:attribute>
+                            <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+                            <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute>
+                            <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute>
+                            <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute>
+                            <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+                            <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+                        </lattice:attributes>
+                        <lattice:elements>
+                            <lattice:element>
+                                <lattice:name>Lane0</lattice:name>
+                                <lattice:type>DCUCHANNEL</lattice:type>
+                                <lattice:attributes>
+                                    <lattice:attribute lattice:name="ElementDrag">true</lattice:attribute>
+                                    <lattice:attribute lattice:name="ElementHide">false</lattice:attribute>
+                                    <lattice:attribute lattice:name="ElementType">DCUCHANNEL</lattice:attribute>
+                                    <lattice:attribute lattice:name="Locate">6</lattice:attribute>
+                                </lattice:attributes>
+                            </lattice:element>
+                        </lattice:elements>
+                        <lattice:lpc>
+                            <lattice:lpcsection lattice:name="Device"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Family</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">ecp5um</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>OperatingCondition</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Package</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">CABGA756</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PartName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F-8BG756C</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PartType</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SpeedGrade</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Status</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">P</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="IP"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">PCS</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreRevision</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">8.2</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreStatus</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreType</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Date</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">04/29/2019</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ModuleName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">PCSD</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SourceFormat</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">vhdl</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Time</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">14:57:43</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>VendorName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="Parameters"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>;ACHARA</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>;ACHARB</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>;ACHARM</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>;RXMCAENABLE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CDRLOLACTION</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Full Recalibration</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CDRLOLRANGE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CDR_MAX_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1.25</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CDR_MULT</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">10X</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CDR_REF_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">125.0000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CH_MODE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Rx and Tx</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Destination</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>EDIF</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Expression</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">BusA(0 to 7)</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>IO</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>IO_TYPE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">GbE</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>LEQ</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>LOOPBACK</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>LOSPORT</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>NUM_CHS</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Order</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PPORT_RX_RDY</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PPORT_TX_RDY</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PROTOCOL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">GbE</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PWAIT_RX_RDY</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">3000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PWAIT_TX_RDY</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">3000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RCSRC</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>REFCLK_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">125.0000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RSTSEQSEL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RX8B10B</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCOMMAA</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1010000011</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCOMMAB</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0101111100</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCOMMAM</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1111111111</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCOUPLING</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">AC</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCTC</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCTCBYTEN</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCTCBYTEN1</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCTCBYTEN2</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1 BCH</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCTCBYTEN3</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0 50H</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCTCMATCHPATTERN</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">M2-S2</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXDIFFTERM</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">50 ohms</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXFIFO_ENABLE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXINVPOL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Non-invert</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXLDR</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Off</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXLOSTHRESHOLD</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">2</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXLSM</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXSC</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">K28P5</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXWA</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Barrel Shift</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RX_DATA_WIDTH</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">8/10-Bit</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RX_FICLK_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">125.0000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RX_LINE_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1.2500</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RX_RATE_DIV</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Full Rate</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SCIPORT</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SOFTLOL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TX8B10B</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXAMPLITUDE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1100</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXDEPOST</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXDEPRE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXDIFFTERM</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">50 ohms</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXFIFO_ENABLE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXINVPOL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Non-invert</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXLDR</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Off</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXPLLLOLTHRESHOLD</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXPLLMULT</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">10X</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TX_DATA_WIDTH</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">8/10-Bit</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TX_FICLK_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">125.0000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TX_LINE_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1.2500</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TX_MAX_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1.25</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TX_RATE_DIV</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Full Rate</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>VHDL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Verilog</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="FilesGenerated"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PCSD.pp</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">pp</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PCSD.sym</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">sym</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PCSD.tft</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">tft</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PCSD.txt</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">pcs_module</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                        </lattice:lpc>
+                        <lattice:groups>
+                            <lattice:group>
+                                <lattice:name>DCUCHANNEL</lattice:name>
+                                <lattice:category>1</lattice:category>
+                                <lattice:attributes>
+                                    <lattice:attribute lattice:name="GroupDrag">true</lattice:attribute>
+                                    <lattice:attribute lattice:name="GroupHide">false</lattice:attribute>
+                                    <lattice:attribute lattice:name="GroupType">DCUCHANNEL</lattice:attribute>
+                                </lattice:attributes>
+                                <lattice:elementref>Lane0</lattice:elementref>
+                            </lattice:group>
+                        </lattice:groups>
+                    </spirit:vendorExtensions>
+                </spirit:componentRef>
+            </spirit:componentInstance>
+            <spirit:componentInstance>
+                <spirit:instanceName>pll_in125_out125_out33</spirit:instanceName>
+                <spirit:componentRef>
+                    <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
+                    <spirit:library>LEGACY</spirit:library>
+                    <spirit:name>PLL</spirit:name>
+                    <spirit:version>5.8</spirit:version>
+                    <spirit:fileSets>
+                        <spirit:fileset>
+                            <spirit:name>Diamond_Simulation</spirit:name>
+                            <spirit:group>simulation</spirit:group>
+                            <spirit:file>
+                                <spirit:name>./pll_in125_out125_out33/pll_in125_out125_out33.vhd</spirit:name>
+                                <spirit:fileType>vhdlSource</spirit:fileType>
+                            </spirit:file>
+                        </spirit:fileset>
+                        <spirit:fileset>
+                            <spirit:name>Diamond_Synthesis</spirit:name>
+                            <spirit:group>synthesis</spirit:group>
+                            <spirit:file>
+                                <spirit:name>./pll_in125_out125_out33/pll_in125_out125_out33.vhd</spirit:name>
+                                <spirit:fileType>vhdlSource</spirit:fileType>
+                            </spirit:file>
+                        </spirit:fileset>
+                    </spirit:fileSets>
+                    <spirit:componentGenerators>
+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>Configuration</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
+                            <spirit:group>CONFIG</spirit:group>
+                        </spirit:componentGenerator>
+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>CreateNGD</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_ngd.tcl</spirit:generatorExe>
+                            <spirit:group>CONFIG</spirit:group>
+                        </spirit:componentGenerator>
+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>Generation</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
+                            <spirit:group>GENERATE</spirit:group>
+                        </spirit:componentGenerator>
+                    </spirit:componentGenerators>
+                    <spirit:model>
+                        <spirit:views/>
+                        <spirit:ports>
+                            <spirit:port>
+                                <spirit:name>CLKI</spirit:name>
+                                <spirit:displayName>CLKI</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>CLKOP</spirit:name>
+                                <spirit:displayName>CLKOP</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>CLKOS</spirit:name>
+                                <spirit:displayName>CLKOS</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>LOCK</spirit:name>
+                                <spirit:displayName>LOCK</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                        </spirit:ports>
+                    </spirit:model>
+                    <spirit:vendorExtensions>
+                        <lattice:synthesis>synplify</lattice:synthesis>
+                        <lattice:modified>2019-05-10.04:50:40 PM</lattice:modified>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+                            <lattice:attribute lattice:name="BBox">false</lattice:attribute>
+                            <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeConfig">true</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+                            <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute>
+                            <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute>
+                            <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute>
+                            <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+                            <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+                        </lattice:attributes>
+                        <lattice:elements/>
+                        <lattice:lpc>
+                            <lattice:lpcsection lattice:name="Device"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Family</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">ecp5um</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>OperatingCondition</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Package</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">CABGA756</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PartName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F-8BG756C</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PartType</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SpeedGrade</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Status</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">P</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="IP"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">PLL</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreRevision</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">5.8</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreStatus</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreType</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Date</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">05/10/2019</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ModuleName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">pll_in125_out125_out33</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SourceFormat</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">vhdl</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Time</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">15:07:09</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>VendorName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="Parameters"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKFB_DIV</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">4</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKI_DIV</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">15</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKI_FREQ</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">125</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOP_ACTUAL_FREQ</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">125.000000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOP_APHASE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOP_DIV</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOP_DPHASE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOP_FREQ</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">125</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOP_MUXA</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">ENABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOP_TOL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0.0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOP_TRIM_DELAY</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOP_TRIM_POL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS2_ACTUAL_FREQ</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS2_APHASE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS2_DIV</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS2_DPHASE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS2_Enable</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS2_FREQ</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">100.00</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS2_MUXC</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS2_TOL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0.0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS2_TRIM_DELAY</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS2_TRIM_POL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS3_ACTUAL_FREQ</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS3_APHASE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS3_DIV</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS3_DPHASE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS3_Enable</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS3_FREQ</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">100.00</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS3_MUXD</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS3_TOL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0.0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS3_TRIM_DELAY</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS3_TRIM_POL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS_ACTUAL_FREQ</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">33.333333</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS_APHASE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS_DIV</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">18</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS_DPHASE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS_Enable</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">ENABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS_FREQ</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">33.3333333333</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS_MUXB</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS_TOL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0.1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS_TRIM_DELAY</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKOS_TRIM_POL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CLKSEL_ENA</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>DPHASE_SOURCE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">STATIC</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Destination</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>EDIF</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ENABLE_CLKOP</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ENABLE_CLKOS</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ENABLE_CLKOS2</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ENABLE_CLKOS3</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ENABLE_HBW</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Expression</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">BusA(0 to 7)</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>FEEDBK_PATH</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">INT_OS</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>FRACN_DIV</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>FRACN_ENABLE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>IO</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>IOBUF</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LVDS</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Order</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PLLRST_ENA</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PLL_BW</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0.955</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PLL_LOCK_MODE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">ENABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PLL_LOCK_STK</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PLL_USE_SMI</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>REFERENCE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>STDBY_ENABLE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>VCO_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">600.000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>VHDL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Verilog</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="Command"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>cmd_line</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">-w -n pll_in125_out125_out33 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 125 -bypassp -fclkos 33.3333333333 -fclkos_tol 0.1 -phase_cntl STATIC -lock -fb_mode 6</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                        </lattice:lpc>
+                        <lattice:groups/>
+                    </spirit:vendorExtensions>
+                </spirit:componentRef>
+            </spirit:componentInstance>
+            <spirit:componentInstance>
+                <spirit:instanceName>sgmii_channel_smi</spirit:instanceName>
+                <spirit:componentRef>
+                    <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
+                    <spirit:library>LEGACY</spirit:library>
+                    <spirit:name>SGMII/Gb Ethernet PCS</spirit:name>
+                    <spirit:version>4.1</spirit:version>
+                    <spirit:fileSets>
+                        <spirit:fileset>
+                            <spirit:name>Diamond_Simulation</spirit:name>
+                            <spirit:group>simulation</spirit:group>
+                            <spirit:file>
+                                <spirit:name>./sgmii_channel_smi/sgmii_channel_smi.v</spirit:name>
+                                <spirit:fileType>verilogSource</spirit:fileType>
+                            </spirit:file>
+                            <spirit:file>
+                                <spirit:name>./sgmii_channel_smi/sgmii_channel_smi.vhd</spirit:name>
+                                <spirit:fileType>vhdlSource</spirit:fileType>
+                            </spirit:file>
+                            <spirit:file>
+                                <spirit:name>./sgmii_channel_smi/sgmii_channel_smi_core_bb.v</spirit:name>
+                                <spirit:fileType>verilogSource</spirit:fileType>
+                            </spirit:file>
+                            <spirit:file>
+                                <spirit:name>./sgmii_channel_smi/sgmii_channel_smi_pcs_bb.v</spirit:name>
+                                <spirit:fileType>verilogSource</spirit:fileType>
+                            </spirit:file>
+                            <spirit:file>
+                                <spirit:name>./sgmii_channel_smi/sgmii_channel_smi.v</spirit:name>
+                                <spirit:fileType>verilogSource</spirit:fileType>
+                            </spirit:file>
+                            <spirit:file>
+                                <spirit:name>./sgmii_channel_smi/sgmii_channel_smi.vhd</spirit:name>
+                                <spirit:fileType>vhdlSource</spirit:fileType>
+                            </spirit:file>
+                            <spirit:file>
+                                <spirit:name>./sgmii_channel_smi/sgmii_channel_smi_core_bb.v</spirit:name>
+                                <spirit:fileType>verilogSource</spirit:fileType>
+                            </spirit:file>
+                            <spirit:file>
+                                <spirit:name>./sgmii_channel_smi/sgmii_channel_smi_pcs_bb.v</spirit:name>
+                                <spirit:fileType>verilogSource</spirit:fileType>
+                            </spirit:file>
+                        </spirit:fileset>
+                        <spirit:fileset>
+                            <spirit:name>Diamond_Synthesis</spirit:name>
+                            <spirit:group>synthesis</spirit:group>
+                            <spirit:file>
+                                <spirit:name>./sgmii_channel_smi/sgmii_channel_smi.v</spirit:name>
+                                <spirit:fileType>verilogSource</spirit:fileType>
+                            </spirit:file>
+                            <spirit:file>
+                                <spirit:name>./sgmii_channel_smi/sgmii_channel_smi.vhd</spirit:name>
+                                <spirit:fileType>vhdlSource</spirit:fileType>
+                            </spirit:file>
+                            <spirit:file>
+                                <spirit:name>./sgmii_channel_smi/sgmii_channel_smi_core_bb.v</spirit:name>
+                                <spirit:fileType>verilogSource</spirit:fileType>
+                            </spirit:file>
+                            <spirit:file>
+                                <spirit:name>./sgmii_channel_smi/sgmii_pcs_eval/models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs_softlogic.v</spirit:name>
+                                <spirit:fileType>verilogSource</spirit:fileType>
+                            </spirit:file>
+                            <spirit:file>
+                                <spirit:name>./sgmii_channel_smi/sgmii_pcs_eval/models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs.v</spirit:name>
+                                <spirit:fileType>verilogSource</spirit:fileType>
+                            </spirit:file>
+                            <spirit:file>
+                                <spirit:name>./sgmii_channel_smi/sgmii_channel_smi_core.ngo</spirit:name>
+                                <spirit:userFileType>NGO</spirit:userFileType>
+                            </spirit:file>
+                            <spirit:file>
+                                <spirit:name>./sgmii_channel_smi/sgmii_channel_smi.v</spirit:name>
+                                <spirit:fileType>verilogSource</spirit:fileType>
+                            </spirit:file>
+                            <spirit:file>
+                                <spirit:name>./sgmii_channel_smi/sgmii_channel_smi.vhd</spirit:name>
+                                <spirit:fileType>vhdlSource</spirit:fileType>
+                            </spirit:file>
+                            <spirit:file>
+                                <spirit:name>./sgmii_channel_smi/sgmii_channel_smi_core_bb.v</spirit:name>
+                                <spirit:fileType>verilogSource</spirit:fileType>
+                            </spirit:file>
+                            <spirit:file>
+                                <spirit:name>./sgmii_channel_smi/sgmii_pcs_eval/models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs_softlogic.v</spirit:name>
+                                <spirit:fileType>verilogSource</spirit:fileType>
+                            </spirit:file>
+                            <spirit:file>
+                                <spirit:name>./sgmii_channel_smi/sgmii_pcs_eval/models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs.v</spirit:name>
+                                <spirit:fileType>verilogSource</spirit:fileType>
+                            </spirit:file>
+                            <spirit:file>
+                                <spirit:name>./sgmii_channel_smi/sgmii_channel_smi_core.ngo</spirit:name>
+                                <spirit:userFileType>NGO</spirit:userFileType>
+                            </spirit:file>
+                        </spirit:fileset>
+                    </spirit:fileSets>
+                    <spirit:componentGenerators>
+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>Configuration</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
+                            <spirit:group>CONFIG</spirit:group>
+                        </spirit:componentGenerator>
+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>CreateNGD</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_ngd.tcl</spirit:generatorExe>
+                            <spirit:group>CONFIG</spirit:group>
+                        </spirit:componentGenerator>
+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>Generation</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
+                            <spirit:group>GENERATE</spirit:group>
+                        </spirit:componentGenerator>
+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>NGDGeneration</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_ngd.tcl</spirit:generatorExe>
+                            <spirit:group>GENERATE</spirit:group>
+                        </spirit:componentGenerator>
+                    </spirit:componentGenerators>
+                    <spirit:model>
+                        <spirit:views/>
+                        <spirit:ports>
+                            <spirit:port>
+                                <spirit:name>an_link_ok</spirit:name>
+                                <spirit:displayName>an_link_ok</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>col</spirit:name>
+                                <spirit:displayName>col</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>crs</spirit:name>
+                                <spirit:displayName>crs</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>cyawstn</spirit:name>
+                                <spirit:displayName>cyawstn</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>debug_link_timer_short</spirit:name>
+                                <spirit:displayName>debug_link_timer_short</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>force_isolate</spirit:name>
+                                <spirit:displayName>force_isolate</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>force_loopback</spirit:name>
+                                <spirit:displayName>force_loopback</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>force_unidir</spirit:name>
+                                <spirit:displayName>force_unidir</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>gbe_mode</spirit:name>
+                                <spirit:displayName>gbe_mode</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>hdinn</spirit:name>
+                                <spirit:displayName>hdinn</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>hdinp</spirit:name>
+                                <spirit:displayName>hdinp</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>hdoutn</spirit:name>
+                                <spirit:displayName>hdoutn</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>hdoutp</spirit:name>
+                                <spirit:displayName>hdoutp</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>mr_an_complete</spirit:name>
+                                <spirit:displayName>mr_an_complete</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>mr_an_enable</spirit:name>
+                                <spirit:displayName>mr_an_enable</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>mr_main_reset</spirit:name>
+                                <spirit:displayName>mr_main_reset</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>mr_page_rx</spirit:name>
+                                <spirit:displayName>mr_page_rx</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>mr_power_down</spirit:name>
+                                <spirit:displayName>mr_power_down</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>mr_restart_an</spirit:name>
+                                <spirit:displayName>mr_restart_an</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>pll_lol</spirit:name>
+                                <spirit:displayName>pll_lol</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>pll_refclki</spirit:name>
+                                <spirit:displayName>pll_refclki</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rst_dual_c</spirit:name>
+                                <spirit:displayName>rst_dual_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rst_n</spirit:name>
+                                <spirit:displayName>rst_n</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_cdr_lol_s</spirit:name>
+                                <spirit:displayName>rx_cdr_lol_s</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_clk_125</spirit:name>
+                                <spirit:displayName>rx_clk_125</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_clock_enable_sink</spirit:name>
+                                <spirit:displayName>rx_clock_enable_sink</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_clock_enable_source</spirit:name>
+                                <spirit:displayName>rx_clock_enable_source</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_dv</spirit:name>
+                                <spirit:displayName>rx_dv</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_er</spirit:name>
+                                <spirit:displayName>rx_er</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_pcs_rst_c</spirit:name>
+                                <spirit:displayName>rx_pcs_rst_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_serdes_rst_c</spirit:name>
+                                <spirit:displayName>rx_serdes_rst_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rxrefclk</spirit:name>
+                                <spirit:displayName>rxrefclk</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_en</spirit:name>
+                                <spirit:displayName>sci_en</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_en_dual</spirit:name>
+                                <spirit:displayName>sci_en_dual</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_int</spirit:name>
+                                <spirit:displayName>sci_int</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_rd</spirit:name>
+                                <spirit:displayName>sci_rd</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_sel</spirit:name>
+                                <spirit:displayName>sci_sel</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_sel_dual</spirit:name>
+                                <spirit:displayName>sci_sel_dual</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_wrn</spirit:name>
+                                <spirit:displayName>sci_wrn</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>serdes_pdb</spirit:name>
+                                <spirit:displayName>serdes_pdb</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>serdes_rst_dual_c</spirit:name>
+                                <spirit:displayName>serdes_rst_dual_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sgmii_mode</spirit:name>
+                                <spirit:displayName>sgmii_mode</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sli_rst</spirit:name>
+                                <spirit:displayName>sli_rst</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                                <spirit:vendorExtensions>
+                                    <lattice:attributes>
+                                        <lattice:attribute lattice:name="Hide">true</lattice:attribute>
+                                    </lattice:attributes>
+                                </spirit:vendorExtensions>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_clk_125</spirit:name>
+                                <spirit:displayName>tx_clk_125</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_clock_enable_sink</spirit:name>
+                                <spirit:displayName>tx_clock_enable_sink</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_clock_enable_source</spirit:name>
+                                <spirit:displayName>tx_clock_enable_source</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_en</spirit:name>
+                                <spirit:displayName>tx_en</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_er</spirit:name>
+                                <spirit:displayName>tx_er</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_pcs_rst_c</spirit:name>
+                                <spirit:displayName>tx_pcs_rst_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_pwrup_c</spirit:name>
+                                <spirit:displayName>tx_pwrup_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_serdes_rst_c</spirit:name>
+                                <spirit:displayName>tx_serdes_rst_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>mr_adv_ability</spirit:name>
+                                <spirit:displayName>mr_adv_ability</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>15</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>mr_lp_adv_ability</spirit:name>
+                                <spirit:displayName>mr_lp_adv_ability</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>15</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>operational_rate</spirit:name>
+                                <spirit:displayName>operational_rate</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>1</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_d</spirit:name>
+                                <spirit:displayName>rx_d</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>7</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_addr</spirit:name>
+                                <spirit:displayName>sci_addr</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>5</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_rddata</spirit:name>
+                                <spirit:displayName>sci_rddata</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>7</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_wrdata</spirit:name>
+                                <spirit:displayName>sci_wrdata</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>7</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_d</spirit:name>
+                                <spirit:displayName>tx_d</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>7</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                        </spirit:ports>
+                    </spirit:model>
+                    <spirit:vendorExtensions>
+                        <lattice:synthesis>synplify</lattice:synthesis>
+                        <lattice:date>2013-09-22.14:14:33</lattice:date>
+                        <lattice:modified>2019-05-10.04:50:40 PM</lattice:modified>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+                            <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+                            <lattice:attribute lattice:name="CoreType">IPCFG</lattice:attribute>
+                            <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute>
+                            <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute>
+                            <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+                            <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+                            <lattice:attribute lattice:name="Resource"></lattice:attribute>
+                        </lattice:attributes>
+                        <lattice:elements>
+                            <lattice:element>
+                                <lattice:name>Lane0</lattice:name>
+                                <lattice:type>DCUCHANNEL</lattice:type>
+                                <lattice:attributes>
+                                    <lattice:attribute lattice:name="ElementDrag">true</lattice:attribute>
+                                    <lattice:attribute lattice:name="ElementHide">false</lattice:attribute>
+                                    <lattice:attribute lattice:name="ElementType">DCUCHANNEL</lattice:attribute>
+                                    <lattice:attribute lattice:name="Locate">5</lattice:attribute>
+                                </lattice:attributes>
+                            </lattice:element>
+                        </lattice:elements>
+                        <lattice:lpc>
+                            <lattice:lpcsection lattice:name="Device"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Family</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">sa5p00m</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>OperatingCondition</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Package</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">CABGA756</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PartName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F-8BG756C</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PartType</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SpeedGrade</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Status</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">P</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="IP"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">SGMII/Gb Ethernet PCS</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreRevision</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">4.1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreStatus</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreType</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">IPCFG</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Date</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">04/29/2019</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ModuleName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">sgmii_channel_smi</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SourceFormat</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">vhdl</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Time</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">14:09:14</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>VendorName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="Parameters"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CH_MODE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Rx and Tx</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CORE_SYNP</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Channel</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">CH0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>DCUA</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">DCU0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>EasyConnect</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>MAX_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1.250</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>NUM_CHS</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PROTOCOL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">SGMII</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>REFCLK_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">125.0000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RX_CTC</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">2</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RX_CTC_HIGH</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">32</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RX_CTC_LOW</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">16</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SBP</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TX_MAX_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">2.5</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                        </lattice:lpc>
+                        <lattice:groups>
+                            <lattice:group>
+                                <lattice:name>DCUCHANNEL</lattice:name>
+                                <lattice:category>1</lattice:category>
+                                <lattice:attributes>
+                                    <lattice:attribute lattice:name="GroupDrag">true</lattice:attribute>
+                                    <lattice:attribute lattice:name="GroupHide">false</lattice:attribute>
+                                    <lattice:attribute lattice:name="GroupType">DCUCHANNEL</lattice:attribute>
+                                </lattice:attributes>
+                                <lattice:elementref>Lane0</lattice:elementref>
+                            </lattice:group>
+                        </lattice:groups>
+                    </spirit:vendorExtensions>
+                </spirit:componentRef>
+            </spirit:componentInstance>
+            <spirit:componentInstance>
+                <spirit:instanceName>sgmii_ecp5</spirit:instanceName>
+                <spirit:componentRef>
+                    <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
+                    <spirit:library>LEGACY</spirit:library>
+                    <spirit:name>PCS</spirit:name>
+                    <spirit:version>8.2</spirit:version>
+                    <spirit:fileSets>
+                        <spirit:fileset>
+                            <spirit:name>Diamond_Simulation</spirit:name>
+                            <spirit:group>simulation</spirit:group>
+                            <spirit:file>
+                                <spirit:name>./sgmii_ecp5/sgmii_ecp5_softlogic.v</spirit:name>
+                                <spirit:fileType>verilogSource</spirit:fileType>
+                            </spirit:file>
+                            <spirit:file>
+                                <spirit:name>./sgmii_ecp5/sgmii_ecp5.vhd</spirit:name>
+                                <spirit:fileType>vhdlSource</spirit:fileType>
+                            </spirit:file>
+                        </spirit:fileset>
+                        <spirit:fileset>
+                            <spirit:name>Diamond_Synthesis</spirit:name>
+                            <spirit:group>synthesis</spirit:group>
+                            <spirit:file>
+                                <spirit:name>./sgmii_ecp5/sgmii_ecp5_softlogic.v</spirit:name>
+                                <spirit:fileType>verilogSource</spirit:fileType>
+                            </spirit:file>
+                            <spirit:file>
+                                <spirit:name>./sgmii_ecp5/sgmii_ecp5.vhd</spirit:name>
+                                <spirit:fileType>vhdlSource</spirit:fileType>
+                            </spirit:file>
+                        </spirit:fileset>
+                    </spirit:fileSets>
+                    <spirit:componentGenerators>
+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>Configuration</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
+                            <spirit:group>CONFIG</spirit:group>
+                        </spirit:componentGenerator>
+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>CreateNGD</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_ngd.tcl</spirit:generatorExe>
+                            <spirit:group>CONFIG</spirit:group>
+                        </spirit:componentGenerator>
+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>Generation</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
+                            <spirit:group>GENERATE</spirit:group>
+                        </spirit:componentGenerator>
+                    </spirit:componentGenerators>
+                    <spirit:model>
+                        <spirit:views/>
+                        <spirit:ports>
+                            <spirit:port>
+                                <spirit:name>ctc_del_s</spirit:name>
+                                <spirit:displayName>ctc_del_s</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>ctc_ins_s</spirit:name>
+                                <spirit:displayName>ctc_ins_s</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>ctc_orun_s</spirit:name>
+                                <spirit:displayName>ctc_orun_s</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>ctc_urun_s</spirit:name>
+                                <spirit:displayName>ctc_urun_s</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>cyawstn</spirit:name>
+                                <spirit:displayName>cyawstn</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>hdinn</spirit:name>
+                                <spirit:displayName>hdinn</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                                <spirit:vendorExtensions>
+                                    <lattice:attributes>
+                                        <lattice:attribute lattice:name="PadPin">true</lattice:attribute>
+                                    </lattice:attributes>
+                                </spirit:vendorExtensions>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>hdinp</spirit:name>
+                                <spirit:displayName>hdinp</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                                <spirit:vendorExtensions>
+                                    <lattice:attributes>
+                                        <lattice:attribute lattice:name="PadPin">true</lattice:attribute>
+                                    </lattice:attributes>
+                                </spirit:vendorExtensions>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>hdoutn</spirit:name>
+                                <spirit:displayName>hdoutn</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                                <spirit:vendorExtensions>
+                                    <lattice:attributes>
+                                        <lattice:attribute lattice:name="PadPin">true</lattice:attribute>
+                                    </lattice:attributes>
+                                </spirit:vendorExtensions>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>hdoutp</spirit:name>
+                                <spirit:displayName>hdoutp</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                                <spirit:vendorExtensions>
+                                    <lattice:attributes>
+                                        <lattice:attribute lattice:name="PadPin">true</lattice:attribute>
+                                    </lattice:attributes>
+                                </spirit:vendorExtensions>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>lsm_status_s</spirit:name>
+                                <spirit:displayName>lsm_status_s</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>pll_lol</spirit:name>
+                                <spirit:displayName>pll_lol</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>pll_refclki</spirit:name>
+                                <spirit:displayName>pll_refclki</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rsl_disable</spirit:name>
+                                <spirit:displayName>rsl_disable</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rsl_rst</spirit:name>
+                                <spirit:displayName>rsl_rst</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rsl_rx_rdy</spirit:name>
+                                <spirit:displayName>rsl_rx_rdy</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rsl_tx_rdy</spirit:name>
+                                <spirit:displayName>rsl_tx_rdy</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rst_dual_c</spirit:name>
+                                <spirit:displayName>rst_dual_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_cdr_lol_s</spirit:name>
+                                <spirit:displayName>rx_cdr_lol_s</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_los_low_s</spirit:name>
+                                <spirit:displayName>rx_los_low_s</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_pcs_rst_c</spirit:name>
+                                <spirit:displayName>rx_pcs_rst_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_pwrup_c</spirit:name>
+                                <spirit:displayName>rx_pwrup_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_serdes_rst_c</spirit:name>
+                                <spirit:displayName>rx_serdes_rst_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rxrefclk</spirit:name>
+                                <spirit:displayName>rxrefclk</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_en</spirit:name>
+                                <spirit:displayName>sci_en</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_en_dual</spirit:name>
+                                <spirit:displayName>sci_en_dual</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_int</spirit:name>
+                                <spirit:displayName>sci_int</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_rd</spirit:name>
+                                <spirit:displayName>sci_rd</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_sel</spirit:name>
+                                <spirit:displayName>sci_sel</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_sel_dual</spirit:name>
+                                <spirit:displayName>sci_sel_dual</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_wrn</spirit:name>
+                                <spirit:displayName>sci_wrn</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>serdes_pdb</spirit:name>
+                                <spirit:displayName>serdes_pdb</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>serdes_rst_dual_c</spirit:name>
+                                <spirit:displayName>serdes_rst_dual_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>signal_detect_c</spirit:name>
+                                <spirit:displayName>signal_detect_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sli_rst</spirit:name>
+                                <spirit:displayName>sli_rst</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                                <spirit:vendorExtensions>
+                                    <lattice:attributes>
+                                        <lattice:attribute lattice:name="Hide">true</lattice:attribute>
+                                    </lattice:attributes>
+                                </spirit:vendorExtensions>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_pclk</spirit:name>
+                                <spirit:displayName>tx_pclk</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_pcs_rst_c</spirit:name>
+                                <spirit:displayName>tx_pcs_rst_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_pwrup_c</spirit:name>
+                                <spirit:displayName>tx_pwrup_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_serdes_rst_c</spirit:name>
+                                <spirit:displayName>tx_serdes_rst_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>txi_clk</spirit:name>
+                                <spirit:displayName>txi_clk</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_cv_err</spirit:name>
+                                <spirit:displayName>rx_cv_err</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>0</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_disp_err</spirit:name>
+                                <spirit:displayName>rx_disp_err</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>0</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_k</spirit:name>
+                                <spirit:displayName>rx_k</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>0</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rxdata</spirit:name>
+                                <spirit:displayName>rxdata</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>7</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_addr</spirit:name>
+                                <spirit:displayName>sci_addr</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>5</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_rddata</spirit:name>
+                                <spirit:displayName>sci_rddata</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>7</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_wrdata</spirit:name>
+                                <spirit:displayName>sci_wrdata</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>7</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_disp_correct</spirit:name>
+                                <spirit:displayName>tx_disp_correct</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>0</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_k</spirit:name>
+                                <spirit:displayName>tx_k</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>0</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>txdata</spirit:name>
+                                <spirit:displayName>txdata</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>7</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>xmit</spirit:name>
+                                <spirit:displayName>xmit</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>0</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                        </spirit:ports>
+                    </spirit:model>
+                    <spirit:vendorExtensions>
+                        <lattice:synthesis>synplify</lattice:synthesis>
+                        <lattice:modified>2019-05-10.04:50:40 PM</lattice:modified>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+                            <lattice:attribute lattice:name="BBox">false</lattice:attribute>
+                            <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+                            <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute>
+                            <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute>
+                            <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute>
+                            <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+                            <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+                        </lattice:attributes>
+                        <lattice:elements>
+                            <lattice:element>
+                                <lattice:name>Lane0</lattice:name>
+                                <lattice:type>DCUCHANNEL</lattice:type>
+                                <lattice:attributes>
+                                    <lattice:attribute lattice:name="ElementDrag">true</lattice:attribute>
+                                    <lattice:attribute lattice:name="ElementHide">false</lattice:attribute>
+                                    <lattice:attribute lattice:name="ElementType">DCUCHANNEL</lattice:attribute>
+                                    <lattice:attribute lattice:name="Locate">9</lattice:attribute>
+                                </lattice:attributes>
+                            </lattice:element>
+                        </lattice:elements>
+                        <lattice:lpc>
+                            <lattice:lpcsection lattice:name="Device"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Family</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">ecp5um</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>OperatingCondition</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Package</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">CABGA756</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PartName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F-8BG756C</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PartType</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SpeedGrade</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Status</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">P</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="IP"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">PCS</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreRevision</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">8.2</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreStatus</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreType</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Date</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">05/10/2019</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ModuleName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">sgmii_ecp5</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SourceFormat</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">vhdl</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Time</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">09:02:05</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>VendorName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="Parameters"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>;ACHARA</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>;ACHARB</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>;ACHARM</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>;RXMCAENABLE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CDRLOLACTION</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Full Recalibration</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CDRLOLRANGE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CDR_MAX_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1.25</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CDR_MULT</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">10X</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CDR_REF_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">125.0000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CH_MODE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Rx and Tx</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Destination</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>EDIF</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Expression</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">BusA(0 to 7)</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>IO</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>IO_TYPE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">GbE</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>LEQ</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>LOOPBACK</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>LOSPORT</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>NUM_CHS</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Order</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PPORT_RX_RDY</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PPORT_TX_RDY</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PROTOCOL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">GbE</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PWAIT_RX_RDY</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">3000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PWAIT_TX_RDY</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">3000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RCSRC</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>REFCLK_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">125.0000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RSTSEQSEL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RX8B10B</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCOMMAA</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1010000011</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCOMMAB</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0101111100</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCOMMAM</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1111111111</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCOUPLING</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">AC</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCTC</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCTCBYTEN</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCTCBYTEN1</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCTCBYTEN2</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1 BCH</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCTCBYTEN3</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0 50H</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCTCMATCHPATTERN</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">M2-S2</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXDIFFTERM</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">50 ohms</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXFIFO_ENABLE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXINVPOL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Non-invert</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXLDR</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Off</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXLOSTHRESHOLD</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">2</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXLSM</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXSC</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">K28P5</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXWA</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Barrel Shift</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RX_DATA_WIDTH</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">8/10-Bit</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RX_FICLK_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">125.0000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RX_LINE_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1.2500</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RX_RATE_DIV</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Full Rate</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SCIPORT</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SOFTLOL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TX8B10B</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXAMPLITUDE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1100</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXDEPOST</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXDEPRE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXDIFFTERM</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">50 ohms</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXFIFO_ENABLE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXINVPOL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Non-invert</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXLDR</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Off</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXPLLLOLTHRESHOLD</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXPLLMULT</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">10X</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TX_DATA_WIDTH</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">8/10-Bit</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TX_FICLK_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">125.0000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TX_LINE_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1.2500</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TX_MAX_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1.25</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TX_RATE_DIV</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Full Rate</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>VHDL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Verilog</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="FilesGenerated"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>sgmii_ecp5.pp</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">pp</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>sgmii_ecp5.sym</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">sym</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>sgmii_ecp5.tft</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">tft</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>sgmii_ecp5.txt</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">pcs_module</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                        </lattice:lpc>
+                        <lattice:groups>
+                            <lattice:group>
+                                <lattice:name>DCUCHANNEL</lattice:name>
+                                <lattice:category>1</lattice:category>
+                                <lattice:attributes>
+                                    <lattice:attribute lattice:name="GroupDrag">true</lattice:attribute>
+                                    <lattice:attribute lattice:name="GroupHide">false</lattice:attribute>
+                                    <lattice:attribute lattice:name="GroupType">DCUCHANNEL</lattice:attribute>
+                                </lattice:attributes>
+                                <lattice:elementref>Lane0</lattice:elementref>
+                            </lattice:group>
+                        </lattice:groups>
+                    </spirit:vendorExtensions>
+                </spirit:componentRef>
+            </spirit:componentInstance>
+            <spirit:componentInstance>
+                <spirit:instanceName>tsmac</spirit:instanceName>
+                <spirit:componentRef>
+                    <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
+                    <spirit:library>LEGACY</spirit:library>
+                    <spirit:name>Tri-Speed Ethernet MAC</spirit:name>
+                    <spirit:version>4.1</spirit:version>
+                    <spirit:fileSets>
+                        <spirit:fileset>
+                            <spirit:name>Diamond_Simulation</spirit:name>
+                            <spirit:group>simulation</spirit:group>
+                            <spirit:file>
+                                <spirit:name>./tsmac/tsmac_beh.v</spirit:name>
+                                <spirit:fileType>verilogSource</spirit:fileType>
+                            </spirit:file>
+                            <spirit:file>
+                                <spirit:name>./tsmac/tsmac_beh.v</spirit:name>
+                                <spirit:fileType>verilogSource</spirit:fileType>
+                            </spirit:file>
+                        </spirit:fileset>
+                        <spirit:fileset>
+                            <spirit:name>Diamond_Synthesis</spirit:name>
+                            <spirit:group>synthesis</spirit:group>
+                            <spirit:file>
+                                <spirit:name>./tsmac/tsmac_bb.v</spirit:name>
+                                <spirit:fileType>verilogSource</spirit:fileType>
+                            </spirit:file>
+                            <spirit:file>
+                                <spirit:name>./tsmac/tsmac.ngo</spirit:name>
+                                <spirit:userFileType>NGO</spirit:userFileType>
+                            </spirit:file>
+                            <spirit:file>
+                                <spirit:name>./tsmac/tsmac_bb.v</spirit:name>
+                                <spirit:fileType>verilogSource</spirit:fileType>
+                            </spirit:file>
+                            <spirit:file>
+                                <spirit:name>./tsmac/tsmac.ngo</spirit:name>
+                                <spirit:userFileType>NGO</spirit:userFileType>
+                            </spirit:file>
+                        </spirit:fileset>
+                    </spirit:fileSets>
+                    <spirit:componentGenerators>
+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>Configuration</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
+                            <spirit:group>CONFIG</spirit:group>
+                        </spirit:componentGenerator>
+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>CreateNGD</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_ngd.tcl</spirit:generatorExe>
+                            <spirit:group>CONFIG</spirit:group>
+                        </spirit:componentGenerator>
+                    </spirit:componentGenerators>
+                    <spirit:model>
+                        <spirit:views/>
+                        <spirit:ports>
+                            <spirit:port>
+                                <spirit:name>col</spirit:name>
+                                <spirit:displayName>col</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>cpu_if_gbit_en</spirit:name>
+                                <spirit:displayName>cpu_if_gbit_en</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>crs</spirit:name>
+                                <spirit:displayName>crs</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>hclk</spirit:name>
+                                <spirit:displayName>hclk</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>hcs_n</spirit:name>
+                                <spirit:displayName>hcs_n</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>hdataout_en_n</spirit:name>
+                                <spirit:displayName>hdataout_en_n</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>hread_n</spirit:name>
+                                <spirit:displayName>hread_n</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>hready_n</spirit:name>
+                                <spirit:displayName>hready_n</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>hwrite_n</spirit:name>
+                                <spirit:displayName>hwrite_n</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>ignore_pkt</spirit:name>
+                                <spirit:displayName>ignore_pkt</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>reset_n</spirit:name>
+                                <spirit:displayName>reset_n</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_dv</spirit:name>
+                                <spirit:displayName>rx_dv</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_eof</spirit:name>
+                                <spirit:displayName>rx_eof</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_er</spirit:name>
+                                <spirit:displayName>rx_er</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_error</spirit:name>
+                                <spirit:displayName>rx_error</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_fifo_error</spirit:name>
+                                <spirit:displayName>rx_fifo_error</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_fifo_full</spirit:name>
+                                <spirit:displayName>rx_fifo_full</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_stat_en</spirit:name>
+                                <spirit:displayName>rx_stat_en</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_write</spirit:name>
+                                <spirit:displayName>rx_write</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rxmac_clk</spirit:name>
+                                <spirit:displayName>rxmac_clk</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rxmac_clk_en</spirit:name>
+                                <spirit:displayName>rxmac_clk_en</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_discfrm</spirit:name>
+                                <spirit:displayName>tx_discfrm</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_done</spirit:name>
+                                <spirit:displayName>tx_done</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_en</spirit:name>
+                                <spirit:displayName>tx_en</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_er</spirit:name>
+                                <spirit:displayName>tx_er</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_fifoavail</spirit:name>
+                                <spirit:displayName>tx_fifoavail</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_fifoctrl</spirit:name>
+                                <spirit:displayName>tx_fifoctrl</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_fifoempty</spirit:name>
+                                <spirit:displayName>tx_fifoempty</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_fifoeof</spirit:name>
+                                <spirit:displayName>tx_fifoeof</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_macread</spirit:name>
+                                <spirit:displayName>tx_macread</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_sndpausreq</spirit:name>
+                                <spirit:displayName>tx_sndpausreq</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_staten</spirit:name>
+                                <spirit:displayName>tx_staten</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>txmac_clk</spirit:name>
+                                <spirit:displayName>txmac_clk</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>txmac_clk_en</spirit:name>
+                                <spirit:displayName>txmac_clk_en</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>haddr</spirit:name>
+                                <spirit:displayName>haddr</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>7</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>hdatain</spirit:name>
+                                <spirit:displayName>hdatain</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>7</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>hdataout</spirit:name>
+                                <spirit:displayName>hdataout</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>7</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_dbout</spirit:name>
+                                <spirit:displayName>rx_dbout</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>7</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_stat_vector</spirit:name>
+                                <spirit:displayName>rx_stat_vector</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>31</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rxd</spirit:name>
+                                <spirit:displayName>rxd</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>7</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_fifodata</spirit:name>
+                                <spirit:displayName>tx_fifodata</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>7</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_sndpaustim</spirit:name>
+                                <spirit:displayName>tx_sndpaustim</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>15</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_statvec</spirit:name>
+                                <spirit:displayName>tx_statvec</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>30</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>txd</spirit:name>
+                                <spirit:displayName>txd</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>7</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                        </spirit:ports>
+                    </spirit:model>
+                    <spirit:vendorExtensions>
+                        <lattice:synthesis>synplify</lattice:synthesis>
+                        <lattice:date>2013-08-08.14:14:33</lattice:date>
+                        <lattice:modified>2019-05-10.04:50:40 PM</lattice:modified>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+                            <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+                            <lattice:attribute lattice:name="CoreType">IPCFG</lattice:attribute>
+                            <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute>
+                            <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute>
+                            <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+                            <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+                        </lattice:attributes>
+                        <lattice:elements/>
+                        <lattice:lpc>
+                            <lattice:lpcsection lattice:name="Device"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Family</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">sa5p00m</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>OperatingCondition</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Package</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">CABGA756</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PartName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F-8BG756C</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PartType</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SpeedGrade</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Status</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">P</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="IP"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Tri-Speed Ethernet MAC</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreRevision</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">4.1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreStatus</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreType</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">IPCFG</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Date</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">04/29/2019</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ModuleName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">tsmac</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SourceFormat</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">vhdl</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Time</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">13:44:50</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>VendorName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="Parameters"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ALDC_TOOL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CORE_SYNP</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>LOOPBACK</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">NO</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>MIIM</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">No</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>MODE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">SGMII easy connect</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>MODS_TOOL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>MULT_WB</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">NO</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>STAT_REGS</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">NO</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="Files"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Logical</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Misc</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Physical</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Simulation</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Synthesis</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+                            </lattice:lpcentry>
+                        </lattice:lpc>
+                        <lattice:groups/>
+                    </spirit:vendorExtensions>
+                </spirit:componentRef>
+            </spirit:componentInstance>
+        </spirit:componentInstances>
+        <spirit:adHocConnections>
+            <spirit:adHocConnection>
+                <spirit:name>PCSD_sgmii_channel_smi_pll_lol</spirit:name>
+                <spirit:displayName>PCSD_sgmii_channel_smi_pll_lol</spirit:displayName>
+                <spirit:description>PCSD_sgmii_channel_smi_pll_lol</spirit:description>
+                <spirit:vendorExtensions>
+                    <lattice:attributes>
+                        <lattice:attribute lattice:name="dualport">pll_lol</lattice:attribute>
+                        <lattice:attribute lattice:name="primitive">DCU</lattice:attribute>
+                        <lattice:attribute lattice:name="type">short</lattice:attribute>
+                    </lattice:attributes>
+                </spirit:vendorExtensions>
+                <spirit:internalPortReference spirit:portRef="pll_lol" spirit:componentRef="PCSD"/>
+                <spirit:internalPortReference spirit:portRef="pll_lol" spirit:componentRef="sgmii_channel_smi"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>PCSD_sgmii_channel_smi_pll_refclki</spirit:name>
+                <spirit:displayName>PCSD_sgmii_channel_smi_pll_refclki</spirit:displayName>
+                <spirit:description>PCSD_sgmii_channel_smi_pll_refclki</spirit:description>
+                <spirit:vendorExtensions>
+                    <lattice:attributes>
+                        <lattice:attribute lattice:name="dualport">pll_refclki</lattice:attribute>
+                        <lattice:attribute lattice:name="primitive">DCU</lattice:attribute>
+                        <lattice:attribute lattice:name="type">short</lattice:attribute>
+                    </lattice:attributes>
+                </spirit:vendorExtensions>
+                <spirit:internalPortReference spirit:portRef="pll_refclki" spirit:componentRef="PCSD"/>
+                <spirit:internalPortReference spirit:portRef="pll_refclki" spirit:componentRef="sgmii_channel_smi"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>PCSD_sgmii_channel_smi_serdes_pdb</spirit:name>
+                <spirit:displayName>PCSD_sgmii_channel_smi_serdes_pdb</spirit:displayName>
+                <spirit:description>PCSD_sgmii_channel_smi_serdes_pdb</spirit:description>
+                <spirit:vendorExtensions>
+                    <lattice:attributes>
+                        <lattice:attribute lattice:name="dualport">serdes_pdb</lattice:attribute>
+                        <lattice:attribute lattice:name="primitive">DCU</lattice:attribute>
+                        <lattice:attribute lattice:name="type">short</lattice:attribute>
+                    </lattice:attributes>
+                </spirit:vendorExtensions>
+                <spirit:internalPortReference spirit:portRef="serdes_pdb" spirit:componentRef="PCSD"/>
+                <spirit:internalPortReference spirit:portRef="serdes_pdb" spirit:componentRef="sgmii_channel_smi"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>PCSD_hdinn</spirit:name>
+                <spirit:displayName>PCSD_hdinn</spirit:displayName>
+                <spirit:vendorExtensions>
+                    <lattice:attributes>
+                        <lattice:attribute lattice:name="export">sys_yes</lattice:attribute>
+                    </lattice:attributes>
+                </spirit:vendorExtensions>
+                <spirit:internalPortReference spirit:portRef="hdinn" spirit:componentRef="PCSD"/>
+                <spirit:externalPortReference spirit:portRef="PCSD_hdinn"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>PCSD_hdinp</spirit:name>
+                <spirit:displayName>PCSD_hdinp</spirit:displayName>
+                <spirit:vendorExtensions>
+                    <lattice:attributes>
+                        <lattice:attribute lattice:name="export">sys_yes</lattice:attribute>
+                    </lattice:attributes>
+                </spirit:vendorExtensions>
+                <spirit:internalPortReference spirit:portRef="hdinp" spirit:componentRef="PCSD"/>
+                <spirit:externalPortReference spirit:portRef="PCSD_hdinp"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>PCSD_hdoutn</spirit:name>
+                <spirit:displayName>PCSD_hdoutn</spirit:displayName>
+                <spirit:vendorExtensions>
+                    <lattice:attributes>
+                        <lattice:attribute lattice:name="export">sys_yes</lattice:attribute>
+                    </lattice:attributes>
+                </spirit:vendorExtensions>
+                <spirit:internalPortReference spirit:portRef="hdoutn" spirit:componentRef="PCSD"/>
+                <spirit:externalPortReference spirit:portRef="PCSD_hdoutn"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>PCSD_hdoutp</spirit:name>
+                <spirit:displayName>PCSD_hdoutp</spirit:displayName>
+                <spirit:vendorExtensions>
+                    <lattice:attributes>
+                        <lattice:attribute lattice:name="export">sys_yes</lattice:attribute>
+                    </lattice:attributes>
+                </spirit:vendorExtensions>
+                <spirit:internalPortReference spirit:portRef="hdoutp" spirit:componentRef="PCSD"/>
+                <spirit:externalPortReference spirit:portRef="PCSD_hdoutp"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>pll_in125_out125_out33_CLKI</spirit:name>
+                <spirit:displayName>pll_in125_out125_out33_CLKI</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="CLKI" spirit:componentRef="pll_in125_out125_out33"/>
+                <spirit:externalPortReference spirit:portRef="pll_in125_out125_out33_CLKI"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>pll_in125_out125_out33_CLKOP</spirit:name>
+                <spirit:displayName>pll_in125_out125_out33_CLKOP</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="CLKOP" spirit:componentRef="pll_in125_out125_out33"/>
+                <spirit:externalPortReference spirit:portRef="pll_in125_out125_out33_CLKOP"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>pll_in125_out125_out33_CLKOS</spirit:name>
+                <spirit:displayName>pll_in125_out125_out33_CLKOS</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="CLKOS" spirit:componentRef="pll_in125_out125_out33"/>
+                <spirit:externalPortReference spirit:portRef="pll_in125_out125_out33_CLKOS"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>pll_in125_out125_out33_LOCK</spirit:name>
+                <spirit:displayName>pll_in125_out125_out33_LOCK</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="LOCK" spirit:componentRef="pll_in125_out125_out33"/>
+                <spirit:externalPortReference spirit:portRef="pll_in125_out125_out33_LOCK"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_hdinn</spirit:name>
+                <spirit:displayName>sgmii_ecp5_hdinn</spirit:displayName>
+                <spirit:vendorExtensions>
+                    <lattice:attributes>
+                        <lattice:attribute lattice:name="export">sys_yes</lattice:attribute>
+                    </lattice:attributes>
+                </spirit:vendorExtensions>
+                <spirit:internalPortReference spirit:portRef="hdinn" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_hdinn"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_hdinp</spirit:name>
+                <spirit:displayName>sgmii_ecp5_hdinp</spirit:displayName>
+                <spirit:vendorExtensions>
+                    <lattice:attributes>
+                        <lattice:attribute lattice:name="export">sys_yes</lattice:attribute>
+                    </lattice:attributes>
+                </spirit:vendorExtensions>
+                <spirit:internalPortReference spirit:portRef="hdinp" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_hdinp"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_hdoutn</spirit:name>
+                <spirit:displayName>sgmii_ecp5_hdoutn</spirit:displayName>
+                <spirit:vendorExtensions>
+                    <lattice:attributes>
+                        <lattice:attribute lattice:name="export">sys_yes</lattice:attribute>
+                    </lattice:attributes>
+                </spirit:vendorExtensions>
+                <spirit:internalPortReference spirit:portRef="hdoutn" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_hdoutn"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_hdoutp</spirit:name>
+                <spirit:displayName>sgmii_ecp5_hdoutp</spirit:displayName>
+                <spirit:vendorExtensions>
+                    <lattice:attributes>
+                        <lattice:attribute lattice:name="export">sys_yes</lattice:attribute>
+                    </lattice:attributes>
+                </spirit:vendorExtensions>
+                <spirit:internalPortReference spirit:portRef="hdoutp" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_hdoutp"/>
+            </spirit:adHocConnection>
+        </spirit:adHocConnections>
+    </spirit:design>
+</lattice:project>

diff --git a/gbe/cores/sgmii/sgmii.vhd b/gbe/cores/sgmii/sgmii.vhd
new file mode 100644 (file)
index 0000000..e2b5bac
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii.vhd
@@ -0,0 +1,336 @@
+
+
+
+
+
+
+
+--
+-- Verific VHDL Description of module sgmii
+--
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+entity sgmii is
+    port (PCSD_hdinn: in std_logic;
+        PCSD_hdinp: in std_logic;
+        PCSD_hdoutn: out std_logic;
+        PCSD_hdoutp: out std_logic;
+        pll_in125_out125_out33_CLKI: in std_logic;
+        pll_in125_out125_out33_CLKOP: out std_logic;
+        pll_in125_out125_out33_CLKOS: out std_logic;
+        pll_in125_out125_out33_LOCK: out std_logic;
+        sgmii_ecp5_hdinn: in std_logic;
+        sgmii_ecp5_hdinp: in std_logic;
+        sgmii_ecp5_hdoutn: out std_logic;
+        sgmii_ecp5_hdoutp: out std_logic
+    );
+    
+end entity sgmii; -- sbp_module=true 
+
+architecture sgmii of sgmii is 
+    component PCSD is
+        port (rx_cv_err: out std_logic_vector(0 downto 0);
+            rx_disp_err: out std_logic_vector(0 downto 0);
+            rx_k: out std_logic_vector(0 downto 0);
+            rxdata: out std_logic_vector(7 downto 0);
+            tx_disp_correct: in std_logic_vector(0 downto 0);
+            tx_k: in std_logic_vector(0 downto 0);
+            txdata: in std_logic_vector(7 downto 0);
+            xmit: in std_logic_vector(0 downto 0);
+            ctc_del_s: out std_logic;
+            ctc_ins_s: out std_logic;
+            ctc_orun_s: out std_logic;
+            ctc_urun_s: out std_logic;
+            hdinn: in std_logic;
+            hdinp: in std_logic;
+            hdoutn: out std_logic;
+            hdoutp: out std_logic;
+            lsm_status_s: out std_logic;
+            pll_lol: in std_logic;
+            pll_refclki: in std_logic;
+            rsl_disable: in std_logic;
+            rsl_rst: in std_logic;
+            rst_dual_c: in std_logic;
+            rx_cdr_lol_s: out std_logic;
+            rx_los_low_s: out std_logic;
+            rx_pcs_rst_c: in std_logic;
+            rx_pwrup_c: in std_logic;
+            rx_serdes_rst_c: in std_logic;
+            rxrefclk: in std_logic;
+            serdes_pdb: in std_logic;
+            serdes_rst_dual_c: in std_logic;
+            signal_detect_c: in std_logic;
+            tx_pclk: out std_logic;
+            tx_pcs_rst_c: in std_logic;
+            tx_pwrup_c: in std_logic;
+            tx_serdes_rst_c: in std_logic;
+            txi_clk: in std_logic
+        );
+        
+    end component PCSD; -- not_need_bbox=true 
+    
+    
+    component pll_in125_out125_out33 is
+        port (CLKI: in std_logic;
+            CLKOP: out std_logic;
+            CLKOS: out std_logic;
+            LOCK: out std_logic
+        );
+        
+    end component pll_in125_out125_out33; -- not_need_bbox=true 
+    
+    
+    component sgmii_channel_smi is
+        port (mr_adv_ability: in std_logic_vector(15 downto 0);
+            mr_lp_adv_ability: out std_logic_vector(15 downto 0);
+            operational_rate: in std_logic_vector(1 downto 0);
+            rx_d: out std_logic_vector(7 downto 0);
+            sci_addr: in std_logic_vector(5 downto 0);
+            sci_rddata: out std_logic_vector(7 downto 0);
+            sci_wrdata: in std_logic_vector(7 downto 0);
+            tx_d: in std_logic_vector(7 downto 0);
+            an_link_ok: out std_logic;
+            col: out std_logic;
+            crs: out std_logic;
+            cyawstn: in std_logic;
+            debug_link_timer_short: in std_logic;
+            force_isolate: in std_logic;
+            force_loopback: in std_logic;
+            force_unidir: in std_logic;
+            gbe_mode: in std_logic;
+            hdinn: in std_logic;
+            hdinp: in std_logic;
+            hdoutn: out std_logic;
+            hdoutp: out std_logic;
+            mr_an_complete: out std_logic;
+            mr_an_enable: in std_logic;
+            mr_main_reset: in std_logic;
+            mr_page_rx: out std_logic;
+            mr_power_down: in std_logic;
+            mr_restart_an: in std_logic;
+            pll_lol: out std_logic;
+            pll_refclki: in std_logic;
+            rst_dual_c: in std_logic;
+            rst_n: in std_logic;
+            rx_cdr_lol_s: out std_logic;
+            rx_clk_125: in std_logic;
+            rx_clock_enable_sink: in std_logic;
+            rx_clock_enable_source: out std_logic;
+            rx_dv: out std_logic;
+            rx_er: out std_logic;
+            rx_pcs_rst_c: in std_logic;
+            rx_serdes_rst_c: in std_logic;
+            rxrefclk: in std_logic;
+            sci_en: in std_logic;
+            sci_en_dual: in std_logic;
+            sci_int: out std_logic;
+            sci_rd: in std_logic;
+            sci_sel: in std_logic;
+            sci_sel_dual: in std_logic;
+            sci_wrn: in std_logic;
+            serdes_pdb: out std_logic;
+            serdes_rst_dual_c: out std_logic;
+            sgmii_mode: in std_logic;
+            sli_rst: in std_logic;
+            tx_clk_125: in std_logic;
+            tx_clock_enable_sink: in std_logic;
+            tx_clock_enable_source: out std_logic;
+            tx_en: in std_logic;
+            tx_er: in std_logic;
+            tx_pcs_rst_c: in std_logic;
+            tx_pwrup_c: out std_logic;
+            tx_serdes_rst_c: out std_logic
+        );
+        
+    end component sgmii_channel_smi; -- not_need_bbox=true 
+    
+    
+    component sgmii_ecp5 is
+        port (rx_cv_err: out std_logic_vector(0 downto 0);
+            rx_disp_err: out std_logic_vector(0 downto 0);
+            rx_k: out std_logic_vector(0 downto 0);
+            rxdata: out std_logic_vector(7 downto 0);
+            sci_addr: in std_logic_vector(5 downto 0);
+            sci_rddata: out std_logic_vector(7 downto 0);
+            sci_wrdata: in std_logic_vector(7 downto 0);
+            tx_disp_correct: in std_logic_vector(0 downto 0);
+            tx_k: in std_logic_vector(0 downto 0);
+            txdata: in std_logic_vector(7 downto 0);
+            xmit: in std_logic_vector(0 downto 0);
+            ctc_del_s: out std_logic;
+            ctc_ins_s: out std_logic;
+            ctc_orun_s: out std_logic;
+            ctc_urun_s: out std_logic;
+            cyawstn: in std_logic;
+            hdinn: in std_logic;
+            hdinp: in std_logic;
+            hdoutn: out std_logic;
+            hdoutp: out std_logic;
+            lsm_status_s: out std_logic;
+            pll_lol: out std_logic;
+            pll_refclki: in std_logic;
+            rsl_disable: in std_logic;
+            rsl_rst: in std_logic;
+            rsl_rx_rdy: out std_logic;
+            rsl_tx_rdy: out std_logic;
+            rst_dual_c: in std_logic;
+            rx_cdr_lol_s: out std_logic;
+            rx_los_low_s: out std_logic;
+            rx_pcs_rst_c: in std_logic;
+            rx_pwrup_c: in std_logic;
+            rx_serdes_rst_c: in std_logic;
+            rxrefclk: in std_logic;
+            sci_en: in std_logic;
+            sci_en_dual: in std_logic;
+            sci_int: out std_logic;
+            sci_rd: in std_logic;
+            sci_sel: in std_logic;
+            sci_sel_dual: in std_logic;
+            sci_wrn: in std_logic;
+            serdes_pdb: in std_logic;
+            serdes_rst_dual_c: in std_logic;
+            signal_detect_c: in std_logic;
+            sli_rst: in std_logic;
+            tx_pclk: out std_logic;
+            tx_pcs_rst_c: in std_logic;
+            tx_pwrup_c: in std_logic;
+            tx_serdes_rst_c: in std_logic;
+            txi_clk: in std_logic
+        );
+        
+    end component sgmii_ecp5; -- not_need_bbox=true 
+    
+    
+    component tsmac is
+        port (haddr: in std_logic_vector(7 downto 0);
+            hdatain: in std_logic_vector(7 downto 0);
+            hdataout: out std_logic_vector(7 downto 0);
+            rx_dbout: out std_logic_vector(7 downto 0);
+            rx_stat_vector: out std_logic_vector(31 downto 0);
+            rxd: in std_logic_vector(7 downto 0);
+            tx_fifodata: in std_logic_vector(7 downto 0);
+            tx_sndpaustim: in std_logic_vector(15 downto 0);
+            tx_statvec: out std_logic_vector(30 downto 0);
+            txd: out std_logic_vector(7 downto 0);
+            col: in std_logic;
+            cpu_if_gbit_en: out std_logic;
+            crs: in std_logic;
+            hclk: in std_logic;
+            hcs_n: in std_logic;
+            hdataout_en_n: out std_logic;
+            hread_n: in std_logic;
+            hready_n: out std_logic;
+            hwrite_n: in std_logic;
+            ignore_pkt: in std_logic;
+            reset_n: in std_logic;
+            rx_dv: in std_logic;
+            rx_eof: out std_logic;
+            rx_er: in std_logic;
+            rx_error: out std_logic;
+            rx_fifo_error: out std_logic;
+            rx_fifo_full: in std_logic;
+            rx_stat_en: out std_logic;
+            rx_write: out std_logic;
+            rxmac_clk: in std_logic;
+            rxmac_clk_en: in std_logic;
+            tx_discfrm: out std_logic;
+            tx_done: out std_logic;
+            tx_en: out std_logic;
+            tx_er: out std_logic;
+            tx_fifoavail: in std_logic;
+            tx_fifoctrl: in std_logic;
+            tx_fifoempty: in std_logic;
+            tx_fifoeof: in std_logic;
+            tx_macread: out std_logic;
+            tx_sndpausreq: in std_logic;
+            tx_staten: out std_logic;
+            txmac_clk: in std_logic;
+            txmac_clk_en: in std_logic
+        );
+        
+    end component tsmac; -- not_need_bbox=true 
+    
+    
+    component PCSCLKDIV is
+        port (CLKI: in std_logic;
+            RST: in std_logic;
+            SEL2: in std_logic;
+            SEL1: in std_logic;
+            SEL0: in std_logic;
+            CDIV1: out std_logic;
+            CDIVX: out std_logic
+        );
+        
+    end component PCSCLKDIV; -- not_need_bbox=true 
+    
+    
+    signal PCSD_pll_lol,PCSD_pll_refclki,PCSD_serdes_pdb,sli_rst_wire1,sgmii_channel_smi_inst_serdes_rst_dual_c_sig,
+        sgmii_channel_smi_inst_tx_serdes_rst_c_sig,sgmii_channel_smi_inst_tx_pwrup_c_sig,
+        sli_rst_wire2,n1,pwr,pcs_clkdiv0_CDIV1_sig,pcs_clkdiv0_CDIVX_sig,
+        pcs_clkdiv0_CLKI_sig,pcs_clkdiv0_RST_sig,gnd : std_logic; 
+begin
+    sli_rst_wire1 <= sgmii_channel_smi_inst_serdes_rst_dual_c_sig OR  sgmii_channel_smi_inst_tx_serdes_rst_c_sig OR  (NOT PCSD_serdes_pdb) OR  (NOT sgmii_channel_smi_inst_tx_pwrup_c_sig);
+    PCSD_inst: component PCSD port map (rx_cv_err=>open,rx_disp_err=>open,
+            rx_k=>open,rxdata=>open,tx_disp_correct=>"0",tx_k=>"0",txdata=>"00000000",
+            xmit=>"0",ctc_del_s=>open,ctc_ins_s=>open,ctc_orun_s=>open,ctc_urun_s=>open,
+            hdinn=>PCSD_hdinn,hdinp=>PCSD_hdinp,hdoutn=>PCSD_hdoutn,hdoutp=>PCSD_hdoutp,
+            lsm_status_s=>open,pll_lol=>PCSD_pll_lol,pll_refclki=>PCSD_pll_refclki,
+            rsl_disable=>'0',rsl_rst=>'0',rst_dual_c=>'0',rx_cdr_lol_s=>open,
+            rx_los_low_s=>open,rx_pcs_rst_c=>'0',rx_pwrup_c=>'0',rx_serdes_rst_c=>'0',
+            rxrefclk=>'0',serdes_pdb=>PCSD_serdes_pdb,serdes_rst_dual_c=>'0',
+            signal_detect_c=>'0',tx_pclk=>open,tx_pcs_rst_c=>'0',tx_pwrup_c=>'0',
+            tx_serdes_rst_c=>'0',txi_clk=>'0');
+    pll_in125_out125_out33_inst: component pll_in125_out125_out33 port map (CLKI=>pll_in125_out125_out33_CLKI,
+            CLKOP=>pll_in125_out125_out33_CLKOP,CLKOS=>pll_in125_out125_out33_CLKOS,
+            LOCK=>pll_in125_out125_out33_LOCK);
+    sgmii_channel_smi_inst: component sgmii_channel_smi port map (mr_adv_ability=>"0000000000000000",
+            mr_lp_adv_ability=>open,operational_rate=>"00",rx_d=>open,sci_addr=>"000000",
+            sci_rddata=>open,sci_wrdata=>"00000000",tx_d=>"00000000",an_link_ok=>open,
+            col=>open,crs=>open,cyawstn=>'0',debug_link_timer_short=>'0',
+            force_isolate=>'0',force_loopback=>'0',force_unidir=>'0',gbe_mode=>'0',
+            hdinn=>'0',hdinp=>'0',hdoutn=>open,hdoutp=>open,mr_an_complete=>open,
+            mr_an_enable=>'0',mr_main_reset=>'0',mr_page_rx=>open,mr_power_down=>'0',
+            mr_restart_an=>'0',pll_lol=>PCSD_pll_lol,pll_refclki=>PCSD_pll_refclki,
+            rst_dual_c=>'0',rst_n=>'0',rx_cdr_lol_s=>open,rx_clk_125=>'0',
+            rx_clock_enable_sink=>'0',rx_clock_enable_source=>open,rx_dv=>open,
+            rx_er=>open,rx_pcs_rst_c=>'0',rx_serdes_rst_c=>'0',rxrefclk=>'0',
+            sci_en=>'0',sci_en_dual=>'0',sci_int=>open,sci_rd=>'0',sci_sel=>'0',
+            sci_sel_dual=>'0',sci_wrn=>'0',serdes_pdb=>PCSD_serdes_pdb,serdes_rst_dual_c=>sgmii_channel_smi_inst_serdes_rst_dual_c_sig,
+            sgmii_mode=>'0',sli_rst=>sli_rst_wire1,tx_clk_125=>'0',tx_clock_enable_sink=>'0',
+            tx_clock_enable_source=>open,tx_en=>'0',tx_er=>'0',tx_pcs_rst_c=>'0',
+            tx_pwrup_c=>sgmii_channel_smi_inst_tx_pwrup_c_sig,tx_serdes_rst_c=>sgmii_channel_smi_inst_tx_serdes_rst_c_sig);
+    sgmii_ecp5_inst: component sgmii_ecp5 port map (rx_cv_err=>open,rx_disp_err=>open,
+            rx_k=>open,rxdata=>open,sci_addr=>"000000",sci_rddata=>open,
+            sci_wrdata=>"00000000",tx_disp_correct=>"0",tx_k=>"0",txdata=>"00000000",
+            xmit=>"0",ctc_del_s=>open,ctc_ins_s=>open,ctc_orun_s=>open,ctc_urun_s=>open,
+            cyawstn=>'0',hdinn=>sgmii_ecp5_hdinn,hdinp=>sgmii_ecp5_hdinp,
+            hdoutn=>sgmii_ecp5_hdoutn,hdoutp=>sgmii_ecp5_hdoutp,lsm_status_s=>open,
+            pll_lol=>open,pll_refclki=>'0',rsl_disable=>'0',rsl_rst=>'0',
+            rsl_rx_rdy=>open,rsl_tx_rdy=>open,rst_dual_c=>'0',rx_cdr_lol_s=>open,
+            rx_los_low_s=>open,rx_pcs_rst_c=>'0',rx_pwrup_c=>'0',rx_serdes_rst_c=>'0',
+            rxrefclk=>'0',sci_en=>'0',sci_en_dual=>'0',sci_int=>open,sci_rd=>'0',
+            sci_sel=>'0',sci_sel_dual=>'0',sci_wrn=>'0',serdes_pdb=>'0',
+            serdes_rst_dual_c=>'0',signal_detect_c=>'0',sli_rst=>sli_rst_wire2,
+            tx_pclk=>open,tx_pcs_rst_c=>'0',tx_pwrup_c=>'0',tx_serdes_rst_c=>'0',
+            txi_clk=>'0');
+    tsmac_inst: component tsmac port map (haddr=>"00000000",hdatain=>"00000000",
+            hdataout=>open,rx_dbout=>open,rx_stat_vector=>open,rxd=>"00000000",
+            tx_fifodata=>"00000000",tx_sndpaustim=>"0000000000000000",tx_statvec=>open,
+            txd=>open,col=>'0',cpu_if_gbit_en=>open,crs=>'0',hclk=>'0',
+            hcs_n=>'0',hdataout_en_n=>open,hread_n=>'0',hready_n=>open,hwrite_n=>'0',
+            ignore_pkt=>'0',reset_n=>'0',rx_dv=>'0',rx_eof=>open,rx_er=>'0',
+            rx_error=>open,rx_fifo_error=>open,rx_fifo_full=>'0',rx_stat_en=>open,
+            rx_write=>open,rxmac_clk=>'0',rxmac_clk_en=>'0',tx_discfrm=>open,
+            tx_done=>open,tx_en=>open,tx_er=>open,tx_fifoavail=>'0',tx_fifoctrl=>'0',
+            tx_fifoempty=>'0',tx_fifoeof=>'0',tx_macread=>open,tx_sndpausreq=>'0',
+            tx_staten=>open,txmac_clk=>'0',txmac_clk_en=>'0');
+    pcs_clkdiv0: component PCSCLKDIV port map (CLKI=>pcs_clkdiv0_CLKI_sig,RST=>pcs_clkdiv0_RST_sig,
+            SEL2=>n1,SEL1=>pwr,SEL0=>n1,CDIV1=>pcs_clkdiv0_CDIV1_sig,CDIVX=>pcs_clkdiv0_CDIVX_sig);
+    n1 <= '0' ;
+    pwr <= '1' ;
+    gnd <= '0' ;
+    
+end architecture sgmii; -- sbp_module=true 
+

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/pmi_fifo_dcEEan163201024102410241818p12701671.ngo b/gbe/cores/sgmii/sgmii_channel_smi/pmi_fifo_dcEEan163201024102410241818p12701671.ngo
new file mode 100644 (file)
index 0000000..8c109a5
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diff --git a/gbe/cores/sgmii/sgmii_channel_smi/pmi_fifo_dcLEan1308881010p11aab620.ngo b/gbe/cores/sgmii/sgmii_channel_smi/pmi_fifo_dcLEan1308881010p11aab620.ngo
new file mode 100644 (file)
index 0000000..af80be3
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diff --git a/gbe/cores/sgmii/sgmii_channel_smi/pmi_fifo_dcLEan1308881212p11aac711.ngo b/gbe/cores/sgmii/sgmii_channel_smi/pmi_fifo_dcLEan1308881212p11aac711.ngo
new file mode 100644 (file)
index 0000000..1dacf6a
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diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi.cmd b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi.cmd
new file mode 100644 (file)
index 0000000..8529e92
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi.cmd
@@ -0,0 +1,23 @@
+PROJECT: sgmii_channel_smi
+working_path: "syn_results"
+module: sgmii_channel_smi
+verilog_file_list: "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/sgmii_pcs_eval/models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs_softlogic.v"
+verilog_file_list: "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/sgmii_pcs_eval/models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs.v"
+vhdl_file_list: "/home/soft/lattice/diamond/3.10_x64/cae_library/synthesis/vhdl/ecp5um.vhd"
+vhdl_file_list: "../sgmii_channel_smi.vhd"
+resource_sharing: false
+write_verilog: false
+write_vhdl: true
+suffix_name: edi
+output_file_name: sgmii_channel_smi
+write_prf: false
+vlog_std_v2001: true
+disable_io_insertion: true
+force_gsr: false
+speed_grade: 8
+frequency: 125.000
+fanout_limit: 100
+retiming: false
+pipe: false
+fixgatedclocks: 0
+fixgeneratedclocks: 0

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi.fdc b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi.fdc
new file mode 100644 (file)
index 0000000..292bc0f
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi.fdc
@@ -0,0 +1,3 @@
+###==== Start Generation
+
+define_attribute  {i:Lane0} {loc} {DCU0_CH0}

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi.lpc b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi.lpc
new file mode 100644 (file)
index 0000000..34c1f1a
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi.lpc
@@ -0,0 +1,37 @@
+[Device]
+Family=sa5p00m
+OperatingCondition=COM
+Package=CABGA756
+PartName=LFE5UM-85F-8BG756C
+PartType=LFE5UM-85F
+SpeedGrade=8
+Status=P
+[IP]
+CoreName=SGMII/Gb Ethernet PCS
+CoreRevision=4.1
+CoreStatus=Demo
+CoreType=IPCFG
+Date=04/29/2019
+ModuleName=sgmii_channel_smi
+ParameterFileVersion=1.0
+SourceFormat=vhdl
+Time=14:09:14
+VendorName=Lattice Semiconductor Corporation
+[Parameters]
+CH_MODE=Rx and Tx
+CORE_SYNP=1
+Channel=CH0
+DCUA=DCU0
+EasyConnect=1
+MAX_RATE=1.250
+NUM_CHS=1
+PROTOCOL=SGMII
+REFCLK_RATE=125.0000
+RX_CTC=2
+RX_CTC_HIGH=32
+RX_CTC_LOW=16
+SBP=1
+SOFTLOL=Enabled
+TX_MAX_RATE=2.5
+[SYSTEMPNR]
+LN0=DCU0_CH0

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi.ngd b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi.ngd
new file mode 100644 (file)
index 0000000..1492a28
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diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi.ngo b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi.ngo
new file mode 100644 (file)
index 0000000..dae439d
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diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi.v
new file mode 100644 (file)
index 0000000..5fd0100
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi.v
@@ -0,0 +1,374 @@
+//**************************************************************************\r
+// *************************************************************************\r
+// *                LATTICE SEMICONDUCTOR CONFIDENTIAL                     *\r
+// *                         PROPRIETARY NOTE                              *\r
+// *                                                                       *\r
+// *  This software contains information confidential and proprietary      *\r
+// *  to Lattice Semiconductor Corporation.  It shall not be reproduced    *\r
+// *  in whole or in part, or transferred to other documents, or disclosed *\r
+// *  to third parties, or used for any purpose other than that for which  *\r
+// *  it was obtained, without the prior written consent of Lattice        *\r
+// *  Semiconductor Corporation.  All rights reserved.                     *\r
+// *                                                                       *\r
+// *************************************************************************\r
+//**************************************************************************\r
+\r
+`define SGMII_YES_SINGLE_CLOCK\r
+\r
+\r
+module sgmii_channel_smi (\r
+\r
+//-----------USERNAME CORE-------------PART PORTS\r
+       // Control Interface\r
+       rst_n,\r
+       gbe_mode,\r
+       sgmii_mode,\r
+       operational_rate,\r
+       debug_link_timer_short,\r
+       force_isolate,\r
+       force_loopback,\r
+       force_unidir,\r
+\r
+       an_link_ok,\r
+\r
+       // G/MII Interface\r
+`ifdef SGMII_YES_SINGLE_CLOCK\r
+  tx_clock_enable_sink ,\r
+       tx_clock_enable_source ,\r
+\r
+       rx_clock_enable_sink ,\r
+       rx_clock_enable_source ,\r
+  tx_clk_125,\r
+  rx_clk_125,\r
+`else\r
+       tx_clk_mii ,\r
+       rx_clk_mii ,\r
+`endif\r
+       tx_d,\r
+       tx_en,\r
+       tx_er,\r
+\r
+       rx_d,\r
+       rx_dv,\r
+       rx_er,\r
+       col,\r
+       crs,\r
+\r
+       // Managment Control Outputs\r
+       mr_an_complete,\r
+       mr_page_rx,\r
+       mr_lp_adv_ability,\r
+\r
+       // Managment Control Inputs\r
+       mr_main_reset,\r
+       mr_an_enable,\r
+       mr_restart_an,\r
+       mr_adv_ability,\r
+       \r
+//-----------USERNAME PCS-------------PART PORTS       \r
+       hdoutp,\r
+       hdoutn,\r
+       hdinp,\r
+       hdinn,\r
+       \r
+  sli_rst,\r
+  serdes_rst_dual_c,\r
+  tx_serdes_rst_c,\r
+  serdes_pdb,\r
+  tx_pwrup_c,\r
+  \r
+  pll_refclki, \r
+  rxrefclk,\r
+  \r
+  sci_wrdata,\r
+       sci_addr,\r
+       sci_rddata,\r
+       sci_en_dual,\r
+       sci_sel_dual,\r
+       sci_en,\r
+       sci_sel,\r
+       sci_rd,\r
+       sci_wrn,\r
+       sci_int, \r
+  cyawstn,\r
+  rx_cdr_lol_s,\r
+        \r
+  tx_pcs_rst_c,\r
+  rx_pcs_rst_c,\r
+  rx_serdes_rst_c,\r
+      \r
+  rst_dual_c,\r
+  pll_lol,\r
+  \r
+`ifndef SGMII_YES_SINGLE_CLOCK\r
+  clk_125,\r
+`endif\r
+\r
+  mr_power_down\r
+       );\r
+\r
+//-----------USERNAME CORE-------------PART PORTS\r
+\r
+// Control Interface\r
+input         rst_n ;\r
+input         gbe_mode ;\r
+input         sgmii_mode ;\r
+input [1:0]   operational_rate ;\r
+input         debug_link_timer_short ;\r
+input         force_isolate ;\r
+input         force_loopback ;\r
+input         force_unidir ;\r
+\r
+output        an_link_ok ;\r
+\r
+// G/MII Interface\r
+\r
+`ifdef SGMII_YES_SINGLE_CLOCK\r
+input       tx_clock_enable_sink;\r
+output      tx_clock_enable_source;\r
+\r
+input       rx_clock_enable_sink;\r
+output      rx_clock_enable_source;\r
+\r
+input         tx_clk_125;\r
+input         rx_clk_125;\r
+\r
+`else\r
+input       tx_clk_mii;\r
+input       rx_clk_mii;\r
+`endif\r
+\r
+input [7:0]   tx_d ;\r
+input         tx_en ;\r
+input         tx_er ;\r
+\r
+output [7:0]   rx_d ;\r
+output         rx_dv ;\r
+output         rx_er ;\r
+output         col ;\r
+output         crs ;\r
+\r
+// Managment Control Outputs\r
+output         mr_an_complete;\r
+output         mr_page_rx;\r
+output [15:0]  mr_lp_adv_ability;\r
+\r
+// Managment Control Inputs\r
+input          mr_main_reset;\r
+input          mr_an_enable;\r
+input          mr_restart_an;\r
+input [15:0]   mr_adv_ability;\r
+\r
+\r
+//-----------USERNAME PCS-------------PART PORTS\r
+output hdoutp;\r
+output hdoutn;\r
+input hdinp;\r
+input hdinn;\r
+\r
+input  sli_rst;\r
+output serdes_rst_dual_c;\r
+output tx_serdes_rst_c;\r
+output serdes_pdb;\r
+output tx_pwrup_c;\r
+\r
+input  pll_refclki; \r
+input  rxrefclk;\r
+\r
+input [7:0]sci_wrdata;\r
+input [5:0]sci_addr;\r
+output [7:0]sci_rddata;\r
+input sci_en_dual;\r
+input sci_sel_dual;\r
+input sci_en;\r
+input sci_sel;\r
+input sci_rd;\r
+input sci_wrn;\r
+output sci_int;\r
+input cyawstn;\r
+output rx_cdr_lol_s;\r
+input tx_pcs_rst_c;\r
+input rx_pcs_rst_c;\r
+input rx_serdes_rst_c;\r
+input rst_dual_c;\r
+output pll_lol;\r
+\r
+\r
+`ifndef SGMII_YES_SINGLE_CLOCK\r
+input clk_125;\r
+`endif \r
+\r
+\r
+input mr_power_down;\r
+\r
+wire           link_status;\r
+wire [7:0]     data_chan2quad;\r
+wire           kcntl_chan2quad;\r
+wire           serdes_recovered_clk;\r
+wire [7:0]     data_quad2chan;\r
+wire           kcntl_quad2chan;\r
+wire           disp_err_quad2chan;\r
+wire    cv_err_quad2chan;\r
+wire           xmit_autoneg;\r
+wire           disparity_cntl_chan2quad;\r
+\r
+// SGMII core\r
+sgmii_channel_smi_core u_sgmii_core (\r
+   // Clock and Reset\r
+   .rst_n                  ( rst_n ) ,\r
+   .signal_detect          ( link_status ) ,\r
+   .gbe_mode               ( gbe_mode ) ,\r
+   .sgmii_mode             ( sgmii_mode ) ,\r
+   .operational_rate       ( operational_rate ) ,\r
+   .debug_link_timer_short ( debug_link_timer_short ) ,\r
+   .force_isolate          ( force_isolate ) ,\r
+   .force_loopback         ( force_loopback ) ,\r
+   .force_unidir           ( force_unidir ) ,\r
+\r
+   .rx_compensation_err    (  ) ,\r
+   .ctc_drop_flag          (  ) ,\r
+   .ctc_add_flag           (  ) ,\r
+   .an_link_ok             ( an_link_ok ) ,\r
+\r
+`ifdef SGMII_YES_SINGLE_CLOCK\r
+   .tx_clock_enable_sink   ( tx_clock_enable_sink ),\r
+   .tx_clock_enable_source ( tx_clock_enable_source ),\r
+\r
+   .rx_clock_enable_sink   ( rx_clock_enable_sink ),\r
+   .rx_clock_enable_source ( rx_clock_enable_source ),\r
+   .tx_clk_125      ( tx_clk_125 ) ,\r
+   .rx_clk_125      ( rx_clk_125 ) ,\r
+`else\r
+   .tx_clk_mii      ( tx_clk_mii ),\r
+   .rx_clk_mii      ( rx_clk_mii ),\r
+   .tx_clk_125      ( clk_125 ) ,\r
+   .rx_clk_125      ( clk_125 ) ,\r
+`endif\r
+   // GMII TX Inputs\r
+   \r
+   .tx_d            ( tx_d) ,\r
+   .tx_en           ( tx_en) ,\r
+   .tx_er           ( tx_er) ,\r
+\r
+   // GMII RX Outputs\r
+   // To GMII/MAC interface\r
+   .rx_d            ( rx_d ) ,\r
+   .rx_dv           ( rx_dv ) ,\r
+   .rx_er           ( rx_er ) ,\r
+   .col             ( col ) ,\r
+   .crs             ( crs ) ,\r
+                  \r
+   // 8BI TX Outputs\r
+   .tx_data           ( data_chan2quad) ,\r
+   .tx_kcntl          ( kcntl_chan2quad) ,\r
+   .tx_disparity_cntl ( disparity_cntl_chan2quad) ,\r
+   .xmit_autoneg      ( xmit_autoneg) ,\r
+\r
+   // 8BI RX Inputs\r
+   .serdes_recovered_clk ( serdes_recovered_clk ) ,\r
+   .rx_data              ( data_quad2chan ) ,\r
+   .rx_kcntl             ( kcntl_quad2chan ) ,\r
+   .rx_even              ( 1'b0 ) ,\r
+   .rx_disp_err          ( disp_err_quad2chan ) ,\r
+   .rx_cv_err            ( cv_err_quad2chan ) ,\r
+   .rx_err_decode_mode   ( 1'b0 ) ,\r
+\r
+   // Management Interface  I/O\r
+   .mr_adv_ability    (mr_adv_ability),\r
+   .mr_an_enable      (mr_an_enable), \r
+   .mr_main_reset     (mr_main_reset),  \r
+   .mr_restart_an     (mr_restart_an),   \r
+\r
+   .mr_an_complete    (mr_an_complete),   \r
+   .mr_lp_adv_ability (mr_lp_adv_ability), \r
+   .mr_page_rx        (mr_page_rx)\r
+   );\r
+\r
+assign serdes_rst_dual_c = ~rst_n;\r
+assign tx_serdes_rst_c   = ~rst_n;\r
+assign serdes_pdb        = 1'b1;\r
+\r
+assign tx_pwrup_c        = ~mr_power_down;\r
+  \r
+\r
+sgmii_channel_smi_pcs u_sgmii_pcs (\r
+\r
+// Global Clocks and Resets\r
+       // inputs\r
+       .rst_dual_c(rst_dual_c), \r
+       .serdes_rst_dual_c(~rst_n), \r
+       .pll_refclki(pll_refclki), \r
+  .rxrefclk(rxrefclk),\r
+  .sli_rst(sli_rst),\r
+  \r
+`ifdef SGMII_YES_SINGLE_CLOCK  \r
+  .txi_clk(tx_clk_125),         \r
+`else\r
+  .txi_clk(clk_125),\r
+`endif  \r
+  \r
+// fpga tx datapath signals\r
+       // inputs\r
+       .tx_pcs_rst_c(tx_pcs_rst_c), \r
+       .txdata(data_chan2quad), \r
+       .tx_k(kcntl_chan2quad), \r
+       .tx_disp_correct(disparity_cntl_chan2quad), \r
+\r
+       // outputs\r
+       .tx_pclk(), \r
+       \r
+// fpga rx datapath signals\r
+       // inputs\r
+       .rx_pcs_rst_c(rx_pcs_rst_c), \r
+       .xmit(xmit_autoneg),\r
+  .signal_detect_c(1'b1), \r
+\r
+       // outputs\r
+       .rx_pclk(serdes_recovered_clk),\r
+       .rxdata(data_quad2chan), \r
+       .rx_k(kcntl_quad2chan), \r
+       .rx_disp_err(disp_err_quad2chan), \r
+       .rx_cv_err(cv_err_quad2chan), \r
+       .lsm_status_s(link_status), \r
+       .rx_cdr_lol_s(rx_cdr_lol_s), \r
+\r
+// serdes signals\r
+       // inputs\r
+       .rx_serdes_rst_c(rx_serdes_rst_c), \r
+  .tx_serdes_rst_c(~rst_n),\r
+\r
+       .hdinp(hdinp), \r
+       .hdinn(hdinn), \r
+\r
+       // outputs\r
+       .hdoutp(hdoutp), \r
+       .hdoutn(hdoutn), \r
+       \r
+       //SCI interface\r
+       \r
+       .cyawstn(cyawstn),\r
+       .sci_en(sci_en),\r
+       .sci_en_dual(sci_en_dual),\r
+       .sci_sel_dual(sci_sel_dual),\r
+       .sci_sel(sci_sel),\r
+       .sci_wrdata(sci_wrdata),\r
+       .sci_addr(sci_addr),\r
+       .sci_rddata(sci_rddata),\r
+       .sci_rd(sci_rd),\r
+       .sci_wrn(sci_wrn),\r
+       .sci_int(sci_int),\r
+\r
+// misc control signals\r
+       // inputs\r
+       .rsl_disable (1'b0),\r
+  .rsl_rst     (~rst_n),\r
+  .tx_pwrup_c(~mr_power_down), // powerup tx channel\r
+       .rx_pwrup_c(~mr_power_down), // power up rx channel\r
+  .serdes_pdb(1'b1),\r
+  \r
+       // outputs\r
+       .pll_lol(pll_lol)\r
+);\r
+\r
+\r
+endmodule\r

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi.vhd b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi.vhd
new file mode 100644 (file)
index 0000000..a50792f
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi.vhd
@@ -0,0 +1,359 @@
+--**************************************************************************\r
+-- *************************************************************************\r
+-- *                LATTICE SEMICONDUCTOR CONFIDENTIAL                     *\r
+-- *                         PROPRIETARY NOTE                              *\r
+-- *                                                                       *\r
+-- *  This software contains information confidential and proprietary      *\r
+-- *  to Lattice Semiconductor Corporation.  It shall not be reproduced    *\r
+-- *  in whole or in part, or transferred to other documents, or disclosed *\r
+-- *  to third parties, or used for any purpose other than that for which  *\r
+-- *  it was obtained, without the prior written consent of Lattice        *\r
+-- *  Semiconductor Corporation.  All rights reserved.                     *\r
+-- *                                                                       *\r
+-- *************************************************************************\r
+--**************************************************************************\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+\r
+entity sgmii_channel_smi is port (\r
+ rst_n                  : in std_logic;\r
+ gbe_mode               : in std_logic;\r
+ sgmii_mode             : in std_logic;\r
+ operational_rate       : in std_logic_vector(1 downto 0);\r
+ debug_link_timer_short : in std_logic;\r
+ force_isolate          : in std_logic;\r
+ force_loopback         : in std_logic;\r
+ force_unidir           : in std_logic;\r
+ --rx_compensation_err    : out std_logic;\r
+ --ctc_drop_flag          : out std_logic;\r
+ --ctc_add_flag           : out std_logic;\r
+ an_link_ok             : out std_logic;\r
+  tx_clock_enable_sink  : in std_logic;\r
+       tx_clock_enable_source : out std_logic;\r
+\r
+       rx_clock_enable_sink : in std_logic;\r
+       rx_clock_enable_source : out std_logic;\r
+  tx_clk_125           : in std_logic;\r
+  rx_clk_125           : in std_logic;\r
+ tx_d                   : in std_logic_vector(7 downto 0);\r
+ tx_en                  : in std_logic;\r
+ tx_er                  : in std_logic;\r
+ rx_d                   : out std_logic_vector(7 downto 0);\r
+ rx_dv                  : out std_logic;\r
+ rx_er                  : out std_logic;\r
+ col                    : out std_logic;\r
+ crs                    : out std_logic;\r
+ mr_an_complete         : out std_logic;\r
+ mr_page_rx             : out std_logic;\r
+ mr_lp_adv_ability      : out std_logic_vector(15 downto 0);\r
+ mr_main_reset          : in std_logic;\r
+ mr_an_enable           : in std_logic;\r
+ mr_restart_an          : in std_logic;\r
+ mr_adv_ability         : in std_logic_vector(15 downto 0);\r
+\r
+ hdoutp: out std_logic;\r
+ hdoutn: out std_logic;\r
+ hdinp: in std_logic;\r
+ hdinn: in std_logic;\r
+ \r
+ sli_rst           : in std_logic;\r
+ serdes_rst_dual_c : out std_logic;\r
+ tx_serdes_rst_c   : out std_logic;\r
+ serdes_pdb        : out std_logic;\r
+ tx_pwrup_c        : out std_logic;\r
+ \r
+ pll_refclki : in std_logic;\r
+ rxrefclk    : in std_logic;\r
+\r
+ sci_wrdata  :  in std_logic_vector(7 downto 0);\r
+ sci_addr    :  in std_logic_vector(5 downto 0);\r
+ sci_rddata  :  out std_logic_vector(7 downto 0);\r
+ sci_en_dual : in std_logic;\r
+ sci_sel_dual: in std_logic;\r
+ sci_en: in std_logic;\r
+ sci_sel: in std_logic;\r
+ sci_rd: in std_logic;\r
+ sci_wrn: in std_logic;\r
+ sci_int:  out std_logic;\r
+ cyawstn: in std_logic;\r
+\r
+ rx_cdr_lol_s: out std_logic;\r
+\r
+ tx_pcs_rst_c: in std_logic;\r
+ rx_pcs_rst_c: in std_logic;\r
+ rx_serdes_rst_c: in std_logic;\r
+\r
+ rst_dual_c: in std_logic;\r
+ pll_lol: out std_logic;\r
+\r
+ \r
+ mr_power_down: in std_logic\r
+   );\r
+end entity;\r
+\r
+architecture arch of sgmii_channel_smi is\r
+component sgmii_channel_smi_core port (\r
+       rst_n                  : in std_logic;\r
+       signal_detect          : in std_logic;\r
+       gbe_mode               : in std_logic;\r
+       sgmii_mode             : in std_logic;\r
+       force_isolate          : in std_logic;\r
+       force_loopback         : in std_logic;\r
+       force_unidir           : in std_logic;\r
+       operational_rate       : in std_logic_vector(1 downto 0);\r
+       debug_link_timer_short : in std_logic;\r
+       rx_compensation_err    : out std_logic;\r
+       ctc_drop_flag          : out std_logic;\r
+       ctc_add_flag           : out std_logic;\r
+       an_link_ok             : out std_logic;\r
+\r
+  tx_clock_enable_sink  : in std_logic;\r
+       tx_clock_enable_source : out std_logic;\r
+\r
+       rx_clock_enable_sink : in std_logic;\r
+       rx_clock_enable_source : out std_logic;\r
+\r
+       tx_clk_125             : in std_logic;\r
+       tx_d                   : in std_logic_vector(7 downto 0);\r
+       tx_en                  : in std_logic;\r
+       tx_er                  : in std_logic;\r
+       rx_clk_125             : in std_logic;\r
+       rx_d                   : out std_logic_vector(7 downto 0);\r
+       rx_dv                  : out std_logic;\r
+       rx_er                  : out std_logic;\r
+       col                    : out std_logic;\r
+       crs                    : out std_logic;\r
+       tx_data                : out std_logic_vector(7 downto 0);\r
+       tx_kcntl               : out std_logic;\r
+       tx_disparity_cntl      : out std_logic;\r
+       xmit_autoneg           : out std_logic;\r
+       serdes_recovered_clk   : in std_logic;\r
+       rx_data                : in std_logic_vector(7 downto 0);\r
+       rx_even                : in std_logic;\r
+       rx_kcntl               : in std_logic;\r
+       rx_disp_err            : in std_logic;\r
+       rx_cv_err              : in std_logic;\r
+       rx_err_decode_mode     : in std_logic;\r
+       mr_an_complete         : out std_logic;\r
+       mr_page_rx             : out std_logic;\r
+       mr_lp_adv_ability      : out std_logic_vector(15 downto 0);\r
+       mr_main_reset          : in std_logic;\r
+       mr_an_enable           : in std_logic;\r
+       mr_restart_an          : in std_logic;\r
+       mr_adv_ability         : in std_logic_vector(15 downto 0)\r
+   );\r
+end component;\r
+\r
+component sgmii_channel_smi_pcs port (\r
+                 hdoutp            : out std_logic;\r
+                 hdoutn            : out std_logic;\r
+                 hdinp             : in std_logic;\r
+                 hdinn             : in std_logic;\r
+            rxrefclk          : in std_logic;\r
+            txi_clk           : in std_logic;\r
+            sli_rst           : in std_logic;\r
+            rx_pclk           : out std_logic;\r
+            tx_pclk           : out std_logic;\r
+            txdata            : in std_logic_vector(7 downto 0);\r
+            tx_k              : in std_logic_vector(0 downto 0);\r
+            xmit              : in std_logic_vector(0 downto 0);\r
+            tx_disp_correct   : in std_logic_vector(0 downto 0);\r
+            rxdata            : out std_logic_vector(7 downto 0);\r
+            rx_k              : out std_logic_vector(0 downto 0);\r
+            rx_disp_err       : out std_logic_vector(0 downto 0);\r
+            rx_cv_err         : out std_logic_vector(0 downto 0);\r
+            sci_wrdata  :  in std_logic_vector(7 downto 0);\r
+            signal_detect_c :  in std_logic;\r
+            sci_addr    :  in std_logic_vector(5 downto 0);\r
+            sci_rddata  :  out std_logic_vector(7 downto 0);\r
+            sci_en_dual : in std_logic;\r
+            sci_sel_dual: in std_logic;\r
+            sci_en: in std_logic;\r
+            sci_sel: in std_logic;\r
+            sci_rd: in std_logic;\r
+            sci_wrn: in std_logic;\r
+            sci_int:  out std_logic;\r
+            cyawstn: in std_logic;\r
+            lsm_status_s      : out std_logic;\r
+            rx_cdr_lol_s      : out std_logic;\r
+            tx_pcs_rst_c      : in std_logic;\r
+            rx_pcs_rst_c      : in std_logic;\r
+            rx_serdes_rst_c   : in std_logic;\r
+            rsl_disable       : in std_logic;\r
+            rsl_rst           : in std_logic;\r
+            tx_pwrup_c        : in std_logic;\r
+            rx_pwrup_c        : in std_logic;\r
+            rst_dual_c        : in std_logic;\r
+            serdes_rst_dual_c : in std_logic;\r
+            serdes_pdb        : in std_logic;\r
+            tx_serdes_rst_c   : in std_logic;\r
+            pll_refclki       : in std_logic;\r
+            pll_lol           : out std_logic\r
+   );\r
+end component;\r
+\r
+--  8-bit Interface Signals from SGMII channel to QuadPCS/SERDES\r
+signal data_chan2quad          : std_logic_vector(7 downto 0);\r
+signal kcntl_chan2quad         : std_logic_vector(0 downto 0);\r
+signal disparity_cntl_chan2quad: std_logic_vector(0 downto 0);\r
+\r
+--  8-bit Interface Signals from QuadPCS/SERDES to SGMII channel\r
+signal data_quad2chan          : std_logic_vector(7 downto 0);\r
+signal kcntl_quad2chan         : std_logic_vector(0 downto 0);\r
+signal disp_err_quad2chan      : std_logic_vector(0 downto 0);\r
+signal cv_err_quad2chan        : std_logic_vector(0 downto 0);\r
+signal link_status             : std_logic;\r
+signal serdes_recovered_clk    : std_logic;\r
+signal xmit_autoneg            : std_logic_vector(0 downto 0);\r
+signal reset                   : std_logic;\r
+signal mr_power_down_inv       : std_logic;\r
+\r
+begin\r
+\r
+reset <= not rst_n;\r
+mr_power_down_inv <= not(mr_power_down);\r
+-- Instantiate SGMII IP Core\r
+u_sgmii_core : sgmii_channel_smi_core port map(\r
+   -- Clock and Reset\r
+   rst_n                   =>  rst_n ,\r
+   signal_detect           =>  link_status ,\r
+   gbe_mode                =>  gbe_mode ,\r
+   sgmii_mode              =>  sgmii_mode ,\r
+   operational_rate        =>  operational_rate ,\r
+   debug_link_timer_short  =>  debug_link_timer_short ,\r
+   force_isolate           =>  force_isolate ,\r
+   force_loopback          =>  force_loopback ,\r
+   force_unidir            =>  force_unidir ,\r
+\r
+   rx_compensation_err     =>  open ,\r
+   ctc_drop_flag           =>  open ,\r
+   ctc_add_flag            =>  open ,\r
+   an_link_ok              =>  an_link_ok ,\r
+\r
+   tx_clock_enable_sink    =>  tx_clock_enable_sink ,\r
+   tx_clock_enable_source  =>  tx_clock_enable_source ,\r
+\r
+   rx_clock_enable_sink    =>  rx_clock_enable_sink ,\r
+   rx_clock_enable_source  =>  rx_clock_enable_source ,\r
+   tx_clk_125       =>  tx_clk_125 ,\r
+   rx_clk_125       =>  rx_clk_125 ,\r
+   -- GMII TX Inputs\r
+   tx_d             =>  tx_d,\r
+   tx_en            =>  tx_en,\r
+   tx_er            =>  tx_er,\r
+   -- GMII RX Outputs\r
+   -- To GMII/MAC interface\r
+   rx_d             =>  rx_d ,\r
+   rx_dv            =>  rx_dv ,\r
+   rx_er            =>  rx_er ,\r
+   col              =>  col ,\r
+   crs              =>  crs ,\r
+\r
+   -- 8BI TX Outputs\r
+   tx_data            =>  data_chan2quad,\r
+   tx_kcntl           =>  kcntl_chan2quad(0),\r
+   tx_disparity_cntl  =>  disparity_cntl_chan2quad(0),\r
+   xmit_autoneg       =>  xmit_autoneg(0),\r
+\r
+   -- 8BI RX Inputs\r
+   serdes_recovered_clk  =>  serdes_recovered_clk ,\r
+   rx_data               =>  data_quad2chan ,\r
+   rx_kcntl              =>  kcntl_quad2chan(0) ,\r
+   rx_even               =>  '0' ,\r
+   rx_disp_err           =>  disp_err_quad2chan(0) ,\r
+   rx_cv_err             =>  cv_err_quad2chan(0) ,\r
+   rx_err_decode_mode    =>  '0' ,\r
+\r
+   -- Management Interface  I/O\r
+   mr_adv_ability     => mr_adv_ability,\r
+   mr_an_enable       => mr_an_enable,\r
+   mr_main_reset      => mr_main_reset,\r
+   mr_restart_an      => mr_restart_an,\r
+\r
+   mr_an_complete     => mr_an_complete,\r
+   mr_lp_adv_ability  => mr_lp_adv_ability,\r
+   mr_page_rx         => mr_page_rx\r
+   );\r
+   \r
+   \r
+  serdes_rst_dual_c <= reset;\r
+  tx_serdes_rst_c   <= reset;\r
+  serdes_pdb        <= '1';\r
+  tx_pwrup_c        <= mr_power_down_inv;   \r
+\r
+u_sgmii_pcs : sgmii_channel_smi_pcs port map(\r
+-- Global Clocks and Resets\r
+       -- inputs\r
+       rst_dual_c           =>   rst_dual_c,\r
+       serdes_rst_dual_c    =>   reset,\r
+       pll_refclki          =>   pll_refclki,\r
+  rxrefclk             =>   rxrefclk,\r
+  \r
+  txi_clk              =>   tx_clk_125,\r
+\r
+  sli_rst              =>   sli_rst,\r
+\r
+-- fpga tx datapath signals\r
+       -- inputs\r
+       tx_pcs_rst_c         =>   tx_pcs_rst_c,\r
+       txdata               =>   data_chan2quad,\r
+       tx_k                 =>   kcntl_chan2quad,\r
+       tx_disp_correct      =>   disparity_cntl_chan2quad,\r
+\r
+       -- outputs\r
+       tx_pclk              =>  open ,\r
+\r
+-- fpga rx datapath signals\r
+       -- inputs\r
+       rx_pcs_rst_c         =>   rx_pcs_rst_c,\r
+       xmit                 =>   xmit_autoneg,\r
+\r
+       -- outputs\r
+       rx_pclk              =>   serdes_recovered_clk,\r
+       rxdata               =>   data_quad2chan,\r
+       rx_k                 =>   kcntl_quad2chan,\r
+       rx_disp_err          =>   disp_err_quad2chan,\r
+       rx_cv_err            =>   cv_err_quad2chan,\r
+       lsm_status_s         =>   link_status,\r
+       rx_cdr_lol_s         =>   rx_cdr_lol_s,\r
+\r
+-- serdes signals\r
+       -- inputs\r
+       rx_serdes_rst_c      =>   rx_serdes_rst_c,\r
+       tx_serdes_rst_c      =>   reset,\r
+\r
+       hdinp                =>   hdinp,\r
+       hdinn                =>   hdinn,\r
+\r
+       -- outputs\r
+       hdoutp               =>   hdoutp,\r
+       hdoutn               =>   hdoutn,\r
+  signal_detect_c      =>   '1',\r
+\r
+  cyawstn              =>   cyawstn,\r
+       sci_en               =>   sci_en,\r
+       sci_en_dual          =>   sci_en_dual,\r
+       sci_sel_dual         =>   sci_sel_dual,\r
+       sci_sel              =>   sci_sel,\r
+       sci_wrdata           =>   sci_wrdata,\r
+       sci_addr             =>   sci_addr,\r
+       sci_rddata           =>   sci_rddata,\r
+       sci_rd               =>   sci_rd,\r
+       sci_wrn              =>   sci_wrn,\r
+       sci_int              =>   sci_int,\r
+\r
+-- misc control signals\r
+       -- inputs\r
+       rsl_disable          => '0',\r
+  rsl_rst              => reset,\r
+  tx_pwrup_c           => mr_power_down_inv, -- powerup tx channel\r
+       rx_pwrup_c           => mr_power_down_inv, -- power up rx channel\r
+  serdes_pdb           => '1',\r
+\r
+       -- outputs\r
+       pll_lol              => pll_lol\r
+);\r
+\r
+end architecture;\r
+\r

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_bb.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_bb.v
new file mode 100644 (file)
index 0000000..0ab55f4
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_bb.v
@@ -0,0 +1,156 @@
+//**************************************************************************\r
+// *************************************************************************\r
+// *                LATTICE SEMICONDUCTOR CONFIDENTIAL                     *\r
+// *                         PROPRIETARY NOTE                              *\r
+// *                                                                       *\r
+// *  This software contains information confidential and proprietary      *\r
+// *  to Lattice Semiconductor Corporation.  It shall not be reproduced    *\r
+// *  in whole or in part, or transferred to other documents, or disclosed *\r
+// *  to third parties, or used for any purpose other than that for which  *\r
+// *  it was obtained, without the prior written consent of Lattice        *\r
+// *  Semiconductor Corporation.  All rights reserved.                     *\r
+// *                                                                       *\r
+// *************************************************************************\r
+//**************************************************************************\r
+\r
+`define SGMII_YES_SINGLE_CLOCK\r
+\r
+\r
+module sgmii_channel_smi (\r
+\r
+//-----------USERNAME CORE-------------PART PORTS\r
+       // Control Interface\r
+       rst_n,\r
+       gbe_mode,\r
+       sgmii_mode,\r
+       operational_rate,\r
+       debug_link_timer_short,\r
+       force_isolate,\r
+       force_loopback,\r
+       force_unidir,\r
+\r
+       an_link_ok,\r
+\r
+       // G/MII Interface\r
+`ifdef SGMII_YES_SINGLE_CLOCK\r
+  tx_clock_enable_sink ,\r
+       tx_clock_enable_source ,\r
+\r
+       rx_clock_enable_sink ,\r
+       rx_clock_enable_source ,\r
+  tx_clk_125,\r
+  rx_clk_125,\r
+`else\r
+       tx_clk_mii ,\r
+       rx_clk_mii ,\r
+`endif\r
+       tx_d,\r
+       tx_en,\r
+       tx_er,\r
+\r
+       rx_d,\r
+       rx_dv,\r
+       rx_er,\r
+       col,\r
+       crs,\r
+\r
+       // Managment Control Outputs\r
+       mr_an_complete,\r
+       mr_page_rx,\r
+       mr_lp_adv_ability,\r
+\r
+       // Managment Control Inputs\r
+       mr_main_reset,\r
+       mr_an_enable,\r
+       mr_restart_an,\r
+       mr_adv_ability,\r
+       \r
+//-----------USERNAME PCS-------------PART PORTS       \r
+       hdoutp,\r
+       hdoutn,\r
+       hdinp,\r
+       hdinn,\r
+           \r
+  rx_cdr_lol_s,\r
+        \r
+  tx_pcs_rst_c,\r
+  rx_pcs_rst_c,\r
+  rx_serdes_rst_c,\r
+      \r
+  rst_dual_c,\r
+  pll_lol,\r
+  refclk2fpga,\r
+  mr_power_down\r
+\r
+       );\r
+\r
+//-----------USERNAME CORE-------------PART PORTS\r
+\r
+// Control Interface\r
+input         rst_n ;\r
+input         gbe_mode ;\r
+input         sgmii_mode ;\r
+input [1:0]   operational_rate ;\r
+input         debug_link_timer_short ;\r
+input         force_isolate ;\r
+input         force_loopback ;\r
+input         force_unidir ;\r
+\r
+output        an_link_ok ;\r
+\r
+// G/MII Interface\r
+\r
+`ifdef SGMII_YES_SINGLE_CLOCK\r
+input       tx_clock_enable_sink;\r
+output      tx_clock_enable_source;\r
+\r
+input       rx_clock_enable_sink;\r
+output      rx_clock_enable_source;\r
+\r
+input         tx_clk_125;\r
+input         rx_clk_125;\r
+\r
+`else\r
+input       tx_clk_mii;\r
+input       rx_clk_mii;\r
+`endif\r
+\r
+input [7:0]   tx_d ;\r
+input         tx_en ;\r
+input         tx_er ;\r
+\r
+output [7:0]   rx_d ;\r
+output         rx_dv ;\r
+output         rx_er ;\r
+output         col ;\r
+output         crs ;\r
+\r
+// Managment Control Outputs\r
+output         mr_an_complete;\r
+output         mr_page_rx;\r
+output [15:0]  mr_lp_adv_ability;\r
+\r
+// Managment Control Inputs\r
+input          mr_main_reset;\r
+input          mr_an_enable;\r
+input          mr_restart_an;\r
+input [15:0]   mr_adv_ability;\r
+\r
+\r
+//-----------USERNAME PCS-------------PART PORTS\r
+output hdoutp;\r
+output hdoutn;\r
+input hdinp;\r
+input hdinn;\r
+output rx_cdr_lol_s;\r
+input tx_pcs_rst_c;\r
+input rx_pcs_rst_c;\r
+input rx_serdes_rst_c;\r
+input rst_dual_c;\r
+output pll_lol;\r
+\r
+// new added\r
+input refclk2fpga; // new added\r
+input mr_power_down; // new added\r
+\r
+endmodule\r

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_beh.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_beh.v
new file mode 100644 (file)
index 0000000..68df57b
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_beh.v
@@ -0,0 +1,3984 @@
+// sgmii_pcs_core_beh_pp.v generated by Lattice IP Model Creator version 1\r
+// created on Wed Mar 19 15:39:54 CST 2014\r
+// Copyright(c) 2007 Lattice Semiconductor Corporation. All rights reserved\r
+// obfuscator_exe version 1.mar0807\r
+// top\r
+`define SGMII_NO_ENC\r
+`define SGMII_YES_CTC_DYNAMIC\r
+`define SGMII_FIFO_FAMILY_ECP5\r
+`define SGMII_YES_SINGLE_CLOCK\r
+`timescale 1 ns / 100 ps\r
+module gd2938d (ui49c6d, of4e369, th71b4d, ym8da6f, su6d379, ne69bc9,\r
+    vi4de4a, wj6f253, ps7929c, uvc94e2, ld4a714, su538a7, ba9c539,\r
+    ale29cb);\r
+input wire [17:0] ui49c6d;\r
+input wire of4e369;\r
+input wire th71b4d;\r
+input wire ym8da6f;\r
+input wire su6d379;\r
+input wire ne69bc9;\r
+input wire vi4de4a;\r
+input wire [9:0] wj6f253;\r
+input wire [9:0] ps7929c;\r
+output wire [17:0] uvc94e2;\r
+output wire ld4a714;\r
+output wire su538a7;\r
+output wire ba9c539;\r
+output wire ale29cb;\r
+wire eaffb08;\r
+wire kdfd840;\r
+wire ldec205;\r
+wire ld6102f;\r
+wire gd817f;\r
+wire dz40bfc;\r
+wire co5fe7;\r
+wire vk2ff39;\r
+wire mr7f9cb;\r
+wire xjfce5c;\r
+wire kde72e7;\r
+wire ux3973c;\r
+wire gocb9e4;\r
+wire ay5cf20;\r
+wire ofe7900;\r
+wire ep3c805;\r
+wire nee402d;\r
+wire vk2016b;\r
+wire gqb5b;\r
+wire aa5ad9;\r
+wire hd2d6c9;\r
+wire fn6b64f;\r
+wire kd5b27e;\r
+wire qtd93f4;\r
+wire qtc9fa5;\r
+wire jp4fd2d;\r
+wire bl7e96e;\r
+wire lqf4b76;\r
+wire pha5bb3;\r
+wire jr2dd9e;\r
+wire rt6ecf6;\r
+wire fa767b7;\r
+wire qib3dbb;\r
+wire zz9edd8;\r
+wire ldf6ec7;\r
+wire jeb763e;\r
+wire yzbb1f3;\r
+wire thd8f9d;\r
+wire ldc7cee;\r
+wire ks3e776;\r
+wire ldf3bb1;\r
+wire ie9dd8e;\r
+wire zkeec70;\r
+wire rg76383;\r
+wire kfb1c1b;\r
+wire hd8e0dd;\r
+wire of706ef;\r
+wire hq8377c;\r
+wire je1bbe3;\r
+wire nrddf1b;\r
+wire meef8de;\r
+wire rg7c6f1;\r
+wire lde378a;\r
+wire ba1bc56;\r
+wire ykde2b3;\r
+wire xwf1598;\r
+wire cb8acc2;\r
+wire ui56614;\r
+wire mgb30a0;\r
+wire uk98501;\r
+wire xjc2809;\r
+wire do1404e;\r
+wire nta0273;\r
+wire vk139f;\r
+wire ph9cfa;\r
+wire al4e7d7;\r
+wire jc73ebd;\r
+wire ux9f5ea;\r
+wire qgfaf54;\r
+wire dzd7aa0;\r
+wire lsbd507;\r
+wire meea83a;\r
+wire sh541d1;\r
+wire dba0e8d;\r
+wire qv746e;\r
+wire do3a375;\r
+wire ead1bab;\r
+wire ou8dd58;\r
+wire th6eac1;\r
+wire wj7560f;\r
+wire uxab07c;\r
+wire zk583e4;\r
+wire icc1f23;\r
+wire qif919;\r
+wire dm7c8c8;\r
+wire fae4643;\r
+wire kf2321b;\r
+wire vx190dc;\r
+wire fnc86e7;\r
+wire su4373e;\r
+wire tw1b9f1;\r
+wire ofdcf8b;\r
+wire wje7c5c;\r
+wire ou3e2e5;\r
+wire psf1729;\r
+wire rv8b94a;\r
+wire kq5ca56;\r
+wire ose52b0;\r
+wire ep29581;\r
+wire hb4ac0d;\r
+wire ic5606e;\r
+wire xlb0370;\r
+wire db81b86;\r
+wire epdc37;\r
+wire rt6e1bd;\r
+wire cz70dee;\r
+wire tw86f75;\r
+wire zz37baa;\r
+wire ribdd56;\r
+wire neeeab3;\r
+wire al7559b;\r
+wire bnaacdc;\r
+wire go566e7;\r
+wire ecb3738;\r
+wire lf9b9c1;\r
+wire czdce0f;\r
+wire ene707c;\r
+wire zz383e4;\r
+wire uic1f26;\r
+wire ief931;\r
+wire rg7c988;\r
+wire nee4c43;\r
+wire sj2621a;\r
+wire ec310d4;\r
+wire ec886a0;\r
+wire kq43500;\r
+wire gq1a801;\r
+wire med4009;\r
+wire hda0049;\r
+wire ym24f;\r
+wire ls1278;\r
+wire nt93c2;\r
+wire ea49e16;\r
+wire rt4f0b1;\r
+wire os7858f;\r
+wire nrc2c78;\r
+wire db163c6;\r
+wire irb1e36;\r
+wire qv8f1b5;\r
+wire go78dad;\r
+wire enc6d69;\r
+wire ir36b4c;\r
+wire ntb5a64;\r
+wire doad327;\r
+wire xw6993b;\r
+wire ww4c9da;\r
+wire fn64ed1;\r
+wire hd2768e;\r
+wire uk3b476;\r
+wire lqda3b1;\r
+wire wwd1d8a;\r
+wire fp8ec50;\r
+wire tu76286;\r
+wire anb1433;\r
+wire an8a19c;\r
+wire ld50ce5;\r
+wire tw8672e;\r
+wire cb33973;\r
+wire pu9cb9c;\r
+wire cme5ce2;\r
+wire gq2e710;\r
+wire rg73880;\r
+wire fc9c402;\r
+wire gbe2013;\r
+wire mg1009c;\r
+wire gd804e1;\r
+wire yz270c;\r
+wire rv13865;\r
+wire tw9c32f;\r
+wire nee197b;\r
+wire tjcbda;\r
+wire gb65ed7;\r
+wire ng2f6bc;\r
+wire xj7b5e2;\r
+wire jcdaf17;\r
+wire nrd78bb;\r
+wire mgbc5df;\r
+wire wje2ef8;\r
+wire qv177c5;\r
+wire irbbe2c;\r
+wire psdf164;\r
+wire enf8b22;\r
+wire nec5915;\r
+wire gd2c8ab;\r
+wire th6455c;\r
+wire tj22ae7;\r
+wire qi1573f;\r
+wire mtab9f9;\r
+wire qg5cfcd;\r
+wire mre7e68;\r
+wire ng3f345;\r
+wire jpf9a2b;\r
+wire dzcd15f;\r
+wire cm68afe;\r
+wire nr457f0;\r
+wire aa2bf86;\r
+wire bl5fc31;\r
+wire zkfe18f;\r
+wire ykf0c7b;\r
+wire ng863d9;\r
+wire ec31ecb;\r
+wire kf8f659;\r
+wire nr7b2cd;\r
+wire ipd966f;\r
+wire cmcb37d;\r
+wire yk59be9;\r
+wire zxcdf48;\r
+wire cz6fa47;\r
+wire os7d23d;\r
+wire nre91e8;\r
+wire zk48f47;\r
+wire by47a3b;\r
+wire lf3d1da;\r
+wire ofe8ed6;\r
+wire dm476b4;\r
+wire co3b5a3;\r
+wire xwdad19;\r
+wire uvd68cb;\r
+wire sjb465d;\r
+wire mga32ec;\r
+wire lf19760;\r
+wire aycbb07;\r
+wire fa5d838;\r
+wire dzec1c2;\r
+wire yx60e17;\r
+wire cb70bc;\r
+wire xl385e5;\r
+wire hbc2f2e;\r
+wire gd17976;\r
+wire iebcbb5;\r
+wire sue5da9;\r
+wire ec2ed48;\r
+wire fa76a41;\r
+wire phb520a;\r
+wire oua9056;\r
+wire ho482b1;\r
+wire kd4158a;\r
+wire coac54;\r
+wire ui562a0;\r
+wire ohb1500;\r
+wire ir8a804;\r
+wire sh54024;\r
+wire dba0125;\r
+wire sw92f;\r
+wire tw4979;\r
+wire aa24bcb;\r
+wire ri25e58;\r
+wire xy2f2c2;\r
+wire xw79612;\r
+wire eacb092;\r
+wire ps58491;\r
+wire jpc248b;\r
+wire an1245f;\r
+wire ie922fc;\r
+wire xl917e0;\r
+wire rv8bf07;\r
+wire nr5f83e;\r
+wire thfc1f7;\r
+wire yke0fbe;\r
+wire cb7df0;\r
+wire qi3ef84;\r
+wire czf7c20;\r
+wire qvbe104;\r
+wire eaf0825;\r
+wire lf84129;\r
+wire ls2094e;\r
+wire ba4a72;\r
+wire ng25393;\r
+wire wl29c9b;\r
+wire qt4e4dc;\r
+wire go726e5;\r
+wire zm93729;\r
+wire db9b94a;\r
+wire qtdca57;\r
+wire kqe52bc;\r
+wire yz295e1;\r
+wire ld4af0d;\r
+wire ps5786e;\r
+wire cobc373;\r
+wire tue1b98;\r
+wire ohdcc2;\r
+wire th6e615;\r
+wire rg730ae;\r
+wire ie98573;\r
+wire fnc2b99;\r
+wire ou15cce;\r
+wire sjae670;\r
+wire jc73384;\r
+wire xy99c23;\r
+wire osce11a;\r
+wire sh708d1;\r
+wire tj8468d;\r
+wire yz2346e;\r
+wire aa1a374;\r
+wire med1ba0;\r
+wire aa8dd00;\r
+wire ld6e801;\r
+wire ld7400f;\r
+wire lfa007e;\r
+wire ec3f7;\r
+reg [17 : 0] hq1fb8;\r
+reg iefdc3;\r
+reg th7ee18;\r
+reg alf70c6;\r
+reg dob8635;\r
+reg czc31aa;\r
+reg wl18d55;\r
+reg [9 : 0] ipc6aac;\r
+reg [9 : 0] ng35564;\r
+reg bnaab22;\r
+reg jp55917;\r
+reg coac8be;\r
+reg nr645f0;\r
+reg xl22f87;\r
+reg yz17c3f;\r
+reg yzbe1fd;\r
+reg qgf0fed;\r
+reg aa87f69;\r
+reg ba3fb48;\r
+reg mrfda42;\r
+reg aled215;\r
+reg zk690ad;\r
+reg rg4856b;\r
+reg lq42b5a;\r
+reg ks15ad2;\r
+reg lsad690;\r
+reg ld6b483;\r
+reg hb5a41e;\r
+reg thd20f6;\r
+reg gd907b6;\r
+reg je83db5;\r
+reg vk1edaa;\r
+reg fnf6d53;\r
+reg mgb6a9e;\r
+reg tjb54f0;\r
+reg xlaa786;\r
+reg ww53c36;\r
+reg jr9e1b1;\r
+reg gof0d8e;\r
+reg zm86c71;\r
+reg ux3638a;\r
+reg irb1c55;\r
+reg rv8e2ad;\r
+reg rt7156f;\r
+reg gd8ab7e;\r
+reg dz55bf4;\r
+reg hqadfa6;\r
+reg al6fd32;\r
+reg bl7e995;\r
+reg lqf4cae;\r
+reg mga6573;\r
+reg lf32b98;\r
+reg kf95cc6;\r
+reg mtae634;\r
+reg ne731a4;\r
+reg co98d23;\r
+reg enc6918;\r
+reg gq348c4;\r
+reg ana4621;\r
+reg wl2310d;\r
+reg mt1886c;\r
+reg eac4364;\r
+reg gq21b20;\r
+reg ohd900;\r
+reg rg6c805;\r
+reg dz6402a;\r
+reg tw20157;\r
+reg qiabb;\r
+reg co55d9;\r
+reg ri2aec8;\r
+reg fa57643;\r
+reg yzbb21a;\r
+reg shd90d5;\r
+reg hbc86ad;\r
+reg ic4356e;\r
+reg qi1ab71;\r
+reg psd5b89;\r
+reg zmadc4a;\r
+reg pf6e252;\r
+reg nr71296;\r
+reg zm894b6;\r
+reg zx4a5b2;\r
+reg by52d97;\r
+reg vk96cbb;\r
+reg ymb65db;\r
+reg ngb2ed9;\r
+reg ym976ca;\r
+reg uxbb650;\r
+reg kqdb285;\r
+reg qtd9428;\r
+reg psca145;\r
+reg bl50a2b;\r
+reg sj8515e;\r
+reg rv28af4;\r
+reg dz457a6;\r
+reg ym2bd36;\r
+reg kd5e9b1;\r
+reg tuf4d8d;\r
+reg yma6c6b;\r
+reg gd36359;\r
+reg anb1acd;\r
+reg co8d66d;\r
+reg xj6b368;\r
+reg ww59b46;\r
+reg jpcda30;\r
+reg cm6d187;\r
+reg os68c39;\r
+reg cm461c8;\r
+reg vk30e41;\r
+reg ou8720b;\r
+reg oh39059;\r
+reg nrc82cc;\r
+reg gb41666;\r
+reg xyb334;\r
+reg kq599a3;\r
+reg qtccd18;\r
+reg ho668c5;\r
+reg ym3462b;\r
+reg iea3158;\r
+reg ep18ac0;\r
+reg tuc5604;\r
+reg wy2b022;\r
+reg ps58110;\r
+reg hoc0883;\r
+reg je441b;\r
+reg xl220da;\r
+reg sw106d6;\r
+reg ba836b1;\r
+reg ng1b58b;\r
+reg nedac5a;\r
+reg shd62d3;\r
+reg yzb169c;\r
+reg lf8b4e4;\r
+reg vv5a727;\r
+reg ald393e;\r
+reg ng9c9f5;\r
+reg nee4faa;\r
+reg tj27d52;\r
+reg qi3ea97;\r
+reg ayf54b8;\r
+reg bnaa5c0;\r
+reg dm52e06;\r
+reg ks97033;\r
+reg lsb8198;\r
+reg nec0cc2;\r
+reg hd6613;\r
+reg kf3309f;\r
+reg ec984fd;\r
+reg zxc27e9;\r
+reg zz13f4f;\r
+reg gd9fa7f;\r
+reg offd3fd;\r
+reg nre9fec;\r
+reg xj4ff66;\r
+reg ip7fb36;\r
+reg qtfd9b4;\r
+reg hbecda5;\r
+reg zk66d2e;\r
+reg oh36973;\r
+reg irb4b9c;\r
+reg rva5ce5;\r
+reg wy2e72e;\r
+reg ps73970;\r
+reg pu9cb82;\r
+reg cme5c12;\r
+reg gq2e090;\r
+reg sh70480;\r
+reg mg82404;\r
+reg yz12021;\r
+reg ux9010c;\r
+reg sj80865;\r
+reg tw432d;\r
+reg wy2196a;\r
+reg ntcb50;\r
+reg kd65a87;\r
+reg vx2d43c;\r
+reg mr6a1e7;\r
+reg pf50f3c;\r
+reg ym879e6;\r
+reg mt3cf30;\r
+reg ale7985;\r
+reg wl3cc2d;\r
+reg dze616d;\r
+reg pu30b6e;\r
+reg ux85b73;\r
+reg lf2db9d;\r
+reg ea6dcee;\r
+reg dz6e770;\r
+reg tu73b86;\r
+reg uk9dc32;\r
+reg rgee190;\r
+reg cz70c82;\r
+reg tw86415;\r
+reg db320ab;\r
+reg cb9055f;\r
+reg co82afd;\r
+reg qi157e8;\r
+reg mtabf41;\r
+reg th5fa0d;\r
+reg offd06f;\r
+reg mre837c;\r
+reg sh41be5;\r
+reg uxdf2d;\r
+reg of6f96d;\r
+reg ho7cb6d;\r
+reg kqe5b6b;\r
+reg vx2db58;\r
+reg go6dac6;\r
+reg qg6d630;\r
+reg zx6b181;\r
+reg ne58c0e;\r
+reg ofc6072;\r
+reg ng30395;\r
+reg bn81caa;\r
+reg nge557;\r
+reg ic72abb;\r
+reg mt955d8;\r
+reg hdaaec5;\r
+reg dm5762f;\r
+reg irbb17a;\r
+reg vvd8bd5;\r
+reg zkc5eae;\r
+reg xy2f573;\r
+reg yx7ab9a;\r
+reg ned5cd4;\r
+reg kfae6a2;\r
+reg xw73514;\r
+reg gd9a8a3;\r
+reg med451d;\r
+reg fca28e9;\r
+reg je1474b;\r
+reg gqa3a5b;\r
+reg sj1d2d9;\r
+reg hbe96cd;\r
+reg en4b66f;\r
+reg qt5b37d;\r
+reg mrd9bec;\r
+reg hbcdf64;\r
+reg of6fb27;\r
+reg go7d93d;\r
+reg fnec9e9;\r
+reg ld64f4e;\r
+reg db27a76;\r
+reg vx3d3b7;\r
+reg rte9dbe;\r
+reg cz4edf6;\r
+reg vi76fb4;\r
+reg lsb7da2;\r
+reg kfbed12;\r
+reg hbf6894;\r
+reg epb44a6;\r
+reg fca2534;\r
+reg gd129a2;\r
+reg lf94d15;\r
+reg swa68ae;\r
+reg ie34571;\r
+reg lsa2b88;\r
+reg ec15c43;\r
+reg qvae218;\r
+reg vv710c4;\r
+reg ks88626;\r
+reg go43130;\r
+reg cb18981;\r
+reg cmc4c0c;\r
+reg wl26061;\r
+reg ls3030c;\r
+reg lf81862;\r
+reg rvc317;\r
+reg nr618be;\r
+reg tjc5f6;\r
+reg ay62fb6;\r
+reg wl17db1;\r
+reg irbed8d;\r
+reg rtf6c6c;\r
+reg ecb6366;\r
+reg kfb1b31;\r
+reg ec8d98d;\r
+reg ps6cc69;\r
+reg lq6634a;\r
+reg aa31a52;\r
+reg co8d291;\r
+reg vi69488;\r
+reg nr4a443;\r
+reg jc5221f;\r
+reg fp910fa;\r
+reg aa887d7;\r
+reg ea43eb8;\r
+reg gq1f5c0;\r
+reg icfae00;\r
+reg rtd7000;\r
+reg pub8006;\r
+reg tuc0032;\r
+reg wy192;\r
+reg ukc90;\r
+reg lf6481;\r
+reg rv3240f;\r
+reg ie9207f;\r
+reg wl903f8;\r
+reg jr81fc5;\r
+reg ymfe2f;\r
+reg qt7f178;\r
+reg gbf8bc5;\r
+reg dmc5e2d;\r
+reg do2f16b;\r
+reg su78b5a;\r
+reg vic5ad1;\r
+reg tj2d68b;\r
+reg xj6b45f;\r
+reg zx5a2fe;\r
+reg [2047:0] ead17f6;\r
+wire [308:0] vx8bfb1;\r
+localparam th5fd8e = 309,nefec77 = 32'hfdffc68b;\r
+localparam [31:0] fnf63ba = nefec77;\r
+localparam tj8eebd = nefec77 & 4'hf;\r
+localparam [11:0] fpbaf71 = 'h7ff;\r
+wire [(1 << tj8eebd) -1:0] jebdc77;\r
+reg [th5fd8e-1:0] fn71dda;\r
+reg [tj8eebd-1:0] ay776be [0:1];\r
+reg [tj8eebd-1:0] nedaf8d;\r
+reg thd7c6b;\r
+integer kfbe35f;\r
+integer jcf1afd;\r
+AND2 wy8d7eb (.A(ym8da6f), .B(eaffb08), .Z(cobc373));    INV vieb1fc (.A(zz383e4), .Z(eaffb08));    AND2 xy3f896 (.A(su6d379), .B(kdfd840), .Z(thfc1f7));    INV tw965a5 (.A(ene707c), .Z(kdfd840));    OR2 ohb4a93 (.A(ne69bc9), .B(vi4de4a), .Z(uic1f26));    XOR2 ng93bd2 (.A(sue5da9), .B(ec2ed48), .Z(vk2ff39));    XOR2 zxd2605 (.A(ec2ed48), .B(ho482b1), .Z(mr7f9cb));    XOR2 uk5c8b (.A(ho482b1), .B(kd4158a), .Z(xjfce5c));    XOR2 xl8b20f (.A(kd4158a), .B(ir8a804), .Z(kde72e7));    XOR2 swfe75 (.A(ir8a804), .B(sh54024), .Z(ux3973c));    XOR2 cz75178 (.A(sh54024), .B(aa24bcb), .Z(gocb9e4));    XOR2 ic788ba (.A(aa24bcb), .B(ri25e58), .Z(ay5cf20));    XOR2 bnba23c (.A(ri25e58), .B(ps58491), .Z(ofe7900));    XOR2 cb3ce4a (.A(ps58491), .B(jpc248b), .Z(ep3c805));    XOR2 ld4ab24 (.A(jpc248b), .B(irb1e36), .Z(nee402d));    XOR2 ec24d86 (.A(ec31ecb), .B(kf8f659), .Z(pha5bb3));    XOR2 ls8616f (.A(kf8f659), .B(yk59be9), .Z(jr2dd9e));    XOR2 gb6f6ee (.A(yk59be9), .B(zxcdf48), .Z(rt6ecf6));    XOR2 hoee9ce (.A(zxcdf48), .B(zk48f47), .Z(fa767b7));    XOR2 qgce7d5 (.A(zk48f47), .B(by47a3b), .Z(qib3dbb));    XOR2 rgd52a0 (.A(by47a3b), .B(co3b5a3), .Z(zz9edd8));    XOR2 jra0675 (.A(co3b5a3), .B(xwdad19), .Z(ldf6ec7));    XOR2 yx75ff0 (.A(xwdad19), .B(lf19760), .Z(jeb763e));    XOR2 osf0be3 (.A(lf19760), .B(aycbb07), .Z(yzbb1f3));    XOR2 nre335a (.A(aycbb07), .B(tw8672e), .Z(thd8f9d));    defparam dz5adb6.initval =  16'h6996 ;    ROM16X1A dz5adb6 (.AD3(fae4643), .AD2(vx190dc), .AD1(su4373e),        .AD0(ofdcf8b), .DO0(dm476b4));    defparam ale8012.initval =  16'h6996 ;    ROM16X1A ale8012 (.AD3(ou8dd58), .AD2(wj7560f), .AD1(zk583e4),        .AD0(qif919), .DO0(ld6102f));    defparam cz70b64.initval =  16'h6996 ;    ROM16X1A cz70b64 (.AD3(su4373e), .AD2(ofdcf8b), .AD1(ld6e801),        .AD0(ld6e801), .DO0(mga32ec));    defparam fn6e596.initval =  16'h6996 ;    ROM16X1A fn6e596 (.AD3(vx190dc), .AD2(su4373e), .AD1(ofdcf8b),        .AD0(ld6e801), .DO0(sjb465d));    defparam ou824ce.initval =  16'h6996 ;    ROM16X1A ou824ce (.AD3(qif919), .AD2(fae4643), .AD1(vx190dc),        .AD0(mga32ec), .DO0(ofe8ed6));    defparam os6247a.initval =  16'h6996 ;    ROM16X1A os6247a (.AD3(zk583e4), .AD2(qif919), .AD1(fae4643),        .AD0(sjb465d), .DO0(nre91e8));    defparam oh26b57.initval =  16'h6996 ;    ROM16X1A oh26b57 (.AD3(wj7560f), .AD2(zk583e4), .AD1(qif919),        .AD0(dm476b4), .DO0(os7d23d));    defparam kd5bad2.initval =  16'h6996 ;    ROM16X1A kd5bad2 (.AD3(dm476b4), .AD2(ld6102f),        .AD1(ld6e801), .AD0(ld6e801), .DO0(cmcb37d));    defparam kd7ade6.initval =  16'h6996 ;    ROM16X1A kd7ade6 (.AD3(dm476b4), .AD2(ld6102f),        .AD1(do3a375), .AD0(ld6e801), .DO0(ipd966f));    defparam ng2a3cf.initval =  16'h6996 ;    ROM16X1A ng2a3cf (.AD3(dm476b4), .AD2(ld6102f),        .AD1(dba0e8d), .AD0(do3a375), .DO0(ng863d9));    defparam pha56e0.initval =  16'h6996 ;    ROM16X1A pha56e0 (.AD3(meea83a), .AD2(dba0e8d), .AD1(do3a375),        .AD0(ld6e801), .DO0(ldec205));    defparam xwc5a2f.initval =  16'h6996 ;    ROM16X1A xwc5a2f (.AD3(dm476b4), .AD2(ld6102f),        .AD1(ldec205), .AD0(ld6e801), .DO0(ykf0c7b));    defparam mrf8eb2.initval =  16'h6996 ;    ROM16X1A mrf8eb2 (.AD3(zz37baa), .AD2(neeeab3), .AD1(bnaacdc),        .AD0(ecb3738), .DO0(tw4979));    defparam qt7a8a6.initval =  16'h6996 ;    ROM16X1A qt7a8a6 (.AD3(hb4ac0d), .AD2(xlb0370), .AD1(epdc37),        .AD0(cz70dee), .DO0(dz40bfc));    defparam xyb445.initval =  16'h6996 ;    ROM16X1A xyb445 (.AD3(bnaacdc), .AD2(ecb3738), .AD1(ld6e801),        .AD0(ld6e801), .DO0(eacb092));    defparam hof138c.initval =  16'h6996 ;    ROM16X1A hof138c (.AD3(neeeab3), .AD2(bnaacdc), .AD1(ecb3738),        .AD0(ld6e801), .DO0(xw79612));    defparam qi9de87.initval =  16'h6996 ;    ROM16X1A qi9de87 (.AD3(cz70dee), .AD2(zz37baa), .AD1(neeeab3),        .AD0(eacb092), .DO0(sw92f));    defparam aa5473.initval =  16'h6996 ;    ROM16X1A aa5473 (.AD3(epdc37), .AD2(cz70dee), .AD1(zz37baa),        .AD0(xw79612), .DO0(ohb1500));    defparam fc14ece.initval =  16'h6996 ;    ROM16X1A fc14ece (.AD3(xlb0370), .AD2(epdc37), .AD1(cz70dee),        .AD0(tw4979), .DO0(ui562a0));    defparam xl91848.initval =  16'h6996 ;    ROM16X1A xl91848 (.AD3(tw4979), .AD2(dz40bfc),        .AD1(ld6e801), .AD0(ld6e801), .DO0(oua9056));    defparam wy97cce.initval =  16'h6996 ;    ROM16X1A wy97cce (.AD3(tw4979), .AD2(dz40bfc),        .AD1(ose52b0), .AD0(ld6e801), .DO0(phb520a));    defparam mr6f479.initval =  16'h6996 ;    ROM16X1A mr6f479 (.AD3(tw4979), .AD2(dz40bfc),        .AD1(rv8b94a), .AD0(ose52b0), .DO0(iebcbb5));    defparam ph28aed.initval =  16'h6996 ;    ROM16X1A ph28aed (.AD3(ou3e2e5), .AD2(rv8b94a), .AD1(ose52b0),        .AD0(ld6e801), .DO0(gd817f));    defparam qvb153b.initval =  16'h6996 ;    ROM16X1A qvb153b (.AD3(tw4979), .AD2(dz40bfc),        .AD1(gd817f), .AD0(ld6e801), .DO0(gd17976));    XOR2 ie24422 (.A(irb1e36), .B(ecb3738), .Z(xj7b5e2));    XOR2 db22386 (.A(ofdcf8b), .B(tw8672e), .Z(cm68afe));    defparam ri86cbd.initval =  16'h0410 ;    ROM16X1A ri86cbd (.AD3(je1bbe3), .AD2(tw8672e), .AD1(ofdcf8b),        .AD0(ld6e801), .DO0(yx60e17));    defparam jraa28f.initval =  16'h1004 ;    ROM16X1A jraa28f (.AD3(je1bbe3), .AD2(tw8672e), .AD1(ofdcf8b),        .AD0(ld6e801), .DO0(dzec1c2));    defparam zmad931.initval =  16'h0140 ;    ROM16X1A zmad931 (.AD3(lqf4b76), .AD2(irb1e36), .AD1(ecb3738),        .AD0(ld6e801), .DO0(xl917e0));    defparam do9682b.initval =  16'h4001 ;    ROM16X1A do9682b (.AD3(lqf4b76), .AD2(irb1e36), .AD1(ecb3738),        .AD0(ld6e801), .DO0(ie922fc));    INV the602c (.A(db9b94a), .Z(co5fe7));    AND2 ec5995 (.A(czdce0f), .B(co5fe7), .Z(kqe52bc));    AND2 wl95316 (.A(czdce0f), .B(db9b94a), .Z(yz295e1));    defparam nt16a01.INIT_DATA = "STATIC" ;    defparam nt16a01.ASYNC_RESET_RELEASE = "SYNC" ;    defparam nt16a01.CSDECODE_B = "0b000" ;    defparam nt16a01.CSDECODE_A = "0b000" ;    defparam nt16a01.WRITEMODE_B = "NORMAL" ;    defparam nt16a01.WRITEMODE_A = "NORMAL" ;    defparam nt16a01.GSR = "ENABLED" ;    defparam nt16a01.RESETMODE = "ASYNC" ;    defparam nt16a01.REGMODE_B = "NOREG" ;    defparam nt16a01.REGMODE_A = "NOREG" ;    defparam nt16a01.DATA_WIDTH_B = 18 ;    defparam nt16a01.DATA_WIDTH_A = 18 ;    DP16KD nt16a01 (.DIA17(ui49c6d[17]), .DIA16(ui49c6d[16]), .DIA15(ui49c6d[15]),        .DIA14(ui49c6d[14]), .DIA13(ui49c6d[13]), .DIA12(ui49c6d[12]), .DIA11(ui49c6d[11]),        .DIA10(ui49c6d[10]), .DIA9(ui49c6d[9]), .DIA8(ui49c6d[8]), .DIA7(ui49c6d[7]),        .DIA6(ui49c6d[6]), .DIA5(ui49c6d[5]), .DIA4(ui49c6d[4]), .DIA3(ui49c6d[3]),        .DIA2(ui49c6d[2]), .DIA1(ui49c6d[1]), .DIA0(ui49c6d[0]), .ADA13(bl7e96e),        .ADA12(jp4fd2d), .ADA11(qtc9fa5), .ADA10(qtd93f4), .ADA9(kd5b27e), .ADA8(fn6b64f),        .ADA7(hd2d6c9), .ADA6(aa5ad9), .ADA5(gqb5b), .ADA4(vk2016b), .ADA3(ld6e801),        .ADA2(ld6e801), .ADA1(lfa007e), .ADA0(lfa007e), .CEA(cobc373),        .OCEA(cobc373), .CLKA(of4e369), .WEA(lfa007e), .CSA2(ld6e801),        .CSA1(ld6e801), .CSA0(ld6e801), .RSTA(ne69bc9), .DIB17(ld6e801),        .DIB16(ld6e801), .DIB15(ld6e801), .DIB14(ld6e801), .DIB13(ld6e801),        .DIB12(ld6e801), .DIB11(ld6e801), .DIB10(ld6e801), .DIB9(ld6e801),        .DIB8(ld6e801), .DIB7(ld6e801), .DIB6(ld6e801), .DIB5(ld6e801),        .DIB4(ld6e801), .DIB3(ld6e801), .DIB2(ld6e801), .DIB1(ld6e801),        .DIB0(ld6e801), .ADB13(hq8377c), .ADB12(of706ef), .ADB11(hd8e0dd),        .ADB10(kfb1c1b), .ADB9(rg76383), .ADB8(zkeec70), .ADB7(ie9dd8e), .ADB6(ldf3bb1),        .ADB5(ks3e776), .ADB4(ldc7cee), .ADB3(ld6e801), .ADB2(ld6e801),        .ADB1(ld6e801), .ADB0(ld6e801), .CEB(thfc1f7), .OCEB(thfc1f7),        .CLKB(th71b4d), .WEB(ld6e801), .CSB2(ld6e801), .CSB1(ld6e801),        .CSB0(ld6e801), .RSTB(ne69bc9), .DOA17(), .DOA16(), .DOA15(), .DOA14(),        .DOA13(), .DOA12(), .DOA11(), .DOA10(), .DOA9(), .DOA8(), .DOA7(),        .DOA6(), .DOA5(), .DOA4(), .DOA3(), .DOA2(), .DOA1(), .DOA0(), .DOB17(uvc94e2[17]),        .DOB16(uvc94e2[16]), .DOB15(uvc94e2[15]), .DOB14(uvc94e2[14]), .DOB13(uvc94e2[13]), .DOB12(uvc94e2[12]),        .DOB11(uvc94e2[11]), .DOB10(uvc94e2[10]), .DOB9(uvc94e2[9]), .DOB8(uvc94e2[8]), .DOB7(uvc94e2[7]),        .DOB6(\r
+uvc94e2[6]), .DOB5(uvc94e2[5]), .DOB4(uvc94e2[4]), .DOB3(uvc94e2[3]), .DOB2(uvc94e2[2]),        .DOB1(uvc94e2[1]), .DOB0(uvc94e2[0]))                          ;    FD1P3BX mg77a (.D(ief931), .SP(cobc373), .CK(of4e369), .PD(ne69bc9),        .Q(sue5da9))             ;    FD1P3DX ng8682a (.D(rg7c988), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(ec2ed48))             ;    FD1P3DX yz90c12 (.D(sj2621a), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(ho482b1))             ;    FD1P3DX aaa346f (.D(ec310d4), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(kd4158a))             ;    FD1P3DX vic0060 (.D(kq43500), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(ir8a804))             ;    FD1P3DX uk107ad (.D(gq1a801), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(sh54024))             ;    FD1P3DX zx4a65b (.D(hda0049), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(aa24bcb))             ;    FD1P3DX ipf866a (.D(ym24f), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(ri25e58))             ;    FD1P3DX hda5dac (.D(nt93c2), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(ps58491))             ;    FD1P3DX ie315c2 (.D(ea49e16), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(jpc248b))             ;    FD1P3DX ph844b8 (.D(os7858f), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(irb1e36))             ;    FD1P3DX oh36a1c (.D(vk2ff39), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(nrddf1b))             ;    FD1P3DX yz26632 (.D(mr7f9cb), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(meef8de))             ;    FD1P3DX jra5176 (.D(xjfce5c), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(rg7c6f1))             ;    FD1P3DX qvbee52 (.D(kde72e7), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(lde378a))             ;    FD1P3DX zza50de (.D(ux3973c), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(ba1bc56))             ;    FD1P3DX zzbf2cc (.D(gocb9e4), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(ykde2b3))             ;    FD1P3DX qi3e229 (.D(ay5cf20), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(xwf1598))             ;    FD1P3DX rt4a3a8 (.D(ofe7900), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(cb8acc2))             ;    FD1P3DX cb3cd12 (.D(ep3c805), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(ui56614))             ;    FD1P3DX vxaf0ac (.D(nee402d), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(mgb30a0))             ;    FD1P3DX je30c02 (.D(irb1e36), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(uk98501))             ;    FD1P3DX hd9b52e (.D(sue5da9), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(vk2016b))             ;    FD1P3DX qib318b (.D(ec2ed48), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(gqb5b))             ;    FD1P3DX zxc8a39 (.D(ho482b1), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(aa5ad9))             ;    FD1P3DX hb7ecea (.D(kd4158a), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(hd2d6c9))             ;    FD1P3DX twb7049 (.D(ir8a804), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(fn6b64f))             ;    FD1P3DX zx5a185 (.D(sh54024), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(kd5b27e))             ;    FD1P3DX su726e8 (.D(aa24bcb), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(qtd93f4))             ;    FD1P3DX qiafec (.D(ri25e58), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(qtc9fa5))             ;    FD1P3DX vx3d7d (.D(ps58491), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(jp4fd2d))             ;    FD1P3DX dm733ca (.D(jpc248b), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(bl7e96e))             ;    FD1P3DX ux9a698 (.D(irb1e36), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(lqf4b76))             ;    FD1P3BX ec24901 (.D(qv8f1b5), .SP(thfc1f7), .CK(th71b4d), .PD(uic1f26),        .Q(ec31ecb))             ;    FD1P3DX nr402d4 (.D(go78dad), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(kf8f659))             ;    FD1P3DX bn327c0 (.D(ir36b4c), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(yk59be9))             ;    FD1P3DX aa3b91d (.D(ntb5a64), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(zxcdf48))             ;    FD1P3DX al4476c (.D(xw6993b), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(zk48f47))             ;    FD1P3DX pu25916 (.D(ww4c9da), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(by47a3b))             ;    FD1P3DX fp94ff2 (.D(hd2768e), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(co3b5a3))             ;    FD1P3DX ecb34e2 (.D(uk3b476), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(xwdad19))             ;    FD1P3DX ng8cae2 (.D(wwd1d8a), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(lf19760))             ;    FD1P3DX co9d267 (.D(fp8ec50), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(aycbb07))             ;    FD1P3DX tucf245 (.D(anb1433), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(tw8672e))             ;    FD1P3DX dz5a8f0 (.D(pha5bb3), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(xjc2809))             ;    FD1P3DX sj39289 (.D(jr2dd9e), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(do1404e))             ;    FD1P3DX dz64f59 (.D(rt6ecf6), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(nta0273))             ;    FD1P3DX ui77c80 (.D(fa767b7), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(vk139f))             ;    FD1P3DX ym5b61 (.D(qib3dbb), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(ph9cfa))             ;    FD1P3DX mr4e0ff (.D(zz9edd8), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(al4e7d7))             ;    FD1P3DX blec445 (.D(ldf6ec7), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(jc73ebd))             ;    FD1P3DX su7867a (.D(jeb763e), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(ux9f5ea))             ;    FD1P3DX mt85cea (.D(yzbb1f3), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(qgfaf54))             ;    FD1P3DX xya844f (.D(thd8f9d), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(dzd7aa0))             ;    FD1P3DX sudb6ff (.D(tw8672e), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(lsbd507))             ;    FD1P3DX fac02cc (.D(ec31ecb), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(ldc7cee))             ;    FD1P3DX cb12620 (.D(kf8f659), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(ks3e776))             ;    FD1P3DX db22012 (.D(yk59be9), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(ldf3bb1))             ;    FD1P3DX kfb196a (.D(zxcdf48), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(ie9dd8e))             ;    FD1P3DX yzab9ef (.D(zk48f47), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(zkeec70))             ;    FD1P3DX gbe8bc8 (.D(by47a3b), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(rg76383))             ;    FD1P3DX tj274bd (.D(co3b5a3), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(kfb1c1b))             ;    FD1P3DX dm73e5a (.D(xwdad19), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(hd8e0dd))             ;    FD1P3DX db94c77 (.D(lf19760), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(of706ef))             ;    FD1P3DX ayf0385 (.D(aycbb07), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(hq8377c))             ;    FD1P3DX ne47766 (.D(tw8672e), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(je1bbe3))             ;    FD1S3DX qi98d95 (.D(nrddf1b), .CK(th71b4d), .CD(ne69bc9), .Q(sh541d1))             ;    FD1S3DX twa8955 (.D(meef8de), .CK(th71b4d), .CD(ne69bc9), .Q(qv746e))             ;    FD1S3DX tjaaadf (.D(rg7c6f1), .CK(th71b4d), .CD(ne69bc9), .Q(ead1bab))             ;    FD1S3DX cmfff2b (.D(lde378a), .CK(th71b4d), .CD(ne69bc9), .Q(th6eac1))             ;    FD1S3DX xw581c8 (.D(ba1bc56), .CK(th71b4d), .CD(ne69bc9), .Q(uxab07c))             ;    FD1S3DX ww43766 (.D(ykde2b3), .CK(th71b4d), .CD(ne69bc9), .Q(icc1f23))             ;    FD1S3DX qi317b2 (.D(xwf1598), .CK(th71b4d), .CD(ne69bc9), .Q(dm7c8c8))             ;    FD1S3DX mt90d7b (.D(cb8acc2), .CK(th71b4d), .CD(ne69bc9), .Q(kf2321b))             ;    FD1S3DX uvdc4f6 (.D(ui56614), .CK(th71b4d), .CD(ne69bc9), .Q(fnc86e7))             ;    FD1S3DX vxb59fe (.D(mgb30a0), .CK(th71b4d), .CD(ne69bc9), .Q(tw1b9f1))             ;    FD1S3DX enf7052 (.D(uk98501), .CK(\r
+th71b4d), .CD(ne69bc9), .Q(wje7c5c))             ;    FD1S3DX oh9540b (.D(xjc2809), .CK(of4e369), .CD(uic1f26), .Q(psf1729))             ;    FD1S3DX tu5ddf2 (.D(do1404e), .CK(of4e369), .CD(uic1f26), .Q(kq5ca56))             ;    FD1S3DX aa9262d (.D(nta0273), .CK(of4e369), .CD(uic1f26), .Q(ep29581))             ;    FD1S3DX me6841f (.D(vk139f), .CK(of4e369), .CD(uic1f26), .Q(ic5606e))             ;    FD1S3DX nrf9650 (.D(ph9cfa), .CK(of4e369), .CD(uic1f26), .Q(db81b86))             ;    FD1S3DX fc8625e (.D(al4e7d7), .CK(of4e369), .CD(uic1f26), .Q(rt6e1bd))             ;    FD1S3DX fnf30a4 (.D(jc73ebd), .CK(of4e369), .CD(uic1f26), .Q(tw86f75))             ;    FD1S3DX bn27394 (.D(ux9f5ea), .CK(of4e369), .CD(uic1f26), .Q(ribdd56))             ;    FD1S3DX mga6a46 (.D(qgfaf54), .CK(of4e369), .CD(uic1f26), .Q(al7559b))             ;    FD1S3DX uk31459 (.D(dzd7aa0), .CK(of4e369), .CD(uic1f26), .Q(go566e7))             ;    FD1S3DX fnc8b79 (.D(lsbd507), .CK(of4e369), .CD(uic1f26), .Q(lf9b9c1))             ;    FD1S3DX facffa3 (.D(sh541d1), .CK(th71b4d), .CD(ne69bc9), .Q(meea83a))             ;    FD1S3DX gq1a890 (.D(qv746e), .CK(th71b4d), .CD(ne69bc9), .Q(dba0e8d))             ;    FD1S3DX lf812a5 (.D(ead1bab), .CK(th71b4d), .CD(ne69bc9), .Q(do3a375))             ;    FD1S3DX qi2eda6 (.D(th6eac1), .CK(th71b4d), .CD(ne69bc9), .Q(ou8dd58))             ;    FD1S3DX gq31428 (.D(uxab07c), .CK(th71b4d), .CD(ne69bc9), .Q(wj7560f))             ;    FD1S3DX bl40ba7 (.D(icc1f23), .CK(th71b4d), .CD(ne69bc9), .Q(zk583e4))             ;    FD1S3DX ls3f27b (.D(dm7c8c8), .CK(th71b4d), .CD(ne69bc9), .Q(qif919))             ;    FD1S3DX sudbd7f (.D(kf2321b), .CK(th71b4d), .CD(ne69bc9), .Q(fae4643))             ;    FD1S3DX xjf927d (.D(fnc86e7), .CK(th71b4d), .CD(ne69bc9), .Q(vx190dc))             ;    FD1S3DX psee871 (.D(tw1b9f1), .CK(th71b4d), .CD(ne69bc9), .Q(su4373e))             ;    FD1S3DX lf8bd1e (.D(wje7c5c), .CK(th71b4d), .CD(ne69bc9), .Q(ofdcf8b))             ;    FD1S3DX rtf6a8b (.D(psf1729), .CK(of4e369), .CD(uic1f26), .Q(ou3e2e5))             ;    FD1S3DX mr5edae (.D(kq5ca56), .CK(of4e369), .CD(uic1f26), .Q(rv8b94a))             ;    FD1S3DX gb75c3d (.D(ep29581), .CK(of4e369), .CD(uic1f26), .Q(ose52b0))             ;    FD1S3DX kded947 (.D(ic5606e), .CK(of4e369), .CD(uic1f26), .Q(hb4ac0d))             ;    FD1S3DX ux3c572 (.D(db81b86), .CK(of4e369), .CD(uic1f26), .Q(xlb0370))             ;    FD1S3DX zz94a20 (.D(rt6e1bd), .CK(of4e369), .CD(uic1f26), .Q(epdc37))             ;    FD1S3DX tj6fa2 (.D(tw86f75), .CK(of4e369), .CD(uic1f26), .Q(cz70dee))             ;    FD1S3DX lf16d13 (.D(ribdd56), .CK(of4e369), .CD(uic1f26), .Q(zz37baa))             ;    FD1S3DX ux9f117 (.D(al7559b), .CK(of4e369), .CD(uic1f26), .Q(neeeab3))             ;    FD1S3DX mgbca3d (.D(go566e7), .CK(of4e369), .CD(uic1f26), .Q(bnaacdc))             ;    FD1S3DX rte9396 (.D(lf9b9c1), .CK(of4e369), .CD(uic1f26), .Q(ecb3738))             ;    FD1S3DX zmb7343 (.D(cb33973), .CK(of4e369), .CD(ne69bc9), .Q(ohdcc2))             ;    FD1S3DX ls1b389 (.D(cme5ce2), .CK(of4e369), .CD(ne69bc9), .Q(th6e615))             ;    FD1S3DX hb4a872 (.D(gq2e710), .CK(of4e369), .CD(ne69bc9), .Q(ie98573))             ;    FD1S3DX je96b18 (.D(fc9c402), .CK(of4e369), .CD(ne69bc9), .Q(fnc2b99))             ;    FD1S3DX alc3e55 (.D(gbe2013), .CK(of4e369), .CD(ne69bc9), .Q(sjae670))             ;    FD1S3DX gqac196 (.D(gd804e1), .CK(of4e369), .CD(ne69bc9), .Q(jc73384))             ;    FD1S3DX irb19f2 (.D(yz270c), .CK(of4e369), .CD(ne69bc9), .Q(osce11a))             ;    FD1S3DX ir9564c (.D(tw9c32f), .CK(of4e369), .CD(ne69bc9), .Q(sh708d1))             ;    FD1S3DX al65869 (.D(nee197b), .CK(of4e369), .CD(ne69bc9), .Q(yz2346e))             ;    FD1S3DX ay4cba2 (.D(gb65ed7), .CK(of4e369), .CD(ne69bc9), .Q(aa1a374))             ;    FD1S3DX hq11872 (.D(ng2f6bc), .CK(of4e369), .CD(ne69bc9), .Q(aa8dd00))             ;    FD1S3DX gq92599 (.D(wje2ef8), .CK(th71b4d), .CD(uic1f26), .Q(cb7df0))             ;    FD1S3DX nrc828b (.D(irbbe2c), .CK(th71b4d), .CD(uic1f26), .Q(qi3ef84))             ;    FD1S3DX sh5e86e (.D(psdf164), .CK(th71b4d), .CD(uic1f26), .Q(qvbe104))             ;    FD1S3DX kd7552f (.D(nec5915), .CK(th71b4d), .CD(uic1f26), .Q(eaf0825))             ;    FD1S3DX xw7cf33 (.D(gd2c8ab), .CK(th71b4d), .CD(uic1f26), .Q(ls2094e))             ;    FD1S3DX nt9bb75 (.D(tj22ae7), .CK(th71b4d), .CD(uic1f26), .Q(ba4a72))             ;    FD1S3DX tjafd3d (.D(qi1573f), .CK(th71b4d), .CD(uic1f26), .Q(wl29c9b))             ;    FD1S3DX eaefcdf (.D(qg5cfcd), .CK(th71b4d), .CD(uic1f26), .Q(qt4e4dc))             ;    FD1S3DX dzf9ffa (.D(mre7e68), .CK(th71b4d), .CD(uic1f26), .Q(zm93729))             ;    FD1S3DX vvd7508 (.D(jpf9a2b), .CK(th71b4d), .CD(uic1f26), .Q(db9b94a))             ;    FD1S3DX ic46c6d (.D(dzcd15f), .CK(th71b4d), .CD(uic1f26), .Q(czdce0f))             ;    FD1S3BX qg68b49 (.D(cb70bc), .CK(th71b4d), .PD(uic1f26), .Q(ene707c))             ;    FD1S3DX ho48fd8 (.D(rv8bf07), .CK(of4e369), .CD(ne69bc9), .Q(zz383e4))             ;    FD1S3BX kdc34df (.D(ld4af0d), .CK(th71b4d), .PD(uic1f26), .Q(ba9c539))             ;    FD1S3DX yxfd13b (.D(ld7400f), .CK(of4e369), .CD(ne69bc9), .Q(ale29cb))             ;    defparam czdc970.INJECT1_1 = "NO" ;    defparam czdc970.INJECT1_0 = "NO" ;    defparam czdc970.INIT1 =  16'h66AA ;    defparam czdc970.INIT0 =  16'h66AA ;    CCU2C czdc970 (.A0(ld6e801), .A1(lfa007e), .B0(ld6e801), .B1(lfa007e),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(), .S0(), .S1(), .COUT(nee4c43));    defparam zm252ac.INJECT1_1 = "NO" ;    defparam zm252ac.INJECT1_0 = "NO" ;    defparam zm252ac.INIT1 =  16'hAA00 ;    defparam zm252ac.INIT0 =  16'hAA00 ;    CCU2C zm252ac (.A0(sue5da9), .A1(ec2ed48), .B0(lfa007e), .B1(lfa007e),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(nee4c43), .S0(ief931), .S1(rg7c988), .COUT(ec886a0));    defparam nt8e731.INJECT1_1 = "NO" ;    defparam nt8e731.INJECT1_0 = "NO" ;    defparam nt8e731.INIT1 =  16'hAA00 ;    defparam nt8e731.INIT0 =  16'hAA00 ;    CCU2C nt8e731 (.A0(ho482b1), .A1(kd4158a), .B0(lfa007e), .B1(lfa007e),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(ec886a0), .S0(sj2621a), .S1(ec310d4), .COUT(med4009));    defparam al448cb.INJECT1_1 = "NO" ;    defparam al448cb.INJECT1_0 = "NO" ;    defparam al448cb.INIT1 =  16'hAA00 ;    defparam al448cb.INIT0 =  16'hAA00 ;    CCU2C al448cb (.A0(ir8a804), .A1(sh54024), .B0(lfa007e), .B1(lfa007e),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(med4009), .S0(kq43500), .S1(gq1a801), .COUT(ls1278));    defparam yz12202.INJECT1_1 = "NO" ;    defparam yz12202.INJECT1_0 = "NO" ;    defparam yz12202.INIT1 =  16'hAA00 ;    defparam yz12202.INIT0 =  16'hAA00 ;    CCU2C yz12202 (.A0(aa24bcb), .A1(ri25e58), .B0(lfa007e), .B1(lfa007e),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(ls1278), .S0(hda0049), .S1(ym24f), .COUT(rt4f0b1));    defparam gqa9061.INJECT1_1 = "NO" ;    defparam gqa9061.INJECT1_0 = "NO" ;    defparam gqa9061.INIT1 =  16'hAA00 ;    defparam gqa9061.INIT0 =  16'hAA00 ;    CCU2C gqa9061 (.A0(ps58491), .A1(jpc248b), .B0(lfa007e), .B1(lfa007e),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(rt4f0b1), .S0(nt93c2), .S1(ea49e16), .COUT(db163c6));    defparam ng30cac.INJECT1_1 = "NO" ;    defparam ng30cac.INJECT1_0 = "NO" ;    defparam ng30cac.INIT1 =  16'hAA00 ;    defparam ng30cac.INIT0 =  16'hAA00 ;    CCU2C ng30cac (.A0(irb1e36), .A1(ld6e801), .B0(lfa007e), .B1(lfa007e),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(db163c6), .S0(os7858f), .S1(), .COUT(nrc2c78));    defparam by486b9.INJECT1_1 = "NO" ;    defparam by486b9.INJECT1_0 = "NO" ;    defparam by486b9.INIT1 =  16'h66AA ;    defparam by486b9.INIT0 =  16'h66AA ;    CCU2C by486b9 (.A0(ld6e801), .A1(lfa007e), .B0(ld6e801), .B1(lfa007e),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(), .S0(), .S1(), .COUT(enc6d69));    defparam rtec55a.INJECT1_1 = "NO" ;    defparam rtec55a.INJECT1_0 = "NO" ;    defparam rtec55a.INIT1 =  16'hAA00 ;\r
+    defparam rtec55a.INIT0 =  16'hAA00 ;    CCU2C rtec55a (.A0(ec31ecb), .A1(kf8f659), .B0(lfa007e), .B1(lfa007e),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(enc6d69), .S0(qv8f1b5), .S1(go78dad), .COUT(doad327));    defparam ww4ca01.INJECT1_1 = "NO" ;    defparam ww4ca01.INJECT1_0 = "NO" ;    defparam ww4ca01.INIT1 =  16'hAA00 ;    defparam ww4ca01.INIT0 =  16'hAA00 ;    CCU2C ww4ca01 (.A0(yk59be9), .A1(zxcdf48), .B0(lfa007e), .B1(lfa007e),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(doad327), .S0(ir36b4c), .S1(ntb5a64), .COUT(fn64ed1));    defparam wl26283.INJECT1_1 = "NO" ;    defparam wl26283.INJECT1_0 = "NO" ;    defparam wl26283.INIT1 =  16'hAA00 ;    defparam wl26283.INIT0 =  16'hAA00 ;    CCU2C wl26283 (.A0(zk48f47), .A1(by47a3b), .B0(lfa007e), .B1(lfa007e),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(fn64ed1), .S0(xw6993b), .S1(ww4c9da), .COUT(lqda3b1));    defparam an90107.INJECT1_1 = "NO" ;    defparam an90107.INJECT1_0 = "NO" ;    defparam an90107.INIT1 =  16'hAA00 ;    defparam an90107.INIT0 =  16'hAA00 ;    CCU2C an90107 (.A0(co3b5a3), .A1(xwdad19), .B0(lfa007e), .B1(lfa007e),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(lqda3b1), .S0(hd2768e), .S1(uk3b476), .COUT(tu76286));    defparam wwff6b5.INJECT1_1 = "NO" ;    defparam wwff6b5.INJECT1_0 = "NO" ;    defparam wwff6b5.INIT1 =  16'hAA00 ;    defparam wwff6b5.INIT0 =  16'hAA00 ;    CCU2C wwff6b5 (.A0(lf19760), .A1(aycbb07), .B0(lfa007e), .B1(lfa007e),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(tu76286), .S0(wwd1d8a), .S1(fp8ec50), .COUT(ld50ce5));    defparam zxc8c00.INJECT1_1 = "NO" ;    defparam zxc8c00.INJECT1_0 = "NO" ;    defparam zxc8c00.INIT1 =  16'hAA00 ;    defparam zxc8c00.INIT0 =  16'hAA00 ;    CCU2C zxc8c00 (.A0(tw8672e), .A1(ld6e801), .B0(lfa007e), .B1(lfa007e),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(ld50ce5), .S0(anb1433), .S1(), .COUT(an8a19c));    defparam ec2b205.INJECT1_1 = "NO" ;    defparam ec2b205.INJECT1_0 = "NO" ;    defparam ec2b205.INIT1 =  16'h0000 ;    defparam ec2b205.INIT0 =  16'h0000 ;    CCU2C ec2b205 (.A0(lfa007e), .A1(lfa007e), .B0(lfa007e),        .B1(lfa007e), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e),        .D1(lfa007e), .CIN(), .S0(), .S1(), .COUT(pu9cb9c));    defparam hd8bd85.INJECT1_1 = "NO" ;    defparam hd8bd85.INJECT1_0 = "NO" ;    defparam hd8bd85.INIT1 =  16'h99AA ;    defparam hd8bd85.INIT0 =  16'h99AA ;    CCU2C hd8bd85 (.A0(lfa007e), .A1(sue5da9), .B0(ld6e801), .B1(gd17976),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(pu9cb9c), .S0(), .S1(cb33973), .COUT(rg73880));    defparam kf33ad4.INJECT1_1 = "NO" ;    defparam kf33ad4.INJECT1_0 = "NO" ;    defparam kf33ad4.INIT1 =  16'h99AA ;    defparam kf33ad4.INIT0 =  16'h99AA ;    CCU2C kf33ad4 (.A0(ec2ed48), .A1(ho482b1), .B0(iebcbb5), .B1(phb520a),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(rg73880), .S0(cme5ce2), .S1(gq2e710), .COUT(mg1009c));    defparam phaa7ab.INJECT1_1 = "NO" ;    defparam phaa7ab.INJECT1_0 = "NO" ;    defparam phaa7ab.INIT1 =  16'h99AA ;    defparam phaa7ab.INIT0 =  16'h99AA ;    CCU2C phaa7ab (.A0(kd4158a), .A1(ir8a804), .B0(oua9056), .B1(ui562a0),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(mg1009c), .S0(fc9c402), .S1(gbe2013), .COUT(rv13865));    defparam lq5df1b.INJECT1_1 = "NO" ;    defparam lq5df1b.INJECT1_0 = "NO" ;    defparam lq5df1b.INIT1 =  16'h99AA ;    defparam lq5df1b.INIT0 =  16'h99AA ;    CCU2C lq5df1b (.A0(sh54024), .A1(aa24bcb), .B0(ohb1500), .B1(sw92f),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(rv13865), .S0(gd804e1), .S1(yz270c), .COUT(tjcbda));    defparam hd32be5.INJECT1_1 = "NO" ;    defparam hd32be5.INJECT1_0 = "NO" ;    defparam hd32be5.INIT1 =  16'h99AA ;    defparam hd32be5.INIT0 =  16'h99AA ;    CCU2C hd32be5 (.A0(ri25e58), .A1(ps58491), .B0(tw4979),        .B1(xw79612), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e),        .D1(lfa007e), .CIN(tjcbda), .S0(tw9c32f), .S1(nee197b), .COUT(jcdaf17));    defparam ne4d155.INJECT1_1 = "NO" ;    defparam ne4d155.INJECT1_0 = "NO" ;    defparam ne4d155.INIT1 =  16'h99AA ;    defparam ne4d155.INIT0 =  16'h99AA ;    CCU2C ne4d155 (.A0(jpc248b), .A1(xj7b5e2), .B0(eacb092), .B1(ld6e801),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(jcdaf17), .S0(gb65ed7), .S1(ng2f6bc), .COUT(mgbc5df));    defparam bab845a.INJECT1_1 = "NO" ;    defparam bab845a.INJECT1_0 = "NO" ;    defparam bab845a.INIT1 =  16'h0000 ;    defparam bab845a.INIT0 =  16'h0000 ;    CCU2C bab845a (.A0(lfa007e), .A1(lfa007e), .B0(lfa007e), .B1(lfa007e),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(mgbc5df), .S0(nrd78bb), .S1(), .COUT());    defparam rgd5621.INJECT1_1 = "NO" ;    defparam rgd5621.INJECT1_0 = "NO" ;    defparam rgd5621.INIT1 =  16'h0000 ;    defparam rgd5621.INIT0 =  16'h0000 ;    CCU2C rgd5621 (.A0(lfa007e), .A1(lfa007e), .B0(lfa007e),        .B1(lfa007e), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e),        .D1(lfa007e), .CIN(), .S0(), .S1(), .COUT(qv177c5));    defparam twe316.INJECT1_1 = "NO" ;    defparam twe316.INJECT1_0 = "NO" ;    defparam twe316.INIT1 =  16'h99AA ;    defparam twe316.INIT0 =  16'h99AA ;    CCU2C twe316 (.A0(lfa007e), .A1(ykf0c7b), .B0(ld6e801), .B1(ec31ecb),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(qv177c5), .S0(), .S1(wje2ef8), .COUT(enf8b22));    defparam rgee357.INJECT1_1 = "NO" ;    defparam rgee357.INJECT1_0 = "NO" ;    defparam rgee357.INIT1 =  16'h99AA ;    defparam rgee357.INIT0 =  16'h99AA ;    CCU2C rgee357 (.A0(ng863d9), .A1(ipd966f), .B0(kf8f659), .B1(yk59be9),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(enf8b22), .S0(irbbe2c), .S1(psdf164), .COUT(th6455c));    defparam ea4991c.INJECT1_1 = "NO" ;    defparam ea4991c.INJECT1_0 = "NO" ;    defparam ea4991c.INIT1 =  16'h99AA ;    defparam ea4991c.INIT0 =  16'h99AA ;    CCU2C ea4991c (.A0(cmcb37d), .A1(os7d23d), .B0(zxcdf48), .B1(zk48f47),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(th6455c), .S0(nec5915), .S1(gd2c8ab), .COUT(mtab9f9));    defparam rv9b44d.INJECT1_1 = "NO" ;    defparam rv9b44d.INJECT1_0 = "NO" ;    defparam rv9b44d.INIT1 =  16'h99AA ;    defparam rv9b44d.INIT0 =  16'h99AA ;    CCU2C rv9b44d (.A0(nre91e8), .A1(ofe8ed6), .B0(by47a3b), .B1(co3b5a3),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(mtab9f9), .S0(tj22ae7), .S1(qi1573f), .COUT(ng3f345));    defparam bn1c928.INJECT1_1 = "NO" ;    defparam bn1c928.INJECT1_0 = "NO" ;    defparam bn1c928.INIT1 =  16'h99AA ;    defparam bn1c928.INIT0 =  16'h99AA ;    CCU2C bn1c928 (.A0(dm476b4), .A1(sjb465d), .B0(xwdad19),        .B1(lf19760), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(ng3f345), .S0(qg5cfcd), .S1(mre7e68), .COUT(nr457f0));    defparam uie009b.INJECT1_1 = "NO" ;    defparam uie009b.INJECT1_0 = "NO" ;    defparam uie009b.INIT1 =  16'h99AA ;    defparam uie009b.INIT0 =  16'h99AA ;    CCU2C uie009b (.A0(mga32ec), .A1(cm68afe), .B0(aycbb07), .B1(ld6e801),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(nr457f0), .S0(jpf9a2b), .S1(dzcd15f), .COUT(bl5fc31));    defparam kdfdc9e.INJECT1_1 = "NO" ;    defparam kdfdc9e.INJECT1_0 = "NO" ;    defparam kdfdc9e.INIT1 =  16'h0000 ;    defparam kdfdc9e.INIT0 =  16'h0000 ;    CCU2C kdfdc9e (.A0(lfa007e), .A1(lfa007e), .B0(lfa007e), .B1(lfa007e),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(bl5fc31), .S0(aa2bf86), .S1(), .COUT());    defparam jrb58ea.INJECT1_1 = "NO" ;    defparam jrb58ea.INJECT1_0 = "NO" ;    defparam jrb58ea.INIT1 =  16'h66AA ;    defparam jrb58ea.INIT0 =  16'h66AA ;    CCU2C jrb58ea (.A0(ld6e801), .A1(thfc1f7), .B0(ld6e801), .B1(thfc1f7),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(), .S0(), .S1(), .COUT(zkfe18f));    defparam ym1ffe6.INJECT1_1 = "NO" ;    defparam ym1ffe6.INJECT1_0 = "NO" ;    defparam ym1ffe6.INIT1 =\r
+  16'h99AA ;    defparam ym1ffe6.INIT0 =  16'h99AA ;    CCU2C ym1ffe6 (.A0(ec31ecb), .A1(kf8f659), .B0(ykf0c7b), .B1(ng863d9),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(zkfe18f), .S0(), .S1(), .COUT(nr7b2cd));    defparam yz8b23.INJECT1_1 = "NO" ;    defparam yz8b23.INJECT1_0 = "NO" ;    defparam yz8b23.INIT1 =  16'h99AA ;    defparam yz8b23.INIT0 =  16'h99AA ;    CCU2C yz8b23 (.A0(yk59be9), .A1(zxcdf48), .B0(ipd966f), .B1(cmcb37d),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(nr7b2cd), .S0(), .S1(), .COUT(cz6fa47));    defparam mr7fe91.INJECT1_1 = "NO" ;    defparam mr7fe91.INJECT1_0 = "NO" ;    defparam mr7fe91.INIT1 =  16'h99AA ;    defparam mr7fe91.INIT0 =  16'h99AA ;    CCU2C mr7fe91 (.A0(zk48f47), .A1(by47a3b), .B0(os7d23d), .B1(nre91e8),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(cz6fa47), .S0(), .S1(), .COUT(lf3d1da));    defparam ec1a3b6.INJECT1_1 = "NO" ;    defparam ec1a3b6.INJECT1_0 = "NO" ;    defparam ec1a3b6.INIT1 =  16'h99AA ;    defparam ec1a3b6.INIT0 =  16'h99AA ;    CCU2C ec1a3b6 (.A0(co3b5a3), .A1(xwdad19), .B0(ofe8ed6), .B1(dm476b4),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(lf3d1da), .S0(), .S1(), .COUT(uvd68cb));    defparam ldf6be2.INJECT1_1 = "NO" ;    defparam ldf6be2.INJECT1_0 = "NO" ;    defparam ldf6be2.INIT1 =  16'h99AA ;    defparam ldf6be2.INIT0 =  16'h99AA ;    CCU2C ldf6be2 (.A0(lf19760), .A1(aycbb07), .B0(sjb465d), .B1(mga32ec),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(uvd68cb), .S0(), .S1(), .COUT(fa5d838));    defparam bn16996.INJECT1_1 = "NO" ;    defparam bn16996.INJECT1_0 = "NO" ;    defparam bn16996.INIT1 =  16'h99AA ;    defparam bn16996.INIT0 =  16'h99AA ;    CCU2C bn16996 (.A0(yx60e17), .A1(ld6e801), .B0(dzec1c2),        .B1(ld6e801), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e),        .D1(lfa007e), .CIN(fa5d838), .S0(), .S1(), .COUT(xl385e5));    defparam vi6cfe5.INJECT1_1 = "NO" ;    defparam vi6cfe5.INJECT1_0 = "NO" ;    defparam vi6cfe5.INIT1 =  16'h0000 ;    defparam vi6cfe5.INIT0 =  16'h0000 ;    CCU2C vi6cfe5 (.A0(lfa007e), .A1(lfa007e), .B0(lfa007e), .B1(lfa007e),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(xl385e5), .S0(cb70bc), .S1(), .COUT());    defparam ym82c41.INJECT1_1 = "NO" ;    defparam ym82c41.INJECT1_0 = "NO" ;    defparam ym82c41.INIT1 =  16'h66AA ;    defparam ym82c41.INIT0 =  16'h66AA ;    CCU2C ym82c41 (.A0(ld6e801), .A1(cobc373), .B0(ld6e801), .B1(cobc373),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(), .S0(), .S1(), .COUT(hbc2f2e));    defparam wl337ff.INJECT1_1 = "NO" ;    defparam wl337ff.INJECT1_0 = "NO" ;    defparam wl337ff.INIT1 =  16'h99AA ;    defparam wl337ff.INIT0 =  16'h99AA ;    CCU2C wl337ff (.A0(sue5da9), .A1(ec2ed48), .B0(gd17976), .B1(iebcbb5),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(hbc2f2e), .S0(), .S1(), .COUT(fa76a41));    defparam hbd8c9b.INJECT1_1 = "NO" ;    defparam hbd8c9b.INJECT1_0 = "NO" ;    defparam hbd8c9b.INIT1 =  16'h99AA ;    defparam hbd8c9b.INIT0 =  16'h99AA ;    CCU2C hbd8c9b (.A0(ho482b1), .A1(kd4158a), .B0(phb520a), .B1(oua9056),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(fa76a41), .S0(), .S1(), .COUT(coac54));    defparam hq30b38.INJECT1_1 = "NO" ;    defparam hq30b38.INJECT1_0 = "NO" ;    defparam hq30b38.INIT1 =  16'h99AA ;    defparam hq30b38.INIT0 =  16'h99AA ;    CCU2C hq30b38 (.A0(ir8a804), .A1(sh54024), .B0(ui562a0), .B1(ohb1500),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(coac54), .S0(), .S1(), .COUT(dba0125));    defparam qi319ee.INJECT1_1 = "NO" ;    defparam qi319ee.INJECT1_0 = "NO" ;    defparam qi319ee.INIT1 =  16'h99AA ;    defparam qi319ee.INIT0 =  16'h99AA ;    CCU2C qi319ee (.A0(aa24bcb), .A1(ri25e58), .B0(sw92f), .B1(tw4979),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(dba0125), .S0(), .S1(), .COUT(xy2f2c2));    defparam ose56a6.INJECT1_1 = "NO" ;    defparam ose56a6.INJECT1_0 = "NO" ;    defparam ose56a6.INIT1 =  16'h99AA ;    defparam ose56a6.INIT0 =  16'h99AA ;    CCU2C ose56a6 (.A0(ps58491), .A1(jpc248b), .B0(xw79612), .B1(eacb092),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(xy2f2c2), .S0(), .S1(), .COUT(an1245f));    defparam mt904a5.INJECT1_1 = "NO" ;    defparam mt904a5.INJECT1_0 = "NO" ;    defparam mt904a5.INIT1 =  16'h99AA ;    defparam mt904a5.INIT0 =  16'h99AA ;    CCU2C mt904a5 (.A0(xl917e0), .A1(ld6e801), .B0(ie922fc),        .B1(ld6e801), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e),        .D1(lfa007e), .CIN(an1245f), .S0(), .S1(), .COUT(nr5f83e));    defparam shd3f61.INJECT1_1 = "NO" ;    defparam shd3f61.INJECT1_0 = "NO" ;    defparam shd3f61.INIT1 =  16'h0000 ;    defparam shd3f61.INIT0 =  16'h0000 ;    CCU2C shd3f61 (.A0(lfa007e), .A1(lfa007e), .B0(lfa007e), .B1(lfa007e),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(nr5f83e), .S0(rv8bf07), .S1(), .COUT());    defparam yx707c8.INJECT1_1 = "NO" ;    defparam yx707c8.INJECT1_0 = "NO" ;    defparam yx707c8.INIT1 =  16'h66AA ;    defparam yx707c8.INIT0 =  16'h66AA ;    CCU2C yx707c8 (.A0(ld6e801), .A1(thfc1f7), .B0(ld6e801), .B1(thfc1f7),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(), .S0(), .S1(), .COUT(yke0fbe));    defparam vx16390.INJECT1_1 = "NO" ;    defparam vx16390.INJECT1_0 = "NO" ;    defparam vx16390.INIT1 =  16'h99AA ;    defparam vx16390.INIT0 =  16'h99AA ;    CCU2C vx16390 (.A0(wj6f253[0]), .A1(wj6f253[1]), .B0(cb7df0),        .B1(qi3ef84), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e),        .D1(lfa007e), .CIN(yke0fbe), .S0(), .S1(), .COUT(czf7c20));    defparam goe0fb3.INJECT1_1 = "NO" ;    defparam goe0fb3.INJECT1_0 = "NO" ;    defparam goe0fb3.INIT1 =  16'h99AA ;    defparam goe0fb3.INIT0 =  16'h99AA ;    CCU2C goe0fb3 (.A0(wj6f253[2]), .A1(wj6f253[3]), .B0(qvbe104),        .B1(eaf0825), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e),        .D1(lfa007e), .CIN(czf7c20), .S0(), .S1(), .COUT(lf84129));    defparam xw66d00.INJECT1_1 = "NO" ;    defparam xw66d00.INJECT1_0 = "NO" ;    defparam xw66d00.INIT1 =  16'h99AA ;    defparam xw66d00.INIT0 =  16'h99AA ;    CCU2C xw66d00 (.A0(wj6f253[4]), .A1(wj6f253[5]), .B0(ls2094e),        .B1(ba4a72), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e),        .D1(lfa007e), .CIN(lf84129), .S0(), .S1(), .COUT(ng25393));    defparam ukbca9a.INJECT1_1 = "NO" ;    defparam ukbca9a.INJECT1_0 = "NO" ;    defparam ukbca9a.INIT1 =  16'h99AA ;    defparam ukbca9a.INIT0 =  16'h99AA ;    CCU2C ukbca9a (.A0(wj6f253[6]), .A1(wj6f253[7]), .B0(wl29c9b),        .B1(qt4e4dc), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e),        .D1(lfa007e), .CIN(ng25393), .S0(), .S1(), .COUT(go726e5));    defparam epb10e7.INJECT1_1 = "NO" ;    defparam epb10e7.INJECT1_0 = "NO" ;    defparam epb10e7.INIT1 =  16'h99AA ;    defparam epb10e7.INIT0 =  16'h99AA ;    CCU2C epb10e7 (.A0(wj6f253[8]), .A1(wj6f253[9]), .B0(zm93729),        .B1(db9b94a), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e),        .D1(lfa007e), .CIN(go726e5), .S0(), .S1(), .COUT(qtdca57));    defparam vk99feb.INJECT1_1 = "NO" ;    defparam vk99feb.INJECT1_0 = "NO" ;    defparam vk99feb.INIT1 =  16'h99AA ;    defparam vk99feb.INIT0 =  16'h99AA ;    CCU2C vk99feb (.A0(yz295e1), .A1(ld6e801), .B0(kqe52bc), .B1(ld6e801),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(qtdca57), .S0(), .S1(), .COUT(ps5786e));    defparam al7f50f.INJECT1_1 = "NO" ;    defparam al7f50f.INJECT1_0 = "NO" ;    defparam al7f50f.INIT1 =  16'h0000 ;    defparam al7f50f.INIT0 =  16'h0000 ;    CCU2C al7f50f (.A0(lfa007e), .A1(lfa007e), .B0(lfa007e), .B1(lfa007e),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(ps5786e), .S0(ld4af0d), .S1(), .COUT());    defparam ksa93bc.INJECT1_1 = "NO" ;    defparam ksa93bc.INJECT1_0 = "NO" ;    defparam ksa93bc.INIT1 =  16'h66AA ;    defparam ksa93bc.INIT0 =  16'h66AA ;    CCU2C ksa93bc (.A0(ld6e801), .A1(cobc373), .B0(ld6e801), .B1(cobc373),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(\r
+lfa007e),        .CIN(), .S0(), .S1(), .COUT(tue1b98));    defparam jr28c2a.INJECT1_1 = "NO" ;    defparam jr28c2a.INJECT1_0 = "NO" ;    defparam jr28c2a.INIT1 =  16'h99AA ;    defparam jr28c2a.INIT0 =  16'h99AA ;    CCU2C jr28c2a (.A0(ohdcc2), .A1(th6e615), .B0(ps7929c[0]),        .B1(ps7929c[1]), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e),        .D1(lfa007e), .CIN(tue1b98), .S0(), .S1(), .COUT(rg730ae));    defparam ld7430e.INJECT1_1 = "NO" ;    defparam ld7430e.INJECT1_0 = "NO" ;    defparam ld7430e.INIT1 =  16'h99AA ;    defparam ld7430e.INIT0 =  16'h99AA ;    CCU2C ld7430e (.A0(ie98573), .A1(fnc2b99), .B0(ps7929c[2]),        .B1(ps7929c[3]), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e),        .D1(lfa007e), .CIN(rg730ae), .S0(), .S1(), .COUT(ou15cce));    defparam cm59a16.INJECT1_1 = "NO" ;    defparam cm59a16.INJECT1_0 = "NO" ;    defparam cm59a16.INIT1 =  16'h99AA ;    defparam cm59a16.INIT0 =  16'h99AA ;    CCU2C cm59a16 (.A0(sjae670), .A1(jc73384), .B0(ps7929c[4]),        .B1(ps7929c[5]), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e),        .D1(lfa007e), .CIN(ou15cce), .S0(), .S1(), .COUT(xy99c23));    defparam vkbb81.INJECT1_1 = "NO" ;    defparam vkbb81.INJECT1_0 = "NO" ;    defparam vkbb81.INIT1 =  16'h99AA ;    defparam vkbb81.INIT0 =  16'h99AA ;    CCU2C vkbb81 (.A0(osce11a), .A1(sh708d1), .B0(ps7929c[6]),        .B1(ps7929c[7]), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e),        .D1(lfa007e), .CIN(xy99c23), .S0(), .S1(), .COUT(tj8468d));    defparam oh80b3c.INJECT1_1 = "NO" ;    defparam oh80b3c.INJECT1_0 = "NO" ;    defparam oh80b3c.INIT1 =  16'h99AA ;    defparam oh80b3c.INIT0 =  16'h99AA ;    CCU2C oh80b3c (.A0(yz2346e), .A1(aa1a374), .B0(ps7929c[8]),        .B1(ps7929c[9]), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e),        .D1(lfa007e), .CIN(tj8468d), .S0(), .S1(), .COUT(med1ba0));    VLO baa2130 (.Z(ld6e801));    defparam vx84c10.INJECT1_1 = "NO" ;    defparam vx84c10.INJECT1_0 = "NO" ;    defparam vx84c10.INIT1 =  16'h99AA ;    defparam vx84c10.INIT0 =  16'h99AA ;    CCU2C vx84c10 (.A0(aa8dd00), .A1(ld6e801), .B0(ld6e801),        .B1(ld6e801), .C0(lfa007e), .C1(lfa007e), .D0(lfa007e),        .D1(lfa007e), .CIN(med1ba0), .S0(), .S1(), .COUT(ec3f7));    VHI xjc7664 (.Z(lfa007e));    defparam end9939.INJECT1_1 = "NO" ;    defparam end9939.INJECT1_0 = "NO" ;    defparam end9939.INIT1 =  16'h0000 ;    defparam end9939.INIT0 =  16'h0000 ;    CCU2C end9939 (.A0(lfa007e), .A1(lfa007e), .B0(lfa007e), .B1(lfa007e),        .C0(lfa007e), .C1(lfa007e), .D0(lfa007e), .D1(lfa007e),        .CIN(ec3f7), .S0(ld7400f), .S1(), .COUT());    assign ld4a714 = xl220da;    assign su538a7 = sw106d6;\r
+always@* begin hq1fb8<={ui49c6d>>1,vx8bfb1[0]};iefdc3<=vx8bfb1[1];th7ee18<=vx8bfb1[2];alf70c6<=vx8bfb1[3];dob8635<=vx8bfb1[4];czc31aa<=vx8bfb1[5];wl18d55<=vx8bfb1[6];ipc6aac<={wj6f253>>1,vx8bfb1[7]};ng35564<={ps7929c>>1,vx8bfb1[8]};bnaab22<=vx8bfb1[9];jp55917<=vx8bfb1[10];coac8be<=vx8bfb1[11];nr645f0<=vx8bfb1[12];xl22f87<=vx8bfb1[13];yz17c3f<=vx8bfb1[14];yzbe1fd<=vx8bfb1[15];qgf0fed<=vx8bfb1[16];aa87f69<=vx8bfb1[17];ba3fb48<=vx8bfb1[18];mrfda42<=vx8bfb1[19];aled215<=vx8bfb1[20];zk690ad<=vx8bfb1[21];rg4856b<=vx8bfb1[22];lq42b5a<=vx8bfb1[23];ks15ad2<=vx8bfb1[24];lsad690<=vx8bfb1[25];ld6b483<=vx8bfb1[26];hb5a41e<=vx8bfb1[27];thd20f6<=vx8bfb1[28];gd907b6<=vx8bfb1[29];je83db5<=vx8bfb1[30];vk1edaa<=vx8bfb1[31];fnf6d53<=vx8bfb1[32];mgb6a9e<=vx8bfb1[33];tjb54f0<=vx8bfb1[34];xlaa786<=vx8bfb1[35];ww53c36<=vx8bfb1[36];jr9e1b1<=vx8bfb1[37];gof0d8e<=vx8bfb1[38];zm86c71<=vx8bfb1[39];ux3638a<=vx8bfb1[40];irb1c55<=vx8bfb1[41];rv8e2ad<=vx8bfb1[42];rt7156f<=vx8bfb1[43];gd8ab7e<=vx8bfb1[44];dz55bf4<=vx8bfb1[45];hqadfa6<=vx8bfb1[46];al6fd32<=vx8bfb1[47];bl7e995<=vx8bfb1[48];lqf4cae<=vx8bfb1[49];mga6573<=vx8bfb1[50];lf32b98<=vx8bfb1[51];kf95cc6<=vx8bfb1[52];mtae634<=vx8bfb1[53];ne731a4<=vx8bfb1[54];co98d23<=vx8bfb1[55];enc6918<=vx8bfb1[56];gq348c4<=vx8bfb1[57];ana4621<=vx8bfb1[58];wl2310d<=vx8bfb1[59];mt1886c<=vx8bfb1[60];eac4364<=vx8bfb1[61];gq21b20<=vx8bfb1[62];ohd900<=vx8bfb1[63];rg6c805<=vx8bfb1[64];dz6402a<=vx8bfb1[65];tw20157<=vx8bfb1[66];qiabb<=vx8bfb1[67];co55d9<=vx8bfb1[68];ri2aec8<=vx8bfb1[69];fa57643<=vx8bfb1[70];yzbb21a<=vx8bfb1[71];shd90d5<=vx8bfb1[72];hbc86ad<=vx8bfb1[73];ic4356e<=vx8bfb1[74];qi1ab71<=vx8bfb1[75];psd5b89<=vx8bfb1[76];zmadc4a<=vx8bfb1[77];pf6e252<=vx8bfb1[78];nr71296<=vx8bfb1[79];zm894b6<=vx8bfb1[80];zx4a5b2<=vx8bfb1[81];by52d97<=vx8bfb1[82];vk96cbb<=vx8bfb1[83];ymb65db<=vx8bfb1[84];ngb2ed9<=vx8bfb1[85];ym976ca<=vx8bfb1[86];uxbb650<=vx8bfb1[87];kqdb285<=vx8bfb1[88];qtd9428<=vx8bfb1[89];psca145<=vx8bfb1[90];bl50a2b<=vx8bfb1[91];sj8515e<=vx8bfb1[92];rv28af4<=vx8bfb1[93];dz457a6<=vx8bfb1[94];ym2bd36<=vx8bfb1[95];kd5e9b1<=vx8bfb1[96];tuf4d8d<=vx8bfb1[97];yma6c6b<=vx8bfb1[98];gd36359<=vx8bfb1[99];anb1acd<=vx8bfb1[100];co8d66d<=vx8bfb1[101];xj6b368<=vx8bfb1[102];ww59b46<=vx8bfb1[103];jpcda30<=vx8bfb1[104];cm6d187<=vx8bfb1[105];os68c39<=vx8bfb1[106];cm461c8<=vx8bfb1[107];vk30e41<=vx8bfb1[108];ou8720b<=vx8bfb1[109];oh39059<=vx8bfb1[110];nrc82cc<=vx8bfb1[111];gb41666<=vx8bfb1[112];xyb334<=vx8bfb1[113];kq599a3<=vx8bfb1[114];qtccd18<=vx8bfb1[115];ho668c5<=vx8bfb1[116];ym3462b<=vx8bfb1[117];iea3158<=vx8bfb1[118];ep18ac0<=vx8bfb1[119];tuc5604<=vx8bfb1[120];wy2b022<=vx8bfb1[121];ps58110<=vx8bfb1[122];hoc0883<=vx8bfb1[123];je441b<=vx8bfb1[124];xl220da<=vx8bfb1[125];sw106d6<=vx8bfb1[126];ba836b1<=vx8bfb1[127];ng1b58b<=vx8bfb1[128];nedac5a<=vx8bfb1[129];shd62d3<=vx8bfb1[130];yzb169c<=vx8bfb1[131];lf8b4e4<=vx8bfb1[132];vv5a727<=vx8bfb1[133];ald393e<=vx8bfb1[134];ng9c9f5<=vx8bfb1[135];nee4faa<=vx8bfb1[136];tj27d52<=vx8bfb1[137];qi3ea97<=vx8bfb1[138];ayf54b8<=vx8bfb1[139];bnaa5c0<=vx8bfb1[140];dm52e06<=vx8bfb1[141];ks97033<=vx8bfb1[142];lsb8198<=vx8bfb1[143];nec0cc2<=vx8bfb1[144];hd6613<=vx8bfb1[145];kf3309f<=vx8bfb1[146];ec984fd<=vx8bfb1[147];zxc27e9<=vx8bfb1[148];zz13f4f<=vx8bfb1[149];gd9fa7f<=vx8bfb1[150];offd3fd<=vx8bfb1[151];nre9fec<=vx8bfb1[152];xj4ff66<=vx8bfb1[153];ip7fb36<=vx8bfb1[154];qtfd9b4<=vx8bfb1[155];hbecda5<=vx8bfb1[156];zk66d2e<=vx8bfb1[157];oh36973<=vx8bfb1[158];irb4b9c<=vx8bfb1[159];rva5ce5<=vx8bfb1[160];wy2e72e<=vx8bfb1[161];ps73970<=vx8bfb1[162];pu9cb82<=vx8bfb1[163];cme5c12<=vx8bfb1[164];gq2e090<=vx8bfb1[165];sh70480<=vx8bfb1[166];mg82404<=vx8bfb1[167];yz12021<=vx8bfb1[168];ux9010c<=vx8bfb1[169];sj80865<=vx8bfb1[170];tw432d<=vx8bfb1[171];wy2196a<=vx8bfb1[172];ntcb50<=vx8bfb1[173];kd65a87<=vx8bfb1[174];vx2d43c<=vx8bfb1[175];mr6a1e7<=vx8bfb1[176];pf50f3c<=vx8bfb1[177];ym879e6<=vx8bfb1[178];mt3cf30<=vx8bfb1[179];ale7985<=vx8bfb1[180];wl3cc2d<=vx8bfb1[181];dze616d<=vx8bfb1[182];pu30b6e<=vx8bfb1[183];ux85b73<=vx8bfb1[184];lf2db9d<=vx8bfb1[185];ea6dcee<=vx8bfb1[186];dz6e770<=vx8bfb1[187];tu73b86<=vx8bfb1[188];uk9dc32<=vx8bfb1[189];rgee190<=vx8bfb1[190];cz70c82<=vx8bfb1[191];tw86415<=vx8bfb1[192];db320ab<=vx8bfb1[193];cb9055f<=vx8bfb1[194];co82afd<=vx8bfb1[195];qi157e8<=vx8bfb1[196];mtabf41<=vx8bfb1[197];th5fa0d<=vx8bfb1[198];offd06f<=vx8bfb1[199];mre837c<=vx8bfb1[200];sh41be5<=vx8bfb1[201];uxdf2d<=vx8bfb1[202];of6f96d<=vx8bfb1[203];ho7cb6d<=vx8bfb1[204];kqe5b6b<=vx8bfb1[205];vx2db58<=vx8bfb1[206];go6dac6<=vx8bfb1[207];qg6d630<=vx8bfb1[208];zx6b181<=vx8bfb1[209];ne58c0e<=vx8bfb1[210];ofc6072<=vx8bfb1[211];ng30395<=vx8bfb1[212];bn81caa<=vx8bfb1[213];nge557<=vx8bfb1[214];ic72abb<=vx8bfb1[215];mt955d8<=vx8bfb1[216];hdaaec5<=vx8bfb1[217];dm5762f<=vx8bfb1[218];irbb17a<=vx8bfb1[219];vvd8bd5<=vx8bfb1[220];zkc5eae<=vx8bfb1[221];xy2f573<=vx8bfb1[222];yx7ab9a<=vx8bfb1[223];ned5cd4<=vx8bfb1[224];kfae6a2<=vx8bfb1[225];xw73514<=vx8bfb1[226];gd9a8a3<=vx8bfb1[227];med451d<=vx8bfb1[228];fca28e9<=vx8bfb1[229];je1474b<=vx8bfb1[230];gqa3a5b<=vx8bfb1[231];sj1d2d9<=vx8bfb1[232];hbe96cd<=vx8bfb1[233];en4b66f<=vx8bfb1[234];qt5b37d<=vx8bfb1[235];mrd9bec<=vx8bfb1[236];hbcdf64<=vx8bfb1[237];of6fb27<=vx8bfb1[238];go7d93d<=vx8bfb1[239];fnec9e9<=vx8bfb1[240];ld64f4e<=vx8bfb1[241];db27a76<=vx8bfb1[\r
+242];vx3d3b7<=vx8bfb1[243];rte9dbe<=vx8bfb1[244];cz4edf6<=vx8bfb1[245];vi76fb4<=vx8bfb1[246];lsb7da2<=vx8bfb1[247];kfbed12<=vx8bfb1[248];hbf6894<=vx8bfb1[249];epb44a6<=vx8bfb1[250];fca2534<=vx8bfb1[251];gd129a2<=vx8bfb1[252];lf94d15<=vx8bfb1[253];swa68ae<=vx8bfb1[254];ie34571<=vx8bfb1[255];lsa2b88<=vx8bfb1[256];ec15c43<=vx8bfb1[257];qvae218<=vx8bfb1[258];vv710c4<=vx8bfb1[259];ks88626<=vx8bfb1[260];go43130<=vx8bfb1[261];cb18981<=vx8bfb1[262];cmc4c0c<=vx8bfb1[263];wl26061<=vx8bfb1[264];ls3030c<=vx8bfb1[265];lf81862<=vx8bfb1[266];rvc317<=vx8bfb1[267];nr618be<=vx8bfb1[268];tjc5f6<=vx8bfb1[269];ay62fb6<=vx8bfb1[270];wl17db1<=vx8bfb1[271];irbed8d<=vx8bfb1[272];rtf6c6c<=vx8bfb1[273];ecb6366<=vx8bfb1[274];kfb1b31<=vx8bfb1[275];ec8d98d<=vx8bfb1[276];ps6cc69<=vx8bfb1[277];lq6634a<=vx8bfb1[278];aa31a52<=vx8bfb1[279];co8d291<=vx8bfb1[280];vi69488<=vx8bfb1[281];nr4a443<=vx8bfb1[282];jc5221f<=vx8bfb1[283];fp910fa<=vx8bfb1[284];aa887d7<=vx8bfb1[285];ea43eb8<=vx8bfb1[286];gq1f5c0<=vx8bfb1[287];icfae00<=vx8bfb1[288];rtd7000<=vx8bfb1[289];pub8006<=vx8bfb1[290];tuc0032<=vx8bfb1[291];wy192<=vx8bfb1[292];ukc90<=vx8bfb1[293];lf6481<=vx8bfb1[294];rv3240f<=vx8bfb1[295];ie9207f<=vx8bfb1[296];wl903f8<=vx8bfb1[297];jr81fc5<=vx8bfb1[298];ymfe2f<=vx8bfb1[299];qt7f178<=vx8bfb1[300];gbf8bc5<=vx8bfb1[301];dmc5e2d<=vx8bfb1[302];do2f16b<=vx8bfb1[303];su78b5a<=vx8bfb1[304];vic5ad1<=vx8bfb1[305];tj2d68b<=vx8bfb1[306];xj6b45f<=vx8bfb1[307];zx5a2fe<=vx8bfb1[308];end\r
+always@* begin ead17f6[2047]<=of4e369;ead17f6[2046]<=th71b4d;ead17f6[2044]<=ym8da6f;ead17f6[2043]<=nrd78bb;ead17f6[2040]<=su6d379;ead17f6[2038]<=mgbc5df;ead17f6[2032]<=ne69bc9;ead17f6[2029]<=wje2ef8;ead17f6[2017]<=vi4de4a;ead17f6[2013]<=db81b86;ead17f6[2010]<=qv177c5;ead17f6[2003]<=ld4af0d;ead17f6[1990]<=ec886a0;ead17f6[1987]<=wj6f253[0];ead17f6[1982]<=zm93729;ead17f6[1980]<=ldf3bb1;ead17f6[1979]<=epdc37;ead17f6[1973]<=irbbe2c;ead17f6[1963]<=qtc9fa5;ead17f6[1958]<=ps5786e;ead17f6[1957]<=go566e7;ead17f6[1953]<=fa76a41;ead17f6[1942]<=hd8e0dd;ead17f6[1932]<=kq43500;ead17f6[1929]<=pu9cb9c;ead17f6[1926]<=ps7929c[0];ead17f6[1923]<=lqda3b1;ead17f6[1921]<=ofe7900;ead17f6[1917]<=db9b94a;ead17f6[1914]<=ribdd56;ead17f6[1913]<=ie9dd8e;ead17f6[1911]<=rt6e1bd;ead17f6[1903]<=zz9edd8;ead17f6[1898]<=psdf164;ead17f6[1879]<=jp4fd2d;ead17f6[1876]<=uxab07c;ead17f6[1872]<=cb8acc2;ead17f6[1868]<=cobc373;ead17f6[1866]<=ecb3738;ead17f6[1863]<=jpc248b;ead17f6[1858]<=phb520a;ead17f6[1837]<=of706ef;ead17f6[1816]<=gq1a801;ead17f6[1810]<=cme5ce2;ead17f6[1805]<=eaffb08;ead17f6[1802]<=cb7df0;ead17f6[1799]<=wwd1d8a;ead17f6[1795]<=ep3c805;ead17f6[1786]<=qtdca57;ead17f6[1783]<=thd8f9d;ead17f6[1780]<=neeeab3;ead17f6[1778]<=zkeec70;ead17f6[1775]<=cz70dee;ead17f6[1770]<=ba1bc56;ead17f6[1758]<=ldf6ec7;ead17f6[1748]<=enf8b22;ead17f6[1710]<=bl7e96e;ead17f6[1704]<=zk583e4;ead17f6[1701]<=sjb465d;ead17f6[1699]<=th6455c;ead17f6[1696]<=ui56614;ead17f6[1689]<=tue1b98;ead17f6[1685]<=lf9b9c1;ead17f6[1679]<=vk2ff39;ead17f6[1678]<=an1245f;ead17f6[1668]<=oua9056;ead17f6[1627]<=hq8377c;ead17f6[1624]<=cm68afe;ead17f6[1605]<=ou15cce;ead17f6[1589]<=ofe8ed6;ead17f6[1584]<=med4009;ead17f6[1573]<=gq2e710;ead17f6[1572]<=ng863d9;ead17f6[1567]<=kq5ca56;ead17f6[1562]<=kdfd840;ead17f6[1557]<=go78dad;ead17f6[1556]<=qi3ef84;ead17f6[1551]<=fp8ec50;ead17f6[1548]<=ea49e16;ead17f6[1543]<=nee402d;ead17f6[1524]<=kqe52bc;ead17f6[1521]<=sj2621a;ead17f6[1519]<=ldc7cee;ead17f6[1513]<=al7559b;ead17f6[1512]<=sue5da9;ead17f6[1509]<=rg76383;ead17f6[1504]<=hd2768e;ead17f6[1502]<=tw86f75;ead17f6[1499]<=fa767b7;ead17f6[1493]<=th6eac1;ead17f6[1492]<=ykde2b3;ead17f6[1469]<=jeb763e;ead17f6[1466]<=rg7c6f1;ead17f6[1448]<=nec5915;ead17f6[1421]<=by47a3b;ead17f6[1417]<=zkfe18f;ead17f6[1415]<=psf1729;ead17f6[1404]<=rg7c988;ead17f6[1402]<=gd17976;ead17f6[1400]<=ww4c9da;ead17f6[1398]<=jr2dd9e;ead17f6[1377]<=wje7c5c;ead17f6[1374]<=xl385e5;ead17f6[1373]<=lqf4b76;ead17f6[1361]<=icc1f23;ead17f6[1359]<=tw9c32f;ead17f6[1355]<=meea83a;ead17f6[1354]<=mga32ec;ead17f6[1350]<=tj22ae7;ead17f6[1349]<=dm7c8c8;ead17f6[1344]<=mgb30a0;ead17f6[1343]<=tjcbda;ead17f6[1341]<=ba4a72;ead17f6[1330]<=ohdcc2;ead17f6[1326]<=dba0e8d;ead17f6[1323]<=czdce0f;ead17f6[1322]<=aycbb07;ead17f6[1310]<=mr7f9cb;ead17f6[1308]<=ie922fc;ead17f6[1305]<=mtab9f9;ead17f6[1301]<=kf2321b;ead17f6[1289]<=ho482b1;ead17f6[1286]<=aa1a374;ead17f6[1280]<=xjc2809;ead17f6[1279]<=ng2f6bc;ead17f6[1271]<=wl29c9b;ead17f6[1224]<=rg730ae;ead17f6[1210]<=do3a375;ead17f6[1207]<=je1bbe3;ead17f6[1201]<=nr457f0;ead17f6[1199]<=zz383e4;ead17f6[1195]<=dzec1c2;ead17f6[1193]<=gd804e1;ead17f6[1163]<=cmcb37d;ead17f6[1162]<=sjae670;ead17f6[1155]<=dba0125;ead17f6[1144]<=kde72e7;ead17f6[1136]<=rv8bf07;ead17f6[1130]<=dm476b4;ead17f6[1125]<=mre7e68;ead17f6[1120]<=hda0049;ead17f6[1112]<=cz6fa47;ead17f6[1110]<=fnc86e7;ead17f6[1104]<=osce11a;ead17f6[1098]<=rg73880;ead17f6[1096]<=ec31ecb;ead17f6[1086]<=ose52b0;ead17f6[1076]<=ldec205;ead17f6[1067]<=enc6d69;ead17f6[1065]<=czf7c20;ead17f6[1060]<=coac54;ead17f6[1054]<=tu76286;ead17f6[1053]<=aa24bcb;ead17f6[1051]<=aa8dd00;ead17f6[1048]<=rt4f0b1;ead17f6[1039]<=vk2016b;ead17f6[1026]<=nta0273;ead17f6[1023]<=ui49c6d[0];ead17f6[1021]<=jcdaf17;ead17f6[1006]<=xlb0370;ead17f6[1001]<=yz295e1;ead17f6[995]<=ec310d4;ead17f6[991]<=go726e5;ead17f6[990]<=ks3e776;ead17f6[981]<=qtd93f4;ead17f6[978]<=bnaacdc;ead17f6[976]<=ec2ed48;ead17f6[971]<=kfb1c1b;ead17f6[964]<=cb33973;ead17f6[961]<=uk3b476;ead17f6[960]<=ay5cf20;ead17f6[957]<=zz37baa;ead17f6[951]<=qib3dbb;ead17f6[938]<=wj7560f;ead17f6[936]<=xwf1598;ead17f6[931]<=ps58491;ead17f6[901]<=yke0fbe;ead17f6[891]<=yzbb1f3;ead17f6[885]<=lde378a;ead17f6[850]<=uvd68cb;ead17f6[849]<=gd2c8ab;ead17f6[839]<=co5fe7;ead17f6[812]<=dzcd15f;ead17f6[802]<=fnc2b99;ead17f6[794]<=lf3d1da;ead17f6[786]<=ykf0c7b;ead17f6[783]<=rv8b94a;ead17f6[778]<=qv8f1b5;ead17f6[774]<=nt93c2;ead17f6[760]<=nee4c43;ead17f6[756]<=iebcbb5;ead17f6[752]<=fn64ed1;ead17f6[749]<=rt6ecf6;ead17f6[746]<=ou8dd58;ead17f6[733]<=meef8de;ead17f6[710]<=zk48f47;ead17f6[708]<=bl5fc31;ead17f6[707]<=ou3e2e5;ead17f6[702]<=ief931;ead17f6[701]<=hbc2f2e;ead17f6[700]<=xw6993b;ead17f6[699]<=pha5bb3;ead17f6[688]<=ofdcf8b;ead17f6[687]<=cb70bc;ead17f6[679]<=rv13865;ead17f6[677]<=lsbd507;ead17f6[674]<=qif919;ead17f6[671]<=nee197b;ead17f6[670]<=ls2094e;ead17f6[663]<=sh541d1;ead17f6[661]<=lf19760;ead17f6[652]<=qi1573f;ead17f6[650]<=fae4643;ead17f6[643]<=yz2346e;ead17f6[640]<=uk98501;ead17f6[639]<=gb65ed7;ead17f6[635]<=ng25393;ead17f6[612]<=th6e615;ead17f6[605]<=qv746e;ead17f6[599]<=ene707c;ead17f6[597]<=fa5d838;ead17f6[596]<=mg1009c;ead17f6[581]<=ipd966f;ead17f6[577]<=sh54024;ead17f6[572]<=xjfce5c;ead17f6[568]<=xl917e0;ead17f6[562]<=qg5cfcd;ead17f6[556]<=zxcdf48;ead17f6[555]<=vx190dc;ead17f6[552]<=xy99c23;ead17f6[530]<=kd4158a;ead17f6[526]<=tw4979;ead17f6[525]<=med1ba0;ead17f6[513]<=do1404e;ead17f6[510]<=xj7b5e2;ead17f6[503]<=ic5606e;ead17f6[495]<=qt4e4dc;ead17f6[490]<=kd5b27e;ead17f6[482]<=tw8672e;ead17f6[480]<=gocb9e4;ead17f6[465]<=eacb092;ead17f6[450]<=thfc1f7;ead17f6[438]<=ec3f7;ead17f6[425]<=xwdad19;ead17f6[419]<=dz40bfc;ead17f6[406]<=jpf9a2b;ead17f6[401]<=ie98573;ead17f6[389]<=irb1e36;ead17f6[387]<=ls1278;ead17f6[373]<=ead1bab;ead17f6[366]<=nrddf1b;ead17f6[355]<=nre91e8;ead17f6[354]<=aa2bf86;ead17f6[351]<=uic1f26;ead17f6[350]<=doad327;ead17f6[344]<=tw1b9f1;ead17f6[343]<=yx60e17;ead17f6[339]<=yz270c;ead17f6[338]<=dzd7aa0;ead17f6[335]<=lf84129;ead17f6[321]<=tj8468d;ead17f6[298]<=gbe2013;ead17f6[290]<=nr7b2cd;ead17f6[288]<=ir8a804;ead17f6[278]<=yk59be9;ead17f6[276]<=jc73384;ead17f6[263]<=sw92f;ead17f6[251]<=hb4ac0d;ead17f6[245]<=fn6b64f;ead17f6[241]<=ld50ce5;ead17f6[240]<=ux3973c;ead17f6[232]<=xw79612;ead17f6[225]<=nr5f83e;ead17f6[219]<=lfa007e;ead17f6[212]<=co3b5a3;ead17f6[209]<=gd817f;ead17f6[203]<=ng3f345;ead17f6[194]<=db163c6;ead17f6[193]<=ym24f;ead17f6[177]<=os7d23d;ead17f6[175]<=ntb5a64;ead17f6[172]<=su4373e;ead17f6[169]<=qgfaf54;ead17f6[167]<=eaf0825;ead17f6[160]<=sh708d1;ead17f6[149]<=fc9c402;ead17f6[145]<=kf8f659;ead17f6[144]<=ohb1500;ead17f6[125]<=ep29581;ead17f6[122]<=hd2d6c9;ead17f6[120]<=an8a19c;ead17f6[116]<=xy2f2c2;ead17f6[109]<=ld7400f;ead17f6[104]<=ld6102f;ead17f6[97]<=nrc2c78;ead17f6[87]<=ir36b4c;ead17f6[84]<=ux9f5ea;ead17f6[83]<=qvbe104;ead17f6[72]<=ui562a0;ead17f6[\r
+61]<=aa5ad9;ead17f6[60]<=anb1433;ead17f6[58]<=ri25e58;ead17f6[54]<=ld6e801;ead17f6[48]<=os7858f;ead17f6[42]<=jc73ebd;ead17f6[30]<=gqb5b;ead17f6[21]<=al4e7d7;ead17f6[10]<=ph9cfa;ead17f6[5]<=vk139f;end         assign jebdc77 = ead17f6,vx8bfb1 = fn71dda; initial begin kfbe35f = $fopen(".fred"); $fdisplay( kfbe35f, "%3h\n%3h", (fnf63ba >> 4) & fpbaf71, (fnf63ba >> (tj8eebd+4)) & fpbaf71 ); $fclose(kfbe35f); $readmemh(".fred", ay776be); end always @ (jebdc77) begin nedaf8d = ay776be[1]; for (jcf1afd=0; jcf1afd<th5fd8e; jcf1afd=jcf1afd+1) begin fn71dda[jcf1afd] = jebdc77[nedaf8d]; thd7c6b = ^(nedaf8d & ay776be[0]); nedaf8d = {nedaf8d, thd7c6b}; end end\r
+endmodule\r
+`timescale 1 ns / 100 ps\r
+module xy300fa (ui49c6d, of4e369, th71b4d, ym8da6f, su6d379, ne69bc9,\r
+    vi4de4a, wj6f253, ps7929c, uvc94e2, ld4a714, su538a7, ba9c539,\r
+    ale29cb);\r
+input wire [17:0] ui49c6d;\r
+input wire of4e369;\r
+input wire th71b4d;\r
+input wire ym8da6f;\r
+input wire su6d379;\r
+input wire ne69bc9;\r
+input wire vi4de4a;\r
+input wire [9:0] wj6f253;\r
+input wire [9:0] ps7929c;\r
+output wire [17:0] uvc94e2;\r
+output wire ld4a714;\r
+output wire su538a7;\r
+output wire ba9c539;\r
+output wire ale29cb;\r
+wire eaffb08;\r
+wire kdfd840;\r
+wire ldec205;\r
+wire ld6102f;\r
+wire gd817f;\r
+wire dz40bfc;\r
+wire co5fe7;\r
+wire vk2ff39;\r
+wire mr7f9cb;\r
+wire xjfce5c;\r
+wire kde72e7;\r
+wire ux3973c;\r
+wire gocb9e4;\r
+wire ay5cf20;\r
+wire ofe7900;\r
+wire ep3c805;\r
+wire nee402d;\r
+wire vk2016b;\r
+wire gqb5b;\r
+wire aa5ad9;\r
+wire hd2d6c9;\r
+wire fn6b64f;\r
+wire kd5b27e;\r
+wire qtd93f4;\r
+wire qtc9fa5;\r
+wire jp4fd2d;\r
+wire bl7e96e;\r
+wire lqf4b76;\r
+wire pha5bb3;\r
+wire jr2dd9e;\r
+wire rt6ecf6;\r
+wire fa767b7;\r
+wire qib3dbb;\r
+wire zz9edd8;\r
+wire ldf6ec7;\r
+wire jeb763e;\r
+wire yzbb1f3;\r
+wire thd8f9d;\r
+wire ldc7cee;\r
+wire ks3e776;\r
+wire ldf3bb1;\r
+wire ie9dd8e;\r
+wire zkeec70;\r
+wire rg76383;\r
+wire kfb1c1b;\r
+wire hd8e0dd;\r
+wire of706ef;\r
+wire hq8377c;\r
+wire je1bbe3;\r
+wire nrddf1b;\r
+wire meef8de;\r
+wire rg7c6f1;\r
+wire lde378a;\r
+wire ba1bc56;\r
+wire ykde2b3;\r
+wire xwf1598;\r
+wire cb8acc2;\r
+wire ui56614;\r
+wire mgb30a0;\r
+wire uk98501;\r
+wire xjc2809;\r
+wire do1404e;\r
+wire nta0273;\r
+wire vk139f;\r
+wire ph9cfa;\r
+wire al4e7d7;\r
+wire jc73ebd;\r
+wire ux9f5ea;\r
+wire qgfaf54;\r
+wire dzd7aa0;\r
+wire lsbd507;\r
+wire meea83a;\r
+wire sh541d1;\r
+wire dba0e8d;\r
+wire qv746e;\r
+wire do3a375;\r
+wire ead1bab;\r
+wire ou8dd58;\r
+wire th6eac1;\r
+wire wj7560f;\r
+wire uxab07c;\r
+wire zk583e4;\r
+wire icc1f23;\r
+wire qif919;\r
+wire dm7c8c8;\r
+wire fae4643;\r
+wire kf2321b;\r
+wire vx190dc;\r
+wire fnc86e7;\r
+wire su4373e;\r
+wire tw1b9f1;\r
+wire ofdcf8b;\r
+wire wje7c5c;\r
+wire ou3e2e5;\r
+wire psf1729;\r
+wire rv8b94a;\r
+wire kq5ca56;\r
+wire ose52b0;\r
+wire ep29581;\r
+wire hb4ac0d;\r
+wire ic5606e;\r
+wire xlb0370;\r
+wire db81b86;\r
+wire epdc37;\r
+wire rt6e1bd;\r
+wire cz70dee;\r
+wire tw86f75;\r
+wire zz37baa;\r
+wire ribdd56;\r
+wire neeeab3;\r
+wire al7559b;\r
+wire bnaacdc;\r
+wire go566e7;\r
+wire ecb3738;\r
+wire lf9b9c1;\r
+wire czdce0f;\r
+wire ene707c;\r
+wire zz383e4;\r
+wire uic1f26;\r
+wire ief931;\r
+wire rg7c988;\r
+wire nee4c43;\r
+wire sj2621a;\r
+wire ec310d4;\r
+wire ec886a0;\r
+wire kq43500;\r
+wire gq1a801;\r
+wire med4009;\r
+wire hda0049;\r
+wire ym24f;\r
+wire ls1278;\r
+wire nt93c2;\r
+wire ea49e16;\r
+wire rt4f0b1;\r
+wire os7858f;\r
+wire nrc2c78;\r
+wire irb1e36;\r
+wire db163c6;\r
+wire qv8f1b5;\r
+wire go78dad;\r
+wire enc6d69;\r
+wire ir36b4c;\r
+wire ntb5a64;\r
+wire doad327;\r
+wire xw6993b;\r
+wire ww4c9da;\r
+wire fn64ed1;\r
+wire hd2768e;\r
+wire uk3b476;\r
+wire lqda3b1;\r
+wire wwd1d8a;\r
+wire fp8ec50;\r
+wire tu76286;\r
+wire anb1433;\r
+wire an8a19c;\r
+wire tw8672e;\r
+wire ld50ce5;\r
+wire cb33973;\r
+wire cme5ce2;\r
+wire gq2e710;\r
+wire rg73880;\r
+wire fc9c402;\r
+wire gbe2013;\r
+wire mg1009c;\r
+wire gd804e1;\r
+wire yz270c;\r
+wire rv13865;\r
+wire tw9c32f;\r
+wire nee197b;\r
+wire tjcbda;\r
+wire gb65ed7;\r
+wire ng2f6bc;\r
+wire jcdaf17;\r
+wire xj7b5e2;\r
+wire nrd78bb;\r
+wire mgbc5df;\r
+wire wje2ef8;\r
+wire lfa007e;\r
+wire irbbe2c;\r
+wire psdf164;\r
+wire enf8b22;\r
+wire nec5915;\r
+wire gd2c8ab;\r
+wire th6455c;\r
+wire tj22ae7;\r
+wire qi1573f;\r
+wire mtab9f9;\r
+wire qg5cfcd;\r
+wire mre7e68;\r
+wire ng3f345;\r
+wire jpf9a2b;\r
+wire dzcd15f;\r
+wire nr457f0;\r
+wire cm68afe;\r
+wire aa2bf86;\r
+wire bl5fc31;\r
+wire zkfe18f;\r
+wire ykf0c7b;\r
+wire ng863d9;\r
+wire ec31ecb;\r
+wire kf8f659;\r
+wire nr7b2cd;\r
+wire ipd966f;\r
+wire cmcb37d;\r
+wire yk59be9;\r
+wire zxcdf48;\r
+wire cz6fa47;\r
+wire os7d23d;\r
+wire nre91e8;\r
+wire zk48f47;\r
+wire by47a3b;\r
+wire lf3d1da;\r
+wire ofe8ed6;\r
+wire dm476b4;\r
+wire co3b5a3;\r
+wire xwdad19;\r
+wire uvd68cb;\r
+wire sjb465d;\r
+wire mga32ec;\r
+wire lf19760;\r
+wire aycbb07;\r
+wire fa5d838;\r
+wire dzec1c2;\r
+wire yx60e17;\r
+wire cb70bc;\r
+wire xl385e5;\r
+wire hbc2f2e;\r
+wire gd17976;\r
+wire iebcbb5;\r
+wire sue5da9;\r
+wire ec2ed48;\r
+wire fa76a41;\r
+wire phb520a;\r
+wire oua9056;\r
+wire ho482b1;\r
+wire kd4158a;\r
+wire coac54;\r
+wire ui562a0;\r
+wire ohb1500;\r
+wire ir8a804;\r
+wire sh54024;\r
+wire dba0125;\r
+wire sw92f;\r
+wire tw4979;\r
+wire aa24bcb;\r
+wire ri25e58;\r
+wire xy2f2c2;\r
+wire xw79612;\r
+wire eacb092;\r
+wire ps58491;\r
+wire jpc248b;\r
+wire an1245f;\r
+wire ie922fc;\r
+wire xl917e0;\r
+wire rv8bf07;\r
+wire nr5f83e;\r
+wire thfc1f7;\r
+wire yke0fbe;\r
+wire cb7df0;\r
+wire qi3ef84;\r
+wire czf7c20;\r
+wire qvbe104;\r
+wire eaf0825;\r
+wire lf84129;\r
+wire ls2094e;\r
+wire ba4a72;\r
+wire ng25393;\r
+wire wl29c9b;\r
+wire qt4e4dc;\r
+wire go726e5;\r
+wire zm93729;\r
+wire db9b94a;\r
+wire qtdca57;\r
+wire kqe52bc;\r
+wire yz295e1;\r
+wire ld4af0d;\r
+wire ps5786e;\r
+wire cobc373;\r
+wire tue1b98;\r
+wire ohdcc2;\r
+wire th6e615;\r
+wire rg730ae;\r
+wire ie98573;\r
+wire fnc2b99;\r
+wire ou15cce;\r
+wire sjae670;\r
+wire jc73384;\r
+wire xy99c23;\r
+wire osce11a;\r
+wire sh708d1;\r
+wire tj8468d;\r
+wire yz2346e;\r
+wire aa1a374;\r
+wire med1ba0;\r
+wire aa8dd00;\r
+wire ld7400f;\r
+wire ec3f7;\r
+wire ld6e801;\r
+reg [17 : 0] hq1fb8;\r
+reg iefdc3;\r
+reg th7ee18;\r
+reg alf70c6;\r
+reg dob8635;\r
+reg czc31aa;\r
+reg wl18d55;\r
+reg [9 : 0] ipc6aac;\r
+reg [9 : 0] ng35564;\r
+reg bnaab22;\r
+reg jp55917;\r
+reg coac8be;\r
+reg nr645f0;\r
+reg xl22f87;\r
+reg yz17c3f;\r
+reg yzbe1fd;\r
+reg qgf0fed;\r
+reg aa87f69;\r
+reg ba3fb48;\r
+reg mrfda42;\r
+reg aled215;\r
+reg zk690ad;\r
+reg rg4856b;\r
+reg lq42b5a;\r
+reg ks15ad2;\r
+reg lsad690;\r
+reg ld6b483;\r
+reg hb5a41e;\r
+reg thd20f6;\r
+reg gd907b6;\r
+reg je83db5;\r
+reg vk1edaa;\r
+reg fnf6d53;\r
+reg mgb6a9e;\r
+reg tjb54f0;\r
+reg xlaa786;\r
+reg ww53c36;\r
+reg jr9e1b1;\r
+reg gof0d8e;\r
+reg zm86c71;\r
+reg ux3638a;\r
+reg irb1c55;\r
+reg rv8e2ad;\r
+reg rt7156f;\r
+reg gd8ab7e;\r
+reg dz55bf4;\r
+reg hqadfa6;\r
+reg al6fd32;\r
+reg bl7e995;\r
+reg lqf4cae;\r
+reg mga6573;\r
+reg lf32b98;\r
+reg kf95cc6;\r
+reg mtae634;\r
+reg ne731a4;\r
+reg co98d23;\r
+reg enc6918;\r
+reg gq348c4;\r
+reg ana4621;\r
+reg wl2310d;\r
+reg mt1886c;\r
+reg eac4364;\r
+reg gq21b20;\r
+reg ohd900;\r
+reg rg6c805;\r
+reg dz6402a;\r
+reg tw20157;\r
+reg qiabb;\r
+reg co55d9;\r
+reg ri2aec8;\r
+reg fa57643;\r
+reg yzbb21a;\r
+reg shd90d5;\r
+reg hbc86ad;\r
+reg ic4356e;\r
+reg qi1ab71;\r
+reg psd5b89;\r
+reg zmadc4a;\r
+reg pf6e252;\r
+reg nr71296;\r
+reg zm894b6;\r
+reg zx4a5b2;\r
+reg by52d97;\r
+reg vk96cbb;\r
+reg ymb65db;\r
+reg ngb2ed9;\r
+reg ym976ca;\r
+reg uxbb650;\r
+reg kqdb285;\r
+reg qtd9428;\r
+reg psca145;\r
+reg bl50a2b;\r
+reg sj8515e;\r
+reg rv28af4;\r
+reg dz457a6;\r
+reg ym2bd36;\r
+reg kd5e9b1;\r
+reg tuf4d8d;\r
+reg yma6c6b;\r
+reg gd36359;\r
+reg anb1acd;\r
+reg co8d66d;\r
+reg xj6b368;\r
+reg ww59b46;\r
+reg jpcda30;\r
+reg cm6d187;\r
+reg os68c39;\r
+reg cm461c8;\r
+reg vk30e41;\r
+reg ou8720b;\r
+reg oh39059;\r
+reg nrc82cc;\r
+reg gb41666;\r
+reg xyb334;\r
+reg kq599a3;\r
+reg qtccd18;\r
+reg ho668c5;\r
+reg ym3462b;\r
+reg iea3158;\r
+reg ep18ac0;\r
+reg tuc5604;\r
+reg wy2b022;\r
+reg ps58110;\r
+reg hoc0883;\r
+reg je441b;\r
+reg xl220da;\r
+reg sw106d6;\r
+reg ba836b1;\r
+reg ng1b58b;\r
+reg nedac5a;\r
+reg shd62d3;\r
+reg yzb169c;\r
+reg lf8b4e4;\r
+reg vv5a727;\r
+reg ald393e;\r
+reg ng9c9f5;\r
+reg nee4faa;\r
+reg tj27d52;\r
+reg qi3ea97;\r
+reg ayf54b8;\r
+reg bnaa5c0;\r
+reg dm52e06;\r
+reg ks97033;\r
+reg lsb8198;\r
+reg nec0cc2;\r
+reg kf3309f;\r
+reg hd6613;\r
+reg ec984fd;\r
+reg zxc27e9;\r
+reg zz13f4f;\r
+reg gd9fa7f;\r
+reg offd3fd;\r
+reg nre9fec;\r
+reg xj4ff66;\r
+reg ip7fb36;\r
+reg qtfd9b4;\r
+reg hbecda5;\r
+reg zk66d2e;\r
+reg oh36973;\r
+reg irb4b9c;\r
+reg rva5ce5;\r
+reg wy2e72e;\r
+reg ps73970;\r
+reg pu9cb82;\r
+reg gq2e090;\r
+reg cme5c12;\r
+reg sh70480;\r
+reg yz12021;\r
+reg ux9010c;\r
+reg sj80865;\r
+reg tw432d;\r
+reg wy2196a;\r
+reg ntcb50;\r
+reg kd65a87;\r
+reg vx2d43c;\r
+reg mr6a1e7;\r
+reg pf50f3c;\r
+reg ym879e6;\r
+reg mt3cf30;\r
+reg ale7985;\r
+reg wl3cc2d;\r
+reg pu30b6e;\r
+reg dze616d;\r
+reg ux85b73;\r
+reg lf2db9d;\r
+reg ea6dcee;\r
+reg xj6b45f;\r
+reg tu73b86;\r
+reg uk9dc32;\r
+reg rgee190;\r
+reg cz70c82;\r
+reg tw86415;\r
+reg db320ab;\r
+reg cb9055f;\r
+reg co82afd;\r
+reg qi157e8;\r
+reg mtabf41;\r
+reg th5fa0d;\r
+reg offd06f;\r
+reg mre837c;\r
+reg sh41be5;\r
+reg of6f96d;\r
+reg uxdf2d;\r
+reg ho7cb6d;\r
+reg kqe5b6b;\r
+reg vx2db58;\r
+reg go6dac6;\r
+reg qg6d630;\r
+reg zx6b181;\r
+reg ne58c0e;\r
+reg ofc6072;\r
+reg ng30395;\r
+reg bn81caa;\r
+reg nge557;\r
+reg ic72abb;\r
+reg mt955d8;\r
+reg hdaaec5;\r
+reg dm5762f;\r
+reg irbb17a;\r
+reg vvd8bd5;\r
+reg zkc5eae;\r
+reg xy2f573;\r
+reg yx7ab9a;\r
+reg ned5cd4;\r
+reg kfae6a2;\r
+reg xw73514;\r
+reg gd9a8a3;\r
+reg med451d;\r
+reg fca28e9;\r
+reg je1474b;\r
+reg gqa3a5b;\r
+reg sj1d2d9;\r
+reg hbe96cd;\r
+reg en4b66f;\r
+reg qt5b37d;\r
+reg mrd9bec;\r
+reg hbcdf64;\r
+reg of6fb27;\r
+reg go7d93d;\r
+reg fnec9e9;\r
+reg ld64f4e;\r
+reg db27a76;\r
+reg vx3d3b7;\r
+reg rte9dbe;\r
+reg cz4edf6;\r
+reg vi76fb4;\r
+reg lsb7da2;\r
+reg kfbed12;\r
+reg hbf6894;\r
+reg epb44a6;\r
+reg fca2534;\r
+reg gd129a2;\r
+reg lf94d15;\r
+reg swa68ae;\r
+reg ie34571;\r
+reg lsa2b88;\r
+reg ec15c43;\r
+reg qvae218;\r
+reg vv710c4;\r
+reg ks88626;\r
+reg go43130;\r
+reg cb18981;\r
+reg cmc4c0c;\r
+reg wl26061;\r
+reg ls3030c;\r
+reg lf81862;\r
+reg rvc317;\r
+reg nr618be;\r
+reg tjc5f6;\r
+reg ay62fb6;\r
+reg wl17db1;\r
+reg irbed8d;\r
+reg rtf6c6c;\r
+reg ecb6366;\r
+reg kfb1b31;\r
+reg ec8d98d;\r
+reg ps6cc69;\r
+reg lq6634a;\r
+reg aa31a52;\r
+reg co8d291;\r
+reg vi69488;\r
+reg nr4a443;\r
+reg jc5221f;\r
+reg fp910fa;\r
+reg aa887d7;\r
+reg ea43eb8;\r
+reg gq1f5c0;\r
+reg icfae00;\r
+reg rtd7000;\r
+reg pub8006;\r
+reg tuc0032;\r
+reg wy192;\r
+reg ukc90;\r
+reg lf6481;\r
+reg rv3240f;\r
+reg ie9207f;\r
+reg wl903f8;\r
+reg jr81fc5;\r
+reg ymfe2f;\r
+reg qt7f178;\r
+reg gbf8bc5;\r
+reg dmc5e2d;\r
+reg do2f16b;\r
+reg su78b5a;\r
+reg tj2d68b;\r
+reg zx5a2fe;\r
+reg vic5ad1;\r
+reg [2047:0] ead17f6;\r
+wire [306:0] vx8bfb1;\r
+localparam th5fd8e = 307,nefec77 = 32'hfdffc68b;\r
+localparam [31:0] fnf63ba = nefec77;\r
+localparam tj8eebd = nefec77 & 4'hf;\r
+localparam [11:0] fpbaf71 = 'h7ff;\r
+wire [(1 << tj8eebd) -1:0] jebdc77;\r
+reg [th5fd8e-1:0] fn71dda;\r
+reg [tj8eebd-1:0] ay776be [0:1];\r
+reg [tj8eebd-1:0] nedaf8d;\r
+reg thd7c6b;\r
+integer kfbe35f;\r
+integer jcf1afd;\r
+AND2 wy8d7eb (.A(ym8da6f), .B(eaffb08), .Z(cobc373));    INV vieb1fc (.A(zz383e4), .Z(eaffb08));    AND2 xy3f896 (.A(su6d379), .B(kdfd840), .Z(thfc1f7));    INV tw965a5 (.A(ene707c), .Z(kdfd840));    OR2 ohb4a93 (.A(ne69bc9), .B(vi4de4a), .Z(uic1f26));    XOR2 ng93bd2 (.A(sue5da9), .B(ec2ed48), .Z(vk2ff39));    XOR2 zxd2605 (.A(ec2ed48), .B(ho482b1), .Z(mr7f9cb));    XOR2 uk5c8b (.A(ho482b1), .B(kd4158a), .Z(xjfce5c));    XOR2 xl8b20f (.A(kd4158a), .B(ir8a804), .Z(kde72e7));    XOR2 swfe75 (.A(ir8a804), .B(sh54024), .Z(ux3973c));    XOR2 cz75178 (.A(sh54024), .B(aa24bcb), .Z(gocb9e4));    XOR2 ic788ba (.A(aa24bcb), .B(ri25e58), .Z(ay5cf20));    XOR2 bnba23c (.A(ri25e58), .B(ps58491), .Z(ofe7900));    XOR2 cb3ce4a (.A(ps58491), .B(jpc248b), .Z(ep3c805));    XOR2 ld4ab24 (.A(jpc248b), .B(irb1e36), .Z(nee402d));    XOR2 ec24d86 (.A(ec31ecb), .B(kf8f659), .Z(pha5bb3));    XOR2 ls8616f (.A(kf8f659), .B(yk59be9), .Z(jr2dd9e));    XOR2 gb6f6ee (.A(yk59be9), .B(zxcdf48), .Z(rt6ecf6));    XOR2 hoee9ce (.A(zxcdf48), .B(zk48f47), .Z(fa767b7));    XOR2 qgce7d5 (.A(zk48f47), .B(by47a3b), .Z(qib3dbb));    XOR2 rgd52a0 (.A(by47a3b), .B(co3b5a3), .Z(zz9edd8));    XOR2 jra0675 (.A(co3b5a3), .B(xwdad19), .Z(ldf6ec7));    XOR2 yx75ff0 (.A(xwdad19), .B(lf19760), .Z(jeb763e));    XOR2 osf0be3 (.A(lf19760), .B(aycbb07), .Z(yzbb1f3));    XOR2 nre335a (.A(aycbb07), .B(tw8672e), .Z(thd8f9d));    defparam dz5adb6.initval =  16'h6996 ;    ROM16X1A dz5adb6 (.AD3(fae4643), .AD2(vx190dc), .AD1(su4373e),        .AD0(ofdcf8b), .DO0(dm476b4));    defparam ale8012.initval =  16'h6996 ;    ROM16X1A ale8012 (.AD3(ou8dd58), .AD2(wj7560f), .AD1(zk583e4),        .AD0(qif919), .DO0(ld6102f));    defparam cz70b64.initval =  16'h6996 ;    ROM16X1A cz70b64 (.AD3(su4373e), .AD2(ofdcf8b), .AD1(ld6e801),        .AD0(ld6e801), .DO0(mga32ec));    defparam fn6e596.initval =  16'h6996 ;    ROM16X1A fn6e596 (.AD3(vx190dc), .AD2(su4373e), .AD1(ofdcf8b),        .AD0(ld6e801), .DO0(sjb465d));    defparam ou824ce.initval =  16'h6996 ;    ROM16X1A ou824ce (.AD3(qif919), .AD2(fae4643), .AD1(vx190dc),        .AD0(mga32ec), .DO0(ofe8ed6));    defparam os6247a.initval =  16'h6996 ;    ROM16X1A os6247a (.AD3(zk583e4), .AD2(qif919), .AD1(fae4643),        .AD0(sjb465d), .DO0(nre91e8));    defparam oh26b57.initval =  16'h6996 ;    ROM16X1A oh26b57 (.AD3(wj7560f), .AD2(zk583e4), .AD1(qif919),        .AD0(dm476b4), .DO0(os7d23d));    defparam kd5bad2.initval =  16'h6996 ;    ROM16X1A kd5bad2 (.AD3(dm476b4), .AD2(ld6102f),        .AD1(ld6e801), .AD0(ld6e801), .DO0(cmcb37d));    defparam kd7ade6.initval =  16'h6996 ;    ROM16X1A kd7ade6 (.AD3(dm476b4), .AD2(ld6102f),        .AD1(do3a375), .AD0(ld6e801), .DO0(ipd966f));    defparam ng2a3cf.initval =  16'h6996 ;    ROM16X1A ng2a3cf (.AD3(dm476b4), .AD2(ld6102f),        .AD1(dba0e8d), .AD0(do3a375), .DO0(ng863d9));    defparam pha56e0.initval =  16'h6996 ;    ROM16X1A pha56e0 (.AD3(meea83a), .AD2(dba0e8d), .AD1(do3a375),        .AD0(ld6e801), .DO0(ldec205));    defparam xwc5a2f.initval =  16'h6996 ;    ROM16X1A xwc5a2f (.AD3(dm476b4), .AD2(ld6102f),        .AD1(ldec205), .AD0(ld6e801), .DO0(ykf0c7b));    defparam mrf8eb2.initval =  16'h6996 ;    ROM16X1A mrf8eb2 (.AD3(zz37baa), .AD2(neeeab3), .AD1(bnaacdc),        .AD0(ecb3738), .DO0(tw4979));    defparam qt7a8a6.initval =  16'h6996 ;    ROM16X1A qt7a8a6 (.AD3(hb4ac0d), .AD2(xlb0370), .AD1(epdc37),        .AD0(cz70dee), .DO0(dz40bfc));    defparam xyb445.initval =  16'h6996 ;    ROM16X1A xyb445 (.AD3(bnaacdc), .AD2(ecb3738), .AD1(ld6e801),        .AD0(ld6e801), .DO0(eacb092));    defparam hof138c.initval =  16'h6996 ;    ROM16X1A hof138c (.AD3(neeeab3), .AD2(bnaacdc), .AD1(ecb3738),        .AD0(ld6e801), .DO0(xw79612));    defparam qi9de87.initval =  16'h6996 ;    ROM16X1A qi9de87 (.AD3(cz70dee), .AD2(zz37baa), .AD1(neeeab3),        .AD0(eacb092), .DO0(sw92f));    defparam aa5473.initval =  16'h6996 ;    ROM16X1A aa5473 (.AD3(epdc37), .AD2(cz70dee), .AD1(zz37baa),        .AD0(xw79612), .DO0(ohb1500));    defparam fc14ece.initval =  16'h6996 ;    ROM16X1A fc14ece (.AD3(xlb0370), .AD2(epdc37), .AD1(cz70dee),        .AD0(tw4979), .DO0(ui562a0));    defparam xl91848.initval =  16'h6996 ;    ROM16X1A xl91848 (.AD3(tw4979), .AD2(dz40bfc),        .AD1(ld6e801), .AD0(ld6e801), .DO0(oua9056));    defparam wy97cce.initval =  16'h6996 ;    ROM16X1A wy97cce (.AD3(tw4979), .AD2(dz40bfc),        .AD1(ose52b0), .AD0(ld6e801), .DO0(phb520a));    defparam mr6f479.initval =  16'h6996 ;    ROM16X1A mr6f479 (.AD3(tw4979), .AD2(dz40bfc),        .AD1(rv8b94a), .AD0(ose52b0), .DO0(iebcbb5));    defparam ph28aed.initval =  16'h6996 ;    ROM16X1A ph28aed (.AD3(ou3e2e5), .AD2(rv8b94a), .AD1(ose52b0),        .AD0(ld6e801), .DO0(gd817f));    defparam qvb153b.initval =  16'h6996 ;    ROM16X1A qvb153b (.AD3(tw4979), .AD2(dz40bfc),        .AD1(gd817f), .AD0(ld6e801), .DO0(gd17976));    XOR2 ie24422 (.A(irb1e36), .B(ecb3738), .Z(xj7b5e2));    XOR2 db22386 (.A(ofdcf8b), .B(tw8672e), .Z(cm68afe));    defparam ri86cbd.initval =  16'h0410 ;    ROM16X1A ri86cbd (.AD3(je1bbe3), .AD2(tw8672e), .AD1(ofdcf8b),        .AD0(ld6e801), .DO0(yx60e17));    defparam jraa28f.initval =  16'h1004 ;    ROM16X1A jraa28f (.AD3(je1bbe3), .AD2(tw8672e), .AD1(ofdcf8b),        .AD0(ld6e801), .DO0(dzec1c2));    defparam zmad931.initval =  16'h0140 ;    ROM16X1A zmad931 (.AD3(lqf4b76), .AD2(irb1e36), .AD1(ecb3738),        .AD0(ld6e801), .DO0(xl917e0));    defparam do9682b.initval =  16'h4001 ;    ROM16X1A do9682b (.AD3(lqf4b76), .AD2(irb1e36), .AD1(ecb3738),        .AD0(ld6e801), .DO0(ie922fc));    INV the602c (.A(db9b94a), .Z(co5fe7));    AND2 ec5995 (.A(czdce0f), .B(co5fe7), .Z(kqe52bc));    AND2 wl95316 (.A(czdce0f), .B(db9b94a), .Z(yz295e1));    defparam nt16a01.CSDECODE_B = "0b000" ;    defparam nt16a01.CSDECODE_A = "0b000" ;    defparam nt16a01.WRITEMODE_B = "NORMAL" ;    defparam nt16a01.WRITEMODE_A = "NORMAL" ;    defparam nt16a01.GSR = "ENABLED" ;    defparam nt16a01.REGMODE_B = "NOREG" ;    defparam nt16a01.REGMODE_A = "NOREG" ;    defparam nt16a01.DATA_WIDTH_B = 18 ;    defparam nt16a01.DATA_WIDTH_A = 18 ;    DP16KC nt16a01 (.DIA0(ui49c6d[0]), .DIA1(ui49c6d[1]), .DIA2(ui49c6d[2]),        .DIA3(ui49c6d[3]), .DIA4(ui49c6d[4]), .DIA5(ui49c6d[5]), .DIA6(ui49c6d[6]),        .DIA7(ui49c6d[7]), .DIA8(ui49c6d[8]), .DIA9(ui49c6d[9]), .DIA10(ui49c6d[10]),        .DIA11(ui49c6d[11]), .DIA12(ui49c6d[12]), .DIA13(ui49c6d[13]), .DIA14(ui49c6d[14]),        .DIA15(ui49c6d[15]), .DIA16(ui49c6d[16]), .DIA17(ui49c6d[17]), .ADA0(lfa007e),        .ADA1(lfa007e), .ADA2(ld6e801), .ADA3(ld6e801), .ADA4(vk2016b),        .ADA5(gqb5b), .ADA6(aa5ad9), .ADA7(hd2d6c9), .ADA8(fn6b64f), .ADA9(kd5b27e),        .ADA10(qtd93f4), .ADA11(qtc9fa5), .ADA12(jp4fd2d), .ADA13(bl7e96e),        .CEA(cobc373), .CLKA(of4e369), .OCEA(cobc373), .WEA(lfa007e), .CSA0(ld6e801),        .CSA1(ld6e801), .CSA2(ld6e801), .RSTA(ne69bc9), .DIB0(ld6e801),        .DIB1(ld6e801), .DIB2(ld6e801), .DIB3(ld6e801), .DIB4(ld6e801),        .DIB5(ld6e801), .DIB6(ld6e801), .DIB7(ld6e801), .DIB8(ld6e801),        .DIB9(ld6e801), .DIB10(ld6e801), .DIB11(ld6e801), .DIB12(ld6e801),        .DIB13(ld6e801), .DIB14(ld6e801), .DIB15(ld6e801), .DIB16(ld6e801),        .DIB17(ld6e801), .ADB0(ld6e801), .ADB1(ld6e801), .ADB2(ld6e801),        .ADB3(ld6e801), .ADB4(ldc7cee), .ADB5(ks3e776), .ADB6(ldf3bb1), .ADB7(ie9dd8e),        .ADB8(zkeec70), .ADB9(rg76383), .ADB10(kfb1c1b), .ADB11(hd8e0dd), .ADB12(of706ef),        .ADB13(hq8377c), .CEB(thfc1f7), .CLKB(th71b4d), .OCEB(thfc1f7), .WEB(ld6e801),        .CSB0(ld6e801), .CSB1(ld6e801), .CSB2(ld6e801), .RSTB(ne69bc9),        .DOA0(), .DOA1(), .DOA2(), .DOA3(), .DOA4(), .DOA5(), .DOA6(), .DOA7(),        .DOA8(), .DOA9(), .DOA10(), .DOA11(), .DOA12(), .DOA13(), .DOA14(),        .DOA15(), .DOA16(), .DOA17(), .DOB0(uvc94e2[0]), .DOB1(uvc94e2[1]), .DOB2(uvc94e2[2]),        .DOB3(uvc94e2[3]), .DOB4(uvc94e2[4]), .DOB5(uvc94e2[5]), .DOB6(uvc94e2[6]), .DOB7(uvc94e2[7]),        .DOB8(uvc94e2[8]), .DOB9(uvc94e2[9]), .DOB10(uvc94e2[10]), .DOB11(uvc94e2[11]), .DOB12(uvc94e2[12]),        .DOB13(uvc94e2[13]), .DOB14(uvc94e2[14]), .DOB15(uvc94e2[15]), .DOB16(uvc94e2[16]), .DOB17(uvc94e2[17]))\r
+                          ;    FD1P3BX mg77a (.D(ief931), .SP(cobc373), .CK(of4e369), .PD(ne69bc9),        .Q(sue5da9))             ;    FD1P3DX ng8682a (.D(rg7c988), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(ec2ed48))             ;    FD1P3DX yz90c12 (.D(sj2621a), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(ho482b1))             ;    FD1P3DX aaa346f (.D(ec310d4), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(kd4158a))             ;    FD1P3DX vic0060 (.D(kq43500), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(ir8a804))             ;    FD1P3DX uk107ad (.D(gq1a801), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(sh54024))             ;    FD1P3DX zx4a65b (.D(hda0049), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(aa24bcb))             ;    FD1P3DX ipf866a (.D(ym24f), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(ri25e58))             ;    FD1P3DX hda5dac (.D(nt93c2), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(ps58491))             ;    FD1P3DX ie315c2 (.D(ea49e16), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(jpc248b))             ;    FD1P3DX ph844b8 (.D(os7858f), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(irb1e36))             ;    FD1P3DX oh36a1c (.D(vk2ff39), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(nrddf1b))             ;    FD1P3DX yz26632 (.D(mr7f9cb), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(meef8de))             ;    FD1P3DX jra5176 (.D(xjfce5c), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(rg7c6f1))             ;    FD1P3DX qvbee52 (.D(kde72e7), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(lde378a))             ;    FD1P3DX zza50de (.D(ux3973c), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(ba1bc56))             ;    FD1P3DX zzbf2cc (.D(gocb9e4), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(ykde2b3))             ;    FD1P3DX qi3e229 (.D(ay5cf20), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(xwf1598))             ;    FD1P3DX rt4a3a8 (.D(ofe7900), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(cb8acc2))             ;    FD1P3DX cb3cd12 (.D(ep3c805), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(ui56614))             ;    FD1P3DX vxaf0ac (.D(nee402d), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(mgb30a0))             ;    FD1P3DX je30c02 (.D(irb1e36), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(uk98501))             ;    FD1P3DX hd9b52e (.D(sue5da9), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(vk2016b))             ;    FD1P3DX qib318b (.D(ec2ed48), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(gqb5b))             ;    FD1P3DX zxc8a39 (.D(ho482b1), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(aa5ad9))             ;    FD1P3DX hb7ecea (.D(kd4158a), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(hd2d6c9))             ;    FD1P3DX twb7049 (.D(ir8a804), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(fn6b64f))             ;    FD1P3DX zx5a185 (.D(sh54024), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(kd5b27e))             ;    FD1P3DX su726e8 (.D(aa24bcb), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(qtd93f4))             ;    FD1P3DX qiafec (.D(ri25e58), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(qtc9fa5))             ;    FD1P3DX vx3d7d (.D(ps58491), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(jp4fd2d))             ;    FD1P3DX dm733ca (.D(jpc248b), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(bl7e96e))             ;    FD1P3DX ux9a698 (.D(irb1e36), .SP(cobc373), .CK(of4e369), .CD(ne69bc9),        .Q(lqf4b76))             ;    FD1P3BX ec24901 (.D(qv8f1b5), .SP(thfc1f7), .CK(th71b4d), .PD(uic1f26),        .Q(ec31ecb))             ;    FD1P3DX nr402d4 (.D(go78dad), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(kf8f659))             ;    FD1P3DX bn327c0 (.D(ir36b4c), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(yk59be9))             ;    FD1P3DX aa3b91d (.D(ntb5a64), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(zxcdf48))             ;    FD1P3DX al4476c (.D(xw6993b), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(zk48f47))             ;    FD1P3DX pu25916 (.D(ww4c9da), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(by47a3b))             ;    FD1P3DX fp94ff2 (.D(hd2768e), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(co3b5a3))             ;    FD1P3DX ecb34e2 (.D(uk3b476), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(xwdad19))             ;    FD1P3DX ng8cae2 (.D(wwd1d8a), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(lf19760))             ;    FD1P3DX co9d267 (.D(fp8ec50), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(aycbb07))             ;    FD1P3DX tucf245 (.D(anb1433), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(tw8672e))             ;    FD1P3DX dz5a8f0 (.D(pha5bb3), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(xjc2809))             ;    FD1P3DX sj39289 (.D(jr2dd9e), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(do1404e))             ;    FD1P3DX dz64f59 (.D(rt6ecf6), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(nta0273))             ;    FD1P3DX ui77c80 (.D(fa767b7), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(vk139f))             ;    FD1P3DX ym5b61 (.D(qib3dbb), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(ph9cfa))             ;    FD1P3DX mr4e0ff (.D(zz9edd8), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(al4e7d7))             ;    FD1P3DX blec445 (.D(ldf6ec7), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(jc73ebd))             ;    FD1P3DX su7867a (.D(jeb763e), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(ux9f5ea))             ;    FD1P3DX mt85cea (.D(yzbb1f3), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(qgfaf54))             ;    FD1P3DX xya844f (.D(thd8f9d), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(dzd7aa0))             ;    FD1P3DX sudb6ff (.D(tw8672e), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(lsbd507))             ;    FD1P3DX fac02cc (.D(ec31ecb), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(ldc7cee))             ;    FD1P3DX cb12620 (.D(kf8f659), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(ks3e776))             ;    FD1P3DX db22012 (.D(yk59be9), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(ldf3bb1))             ;    FD1P3DX kfb196a (.D(zxcdf48), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(ie9dd8e))             ;    FD1P3DX yzab9ef (.D(zk48f47), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(zkeec70))             ;    FD1P3DX gbe8bc8 (.D(by47a3b), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(rg76383))             ;    FD1P3DX tj274bd (.D(co3b5a3), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(kfb1c1b))             ;    FD1P3DX dm73e5a (.D(xwdad19), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(hd8e0dd))             ;    FD1P3DX db94c77 (.D(lf19760), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(of706ef))             ;    FD1P3DX ayf0385 (.D(aycbb07), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26), .Q(hq8377c))             ;    FD1P3DX ne47766 (.D(tw8672e), .SP(thfc1f7), .CK(th71b4d), .CD(uic1f26),        .Q(je1bbe3))             ;    FD1S3DX qi98d95 (.D(nrddf1b), .CK(th71b4d), .CD(ne69bc9), .Q(sh541d1))             ;    FD1S3DX twa8955 (.D(meef8de), .CK(th71b4d), .CD(ne69bc9), .Q(qv746e))             ;    FD1S3DX tjaaadf (.D(rg7c6f1), .CK(th71b4d), .CD(ne69bc9), .Q(ead1bab))             ;    FD1S3DX cmfff2b (.D(lde378a), .CK(th71b4d), .CD(ne69bc9), .Q(th6eac1))             ;    FD1S3DX xw581c8 (.D(ba1bc56), .CK(th71b4d), .CD(ne69bc9), .Q(uxab07c))             ;    FD1S3DX ww43766 (.D(ykde2b3), .CK(th71b4d), .CD(ne69bc9), .Q(icc1f23))             ;    FD1S3DX qi317b2 (.D(xwf1598), .CK(th71b4d), .CD(ne69bc9), .Q(dm7c8c8))             ;    FD1S3DX mt90d7b (.D(cb8acc2), .CK(th71b4d), .CD(ne69bc9), .Q(kf2321b))             ;    FD1S3DX uvdc4f6 (.D(ui56614), .CK(th71b4d), .CD(ne69bc9), .Q(fnc86e7))             ;    FD1S3DX vxb59fe (.D(mgb30a0), .CK(th71b4d), .CD(ne69bc9), .Q(tw1b9f1))             ;    FD1S3DX enf7052 (.D(uk98501), .CK(th71b4d), .CD(ne69bc9), .Q(wje7c5c))             ;    FD1S3DX oh9540b (.D(xjc2809), .CK(of4e369), .CD(uic1f26), .Q(psf1729))             ;\r
+    FD1S3DX tu5ddf2 (.D(do1404e), .CK(of4e369), .CD(uic1f26), .Q(kq5ca56))             ;    FD1S3DX aa9262d (.D(nta0273), .CK(of4e369), .CD(uic1f26), .Q(ep29581))             ;    FD1S3DX me6841f (.D(vk139f), .CK(of4e369), .CD(uic1f26), .Q(ic5606e))             ;    FD1S3DX nrf9650 (.D(ph9cfa), .CK(of4e369), .CD(uic1f26), .Q(db81b86))             ;    FD1S3DX fc8625e (.D(al4e7d7), .CK(of4e369), .CD(uic1f26), .Q(rt6e1bd))             ;    FD1S3DX fnf30a4 (.D(jc73ebd), .CK(of4e369), .CD(uic1f26), .Q(tw86f75))             ;    FD1S3DX bn27394 (.D(ux9f5ea), .CK(of4e369), .CD(uic1f26), .Q(ribdd56))             ;    FD1S3DX mga6a46 (.D(qgfaf54), .CK(of4e369), .CD(uic1f26), .Q(al7559b))             ;    FD1S3DX uk31459 (.D(dzd7aa0), .CK(of4e369), .CD(uic1f26), .Q(go566e7))             ;    FD1S3DX fnc8b79 (.D(lsbd507), .CK(of4e369), .CD(uic1f26), .Q(lf9b9c1))             ;    FD1S3DX facffa3 (.D(sh541d1), .CK(th71b4d), .CD(ne69bc9), .Q(meea83a))             ;    FD1S3DX gq1a890 (.D(qv746e), .CK(th71b4d), .CD(ne69bc9), .Q(dba0e8d))             ;    FD1S3DX lf812a5 (.D(ead1bab), .CK(th71b4d), .CD(ne69bc9), .Q(do3a375))             ;    FD1S3DX qi2eda6 (.D(th6eac1), .CK(th71b4d), .CD(ne69bc9), .Q(ou8dd58))             ;    FD1S3DX gq31428 (.D(uxab07c), .CK(th71b4d), .CD(ne69bc9), .Q(wj7560f))             ;    FD1S3DX bl40ba7 (.D(icc1f23), .CK(th71b4d), .CD(ne69bc9), .Q(zk583e4))             ;    FD1S3DX ls3f27b (.D(dm7c8c8), .CK(th71b4d), .CD(ne69bc9), .Q(qif919))             ;    FD1S3DX sudbd7f (.D(kf2321b), .CK(th71b4d), .CD(ne69bc9), .Q(fae4643))             ;    FD1S3DX xjf927d (.D(fnc86e7), .CK(th71b4d), .CD(ne69bc9), .Q(vx190dc))             ;    FD1S3DX psee871 (.D(tw1b9f1), .CK(th71b4d), .CD(ne69bc9), .Q(su4373e))             ;    FD1S3DX lf8bd1e (.D(wje7c5c), .CK(th71b4d), .CD(ne69bc9), .Q(ofdcf8b))             ;    FD1S3DX rtf6a8b (.D(psf1729), .CK(of4e369), .CD(uic1f26), .Q(ou3e2e5))             ;    FD1S3DX mr5edae (.D(kq5ca56), .CK(of4e369), .CD(uic1f26), .Q(rv8b94a))             ;    FD1S3DX gb75c3d (.D(ep29581), .CK(of4e369), .CD(uic1f26), .Q(ose52b0))             ;    FD1S3DX kded947 (.D(ic5606e), .CK(of4e369), .CD(uic1f26), .Q(hb4ac0d))             ;    FD1S3DX ux3c572 (.D(db81b86), .CK(of4e369), .CD(uic1f26), .Q(xlb0370))             ;    FD1S3DX zz94a20 (.D(rt6e1bd), .CK(of4e369), .CD(uic1f26), .Q(epdc37))             ;    FD1S3DX tj6fa2 (.D(tw86f75), .CK(of4e369), .CD(uic1f26), .Q(cz70dee))             ;    FD1S3DX lf16d13 (.D(ribdd56), .CK(of4e369), .CD(uic1f26), .Q(zz37baa))             ;    FD1S3DX ux9f117 (.D(al7559b), .CK(of4e369), .CD(uic1f26), .Q(neeeab3))             ;    FD1S3DX mgbca3d (.D(go566e7), .CK(of4e369), .CD(uic1f26), .Q(bnaacdc))             ;    FD1S3DX rte9396 (.D(lf9b9c1), .CK(of4e369), .CD(uic1f26), .Q(ecb3738))             ;    FD1S3DX zmb7343 (.D(cb33973), .CK(of4e369), .CD(ne69bc9), .Q(ohdcc2))             ;    FD1S3DX ls1b389 (.D(cme5ce2), .CK(of4e369), .CD(ne69bc9), .Q(th6e615))             ;    FD1S3DX hb4a872 (.D(gq2e710), .CK(of4e369), .CD(ne69bc9), .Q(ie98573))             ;    FD1S3DX je96b18 (.D(fc9c402), .CK(of4e369), .CD(ne69bc9), .Q(fnc2b99))             ;    FD1S3DX alc3e55 (.D(gbe2013), .CK(of4e369), .CD(ne69bc9), .Q(sjae670))             ;    FD1S3DX gqac196 (.D(gd804e1), .CK(of4e369), .CD(ne69bc9), .Q(jc73384))             ;    FD1S3DX irb19f2 (.D(yz270c), .CK(of4e369), .CD(ne69bc9), .Q(osce11a))             ;    FD1S3DX ir9564c (.D(tw9c32f), .CK(of4e369), .CD(ne69bc9), .Q(sh708d1))             ;    FD1S3DX al65869 (.D(nee197b), .CK(of4e369), .CD(ne69bc9), .Q(yz2346e))             ;    FD1S3DX ay4cba2 (.D(gb65ed7), .CK(of4e369), .CD(ne69bc9), .Q(aa1a374))             ;    FD1S3DX hq11872 (.D(ng2f6bc), .CK(of4e369), .CD(ne69bc9), .Q(aa8dd00))             ;    FD1S3DX gq92599 (.D(wje2ef8), .CK(th71b4d), .CD(uic1f26), .Q(cb7df0))             ;    FD1S3DX nrc828b (.D(irbbe2c), .CK(th71b4d), .CD(uic1f26), .Q(qi3ef84))             ;    FD1S3DX sh5e86e (.D(psdf164), .CK(th71b4d), .CD(uic1f26), .Q(qvbe104))             ;    FD1S3DX kd7552f (.D(nec5915), .CK(th71b4d), .CD(uic1f26), .Q(eaf0825))             ;    FD1S3DX xw7cf33 (.D(gd2c8ab), .CK(th71b4d), .CD(uic1f26), .Q(ls2094e))             ;    FD1S3DX nt9bb75 (.D(tj22ae7), .CK(th71b4d), .CD(uic1f26), .Q(ba4a72))             ;    FD1S3DX tjafd3d (.D(qi1573f), .CK(th71b4d), .CD(uic1f26), .Q(wl29c9b))             ;    FD1S3DX eaefcdf (.D(qg5cfcd), .CK(th71b4d), .CD(uic1f26), .Q(qt4e4dc))             ;    FD1S3DX dzf9ffa (.D(mre7e68), .CK(th71b4d), .CD(uic1f26), .Q(zm93729))             ;    FD1S3DX vvd7508 (.D(jpf9a2b), .CK(th71b4d), .CD(uic1f26), .Q(db9b94a))             ;    FD1S3DX ic46c6d (.D(dzcd15f), .CK(th71b4d), .CD(uic1f26), .Q(czdce0f))             ;    FD1S3BX qg68b49 (.D(cb70bc), .CK(th71b4d), .PD(uic1f26), .Q(ene707c))             ;    FD1S3DX ho48fd8 (.D(rv8bf07), .CK(of4e369), .CD(ne69bc9), .Q(zz383e4))             ;    FD1S3BX kdc34df (.D(ld4af0d), .CK(th71b4d), .PD(uic1f26), .Q(ba9c539))             ;    FD1S3DX yxfd13b (.D(ld7400f), .CK(of4e369), .CD(ne69bc9), .Q(ale29cb))             ;    FADD2B czdc970 (.A0(ld6e801), .A1(lfa007e), .B0(ld6e801), .B1(lfa007e),        .CI(ld6e801), .COUT(nee4c43), .S0(), .S1());    CU2 zm252ac (.CI(nee4c43), .PC0(sue5da9), .PC1(ec2ed48), .CO(ec886a0),        .NC0(ief931), .NC1(rg7c988));    CU2 nt8e731 (.CI(ec886a0), .PC0(ho482b1), .PC1(kd4158a), .CO(med4009), .NC0(sj2621a),        .NC1(ec310d4));    CU2 al448cb (.CI(med4009), .PC0(ir8a804), .PC1(sh54024), .CO(ls1278), .NC0(kq43500),        .NC1(gq1a801));    CU2 yz12202 (.CI(ls1278), .PC0(aa24bcb), .PC1(ri25e58), .CO(rt4f0b1), .NC0(hda0049),        .NC1(ym24f));    CU2 gqa9061 (.CI(rt4f0b1), .PC0(ps58491), .PC1(jpc248b), .CO(db163c6), .NC0(nt93c2),        .NC1(ea49e16));    CU2 ng30cac (.CI(db163c6), .PC0(irb1e36), .PC1(ld6e801), .CO(nrc2c78),        .NC0(os7858f), .NC1());    FADD2B by486b9 (.A0(ld6e801), .A1(lfa007e), .B0(ld6e801), .B1(lfa007e),        .CI(ld6e801), .COUT(enc6d69), .S0(), .S1());    CU2 rtec55a (.CI(enc6d69), .PC0(ec31ecb), .PC1(kf8f659), .CO(doad327),        .NC0(qv8f1b5), .NC1(go78dad));    CU2 ww4ca01 (.CI(doad327), .PC0(yk59be9), .PC1(zxcdf48), .CO(fn64ed1),        .NC0(ir36b4c), .NC1(ntb5a64));    CU2 wl26283 (.CI(fn64ed1), .PC0(zk48f47), .PC1(by47a3b), .CO(lqda3b1),        .NC0(xw6993b), .NC1(ww4c9da));    CU2 an90107 (.CI(lqda3b1), .PC0(co3b5a3), .PC1(xwdad19), .CO(tu76286),        .NC0(hd2768e), .NC1(uk3b476));    CU2 wwff6b5 (.CI(tu76286), .PC0(lf19760), .PC1(aycbb07), .CO(ld50ce5),        .NC0(wwd1d8a), .NC1(fp8ec50));    CU2 zxc8c00 (.CI(ld50ce5), .PC0(tw8672e), .PC1(ld6e801), .CO(an8a19c),        .NC0(anb1433), .NC1());    FSUB2B hd8bd85 (.A0(lfa007e), .A1(sue5da9), .B0(ld6e801), .B1(gd17976),        .BI(ld6e801), .BOUT(rg73880), .S0(), .S1(cb33973));    FSUB2B kf33ad4 (.A0(ec2ed48), .A1(ho482b1), .B0(iebcbb5), .B1(phb520a),        .BI(rg73880), .BOUT(mg1009c), .S0(cme5ce2), .S1(gq2e710));    FSUB2B phaa7ab (.A0(kd4158a), .A1(ir8a804), .B0(oua9056), .B1(ui562a0),        .BI(mg1009c), .BOUT(rv13865), .S0(fc9c402), .S1(gbe2013));    FSUB2B lq5df1b (.A0(sh54024), .A1(aa24bcb), .B0(ohb1500), .B1(sw92f),        .BI(rv13865), .BOUT(tjcbda), .S0(gd804e1), .S1(yz270c));    FSUB2B hd32be5 (.A0(ri25e58), .A1(ps58491), .B0(tw4979),        .B1(xw79612), .BI(tjcbda), .BOUT(jcdaf17), .S0(tw9c32f), .S1(nee197b));    FSUB2B ne4d155 (.A0(jpc248b), .A1(xj7b5e2), .B0(eacb092), .B1(ld6e801),        .BI(jcdaf17), .BOUT(mgbc5df), .S0(gb65ed7), .S1(ng2f6bc));    FADD2B bab845a (.A0(ld6e801), .A1(ld6e801), .B0(ld6e801), .B1(ld6e801),        .CI(mgbc5df), .COUT(), .S0(nrd78bb), .S1());    VHI xjc7664 (.Z(lfa007e));    FSUB2B twe316 (.A0(lfa007e), .A1(ykf0c7b), .B0(ld6e801), .B1(ec31ecb),        .BI(ld6e801), .BOUT(enf8b22), .S0(), .S1(wje2ef8));    FSUB2B rgee357 (.A0(ng863d9), .A1(ipd966f), .B0(kf8f659), .B1(yk59be9),        .BI(enf8b22), .BOUT(th6455c), .S0(irbbe2c), .S1(psdf164));    FSUB2B ea4991c (.A0(cmcb37d), .A1(os7d23d), .B0(zxcdf48), .B1(zk48f47),        .BI(th6455c), .BOUT(mtab9f9), .S0(nec5915), .S1(gd2c8ab));    FSUB2B rv9b44d (.A0(nre91e8), .A1(ofe8ed6), .B0(by47a3b), .B1(co3b5a3),        .BI(mtab9f9), .BOUT(ng3f345), .S0\r
+(tj22ae7), .S1(qi1573f));    FSUB2B bn1c928 (.A0(dm476b4), .A1(sjb465d), .B0(xwdad19),        .B1(lf19760), .BI(ng3f345), .BOUT(nr457f0), .S0(qg5cfcd), .S1(mre7e68));    FSUB2B uie009b (.A0(mga32ec), .A1(cm68afe), .B0(aycbb07), .B1(ld6e801),        .BI(nr457f0), .BOUT(bl5fc31), .S0(jpf9a2b), .S1(dzcd15f));    FADD2B kdfdc9e (.A0(ld6e801), .A1(ld6e801), .B0(ld6e801), .B1(ld6e801),        .CI(bl5fc31), .COUT(), .S0(aa2bf86), .S1());    FADD2B jrb58ea (.A0(ld6e801), .A1(thfc1f7), .B0(ld6e801),        .B1(thfc1f7), .CI(ld6e801), .COUT(zkfe18f), .S0(), .S1());    AGEB2 ym1ffe6 (.A0(ec31ecb), .A1(kf8f659), .B0(ykf0c7b), .B1(ng863d9),        .CI(zkfe18f), .GE(nr7b2cd));    AGEB2 yz8b23 (.A0(yk59be9), .A1(zxcdf48), .B0(ipd966f), .B1(cmcb37d),        .CI(nr7b2cd), .GE(cz6fa47));    AGEB2 mr7fe91 (.A0(zk48f47), .A1(by47a3b), .B0(os7d23d), .B1(nre91e8),        .CI(cz6fa47), .GE(lf3d1da));    AGEB2 ec1a3b6 (.A0(co3b5a3), .A1(xwdad19), .B0(ofe8ed6), .B1(dm476b4),        .CI(lf3d1da), .GE(uvd68cb));    AGEB2 ldf6be2 (.A0(lf19760), .A1(aycbb07), .B0(sjb465d), .B1(mga32ec),        .CI(uvd68cb), .GE(fa5d838));    AGEB2 bn16996 (.A0(yx60e17), .A1(ld6e801), .B0(dzec1c2),        .B1(ld6e801), .CI(fa5d838), .GE(xl385e5));    FADD2B vi6cfe5 (.A0(ld6e801), .A1(ld6e801), .B0(ld6e801), .B1(ld6e801),        .CI(xl385e5), .COUT(), .S0(cb70bc), .S1());    FADD2B ym82c41 (.A0(ld6e801), .A1(cobc373), .B0(ld6e801), .B1(cobc373),        .CI(ld6e801), .COUT(hbc2f2e), .S0(), .S1());    AGEB2 wl337ff (.A0(sue5da9), .A1(ec2ed48), .B0(gd17976), .B1(iebcbb5),        .CI(hbc2f2e), .GE(fa76a41));    AGEB2 hbd8c9b (.A0(ho482b1), .A1(kd4158a), .B0(phb520a), .B1(oua9056),        .CI(fa76a41), .GE(coac54));    AGEB2 hq30b38 (.A0(ir8a804), .A1(sh54024), .B0(ui562a0), .B1(ohb1500),        .CI(coac54), .GE(dba0125));    AGEB2 qi319ee (.A0(aa24bcb), .A1(ri25e58), .B0(sw92f), .B1(tw4979),        .CI(dba0125), .GE(xy2f2c2));    AGEB2 ose56a6 (.A0(ps58491), .A1(jpc248b), .B0(xw79612), .B1(eacb092),        .CI(xy2f2c2), .GE(an1245f));    AGEB2 mt904a5 (.A0(xl917e0), .A1(ld6e801), .B0(ie922fc),        .B1(ld6e801), .CI(an1245f), .GE(nr5f83e));    FADD2B shd3f61 (.A0(ld6e801), .A1(ld6e801), .B0(ld6e801), .B1(ld6e801),        .CI(nr5f83e), .COUT(), .S0(rv8bf07), .S1());    FADD2B yx707c8 (.A0(ld6e801), .A1(thfc1f7), .B0(ld6e801), .B1(thfc1f7),        .CI(ld6e801), .COUT(yke0fbe), .S0(), .S1());    AGEB2 vx16390 (.A0(wj6f253[0]), .A1(wj6f253[1]), .B0(cb7df0),        .B1(qi3ef84), .CI(yke0fbe), .GE(czf7c20));    AGEB2 goe0fb3 (.A0(wj6f253[2]), .A1(wj6f253[3]), .B0(qvbe104),        .B1(eaf0825), .CI(czf7c20), .GE(lf84129));    AGEB2 xw66d00 (.A0(wj6f253[4]), .A1(wj6f253[5]), .B0(ls2094e),        .B1(ba4a72), .CI(lf84129), .GE(ng25393));    AGEB2 ukbca9a (.A0(wj6f253[6]), .A1(wj6f253[7]), .B0(wl29c9b),        .B1(qt4e4dc), .CI(ng25393), .GE(go726e5));    AGEB2 epb10e7 (.A0(wj6f253[8]), .A1(wj6f253[9]), .B0(zm93729),        .B1(db9b94a), .CI(go726e5), .GE(qtdca57));    AGEB2 vk99feb (.A0(yz295e1), .A1(ld6e801), .B0(kqe52bc), .B1(ld6e801),        .CI(qtdca57), .GE(ps5786e));    FADD2B al7f50f (.A0(ld6e801), .A1(ld6e801), .B0(ld6e801), .B1(ld6e801),        .CI(ps5786e), .COUT(), .S0(ld4af0d), .S1());    FADD2B ksa93bc (.A0(ld6e801), .A1(cobc373), .B0(ld6e801), .B1(cobc373),        .CI(ld6e801), .COUT(tue1b98), .S0(), .S1());    AGEB2 jr28c2a (.A0(ohdcc2), .A1(th6e615), .B0(ps7929c[0]),        .B1(ps7929c[1]), .CI(tue1b98), .GE(rg730ae));    AGEB2 ld7430e (.A0(ie98573), .A1(fnc2b99), .B0(ps7929c[2]),        .B1(ps7929c[3]), .CI(rg730ae), .GE(ou15cce));    AGEB2 cm59a16 (.A0(sjae670), .A1(jc73384), .B0(ps7929c[4]),        .B1(ps7929c[5]), .CI(ou15cce), .GE(xy99c23));    AGEB2 vkbb81 (.A0(osce11a), .A1(sh708d1), .B0(ps7929c[6]),        .B1(ps7929c[7]), .CI(xy99c23), .GE(tj8468d));    AGEB2 oh80b3c (.A0(yz2346e), .A1(aa1a374), .B0(ps7929c[8]),        .B1(ps7929c[9]), .CI(tj8468d), .GE(med1ba0));    AGEB2 vx84c10 (.A0(aa8dd00), .A1(ld6e801), .B0(ld6e801),        .B1(ld6e801), .CI(med1ba0), .GE(ec3f7));    VLO baa2130 (.Z(ld6e801));    FADD2B end9939 (.A0(ld6e801), .A1(ld6e801), .B0(ld6e801), .B1(ld6e801),        .CI(ec3f7), .COUT(), .S0(ld7400f), .S1());    assign ld4a714 = xl220da;    assign su538a7 = sw106d6;\r
+always@* begin hq1fb8<={ui49c6d>>1,vx8bfb1[0]};iefdc3<=vx8bfb1[1];th7ee18<=vx8bfb1[2];alf70c6<=vx8bfb1[3];dob8635<=vx8bfb1[4];czc31aa<=vx8bfb1[5];wl18d55<=vx8bfb1[6];ipc6aac<={wj6f253>>1,vx8bfb1[7]};ng35564<={ps7929c>>1,vx8bfb1[8]};bnaab22<=vx8bfb1[9];jp55917<=vx8bfb1[10];coac8be<=vx8bfb1[11];nr645f0<=vx8bfb1[12];xl22f87<=vx8bfb1[13];yz17c3f<=vx8bfb1[14];yzbe1fd<=vx8bfb1[15];qgf0fed<=vx8bfb1[16];aa87f69<=vx8bfb1[17];ba3fb48<=vx8bfb1[18];mrfda42<=vx8bfb1[19];aled215<=vx8bfb1[20];zk690ad<=vx8bfb1[21];rg4856b<=vx8bfb1[22];lq42b5a<=vx8bfb1[23];ks15ad2<=vx8bfb1[24];lsad690<=vx8bfb1[25];ld6b483<=vx8bfb1[26];hb5a41e<=vx8bfb1[27];thd20f6<=vx8bfb1[28];gd907b6<=vx8bfb1[29];je83db5<=vx8bfb1[30];vk1edaa<=vx8bfb1[31];fnf6d53<=vx8bfb1[32];mgb6a9e<=vx8bfb1[33];tjb54f0<=vx8bfb1[34];xlaa786<=vx8bfb1[35];ww53c36<=vx8bfb1[36];jr9e1b1<=vx8bfb1[37];gof0d8e<=vx8bfb1[38];zm86c71<=vx8bfb1[39];ux3638a<=vx8bfb1[40];irb1c55<=vx8bfb1[41];rv8e2ad<=vx8bfb1[42];rt7156f<=vx8bfb1[43];gd8ab7e<=vx8bfb1[44];dz55bf4<=vx8bfb1[45];hqadfa6<=vx8bfb1[46];al6fd32<=vx8bfb1[47];bl7e995<=vx8bfb1[48];lqf4cae<=vx8bfb1[49];mga6573<=vx8bfb1[50];lf32b98<=vx8bfb1[51];kf95cc6<=vx8bfb1[52];mtae634<=vx8bfb1[53];ne731a4<=vx8bfb1[54];co98d23<=vx8bfb1[55];enc6918<=vx8bfb1[56];gq348c4<=vx8bfb1[57];ana4621<=vx8bfb1[58];wl2310d<=vx8bfb1[59];mt1886c<=vx8bfb1[60];eac4364<=vx8bfb1[61];gq21b20<=vx8bfb1[62];ohd900<=vx8bfb1[63];rg6c805<=vx8bfb1[64];dz6402a<=vx8bfb1[65];tw20157<=vx8bfb1[66];qiabb<=vx8bfb1[67];co55d9<=vx8bfb1[68];ri2aec8<=vx8bfb1[69];fa57643<=vx8bfb1[70];yzbb21a<=vx8bfb1[71];shd90d5<=vx8bfb1[72];hbc86ad<=vx8bfb1[73];ic4356e<=vx8bfb1[74];qi1ab71<=vx8bfb1[75];psd5b89<=vx8bfb1[76];zmadc4a<=vx8bfb1[77];pf6e252<=vx8bfb1[78];nr71296<=vx8bfb1[79];zm894b6<=vx8bfb1[80];zx4a5b2<=vx8bfb1[81];by52d97<=vx8bfb1[82];vk96cbb<=vx8bfb1[83];ymb65db<=vx8bfb1[84];ngb2ed9<=vx8bfb1[85];ym976ca<=vx8bfb1[86];uxbb650<=vx8bfb1[87];kqdb285<=vx8bfb1[88];qtd9428<=vx8bfb1[89];psca145<=vx8bfb1[90];bl50a2b<=vx8bfb1[91];sj8515e<=vx8bfb1[92];rv28af4<=vx8bfb1[93];dz457a6<=vx8bfb1[94];ym2bd36<=vx8bfb1[95];kd5e9b1<=vx8bfb1[96];tuf4d8d<=vx8bfb1[97];yma6c6b<=vx8bfb1[98];gd36359<=vx8bfb1[99];anb1acd<=vx8bfb1[100];co8d66d<=vx8bfb1[101];xj6b368<=vx8bfb1[102];ww59b46<=vx8bfb1[103];jpcda30<=vx8bfb1[104];cm6d187<=vx8bfb1[105];os68c39<=vx8bfb1[106];cm461c8<=vx8bfb1[107];vk30e41<=vx8bfb1[108];ou8720b<=vx8bfb1[109];oh39059<=vx8bfb1[110];nrc82cc<=vx8bfb1[111];gb41666<=vx8bfb1[112];xyb334<=vx8bfb1[113];kq599a3<=vx8bfb1[114];qtccd18<=vx8bfb1[115];ho668c5<=vx8bfb1[116];ym3462b<=vx8bfb1[117];iea3158<=vx8bfb1[118];ep18ac0<=vx8bfb1[119];tuc5604<=vx8bfb1[120];wy2b022<=vx8bfb1[121];ps58110<=vx8bfb1[122];hoc0883<=vx8bfb1[123];je441b<=vx8bfb1[124];xl220da<=vx8bfb1[125];sw106d6<=vx8bfb1[126];ba836b1<=vx8bfb1[127];ng1b58b<=vx8bfb1[128];nedac5a<=vx8bfb1[129];shd62d3<=vx8bfb1[130];yzb169c<=vx8bfb1[131];lf8b4e4<=vx8bfb1[132];vv5a727<=vx8bfb1[133];ald393e<=vx8bfb1[134];ng9c9f5<=vx8bfb1[135];nee4faa<=vx8bfb1[136];tj27d52<=vx8bfb1[137];qi3ea97<=vx8bfb1[138];ayf54b8<=vx8bfb1[139];bnaa5c0<=vx8bfb1[140];dm52e06<=vx8bfb1[141];ks97033<=vx8bfb1[142];lsb8198<=vx8bfb1[143];nec0cc2<=vx8bfb1[144];kf3309f<=vx8bfb1[145];hd6613<=vx8bfb1[146];ec984fd<=vx8bfb1[147];zxc27e9<=vx8bfb1[148];zz13f4f<=vx8bfb1[149];gd9fa7f<=vx8bfb1[150];offd3fd<=vx8bfb1[151];nre9fec<=vx8bfb1[152];xj4ff66<=vx8bfb1[153];ip7fb36<=vx8bfb1[154];qtfd9b4<=vx8bfb1[155];hbecda5<=vx8bfb1[156];zk66d2e<=vx8bfb1[157];oh36973<=vx8bfb1[158];irb4b9c<=vx8bfb1[159];rva5ce5<=vx8bfb1[160];wy2e72e<=vx8bfb1[161];ps73970<=vx8bfb1[162];pu9cb82<=vx8bfb1[163];gq2e090<=vx8bfb1[164];cme5c12<=vx8bfb1[165];sh70480<=vx8bfb1[166];yz12021<=vx8bfb1[167];ux9010c<=vx8bfb1[168];sj80865<=vx8bfb1[169];tw432d<=vx8bfb1[170];wy2196a<=vx8bfb1[171];ntcb50<=vx8bfb1[172];kd65a87<=vx8bfb1[173];vx2d43c<=vx8bfb1[174];mr6a1e7<=vx8bfb1[175];pf50f3c<=vx8bfb1[176];ym879e6<=vx8bfb1[177];mt3cf30<=vx8bfb1[178];ale7985<=vx8bfb1[179];wl3cc2d<=vx8bfb1[180];pu30b6e<=vx8bfb1[181];dze616d<=vx8bfb1[182];ux85b73<=vx8bfb1[183];lf2db9d<=vx8bfb1[184];ea6dcee<=vx8bfb1[185];xj6b45f<=vx8bfb1[186];tu73b86<=vx8bfb1[187];uk9dc32<=vx8bfb1[188];rgee190<=vx8bfb1[189];cz70c82<=vx8bfb1[190];tw86415<=vx8bfb1[191];db320ab<=vx8bfb1[192];cb9055f<=vx8bfb1[193];co82afd<=vx8bfb1[194];qi157e8<=vx8bfb1[195];mtabf41<=vx8bfb1[196];th5fa0d<=vx8bfb1[197];offd06f<=vx8bfb1[198];mre837c<=vx8bfb1[199];sh41be5<=vx8bfb1[200];of6f96d<=vx8bfb1[201];uxdf2d<=vx8bfb1[202];ho7cb6d<=vx8bfb1[203];kqe5b6b<=vx8bfb1[204];vx2db58<=vx8bfb1[205];go6dac6<=vx8bfb1[206];qg6d630<=vx8bfb1[207];zx6b181<=vx8bfb1[208];ne58c0e<=vx8bfb1[209];ofc6072<=vx8bfb1[210];ng30395<=vx8bfb1[211];bn81caa<=vx8bfb1[212];nge557<=vx8bfb1[213];ic72abb<=vx8bfb1[214];mt955d8<=vx8bfb1[215];hdaaec5<=vx8bfb1[216];dm5762f<=vx8bfb1[217];irbb17a<=vx8bfb1[218];vvd8bd5<=vx8bfb1[219];zkc5eae<=vx8bfb1[220];xy2f573<=vx8bfb1[221];yx7ab9a<=vx8bfb1[222];ned5cd4<=vx8bfb1[223];kfae6a2<=vx8bfb1[224];xw73514<=vx8bfb1[225];gd9a8a3<=vx8bfb1[226];med451d<=vx8bfb1[227];fca28e9<=vx8bfb1[228];je1474b<=vx8bfb1[229];gqa3a5b<=vx8bfb1[230];sj1d2d9<=vx8bfb1[231];hbe96cd<=vx8bfb1[232];en4b66f<=vx8bfb1[233];qt5b37d<=vx8bfb1[234];mrd9bec<=vx8bfb1[235];hbcdf64<=vx8bfb1[236];of6fb27<=vx8bfb1[237];go7d93d<=vx8bfb1[238];fnec9e9<=vx8bfb1[239];ld64f4e<=vx8bfb1[240];db27a76<=vx8bfb1[241];vx3d3b7<=\r
+vx8bfb1[242];rte9dbe<=vx8bfb1[243];cz4edf6<=vx8bfb1[244];vi76fb4<=vx8bfb1[245];lsb7da2<=vx8bfb1[246];kfbed12<=vx8bfb1[247];hbf6894<=vx8bfb1[248];epb44a6<=vx8bfb1[249];fca2534<=vx8bfb1[250];gd129a2<=vx8bfb1[251];lf94d15<=vx8bfb1[252];swa68ae<=vx8bfb1[253];ie34571<=vx8bfb1[254];lsa2b88<=vx8bfb1[255];ec15c43<=vx8bfb1[256];qvae218<=vx8bfb1[257];vv710c4<=vx8bfb1[258];ks88626<=vx8bfb1[259];go43130<=vx8bfb1[260];cb18981<=vx8bfb1[261];cmc4c0c<=vx8bfb1[262];wl26061<=vx8bfb1[263];ls3030c<=vx8bfb1[264];lf81862<=vx8bfb1[265];rvc317<=vx8bfb1[266];nr618be<=vx8bfb1[267];tjc5f6<=vx8bfb1[268];ay62fb6<=vx8bfb1[269];wl17db1<=vx8bfb1[270];irbed8d<=vx8bfb1[271];rtf6c6c<=vx8bfb1[272];ecb6366<=vx8bfb1[273];kfb1b31<=vx8bfb1[274];ec8d98d<=vx8bfb1[275];ps6cc69<=vx8bfb1[276];lq6634a<=vx8bfb1[277];aa31a52<=vx8bfb1[278];co8d291<=vx8bfb1[279];vi69488<=vx8bfb1[280];nr4a443<=vx8bfb1[281];jc5221f<=vx8bfb1[282];fp910fa<=vx8bfb1[283];aa887d7<=vx8bfb1[284];ea43eb8<=vx8bfb1[285];gq1f5c0<=vx8bfb1[286];icfae00<=vx8bfb1[287];rtd7000<=vx8bfb1[288];pub8006<=vx8bfb1[289];tuc0032<=vx8bfb1[290];wy192<=vx8bfb1[291];ukc90<=vx8bfb1[292];lf6481<=vx8bfb1[293];rv3240f<=vx8bfb1[294];ie9207f<=vx8bfb1[295];wl903f8<=vx8bfb1[296];jr81fc5<=vx8bfb1[297];ymfe2f<=vx8bfb1[298];qt7f178<=vx8bfb1[299];gbf8bc5<=vx8bfb1[300];dmc5e2d<=vx8bfb1[301];do2f16b<=vx8bfb1[302];su78b5a<=vx8bfb1[303];tj2d68b<=vx8bfb1[304];zx5a2fe<=vx8bfb1[305];vic5ad1<=vx8bfb1[306];end\r
+always@* begin ead17f6[2047]<=of4e369;ead17f6[2046]<=th71b4d;ead17f6[2044]<=ym8da6f;ead17f6[2043]<=mgbc5df;ead17f6[2040]<=su6d379;ead17f6[2038]<=wje2ef8;ead17f6[2032]<=ne69bc9;ead17f6[2029]<=lfa007e;ead17f6[2017]<=vi4de4a;ead17f6[2013]<=db81b86;ead17f6[2010]<=irbbe2c;ead17f6[2003]<=ps5786e;ead17f6[1990]<=ec886a0;ead17f6[1987]<=wj6f253[0];ead17f6[1982]<=db9b94a;ead17f6[1980]<=ldf3bb1;ead17f6[1979]<=epdc37;ead17f6[1973]<=psdf164;ead17f6[1963]<=qtc9fa5;ead17f6[1958]<=cobc373;ead17f6[1957]<=go566e7;ead17f6[1953]<=phb520a;ead17f6[1942]<=hd8e0dd;ead17f6[1932]<=kq43500;ead17f6[1929]<=cme5ce2;ead17f6[1926]<=ps7929c[0];ead17f6[1923]<=lqda3b1;ead17f6[1921]<=ofe7900;ead17f6[1917]<=qtdca57;ead17f6[1914]<=ribdd56;ead17f6[1913]<=ie9dd8e;ead17f6[1911]<=rt6e1bd;ead17f6[1903]<=zz9edd8;ead17f6[1898]<=enf8b22;ead17f6[1879]<=jp4fd2d;ead17f6[1876]<=uxab07c;ead17f6[1872]<=cb8acc2;ead17f6[1868]<=tue1b98;ead17f6[1866]<=ecb3738;ead17f6[1863]<=an1245f;ead17f6[1858]<=oua9056;ead17f6[1837]<=of706ef;ead17f6[1816]<=gq1a801;ead17f6[1810]<=gq2e710;ead17f6[1805]<=eaffb08;ead17f6[1802]<=qi3ef84;ead17f6[1799]<=wwd1d8a;ead17f6[1795]<=ep3c805;ead17f6[1786]<=kqe52bc;ead17f6[1783]<=thd8f9d;ead17f6[1780]<=neeeab3;ead17f6[1778]<=zkeec70;ead17f6[1775]<=cz70dee;ead17f6[1770]<=ba1bc56;ead17f6[1758]<=ldf6ec7;ead17f6[1748]<=nec5915;ead17f6[1710]<=bl7e96e;ead17f6[1704]<=zk583e4;ead17f6[1701]<=mga32ec;ead17f6[1699]<=tj22ae7;ead17f6[1696]<=ui56614;ead17f6[1689]<=ohdcc2;ead17f6[1685]<=lf9b9c1;ead17f6[1679]<=vk2ff39;ead17f6[1678]<=ie922fc;ead17f6[1668]<=ho482b1;ead17f6[1627]<=hq8377c;ead17f6[1624]<=cm68afe;ead17f6[1605]<=sjae670;ead17f6[1589]<=dm476b4;ead17f6[1584]<=med4009;ead17f6[1573]<=rg73880;ead17f6[1572]<=ec31ecb;ead17f6[1567]<=kq5ca56;ead17f6[1562]<=kdfd840;ead17f6[1557]<=go78dad;ead17f6[1556]<=czf7c20;ead17f6[1551]<=fp8ec50;ead17f6[1548]<=ea49e16;ead17f6[1543]<=nee402d;ead17f6[1524]<=yz295e1;ead17f6[1521]<=sj2621a;ead17f6[1519]<=ldc7cee;ead17f6[1513]<=al7559b;ead17f6[1512]<=ec2ed48;ead17f6[1509]<=rg76383;ead17f6[1504]<=hd2768e;ead17f6[1502]<=tw86f75;ead17f6[1499]<=fa767b7;ead17f6[1493]<=th6eac1;ead17f6[1492]<=ykde2b3;ead17f6[1469]<=jeb763e;ead17f6[1466]<=rg7c6f1;ead17f6[1448]<=gd2c8ab;ead17f6[1421]<=lf3d1da;ead17f6[1417]<=ykf0c7b;ead17f6[1415]<=psf1729;ead17f6[1404]<=rg7c988;ead17f6[1402]<=iebcbb5;ead17f6[1400]<=ww4c9da;ead17f6[1398]<=jr2dd9e;ead17f6[1377]<=wje7c5c;ead17f6[1374]<=hbc2f2e;ead17f6[1373]<=lqf4b76;ead17f6[1361]<=icc1f23;ead17f6[1359]<=nee197b;ead17f6[1355]<=meea83a;ead17f6[1354]<=lf19760;ead17f6[1350]<=qi1573f;ead17f6[1349]<=dm7c8c8;ead17f6[1344]<=mgb30a0;ead17f6[1343]<=gb65ed7;ead17f6[1341]<=ng25393;ead17f6[1330]<=th6e615;ead17f6[1326]<=dba0e8d;ead17f6[1323]<=czdce0f;ead17f6[1322]<=fa5d838;ead17f6[1310]<=mr7f9cb;ead17f6[1308]<=xl917e0;ead17f6[1305]<=qg5cfcd;ead17f6[1301]<=kf2321b;ead17f6[1289]<=kd4158a;ead17f6[1286]<=med1ba0;ead17f6[1280]<=xjc2809;ead17f6[1279]<=jcdaf17;ead17f6[1271]<=qt4e4dc;ead17f6[1224]<=ie98573;ead17f6[1210]<=do3a375;ead17f6[1207]<=je1bbe3;ead17f6[1201]<=aa2bf86;ead17f6[1199]<=zz383e4;ead17f6[1195]<=yx60e17;ead17f6[1193]<=yz270c;ead17f6[1163]<=yk59be9;ead17f6[1162]<=jc73384;ead17f6[1155]<=sw92f;ead17f6[1144]<=kde72e7;ead17f6[1136]<=nr5f83e;ead17f6[1130]<=co3b5a3;ead17f6[1125]<=ng3f345;ead17f6[1120]<=hda0049;ead17f6[1112]<=os7d23d;ead17f6[1110]<=fnc86e7;ead17f6[1104]<=sh708d1;ead17f6[1098]<=fc9c402;ead17f6[1096]<=kf8f659;ead17f6[1086]<=ose52b0;ead17f6[1076]<=ldec205;ead17f6[1067]<=enc6d69;ead17f6[1065]<=qvbe104;ead17f6[1060]<=ui562a0;ead17f6[1054]<=tu76286;ead17f6[1053]<=ri25e58;ead17f6[1051]<=ld7400f;ead17f6[1048]<=rt4f0b1;ead17f6[1039]<=vk2016b;ead17f6[1026]<=nta0273;ead17f6[1023]<=ui49c6d[0];ead17f6[1021]<=nrd78bb;ead17f6[1006]<=xlb0370;ead17f6[1001]<=ld4af0d;ead17f6[995]<=ec310d4;ead17f6[991]<=zm93729;ead17f6[990]<=ks3e776;ead17f6[981]<=qtd93f4;ead17f6[978]<=bnaacdc;ead17f6[976]<=fa76a41;ead17f6[971]<=kfb1c1b;ead17f6[964]<=cb33973;ead17f6[961]<=uk3b476;ead17f6[960]<=ay5cf20;ead17f6[957]<=zz37baa;ead17f6[951]<=qib3dbb;ead17f6[938]<=wj7560f;ead17f6[936]<=xwf1598;ead17f6[931]<=jpc248b;ead17f6[901]<=cb7df0;ead17f6[891]<=yzbb1f3;ead17f6[885]<=lde378a;ead17f6[850]<=sjb465d;ead17f6[849]<=th6455c;ead17f6[839]<=co5fe7;ead17f6[812]<=nr457f0;ead17f6[802]<=ou15cce;ead17f6[794]<=ofe8ed6;ead17f6[786]<=ng863d9;ead17f6[783]<=rv8b94a;ead17f6[778]<=qv8f1b5;ead17f6[774]<=nt93c2;ead17f6[760]<=nee4c43;ead17f6[756]<=sue5da9;ead17f6[752]<=fn64ed1;ead17f6[749]<=rt6ecf6;ead17f6[746]<=ou8dd58;ead17f6[733]<=meef8de;ead17f6[710]<=by47a3b;ead17f6[708]<=zkfe18f;ead17f6[707]<=ou3e2e5;ead17f6[702]<=ief931;ead17f6[701]<=gd17976;ead17f6[700]<=xw6993b;ead17f6[699]<=pha5bb3;ead17f6[688]<=ofdcf8b;ead17f6[687]<=xl385e5;ead17f6[679]<=tw9c32f;ead17f6[677]<=lsbd507;ead17f6[674]<=qif919;ead17f6[671]<=tjcbda;ead17f6[670]<=ba4a72;ead17f6[663]<=sh541d1;ead17f6[661]<=aycbb07;ead17f6[652]<=mtab9f9;ead17f6[650]<=fae4643;ead17f6[643]<=aa1a374;ead17f6[640]<=uk98501;ead17f6[639]<=ng2f6bc;ead17f6[635]<=wl29c9b;ead17f6[612]<=rg730ae;ead17f6[605]<=qv746e;ead17f6[599]<=ene707c;ead17f6[597]<=dzec1c2;ead17f6[596]<=gd804e1;ead17f6[581]<=cmcb37d;ead17f6[577]<=dba0125;ead17f6[572]<=xjfce5c;ead17f6[568]<=rv8bf07;ead17f6[562]<=mre7e68;ead17f6[556]<=cz6fa47;ead17f6[555]<=vx190dc;ead17f6[552]<=osce11a;ead17f6[530]<=coac54;ead17f6[526]<=aa24bcb;ead17f6[525]<=aa8dd00;ead17f6[513]<=do1404e;ead17f6[510]<=xj7b5e2;ead17f6[503]<=ic5606e;ead17f6[495]<=go726e5;ead17f6[490]<=kd5b27e;ead17f6[482]<=ld50ce5;ead17f6[480]<=gocb9e4;ead17f6[465]<=ps58491;ead17f6[450]<=yke0fbe;ead17f6[425]<=uvd68cb;ead17f6[419]<=dz40bfc;ead17f6[406]<=dzcd15f;ead17f6[401]<=fnc2b99;ead17f6[389]<=db163c6;ead17f6[387]<=ls1278;ead17f6[373]<=ead1bab;ead17f6[366]<=nrddf1b;ead17f6[355]<=zk48f47;ead17f6[354]<=bl5fc31;ead17f6[351]<=uic1f26;ead17f6[350]<=doad327;ead17f6[344]<=tw1b9f1;ead17f6[343]<=cb70bc;ead17f6[339]<=rv13865;ead17f6[338]<=dzd7aa0;ead17f6[335]<=ls2094e;ead17f6[321]<=yz2346e;ead17f6[298]<=mg1009c;ead17f6[290]<=ipd966f;ead17f6[288]<=sh54024;ead17f6[278]<=zxcdf48;ead17f6[276]<=xy99c23;ead17f6[263]<=tw4979;ead17f6[251]<=hb4ac0d;ead17f6[245]<=fn6b64f;ead17f6[241]<=tw8672e;ead17f6[240]<=ux3973c;ead17f6[232]<=eacb092;ead17f6[225]<=thfc1f7;ead17f6[212]<=xwdad19;ead17f6[209]<=gd817f;ead17f6[203]<=jpf9a2b;ead17f6[194]<=irb1e36;ead17f6[193]<=ym24f;ead17f6[177]<=nre91e8;ead17f6[175]<=ntb5a64;ead17f6[172]<=su4373e;ead17f6[169]<=qgfaf54;ead17f6[167]<=lf84129;ead17f6[160]<=tj8468d;ead17f6[149]<=gbe2013;ead17f6[145]<=nr7b2cd;ead17f6[144]<=ir8a804;ead17f6[125]<=ep29581;ead17f6[122]<=hd2d6c9;ead17f6[120]<=an8a19c;ead17f6[116]<=xw79612;ead17f6[109]<=ld6e801;ead17f6[104]<=ld6102f;ead17f6[97]<=nrc2c78;ead17f6[87]<=ir36b4c;ead17f6[84]<=ux9f5ea;ead17f6[83]<=eaf0825;ead17f6[72]<=ohb1500;ead17f6[61]<=aa5ad9;ead17f6[60]<=anb1433;\r
+ead17f6[58]<=xy2f2c2;ead17f6[54]<=ec3f7;ead17f6[48]<=os7858f;ead17f6[42]<=jc73ebd;ead17f6[30]<=gqb5b;ead17f6[21]<=al4e7d7;ead17f6[10]<=ph9cfa;ead17f6[5]<=vk139f;end         assign jebdc77 = ead17f6,vx8bfb1 = fn71dda; initial begin kfbe35f = $fopen(".fred"); $fdisplay( kfbe35f, "%3h\n%3h", (fnf63ba >> 4) & fpbaf71, (fnf63ba >> (tj8eebd+4)) & fpbaf71 ); $fclose(kfbe35f); $readmemh(".fred", ay776be); end always @ (jebdc77) begin nedaf8d = ay776be[1]; for (jcf1afd=0; jcf1afd<th5fd8e; jcf1afd=jcf1afd+1) begin fn71dda[jcf1afd] = jebdc77[nedaf8d]; thd7c6b = ^(nedaf8d & ay776be[0]); nedaf8d = {nedaf8d, thd7c6b}; end end\r
+endmodule\r
+`timescale 1 ns / 100 ps\r
+module pf6bfe4 (rst_n,\r
+                  gbe_mode,\r
+                  zxfc9f8,\r
+                  zke4fc7,\r
+                  force_isolate,\r
+                  fc3f1d7,\r
+                  wjf8ebb,\r
+                  dzc75dd,\r
+                  do3aeef,\r
+                  dzd777a,\r
+                  irbbbd6,\r
+                  rtddeb4\r
+                 );\r
+input                rst_n;\r
+input                gbe_mode;\r
+input                zxfc9f8;\r
+input  [1:0]         zke4fc7;\r
+input                force_isolate;\r
+input  [7:0]         fc3f1d7;\r
+input                wjf8ebb;\r
+input                dzc75dd;\r
+input                do3aeef;\r
+output  [7:0]        dzd777a;\r
+output               irbbbd6;\r
+output               rtddeb4;\r
+reg  [7:0]           dzd777a;\r
+reg                  irbbbd6;\r
+reg                  rtddeb4;\r
+reg [1:0] thc8030;\r
+reg [1:0] dz40186;\r
+reg [1:0] ymc36;\r
+reg [1:0] rv61b1;\r
+reg [1:0] ls30d8f;\r
+reg [1:0] ng86c7b;\r
+reg cb363da;\r
+reg uxb1ed5;\r
+reg ir8f6ad;\r
+reg xj7b56d;\r
+reg [7:0] jcdab6f;\r
+reg lqd5b7b;\r
+reg twadbda;\r
+reg [7:0] qg6ded2;\r
+reg uv6f690;\r
+reg bl7b484;\r
+reg [7:0] psda427;\r
+reg fnd213a;\r
+reg yz909d6;\r
+reg vx84eb4;\r
+wire tj275a7;\r
+wire ng3ad3e;\r
+wire [7:0] end69f2;\r
+wire uxb4f95;\r
+reg hqa7cad;\r
+reg ym3e56b;\r
+reg shf2b59;\r
+reg oh95acc;\r
+reg riad664;\r
+reg hb6b323;\r
+reg yk5991e;\r
+reg yxcc8f0;\r
+reg [6:0] vv64785;\r
+reg ir23c2f;\r
+reg hq1e17d;\r
+reg qgf0bea;\r
+reg cb85f51;\r
+reg vk2fa8d;\r
+reg kq7d46b;\r
+reg eaea358;\r
+reg cz51ac0;\r
+reg ym8d604;\r
+`ifdef SGMII_FIFO_FAMILY_SC\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP2M\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP3\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP5\r
+`endif\r
+reg rt6b020;\r
+reg [1 : 0] by58106;\r
+reg zkc0833;\r
+reg [7 : 0] xy419b;\r
+reg do20cda;\r
+reg rv66d2;\r
+reg [1 : 0] mt33697;\r
+reg [1 : 0] xl9b4bd;\r
+reg [1 : 0] psda5ee;\r
+reg [1 : 0] fnd2f72;\r
+reg [1 : 0] aa97b97;\r
+reg [1 : 0] ngbdcb9;\r
+reg hoee5cb;\r
+reg yk72e5a;\r
+reg ie972d0;\r
+reg ukb9680;\r
+reg [7 : 0] gocb400;\r
+reg hb5a001;\r
+reg rgd000e;\r
+reg [7 : 0] ux80073;\r
+reg ec39c;\r
+reg hq1ce0;\r
+reg [7 : 0] jee703;\r
+reg dm7381b;\r
+reg xy9c0da;\r
+reg sue06d3;\r
+reg lf3699;\r
+reg pu1b4cf;\r
+reg [7 : 0] dmda67a;\r
+reg mrd33d2;\r
+reg ba99e94;\r
+reg vicf4a2;\r
+reg wj7a513;\r
+reg dzd289d;\r
+reg nt944ef;\r
+reg nga277f;\r
+reg tj13bfa;\r
+reg ie9dfd7;\r
+reg [6 : 0] ykefeb8;\r
+reg kd7f5c1;\r
+reg icfae0d;\r
+reg rtd7068;\r
+reg pub8346;\r
+reg suc1a32;\r
+reg uxd191;\r
+reg ic68c8c;\r
+reg go46460;\r
+reg db32301;\r
+reg [2047:0] ead17f6;\r
+wire [47:0] vx8bfb1;\r
+`ifdef SGMII_FIFO_FAMILY_SC\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP2M\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP3\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP5\r
+`endif\r
+localparam th5fd8e = 48,nefec77 = 32'hfdffca8b;\r
+localparam [31:0] fnf63ba = nefec77;\r
+localparam tj8eebd = nefec77 & 4'hf;\r
+localparam [11:0] fpbaf71 = 'h7ff;\r
+wire [(1 << tj8eebd) -1:0] jebdc77;\r
+reg [th5fd8e-1:0] fn71dda;\r
+reg [tj8eebd-1:0] ay776be [0:1];\r
+reg [tj8eebd-1:0] nedaf8d;\r
+reg thd7c6b;\r
+integer kfbe35f;\r
+integer jcf1afd;\r
+`ifdef SGMII_FIFO_FAMILY_SC\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP2M\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP3\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP5\r
+`endif\r
+always @(posedge zxfc9f8 or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        shf2b59 <= 1'd1;        oh95acc <= 1'd1;        end     else begin              shf2b59 <= vicf4a2;     oh95acc <= wj7a513;     end\r
+end\r
+always @(posedge zxfc9f8 or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        riad664 <= 1'd1;        hb6b323 <= 1'd1;        end     else begin              riad664 <= yk72e5a;     hb6b323 <= nt944ef;     end\r
+end\r
+always @(posedge zxfc9f8 or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        cz51ac0 <= 1'b0;        ym8d604 <= 1'b0;        end     else begin      cz51ac0 <= zkc0833;     ym8d604 <= go46460;     end\r
+end\r
+always @(posedge zxfc9f8 or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        lqd5b7b <= 1'b0;        twadbda <= 1'b0;        jcdab6f <= 8'd0;        uv6f690 <= 1'b0;        bl7b484 <= 1'b0;        qg6ded2 <= 8'd0;        fnd213a <= 1'b0;        yz909d6 <= 1'b0;        psda427 <= 8'd0;        vx84eb4 <= 1'b0;        end     else begin              if (db32301) begin      jcdab6f <= 8'd0;        twadbda <= 1'b0;        lqd5b7b <= 1'b0;        end     else begin      jcdab6f <= xy419b;      twadbda <= rv66d2;      lqd5b7b <= do20cda;     end             qg6ded2 <= gocb400;     bl7b484 <= rgd000e;     uv6f690 <= hb5a001;\r
+               if (dzd289d) begin      vx84eb4 <= 1'b0;        end     else if (((rgd000e==1'd1)  && (hq1ce0==1'd0)) || (nga277f ==1'd1))      vx84eb4 <= 1'b1;        else    vx84eb4 <= (~sue06d3);          if (sue06d3) begin      psda427[3:0] <= ux80073[3:0];   yz909d6 <= hq1ce0;      fnd213a <= ec39c;       if (nga277f) begin      psda427[7:4] <= ux80073[7:4];   end     else begin      psda427[7:4] <= gocb400[3:0];                   end     end     end\r
+end\r
+`ifdef SGMII_FIFO_FAMILY_SC\r
+       pmi_fifo_dc #(  .pmi_data_width_w(10),  .pmi_data_width_r(10),  .pmi_data_depth_w(8),  .pmi_data_depth_r(8),  .pmi_full_flag(8),  .pmi_empty_flag(0),  .pmi_almost_full_flag(3),  .pmi_almost_empty_flag(1),  .pmi_regmode("no_reg"),  .pmi_resetmode("async"),  .pmi_family("SC"),  .module_type("pmi_fifo_dc"),  .pmi_implementation("LUT")) wl39c71 (        .Reset(oh95acc),        .RPReset(oh95acc),      .WrClock(zxfc9f8),      .WrEn(vx84eb4), .Data({fnd213a, yz909d6, psda427}),\r
+       .RdClock(do3aeef),      .RdEn(hqa7cad), .Q({tj275a7, ng3ad3e, end69f2}),\r
+       .Empty(uxb4f95),        .Full(),        .AlmostEmpty(), .AlmostFull()   );\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP2M\r
+       pmi_fifo_dc #(  .pmi_data_width_w(10),  .pmi_data_width_r(10),  .pmi_data_depth_w(8),  .pmi_data_depth_r(8),  .pmi_full_flag(8),  .pmi_empty_flag(0),  .pmi_almost_full_flag(3),  .pmi_almost_empty_flag(1),  .pmi_regmode("no_reg"),  .pmi_resetmode("async"),  .pmi_family("ECP2M"),  .module_type("pmi_fifo_dc"),  .pmi_implementation("LUT")) wl39c71 (     .Reset(oh95acc),        .RPReset(oh95acc),      .WrClock(zxfc9f8),      .WrEn(vx84eb4), .Data({fnd213a, yz909d6, psda427}),\r
+       .RdClock(do3aeef),      .RdEn(hqa7cad), .Q({tj275a7, ng3ad3e, end69f2}),\r
+       .Empty(uxb4f95),        .Full(),        .AlmostEmpty(), .AlmostFull()   );\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP3\r
+       pmi_fifo_dc #(  .pmi_data_width_w(10),  .pmi_data_width_r(10),  .pmi_data_depth_w(8),  .pmi_data_depth_r(8),  .pmi_full_flag(8),  .pmi_empty_flag(0),  .pmi_almost_full_flag(3),  .pmi_almost_empty_flag(1),  .pmi_regmode("no_reg"),  .pmi_resetmode("async"),  .pmi_family("ECP3"),  .module_type("pmi_fifo_dc"),  .pmi_implementation("LUT")) wl39c71 (      .Reset(oh95acc),        .RPReset(oh95acc),      .WrClock(zxfc9f8),      .WrEn(vx84eb4), .Data({fnd213a, yz909d6, psda427}),\r
+       .RdClock(do3aeef),      .RdEn(hqa7cad), .Q({tj275a7, ng3ad3e, end69f2}),\r
+       .Empty(uxb4f95),        .Full(),        .AlmostEmpty(), .AlmostFull()   );\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP5\r
+       pmi_fifo_dc #(  .pmi_data_width_w(10),  .pmi_data_width_r(10),  .pmi_data_depth_w(8),  .pmi_data_depth_r(8),  .pmi_full_flag(8),  .pmi_empty_flag(0),  .pmi_almost_full_flag(3),  .pmi_almost_empty_flag(1),  .pmi_regmode("no_reg"),  .pmi_resetmode("async"),  .pmi_family("ECP5UM"),  .module_type("pmi_fifo_dc"),  .pmi_implementation("LUT")) wl39c71 (    .Reset(oh95acc),        .RPReset(oh95acc),      .WrClock(zxfc9f8),      .WrEn(vx84eb4), .Data({fnd213a, yz909d6, psda427}),\r
+       .RdClock(do3aeef),      .RdEn(hqa7cad), .Q({tj275a7, ng3ad3e, end69f2}),\r
+       .Empty(uxb4f95),        .Full(),        .AlmostEmpty(), .AlmostFull()   );\r
+`endif\r
+always @(posedge do3aeef or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        hq1e17d <= 1'b0;        qgf0bea <= 1'b0;        cb85f51 <= 1'b0;        vk2fa8d <= 1'b0;        kq7d46b <= 1'b0;        eaea358 <= 1'b0;        end     else begin              hq1e17d <= rt6b020;     qgf0bea <= icfae0d;\r
+               cb85f51 <= rtd7068;             vk2fa8d <= rtd7068 & (~pub8346);                kq7d46b <= ~rtd7068 & (pub8346);                eaea358 <= suc1a32 || uxd191;   end\r
+end\r
+always @(posedge do3aeef or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        thc8030 <= 2'd0;        dz40186 <= 2'd0;        ymc36 <= 2'd0;  rv61b1 <= 2'd0; ls30d8f <= 2'd0;        ng86c7b <= 2'd0;        cb363da <= 1'b0;        uxb1ed5 <= 1'b0;        ir8f6ad <= 1'b0;        xj7b56d <= 1'b0;        end     else begin              thc8030 <= by58106;             dz40186 <= mt33697;     ymc36 <= xl9b4bd;       rv61b1 <= psda5ee;      if ((xl9b4bd==psda5ee) && (xl9b4bd==fnd2f72))   ls30d8f <= fnd2f72;     ng86c7b <= aa97b97;             if (ic68c8c)    cb363da <= 1'b1;        else if (aa97b97 != ngbdcb9)    cb363da <= 1'b1;        else    cb363da <= 1'b0;                if (pub8346) begin      uxb1ed5    <=  1'b1;    ir8f6ad  <=  1'b0;      xj7b56d   <=  1'b0;     end     else begin      uxb1ed5    <=   aa97b97[1];     ir8f6ad  <=  !aa97b97[1]  & ( aa97b97[0]);      xj7b56d   <=  !aa97b97[1]  & (!aa97b97[0]);     end\r
+               case (tj13bfa)  1'd0: begin     if (hoee5cb) begin      ym3e56b <= 1'b1;        yk5991e <= 1'd1;        end     else begin      ym3e56b <= 1'b0;        yk5991e <= 1'd0;        end     end     1'd1: begin     ym3e56b <= 1'b1;        if (ie9dfd7) begin      yk5991e <= 1'd0;        end     else begin      yk5991e <= 1'd1;        end     end     default: begin  yk5991e <= 1'd0;        end     endcase\r
+       end\r
+end\r
+always @(posedge do3aeef or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        vv64785 <= 7'd0;        ir23c2f <= 1'b0;        end     else begin              if (hoee5cb || kd7f5c1) begin   vv64785 <= 7'd0;        end     else begin      vv64785 <= ykefeb8 + 1; end\r
+               if (hoee5cb) begin      ir23c2f <= 1'b0;        end     else if (ie972d0) begin         if (ykefeb8 == 7'd8) begin      ir23c2f <= 1'b1;        end     else begin      ir23c2f <= 1'b0;        end     end     else if (ukb9680) begin         if (ykefeb8 == 7'd98) begin     ir23c2f <= 1'b1;        end     else begin      ir23c2f <= 1'b0;        end     end     else begin              ir23c2f <= 1'b1;        end     end\r
+end\r
+always @(posedge do3aeef or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        yxcc8f0 <= 1'b0;        end     else begin      if (hoee5cb) begin      yxcc8f0 <=  1'b0;       end     else if (ie972d0) begin         if (ykefeb8 == 7'd3) begin      yxcc8f0 <=  1'b1;       end     else begin      yxcc8f0 <=  1'b0;       end     end     else if (ukb9680) begin         if (ykefeb8 == 7'd49) begin     yxcc8f0 <=  1'b1;       end     else begin      yxcc8f0 <=  1'b0;       end     end     else begin              yxcc8f0 <=  1'b1;       end     end\r
+end\r
+always @(posedge do3aeef or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        hqa7cad <= 1'b0;        end     else begin      if (vicf4a2) begin      hqa7cad <= 1'b0;        end     else if (!mrd33d2 && ie9dfd7) begin     hqa7cad <= 1'b1;        end     else begin      hqa7cad <= 1'b0;        end     end\r
+end\r
+always @(posedge do3aeef or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        dzd777a <= 8'd0;        irbbbd6 <= 1'd0;        rtddeb4 <= 1'd0;        end     else begin      dzd777a <= dmda67a;     irbbbd6 <= lf3699;      rtddeb4 <= pu1b4cf;     end\r
+end\r
+always@* begin rt6b020<=vx8bfb1[0];by58106<={zke4fc7>>1,vx8bfb1[1]};zkc0833<=vx8bfb1[2];xy419b<={fc3f1d7>>1,vx8bfb1[3]};do20cda<=vx8bfb1[4];rv66d2<=vx8bfb1[5];mt33697<={thc8030>>1,vx8bfb1[6]};xl9b4bd<={dz40186>>1,vx8bfb1[7]};psda5ee<={ymc36>>1,vx8bfb1[8]};fnd2f72<={rv61b1>>1,vx8bfb1[9]};aa97b97<={ls30d8f>>1,vx8bfb1[10]};ngbdcb9<={ng86c7b>>1,vx8bfb1[11]};hoee5cb<=vx8bfb1[12];yk72e5a<=vx8bfb1[13];ie972d0<=vx8bfb1[14];ukb9680<=vx8bfb1[15];gocb400<={jcdab6f>>1,vx8bfb1[16]};hb5a001<=vx8bfb1[17];rgd000e<=vx8bfb1[18];ux80073<={qg6ded2>>1,vx8bfb1[19]};ec39c<=vx8bfb1[20];hq1ce0<=vx8bfb1[21];jee703<={psda427>>1,vx8bfb1[22]};dm7381b<=vx8bfb1[23];xy9c0da<=vx8bfb1[24];sue06d3<=vx8bfb1[25];lf3699<=vx8bfb1[26];pu1b4cf<=vx8bfb1[27];dmda67a<={end69f2>>1,vx8bfb1[28]};mrd33d2<=vx8bfb1[29];ba99e94<=vx8bfb1[30];vicf4a2<=vx8bfb1[31];wj7a513<=vx8bfb1[32];dzd289d<=vx8bfb1[33];nt944ef<=vx8bfb1[34];nga277f<=vx8bfb1[35];tj13bfa<=vx8bfb1[36];ie9dfd7<=vx8bfb1[37];ykefeb8<={vv64785>>1,vx8bfb1[38]};kd7f5c1<=vx8bfb1[39];icfae0d<=vx8bfb1[40];rtd7068<=vx8bfb1[41];pub8346<=vx8bfb1[42];suc1a32<=vx8bfb1[43];uxd191<=vx8bfb1[44];ic68c8c<=vx8bfb1[45];go46460<=vx8bfb1[46];db32301<=vx8bfb1[47];end\r
+always@* begin ead17f6[2047]<=zke4fc7[0];ead17f6[2046]<=force_isolate;ead17f6[2044]<=fc3f1d7[0];ead17f6[2040]<=wjf8ebb;ead17f6[2032]<=dzc75dd;ead17f6[2017]<=thc8030[0];ead17f6[1987]<=dz40186[0];ead17f6[1926]<=ymc36[0];ead17f6[1805]<=hb6b323;ead17f6[1804]<=rv61b1[0];ead17f6[1803]<=fnd213a;ead17f6[1761]<=shf2b59;ead17f6[1668]<=cb85f51;ead17f6[1562]<=yk5991e;ead17f6[1560]<=ls30d8f[0];ead17f6[1558]<=yz909d6;ead17f6[1550]<=jcdab6f[0];ead17f6[1475]<=oh95acc;ead17f6[1464]<=hqa7cad;ead17f6[1288]<=vk2fa8d;ead17f6[1076]<=yxcc8f0;ead17f6[1072]<=ng86c7b[0];ead17f6[1069]<=vx84eb4;ead17f6[1056]<=eaea358;ead17f6[1052]<=lqd5b7b;ead17f6[1023]<=gbe_mode;ead17f6[902]<=riad664;ead17f6[901]<=psda427[0];ead17f6[880]<=ym3e56b;ead17f6[834]<=qgf0bea;ead17f6[775]<=xj7b56d;ead17f6[732]<=uxb4f95;ead17f6[528]<=kq7d46b;ead17f6[450]<=bl7b484;ead17f6[417]<=hq1e17d;ead17f6[387]<=ir8f6ad;ead17f6[366]<=end69f2[0];ead17f6[225]<=uv6f690;ead17f6[208]<=ir23c2f;ead17f6[193]<=uxb1ed5;ead17f6[183]<=ng3ad3e;ead17f6[128]<=ym8d604;ead17f6[112]<=qg6ded2[0];ead17f6[104]<=vv64785[0];ead17f6[96]<=cb363da;ead17f6[91]<=tj275a7;ead17f6[64]<=cz51ac0;ead17f6[56]<=twadbda;end         assign jebdc77 = ead17f6,vx8bfb1 = fn71dda; initial begin kfbe35f = $fopen(".fred"); $fdisplay( kfbe35f, "%3h\n%3h", (fnf63ba >> 4) & fpbaf71, (fnf63ba >> (tj8eebd+4)) & fpbaf71 ); $fclose(kfbe35f); $readmemh(".fred", ay776be); end always @ (jebdc77) begin nedaf8d = ay776be[1]; for (jcf1afd=0; jcf1afd<th5fd8e; jcf1afd=jcf1afd+1) begin fn71dda[jcf1afd] = jebdc77[nedaf8d]; thd7c6b = ^(nedaf8d & ay776be[0]); nedaf8d = {nedaf8d, thd7c6b}; end end\r
+endmodule\r
+`timescale 1 ns / 100 ps\r
+module gq2bcea (rst_n,\r
+                  gbe_mode,\r
+                  force_isolate,\r
+                  zxfc9f8,\r
+                  fc3f1d7,\r
+                  wjf8ebb,\r
+                  dzc75dd,\r
+                  ym3111a,\r
+                  ie888d0,\r
+                  do3aeef,\r
+                  wl2340c,\r
+                  dzd777a,\r
+                  irbbbd6,\r
+                  rtddeb4,\r
+                  vxc81f,\r
+                  xj640ff\r
+                 );\r
+input                rst_n;\r
+input                gbe_mode;\r
+input                force_isolate;\r
+input                zxfc9f8;\r
+input  [7:0]         fc3f1d7;\r
+input                wjf8ebb;\r
+input                dzc75dd;\r
+input                ym3111a;\r
+input                ie888d0;\r
+input                do3aeef;\r
+input  [1:0]         wl2340c;\r
+output  [7:0]        dzd777a;\r
+output               irbbbd6;\r
+output               rtddeb4;\r
+output               vxc81f;\r
+output               xj640ff;\r
+reg [7:0] dzd777a;\r
+reg irbbbd6;\r
+reg rtddeb4;\r
+reg vxc81f;\r
+reg xj640ff;\r
+reg [1:0] thc8030;\r
+reg [1:0] dz40186;\r
+reg [1:0] ymc36;\r
+reg [1:0] rv61b1;\r
+reg [1:0] ls30d8f;\r
+reg [1:0] ng86c7b;\r
+reg cb363da;\r
+reg uxb1ed5;\r
+reg ir8f6ad;\r
+reg xj7b56d;\r
+reg ym3e56b;\r
+reg shf2b59;\r
+reg qi31243;\r
+reg yxcc8f0;\r
+reg [6:0] vv64785;\r
+reg ir23c2f;\r
+reg me43082;\r
+reg yz18411;\r
+reg hqa7cad;\r
+reg [7:0] jcdab6f;\r
+reg twadbda;\r
+reg lqd5b7b;\r
+reg uk8de4a;\r
+reg of6f251;\r
+wire [7:0] end69f2;\r
+wire ng3ad3e;\r
+wire tj275a7;\r
+wire mr518a7;\r
+wire ba8c53c;\r
+reg [7:0] me629e2;\r
+reg ng14f11;\r
+reg jea788a;\r
+reg qv3c453;\r
+reg cze229c;\r
+reg yk5991e;\r
+reg riad664;\r
+reg ww5391d;\r
+reg hq1e17d;\r
+reg qgf0bea;\r
+reg cb85f51;\r
+reg vk2fa8d;\r
+reg kq7d46b;\r
+reg eaea358;\r
+reg cz51ac0;\r
+reg ym8d604;\r
+`ifdef SGMII_FIFO_FAMILY_SC\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP2M\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP3\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP5\r
+`endif\r
+reg rt6b020;\r
+reg zkc0833;\r
+reg [7 : 0] xy419b;\r
+reg do20cda;\r
+reg rv66d2;\r
+reg gb44b77;\r
+reg ba25bbd;\r
+reg [1 : 0] bn2ddea;\r
+reg [1 : 0] mt33697;\r
+reg [1 : 0] xl9b4bd;\r
+reg [1 : 0] psda5ee;\r
+reg [1 : 0] fnd2f72;\r
+reg [1 : 0] aa97b97;\r
+reg [1 : 0] ngbdcb9;\r
+reg hoee5cb;\r
+reg yk72e5a;\r
+reg ie972d0;\r
+reg ukb9680;\r
+reg vicf4a2;\r
+reg wj7a513;\r
+reg xjd76af;\r
+reg ie9dfd7;\r
+reg [6 : 0] ykefeb8;\r
+reg kd7f5c1;\r
+reg fpafd5a;\r
+reg pf7ead7;\r
+reg ba99e94;\r
+reg [7 : 0] gocb400;\r
+reg rgd000e;\r
+reg hb5a001;\r
+reg sjbe13f;\r
+reg uif09fd;\r
+reg [7 : 0] dmda67a;\r
+reg pu1b4cf;\r
+reg lf3699;\r
+reg czfd3fa;\r
+reg vve9fd4;\r
+reg [7 : 0] jp4fea6;\r
+reg al7f536;\r
+reg gofa9b5;\r
+reg ykd4da8;\r
+reg swa6d40;\r
+reg tj13bfa;\r
+reg nt944ef;\r
+reg xya8066;\r
+reg icfae0d;\r
+reg rtd7068;\r
+reg pub8346;\r
+reg suc1a32;\r
+reg uxd191;\r
+reg ic68c8c;\r
+reg go46460;\r
+reg db32301;\r
+reg [2047:0] ead17f6;\r
+wire [52:0] vx8bfb1;\r
+`ifdef SGMII_FIFO_FAMILY_SC\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP2M\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP3\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP5\r
+`endif\r
+localparam th5fd8e = 53,nefec77 = 32'hfdffe06b;\r
+localparam [31:0] fnf63ba = nefec77;\r
+localparam tj8eebd = nefec77 & 4'hf;\r
+localparam [11:0] fpbaf71 = 'h7ff;\r
+wire [(1 << tj8eebd) -1:0] jebdc77;\r
+reg [th5fd8e-1:0] fn71dda;\r
+reg [tj8eebd-1:0] ay776be [0:1];\r
+reg [tj8eebd-1:0] nedaf8d;\r
+reg thd7c6b;\r
+integer kfbe35f;\r
+integer jcf1afd;\r
+`ifdef SGMII_FIFO_FAMILY_SC\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP2M\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP3\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP5\r
+`endif\r
+always @(posedge zxfc9f8 or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        hq1e17d <= 1'b0;        qgf0bea <= 1'b0;        cb85f51 <= 1'b0;        vk2fa8d <= 1'b0;        kq7d46b <= 1'b0;        eaea358 <= 1'b0;        end     else begin              hq1e17d <= rt6b020;     qgf0bea <= icfae0d;\r
+               cb85f51 <= rtd7068;             vk2fa8d <= rtd7068 & (~pub8346);                kq7d46b <= ~rtd7068 & (pub8346);                eaea358 <= suc1a32 || uxd191;   end\r
+end\r
+always @(posedge zxfc9f8 or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        thc8030 <= 2'd0;        dz40186 <= 2'd0;        ymc36 <= 2'd0;  rv61b1 <= 2'd0; ls30d8f <= 2'd0;        ng86c7b <= 2'd0;        cb363da <= 1'b1;        uxb1ed5 <= 1'b0;        ir8f6ad <= 1'b0;        xj7b56d <= 1'b0;        end     else begin              thc8030 <= bn2ddea;             dz40186 <= mt33697;     ymc36 <= xl9b4bd;       rv61b1 <= psda5ee;      if ((xl9b4bd==psda5ee) && (xl9b4bd==fnd2f72))   ls30d8f <= fnd2f72;     ng86c7b <= aa97b97;             if (ic68c8c)    cb363da <= 1'b1;        else if (aa97b97 != ngbdcb9)    cb363da <= 1'b1;        else    cb363da <= 1'b0;                if (pub8346) begin      uxb1ed5    <=  1'b1;    ir8f6ad  <=  1'b0;      xj7b56d   <=  1'b0;     end     else begin      uxb1ed5    <=   aa97b97[1];     ir8f6ad  <=  !aa97b97[1]  & ( aa97b97[0]);      xj7b56d   <=  !aa97b97[1]  & (!aa97b97[0]);     end             case (tj13bfa)  1'd0: begin     if (hoee5cb) begin      ym3e56b <= 1'b1;        yk5991e <= 1'd1;        end     else begin      ym3e56b <= 1'b0;        yk5991e <= 1'd0;        end     end     1'd1: begin     ym3e56b <= 1'b1;        if (ie9dfd7) begin      yk5991e <= 1'd0;        end     else begin      yk5991e <= 1'd1;        end     end     default: begin  yk5991e <= 1'd0;        end     endcase end\r
+end\r
+always @(posedge zxfc9f8 or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        vv64785 <= 7'd0;        ir23c2f <= 1'b0;        end     else begin              if (hoee5cb || kd7f5c1) begin   vv64785 <= 7'd0;        end     else begin      vv64785 <= ykefeb8 + 1; end\r
+               if (hoee5cb) begin      ir23c2f <= 1'b0;        end     else if (ie972d0) begin         if (ykefeb8 == 7'd8) begin      ir23c2f <= 1'b1;        end     else begin      ir23c2f <= 1'b0;        end     end     else if (ukb9680) begin         if (ykefeb8 == 7'd98) begin     ir23c2f <= 1'b1;        end     else begin      ir23c2f <= 1'b0;        end     end     else begin              ir23c2f <= 1'b1;        end     end\r
+end\r
+always @(posedge zxfc9f8 or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        yxcc8f0 <= 1'b0;        end     else begin      if (hoee5cb) begin      yxcc8f0 <=  1'b0;       end     else if (ie972d0) begin         if (ykefeb8 == 7'd3) begin      yxcc8f0 <=  1'b1;       end     else begin      yxcc8f0 <=  1'b0;       end     end     else if (ukb9680) begin         if (ykefeb8 == 7'd49) begin     yxcc8f0 <=  1'b1;       end     else begin      yxcc8f0 <=  1'b0;       end     end     else begin              yxcc8f0 <=  1'b1;       end     end\r
+end\r
+always @(posedge zxfc9f8 or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        lqd5b7b <= 0;   twadbda <= 0;   uk8de4a <= 0;   of6f251 <= 0;   jcdab6f <= 8'd0;        end     else begin              jcdab6f <= xy419b;      twadbda <= rv66d2;      lqd5b7b <= do20cda;     uk8de4a <= gb44b77;     of6f251 <= ba25bbd;     end\r
+end\r
+`ifdef SGMII_FIFO_FAMILY_SC\r
+       pmi_fifo_dc #(  .pmi_data_width_w(12),  .pmi_data_width_r(12),  .pmi_data_depth_w(8),  .pmi_data_depth_r(8),  .pmi_full_flag(8),  .pmi_empty_flag(0),  .pmi_almost_full_flag(3),  .pmi_almost_empty_flag(1),  .pmi_regmode("no_reg"),  .pmi_resetmode("async"),  .pmi_family("SC"),  .module_type("pmi_fifo_dc"),  .pmi_implementation("LUT")) icc1bfd (        .Reset(qi31243),        .RPReset(qi31243),      .WrClock(zxfc9f8),      .WrEn(yxcc8f0), .Data({of6f251, uk8de4a, lqd5b7b, twadbda, jcdab6f}),\r
+       .RdClock(do3aeef),      .RdEn(hqa7cad), .Q({ba8c53c, mr518a7, tj275a7, ng3ad3e, end69f2}),\r
+       .Empty(uxb4f95),        .Full(),        .AlmostEmpty(), .AlmostFull()   );\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP2M\r
+       pmi_fifo_dc #(  .pmi_data_width_w(12),  .pmi_data_width_r(12),  .pmi_data_depth_w(8),  .pmi_data_depth_r(8),  .pmi_full_flag(8),  .pmi_empty_flag(0),  .pmi_almost_full_flag(3),  .pmi_almost_empty_flag(1),  .pmi_regmode("no_reg"),  .pmi_resetmode("async"),  .pmi_family("ECP2M"),  .module_type("pmi_fifo_dc"),  .pmi_implementation("LUT")) icc1bfd (     .Reset(qi31243),        .RPReset(qi31243),      .WrClock(zxfc9f8),      .WrEn(yxcc8f0), .Data({of6f251, uk8de4a, lqd5b7b, twadbda, jcdab6f}),\r
+       .RdClock(do3aeef),      .RdEn(hqa7cad), .Q({ba8c53c, mr518a7, tj275a7, ng3ad3e, end69f2}),\r
+       .Empty(uxb4f95),        .Full(),        .AlmostEmpty(), .AlmostFull()   );\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP3\r
+       pmi_fifo_dc #(  .pmi_data_width_w(12),  .pmi_data_width_r(12),  .pmi_data_depth_w(8),  .pmi_data_depth_r(8),  .pmi_full_flag(8),  .pmi_empty_flag(0),  .pmi_almost_full_flag(3),  .pmi_almost_empty_flag(1),  .pmi_regmode("no_reg"),  .pmi_resetmode("async"),  .pmi_family("ECP3"),  .module_type("pmi_fifo_dc"),  .pmi_implementation("LUT")) icc1bfd (      .Reset(qi31243),        .RPReset(qi31243),      .WrClock(zxfc9f8),      .WrEn(yxcc8f0), .Data({of6f251, uk8de4a, lqd5b7b, twadbda, jcdab6f}),\r
+       .RdClock(do3aeef),      .RdEn(hqa7cad), .Q({ba8c53c, mr518a7, tj275a7, ng3ad3e, end69f2}),\r
+       .Empty(uxb4f95),        .Full(),        .AlmostEmpty(), .AlmostFull()   );\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP5\r
+       pmi_fifo_dc #(  .pmi_data_width_w(12),  .pmi_data_width_r(12),  .pmi_data_depth_w(8),  .pmi_data_depth_r(8),  .pmi_full_flag(8),  .pmi_empty_flag(0),  .pmi_almost_full_flag(3),  .pmi_almost_empty_flag(1),  .pmi_regmode("no_reg"),  .pmi_resetmode("async"),  .pmi_family("ECP5UM"),  .module_type("pmi_fifo_dc"),  .pmi_implementation("LUT")) icc1bfd (    .Reset(qi31243),        .RPReset(qi31243),      .WrClock(zxfc9f8),      .WrEn(yxcc8f0), .Data({of6f251, uk8de4a, lqd5b7b, twadbda, jcdab6f}),\r
+       .RdClock(do3aeef),      .RdEn(hqa7cad), .Q({ba8c53c, mr518a7, tj275a7, ng3ad3e, end69f2}),\r
+       .Empty(uxb4f95),        .Full(),        .AlmostEmpty(), .AlmostFull()   );\r
+`endif\r
+always @(posedge do3aeef or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        shf2b59 <= 1'd1;        qi31243 <= 1'd1;        end     else begin              shf2b59 <= vicf4a2;     qi31243 <= wj7a513;     end\r
+end\r
+always @(posedge do3aeef or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        riad664 <= 1'd1;        ww5391d <= 1'd1;        end     else begin              riad664 <= yk72e5a;     ww5391d <= nt944ef;     end\r
+end\r
+always @(posedge do3aeef or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        me43082 <= 1'b0;        yz18411 <= 1'b0;        end     else begin  if (xjd76af) begin  me43082 <= 1'b0;  end  else begin       if (xya8066) begin      me43082 <= 1'b1;        end     else begin      me43082 <= ~fpafd5a;    end  end\r
+    yz18411 <= fpafd5a;\r
+       end\r
+end\r
+always @(posedge do3aeef or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        hqa7cad <= 1'b0;        end     else begin  if (xjd76af) begin  hqa7cad <= 1'b0;  end  else begin       if (!uxb4f95 && fpafd5a) begin  hqa7cad <= 1'b1;        end     else begin      hqa7cad <= 1'b0;        end  end        end\r
+end\r
+always @(posedge do3aeef or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        jea788a <= 0;   ng14f11 <= 0;   qv3c453 <= 0;   cze229c <= 0;   me629e2 <= 8'd0;        end     else begin      if (fpafd5a) begin      ng14f11 <= pu1b4cf;     qv3c453 <= czfd3fa;     cze229c <= vve9fd4;     if ((!xya8066)  && lf3699  &&  (dmda67a == 8'h0F) && (!pu1b4cf) &&  al7f536) begin      jea788a <= 1'b0;        me629e2 <= 8'h00;       end     else begin      jea788a <= lf3699;      me629e2 <= dmda67a;     end     end\r
+       end\r
+end\r
+always @(posedge do3aeef or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        cz51ac0 <= 1'b0;        ym8d604 <= 1'b0;        end     else begin      cz51ac0 <= zkc0833;     ym8d604 <= go46460;     end\r
+end\r
+always @(posedge do3aeef or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        irbbbd6 <= 0;   rtddeb4 <= 0;   vxc81f <= 0;    xj640ff <= 0;   dzd777a <= 8'd0;        end     else begin  if (db32301) begin  irbbbd6 <= 0;   rtddeb4 <= 0;   vxc81f <= 0;    xj640ff <= 0;   dzd777a <= 8'd0;  end  else begin               if (pf7ead7) begin      dzd777a[3:0] <= jp4fea6[3:0];   end     else begin      dzd777a[3:0] <= jp4fea6[7:4];   end             dzd777a[7:4] <= jp4fea6[7:4];           rtddeb4 <= al7f536;     irbbbd6 <= gofa9b5;     vxc81f <= ykd4da8;      xj640ff <= swa6d40;  end        end\r
+end\r
+always@* begin rt6b020<=vx8bfb1[0];zkc0833<=vx8bfb1[1];xy419b<={fc3f1d7>>1,vx8bfb1[2]};do20cda<=vx8bfb1[3];rv66d2<=vx8bfb1[4];gb44b77<=vx8bfb1[5];ba25bbd<=vx8bfb1[6];bn2ddea<={wl2340c>>1,vx8bfb1[7]};mt33697<={thc8030>>1,vx8bfb1[8]};xl9b4bd<={dz40186>>1,vx8bfb1[9]};psda5ee<={ymc36>>1,vx8bfb1[10]};fnd2f72<={rv61b1>>1,vx8bfb1[11]};aa97b97<={ls30d8f>>1,vx8bfb1[12]};ngbdcb9<={ng86c7b>>1,vx8bfb1[13]};hoee5cb<=vx8bfb1[14];yk72e5a<=vx8bfb1[15];ie972d0<=vx8bfb1[16];ukb9680<=vx8bfb1[17];vicf4a2<=vx8bfb1[18];wj7a513<=vx8bfb1[19];xjd76af<=vx8bfb1[20];ie9dfd7<=vx8bfb1[21];ykefeb8<={vv64785>>1,vx8bfb1[22]};kd7f5c1<=vx8bfb1[23];fpafd5a<=vx8bfb1[24];pf7ead7<=vx8bfb1[25];ba99e94<=vx8bfb1[26];gocb400<={jcdab6f>>1,vx8bfb1[27]};rgd000e<=vx8bfb1[28];hb5a001<=vx8bfb1[29];sjbe13f<=vx8bfb1[30];uif09fd<=vx8bfb1[31];dmda67a<={end69f2>>1,vx8bfb1[32]};pu1b4cf<=vx8bfb1[33];lf3699<=vx8bfb1[34];czfd3fa<=vx8bfb1[35];vve9fd4<=vx8bfb1[36];jp4fea6<={me629e2>>1,vx8bfb1[37]};al7f536<=vx8bfb1[38];gofa9b5<=vx8bfb1[39];ykd4da8<=vx8bfb1[40];swa6d40<=vx8bfb1[41];tj13bfa<=vx8bfb1[42];nt944ef<=vx8bfb1[43];xya8066<=vx8bfb1[44];icfae0d<=vx8bfb1[45];rtd7068<=vx8bfb1[46];pub8346<=vx8bfb1[47];suc1a32<=vx8bfb1[48];uxd191<=vx8bfb1[49];ic68c8c<=vx8bfb1[50];go46460<=vx8bfb1[51];db32301<=vx8bfb1[52];end\r
+always@* begin ead17f6[2047]<=force_isolate;ead17f6[2046]<=fc3f1d7[0];ead17f6[2044]<=wjf8ebb;ead17f6[2041]<=dzc75dd;ead17f6[2034]<=ym3111a;ead17f6[2021]<=ie888d0;ead17f6[2017]<=yxcc8f0;ead17f6[1995]<=wl2340c[0];ead17f6[1986]<=vv64785[0];ead17f6[1943]<=thc8030[0];ead17f6[1925]<=ir23c2f;ead17f6[1908]<=ng3ad3e;ead17f6[1864]<=me629e2[0];ead17f6[1855]<=ir8f6ad;ead17f6[1838]<=dz40186[0];ead17f6[1803]<=me43082;ead17f6[1769]<=tj275a7;ead17f6[1680]<=ng14f11;ead17f6[1662]<=xj7b56d;ead17f6[1628]<=ymc36[0];ead17f6[1583]<=eaea358;ead17f6[1559]<=yz18411;ead17f6[1501]<=of6f251;ead17f6[1490]<=mr518a7;ead17f6[1487]<=cb363da;ead17f6[1312]<=jea788a;ead17f6[1276]<=ym3e56b;ead17f6[1209]<=rv61b1[0];ead17f6[1155]<=cze229c;ead17f6[1118]<=cz51ac0;ead17f6[1070]<=hqa7cad;ead17f6[1048]<=ww5391d;ead17f6[1023]<=gbe_mode;ead17f6[1008]<=qi31243;ead17f6[954]<=end69f2[0];ead17f6[932]<=ba8c53c;ead17f6[927]<=uxb1ed5;ead17f6[791]<=kq7d46b;ead17f6[750]<=uk8de4a;ead17f6[743]<=ng86c7b[0];ead17f6[577]<=qv3c453;ead17f6[524]<=riad664;ead17f6[504]<=shf2b59;ead17f6[395]<=vk2fa8d;ead17f6[375]<=lqd5b7b;ead17f6[371]<=ls30d8f[0];ead17f6[262]<=yk5991e;ead17f6[197]<=cb85f51;ead17f6[189]<=ym8d604;ead17f6[187]<=twadbda;ead17f6[98]<=qgf0bea;ead17f6[93]<=jcdab6f[0];ead17f6[49]<=hq1e17d;end         assign jebdc77 = ead17f6,vx8bfb1 = fn71dda; initial begin kfbe35f = $fopen(".fred"); $fdisplay( kfbe35f, "%3h\n%3h", (fnf63ba >> 4) & fpbaf71, (fnf63ba >> (tj8eebd+4)) & fpbaf71 ); $fclose(kfbe35f); $readmemh(".fred", ay776be); end always @ (jebdc77) begin nedaf8d = ay776be[1]; for (jcf1afd=0; jcf1afd<th5fd8e; jcf1afd=jcf1afd+1) begin fn71dda[jcf1afd] = jebdc77[nedaf8d]; thd7c6b = ^(nedaf8d & ay776be[0]); nedaf8d = {nedaf8d, thd7c6b}; end end\r
+endmodule\r
+`timescale 1 ns / 100 ps\r
+module rv9e7a (rst_n,\r
+                  gbe_mode,\r
+                  xwcf5fb,\r
+                  mr7afdb,\r
+                  yxcc8f0,\r
+                  force_isolate,\r
+                  fc3f1d7,\r
+                  wjf8ebb,\r
+                  dzc75dd,\r
+                  wje7ecc,\r
+                  dzd777a,\r
+                  irbbbd6,\r
+                  rtddeb4\r
+                 );\r
+input                rst_n;\r
+input                gbe_mode;\r
+input                xwcf5fb;\r
+input                mr7afdb;\r
+output               yxcc8f0;\r
+input                force_isolate;\r
+input  [7:0]         fc3f1d7;\r
+input                wjf8ebb;\r
+input                dzc75dd;\r
+input  [1:0]         wje7ecc;\r
+output  [7:0]        dzd777a;\r
+output               irbbbd6;\r
+output               rtddeb4;\r
+reg [7:0] dzd777a;\r
+reg irbbbd6;\r
+reg rtddeb4;\r
+reg [1:0] thc8030;\r
+reg [1:0] dz40186;\r
+reg [1:0] ymc36;\r
+reg [1:0] rv61b1;\r
+reg [1:0] ls30d8f;\r
+reg [1:0] ng86c7b;\r
+reg cb363da;\r
+reg uxb1ed5;\r
+reg ir8f6ad;\r
+reg xj7b56d;\r
+reg yxcc8f0;\r
+reg [6:0] vv64785;\r
+reg ir23c2f;\r
+reg me43082;\r
+reg hqa7cad;\r
+reg [7:0] jcdab6f;\r
+reg twadbda;\r
+reg lqd5b7b;\r
+reg hq1e17d;\r
+reg qgf0bea;\r
+reg cb85f51;\r
+reg vk2fa8d;\r
+reg kq7d46b;\r
+reg eaea358;\r
+reg cz51ac0;\r
+reg ym8d604;\r
+reg rt6b020;\r
+reg ea4c72b;\r
+reg zkc0833;\r
+reg [7 : 0] xy419b;\r
+reg do20cda;\r
+reg rv66d2;\r
+reg [1 : 0] jc58788;\r
+reg [1 : 0] mt33697;\r
+reg [1 : 0] xl9b4bd;\r
+reg [1 : 0] psda5ee;\r
+reg [1 : 0] fnd2f72;\r
+reg [1 : 0] aa97b97;\r
+reg [1 : 0] ngbdcb9;\r
+reg hoee5cb;\r
+reg yk72e5a;\r
+reg ie972d0;\r
+reg ukb9680;\r
+reg [6 : 0] ykefeb8;\r
+reg kd7f5c1;\r
+reg fpafd5a;\r
+reg ba99e94;\r
+reg [7 : 0] gocb400;\r
+reg rgd000e;\r
+reg hb5a001;\r
+reg icfae0d;\r
+reg rtd7068;\r
+reg pub8346;\r
+reg suc1a32;\r
+reg uxd191;\r
+reg ic68c8c;\r
+reg go46460;\r
+reg db32301;\r
+reg [2047:0] ead17f6;\r
+wire [31:0] vx8bfb1;\r
+localparam th5fd8e = 32,nefec77 = 32'hfdffca8b;\r
+localparam [31:0] fnf63ba = nefec77;\r
+localparam tj8eebd = nefec77 & 4'hf;\r
+localparam [11:0] fpbaf71 = 'h7ff;\r
+wire [(1 << tj8eebd) -1:0] jebdc77;\r
+reg [th5fd8e-1:0] fn71dda;\r
+reg [tj8eebd-1:0] ay776be [0:1];\r
+reg [tj8eebd-1:0] nedaf8d;\r
+reg thd7c6b;\r
+integer kfbe35f;\r
+integer jcf1afd;\r
+always @(posedge xwcf5fb or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        cz51ac0 <= 1'b0;        ym8d604 <= 1'b0;        end     else begin      cz51ac0 <= zkc0833;     ym8d604 <= go46460;     end\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        hq1e17d <= 1'b0;        qgf0bea <= 1'b0;        cb85f51 <= 1'b0;        vk2fa8d <= 1'b0;        kq7d46b <= 1'b0;        eaea358 <= 1'b0;        end     else begin              hq1e17d <= rt6b020;     qgf0bea <= icfae0d;\r
+               cb85f51 <= rtd7068;             vk2fa8d <= rtd7068 & (~pub8346);                kq7d46b <= ~rtd7068 & (pub8346);                eaea358 <= suc1a32 || uxd191;   end\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        thc8030 <= 2'd0;        dz40186 <= 2'd0;        ymc36 <= 2'd0;  rv61b1 <= 2'd0; ls30d8f <= 2'd0;        ng86c7b <= 2'd0;        cb363da <= 1'b1;        uxb1ed5 <= 1'b0;        ir8f6ad <= 1'b0;        xj7b56d <= 1'b0;        end     else begin              thc8030 <= jc58788;             dz40186 <= mt33697;     ymc36 <= xl9b4bd;       rv61b1 <= psda5ee;      if ((xl9b4bd==psda5ee) && (xl9b4bd==fnd2f72))   ls30d8f <= fnd2f72;     ng86c7b <= aa97b97;             if (ic68c8c)    cb363da <= 1'b1;        else if (aa97b97 != ngbdcb9)    cb363da <= 1'b1;        else    cb363da <= 1'b0;                if (pub8346) begin      uxb1ed5    <=  1'b1;    ir8f6ad  <=  1'b0;      xj7b56d   <=  1'b0;     end     else begin      uxb1ed5    <=   aa97b97[1];     ir8f6ad  <=  !aa97b97[1]  & ( aa97b97[0]);      xj7b56d   <=  !aa97b97[1]  & (!aa97b97[0]);     end     end\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        vv64785 <= 7'd0;        ir23c2f <= 1'b0;        end     else begin              if (hoee5cb || kd7f5c1) begin   vv64785 <= 7'd0;        end     else begin      vv64785 <= ykefeb8 + 1; end\r
+               if (hoee5cb) begin      ir23c2f <= 1'b0;        end     else if (ie972d0) begin         if (ykefeb8 == 7'd8) begin      ir23c2f <= 1'b1;        end     else begin      ir23c2f <= 1'b0;        end     end     else if (ukb9680) begin         if (ykefeb8 == 7'd98) begin     ir23c2f <= 1'b1;        end     else begin      ir23c2f <= 1'b0;        end     end     else begin              ir23c2f <= 1'b1;        end     end\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        yxcc8f0 <= 1'b0;        end     else begin      if (hoee5cb) begin      yxcc8f0 <=  1'b0;       end     else if (ie972d0) begin         if (ykefeb8 == 7'd3) begin      yxcc8f0 <=  1'b1;       end     else begin      yxcc8f0 <=  1'b0;       end     end     else if (ukb9680) begin         if (ykefeb8 == 7'd49) begin     yxcc8f0 <=  1'b1;       end     else begin      yxcc8f0 <=  1'b0;       end     end     else begin              yxcc8f0 <=  1'b1;       end     end\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        lqd5b7b <= 0;   twadbda <= 0;   jcdab6f <= 8'd0;        end     else begin  if (ea4c72b) begin  if (db32301) begin      jcdab6f <= 8'd0;        twadbda <= 1'b0;        lqd5b7b <= 1'b0;        end     else begin      jcdab6f <= xy419b;      twadbda <= rv66d2;      lqd5b7b <= do20cda;     end  end        end\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        irbbbd6 <= 0;   rtddeb4 <= 0;   dzd777a <= 8'd0;        end     else begin      if (ea4c72b) begin      rtddeb4 <= rgd000e;     irbbbd6 <= hb5a001;     dzd777a <= gocb400;     end     end\r
+end\r
+always@* begin rt6b020<=vx8bfb1[0];ea4c72b<=vx8bfb1[1];zkc0833<=vx8bfb1[2];xy419b<={fc3f1d7>>1,vx8bfb1[3]};do20cda<=vx8bfb1[4];rv66d2<=vx8bfb1[5];jc58788<={wje7ecc>>1,vx8bfb1[6]};mt33697<={thc8030>>1,vx8bfb1[7]};xl9b4bd<={dz40186>>1,vx8bfb1[8]};psda5ee<={ymc36>>1,vx8bfb1[9]};fnd2f72<={rv61b1>>1,vx8bfb1[10]};aa97b97<={ls30d8f>>1,vx8bfb1[11]};ngbdcb9<={ng86c7b>>1,vx8bfb1[12]};hoee5cb<=vx8bfb1[13];yk72e5a<=vx8bfb1[14];ie972d0<=vx8bfb1[15];ukb9680<=vx8bfb1[16];ykefeb8<={vv64785>>1,vx8bfb1[17]};kd7f5c1<=vx8bfb1[18];fpafd5a<=vx8bfb1[19];ba99e94<=vx8bfb1[20];gocb400<={jcdab6f>>1,vx8bfb1[21]};rgd000e<=vx8bfb1[22];hb5a001<=vx8bfb1[23];icfae0d<=vx8bfb1[24];rtd7068<=vx8bfb1[25];pub8346<=vx8bfb1[26];suc1a32<=vx8bfb1[27];uxd191<=vx8bfb1[28];ic68c8c<=vx8bfb1[29];go46460<=vx8bfb1[30];db32301<=vx8bfb1[31];end\r
+always@* begin ead17f6[2047]<=mr7afdb;ead17f6[2046]<=force_isolate;ead17f6[2044]<=fc3f1d7[0];ead17f6[2040]<=wjf8ebb;ead17f6[2032]<=dzc75dd;ead17f6[2017]<=wje7ecc[0];ead17f6[1987]<=thc8030[0];ead17f6[1926]<=dz40186[0];ead17f6[1804]<=ymc36[0];ead17f6[1803]<=lqd5b7b;ead17f6[1560]<=rv61b1[0];ead17f6[1558]<=hq1e17d;ead17f6[1550]<=xj7b56d;ead17f6[1464]<=cz51ac0;ead17f6[1072]<=ls30d8f[0];ead17f6[1069]<=qgf0bea;ead17f6[1052]<=vv64785[0];ead17f6[1023]<=gbe_mode;ead17f6[901]<=twadbda;ead17f6[880]<=ym8d604;ead17f6[775]<=ir8f6ad;ead17f6[732]<=eaea358;ead17f6[450]<=jcdab6f[0];ead17f6[387]<=uxb1ed5;ead17f6[366]<=kq7d46b;ead17f6[225]<=hqa7cad;ead17f6[193]<=cb363da;ead17f6[183]<=vk2fa8d;ead17f6[112]<=me43082;ead17f6[96]<=ng86c7b[0];ead17f6[91]<=cb85f51;ead17f6[56]<=ir23c2f;end         assign jebdc77 = ead17f6,vx8bfb1 = fn71dda; initial begin kfbe35f = $fopen(".fred"); $fdisplay( kfbe35f, "%3h\n%3h", (fnf63ba >> 4) & fpbaf71, (fnf63ba >> (tj8eebd+4)) & fpbaf71 ); $fclose(kfbe35f); $readmemh(".fred", ay776be); end always @ (jebdc77) begin nedaf8d = ay776be[1]; for (jcf1afd=0; jcf1afd<th5fd8e; jcf1afd=jcf1afd+1) begin fn71dda[jcf1afd] = jebdc77[nedaf8d]; thd7c6b = ^(nedaf8d & ay776be[0]); nedaf8d = {nedaf8d, thd7c6b}; end end\r
+endmodule\r
+`timescale 1 ns / 100 ps\r
+module xwcf593 (rst_n,\r
+                  gbe_mode,\r
+                  force_isolate,\r
+                  xwcf5fb,\r
+                  mr7afdb,\r
+                  yxcc8f0,\r
+                  fc3f1d7,\r
+                  wjf8ebb,\r
+                  dzc75dd,\r
+                  ym3111a,\r
+                  ie888d0,\r
+                  wje7ecc,\r
+                  dzd777a,\r
+                  irbbbd6,\r
+                  rtddeb4,\r
+                  vxc81f,\r
+                  xj640ff\r
+                 );\r
+input                rst_n;\r
+input                gbe_mode;\r
+input                force_isolate;\r
+input                xwcf5fb;\r
+input                mr7afdb;\r
+output               yxcc8f0;\r
+input  [7:0]         fc3f1d7;\r
+input                wjf8ebb;\r
+input                dzc75dd;\r
+input                ym3111a;\r
+input                ie888d0;\r
+input  [1:0]         wje7ecc;\r
+output  [7:0]        dzd777a;\r
+output               irbbbd6;\r
+output               rtddeb4;\r
+output               vxc81f;\r
+output               xj640ff;\r
+reg [7:0] dzd777a;\r
+reg irbbbd6;\r
+reg rtddeb4;\r
+reg vxc81f;\r
+reg xj640ff;\r
+reg [1:0] thc8030;\r
+reg [1:0] dz40186;\r
+reg [1:0] ymc36;\r
+reg [1:0] rv61b1;\r
+reg [1:0] ls30d8f;\r
+reg [1:0] ng86c7b;\r
+reg cb363da;\r
+reg uxb1ed5;\r
+reg ir8f6ad;\r
+reg xj7b56d;\r
+reg yxcc8f0;\r
+reg [6:0] vv64785;\r
+reg ir23c2f;\r
+reg me43082;\r
+reg hqa7cad;\r
+reg [7:0] jcdab6f;\r
+reg twadbda;\r
+reg lqd5b7b;\r
+reg uk8de4a;\r
+reg of6f251;\r
+reg hq1e17d;\r
+reg qgf0bea;\r
+reg cb85f51;\r
+reg vk2fa8d;\r
+reg kq7d46b;\r
+reg eaea358;\r
+reg cz51ac0;\r
+reg ym8d604;\r
+reg rt6b020;\r
+reg zkc0833;\r
+reg ea4c72b;\r
+reg [7 : 0] xy419b;\r
+reg do20cda;\r
+reg rv66d2;\r
+reg gb44b77;\r
+reg ba25bbd;\r
+reg [1 : 0] jc58788;\r
+reg [1 : 0] mt33697;\r
+reg [1 : 0] xl9b4bd;\r
+reg [1 : 0] psda5ee;\r
+reg [1 : 0] fnd2f72;\r
+reg [1 : 0] aa97b97;\r
+reg [1 : 0] ngbdcb9;\r
+reg hoee5cb;\r
+reg yk72e5a;\r
+reg ie972d0;\r
+reg ukb9680;\r
+reg [6 : 0] ykefeb8;\r
+reg kd7f5c1;\r
+reg fpafd5a;\r
+reg ba99e94;\r
+reg [7 : 0] gocb400;\r
+reg rgd000e;\r
+reg hb5a001;\r
+reg sjbe13f;\r
+reg uif09fd;\r
+reg icfae0d;\r
+reg rtd7068;\r
+reg pub8346;\r
+reg suc1a32;\r
+reg uxd191;\r
+reg ic68c8c;\r
+reg go46460;\r
+reg db32301;\r
+reg [2047:0] ead17f6;\r
+wire [35:0] vx8bfb1;\r
+localparam th5fd8e = 36,nefec77 = 32'hfdffd42b;\r
+localparam [31:0] fnf63ba = nefec77;\r
+localparam tj8eebd = nefec77 & 4'hf;\r
+localparam [11:0] fpbaf71 = 'h7ff;\r
+wire [(1 << tj8eebd) -1:0] jebdc77;\r
+reg [th5fd8e-1:0] fn71dda;\r
+reg [tj8eebd-1:0] ay776be [0:1];\r
+reg [tj8eebd-1:0] nedaf8d;\r
+reg thd7c6b;\r
+integer kfbe35f;\r
+integer jcf1afd;\r
+always @(posedge xwcf5fb or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        hq1e17d <= 1'b0;        qgf0bea <= 1'b0;        cb85f51 <= 1'b0;        vk2fa8d <= 1'b0;        kq7d46b <= 1'b0;        eaea358 <= 1'b0;        end     else begin              hq1e17d <= rt6b020;     qgf0bea <= icfae0d;\r
+               cb85f51 <= rtd7068;             vk2fa8d <= rtd7068 & (~pub8346);                kq7d46b <= ~rtd7068 & (pub8346);                eaea358 <= suc1a32 || uxd191;   end\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        thc8030 <= 2'd0;        dz40186 <= 2'd0;        ymc36 <= 2'd0;  rv61b1 <= 2'd0; ls30d8f <= 2'd0;        ng86c7b <= 2'd0;        cb363da <= 1'b1;        uxb1ed5 <= 1'b0;        ir8f6ad <= 1'b0;        xj7b56d <= 1'b0;        end     else begin              thc8030 <= jc58788;             dz40186 <= mt33697;     ymc36 <= xl9b4bd;       rv61b1 <= psda5ee;      if ((xl9b4bd==psda5ee) && (xl9b4bd==fnd2f72))   ls30d8f <= fnd2f72;     ng86c7b <= aa97b97;             if (ic68c8c)    cb363da <= 1'b1;        else if (aa97b97 != ngbdcb9)    cb363da <= 1'b1;        else    cb363da <= 1'b0;                if (pub8346) begin      uxb1ed5    <=  1'b1;    ir8f6ad  <=  1'b0;      xj7b56d   <=  1'b0;     end     else begin      uxb1ed5    <=   aa97b97[1];     ir8f6ad  <=  !aa97b97[1]  & ( aa97b97[0]);      xj7b56d   <=  !aa97b97[1]  & (!aa97b97[0]);     end     end\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        vv64785 <= 7'd0;        ir23c2f <= 1'b0;        end     else begin              if (hoee5cb || kd7f5c1) begin   vv64785 <= 7'd0;        end     else begin      vv64785 <= ykefeb8 + 1; end\r
+               if (hoee5cb) begin      ir23c2f <= 1'b0;        end     else if (ie972d0) begin         if (ykefeb8 == 7'd8) begin      ir23c2f <= 1'b1;        end     else begin      ir23c2f <= 1'b0;        end     end     else if (ukb9680) begin         if (ykefeb8 == 7'd98) begin     ir23c2f <= 1'b1;        end     else begin      ir23c2f <= 1'b0;        end     end     else begin              ir23c2f <= 1'b1;        end     end\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        yxcc8f0 <= 1'b0;        end     else begin      if (hoee5cb) begin      yxcc8f0 <=  1'b0;       end     else if (ie972d0) begin         if (ykefeb8 == 7'd3) begin      yxcc8f0 <=  1'b1;       end     else begin      yxcc8f0 <=  1'b0;       end     end     else if (ukb9680) begin         if (ykefeb8 == 7'd49) begin     yxcc8f0 <=  1'b1;       end     else begin      yxcc8f0 <=  1'b0;       end     end     else begin              yxcc8f0 <=  1'b1;       end     end\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        lqd5b7b <= 0;   twadbda <= 0;   uk8de4a <= 0;   of6f251 <= 0;   jcdab6f <= 8'd0;        end     else begin  if (ea4c72b) begin  jcdab6f <= xy419b;      twadbda <= rv66d2;      lqd5b7b <= do20cda;     uk8de4a <= gb44b77;     of6f251 <= ba25bbd;  end        end\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        cz51ac0 <= 1'b0;        ym8d604 <= 1'b0;        end     else begin      cz51ac0 <= zkc0833;     ym8d604 <= go46460;     end\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        irbbbd6 <= 0;   rtddeb4 <= 0;   vxc81f <= 0;    xj640ff <= 0;   dzd777a <= 8'd0;        end     else begin      if (ea4c72b) begin  if (db32301) begin  irbbbd6 <= 0;   rtddeb4 <= 0;   vxc81f <= 0;    xj640ff <= 0;   dzd777a <= 8'd0;  end  else begin       rtddeb4 <= rgd000e;     vxc81f <= sjbe13f;      xj640ff <= uif09fd;     if ((!yk72e5a)  && hb5a001  &&  (gocb400 == 8'h0F) && (!rgd000e) &&  rtddeb4) begin     irbbbd6 <= 1'b0;        dzd777a <= 8'h00;       end     else begin      irbbbd6 <= hb5a001;     dzd777a <= gocb400;     end  end        end\r
+       end\r
+end\r
+always@* begin rt6b020<=vx8bfb1[0];zkc0833<=vx8bfb1[1];ea4c72b<=vx8bfb1[2];xy419b<={fc3f1d7>>1,vx8bfb1[3]};do20cda<=vx8bfb1[4];rv66d2<=vx8bfb1[5];gb44b77<=vx8bfb1[6];ba25bbd<=vx8bfb1[7];jc58788<={wje7ecc>>1,vx8bfb1[8]};mt33697<={thc8030>>1,vx8bfb1[9]};xl9b4bd<={dz40186>>1,vx8bfb1[10]};psda5ee<={ymc36>>1,vx8bfb1[11]};fnd2f72<={rv61b1>>1,vx8bfb1[12]};aa97b97<={ls30d8f>>1,vx8bfb1[13]};ngbdcb9<={ng86c7b>>1,vx8bfb1[14]};hoee5cb<=vx8bfb1[15];yk72e5a<=vx8bfb1[16];ie972d0<=vx8bfb1[17];ukb9680<=vx8bfb1[18];ykefeb8<={vv64785>>1,vx8bfb1[19]};kd7f5c1<=vx8bfb1[20];fpafd5a<=vx8bfb1[21];ba99e94<=vx8bfb1[22];gocb400<={jcdab6f>>1,vx8bfb1[23]};rgd000e<=vx8bfb1[24];hb5a001<=vx8bfb1[25];sjbe13f<=vx8bfb1[26];uif09fd<=vx8bfb1[27];icfae0d<=vx8bfb1[28];rtd7068<=vx8bfb1[29];pub8346<=vx8bfb1[30];suc1a32<=vx8bfb1[31];uxd191<=vx8bfb1[32];ic68c8c<=vx8bfb1[33];go46460<=vx8bfb1[34];db32301<=vx8bfb1[35];end\r
+always@* begin ead17f6[2047]<=force_isolate;ead17f6[2046]<=mr7afdb;ead17f6[2044]<=fc3f1d7[0];ead17f6[2041]<=wjf8ebb;ead17f6[2035]<=dzc75dd;ead17f6[2022]<=ym3111a;ead17f6[1996]<=ie888d0;ead17f6[1945]<=wje7ecc[0];ead17f6[1922]<=lqd5b7b;ead17f6[1842]<=thc8030[0];ead17f6[1797]<=uk8de4a;ead17f6[1776]<=hqa7cad;ead17f6[1637]<=dz40186[0];ead17f6[1622]<=ng86c7b[0];ead17f6[1546]<=of6f251;ead17f6[1504]<=jcdab6f[0];ead17f6[1468]<=ir23c2f;ead17f6[1391]<=xj7b56d;ead17f6[1312]<=cz51ac0;ead17f6[1226]<=ymc36[0];ead17f6[1197]<=cb363da;ead17f6[1044]<=hq1e17d;ead17f6[1023]<=gbe_mode;ead17f6[961]<=twadbda;ead17f6[888]<=me43082;ead17f6[811]<=ls30d8f[0];ead17f6[734]<=vv64785[0];ead17f6[695]<=ir8f6ad;ead17f6[656]<=eaea358;ead17f6[576]<=ym8d604;ead17f6[405]<=rv61b1[0];ead17f6[347]<=uxb1ed5;ead17f6[328]<=kq7d46b;ead17f6[164]<=vk2fa8d;ead17f6[82]<=cb85f51;ead17f6[41]<=qgf0bea;end         assign jebdc77 = ead17f6,vx8bfb1 = fn71dda; initial begin kfbe35f = $fopen(".fred"); $fdisplay( kfbe35f, "%3h\n%3h", (fnf63ba >> 4) & fpbaf71, (fnf63ba >> (tj8eebd+4)) & fpbaf71 ); $fclose(kfbe35f); $readmemh(".fred", ay776be); end always @ (jebdc77) begin nedaf8d = ay776be[1]; for (jcf1afd=0; jcf1afd<th5fd8e; jcf1afd=jcf1afd+1) begin fn71dda[jcf1afd] = jebdc77[nedaf8d]; thd7c6b = ^(nedaf8d & ay776be[0]); nedaf8d = {nedaf8d, thd7c6b}; end end\r
+endmodule\r
+`timescale 1 ns / 100 ps\r
+module uk1087d (   xwcf5fb,\r
+                   rst_n,\r
+                   gbe_mode,\r
+                   sgmii_mode,\r
+                   force_unidir,\r
+                   mr_main_reset,\r
+                   mr_restart_an,\r
+                   mr_an_enable,\r
+                   mr_adv_ability,\r
+                   mr_lp_adv_ability,\r
+                   ou2150a,\r
+                   mr_page_rx,\r
+                   mr_an_complete,\r
+                   ira1445,\r
+                   gqa22d,\r
+                   gb51169,\r
+                   ie88b4d,\r
+                   xj45a69,\r
+                   jr2d34f,\r
+                   tu69a7f,\r
+                   an_link_ok\r
+                   );\r
+input             xwcf5fb;\r
+input             rst_n;\r
+input             gbe_mode;\r
+input             sgmii_mode;\r
+input             force_unidir;\r
+input             mr_main_reset;\r
+input             mr_restart_an;\r
+input             mr_an_enable;\r
+input    [16:1]   mr_adv_ability;\r
+output   [16:1]   mr_lp_adv_ability;\r
+input             ou2150a;\r
+output            mr_page_rx;\r
+output            mr_an_complete;\r
+input             ira1445;\r
+input             gqa22d;\r
+input             gb51169;\r
+input             ie88b4d;\r
+input   [15:0]    xj45a69;\r
+output  [15:0]    jr2d34f;\r
+output  [1:0]     tu69a7f;\r
+output            an_link_ok;\r
+reg   [16:1]      mr_lp_adv_ability;\r
+reg               mr_page_rx;\r
+reg               mr_an_complete;\r
+reg   [15:0]      jr2d34f;\r
+reg   [1:0]       tu69a7f;\r
+reg [15:0] do1e90d;\r
+reg [15:0] psf486b;\r
+reg [15:0] uxa435b;\r
+reg [15:0] ym21add;\r
+reg [15:0] cbd6e8;\r
+reg xj6b744;\r
+localparam yx5ba26                 = 2'b00,          dzdd135        = 2'b01,          qte89af                 = 2'b10;\r
+localparam uv44d7c            = 4'b0000,          kf26be5           = 4'b0001,          xy35f2d   = 4'b0010,          hdaf96b       = 4'b0011,          dm7cb5f   = 4'b0100,          eae5afb = 4'b0101,          zz2d7d8          = 4'b0111,          th6bec7              = 4'b1000;\r
+parameter xj5f63f    = 21'h1cf2bf,           psfb1fe      = 21'h0ced2f,           LINK_TIMER_SH       = 21'h1fff01;\r
+reg               hbc7f9e;\r
+reg               fc3fcf6;\r
+reg               rgfe7b2;\r
+reg               pff3d93;\r
+reg               rv9ec9e;\r
+reg   [20:0]      zxf64f7;\r
+reg               vkb27bf;\r
+reg   [20:0]      pu93dfb;\r
+reg               fp9efdb;\r
+reg   [3:0]       gbf7edf, xlbf6fc, jcfb7e7;\r
+wire  [15:0]      xj45a69;\r
+reg   [15:0]      rgdf9d9;\r
+reg   [15:0]      zxfcecb;\r
+reg   [15:0]      ale765f;\r
+reg   [ 1:0]      qi3b2fc;\r
+reg   [ 1:0]      gbd97e1;\r
+reg   [ 1:0]      mecbf0d;\r
+wire              ie88b4d;\r
+reg               ldfc347;\r
+wire              gb51169;\r
+reg               sjd1f2;\r
+reg               su68f94;\r
+reg               jc47ca0;\r
+reg               uk3e502;\r
+reg               mrf2811;\r
+reg               tj9408c;\r
+reg               lfa0467;\r
+reg               gd233f;\r
+reg    ba119fd;\r
+reg    ri8cfea;\r
+reg    os67f53;\r
+reg    do3fa99;\r
+reg [16:1]     czfd4ca;\r
+reg    suea654;\r
+reg    ic532a0;\r
+reg    vk99500;\r
+reg    dmca803;\r
+reg    en5401a;\r
+reg[15:0]      vxa00d5;\r
+reg    gq6af;\r
+reg    zz3578;\r
+reg    wy1abc7;\r
+reg    lqd5e39;\r
+reg [16:1]     vxaf1ca;\r
+reg    go78e56;\r
+reg    fnc72b1;\r
+reg    ux3958f;\r
+reg    hocac7c;\r
+reg    ic563e2;\r
+reg[15:0]      wlb1f10;\r
+reg yz8f885 ;\r
+reg ps7c42c ;\r
+wire uve2162 ;\r
+reg  [(22*8):1] uk10b14;\r
+reg rt6b020;\r
+reg oh2c505;\r
+reg go6282d;\r
+reg ri14169;\r
+reg vxa0b4b;\r
+reg co5a5e;\r
+reg [16 : 1] xl2d2f1;\r
+reg by6978f;\r
+reg ip4bc7b;\r
+reg sh5e3dc;\r
+reg byf1ee4;\r
+reg mt8f723;\r
+reg [15 : 0] dz7b91d;\r
+reg [15 : 0] czdc8ee;\r
+reg [15 : 0] dme4774;\r
+reg [15 : 0] ux23ba3;\r
+reg [15 : 0] an1dd1d;\r
+reg neee8ec;\r
+reg bl74763;\r
+reg gqa3b1e;\r
+reg sj1d8f1;\r
+reg dzec78c;\r
+reg xw63c67;\r
+reg [20 : 0] xy1e33b;\r
+reg psf19da;\r
+reg [20 : 0] tw8ced3;\r
+reg ea6769b;\r
+reg [3 : 0] wy3b4d8;\r
+reg [3 : 0] byda6c1;\r
+reg [3 : 0] wjd360a;\r
+reg [15 : 0] fp9b054;\r
+reg [15 : 0] dzd82a6;\r
+reg [15 : 0] osc1537;\r
+reg [1 : 0] iea9b8;\r
+reg [1 : 0] sh54dc0;\r
+reg [1 : 0] wya6e04;\r
+reg rv37021;\r
+reg jeb810f;\r
+reg xwc087a;\r
+reg hq43d3;\r
+reg ec21e9a;\r
+reg wyf4d0;\r
+reg en7a681;\r
+reg ofd340d;\r
+reg sj9a06c;\r
+reg byd0364;\r
+reg xl81b23;\r
+reg ird91f;\r
+reg vi6c8fd;\r
+reg [16 : 1] jp647ea;\r
+reg qv23f57;\r
+reg sw1fabd;\r
+reg gbfd5e9;\r
+reg ykeaf4c;\r
+reg jc57a61;\r
+reg [15 : 0] hqbd30b;\r
+reg jpe985a;\r
+reg os4c2d6;\r
+reg pf616b0;\r
+reg lsb587;\r
+reg [16 : 1] vv5ac3b;\r
+reg end61df;\r
+reg rvb0efc;\r
+reg ie877e7;\r
+reg qi3bf39;\r
+reg bydf9c8;\r
+reg [15 : 0] blfce43;\r
+reg qte721f;\r
+reg qv390fc;\r
+reg dzc87e4;\r
+reg [(22 * 8) : 1] cm43f26;\r
+reg [2047:0] ead17f6;\r
+wire [70:0] vx8bfb1;\r
+localparam th5fd8e = 71,nefec77 = 32'hfdffd84b;\r
+localparam [31:0] fnf63ba = nefec77;\r
+localparam tj8eebd = nefec77 & 4'hf;\r
+localparam [11:0] fpbaf71 = 'h7ff;\r
+wire [(1 << tj8eebd) -1:0] jebdc77;\r
+reg [th5fd8e-1:0] fn71dda;\r
+reg [tj8eebd-1:0] ay776be [0:1];\r
+reg [tj8eebd-1:0] nedaf8d;\r
+reg thd7c6b;\r
+integer kfbe35f;\r
+integer jcf1afd;\r
+always @(posedge xwcf5fb or negedge rst_n)\r
+begin  if(!rst_n) begin        yz8f885 <= 1'b1;        ps7c42c <= 1'b1;        end     else begin      yz8f885 <= ri14169;     ps7c42c <= qte721f;     end\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n)\r
+begin  if(!rst_n) begin        ba119fd <= 1'b0;        ri8cfea <= 1'b0;        os67f53 <= 1'b0;        do3fa99 <= 1'b0;        czfd4ca <= 16'd0;       suea654 <= 1'b0;        ic532a0 <= 1'b0;        vk99500 <= 1'b0;        dmca803 <= 1'b0;        en5401a <= 1'b0;        vxa00d5 <= 16'b0;       gq6af <= 1'b0;  zz3578 <= 1'b0; wy1abc7 <= 1'b0;        lqd5e39 <= 1'b0;        vxaf1ca <= 16'b0;       go78e56 <= 1'b0;        fnc72b1 <= 1'b0;        ux3958f <= 1'b0;        hocac7c <= 1'b0;        ic563e2 <= 1'b0;        wlb1f10 <= 16'b0;       end     else begin      ba119fd <= rt6b020;     ri8cfea <= oh2c505;     os67f53 <= vxa0b4b;     do3fa99 <= co5a5e & (!go6282d); czfd4ca <= xl2d2f1;     suea654 <= by6978f;     ic532a0 <= ip4bc7b;     vk99500 <= sh5e3dc;     dmca803 <= byf1ee4;     en5401a <= mt8f723;     vxa00d5 <= xj45a69;     gq6af <= byd0364;       zz3578 <= xl81b23;      wy1abc7 <= ird91f;      lqd5e39 <= vi6c8fd;     vxaf1ca <= jp647ea;     go78e56 <= qv23f57;     fnc72b1 <= sw1fabd;     ux3958f <= gbfd5e9;     hocac7c <= ykeaf4c;     ic563e2 <= jc57a61;     wlb1f10 <= hqbd30b;     end\r
+end\r
+assign uve2162 = (blfce43[15] == dzd82a6[15]) &                               (blfce43[13:0] == dzd82a6[13:0]);\r
+always @(posedge xwcf5fb or negedge rst_n) begin : osea4da   if(!rst_n) begin      sjd1f2     <= 1'b0;      su68f94 <= 1'b0;      jc47ca0      <= 1'b0;      uk3e502        <= 1'b0;      mrf2811    <= 1'b0;      tj9408c           <= 1'b0;      lfa0467    <= 1'b0;      gd233f         <= 1'b0;   end   else begin      sjd1f2     <= (bl74763 != lsb587);      su68f94 <= dzc87e4 ;      jc47ca0      <= dzc87e4 & blfce43[14] &  dzd82a6[14];      uk3e502        <= (iea9b8 == 2'b10) & rv37021;      mrf2811    <= (sh54dc0 == 2'b10) & rv37021;      tj9408c           <= (wya6e04 == 2'b11);      lfa0467    <= (iea9b8 == 2'b10) &                      rv37021 & dzc87e4 ;      gd233f         <= (wjd360a != byda6c1);   end\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n) begin : ne48307   if(!rst_n) begin      xlbf6fc <= uv44d7c;   end   else begin       if(pf616b0 || !ea6769b ||            jeb810f || ie877e7 || neee8ec || qv390fc) begin                 xlbf6fc <= uv44d7c;       end       else begin                 xlbf6fc <= wy3b4d8;       end   end\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n) begin   if(!rst_n) begin      jcfb7e7 <= uv44d7c;      hbc7f9e <= 1'b0;      ldfc347  <= 1'b0;      rgdf9d9 <= 16'h0000;   end   else  begin    if(qv390fc) begin      jcfb7e7 <= uv44d7c;    end    else begin      jcfb7e7 <= byda6c1;      hbc7f9e <= lsb587;      ldfc347  <= bydf9c8;      rgdf9d9 <= blfce43;    end   end\r
+end\r
+always @( byda6c1 or lsb587 or psf19da or ec21e9a or fp9b054 or  wyf4d0 or ofd340d or en7a681) begin : oh36f09   case (byda6c1)      uv44d7c : begin         if(lsb587)            gbf7edf = kf26be5;         else            gbf7edf = xy35f2d;      end\r
+      kf26be5 : begin         if(psf19da)            gbf7edf = hdaf96b;         else            gbf7edf = kf26be5;      end\r
+      hdaf96b : begin         if(ec21e9a && fp9b054 != 16'd0)            gbf7edf = dm7cb5f;         else            gbf7edf = hdaf96b;      end\r
+      dm7cb5f : begin         if((wyf4d0 && !ofd340d) ||            (ec21e9a     && fp9b054 == 16'h0000))            gbf7edf = uv44d7c;         else if(wyf4d0 && ofd340d)            gbf7edf = eae5afb;         else            gbf7edf = dm7cb5f;      end\r
+      eae5afb : begin         if(ec21e9a && fp9b054 == 16'h0000)            gbf7edf = uv44d7c;         else if((psf19da) &&                 (!ec21e9a || fp9b054 != 16'h0000))            gbf7edf = zz2d7d8;         else            gbf7edf = eae5afb;      end\r
+      zz2d7d8 : begin         if (ec21e9a   && fp9b054 == 16'h0000)            gbf7edf = uv44d7c;         else if (en7a681 && psf19da)            gbf7edf = th6bec7;         else            gbf7edf = zz2d7d8;      end\r
+      th6bec7 : begin         if (ec21e9a)            gbf7edf = uv44d7c;         else            gbf7edf = th6bec7;      end\r
+      xy35f2d :         gbf7edf = xy35f2d;\r
+      default : begin         gbf7edf = uv44d7c;      end\r
+   endcase\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n) begin   if(!rst_n) begin      mr_page_rx <= 1'b0;   end   else begin     if (byda6c1 == eae5afb) begin      mr_page_rx <= 1'b1;     end     else begin      mr_page_rx <= 1'b0;     end   end\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n) begin   if(!rst_n ) begin      mr_lp_adv_ability <= 16'h0000;   end   else begin     if ((byda6c1 == uv44d7c) || (byda6c1 == hdaf96b))  begin          mr_lp_adv_ability <= 16'h0000;     end     else if (byda6c1 == eae5afb) begin          mr_lp_adv_ability <= blfce43;     end     else begin         mr_lp_adv_ability <= mr_lp_adv_ability;     end   end\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n) begin : vk1b240   if(!rst_n ) begin      mr_an_complete <= 1'b0;   end   else begin     if (byda6c1 == uv44d7c) begin        mr_an_complete <= 1'b0;     end     else if (byda6c1 == th6bec7) begin        mr_an_complete <= 1'b1;     end     else begin        mr_an_complete <= mr_an_complete;     end   end\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n) begin : fp9f3a   if(!rst_n ) begin      jr2d34f <= 16'd0;   end   else begin     if ((byda6c1 == uv44d7c && lsb587) || (byda6c1 == kf26be5)) begin        jr2d34f <= 16'd0;     end     else if (byda6c1 == hdaf96b) begin        jr2d34f <= {vv5ac3b[16],1'b0,vv5ac3b[14:1]};     end     else if (byda6c1 == dm7cb5f) begin        jr2d34f <= (jr2d34f | 16'h4000);     end     else begin        jr2d34f <= jr2d34f;     end   end\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n) begin : rg76d29   if(!rst_n ) begin      tu69a7f <= yx5ba26;   end   else begin     if (((byda6c1 == uv44d7c) && lsb587) || (byda6c1 == kf26be5)) begin        tu69a7f <= dzdd135;     end     else if (((byda6c1 == uv44d7c) && !lsb587) || (byda6c1 == zz2d7d8)) begin        tu69a7f <= yx5ba26;     end     else if ((byda6c1 == xy35f2d) || (byda6c1 == th6bec7)) begin        tu69a7f <= qte89af;     end     else begin        tu69a7f <= tu69a7f;     end   end\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n) begin   if(!rst_n ) begin      rgfe7b2             <= 1'b0;      pff3d93         <= 1'b0;      rv9ec9e          <= 1'b0;      fc3fcf6 <= 1'b0;   end   else begin      if ((byda6c1 == kf26be5) && (wjd360a == uv44d7c)) begin         rgfe7b2 <= 1'b1;      end      else begin         rgfe7b2 <= 1'b0;      end      if ((byda6c1 == eae5afb) && (wjd360a == dm7cb5f))  begin         pff3d93 <= 1'b1;      end      else  begin         pff3d93 <= 1'b0;      end      if ((byda6c1 == zz2d7d8) && (wjd360a == eae5afb))  begin         rv9ec9e <= 1'b1;      end      else  begin         rv9ec9e <= 1'b0;      end      if (sj1d8f1 || dzec78c || xw63c67)  begin         fc3fcf6 <= 1'b1;      end      else  begin         fc3fcf6 <= 1'b0;      end   end\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n) begin : vkbbc2   if(!rst_n ) begin      zxf64f7 <= xj5f63f;   end   else if (gqa3b1e) begin      if (end61df) begin            zxf64f7 <= LINK_TIMER_SH;      end      else if (jpe985a) begin            zxf64f7 <= psfb1fe;      end      else begin            zxf64f7 <= xj5f63f;      end   end   else if (!psf19da) begin      zxf64f7 <= xy1e33b + 'd1;   end   else begin      zxf64f7 <= xy1e33b;   end\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n) begin : co976d8   if(!rst_n ) begin      vkb27bf <= 1'b0;   end   else begin     if (xy1e33b == 'd0 && !gqa3b1e) begin        vkb27bf <=  1'b1;     end     else begin        vkb27bf <=  1'b0;     end   end\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n) begin : ep763f   if(!rst_n ) begin      pu93dfb <= 21'd0;   end   else if (rvb0efc) begin      if (end61df) begin            pu93dfb <= LINK_TIMER_SH;      end      else if (jpe985a) begin            pu93dfb <= psfb1fe;      end      else begin            pu93dfb <= xj5f63f;      end   end   else begin      pu93dfb <= tw8ced3 + 'd1;   end\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n) begin : mtb100c   if(!rst_n ) begin fp9efdb <= 1'b0;    end   else begin    case(ea6769b)   1'b0: begin             if (rvb0efc) begin      fp9efdb <= 1'b1;        end     end     1'b1: begin             if(tw8ced3 == 21'd0) begin      fp9efdb <= 1'b0;        end     end     default: begin  fp9efdb <= 1'b0;        end        endcase   end\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n) begin : ayfaf29   if(!rst_n )      zxfcecb <= 16'h0000;   else if(sj9a06c)      zxfcecb <= 16'h0000;   else if(bydf9c8)      zxfcecb <= blfce43;   else      zxfcecb <= dzd82a6;\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n) begin : czdcab5   if(!rst_n ) begin      ale765f <= 16'h0000;   end   else begin     if(ec21e9a) begin        ale765f <= blfce43;     end     else begin        ale765f <= osc1537;     end   end\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n) begin : fa79ec3   if(!rst_n )      qi3b2fc <= 2'b00;   else if(sj9a06c || qi3bf39 || (bydf9c8 && !xwc087a))        qi3b2fc <= 2'b00;   else if(bydf9c8 && xwc087a && (iea9b8 != 2'b10))      qi3b2fc <= iea9b8 + 2'b01;   else      qi3b2fc <= iea9b8;\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n) begin : ls2f411   if(!rst_n )      gbd97e1 <= 2'b00;   else if(sj9a06c || qi3bf39)      gbd97e1 <= 2'b00;   else if(bydf9c8 && hq43d3 && (sh54dc0 != 2'b10))      gbd97e1 <= sh54dc0 + 2'b01;   else      gbd97e1 <= sh54dc0;\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n) begin : rt40b1c   if(!rst_n )      mecbf0d <= 2'b00;   else if(sj9a06c)      mecbf0d <= 2'b00;   else if(qi3bf39 && !en7a681)      mecbf0d <= wya6e04 + 2'b01;   else      mecbf0d <= wya6e04;\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n) begin   if(!rst_n) begin      do1e90d             <= 16'd0;      psf486b             <= 16'd0;      uxa435b             <= 16'd0;      ym21add       <= 16'd0;      cbd6e8   <= 16'd0;      xj6b744 <= 1'b0;   end   else begin                        do1e90d[15:0] <= vv5ac3b[16:1];      psf486b <= dz7b91d;      uxa435b <= czdc8ee;      if ((dz7b91d == czdc8ee) && (dz7b91d == dme4774))        cbd6e8 <= dme4774;      else        cbd6e8 <= an1dd1d;                        ym21add <= an1dd1d;                        if ((os4c2d6==1'b1) && (jpe985a==1'b0)) begin                if (an1dd1d != ux23ba3) begin          xj6b744 <= 1'b1;        end        else begin          xj6b744 <= 1'b0;         end      end      else begin          xj6b744 <= 1'b0;      end         end\r
+end\r
+assign an_link_ok = ((byda6c1==th6bec7) || (byda6c1==xy35f2d)) ? 1'b1 : 1'b0;\r
+always @(byda6c1) begin   case (byda6c1)      uv44d7c            : uk10b14 = "AN_ENABLE";      kf26be5           : uk10b14 = "AN_RESTART";      xy35f2d   : uk10b14 = "AN_DISABLE_LINK_OK";      hdaf96b       : uk10b14 = "ABILITY_DETECT";      dm7cb5f   : uk10b14 = "ACKNOWLEDGE_DETECT";      eae5afb : uk10b14 = "COMPLETE_ACKNOWLEDGE";      zz2d7d8          : uk10b14 = "IDLE_DETECT";      th6bec7              : uk10b14 = "LINK_OK";\r
+      default              : uk10b14 = "***ERROR***";   endcase\r
+end\r
+always@* begin rt6b020<=vx8bfb1[0];oh2c505<=vx8bfb1[1];go6282d<=vx8bfb1[2];ri14169<=vx8bfb1[3];vxa0b4b<=vx8bfb1[4];co5a5e<=vx8bfb1[5];xl2d2f1<={mr_adv_ability>>1,vx8bfb1[6]};by6978f<=vx8bfb1[7];ip4bc7b<=vx8bfb1[8];sh5e3dc<=vx8bfb1[9];byf1ee4<=vx8bfb1[10];mt8f723<=vx8bfb1[11];dz7b91d<={do1e90d>>1,vx8bfb1[12]};czdc8ee<={psf486b>>1,vx8bfb1[13]};dme4774<={uxa435b>>1,vx8bfb1[14]};ux23ba3<={ym21add>>1,vx8bfb1[15]};an1dd1d<={cbd6e8>>1,vx8bfb1[16]};neee8ec<=vx8bfb1[17];bl74763<=vx8bfb1[18];gqa3b1e<=vx8bfb1[19];sj1d8f1<=vx8bfb1[20];dzec78c<=vx8bfb1[21];xw63c67<=vx8bfb1[22];xy1e33b<={zxf64f7>>1,vx8bfb1[23]};psf19da<=vx8bfb1[24];tw8ced3<={pu93dfb>>1,vx8bfb1[25]};ea6769b<=vx8bfb1[26];wy3b4d8<={gbf7edf>>1,vx8bfb1[27]};byda6c1<={xlbf6fc>>1,vx8bfb1[28]};wjd360a<={jcfb7e7>>1,vx8bfb1[29]};fp9b054<={rgdf9d9>>1,vx8bfb1[30]};dzd82a6<={zxfcecb>>1,vx8bfb1[31]};osc1537<={ale765f>>1,vx8bfb1[32]};iea9b8<={qi3b2fc>>1,vx8bfb1[33]};sh54dc0<={gbd97e1>>1,vx8bfb1[34]};wya6e04<={mecbf0d>>1,vx8bfb1[35]};rv37021<=vx8bfb1[36];jeb810f<=vx8bfb1[37];xwc087a<=vx8bfb1[38];hq43d3<=vx8bfb1[39];ec21e9a<=vx8bfb1[40];wyf4d0<=vx8bfb1[41];en7a681<=vx8bfb1[42];ofd340d<=vx8bfb1[43];sj9a06c<=vx8bfb1[44];byd0364<=vx8bfb1[45];xl81b23<=vx8bfb1[46];ird91f<=vx8bfb1[47];vi6c8fd<=vx8bfb1[48];jp647ea<={czfd4ca>>1,vx8bfb1[49]};qv23f57<=vx8bfb1[50];sw1fabd<=vx8bfb1[51];gbfd5e9<=vx8bfb1[52];ykeaf4c<=vx8bfb1[53];jc57a61<=vx8bfb1[54];hqbd30b<={vxa00d5>>1,vx8bfb1[55]};jpe985a<=vx8bfb1[56];os4c2d6<=vx8bfb1[57];pf616b0<=vx8bfb1[58];lsb587<=vx8bfb1[59];vv5ac3b<={vxaf1ca>>1,vx8bfb1[60]};end61df<=vx8bfb1[61];rvb0efc<=vx8bfb1[62];ie877e7<=vx8bfb1[63];qi3bf39<=vx8bfb1[64];bydf9c8<=vx8bfb1[65];blfce43<={wlb1f10>>1,vx8bfb1[66]};qte721f<=vx8bfb1[67];qv390fc<=vx8bfb1[68];dzc87e4<=vx8bfb1[69];cm43f26<={uk10b14>>1,vx8bfb1[70]};end\r
+always@* begin ead17f6[2047]<=sgmii_mode;ead17f6[2046]<=force_unidir;ead17f6[2044]<=mr_main_reset;ead17f6[2040]<=mr_restart_an;ead17f6[2033]<=mr_an_enable;ead17f6[2019]<=mr_adv_ability[1];ead17f6[1999]<=mecbf0d[0];ead17f6[1991]<=ou2150a;ead17f6[1981]<=ic532a0;ead17f6[1958]<=gq6af;ead17f6[1950]<=ldfc347;ead17f6[1947]<=tj9408c;ead17f6[1934]<=ira1445;ead17f6[1914]<=vk99500;ead17f6[1892]<=rgfe7b2;ead17f6[1868]<=zz3578;ead17f6[1852]<=sjd1f2;ead17f6[1851]<=ym21add[0];ead17f6[1847]<=lfa0467;ead17f6[1820]<=gqa22d;ead17f6[1783]<=do3fa99;ead17f6[1780]<=dmca803;ead17f6[1737]<=pff3d93;ead17f6[1689]<=wy1abc7;ead17f6[1657]<=su68f94;ead17f6[1654]<=cbd6e8[0];ead17f6[1647]<=gd233f;ead17f6[1610]<=vkb27bf;ead17f6[1608]<=hocac7c;ead17f6[1593]<=gb51169;ead17f6[1523]<=qi3b2fc[0];ead17f6[1519]<=czfd4ca[1];ead17f6[1513]<=en5401a;ead17f6[1426]<=rv9ec9e;ead17f6[1404]<=zxfcecb[0];ead17f6[1330]<=lqd5e39;ead17f6[1267]<=jc47ca0;ead17f6[1260]<=xj6b744;ead17f6[1246]<=ba119fd;ead17f6[1225]<=go78e56;ead17f6[1199]<=xlbf6fc[0];ead17f6[1173]<=pu93dfb[0];ead17f6[1169]<=ic563e2;ead17f6[1163]<=ps7c42c;ead17f6[1139]<=ie88b4d;ead17f6[1023]<=gbe_mode;ead17f6[999]<=gbd97e1[0];ead17f6[990]<=suea654;ead17f6[979]<=vxa00d5[0];ead17f6[973]<=mrf2811;ead17f6[946]<=fc3fcf6;ead17f6[925]<=uxa435b[0];ead17f6[891]<=os67f53;ead17f6[805]<=zxf64f7[0];ead17f6[804]<=ux3958f;ead17f6[761]<=ale765f[0];ead17f6[702]<=rgdf9d9[0];ead17f6[612]<=vxaf1ca[1];ead17f6[599]<=gbf7edf[0];ead17f6[581]<=yz8f885;ead17f6[556]<=uk10b14[1];ead17f6[486]<=uk3e502;ead17f6[473]<=hbc7f9e;ead17f6[462]<=psf486b[0];ead17f6[445]<=ri8cfea;ead17f6[402]<=fnc72b1;ead17f6[351]<=jcfb7e7[0];ead17f6[299]<=fp9efdb;ead17f6[290]<=wlb1f10[0];ead17f6[278]<=uve2162;ead17f6[231]<=do1e90d[0];end         assign jebdc77 = ead17f6,vx8bfb1 = fn71dda; initial begin kfbe35f = $fopen(".fred"); $fdisplay( kfbe35f, "%3h\n%3h", (fnf63ba >> 4) & fpbaf71, (fnf63ba >> (tj8eebd+4)) & fpbaf71 ); $fclose(kfbe35f); $readmemh(".fred", ay776be); end always @ (jebdc77) begin nedaf8d = ay776be[1]; for (jcf1afd=0; jcf1afd<th5fd8e; jcf1afd=jcf1afd+1) begin fn71dda[jcf1afd] = jebdc77[nedaf8d]; thd7c6b = ^(nedaf8d & ay776be[0]); nedaf8d = {nedaf8d, thd7c6b}; end end\r
+endmodule\r
+`timescale 1 ns / 100 ps\r
+module gqa018 (\r
+   hb500c1 ,\r
+   rst_n ,\r
+   mr_main_reset ,\r
+   sgmii_mode ,\r
+   gbe_mode ,\r
+   qif9e9 ,\r
+   rx_data ,\r
+   rx_kcntl ,\r
+   tj3d21d ,\r
+   ira1445 ,\r
+   rx_even ,\r
+   tu69a7f ,\r
+   xj45a69 ,\r
+   vieee84 ,\r
+   kq77423 ,\r
+   hdba119 ,\r
+   lqd08cf ,\r
+   vx8467a ,\r
+   oh233d6\r
+   );\r
+input         hb500c1;\r
+input         rst_n;\r
+input         mr_main_reset;\r
+input         sgmii_mode;\r
+input         gbe_mode;\r
+input         qif9e9;\r
+input [7:0]   rx_data;\r
+input         rx_kcntl;\r
+input         tj3d21d;\r
+input         ira1445;\r
+input         rx_even;\r
+input [1:0]   tu69a7f;\r
+output [15:0] xj45a69;\r
+output        vieee84;\r
+output        kq77423;\r
+output        hdba119;\r
+output [7:0]  lqd08cf;\r
+output        vx8467a;\r
+output        oh233d6;\r
+localparam  tj81e62 = 8'hBC ,             aaf317 = 8'hFE ,                jc798b9 = 8'hFB ,               czcc5cb = 8'hFD ,               ui62e5c = 8'hF7 ,               an172e1 = 8'hB5 ,               ieb970c  = 8'h42 ,              oscb860  = 8'hC5 ,              me5c300 = 8'h50 ,               jce1801  = 8'h00 ,              ntc00a = 8'hFC ,                gb60056 = 8'h3C ;\r
+localparam  qi2b5     = 5'd0 ,           zm15a8       = 5'd1 ,           swad42         = 5'd2 ,           su56a10        = 5'd3 ,           dbb5081        = 5'd4 ,           xya840e        = 5'd5 ,           by42073       = 5'd6 ,           mg1039b        = 5'd7 ,           hd81cd9     = 5'd8 ,           jee6cf          = 5'd9 ,           dm7367b     = 5'd10 ,           db9b3db      = 5'd11 ,           mrd9ede      = 5'd12 ,           facf6f4      = 5'd13 ,           zx7b7a3         = 5'd14 ,           ykdbd1f     = 5'd15 ,           ayde8f9     = 5'd16 ,           rgf47c9      = 5'd17 ;\r
+reg               eca3e4a;\r
+wire              aa1f251;\r
+wire              oh233d6;\r
+reg               vx8467a;\r
+reg [7:0]         lqd08cf;\r
+reg               uv511a7;\r
+reg [15:0]        xj45a69;\r
+reg               vieee84;\r
+reg               kq77423;\r
+reg               hdba119;\r
+reg [7:0]         zz3d20b ;\r
+reg [7:0]         xje905e ;\r
+reg [7:0]         by482f7 ;\r
+reg [7:0]         of417ba ;\r
+reg [7:0]         jebdd4 ;\r
+reg               al5eea2 ;\r
+reg               shf7515 ;\r
+reg               tjba8ad ;\r
+reg               ykd456e ;\r
+reg               xya2b71 ;\r
+reg               wy15b8b ;\r
+reg               doadc58 ;\r
+reg               vv6e2c2 ;\r
+reg               jp71616 ;\r
+reg               vx8b0b6 ;\r
+reg               vi585b7 ;\r
+reg               fnc2dbb ;\r
+reg               rv16dde ;\r
+reg               swb6ef7 ;\r
+reg               ngb77b8 ;\r
+reg               epbbdc3 ;\r
+reg               icdee1c ;\r
+reg               enf70e1 ;\r
+reg               jeb870d ;\r
+reg               yxc386a ;\r
+reg               nt1c354 ;\r
+reg               rge1aa7 ;\r
+reg               yzd53a ;\r
+reg               qt6a9d4 ;\r
+reg [4:0]         yx54ea5 ;\r
+reg [4:0]         twa752c ;\r
+wire              ng3a962 ;\r
+wire              cmd4b12 ;\r
+wire              bna5890 ;\r
+wire              an2c486 ;\r
+wire              yk62435 ;\r
+wire              cb121a8 ;\r
+wire              an90d44 ;\r
+wire              je86a24 ;\r
+wire              vk35122 ;\r
+wire              lsa8912 ;\r
+wire              gb44892 ;\r
+wire              aa24495 ;\r
+wire              xl224a9 ;\r
+wire              ux1254e ;\r
+reg [1:0] mg92a74;\r
+reg [1:0] gd953a1;\r
+reg yz8f885 ;\r
+reg ps7c42c ;\r
+reg th74344;\r
+reg wla1a26;\r
+reg mtd134;\r
+reg ww689a4;\r
+reg hq1e17d;\r
+reg qgf0bea;\r
+reg  [(20*8):1] aa3482d;\r
+reg ri14169;\r
+reg oh2c505;\r
+reg rt6b020;\r
+reg rv2d351;\r
+reg [7 : 0] fa69a8f;\r
+reg jc4d47a;\r
+reg al6a3d2;\r
+reg ip4bc7b;\r
+reg ep8f4a4;\r
+reg [1 : 0] qt7a525;\r
+reg hbd292d;\r
+reg tj9496f;\r
+reg gda4b7e;\r
+reg [7 : 0] ng25bf4;\r
+reg [7 : 0] tj2dfa2;\r
+reg [7 : 0] sh6fd16;\r
+reg [7 : 0] pf7e8b5;\r
+reg [7 : 0] tuf45ae;\r
+reg vka2d72;\r
+reg jr16b93;\r
+reg jrb5c9f;\r
+reg yzae4ff;\r
+reg ea727fc;\r
+reg je93fe1;\r
+reg ir9ff0b;\r
+reg cmff85d;\r
+reg vvfc2e8;\r
+reg pse1746;\r
+reg lsba33;\r
+reg ps5d19a;\r
+reg ipe8cd3;\r
+reg go4669c;\r
+reg cb334e1;\r
+reg ux9a70d;\r
+reg shd386c;\r
+reg ba9c365;\r
+reg zke1b2b;\r
+reg kfd95a;\r
+reg lq6cad5;\r
+reg gb656aa;\r
+reg qi2b555;\r
+reg vv5aaa8;\r
+reg [4 : 0] dmd5547;\r
+reg [4 : 0] ntaaa3b;\r
+reg bl551df;\r
+reg vka8eff;\r
+reg ho477fa;\r
+reg ie3bfd3;\r
+reg psdfe98;\r
+reg goff4c3;\r
+reg cmfa619;\r
+reg yxd30c9;\r
+reg sw9864c;\r
+reg gbc3261;\r
+reg db1930d;\r
+reg qtc986f;\r
+reg go4c37d;\r
+reg dz61be8;\r
+reg [1 : 0] qvdf46;\r
+reg [1 : 0] ip6fa35;\r
+reg qte721f;\r
+reg qv390fc;\r
+reg qg46b44;\r
+reg zm35a20;\r
+reg vkad103;\r
+reg kq6881b;\r
+reg icfae0d;\r
+reg rtd7068;\r
+reg [(20 * 8) : 1] hd3623;\r
+reg [2047:0] ead17f6;\r
+wire [68:0] vx8bfb1;\r
+localparam th5fd8e = 69,nefec77 = 32'hfdffc70b;\r
+localparam [31:0] fnf63ba = nefec77;\r
+localparam tj8eebd = nefec77 & 4'hf;\r
+localparam [11:0] fpbaf71 = 'h7ff;\r
+wire [(1 << tj8eebd) -1:0] jebdc77;\r
+reg [th5fd8e-1:0] fn71dda;\r
+reg [tj8eebd-1:0] ay776be [0:1];\r
+reg [tj8eebd-1:0] nedaf8d;\r
+reg thd7c6b;\r
+integer kfbe35f;\r
+integer jcf1afd;\r
+always @(posedge hb500c1 or negedge rst_n) begin   if (!rst_n) begin      zz3d20b <= 8'h00 ;      xje905e <= 8'h00 ;      by482f7 <= 8'h00 ;      of417ba <= 8'h00 ;      jebdd4 <= 8'h00 ;      al5eea2 <= 1'b0 ;      shf7515 <= 1'b0 ;      tjba8ad <= 1'b0 ;      ykd456e <= 1'b0 ;      xya2b71 <= 1'b0 ;      wy15b8b <= 1'b0 ;      doadc58 <= 1'b0 ;      vv6e2c2 <= 1'b0 ;      jp71616 <= 1'b0 ;      vx8b0b6 <= 1'b0 ;      vi585b7 <= 1'b0 ;      fnc2dbb <= 1'b0 ;   end   else begin      zz3d20b <= fa69a8f ;      xje905e <= ng25bf4 ;      by482f7 <= tj2dfa2 ;      of417ba <= sh6fd16 ;      jebdd4 <= pf7e8b5 ;      al5eea2 <= jc4d47a ;      shf7515 <= vka2d72 ;      tjba8ad <= jr16b93 ;      ykd456e <= jrb5c9f ;      xya2b71 <= al6a3d2 ;      wy15b8b <= ea727fc ;      doadc58 <= je93fe1 ;      vv6e2c2 <= ir9ff0b ;      vx8b0b6 <= ep8f4a4 ;                  vi585b7 <= pse1746 ;      fnc2dbb <= lsba33 ;   end\r
+end\r
+always @(posedge hb500c1 or negedge rst_n)\r
+begin  if(!rst_n) begin        yz8f885 <= 1'b1;        ps7c42c <= 1'b1;        end     else begin      yz8f885 <= ri14169;     ps7c42c <= qte721f;     end\r
+end\r
+always @(posedge hb500c1 or negedge rst_n) begin       if (!rst_n) begin       mg92a74 <= 2'd0 ;       gd953a1 <= 2'd0 ;       th74344 <= 1'b0 ;       wla1a26 <= 1'b0 ;       mtd134 <= 1'b0 ;        ww689a4 <= 1'b0 ;       hq1e17d <= 1'b0 ;       qgf0bea <= 1'b0 ;       end     else begin      mg92a74 <= qt7a525 ;    gd953a1 <= qvdf46 ;     th74344 <= rv2d351 ;    wla1a26 <= qg46b44 ;    mtd134 <= oh2c505 ;     ww689a4 <= vkad103 ;    hq1e17d <= rt6b020 ;    qgf0bea <= icfae0d ;    end\r
+end\r
+assign ng3a962 =  ((sh6fd16 == tj81e62) & jrb5c9f) ;\r
+assign cmd4b12 =  ((sh6fd16 == jc798b9) & jrb5c9f) ;\r
+assign bna5890 =  ((sh6fd16 == an172e1) & ~jrb5c9f) ;\r
+assign an2c486  =  ((sh6fd16 == ieb970c)  & ~jrb5c9f) ;\r
+assign yk62435  = ~((sh6fd16 ==  tj81e62) & jrb5c9f) ;\r
+always @(posedge hb500c1 or negedge rst_n) begin   if (!rst_n) begin      rv16dde <= 1'b0 ;      swb6ef7 <= 1'b0 ;      ngb77b8 <= 1'b0 ;      epbbdc3  <= 1'b0 ;      icdee1c  <= 1'b0 ;   end   else begin      rv16dde <= bl551df ;      swb6ef7 <= vka8eff ;      ngb77b8 <= ho477fa ;      epbbdc3  <= ie3bfd3 ;      icdee1c  <= psdfe98 ;   end\r
+end\r
+assign cb121a8 = (((sh6fd16 == tj81e62) &  jrb5c9f ) &                        (                      ~jr16b93 ) &                        ((ng25bf4 == tj81e62) &  vka2d72 )                       ) ;\r
+assign an90d44 = (((sh6fd16 == tj81e62) &  jrb5c9f ) &                        (((tj2dfa2 == an172e1) |                          (tj2dfa2 == ieb970c)) & ~jr16b93 ) &                        ((ng25bf4 == jce1801) &  ~vka2d72 )                       ) ;\r
+assign je86a24 = (((sh6fd16 == czcc5cb) & jrb5c9f ) &                        ((tj2dfa2 == ui62e5c) & jr16b93 ) &                        ((ng25bf4 == tj81e62) & vka2d72 )                       ) ;\r
+assign vk35122 = (((sh6fd16 == czcc5cb) & jrb5c9f ) &                        ((tj2dfa2 == ui62e5c) & jr16b93 ) &                        ((ng25bf4 == ui62e5c) & vka2d72 )                       ) ;\r
+assign lsa8912 = (((sh6fd16 == ui62e5c) & jrb5c9f ) &                        ((tj2dfa2 == ui62e5c) & jr16b93 ) &                        ((ng25bf4 == ui62e5c) & vka2d72 )                       ) ;\r
+assign gb44892 = (((sh6fd16 == ui62e5c) & jrb5c9f ) &                        ((tj2dfa2 == ui62e5c) & jr16b93 ) &                        ((ng25bf4 == tj81e62) & vka2d72 )                       ) ;\r
+assign aa24495 = (((sh6fd16 == ui62e5c) & jrb5c9f ) &                        ((tj2dfa2 == ui62e5c) & jr16b93 ) &                        ((ng25bf4 == jc798b9) & vka2d72 )                       ) ;\r
+always @(posedge hb500c1 or negedge rst_n) begin   if (!rst_n) begin      enf70e1 <= 1'b0 ;      jeb870d <= 1'b0 ;      yxc386a <= 1'b0 ;      nt1c354 <= 1'b0 ;      rge1aa7 <= 1'b0 ;      yzd53a <= 1'b0 ;      qt6a9d4 <= 1'b0 ;   end   else begin      enf70e1 <= goff4c3 ;      jeb870d <= cmfa619 ;      yxc386a <= yxd30c9 ;      nt1c354 <= sw9864c ;      rge1aa7 <= gbc3261 ;      yzd53a <= db1930d ;      qt6a9d4 <= qtc986f ;   end\r
+end\r
+   assign xl224a9   = (ip6fa35 == 2'b01) ;   assign ux1254e  = (ip6fa35 == 2'b10) ;\r
+always @(posedge hb500c1 or negedge rst_n) begin   if (!rst_n)      yx54ea5 <= zm15a8 ;   else if (qv390fc)      yx54ea5 <= zm15a8 ;   else if (!ip4bc7b)      yx54ea5 <= qi2b5 ;   else      yx54ea5 <= ntaaa3b ;\r
+end\r
+always @(dmd5547 or lsba33 or dz61be8 or go4c37d or yzae4ff or cmff85d or         ba9c365 or zke1b2b or kfd95a or lq6cad5 or         gb656aa or qi2b555 or vv5aaa8 or         ipe8cd3 or go4669c or cb334e1 or ux9a70d or shd386c ) begin   case (dmd5547)      qi2b5 :         twa752c = zm15a8 ;      zm15a8 :         if (ipe8cd3 && lsba33)            twa752c = swad42 ;         else            twa752c = zm15a8 ;      swad42 :         if (cb334e1 || ux9a70d)            twa752c = su56a10 ;         else if (!dz61be8 && (yzae4ff || cmff85d))            twa752c = by42073 ;         else if ((!dz61be8 && (!yzae4ff && !cmff85d) && !cb334e1 && !ux9a70d) ||                  (dz61be8 && !cb334e1 && !ux9a70d))            twa752c = mg1039b ;         else            twa752c = swad42 ;      su56a10 :         if (!yzae4ff && !cmff85d)            twa752c = dbb5081 ;         else            twa752c = by42073 ;      dbb5081 :         if (!yzae4ff && !cmff85d)            twa752c = xya840e ;         else            twa752c = by42073 ;      xya840e :         if (ipe8cd3 && lsba33)            twa752c = swad42 ;         else if (!ipe8cd3 || !lsba33)            twa752c = by42073 ;         else            twa752c = xya840e ;      by42073 :         if (ipe8cd3 && lsba33)            twa752c = swad42;         else if (!ipe8cd3 && lsba33)            twa752c = zm15a8;         else            twa752c = by42073;      mg1039b :         if (!ipe8cd3 && !dz61be8)            twa752c = by42073;         else if (dz61be8 && shd386c)            if (!go4669c)               twa752c = hd81cd9;            else               twa752c = jee6cf;         else if ((dz61be8 && !shd386c) || ipe8cd3)            twa752c = swad42;         else            twa752c = mg1039b;      hd81cd9 :         if (ipe8cd3 && lsba33)            twa752c = swad42;         else            twa752c = hd81cd9;      jee6cf :         if ((ba9c365 || zke1b2b) && lsba33)            twa752c = dm7367b;         else if (kfd95a && lsba33)            twa752c = db9b3db;         else if (lq6cad5)            twa752c = mrd9ede;         else if (gb656aa)            twa752c = ykdbd1f;         else if (!yzae4ff && !cmff85d)            twa752c = zx7b7a3;         else            twa752c = facf6f4;      dm7367b :         if (!cb334e1 && !ux9a70d)            twa752c = mg1039b;         else            twa752c = su56a10;      db9b3db :         if (ipe8cd3)            twa752c = swad42;         else            twa752c = db9b3db;      mrd9ede :         if (gb656aa)            twa752c = mrd9ede;         else if (qi2b555 && lsba33)            twa752c = db9b3db;         else if (vv5aaa8)            twa752c = ayde8f9;         else            twa752c = rgf47c9;      facf6f4 :         if ((ba9c365 || zke1b2b) && lsba33)            twa752c = dm7367b;         else if (kfd95a && lsba33)            twa752c = db9b3db;         else if (lq6cad5)            twa752c = mrd9ede;         else if (gb656aa)            twa752c = ykdbd1f;         else if (!yzae4ff && !cmff85d)            twa752c = zx7b7a3;         else            twa752c = facf6f4;      zx7b7a3 :         if ((ba9c365 || zke1b2b) && lsba33)            twa752c = dm7367b;         else if (kfd95a && lsba33)            twa752c = db9b3db;         else if (lq6cad5)            twa752c = mrd9ede;         else if (gb656aa)            twa752c = ykdbd1f;         else if (!yzae4ff && !cmff85d)            twa752c = zx7b7a3;         else            twa752c = facf6f4;      ykdbd1f :         if (gb656aa)            twa752c = mrd9ede;         else if (qi2b555 && lsba33)            twa752c = db9b3db;         else if (vv5aaa8)            twa752c = ayde8f9;         else            twa752c = rgf47c9;      ayde8f9 :         if (go4669c)            twa752c = jee6cf;         else            twa752c = ayde8f9;      rgf47c9 :         if (go4669c)            twa752c = jee6cf;         else if (ipe8cd3 && lsba33)            twa752c = swad42;         else if (!go4669c && !ipe8cd3 && lsba33)            if (gb656aa)               twa752c = mrd9ede;            else if (qi2b555 && lsba33)               twa752c = db9b3db;            else if (vv5aaa8)               twa752c = ayde8f9;            else               twa752c = rgf47c9;         else            twa752c = rgf47c9;      default :         twa752c = zm15a8;   endcase\r
+end\r
+always @(posedge hb500c1 or negedge rst_n) begin   if(!rst_n)      eca3e4a <= 1'b0;   else if (dmd5547 == hd81cd9 || dmd5547 == dm7367b ||            dmd5547 == facf6f4 || dmd5547 == ykdbd1f ||            dmd5547 == mrd9ede || (dmd5547 == qi2b5 && gda4b7e))      eca3e4a <= 1'b1;   else if (dmd5547 == dbb5081 || dmd5547 == xya840e || dmd5547 == by42073 ||            dmd5547 == rgf47c9 || dmd5547 == ayde8f9)      eca3e4a <= hbd292d;   else      eca3e4a <= 1'b0;\r
+end\r
+always @(posedge hb500c1 or negedge rst_n) begin   if(!rst_n)      vx8467a <= 1'b0;   else if (dmd5547 == jee6cf)      vx8467a <= 1'b1;   else if (dmd5547 == dbb5081 || dmd5547 == xya840e || dmd5547 == by42073 ||            dmd5547 == hd81cd9 || (dmd5547 == qi2b5 && gda4b7e == 1'b1) ||            dmd5547 == dm7367b || dmd5547 == facf6f4 ||            dmd5547 == zx7b7a3 || dmd5547 == ykdbd1f)      vx8467a <= vx8467a;   else      vx8467a <= 1'b0;\r
+end\r
+always @(posedge hb500c1 or negedge rst_n) begin   if(!rst_n)      lqd08cf <= 8'b00000000;   else if (dmd5547 == jee6cf)      lqd08cf <= 8'b01010101;   else if (dmd5547 == ayde8f9 || dmd5547 == mrd9ede)      lqd08cf <= 8'b00001111;   else if (dmd5547 == rgf47c9)      lqd08cf <= 8'b00011111;   else if (dmd5547 == hd81cd9)      lqd08cf <= 8'b00001110;   else if (dmd5547 == zx7b7a3)      lqd08cf <= tuf45ae;   else      lqd08cf <= 8'b00000000;\r
+end\r
+always @(posedge hb500c1 or negedge rst_n) begin   if(!rst_n)      uv511a7 <= 1'b0;   else if (dmd5547 == mg1039b && dz61be8 && shd386c)      uv511a7 <= 1'b1;   else if (dmd5547 == db9b3db || (dmd5547 == qi2b5 && gda4b7e) ||            dmd5547 == zm15a8 || dmd5547 == swad42 ||            dmd5547 == su56a10 || dmd5547 == mg1039b)      uv511a7 <= 1'b0;   else      uv511a7 <= gda4b7e;\r
+end         always @(posedge hb500c1 or negedge rst_n) begin      if(!rst_n) begin         xj45a69 <= 16'h0000;      end      else if(dmd5547 == dbb5081) begin         xj45a69[7:0]  <= tuf45ae;         xj45a69[15:8] <= xj45a69[15:8];      end      else if(dmd5547 == xya840e) begin         xj45a69[ 7:0] <= xj45a69[7:0];         xj45a69[15:8] <= tuf45ae;      end      else         xj45a69 <= xj45a69;   end\r
+         always @(posedge hb500c1 or negedge rst_n) begin      if(!rst_n)         vieee84 <= 1'b0;      else if(dmd5547 == xya840e)         vieee84 <= 1'b1;      else         vieee84 <= 1'b0;   end   always @(posedge hb500c1 or negedge rst_n) begin      if(!rst_n)         kq77423 <= 1'b0;      else if(dmd5547 == mg1039b)         kq77423 <= 1'b1;      else         kq77423 <= 1'b0;   end   always @(posedge hb500c1 or negedge rst_n) begin      if(!rst_n)         hdba119 <= 1'b0;      else if((dmd5547 == by42073  && go4c37d) ||            (dmd5547 == qi2b5 && !dz61be8))         hdba119 <= 1'b1;      else         hdba119 <= 1'b0;   end\r
+assign aa1f251 = zm35a20                  ? (hbd292d & vx8467a) : hbd292d;\r
+assign oh233d6     = (kq6881b & !rtd7068)  ?  tj9496f                : hbd292d;\r
+always @(dmd5547)\r
+begin  case (dmd5547)  qi2b5   : aa3482d = "LNK_FAIL"; zm15a8  : aa3482d = "WAIT_K";   swad42  : aa3482d = "RX_K";     su56a10 : aa3482d = "RX_CB";    dbb5081 : aa3482d = "RX_CC";    xya840e : aa3482d = "RX_CD";    by42073 : aa3482d = "RX_INV";   mg1039b : aa3482d = "IDL_D";    hd81cd9 : aa3482d = "FLS_CARR"; jee6cf  : aa3482d = "SOP";      dm7367b : aa3482d = "ERLY_END"; db9b3db : aa3482d = "TRI_RRI";  mrd9ede : aa3482d = "TRR_EXT";  facf6f4 : aa3482d = "RXD_ERR";  zx7b7a3 : aa3482d = "RX_D";     ykdbd1f : aa3482d = "EEND_EXT"; ayde8f9 : aa3482d = "PKT_BRRS"; rgf47c9 : aa3482d = "EXT_ERR";  default : aa3482d = " ERROR ";  endcase\r
+end\r
+always@* begin ri14169<=vx8bfb1[0];oh2c505<=vx8bfb1[1];rt6b020<=vx8bfb1[2];rv2d351<=vx8bfb1[3];fa69a8f<={rx_data>>1,vx8bfb1[4]};jc4d47a<=vx8bfb1[5];al6a3d2<=vx8bfb1[6];ip4bc7b<=vx8bfb1[7];ep8f4a4<=vx8bfb1[8];qt7a525<={tu69a7f>>1,vx8bfb1[9]};hbd292d<=vx8bfb1[10];tj9496f<=vx8bfb1[11];gda4b7e<=vx8bfb1[12];ng25bf4<={zz3d20b>>1,vx8bfb1[13]};tj2dfa2<={xje905e>>1,vx8bfb1[14]};sh6fd16<={by482f7>>1,vx8bfb1[15]};pf7e8b5<={of417ba>>1,vx8bfb1[16]};tuf45ae<={jebdd4>>1,vx8bfb1[17]};vka2d72<=vx8bfb1[18];jr16b93<=vx8bfb1[19];jrb5c9f<=vx8bfb1[20];yzae4ff<=vx8bfb1[21];ea727fc<=vx8bfb1[22];je93fe1<=vx8bfb1[23];ir9ff0b<=vx8bfb1[24];cmff85d<=vx8bfb1[25];vvfc2e8<=vx8bfb1[26];pse1746<=vx8bfb1[27];lsba33<=vx8bfb1[28];ps5d19a<=vx8bfb1[29];ipe8cd3<=vx8bfb1[30];go4669c<=vx8bfb1[31];cb334e1<=vx8bfb1[32];ux9a70d<=vx8bfb1[33];shd386c<=vx8bfb1[34];ba9c365<=vx8bfb1[35];zke1b2b<=vx8bfb1[36];kfd95a<=vx8bfb1[37];lq6cad5<=vx8bfb1[38];gb656aa<=vx8bfb1[39];qi2b555<=vx8bfb1[40];vv5aaa8<=vx8bfb1[41];dmd5547<={yx54ea5>>1,vx8bfb1[42]};ntaaa3b<={twa752c>>1,vx8bfb1[43]};bl551df<=vx8bfb1[44];vka8eff<=vx8bfb1[45];ho477fa<=vx8bfb1[46];ie3bfd3<=vx8bfb1[47];psdfe98<=vx8bfb1[48];goff4c3<=vx8bfb1[49];cmfa619<=vx8bfb1[50];yxd30c9<=vx8bfb1[51];sw9864c<=vx8bfb1[52];gbc3261<=vx8bfb1[53];db1930d<=vx8bfb1[54];qtc986f<=vx8bfb1[55];go4c37d<=vx8bfb1[56];dz61be8<=vx8bfb1[57];qvdf46<={mg92a74>>1,vx8bfb1[58]};ip6fa35<={gd953a1>>1,vx8bfb1[59]};qte721f<=vx8bfb1[60];qv390fc<=vx8bfb1[61];qg46b44<=vx8bfb1[62];zm35a20<=vx8bfb1[63];vkad103<=vx8bfb1[64];kq6881b<=vx8bfb1[65];icfae0d<=vx8bfb1[66];rtd7068<=vx8bfb1[67];hd3623<={aa3482d>>1,vx8bfb1[68]};end\r
+always@* begin ead17f6[2047]<=sgmii_mode;ead17f6[2046]<=gbe_mode;ead17f6[2044]<=qif9e9;ead17f6[2040]<=rx_data[0];ead17f6[2032]<=rx_kcntl;ead17f6[2016]<=tj3d21d;ead17f6[1985]<=ira1445;ead17f6[1927]<=th74344;ead17f6[1922]<=rx_even;ead17f6[1867]<=shf7515;ead17f6[1807]<=wla1a26;ead17f6[1804]<=an2c486;ead17f6[1797]<=tu69a7f[0];ead17f6[1761]<=ng3a962;ead17f6[1686]<=tjba8ad;ead17f6[1623]<=gb44892;ead17f6[1567]<=mtd134;ead17f6[1561]<=yk62435;ead17f6[1558]<=vi585b7;ead17f6[1547]<=eca3e4a;ead17f6[1542]<=jeb870d;ead17f6[1505]<=yz8f885;ead17f6[1490]<=jebdd4[0];ead17f6[1475]<=cmd4b12;ead17f6[1413]<=jp71616;ead17f6[1409]<=icdee1c;ead17f6[1400]<=mg92a74[0];ead17f6[1324]<=ykd456e;ead17f6[1200]<=wy15b8b;ead17f6[1199]<=aa24495;ead17f6[1086]<=ww689a4;ead17f6[1074]<=cb121a8;ead17f6[1068]<=fnc2dbb;ead17f6[1047]<=aa1f251;ead17f6[1037]<=yxc386a;ead17f6[1023]<=mr_main_reset;ead17f6[963]<=ps7c42c;ead17f6[933]<=al5eea2;ead17f6[902]<=bna5890;ead17f6[880]<=twa752c[0];ead17f6[811]<=lsa8912;ead17f6[779]<=vx8b0b6;ead17f6[771]<=enf70e1;ead17f6[752]<=gd953a1[0];ead17f6[745]<=of417ba[0];ead17f6[706]<=vv6e2c2;ead17f6[704]<=epbbdc3;ead17f6[700]<=ux1254e;ead17f6[600]<=xya2b71;ead17f6[503]<=aa3482d[1];ead17f6[440]<=yx54ea5[0];ead17f6[405]<=vk35122;ead17f6[372]<=by482f7[0];ead17f6[353]<=doadc58;ead17f6[352]<=ngb77b8;ead17f6[350]<=xl224a9;ead17f6[251]<=qgf0bea;ead17f6[220]<=qt6a9d4;ead17f6[202]<=je86a24;ead17f6[186]<=xje905e[0];ead17f6[176]<=swb6ef7;ead17f6[125]<=hq1e17d;ead17f6[110]<=yzd53a;ead17f6[101]<=an90d44;ead17f6[93]<=zz3d20b[0];ead17f6[88]<=rv16dde;ead17f6[55]<=rge1aa7;ead17f6[46]<=uv511a7;ead17f6[27]<=nt1c354;end         assign jebdc77 = ead17f6,vx8bfb1 = fn71dda; initial begin kfbe35f = $fopen(".fred"); $fdisplay( kfbe35f, "%3h\n%3h", (fnf63ba >> 4) & fpbaf71, (fnf63ba >> (tj8eebd+4)) & fpbaf71 ); $fclose(kfbe35f); $readmemh(".fred", ay776be); end always @ (jebdc77) begin nedaf8d = ay776be[1]; for (jcf1afd=0; jcf1afd<th5fd8e; jcf1afd=jcf1afd+1) begin fn71dda[jcf1afd] = jebdc77[nedaf8d]; thd7c6b = ^(nedaf8d & ay776be[0]); nedaf8d = {nedaf8d, thd7c6b}; end end\r
+endmodule\r
+`timescale 1 ns / 100 ps\r
+module enc9ddb (\r
+   hb500c1 ,\r
+   rst_n ,\r
+   mr_main_reset ,\r
+   signal_detect ,\r
+   rx_data ,\r
+   rx_kcntl ,\r
+   tj3d21d ,\r
+   ira1445 ,\r
+   rx_even\r
+   );\r
+input                hb500c1 ;\r
+input                rst_n ;\r
+input                mr_main_reset ;\r
+input                signal_detect ;\r
+input [7:0]          rx_data ;\r
+input                rx_kcntl ;\r
+input                tj3d21d ;\r
+output               ira1445 ;\r
+output               rx_even ;\r
+localparam vx13796          = 4'b0000 ,          xl9bcb6     = 4'b0001 ,          sude5b7    = 4'b0010 ,          czf2db8     = 4'b0011 ,          pu96dc4    = 4'b0100 ,          cob6e23     = 4'b0101 ,          pub7118   = 4'b0110 ,          twb88c3   = 4'b0111 ,          cmc461b  = 4'b1000 ,          sj230d8   = 4'b1001 ,          gd186c4  = 4'b1010 ,          ofc3625   = 4'b1011 ,          ng1b12d  = 4'b1100 ;\r
+reg         ira1445 ;\r
+reg         rx_even ;\r
+reg [3:0]   vk25ab1 ;\r
+reg [3:0]   fp2d58a ;\r
+reg [1:0]   of6ac57 ;\r
+reg         go562bd ;\r
+reg         gdb15e8 ;\r
+reg yz8f885 ;\r
+reg ps7c42c ;\r
+reg         fcbd123 ;\r
+reg         she891a ;\r
+reg         kd448d4 ;\r
+wire        gq246a5 ;\r
+reg         sj23529 ;\r
+reg         ec1a94c ;\r
+reg         wwd4a61 ;\r
+reg  [(20*8):1] fpa5308;\r
+reg ri14169;\r
+reg ww4c23c;\r
+reg [7 : 0] fa69a8f;\r
+reg jc4d47a;\r
+reg al6a3d2;\r
+reg [3 : 0] sj3c1ea;\r
+reg [3 : 0] qge0f54;\r
+reg [1 : 0] qv7aa0;\r
+reg bn3d504;\r
+reg kqea826;\r
+reg qte721f;\r
+reg qv390fc;\r
+reg fc4c6e;\r
+reg ux26373;\r
+reg uk31b9c;\r
+reg gq8dce1;\r
+reg hb6e709;\r
+reg zk7384e;\r
+reg ri9c272;\r
+reg [(20 * 8) : 1] xwe1393;\r
+reg [2047:0] ead17f6;\r
+wire [19:0] vx8bfb1;\r
+localparam th5fd8e = 20,nefec77 = 32'hfdffe0cb;\r
+localparam [31:0] fnf63ba = nefec77;\r
+localparam tj8eebd = nefec77 & 4'hf;\r
+localparam [11:0] fpbaf71 = 'h7ff;\r
+wire [(1 << tj8eebd) -1:0] jebdc77;\r
+reg [th5fd8e-1:0] fn71dda;\r
+reg [tj8eebd-1:0] ay776be [0:1];\r
+reg [tj8eebd-1:0] nedaf8d;\r
+reg thd7c6b;\r
+integer kfbe35f;\r
+integer jcf1afd;\r
+assign gq246a5 = ( jc4d47a & (fa69a8f[5:0] == 6'b111100) &                                ((fa69a8f[7:6] == 2'b00) |                                 (fa69a8f[7:6] == 2'b10) |                                 (fa69a8f[7:6] == 2'b11)));\r
+always @(posedge hb500c1 or negedge rst_n)\r
+begin  if(!rst_n) begin        yz8f885 <= 1'b1;        ps7c42c <= 1'b1;        end     else begin      yz8f885 <= ri14169;     ps7c42c <= qte721f;     end\r
+end\r
+always @(posedge hb500c1 or negedge rst_n) begin   if (!rst_n) begin      wwd4a61 <= 1'b0 ;      sj23529     <= 1'b0 ;      ec1a94c     <= 1'b0 ;   end   else  begin      wwd4a61 <= gq8dce1 & ~al6a3d2;      sj23529     <= (al6a3d2 | (gq8dce1 & uk31b9c));      ec1a94c     <= ~jc4d47a & ~hb6e709 ;   end\r
+end\r
+always @(posedge hb500c1 or negedge rst_n) begin   if (!rst_n) begin      go562bd <= 1'b0 ;      gdb15e8 <= 1'b0 ;      fcbd123 <= 1'b0 ;      she891a   <= 1'b0 ;      kd448d4  <= 1'b0 ;   end   else  begin      go562bd <= ww4c23c ;            gdb15e8 <= bn3d504 ;       fcbd123 <= kqea826 ;      she891a   <= (kqea826 ^ fc4c6e) ;      kd448d4  <= rx_even ;   end\r
+end\r
+always @(posedge hb500c1 or negedge rst_n) begin   if(!rst_n)      vk25ab1 <= vx13796 ;   else if (qv390fc || ux26373)      vk25ab1 <= vx13796 ;   else      vk25ab1 <= qge0f54 ;\r
+end\r
+always @(sj3c1ea or ri9c272 or zk7384e or qv7aa0 or rx_even or hb6e709) begin   case (sj3c1ea)      vx13796 :         if (ri9c272 && fc4c6e)            fp2d58a = xl9bcb6 ;         else            fp2d58a = vx13796 ;      xl9bcb6 :         if (zk7384e)            fp2d58a = sude5b7 ;         else            fp2d58a = vx13796 ;      sude5b7 :         if (!rx_even && ri9c272)            fp2d58a = czf2db8 ;         else if (hb6e709)            fp2d58a = vx13796 ;         else            fp2d58a = sude5b7 ;      czf2db8 :         if (zk7384e)            fp2d58a = pu96dc4 ;         else            fp2d58a = vx13796 ;      pu96dc4 :          if (!rx_even && ri9c272)            fp2d58a = cob6e23 ;          else if (hb6e709)            fp2d58a = vx13796 ;          else            fp2d58a = pu96dc4 ;      cob6e23:   if (zk7384e)             fp2d58a = pub7118;           else             fp2d58a = vx13796;      pub7118:         if (hb6e709)            fp2d58a = twb88c3;         else            fp2d58a = pub7118;      twb88c3:         if (hb6e709)            fp2d58a = sj230d8;         else            fp2d58a = cmc461b;      cmc461b:         if (hb6e709)            fp2d58a = sj230d8;         else if (qv7aa0 == 2'b11)            fp2d58a = pub7118;         else            fp2d58a = cmc461b;      sj230d8:         if (hb6e709)            fp2d58a = ofc3625;         else            fp2d58a = gd186c4;      gd186c4:         if (hb6e709)            fp2d58a = ofc3625;         else if (qv7aa0 == 2'b11)            fp2d58a = twb88c3;         else            fp2d58a = gd186c4;      ofc3625:         if (hb6e709)            fp2d58a = vx13796;         else            fp2d58a = ng1b12d;      ng1b12d:         if (hb6e709)            fp2d58a = vx13796;         else if (qv7aa0 == 2'b11)            fp2d58a = sj230d8;         else            fp2d58a = ng1b12d;      default:         fp2d58a = vx13796;   endcase\r
+end\r
+always @(posedge hb500c1 or negedge rst_n) begin   if (!rst_n)      of6ac57 <= 2'b00;   else if ((sj3c1ea == cmc461b) ||            (sj3c1ea == gd186c4) ||            (sj3c1ea == ng1b12d))      of6ac57 <= qv7aa0 + 1'b1;   else      of6ac57 <= 2'b00;\r
+end\r
+always @(posedge hb500c1 or negedge rst_n) begin   if (!rst_n)      ira1445 <= 1'b0;   else if (sj3c1ea == vx13796)      ira1445 <= 1'b0;   else if (sj3c1ea == pub7118)      ira1445 <= 1'b1;   else      ira1445 <= ira1445 ;\r
+end\r
+always @(sj3c1ea or uk31b9c) begin   case (sj3c1ea)      xl9bcb6, czf2db8, cob6e23 :         rx_even = 1'b1 ;      vx13796, sude5b7, pu96dc4,      pub7118, twb88c3, sj230d8, ofc3625,      cmc461b, gd186c4, ng1b12d :         rx_even = ~uk31b9c ;      default :         rx_even = 1'b0;   endcase\r
+end\r
+always @(sj3c1ea)\r
+begin  case (sj3c1ea)  vx13796 : fpa5308 = "LOS";      xl9bcb6 : fpa5308 = "COM_DET1"; sude5b7 : fpa5308 = "AQR_SYNC1";        czf2db8 : fpa5308 = "COM_DET2"; pu96dc4 : fpa5308 = "AQR_SYNC2";        cob6e23 : fpa5308 = "COM_DET3"; pub7118 : fpa5308 = "SYNC_AQRD1";       twb88c3 : fpa5308 = "SYNC_AQRD2";       cmc461b : fpa5308 = "SYNC_AQRD2A";      sj230d8 : fpa5308 = "SYNC_AQRD3";       gd186c4 : fpa5308 = "SYNC_AQRD3A";      ofc3625 : fpa5308 = "SYNC_AQRD4";       ng1b12d : fpa5308 = "SYNC_AQRD4A";      default : fpa5308 = " ERROR ";  endcase\r
+end\r
+always@* begin ri14169<=vx8bfb1[0];ww4c23c<=vx8bfb1[1];fa69a8f<={rx_data>>1,vx8bfb1[2]};jc4d47a<=vx8bfb1[3];al6a3d2<=vx8bfb1[4];sj3c1ea<={vk25ab1>>1,vx8bfb1[5]};qge0f54<={fp2d58a>>1,vx8bfb1[6]};qv7aa0<={of6ac57>>1,vx8bfb1[7]};bn3d504<=vx8bfb1[8];kqea826<=vx8bfb1[9];qte721f<=vx8bfb1[10];qv390fc<=vx8bfb1[11];fc4c6e<=vx8bfb1[12];ux26373<=vx8bfb1[13];uk31b9c<=vx8bfb1[14];gq8dce1<=vx8bfb1[15];hb6e709<=vx8bfb1[16];zk7384e<=vx8bfb1[17];ri9c272<=vx8bfb1[18];xwe1393<={fpa5308>>1,vx8bfb1[19]};end\r
+always@* begin ead17f6[2047]<=signal_detect;ead17f6[2046]<=rx_data[0];ead17f6[2044]<=rx_kcntl;ead17f6[2040]<=tj3d21d;ead17f6[2033]<=vk25ab1[0];ead17f6[2018]<=fp2d58a[0];ead17f6[1988]<=of6ac57[0];ead17f6[1929]<=go562bd;ead17f6[1811]<=gdb15e8;ead17f6[1789]<=wwd4a61;ead17f6[1574]<=yz8f885;ead17f6[1530]<=fpa5308[1];ead17f6[1247]<=gq246a5;ead17f6[1101]<=ps7c42c;ead17f6[1023]<=mr_main_reset;ead17f6[894]<=ec1a94c;ead17f6[623]<=kd448d4;ead17f6[447]<=sj23529;ead17f6[311]<=she891a;ead17f6[155]<=fcbd123;end         assign jebdc77 = ead17f6,vx8bfb1 = fn71dda; initial begin kfbe35f = $fopen(".fred"); $fdisplay( kfbe35f, "%3h\n%3h", (fnf63ba >> 4) & fpbaf71, (fnf63ba >> (tj8eebd+4)) & fpbaf71 ); $fclose(kfbe35f); $readmemh(".fred", ay776be); end always @ (jebdc77) begin nedaf8d = ay776be[1]; for (jcf1afd=0; jcf1afd<th5fd8e; jcf1afd=jcf1afd+1) begin fn71dda[jcf1afd] = jebdc77[nedaf8d]; thd7c6b = ^(nedaf8d & ay776be[0]); nedaf8d = {nedaf8d, thd7c6b}; end end\r
+endmodule\r
+`timescale 1 ns / 100 ps\r
+module vk96fe1 (\r
+       rst_n,\r
+       mr_main_reset,\r
+       an_link_ok,\r
+       lqe16b6,\r
+       gbe_mode,\r
+       operational_rate,\r
+       kdd6cdf,\r
+       oub66fd,\r
+       ksb37e9,\r
+       hd9bf49,\r
+       vidfa4f,\r
+       enfd27b,\r
+       lde93dc,\r
+       ic49ee7,\r
+       xj4f739,\r
+       ctc_drop_flag,\r
+       ctc_add_flag\r
+);\r
+input  rst_n;\r
+input  mr_main_reset;\r
+input  an_link_ok;\r
+input  lqe16b6;\r
+input  gbe_mode;\r
+input [1:0]    operational_rate;\r
+input  kdd6cdf;\r
+input [7:0]    oub66fd;\r
+input  ksb37e9;\r
+input  hd9bf49;\r
+input  vidfa4f;\r
+output [7:0]   enfd27b;\r
+output lde93dc;\r
+output ic49ee7;\r
+output xj4f739;\r
+output ctc_drop_flag;\r
+output ctc_add_flag;\r
+parameter DYNAMIC_LT_10MBPS = 340;\r
+parameter DYNAMIC_HT_10MBPS = 680;\r
+parameter DYNAMIC_LT_100MBPS = 34;\r
+parameter DYNAMIC_HT_100MBPS = 68;\r
+parameter DYNAMIC_LT_1000MBPS = 16;\r
+parameter DYNAMIC_HT_1000MBPS = 32;\r
+localparam     pha0d17 = 2'd0, jr68be  = 2'd1, uk345f6 = 2'd2, doa2fb0 = 2'd3;\r
+reg[1:0] ux17d83;\r
+localparam     sjbec1d = 3'd0, thf60ec = 3'd1, bnb0767 = 3'd2, hq83b3e = 3'd3, gd1d9f2 = 3'd4, ldecf94 = 3'd5;\r
+reg [2:0] ea67ca6;\r
+reg [7:0] aa3e531;\r
+reg ipf2989;\r
+reg nt94c4c ;\r
+reg [7:0] iea6266;\r
+reg co31330;\r
+reg pu89980 ;\r
+reg [7:0] yk4cc03;\r
+reg tu66019;\r
+reg ng300ca ;\r
+reg an80652;\r
+reg db3294;\r
+reg fp194a7;\r
+reg faca53f;\r
+reg xw529fb;\r
+reg rv94fdb;\r
+reg pua7ede;\r
+reg hqa7cad;\r
+reg [7:0] enfd27b;\r
+reg lde93dc;\r
+reg ic49ee7;\r
+wire [7:0] end69f2;\r
+wire nt9b647;\r
+wire tj275a7;\r
+wire gbd91f0;\r
+wire pfc8f85;\r
+wire zk47c2f;\r
+reg sw3e17a;\r
+wire uxb4f95;\r
+reg ir85e89;\r
+reg ri2f44d;\r
+reg cz7a26a;\r
+reg wwd1355;\r
+reg hq89aa9;\r
+reg ne4d54b;\r
+reg gb6aa5a;\r
+wire xj4f739;\r
+wire [7:0] oua96af;\r
+reg [1:0] dz40186;\r
+reg [1:0] ymc36;\r
+reg [1:0] tud5e6f;\r
+reg [1:0] hdaf37a;\r
+reg zk79bd6;\r
+reg blcdeb3;\r
+reg sh6f59f;\r
+reg kd7acfc;\r
+reg cb363da;\r
+reg ecb3f24;\r
+reg gd9f920;\r
+reg pffc905;\r
+reg xwe482f;\r
+reg sw2417a;\r
+reg je20bd1;\r
+reg [9:0] ks5e8a;\r
+reg [9:0] hq2f451;\r
+reg hq1e17d;\r
+reg qgf0bea;\r
+reg [1:0] kf8a2a9;\r
+reg [1:0] mr5154d;\r
+reg gd8aa6d;\r
+reg dz5536c;\r
+reg ksa9b67;\r
+reg xw4db38;\r
+reg kq6d9c3 ;\r
+reg xw6ce18 ;\r
+reg ww670c2 ;\r
+reg nt38610 ;\r
+reg enc3086;\r
+reg mt18435;\r
+reg ctc_drop_flag;\r
+reg ou10d6f;\r
+reg ri86b78;\r
+reg ctc_add_flag;\r
+`ifdef SGMII_FIFO_FAMILY_SC\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP2M\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP3\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP5\r
+`endif\r
+reg  [(22*8):1] hqade13;\r
+reg  [(22*8):1] al6f09a;\r
+reg ri14169;\r
+reg jpc26a0;\r
+reg bn13507;\r
+reg rt6b020;\r
+reg [1 : 0] ead41f5;\r
+reg [7 : 0] vxa0fa9;\r
+reg ep7d4e;\r
+reg gq3ea74;\r
+reg [1 : 0] ykf53a0;\r
+reg [2 : 0] iea9d00;\r
+reg [7 : 0] ip4e800;\r
+reg th74004;\r
+reg xla0026;\r
+reg [7 : 0] wy137;\r
+reg uk9b8;\r
+reg je4dc1;\r
+reg [7 : 0] an26e0b;\r
+reg xl3705d;\r
+reg fcb82ef;\r
+reg qgc177a;\r
+reg zmbbd0;\r
+reg xw5de82;\r
+reg osef412;\r
+reg en7a090;\r
+reg ned0485;\r
+reg mg8242b;\r
+reg ba99e94;\r
+reg [7 : 0] dmda67a;\r
+reg oh85664;\r
+reg lf3699;\r
+reg go59920;\r
+reg kdcc900;\r
+reg nr64805;\r
+reg qi2402e;\r
+reg mrd33d2;\r
+reg qib8b;\r
+reg co5c59;\r
+reg uk2e2c9;\r
+reg bl71648;\r
+reg jr8b246;\r
+reg cm59237;\r
+reg ipc91b9;\r
+reg [7 : 0] rg48dcc;\r
+reg [1 : 0] xl9b4bd;\r
+reg [1 : 0] psda5ee;\r
+reg [1 : 0] mgb98c7;\r
+reg [1 : 0] alcc639;\r
+reg fa631cc;\r
+reg gd18e62;\r
+reg ldc7314;\r
+reg qv398a7;\r
+reg hoee5cb;\r
+reg ay629ec;\r
+reg vk14f61;\r
+reg vka7b0a;\r
+reg jr3d853;\r
+reg dzec29f;\r
+reg zx614ff;\r
+reg [9 : 0] mga7ff;\r
+reg [9 : 0] ay53ff9;\r
+reg icfae0d;\r
+reg rtd7068;\r
+reg [1 : 0] meff268;\r
+reg [1 : 0] blf9341;\r
+reg mrc9a0e;\r
+reg by4d075;\r
+reg me683aa;\r
+reg sh41d51;\r
+reg twea8d;\r
+reg cz7546a;\r
+reg rvaa354;\r
+reg cz51aa6;\r
+reg ym8d534;\r
+reg qt6a9a0;\r
+reg yx54d05;\r
+reg swa682c;\r
+reg [(22 * 8) : 1] ie34161;\r
+reg [(22 * 8) : 1] nta0b08;\r
+reg [2047:0] ead17f6;\r
+wire [77:0] vx8bfb1;\r
+`ifdef SGMII_FIFO_FAMILY_SC\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP2M\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP3\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP5\r
+`endif\r
+localparam th5fd8e = 78,nefec77 = 32'hfdffd48b;\r
+localparam [31:0] fnf63ba = nefec77;\r
+localparam tj8eebd = nefec77 & 4'hf;\r
+localparam [11:0] fpbaf71 = 'h7ff;\r
+wire [(1 << tj8eebd) -1:0] jebdc77;\r
+reg [th5fd8e-1:0] fn71dda;\r
+reg [tj8eebd-1:0] ay776be [0:1];\r
+reg [tj8eebd-1:0] nedaf8d;\r
+reg thd7c6b;\r
+integer kfbe35f;\r
+integer jcf1afd;\r
+`ifdef SGMII_FIFO_FAMILY_SC\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP2M\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP3\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP5\r
+`endif\r
+always @(posedge vidfa4f or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        ww670c2 <= 1'b1;        nt38610 <= 1'b1;        end     else begin      ww670c2 <= ri14169;     nt38610 <= rvaa354;     end\r
+end\r
+always @(posedge vidfa4f or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        hq1e17d <= 1'b0;        qgf0bea <= 1'b0;        end     else begin      hq1e17d <= rt6b020;     qgf0bea <= icfae0d;     end\r
+end\r
+always @(posedge vidfa4f or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        kf8a2a9 <= 2'b10;       mr5154d <= 2'b10;       end     else begin      kf8a2a9 <= ead41f5;     mr5154d <= meff268;     end\r
+end\r
+always @(posedge vidfa4f or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        gd8aa6d <= 1'b0;        dz5536c <= 1'b0;        ksa9b67 <= 1'b1;        xw4db38 <= 1'b1;        end     else begin      gd8aa6d <= jpc26a0;     dz5536c <= mrc9a0e;     ksa9b67 <= bn13507;     xw4db38 <= me683aa;     end\r
+end\r
+always @(posedge vidfa4f or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        dz40186 <= 2'b10;       ymc36 <= 2'b10; zk79bd6 <= 1'b1;        blcdeb3 <= 1'b1;        sh6f59f <= 1'b1;        kd7acfc <= 1'b1;        cb363da <= 1'b1;        end     else begin      if (rtd7068) begin      dz40186 <= 2'b10;       end     else if (by4d075 || (!sh41d51)) begin           dz40186 <= blf9341;     end     else begin      dz40186 <= 2'b10;       end             ymc36 <= xl9b4bd;               zk79bd6 <= xl9b4bd != psda5ee;  blcdeb3 <= fa631cc;     sh6f59f <= gd18e62;     kd7acfc <= ldc7314;             cb363da <= fa631cc | gd18e62 | ldc7314 | qv398a7;       end\r
+end\r
+always @(posedge kdd6cdf or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        kq6d9c3 <= 1'b1;        xw6ce18 <= 1'b1;        end     else begin      kq6d9c3 <= ri14169;     xw6ce18 <= twea8d;      end\r
+end\r
+always @(posedge kdd6cdf or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        tud5e6f <= 2'b10;       hdaf37a <= 2'b10;       end     else begin      tud5e6f <= xl9b4bd;     hdaf37a <= mgb98c7;     end\r
+end\r
+always @(posedge kdd6cdf or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        ecb3f24 <= 1'b1;        gd9f920 <= 1'b1;        pffc905 <= 1'b1;        end     else begin  if (cz7546a) begin  ecb3f24 <= 1'b1;        gd9f920 <= 1'b1;        pffc905 <= 1'b1;  end  else begin               ecb3f24 <= hoee5cb;     gd9f920 <= ay629ec;             pffc905 <= vk14f61;     end\r
+end\r
+end\r
+always @(posedge vidfa4f or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        xwe482f <= 1'b1;        sw2417a <= 1'b1;        je20bd1 <= 1'b1;        end     else begin  if (cz51aa6) begin  xwe482f <= 1'b1;        sw2417a <= 1'b1;        je20bd1 <= 1'b1;  end  else begin               xwe482f <= hoee5cb;     sw2417a <= jr3d853;             je20bd1 <= dzec29f;     end\r
+end\r
+end\r
+always @(posedge vidfa4f or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        ks5e8a <= 10'd16;       end     else begin      case (psda5ee)  2'd0: begin     ks5e8a <= DYNAMIC_LT_10MBPS;    end     2'd1: begin     ks5e8a <= DYNAMIC_LT_100MBPS;   end     2'd2: begin     ks5e8a <= DYNAMIC_LT_1000MBPS;  end     2'd3: begin     ks5e8a <= DYNAMIC_LT_1000MBPS;  end     default: begin  ks5e8a <= mga7ff;       end     endcase end\r
+end\r
+always @(posedge kdd6cdf or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        hq2f451 <= 10'd32;      end     else begin      case (alcc639)  2'd0: begin     hq2f451 <= DYNAMIC_HT_10MBPS;   end     2'd1: begin     hq2f451 <= DYNAMIC_HT_100MBPS;  end     2'd2: begin     hq2f451 <= DYNAMIC_HT_1000MBPS; end     2'd3: begin     hq2f451 <= DYNAMIC_HT_1000MBPS; end     default: begin  hq2f451 <= ay53ff9;     end     endcase end\r
+end\r
+always @(posedge kdd6cdf or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        aa3e531 <= 8'd0;        ipf2989 <= 1'b0;        nt94c4c <= 1'b0;        iea6266 <= 8'd0;        co31330 <= 1'b0;        pu89980 <= 1'b0;        yk4cc03 <= 8'd0;        tu66019 <= 1'b0;        ng300ca <= 1'b0;        end     else begin      aa3e531 <= vxa0fa9;     ipf2989 <= ep7d4e;      nt94c4c <= gq3ea74;     iea6266 <= ip4e800;     co31330 <= th74004;     pu89980 <= xla0026;     yk4cc03 <= wy137;       tu66019 <= uk9b8;       ng300ca <= je4dc1;      end\r
+end\r
+always @(posedge kdd6cdf or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        an80652 <= 1'b0;        db3294 <= 1'b0; fp194a7 <= 1'b0;        faca53f <= 1'b0;        xw529fb <= 1'b0;        rv94fdb <= 1'b0;        end     else begin              if ((th74004 == 1'b1) && (ip4e800 == 8'hBC)) begin      an80652 <= 1'b1;        end     else begin      an80652 <= 1'b0;        end\r
+               if ((ep7d4e == 1'b0) && (vxa0fa9 == 8'hC5)) begin       db3294 <= 1'b1; end     else begin      db3294 <= 1'b0; end             if ((ep7d4e == 1'b0) && (vxa0fa9 == 8'h50)) begin       fp194a7 <= 1'b1;        end     else begin      fp194a7 <= 1'b0;        end             if ((ep7d4e == 1'b0) && (vxa0fa9 == 8'h42)) begin       faca53f <= 1'b1;        end     else begin      faca53f <= 1'b0;        end             if ((ep7d4e == 1'b0) && (vxa0fa9 == 8'hB5)) begin       xw529fb <= 1'b1;        end     else begin      xw529fb <= 1'b0;        end             if (qgc177a && (osef412 || en7a090)) begin      rv94fdb <= 1'b1;        end     else begin      rv94fdb <= 1'b0;        end     end\r
+end\r
+always @(posedge kdd6cdf or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        ux17d83 <= pha0d17;     pua7ede <= 1'b0;        enc3086 <= 1'b0;        end     else begin  if (vka7b0a) begin  ux17d83 <= pha0d17;     pua7ede <= 1'b0;        enc3086 <= 1'b0;  end  else begin               enc3086 <= 1'b0;        case (ykf53a0)  pha0d17:        begin   if (kdcc900) begin                      if (qgc177a && (xw5de82 || osef412 || en7a090)) begin   pua7ede <= 1'b0;        ux17d83 <= jr68be;      enc3086 <= 1'b1;        end     end     else begin              pua7ede <= 1'b1;        ux17d83 <= pha0d17;     end     end     jr68be: begin           pua7ede <= 1'b0;        enc3086 <= 1'b1;        if (ned0485) begin              ux17d83 <= uk345f6;     end     else begin      ux17d83 <= pha0d17;     end     end     uk345f6:        begin           pua7ede <= 1'b0;        enc3086 <= 1'b1;        ux17d83 <= doa2fb0;     end     doa2fb0:        begin           pua7ede <= 1'b0;        enc3086 <= 1'b1;        ux17d83 <= pha0d17;     end\r
+       default:        begin   ux17d83 <= pha0d17;     end     endcase  end    end\r
+end\r
+always @(posedge kdd6cdf or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        mt18435 <= 1'b0;        ctc_drop_flag <= 1'b0;  end     else begin      mt18435 <= ym8d534;     ctc_drop_flag <= ym8d534 | qt6a9a0;     end\r
+end\r
+always @(posedge vidfa4f or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        ea67ca6 <= sjbec1d;     enfd27b <= 8'hBC;       lde93dc <= 1'b1;        ic49ee7 <= 1'b0;        hqa7cad <= 1'b0;        ou10d6f <= 1'b1;        end     else begin  if (zx614ff) begin  ea67ca6 <= sjbec1d;     enfd27b <= 8'hBC;       lde93dc <= 1'b1;        ic49ee7 <= 1'b0;        hqa7cad <= 1'b0;        ou10d6f <= 1'b1;  end  else begin               enfd27b <= dmda67a;     lde93dc <= oh85664;     ic49ee7 <= lf3699;      hqa7cad <= 1'b0;        ou10d6f <= 1'b0;        case (iea9d00)  sjbec1d:        begin           lde93dc <= 1'b1;        ic49ee7 <= 1'b0;        enfd27b <= 8'hBC;       ou10d6f <= 1'b1;        if (go59920) begin              ea67ca6 <= ldecf94;     end     else begin              hqa7cad <= 1'b1;        ea67ca6 <= thf60ec;     end     end     thf60ec:        begin           lde93dc <= 1'b0;        ic49ee7 <= 1'b0;        enfd27b <= 8'h50;       ou10d6f <= 1'b1;        hqa7cad <= 1'b1;        ea67ca6 <= gd1d9f2;     end     bnb0767:        begin           lde93dc <= 1'b1;        ic49ee7 <= 1'b0;        enfd27b <= 8'hBC;       ou10d6f <= 1'b1;        if (go59920) begin              ea67ca6 <= ldecf94;     end     else begin              hqa7cad <= 1'b1;        ea67ca6 <= hq83b3e;     end     end\r
+       hq83b3e:        begin           hqa7cad <= 1'b1;        ea67ca6 <= gd1d9f2;     end\r
+       gd1d9f2:        begin                   if (go59920 && oh85664 && (dmda67a == 8'hBC)) begin             lde93dc <= 1'b1;        ic49ee7 <= 1'b0;        enfd27b <= 8'hBC;       ou10d6f <= 1'b1;        ea67ca6 <= ldecf94;     end     else begin              hqa7cad <= 1'b1;        ea67ca6 <= gd1d9f2;     end     end     ldecf94:        begin           lde93dc <= 1'b0;        ic49ee7 <= 1'b0;        enfd27b <= 8'h50;       ou10d6f <= 1'b1;        ea67ca6 <= bnb0767;     end     default:        begin   ea67ca6 <= sjbec1d;     end     endcase  end    end\r
+end\r
+always @(posedge vidfa4f or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        ri86b78 <= 1'b1;        ctc_add_flag <= 1'b1;   end     else begin      ri86b78 <= yx54d05;     ctc_add_flag <= yx54d05 | swa682c;      end\r
+end\r
+always @(posedge kdd6cdf or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        ri2f44d <= 1'd0;        cz7a26a <= 1'd0;        wwd1355 <= 1'd0;        sw3e17a <= 1'd0;        end     else begin  if (vka7b0a) begin  ri2f44d <= 1'd0;        cz7a26a <= 1'd0;        wwd1355 <= 1'd0;        sw3e17a <= 1'd0;  end  else begin               sw3e17a <= nr64805;             if (qi2402e && mg8242b) begin   ri2f44d <= 1'd1;        end     else begin      ri2f44d <= 1'd0;        end             cz7a26a <= co5c59;              wwd1355 <= co5c59 | uk2e2c9;  end       end\r
+end\r
+always @(posedge vidfa4f or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        hq89aa9 <= 1'd0;        ne4d54b <= 1'd0;        gb6aa5a <= 1'd0;        ir85e89 <= 1'd1;        end     else begin  if (zx614ff) begin  hq89aa9 <= 1'd0;        ne4d54b <= 1'd0;        gb6aa5a <= 1'd0;        ir85e89 <= 1'd1;  end  else begin               ir85e89 <= mrd33d2;             if (qib8b && ba99e94) begin     hq89aa9 <= 1'd1;        end     else begin      hq89aa9 <= 1'd0;        end             ne4d54b <= jr8b246;             gb6aa5a <= jr8b246 | cm59237;  end      end\r
+end\r
+assign xj4f739 = bl71648 | ipc91b9;\r
+`ifdef SGMII_FIFO_FAMILY_SC\r
+               fifo1024x18_sc   ls35dd8 (  .Reset(pffc905),  .WrClock(kdd6cdf),  .WrEn(pua7ede),  .AmFullThresh(hq2f451),  .Data({8'd0, ng300ca, tu66019, yk4cc03}),\r
+  .RPReset(je20bd1),  .RdClock(vidfa4f),  .RdEn(hqa7cad),  .AmEmptyThresh(ks5e8a),  .Q({oua96af, tj275a7, nt9b647, end69f2}),\r
+  .Empty(uxb4f95),  .Full(zk47c2f),  .AlmostEmpty(gbd91f0),  .AlmostFull(pfc8f85)  );\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP2M\r
+               fifo1024x18_ecp2m   ls35dd8 (  .Reset(pffc905),  .WrClock(kdd6cdf),  .WrEn(pua7ede),  .AmFullThresh(hq2f451),  .Data({8'd0, ng300ca, tu66019, yk4cc03}),\r
+  .RPReset(je20bd1),  .RdClock(vidfa4f),  .RdEn(hqa7cad),  .AmEmptyThresh(ks5e8a),  .Q({oua96af, tj275a7, nt9b647, end69f2}),\r
+  .Empty(uxb4f95),  .Full(zk47c2f),  .AlmostEmpty(gbd91f0),  .AlmostFull(pfc8f85)  );\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP3\r
+               xy300fa   ls35dd8 (  .ne69bc9(vka7b0a),  .of4e369(kdd6cdf),  .ym8da6f(mg8242b),  .ps7929c(ay53ff9),  .ui49c6d({8'd0, fcb82ef, xl3705d, an26e0b}),\r
+  .vi4de4a(zx614ff),  .th71b4d(vidfa4f),  .su6d379(ba99e94),  .wj6f253(mga7ff),  .uvc94e2({oua96af, tj275a7, nt9b647, end69f2}),\r
+  .ld4a714(uxb4f95),  .su538a7(zk47c2f),  .ba9c539(gbd91f0),  .ale29cb(pfc8f85)  );\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP5\r
+               gd2938d   ls35dd8 (  .ne69bc9(vka7b0a),  .of4e369(kdd6cdf),  .ym8da6f(mg8242b),  .ps7929c(ay53ff9),  .ui49c6d({8'd0, fcb82ef, xl3705d, an26e0b}),\r
+  .vi4de4a(zx614ff),  .th71b4d(vidfa4f),  .su6d379(ba99e94),  .wj6f253(mga7ff),  .uvc94e2({oua96af, tj275a7, nt9b647, end69f2}),\r
+  .ld4a714(uxb4f95),  .su538a7(zk47c2f),  .ba9c539(gbd91f0),  .ale29cb(pfc8f85)  );\r
+`endif\r
+always @(ykf53a0) begin        case (ykf53a0)  pha0d17 :       hqade13 = "SEEK_IDLE_START";    jr68be :        hqade13 = "DISABLE_WRITES";     uk345f6 :       hqade13 = "DISABLE_W3"; doa2fb0 :       hqade13 = "DISABLE_W4"; default :       hqade13 = "***ERROR***";        endcase\r
+end\r
+always @(iea9d00) begin        case (iea9d00)  sjbec1d :       al6f09a = "SEEK_BEGIN_THRESH";  thf60ec  :      al6f09a = "DELAY_BEGIN";        bnb0767 :       al6f09a = "SEEK_START_THRESH";  hq83b3e  :      al6f09a = "DELAY";      gd1d9f2 :       al6f09a = "SEEK_STOP_THRESH";   ldecf94 :       al6f09a = "INSERT_IDLE";        default :       al6f09a = "***ERROR***";        endcase\r
+end\r
+always@* begin ri14169<=vx8bfb1[0];jpc26a0<=vx8bfb1[1];bn13507<=vx8bfb1[2];rt6b020<=vx8bfb1[3];ead41f5<={operational_rate>>1,vx8bfb1[4]};vxa0fa9<={oub66fd>>1,vx8bfb1[5]};ep7d4e<=vx8bfb1[6];gq3ea74<=vx8bfb1[7];ykf53a0<={ux17d83>>1,vx8bfb1[8]};iea9d00<={ea67ca6>>1,vx8bfb1[9]};ip4e800<={aa3e531>>1,vx8bfb1[10]};th74004<=vx8bfb1[11];xla0026<=vx8bfb1[12];wy137<={iea6266>>1,vx8bfb1[13]};uk9b8<=vx8bfb1[14];je4dc1<=vx8bfb1[15];an26e0b<={yk4cc03>>1,vx8bfb1[16]};xl3705d<=vx8bfb1[17];fcb82ef<=vx8bfb1[18];qgc177a<=vx8bfb1[19];zmbbd0<=vx8bfb1[20];xw5de82<=vx8bfb1[21];osef412<=vx8bfb1[22];en7a090<=vx8bfb1[23];ned0485<=vx8bfb1[24];mg8242b<=vx8bfb1[25];ba99e94<=vx8bfb1[26];dmda67a<={end69f2>>1,vx8bfb1[27]};oh85664<=vx8bfb1[28];lf3699<=vx8bfb1[29];go59920<=vx8bfb1[30];kdcc900<=vx8bfb1[31];nr64805<=vx8bfb1[32];qi2402e<=vx8bfb1[33];mrd33d2<=vx8bfb1[34];qib8b<=vx8bfb1[35];co5c59<=vx8bfb1[36];uk2e2c9<=vx8bfb1[37];bl71648<=vx8bfb1[38];jr8b246<=vx8bfb1[39];cm59237<=vx8bfb1[40];ipc91b9<=vx8bfb1[41];rg48dcc<={oua96af>>1,vx8bfb1[42]};xl9b4bd<={dz40186>>1,vx8bfb1[43]};psda5ee<={ymc36>>1,vx8bfb1[44]};mgb98c7<={tud5e6f>>1,vx8bfb1[45]};alcc639<={hdaf37a>>1,vx8bfb1[46]};fa631cc<=vx8bfb1[47];gd18e62<=vx8bfb1[48];ldc7314<=vx8bfb1[49];qv398a7<=vx8bfb1[50];hoee5cb<=vx8bfb1[51];ay629ec<=vx8bfb1[52];vk14f61<=vx8bfb1[53];vka7b0a<=vx8bfb1[54];jr3d853<=vx8bfb1[55];dzec29f<=vx8bfb1[56];zx614ff<=vx8bfb1[57];mga7ff<={ks5e8a>>1,vx8bfb1[58]};ay53ff9<={hq2f451>>1,vx8bfb1[59]};icfae0d<=vx8bfb1[60];rtd7068<=vx8bfb1[61];meff268<={kf8a2a9>>1,vx8bfb1[62]};blf9341<={mr5154d>>1,vx8bfb1[63]};mrc9a0e<=vx8bfb1[64];by4d075<=vx8bfb1[65];me683aa<=vx8bfb1[66];sh41d51<=vx8bfb1[67];twea8d<=vx8bfb1[68];cz7546a<=vx8bfb1[69];rvaa354<=vx8bfb1[70];cz51aa6<=vx8bfb1[71];ym8d534<=vx8bfb1[72];qt6a9a0<=vx8bfb1[73];yx54d05<=vx8bfb1[74];swa682c<=vx8bfb1[75];ie34161<={hqade13>>1,vx8bfb1[76]};nta0b08<={al6f09a>>1,vx8bfb1[77]};end\r
+always@* begin ead17f6[2047]<=an_link_ok;ead17f6[2046]<=lqe16b6;ead17f6[2044]<=gbe_mode;ead17f6[2040]<=operational_rate[0];ead17f6[2032]<=oub66fd[0];ead17f6[2018]<=oua96af[0];ead17f6[2017]<=ksb37e9;ead17f6[1989]<=dz40186[0];ead17f6[1987]<=hd9bf49;ead17f6[1931]<=ymc36[0];ead17f6[1927]<=ux17d83[0];ead17f6[1865]<=yk4cc03[0];ead17f6[1859]<=sw3e17a;ead17f6[1844]<=gd9f920;ead17f6[1815]<=tud5e6f[0];ead17f6[1806]<=ea67ca6[0];ead17f6[1682]<=tu66019;ead17f6[1674]<=ks5e8a[0];ead17f6[1671]<=uxb4f95;ead17f6[1640]<=pffc905;ead17f6[1582]<=hdaf37a[0];ead17f6[1565]<=aa3e531[0];ead17f6[1488]<=pfc8f85;ead17f6[1485]<=cb363da;ead17f6[1326]<=hqa7cad;ead17f6[1317]<=ng300ca;ead17f6[1300]<=hq2f451[0];ead17f6[1297]<=dz5536c;ead17f6[1295]<=ir85e89;ead17f6[1233]<=xwe482f;ead17f6[1210]<=nt9b647;ead17f6[1189]<=xw529fb;ead17f6[1172]<=db3294;ead17f6[1124]<=ri86b78;ead17f6[1116]<=zk79bd6;ead17f6[1105]<=qgf0bea;ead17f6[1094]<=nt38610;ead17f6[1092]<=xw4db38;ead17f6[1087]<=cz7a26a;ead17f6[1082]<=ipf2989;ead17f6[1023]<=mr_main_reset;ead17f6[1009]<=gb6aa5a;ead17f6[932]<=pu89980;ead17f6[929]<=zk47c2f;ead17f6[922]<=ecb3f24;ead17f6[837]<=je20bd1;ead17f6[744]<=gbd91f0;ead17f6[742]<=kd7acfc;ead17f6[663]<=pua7ede;ead17f6[648]<=gd8aa6d;ead17f6[605]<=end69f2[0];ead17f6[594]<=faca53f;ead17f6[586]<=an80652;ead17f6[562]<=ou10d6f;ead17f6[552]<=hq1e17d;ead17f6[547]<=ww670c2;ead17f6[546]<=ksa9b67;ead17f6[543]<=ri2f44d;ead17f6[504]<=ne4d54b;ead17f6[466]<=co31330;ead17f6[418]<=sw2417a;ead17f6[400]<=al6f09a[1];ead17f6[372]<=tj275a7;ead17f6[371]<=sh6f59f;ead17f6[331]<=rv94fdb;ead17f6[324]<=mr5154d[0];ead17f6[297]<=fp194a7;ead17f6[281]<=mt18435;ead17f6[273]<=xw6ce18;ead17f6[252]<=hq89aa9;ead17f6[233]<=iea6266[0];ead17f6[200]<=hqade13[1];ead17f6[185]<=blcdeb3;ead17f6[162]<=kf8a2a9[0];ead17f6[140]<=enc3086;ead17f6[136]<=kq6d9c3;ead17f6[126]<=wwd1355;ead17f6[116]<=nt94c4c;end         assign jebdc77 = ead17f6,vx8bfb1 = fn71dda; initial begin kfbe35f = $fopen(".fred"); $fdisplay( kfbe35f, "%3h\n%3h", (fnf63ba >> 4) & fpbaf71, (fnf63ba >> (tj8eebd+4)) & fpbaf71 ); $fclose(kfbe35f); $readmemh(".fred", ay776be); end always @ (jebdc77) begin nedaf8d = ay776be[1]; for (jcf1afd=0; jcf1afd<th5fd8e; jcf1afd=jcf1afd+1) begin fn71dda[jcf1afd] = jebdc77[nedaf8d]; thd7c6b = ^(nedaf8d & ay776be[0]); nedaf8d = {nedaf8d, thd7c6b}; end end\r
+endmodule\r
+`timescale 1 ns / 100 ps\r
+module tw86c28 (\r
+       rst_n,\r
+       mr_main_reset,\r
+       kdd6cdf,\r
+       oub66fd,\r
+       ksb37e9,\r
+       hd9bf49,\r
+       vidfa4f,\r
+       enfd27b,\r
+       lde93dc,\r
+       ic49ee7,\r
+       xj4f739,\r
+       ctc_drop_flag,\r
+       ctc_add_flag\r
+);\r
+input  rst_n;\r
+input  mr_main_reset;\r
+input  kdd6cdf;\r
+input [7:0]    oub66fd;\r
+input  ksb37e9;\r
+input  hd9bf49;\r
+input  vidfa4f;\r
+output [7:0]   enfd27b;\r
+output lde93dc;\r
+output ic49ee7;\r
+output xj4f739;\r
+output ctc_drop_flag;\r
+output ctc_add_flag;\r
+parameter STATIC_HI_THRESH = 32;\r
+parameter STATIC_LO_THRESH = 16;\r
+localparam     pha0d17 = 2'd0, jr68be  = 2'd1, uk345f6 = 2'd2, doa2fb0 = 2'd3;\r
+reg[1:0] ux17d83;\r
+localparam     sjbec1d = 3'd0, thf60ec = 3'd1, bnb0767 = 3'd2, hq83b3e = 3'd3, gd1d9f2 = 3'd4, ldecf94 = 3'd5;\r
+reg [2:0] ea67ca6;\r
+reg [7:0] aa3e531;\r
+reg ipf2989;\r
+reg nt94c4c ;\r
+reg [7:0] iea6266;\r
+reg co31330;\r
+reg pu89980 ;\r
+reg [7:0] yk4cc03;\r
+reg tu66019;\r
+reg ng300ca ;\r
+reg an80652;\r
+reg db3294;\r
+reg fp194a7;\r
+reg faca53f;\r
+reg xw529fb;\r
+reg rv94fdb;\r
+reg pua7ede;\r
+reg hqa7cad;\r
+reg [7:0] enfd27b;\r
+reg lde93dc;\r
+reg ic49ee7;\r
+wire [7:0] end69f2;\r
+wire nt9b647;\r
+wire tj275a7;\r
+wire gbd91f0;\r
+wire pfc8f85;\r
+wire zk47c2f;\r
+reg sw3e17a;\r
+wire uxb4f95;\r
+reg ir85e89;\r
+reg ri2f44d;\r
+reg cz7a26a;\r
+reg wwd1355;\r
+reg hq89aa9;\r
+reg ne4d54b;\r
+reg gb6aa5a;\r
+wire xj4f739;\r
+wire [7:0] oua96af;\r
+reg kq6d9c3 ;\r
+reg xw6ce18 ;\r
+reg ww670c2 ;\r
+reg nt38610 ;\r
+reg enc3086;\r
+reg mt18435;\r
+reg ctc_drop_flag;\r
+reg ou10d6f;\r
+reg ri86b78;\r
+reg ctc_add_flag;\r
+`ifdef SGMII_FIFO_FAMILY_SC\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP2M\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP3\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP5\r
+`endif\r
+reg  [(22*8):1] hqade13;\r
+reg  [(22*8):1] al6f09a;\r
+reg ri14169;\r
+reg [7 : 0] vxa0fa9;\r
+reg ep7d4e;\r
+reg gq3ea74;\r
+reg [1 : 0] ykf53a0;\r
+reg [2 : 0] iea9d00;\r
+reg [7 : 0] ip4e800;\r
+reg th74004;\r
+reg xla0026;\r
+reg [7 : 0] wy137;\r
+reg uk9b8;\r
+reg je4dc1;\r
+reg [7 : 0] an26e0b;\r
+reg xl3705d;\r
+reg fcb82ef;\r
+reg qgc177a;\r
+reg zmbbd0;\r
+reg xw5de82;\r
+reg osef412;\r
+reg en7a090;\r
+reg ned0485;\r
+reg mg8242b;\r
+reg ba99e94;\r
+reg [7 : 0] dmda67a;\r
+reg oh85664;\r
+reg lf3699;\r
+reg go59920;\r
+reg kdcc900;\r
+reg nr64805;\r
+reg qi2402e;\r
+reg mrd33d2;\r
+reg qib8b;\r
+reg co5c59;\r
+reg uk2e2c9;\r
+reg bl71648;\r
+reg jr8b246;\r
+reg cm59237;\r
+reg ipc91b9;\r
+reg [7 : 0] rg48dcc;\r
+reg twea8d;\r
+reg cz7546a;\r
+reg rvaa354;\r
+reg cz51aa6;\r
+reg ym8d534;\r
+reg qt6a9a0;\r
+reg yx54d05;\r
+reg swa682c;\r
+reg [(22 * 8) : 1] ie34161;\r
+reg [(22 * 8) : 1] nta0b08;\r
+reg [2047:0] ead17f6;\r
+wire [48:0] vx8bfb1;\r
+`ifdef SGMII_FIFO_FAMILY_SC\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP2M\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP3\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP5\r
+`endif\r
+localparam th5fd8e = 49,nefec77 = 32'hfdffe44b;\r
+localparam [31:0] fnf63ba = nefec77;\r
+localparam tj8eebd = nefec77 & 4'hf;\r
+localparam [11:0] fpbaf71 = 'h7ff;\r
+wire [(1 << tj8eebd) -1:0] jebdc77;\r
+reg [th5fd8e-1:0] fn71dda;\r
+reg [tj8eebd-1:0] ay776be [0:1];\r
+reg [tj8eebd-1:0] nedaf8d;\r
+reg thd7c6b;\r
+integer kfbe35f;\r
+integer jcf1afd;\r
+`ifdef SGMII_FIFO_FAMILY_SC\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP2M\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP3\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP5\r
+`endif\r
+always @(posedge kdd6cdf or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        kq6d9c3 <= 1'b1;        xw6ce18 <= 1'b1;        end     else begin      kq6d9c3 <= ri14169;     xw6ce18 <= twea8d;      end\r
+end\r
+always @(posedge vidfa4f or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        ww670c2 <= 1'b1;        nt38610 <= 1'b1;        end     else begin      ww670c2 <= ri14169;     nt38610 <= rvaa354;     end\r
+end\r
+always @(posedge kdd6cdf or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        aa3e531 <= 8'd0;        ipf2989 <= 1'b0;        nt94c4c <= 1'b0;        iea6266 <= 8'd0;        co31330 <= 1'b0;        pu89980 <= 1'b0;        yk4cc03 <= 8'd0;        tu66019 <= 1'b0;        ng300ca <= 1'b0;        end     else begin      aa3e531 <= vxa0fa9;     ipf2989 <= ep7d4e;      nt94c4c <= gq3ea74;     iea6266 <= ip4e800;     co31330 <= th74004;     pu89980 <= xla0026;     yk4cc03 <= wy137;       tu66019 <= uk9b8;       ng300ca <= je4dc1;      end\r
+end\r
+always @(posedge kdd6cdf or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        an80652 <= 1'b0;        db3294 <= 1'b0; fp194a7 <= 1'b0;        faca53f <= 1'b0;        xw529fb <= 1'b0;        rv94fdb <= 1'b0;        end     else begin              if ((th74004 == 1'b1) && (ip4e800 == 8'hBC)) begin      an80652 <= 1'b1;        end     else begin      an80652 <= 1'b0;        end\r
+               if ((ep7d4e == 1'b0) && (vxa0fa9 == 8'hC5)) begin       db3294 <= 1'b1; end     else begin      db3294 <= 1'b0; end             if ((ep7d4e == 1'b0) && (vxa0fa9 == 8'h50)) begin       fp194a7 <= 1'b1;        end     else begin      fp194a7 <= 1'b0;        end             if ((ep7d4e == 1'b0) && (vxa0fa9 == 8'h42)) begin       faca53f <= 1'b1;        end     else begin      faca53f <= 1'b0;        end             if ((ep7d4e == 1'b0) && (vxa0fa9 == 8'hB5)) begin       xw529fb <= 1'b1;        end     else begin      xw529fb <= 1'b0;        end             if (qgc177a && (osef412 || en7a090)) begin      rv94fdb <= 1'b1;        end     else begin      rv94fdb <= 1'b0;        end     end\r
+end\r
+always @(posedge kdd6cdf or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        ux17d83 <= pha0d17;     pua7ede <= 1'b0;        enc3086 <= 1'b0;        end     else begin  if (cz7546a) begin  ux17d83 <= pha0d17;     pua7ede <= 1'b0;  end  else begin               enc3086 <= 1'b0;        case (ykf53a0)  pha0d17:        begin   if (kdcc900) begin                      if (qgc177a && (xw5de82 || osef412 || en7a090)) begin   pua7ede <= 1'b0;        ux17d83 <= jr68be;      enc3086 <= 1'b1;        end     end     else begin              pua7ede <= 1'b1;        ux17d83 <= pha0d17;     end     end     jr68be: begin           pua7ede <= 1'b0;        enc3086 <= 1'b1;        if (ned0485) begin              ux17d83 <= uk345f6;     end     else begin      ux17d83 <= pha0d17;     end     end     uk345f6:        begin           pua7ede <= 1'b0;        enc3086 <= 1'b1;        ux17d83 <= doa2fb0;     end     doa2fb0:        begin           pua7ede <= 1'b0;        enc3086 <= 1'b1;        ux17d83 <= pha0d17;     end\r
+       default:        begin   ux17d83 <= pha0d17;     end     endcase  end    end\r
+end\r
+always @(posedge kdd6cdf or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        mt18435 <= 1'b0;        ctc_drop_flag <= 1'b0;  end     else begin      mt18435 <= ym8d534;     ctc_drop_flag <= ym8d534 | qt6a9a0;     end\r
+end\r
+always @(posedge vidfa4f or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        ea67ca6 <= sjbec1d;     enfd27b <= 8'hBC;       lde93dc <= 1'b1;        ic49ee7 <= 1'b0;        hqa7cad <= 1'b0;        ou10d6f <= 1'b1;        end     else begin  if (cz51aa6) begin  ea67ca6 <= sjbec1d;     hqa7cad <= 1'b0;  end  else begin               enfd27b <= dmda67a;     lde93dc <= oh85664;     ic49ee7 <= lf3699;      hqa7cad <= 1'b0;        ou10d6f <= 1'b0;        case (iea9d00)  sjbec1d:        begin           lde93dc <= 1'b1;        ic49ee7 <= 1'b0;        enfd27b <= 8'hBC;       ou10d6f <= 1'b1;        if (go59920) begin              ea67ca6 <= ldecf94;     end     else begin              hqa7cad <= 1'b1;        ea67ca6 <= thf60ec;     end     end     thf60ec:        begin           lde93dc <= 1'b0;        ic49ee7 <= 1'b0;        enfd27b <= 8'h50;       ou10d6f <= 1'b1;        hqa7cad <= 1'b1;        ea67ca6 <= gd1d9f2;     end     bnb0767:        begin           lde93dc <= 1'b1;        ic49ee7 <= 1'b0;        enfd27b <= 8'hBC;       ou10d6f <= 1'b1;        if (go59920) begin              ea67ca6 <= ldecf94;     end     else begin              hqa7cad <= 1'b1;        ea67ca6 <= hq83b3e;     end     end\r
+       hq83b3e:        begin           hqa7cad <= 1'b1;        ea67ca6 <= gd1d9f2;     end\r
+       gd1d9f2:        begin                   if (go59920 && oh85664 && (dmda67a == 8'hBC)) begin             lde93dc <= 1'b1;        ic49ee7 <= 1'b0;        enfd27b <= 8'hBC;       ou10d6f <= 1'b1;        ea67ca6 <= ldecf94;     end     else begin              hqa7cad <= 1'b1;        ea67ca6 <= gd1d9f2;     end     end     ldecf94:        begin           lde93dc <= 1'b0;        ic49ee7 <= 1'b0;        enfd27b <= 8'h50;       ou10d6f <= 1'b1;        ea67ca6 <= bnb0767;     end     default:        begin   ea67ca6 <= sjbec1d;     end     endcase  end    end\r
+end\r
+always @(posedge vidfa4f or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        ri86b78 <= 1'b1;        ctc_add_flag <= 1'b1;   end     else begin      ri86b78 <= yx54d05;     ctc_add_flag <= yx54d05 | swa682c;      end\r
+end\r
+always @(posedge kdd6cdf or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        ri2f44d <= 1'd0;        cz7a26a <= 1'd0;        wwd1355 <= 1'd0;        sw3e17a <= 1'd0;        end     else begin              sw3e17a <= nr64805;             if (qi2402e && mg8242b) begin   ri2f44d <= 1'd1;        end     else begin      ri2f44d <= 1'd0;        end             cz7a26a <= co5c59;              wwd1355 <= co5c59 | uk2e2c9;    end\r
+end\r
+always @(posedge vidfa4f or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        hq89aa9 <= 1'd0;        ne4d54b <= 1'd0;        gb6aa5a <= 1'd0;        ir85e89 <= 1'd1;        end     else begin              ir85e89 <= mrd33d2;             if (qib8b && ba99e94) begin     hq89aa9 <= 1'd1;        end     else begin      hq89aa9 <= 1'd0;        end             ne4d54b <= jr8b246;             gb6aa5a <= jr8b246 | cm59237;   end\r
+end\r
+assign xj4f739 = bl71648 | ipc91b9;\r
+`ifdef SGMII_FIFO_FAMILY_SC\r
+               pmi_fifo_dc #(  .pmi_data_width_w(18),  .pmi_data_width_r(18),  .pmi_data_depth_w(1024),        .pmi_data_depth_r(1024),        .pmi_full_flag(1024),   .pmi_empty_flag(0),     .pmi_almost_full_flag(STATIC_HI_THRESH),        .pmi_almost_empty_flag(STATIC_LO_THRESH),       .pmi_regmode("no_reg"), .pmi_resetmode("async"),        .pmi_family("SC"),      .module_type("pmi_fifo_dc"),    .pmi_implementation("EBR")) ls35dd8 (   .Reset(xw6ce18),        .RPReset(nt38610),      .WrClock(kdd6cdf),      .WrEn(pua7ede), .Data({8'd0, ng300ca, tu66019, yk4cc03}),\r
+       .RdClock(vidfa4f),      .RdEn(hqa7cad), .Q({oua96af, tj275a7, nt9b647, end69f2}),\r
+       .Empty(uxb4f95),        .Full(zk47c2f), .AlmostEmpty(gbd91f0),  .AlmostFull(pfc8f85)    );\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP2M\r
+               pmi_fifo_dc #(  .pmi_data_width_w(18),  .pmi_data_width_r(18),  .pmi_data_depth_w(1024),        .pmi_data_depth_r(1024),        .pmi_full_flag(1024),   .pmi_empty_flag(0),     .pmi_almost_full_flag(STATIC_HI_THRESH),        .pmi_almost_empty_flag(STATIC_LO_THRESH),       .pmi_regmode("no_reg"), .pmi_resetmode("async"),        .pmi_family("ECP2M"),   .module_type("pmi_fifo_dc"),    .pmi_implementation("EBR")) ls35dd8 (   .Reset(xw6ce18),        .RPReset(nt38610),      .WrClock(kdd6cdf),      .WrEn(pua7ede), .Data({8'd0, ng300ca, tu66019, yk4cc03}),\r
+       .RdClock(vidfa4f),      .RdEn(hqa7cad), .Q({oua96af, tj275a7, nt9b647, end69f2}),\r
+       .Empty(uxb4f95),        .Full(zk47c2f), .AlmostEmpty(gbd91f0),  .AlmostFull(pfc8f85)    );\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP3\r
+               pmi_fifo_dc #(  .pmi_data_width_w(18),  .pmi_data_width_r(18),  .pmi_data_depth_w(1024),        .pmi_data_depth_r(1024),        .pmi_full_flag(1024),   .pmi_empty_flag(0),     .pmi_almost_full_flag(STATIC_HI_THRESH),        .pmi_almost_empty_flag(STATIC_LO_THRESH),       .pmi_regmode("no_reg"), .pmi_resetmode("async"),        .pmi_family("ECP3"),    .module_type("pmi_fifo_dc"),    .pmi_implementation("EBR")) ls35dd8 (   .Reset(xw6ce18),        .RPReset(nt38610),      .WrClock(kdd6cdf),      .WrEn(pua7ede), .Data({8'd0, ng300ca, tu66019, yk4cc03}),\r
+       .RdClock(vidfa4f),      .RdEn(hqa7cad), .Q({oua96af, tj275a7, nt9b647, end69f2}),\r
+       .Empty(uxb4f95),        .Full(zk47c2f), .AlmostEmpty(gbd91f0),  .AlmostFull(pfc8f85)    );\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP5\r
+               pmi_fifo_dc #(  .pmi_data_width_w(18),  .pmi_data_width_r(18),  .pmi_data_depth_w(1024),        .pmi_data_depth_r(1024),        .pmi_full_flag(1024),   .pmi_empty_flag(0),     .pmi_almost_full_flag(STATIC_HI_THRESH),        .pmi_almost_empty_flag(STATIC_LO_THRESH),       .pmi_regmode("no_reg"), .pmi_resetmode("async"),        .pmi_family("ECP5UM"),  .module_type("pmi_fifo_dc"),    .pmi_implementation("EBR")) ls35dd8 (   .Reset(xw6ce18),        .RPReset(nt38610),      .WrClock(kdd6cdf),      .WrEn(pua7ede), .Data({8'd0, ng300ca, tu66019, yk4cc03}),\r
+       .RdClock(vidfa4f),      .RdEn(hqa7cad), .Q({oua96af, tj275a7, nt9b647, end69f2}),\r
+       .Empty(uxb4f95),        .Full(zk47c2f), .AlmostEmpty(gbd91f0),  .AlmostFull(pfc8f85)    );\r
+`endif\r
+always @(ykf53a0) begin        case (ykf53a0)  pha0d17 :       hqade13 = "SEEK_IDLE_START";    jr68be :        hqade13 = "DISABLE_WRITES";     uk345f6 :       hqade13 = "DISABLE_W3"; doa2fb0 :       hqade13 = "DISABLE_W4"; default :       hqade13 = "***ERROR***";        endcase\r
+end\r
+always @(iea9d00) begin        case (iea9d00)  sjbec1d :       al6f09a = "SEEK_BEGIN_THRESH";  thf60ec  :      al6f09a = "DELAY_BEGIN";        bnb0767 :       al6f09a = "SEEK_START_THRESH";  hq83b3e  :      al6f09a = "DELAY";      gd1d9f2 :       al6f09a = "SEEK_STOP_THRESH";   ldecf94 :       al6f09a = "INSERT_IDLE";        default :       al6f09a = "***ERROR***";        endcase\r
+end\r
+always@* begin ri14169<=vx8bfb1[0];vxa0fa9<={oub66fd>>1,vx8bfb1[1]};ep7d4e<=vx8bfb1[2];gq3ea74<=vx8bfb1[3];ykf53a0<={ux17d83>>1,vx8bfb1[4]};iea9d00<={ea67ca6>>1,vx8bfb1[5]};ip4e800<={aa3e531>>1,vx8bfb1[6]};th74004<=vx8bfb1[7];xla0026<=vx8bfb1[8];wy137<={iea6266>>1,vx8bfb1[9]};uk9b8<=vx8bfb1[10];je4dc1<=vx8bfb1[11];an26e0b<={yk4cc03>>1,vx8bfb1[12]};xl3705d<=vx8bfb1[13];fcb82ef<=vx8bfb1[14];qgc177a<=vx8bfb1[15];zmbbd0<=vx8bfb1[16];xw5de82<=vx8bfb1[17];osef412<=vx8bfb1[18];en7a090<=vx8bfb1[19];ned0485<=vx8bfb1[20];mg8242b<=vx8bfb1[21];ba99e94<=vx8bfb1[22];dmda67a<={end69f2>>1,vx8bfb1[23]};oh85664<=vx8bfb1[24];lf3699<=vx8bfb1[25];go59920<=vx8bfb1[26];kdcc900<=vx8bfb1[27];nr64805<=vx8bfb1[28];qi2402e<=vx8bfb1[29];mrd33d2<=vx8bfb1[30];qib8b<=vx8bfb1[31];co5c59<=vx8bfb1[32];uk2e2c9<=vx8bfb1[33];bl71648<=vx8bfb1[34];jr8b246<=vx8bfb1[35];cm59237<=vx8bfb1[36];ipc91b9<=vx8bfb1[37];rg48dcc<={oua96af>>1,vx8bfb1[38]};twea8d<=vx8bfb1[39];cz7546a<=vx8bfb1[40];rvaa354<=vx8bfb1[41];cz51aa6<=vx8bfb1[42];ym8d534<=vx8bfb1[43];qt6a9a0<=vx8bfb1[44];yx54d05<=vx8bfb1[45];swa682c<=vx8bfb1[46];ie34161<={hqade13>>1,vx8bfb1[47]};nta0b08<={al6f09a>>1,vx8bfb1[48]};end\r
+always@* begin ead17f6[2047]<=oub66fd[0];ead17f6[2046]<=ksb37e9;ead17f6[2044]<=hd9bf49;ead17f6[2040]<=ux17d83[0];ead17f6[2033]<=ea67ca6[0];ead17f6[2019]<=aa3e531[0];ead17f6[1991]<=ipf2989;ead17f6[1934]<=nt94c4c;ead17f6[1929]<=hqade13[1];ead17f6[1898]<=an80652;ead17f6[1821]<=iea6266[0];ead17f6[1810]<=al6f09a[1];ead17f6[1749]<=db3294;ead17f6[1707]<=xw529fb;ead17f6[1666]<=zk47c2f;ead17f6[1630]<=ww670c2;ead17f6[1595]<=co31330;ead17f6[1506]<=ou10d6f;ead17f6[1450]<=fp194a7;ead17f6[1440]<=gbd91f0;ead17f6[1384]<=nt9b647;ead17f6[1370]<=hqa7cad;ead17f6[1366]<=rv94fdb;ead17f6[1284]<=sw3e17a;ead17f6[1212]<=nt38610;ead17f6[1142]<=pu89980;ead17f6[1125]<=gb6aa5a;ead17f6[1041]<=ir85e89;ead17f6[1023]<=mr_main_reset;ead17f6[964]<=ri86b78;ead17f6[949]<=ng300ca;ead17f6[853]<=faca53f;ead17f6[833]<=pfc8f85;ead17f6[815]<=xw6ce18;ead17f6[753]<=mt18435;ead17f6[720]<=tj275a7;ead17f6[692]<=end69f2[0];ead17f6[685]<=pua7ede;ead17f6[562]<=ne4d54b;ead17f6[520]<=uxb4f95;ead17f6[474]<=tu66019;ead17f6[407]<=kq6d9c3;ead17f6[376]<=enc3086;ead17f6[281]<=hq89aa9;ead17f6[237]<=yk4cc03[0];ead17f6[203]<=oua96af[0];ead17f6[140]<=wwd1355;ead17f6[70]<=cz7a26a;ead17f6[35]<=ri2f44d;end         assign jebdc77 = ead17f6,vx8bfb1 = fn71dda; initial begin kfbe35f = $fopen(".fred"); $fdisplay( kfbe35f, "%3h\n%3h", (fnf63ba >> 4) & fpbaf71, (fnf63ba >> (tj8eebd+4)) & fpbaf71 ); $fclose(kfbe35f); $readmemh(".fred", ay776be); end always @ (jebdc77) begin nedaf8d = ay776be[1]; for (jcf1afd=0; jcf1afd<th5fd8e; jcf1afd=jcf1afd+1) begin fn71dda[jcf1afd] = jebdc77[nedaf8d]; thd7c6b = ^(nedaf8d & ay776be[0]); nedaf8d = {nedaf8d, thd7c6b}; end end\r
+endmodule\r
+`timescale 1 ns / 100 ps\r
+module zxdd74c (\r
+       rst_n,\r
+       mr_main_reset,\r
+       kdd6cdf,\r
+       oub66fd,\r
+       ksb37e9,\r
+       hd9bf49,\r
+       vidfa4f,\r
+       enfd27b,\r
+       lde93dc,\r
+       ic49ee7,\r
+       xj4f739\r
+);\r
+input  rst_n;\r
+input  mr_main_reset;\r
+input  kdd6cdf;\r
+input [7:0]    oub66fd;\r
+input  ksb37e9;\r
+input  hd9bf49;\r
+input  vidfa4f;\r
+output [7:0]   enfd27b;\r
+output lde93dc;\r
+output ic49ee7;\r
+output xj4f739;\r
+reg [7:0] aa3e531;\r
+reg ipf2989;\r
+reg nt94c4c;\r
+reg pua7ede;\r
+reg hqa7cad;\r
+reg [7:0] enfd27b;\r
+reg lde93dc;\r
+reg ic49ee7;\r
+wire [7:0] end69f2;\r
+wire nt9b647;\r
+wire tj275a7;\r
+wire gbd91f0;\r
+wire pfc8f85;\r
+wire zk47c2f;\r
+wire uxb4f95;\r
+reg ri2f44d;\r
+reg cz7a26a;\r
+reg wwd1355;\r
+reg hq89aa9;\r
+reg ne4d54b;\r
+reg gb6aa5a;\r
+wire xj4f739;\r
+reg kq6d9c3 ;\r
+reg xw6ce18 ;\r
+reg ww670c2 ;\r
+reg nt38610 ;\r
+`ifdef SGMII_FIFO_FAMILY_SC\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP2M\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP3\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP5\r
+`endif\r
+reg ri14169;\r
+reg [7 : 0] vxa0fa9;\r
+reg ep7d4e;\r
+reg gq3ea74;\r
+reg [7 : 0] ip4e800;\r
+reg th74004;\r
+reg xla0026;\r
+reg mg8242b;\r
+reg ba99e94;\r
+reg [7 : 0] dmda67a;\r
+reg oh85664;\r
+reg lf3699;\r
+reg go59920;\r
+reg kdcc900;\r
+reg nr64805;\r
+reg mrd33d2;\r
+reg co5c59;\r
+reg uk2e2c9;\r
+reg bl71648;\r
+reg jr8b246;\r
+reg cm59237;\r
+reg ipc91b9;\r
+reg twea8d;\r
+reg cz7546a;\r
+reg rvaa354;\r
+reg cz51aa6;\r
+reg [2047:0] ead17f6;\r
+wire [25:0] vx8bfb1;\r
+`ifdef SGMII_FIFO_FAMILY_SC\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP2M\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP3\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP5\r
+`endif\r
+localparam th5fd8e = 26,nefec77 = 32'hfdffd14b;\r
+localparam [31:0] fnf63ba = nefec77;\r
+localparam tj8eebd = nefec77 & 4'hf;\r
+localparam [11:0] fpbaf71 = 'h7ff;\r
+wire [(1 << tj8eebd) -1:0] jebdc77;\r
+reg [th5fd8e-1:0] fn71dda;\r
+reg [tj8eebd-1:0] ay776be [0:1];\r
+reg [tj8eebd-1:0] nedaf8d;\r
+reg thd7c6b;\r
+integer kfbe35f;\r
+integer jcf1afd;\r
+`ifdef SGMII_FIFO_FAMILY_SC\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP2M\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP3\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP5\r
+`endif\r
+always @(posedge kdd6cdf or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        kq6d9c3 <= 1'b1;        xw6ce18 <= 1'b1;        end     else begin      kq6d9c3 <= ri14169;     xw6ce18 <= twea8d;      end\r
+end\r
+always @(posedge vidfa4f or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        ww670c2 <= 1'b1;        nt38610 <= 1'b1;        end     else begin      ww670c2 <= ri14169;     nt38610 <= rvaa354;     end\r
+end\r
+always @(posedge kdd6cdf or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        aa3e531 <= 8'd0;        ipf2989 <= 1'b0;        nt94c4c <= 1'b0;        end     else begin      aa3e531 <= vxa0fa9;     ipf2989 <= ep7d4e;      nt94c4c <= gq3ea74;     end\r
+end\r
+always @(posedge vidfa4f or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        enfd27b <= 8'd0;        lde93dc <= 1'b0;        ic49ee7 <= 1'b0;        end     else begin      enfd27b <= dmda67a;     lde93dc <= oh85664;     ic49ee7 <= lf3699;      end\r
+end\r
+always @(posedge kdd6cdf or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        pua7ede <= 1'b0;        end     else begin  if (cz7546a) begin  pua7ede <= 1'b0;  end  else begin       if (nr64805) begin      pua7ede <= 1'b0;        end     else begin      pua7ede <= 1'b1;        end  end        end\r
+end\r
+always @(posedge vidfa4f or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        hqa7cad <= 1'b0;        end     else begin  if (cz51aa6) begin  hqa7cad <= 1'b0;  end  else begin       if (mrd33d2) begin      hqa7cad <= 1'b0;        end     else if (go59920) begin hqa7cad <= 1'b0;        end     else begin      hqa7cad <= 1'b1;        end  end        end\r
+end\r
+always @(posedge kdd6cdf or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        ri2f44d <= 1'd0;        cz7a26a <= 1'd0;        wwd1355 <= 1'd0;        end     else begin              if (nr64805 && mg8242b) begin   ri2f44d <= 1'd1;        end     else begin      ri2f44d <= 1'd0;        end             cz7a26a <= co5c59;              wwd1355 <= co5c59 | uk2e2c9;    end\r
+end\r
+always @(posedge vidfa4f or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        hq89aa9 <= 1'd0;        ne4d54b <= 1'd0;        gb6aa5a <= 1'd0;        end     else begin              if (mrd33d2 && ba99e94) begin   hq89aa9 <= 1'd1;        end     else begin      hq89aa9 <= 1'd0;        end             ne4d54b <= jr8b246;             gb6aa5a <= jr8b246 | cm59237;   end\r
+end\r
+assign xj4f739 = bl71648 | ipc91b9;\r
+`ifdef SGMII_FIFO_FAMILY_SC\r
+               pmi_fifo_dc #(  .pmi_data_width_w(10),  .pmi_data_width_r(10),  .pmi_data_depth_w(16),  .pmi_data_depth_r(16),  .pmi_full_flag(16),     .pmi_empty_flag(0),     .pmi_almost_full_flag(13),      .pmi_almost_empty_flag(7),      .pmi_regmode("no_reg"), .pmi_resetmode("async"),        .pmi_family("SC"),      .module_type("pmi_fifo_dc"),    .pmi_implementation("LUT")) ls35dd8 (   .Reset(xw6ce18),        .RPReset(nt38610),      .WrClock(kdd6cdf),      .WrEn(pua7ede), .Data({nt94c4c, ipf2989, aa3e531}),\r
+       .RdClock(vidfa4f),      .RdEn(hqa7cad), .Q({tj275a7, nt9b647, end69f2}),\r
+       .Empty(uxb4f95),        .Full(zk47c2f), .AlmostEmpty(gbd91f0),  .AlmostFull(pfc8f85)    );\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP2M\r
+               pmi_fifo_dc #(  .pmi_data_width_w(10),  .pmi_data_width_r(10),  .pmi_data_depth_w(16),  .pmi_data_depth_r(16),  .pmi_full_flag(16),     .pmi_empty_flag(0),     .pmi_almost_full_flag(13),      .pmi_almost_empty_flag(7),      .pmi_regmode("no_reg"), .pmi_resetmode("async"),        .pmi_family("ECP2M"),   .module_type("pmi_fifo_dc"),    .pmi_implementation("LUT")) ls35dd8 (   .Reset(xw6ce18),        .RPReset(nt38610),      .WrClock(kdd6cdf),      .WrEn(pua7ede), .Data({nt94c4c, ipf2989, aa3e531}),\r
+       .RdClock(vidfa4f),      .RdEn(hqa7cad), .Q({tj275a7, nt9b647, end69f2}),\r
+       .Empty(uxb4f95),        .Full(zk47c2f), .AlmostEmpty(gbd91f0),  .AlmostFull(pfc8f85)    );\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP3\r
+               pmi_fifo_dc #(  .pmi_data_width_w(10),  .pmi_data_width_r(10),  .pmi_data_depth_w(16),  .pmi_data_depth_r(16),  .pmi_full_flag(16),     .pmi_empty_flag(0),     .pmi_almost_full_flag(13),      .pmi_almost_empty_flag(7),      .pmi_regmode("no_reg"), .pmi_resetmode("async"),        .pmi_family("ECP3"),    .module_type("pmi_fifo_dc"),    .pmi_implementation("LUT")) ls35dd8 (   .Reset(xw6ce18),        .RPReset(nt38610),      .WrClock(kdd6cdf),      .WrEn(pua7ede), .Data({nt94c4c, ipf2989, aa3e531}),\r
+       .RdClock(vidfa4f),      .RdEn(hqa7cad), .Q({tj275a7, nt9b647, end69f2}),\r
+       .Empty(uxb4f95),        .Full(zk47c2f), .AlmostEmpty(gbd91f0),  .AlmostFull(pfc8f85)    );\r
+`endif\r
+`ifdef SGMII_FIFO_FAMILY_ECP5\r
+               pmi_fifo_dc #(  .pmi_data_width_w(10),  .pmi_data_width_r(10),  .pmi_data_depth_w(16),  .pmi_data_depth_r(16),  .pmi_full_flag(16),     .pmi_empty_flag(0),     .pmi_almost_full_flag(13),      .pmi_almost_empty_flag(7),      .pmi_regmode("no_reg"), .pmi_resetmode("async"),        .pmi_family("ECP5UM"),  .module_type("pmi_fifo_dc"),    .pmi_implementation("LUT")) ls35dd8 (   .Reset(xw6ce18),        .RPReset(nt38610),      .WrClock(kdd6cdf),      .WrEn(pua7ede), .Data({nt94c4c, ipf2989, aa3e531}),\r
+       .RdClock(vidfa4f),      .RdEn(hqa7cad), .Q({tj275a7, nt9b647, end69f2}),\r
+       .Empty(uxb4f95),        .Full(zk47c2f), .AlmostEmpty(gbd91f0),  .AlmostFull(pfc8f85)    );\r
+`endif\r
+always@* begin ri14169<=vx8bfb1[0];vxa0fa9<={oub66fd>>1,vx8bfb1[1]};ep7d4e<=vx8bfb1[2];gq3ea74<=vx8bfb1[3];ip4e800<={aa3e531>>1,vx8bfb1[4]};th74004<=vx8bfb1[5];xla0026<=vx8bfb1[6];mg8242b<=vx8bfb1[7];ba99e94<=vx8bfb1[8];dmda67a<={end69f2>>1,vx8bfb1[9]};oh85664<=vx8bfb1[10];lf3699<=vx8bfb1[11];go59920<=vx8bfb1[12];kdcc900<=vx8bfb1[13];nr64805<=vx8bfb1[14];mrd33d2<=vx8bfb1[15];co5c59<=vx8bfb1[16];uk2e2c9<=vx8bfb1[17];bl71648<=vx8bfb1[18];jr8b246<=vx8bfb1[19];cm59237<=vx8bfb1[20];ipc91b9<=vx8bfb1[21];twea8d<=vx8bfb1[22];cz7546a<=vx8bfb1[23];rvaa354<=vx8bfb1[24];cz51aa6<=vx8bfb1[25];end\r
+always@* begin ead17f6[2047]<=oub66fd[0];ead17f6[2046]<=ksb37e9;ead17f6[2044]<=hd9bf49;ead17f6[2040]<=aa3e531[0];ead17f6[2033]<=ipf2989;ead17f6[2019]<=nt94c4c;ead17f6[1990]<=pua7ede;ead17f6[1939]<=wwd1355;ead17f6[1933]<=hqa7cad;ead17f6[1831]<=hq89aa9;ead17f6[1819]<=end69f2[0];ead17f6[1778]<=uxb4f95;ead17f6[1615]<=ne4d54b;ead17f6[1591]<=nt9b647;ead17f6[1508]<=ri2f44d;ead17f6[1271]<=ww670c2;ead17f6[1182]<=gb6aa5a;ead17f6[1135]<=tj275a7;ead17f6[1023]<=mr_main_reset;ead17f6[969]<=cz7a26a;ead17f6[889]<=zk47c2f;ead17f6[635]<=xw6ce18;ead17f6[495]<=nt38610;ead17f6[444]<=pfc8f85;ead17f6[317]<=kq6d9c3;ead17f6[222]<=gbd91f0;end         assign jebdc77 = ead17f6,vx8bfb1 = fn71dda; initial begin kfbe35f = $fopen(".fred"); $fdisplay( kfbe35f, "%3h\n%3h", (fnf63ba >> 4) & fpbaf71, (fnf63ba >> (tj8eebd+4)) & fpbaf71 ); $fclose(kfbe35f); $readmemh(".fred", ay776be); end always @ (jebdc77) begin nedaf8d = ay776be[1]; for (jcf1afd=0; jcf1afd<th5fd8e; jcf1afd=jcf1afd+1) begin fn71dda[jcf1afd] = jebdc77[nedaf8d]; thd7c6b = ^(nedaf8d & ay776be[0]); nedaf8d = {nedaf8d, thd7c6b}; end end\r
+endmodule\r
+`timescale 1 ns / 100 ps\r
+module zm4120 (    xwcf5fb,\r
+                  rst_n,\r
+                  mr_main_reset,\r
+                  force_unidir,\r
+                  tu69a7f,\r
+                  mt1265d,\r
+                  tx_en,\r
+                  tx_er,\r
+                  jr2d34f,\r
+                  zk5d898,\r
+                  hbec4c2,\r
+                  cm62617\r
+                 );\r
+parameter tj81e62               = 8'hbc,              aaf317               = 8'hfe,              jc798b9               = 8'hfb,              czcc5cb               = 8'hfd,              ui62e5c               = 8'hf7,              an172e1               = 8'hb5,              ieb970c                = 8'h42,              oscb860                = 8'hc5,              me5c300               = 8'h50;\r
+parameter yx5ba26                = 2'b00,              dzdd135       = 2'b01,          qte89af                = 2'b10;\r
+parameter uv4ec6e              = 5'd0,               jc76374              = 5'd1,          yzb1ba3               = 5'd2,          mg8dd1d               = 5'd3,          dz6e8e9               = 5'd4,          zx7474f               = 5'd5,          qia3a7e     = 5'd6,          ux1d3f1             = 5'd7,          xje9f8d = 5'd8,          zx4fc6e          = 5'd9,          zx7e376                = 5'd10,          zkf1bb7   = 5'd11,          uk8ddbb         = 5'd12,          pf6edd9      = 5'd13,          ps76ecf         = 5'd14,          pub767a       = 5'd15,          uxbb3d3       = 5'd16,          mrd9e9d       = 5'd17,          facf4ec       = 5'd18;\r
+input                xwcf5fb;\r
+input                rst_n;\r
+input                mr_main_reset;\r
+input                force_unidir;\r
+input  [1:0]         tu69a7f;\r
+input  [7:0]         mt1265d;\r
+input                tx_en;\r
+input                tx_er;\r
+input  [15:0]        jr2d34f;\r
+output [7:0]         zk5d898;\r
+output               hbec4c2;\r
+output                  cm62617;\r
+wire                 xwcf5fb;\r
+wire                 rst_n;\r
+wire   [1:0]         tu69a7f;\r
+wire   [7:0]         mt1265d;\r
+wire                 tx_en;\r
+wire                 tx_er;\r
+wire   [15:0]        jr2d34f;\r
+reg    [7:0]         zk5d898;\r
+reg    [7:0]         en6005c;\r
+reg    [7:0]         aa2e5;\r
+reg                  ba1728;\r
+reg                  hbec4c2;\r
+reg                  yk5ca12;\r
+reg                  cm62617;\r
+reg   [7:0]          rv28481;\r
+reg                  fa4240f;\r
+reg                  ux1207b;\r
+reg   [4:0]          xlbf6fc;\r
+reg   [4:0]          jcfb7e7;\r
+reg   [4:0]          gbf7edf;\r
+reg                  hb7b979;\r
+reg                  ipdcbce;\r
+reg                  yke5e74;\r
+reg    [1:0]         ba2f3a0;\r
+wire   [1:0]         dm79d02;\r
+reg                  eace813;\r
+wire                 nr74098;\r
+reg bna04c6;\r
+reg yz8f885 ;\r
+reg ps7c42c ;\r
+reg ie98dee;\r
+reg alc6f70;\r
+reg  [(20*8):1] uk10b14;\r
+reg ri14169;\r
+reg go6282d;\r
+reg qt7099a;\r
+reg db84cd5;\r
+reg [7 : 0] ep266af;\r
+reg [7 : 0] yz3357c;\r
+reg oh9abe5;\r
+reg zkd5f2d;\r
+reg [7 : 0] dbaf96a;\r
+reg xw7cb57;\r
+reg ice5abb;\r
+reg [4 : 0] byda6c1;\r
+reg [4 : 0] wjd360a;\r
+reg [4 : 0] wy3b4d8;\r
+reg ohbb1ea;\r
+reg rtd8f55;\r
+reg vvc7aae;\r
+reg [1 : 0] ph3d576;\r
+reg [1 : 0] sueabb6;\r
+reg pf55db1;\r
+reg anaed8e;\r
+reg zk76c75;\r
+reg qte721f;\r
+reg qv390fc;\r
+reg vx8ea8d;\r
+reg sh7546e;\r
+reg [(20 * 8) : 1] cm43f26;\r
+reg [2047:0] ead17f6;\r
+wire [26:0] vx8bfb1;\r
+localparam th5fd8e = 27,nefec77 = 32'hfdffd48b;\r
+localparam [31:0] fnf63ba = nefec77;\r
+localparam tj8eebd = nefec77 & 4'hf;\r
+localparam [11:0] fpbaf71 = 'h7ff;\r
+wire [(1 << tj8eebd) -1:0] jebdc77;\r
+reg [th5fd8e-1:0] fn71dda;\r
+reg [tj8eebd-1:0] ay776be [0:1];\r
+reg [tj8eebd-1:0] nedaf8d;\r
+reg thd7c6b;\r
+integer kfbe35f;\r
+integer jcf1afd;\r
+assign dm79d02[1:0] = sh7546e ? qte89af : tu69a7f;\r
+assign nr74098 = ((sueabb6 != ph3d576) && !rtd8f55) ||                                     pf55db1;\r
+function [7:0] zza0e31;\r
+input [7:0] kf718e;\r
+input       jr38c75;\r
+input       czc63af;\r
+input [7:0] uk31d7d;\r
+begin   if(jr38c75 == 1'b0 &&      czc63af == 1'b1 &&      uk31d7d != 8'b00001111)      zza0e31 = aaf317;   else if(jr38c75 == 1'b1 && czc63af == 1'b1)      zza0e31 = aaf317;   else      zza0e31 = kf718e;\r
+end\r
+endfunction\r
+function jra5c61;\r
+input [7:0] kf718e;\r
+input       jr38c75;\r
+input       czc63af;\r
+input [7:0] uk31d7d;\r
+begin   if(jr38c75 == 1'b0 &&      czc63af == 1'b1 &&      uk31d7d   != 8'b00001111)      jra5c61 = 1'b1;   else if(jr38c75 == 1'b1 && czc63af == 1'b1)      jra5c61 = 1'b1;   else      jra5c61 = kf718e;\r
+end\r
+endfunction\r
+always @(posedge xwcf5fb or negedge rst_n)\r
+begin  if(!rst_n) begin        yz8f885 <= 1'b1;        ps7c42c <= 1'b1;        ie98dee <= 1'b0;        alc6f70 <= 1'b0;        end     else begin      yz8f885 <= ri14169;     ps7c42c <= qte721f;     ie98dee <= go6282d;     alc6f70 <= vx8ea8d;     end\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n)\r
+begin : ip70805\r
+if(!rst_n) begin   rv28481 <= 8'd0;   ux1207b <= 1'd0;   fa4240f <= 1'd0; end\r
+else begin   rv28481  <= mt1265d;   ux1207b  <= qt7099a;   fa4240f  <= db84cd5; end\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n)\r
+begin : jr9bb19\r
+if(!rst_n) begin   ba2f3a0 <= 1'd0;   eace813 <= 1'd0; end\r
+else begin   ba2f3a0 <= sueabb6;   eace813 <= (sueabb6 != ph3d576) && rtd8f55; end\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n)\r
+begin : fpb5d13   if(!rst_n)      hb7b979 <= 1'b0;   else   begin      if(byda6c1 == zx7474f)         hb7b979 <= ~ohbb1ea;      else         hb7b979 <= ohbb1ea;   end\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n)\r
+begin : gbed40b\r
+if(!rst_n)   yke5e74 <= 1'd0;\r
+else   yke5e74 <= rtd8f55;\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n)\r
+begin : su67c96   if (!rst_n) begin      xlbf6fc <= uv4ec6e;      jcfb7e7 <= uv4ec6e;      bna04c6 <= 1'b0;   end   else if (qv390fc) begin      xlbf6fc <= uv4ec6e;      jcfb7e7 <= uv4ec6e;      bna04c6 <= 1'b0;   end   else begin      jcfb7e7 <= byda6c1;      if (anaed8e) begin        bna04c6 <= 1'b0;        case (byda6c1)  yzb1ba3: begin  xlbf6fc <= uxbb3d3;     end     mg8dd1d: begin  xlbf6fc <= mrd9e9d;     end     dz6e8e9: begin  xlbf6fc <= facf4ec;     end     default: begin  xlbf6fc <= uv4ec6e;     end\r
+       endcase      end      else begin         xlbf6fc <= wy3b4d8;    case(zk76c75)   0: begin        if  (byda6c1 == jc76374) begin  bna04c6 <= 1'b1;        end   end       1: begin        if  ( (byda6c1 != uv4ec6e) && (byda6c1 != jc76374) ) begin      bna04c6 <= 1'b0;        end   end       default: begin  bna04c6 <= zk76c75;   end       endcase\r
+      end   end\r
+end\r
+always @(byda6c1 or tu69a7f or sueabb6 or qt7099a or db84cd5 or rtd8f55)\r
+begin : oh36f09   case (byda6c1)      uv4ec6e :         gbf7edf = jc76374;      jc76374 :      begin         if (sueabb6 == dzdd135)            gbf7edf = yzb1ba3;\r
+         else if (sueabb6 == yx5ba26)            gbf7edf = uv4ec6e;         else if (sueabb6 == qte89af)         begin            if (qt7099a)            begin               if(db84cd5 == 1'b0)                  gbf7edf = qia3a7e;               else                  gbf7edf = ps76ecf;            end            else               gbf7edf = uv4ec6e;         end         else            gbf7edf = uv4ec6e;      end      yzb1ba3 :         gbf7edf = mg8dd1d;      mg8dd1d :         gbf7edf = dz6e8e9;      dz6e8e9 :         gbf7edf = zx7474f;      zx7474f :         gbf7edf = yzb1ba3;      uxbb3d3 :         gbf7edf = mrd9e9d;      mrd9e9d :         gbf7edf = facf4ec;      facf4ec :         gbf7edf = uv4ec6e;\r
+      qia3a7e :      begin         if (qt7099a == 1'b1)            gbf7edf = ux1d3f1;         else         begin            if (db84cd5 == 1'b0)               gbf7edf = xje9f8d;            else               gbf7edf = zkf1bb7;         end      end      ux1d3f1 :      begin         if (qt7099a == 1'b1)            gbf7edf = ux1d3f1;         else         begin            if (db84cd5 == 1'b0)               gbf7edf = xje9f8d;            else               gbf7edf = zkf1bb7;         end      end      xje9f8d :         gbf7edf = zx4fc6e;      zx4fc6e :      begin         if (rtd8f55 == 1'b0)            gbf7edf = uv4ec6e;         else            gbf7edf = zx7e376;       end      zx7e376 :        gbf7edf = uv4ec6e;      zkf1bb7 :      begin         if (db84cd5 == 1'b0)            gbf7edf = uk8ddbb;         else            gbf7edf = pf6edd9;      end      uk8ddbb :         gbf7edf = zx4fc6e;      pf6edd9 :      begin         if (qt7099a == 1'b0 && db84cd5 == 1'b0)            gbf7edf = uk8ddbb;         else if (qt7099a == 1'b1 && db84cd5 == 1'b1)            gbf7edf = ps76ecf;         else if (qt7099a == 1'b1 && db84cd5 == 1'b0)            gbf7edf = qia3a7e;         else            gbf7edf = pf6edd9;      end      ps76ecf :         gbf7edf = pub767a;      pub767a :      begin         if (qt7099a == 1'b1)            gbf7edf = ux1d3f1;         else         begin            if (db84cd5 == 1'b0)               gbf7edf = xje9f8d;            else               gbf7edf = zkf1bb7;         end       end       default :            gbf7edf = uv4ec6e;    endcase\r
+end\r
+always @(posedge xwcf5fb or negedge rst_n)\r
+begin : of60733\r
+if(!rst_n) begin    zk5d898 <= tj81e62;    en6005c <= tj81e62;    aa2e5 <= tj81e62;    hbec4c2 <= 1'b1;    ba1728 <= 1'b1;    cm62617 <= 1'b0;    yk5ca12 <= 1'b0; end\r
+else begin     if (    (wjd360a == uv4ec6e) || (wjd360a == jc76374) || (wjd360a == yzb1ba3) || (wjd360a == mg8dd1d) || (wjd360a == dz6e8e9) || (wjd360a == zx7474f) || (wjd360a == qia3a7e) || (wjd360a == uxbb3d3) || (wjd360a == mrd9e9d) || (wjd360a == facf4ec)) begin      zk5d898 <= ep266af;    end     else begin      zk5d898 <= yz3357c;     end\r
+   hbec4c2 <= oh9abe5;   cm62617 <= zkd5f2d;      yk5ca12   <= 1'b0;\r
+   case(byda6c1)      uv4ec6e :      begin         en6005c         <= tj81e62;             ba1728        <= 1'b1;               end      jc76374 :      begin         en6005c         <= me5c300;         ba1728        <= 1'b0;         yk5ca12   <= ~zk76c75;      end      yzb1ba3 :      begin         en6005c         <= tj81e62;             ba1728        <= 1'b1;      end      mg8dd1d, uxbb3d3 :      begin         en6005c         <= ohbb1ea ? ieb970c : an172e1;         ba1728        <= 1'b0;      end      dz6e8e9 , mrd9e9d:      begin         en6005c         <= jr2d34f[7:0];         ba1728        <= 1'b0;      end      zx7474f , facf4ec:      begin         en6005c         <= jr2d34f[15:8];         ba1728        <= 1'b0;      end      qia3a7e :      begin         en6005c         <= jc798b9;                   ba1728        <= 1'b1;      end      ps76ecf :      begin         aa2e5         <= jc798b9;                   ba1728        <= 1'b1;      end      ux1d3f1 :      begin         aa2e5         <= zza0e31(dbaf96a, ice5abb, xw7cb57, dbaf96a);         ba1728        <= jra5c61(1'b0, ice5abb, xw7cb57, dbaf96a);      end      xje9f8d :      begin         aa2e5         <= czcc5cb;                   ba1728        <= 1'b1;      end      zx4fc6e,      zx7e376,      uk8ddbb :      begin         aa2e5         <= ui62e5c;                   ba1728        <= 1'b1;      end      zkf1bb7 :      begin         aa2e5         <= zza0e31(czcc5cb, ice5abb, xw7cb57, dbaf96a);             ba1728        <= 1'b1;      end      pf6edd9 :      begin         aa2e5         <= zza0e31(ui62e5c, ice5abb, xw7cb57, dbaf96a);             ba1728        <= 1'b1;      end      pub767a :      begin         aa2e5         <= aaf317;                   ba1728        <= 1'b1;      end      default :      begin         aa2e5         <= tj81e62;                   ba1728        <= 1'b1;      end   endcase\r
+end\r
+end\r
+always @(byda6c1 or vvc7aae)\r
+begin : hqbdcb1   case(byda6c1)      uv4ec6e              : ipdcbce = 1'b1;      jc76374              : ipdcbce = 1'b0;      yzb1ba3               : ipdcbce = 1'b1;      mg8dd1d               : ipdcbce = 1'b0;      uxbb3d3       : ipdcbce = 1'b0;      dz6e8e9               : ipdcbce = 1'b1;      mrd9e9d       : ipdcbce = 1'b1;      zx7474f               : ipdcbce = 1'b0;      facf4ec       : ipdcbce = 1'b0;      qia3a7e     : ipdcbce = ~vvc7aae;      ps76ecf         : ipdcbce = ~vvc7aae;      ux1d3f1             : ipdcbce = ~vvc7aae;      xje9f8d : ipdcbce = ~vvc7aae;      zx4fc6e          : ipdcbce = ~vvc7aae;      zx7e376                : ipdcbce = ~vvc7aae;      uk8ddbb         : ipdcbce = ~vvc7aae;      zkf1bb7   : ipdcbce = ~vvc7aae;      pf6edd9      : ipdcbce = ~vvc7aae;      pub767a       : ipdcbce = ~vvc7aae;      default             : ipdcbce = 1'b1;   endcase\r
+end\r
+always @(byda6c1)\r
+begin   case (byda6c1)      uv4ec6e              : uk10b14 = "IDLE_A";      jc76374              : uk10b14 = "IDLE_B";      yzb1ba3               : uk10b14 = "CFG_A";      mg8dd1d               : uk10b14 = "CFG_B";      dz6e8e9               : uk10b14 = "CFG_C";      zx7474f               : uk10b14 = "CFG_D";      qia3a7e     : uk10b14 = "START_OF_PACKET";      ux1d3f1             : uk10b14 = "TX_DATA";      xje9f8d : uk10b14 = "END_OF_PACKET_NOEXT";      zx4fc6e          : uk10b14 = "EPD2_NOEXT";      zx7e376                : uk10b14 = "EPD3";      zkf1bb7   : uk10b14 = "END_OF_PACKET_EXT";      uk8ddbb         : uk10b14 = "EXTEND_BY_1";      pf6edd9      : uk10b14 = "CARRIER_EXTEND";      ps76ecf         : uk10b14 = "START_ERROR";      pub767a       : uk10b14 = "TX_DATA_ERROR";      uxbb3d3       : uk10b14 = "cleanup_CFG_B";      mrd9e9d       : uk10b14 = "cleanup_CFG_C";      facf4ec       : uk10b14 = "cleanup_CFG_D";      default             : uk10b14 = " ERROR ";   endcase\r
+end\r
+always@* begin ri14169<=vx8bfb1[0];go6282d<=vx8bfb1[1];qt7099a<=vx8bfb1[2];db84cd5<=vx8bfb1[3];ep266af<={en6005c>>1,vx8bfb1[4]};yz3357c<={aa2e5>>1,vx8bfb1[5]};oh9abe5<=vx8bfb1[6];zkd5f2d<=vx8bfb1[7];dbaf96a<={rv28481>>1,vx8bfb1[8]};xw7cb57<=vx8bfb1[9];ice5abb<=vx8bfb1[10];byda6c1<={xlbf6fc>>1,vx8bfb1[11]};wjd360a<={jcfb7e7>>1,vx8bfb1[12]};wy3b4d8<={gbf7edf>>1,vx8bfb1[13]};ohbb1ea<=vx8bfb1[14];rtd8f55<=vx8bfb1[15];vvc7aae<=vx8bfb1[16];ph3d576<={ba2f3a0>>1,vx8bfb1[17]};sueabb6<={dm79d02>>1,vx8bfb1[18]};pf55db1<=vx8bfb1[19];anaed8e<=vx8bfb1[20];zk76c75<=vx8bfb1[21];qte721f<=vx8bfb1[22];qv390fc<=vx8bfb1[23];vx8ea8d<=vx8bfb1[24];sh7546e<=vx8bfb1[25];cm43f26<={uk10b14>>1,vx8bfb1[26]};end\r
+always@* begin ead17f6[2047]<=force_unidir;ead17f6[2046]<=tx_en;ead17f6[2044]<=tx_er;ead17f6[2040]<=en6005c[0];ead17f6[2032]<=aa2e5[0];ead17f6[2017]<=ba1728;ead17f6[1987]<=yk5ca12;ead17f6[1927]<=rv28481[0];ead17f6[1865]<=yke5e74;ead17f6[1806]<=fa4240f;ead17f6[1682]<=ba2f3a0[0];ead17f6[1565]<=ux1207b;ead17f6[1326]<=uk10b14[1];ead17f6[1317]<=dm79d02[0];ead17f6[1189]<=ps7c42c;ead17f6[1172]<=nr74098;ead17f6[1082]<=xlbf6fc[0];ead17f6[1023]<=mr_main_reset;ead17f6[932]<=ipdcbce;ead17f6[663]<=alc6f70;ead17f6[594]<=yz8f885;ead17f6[586]<=eace813;ead17f6[466]<=hb7b979;ead17f6[331]<=ie98dee;ead17f6[297]<=bna04c6;ead17f6[233]<=gbf7edf[0];ead17f6[116]<=jcfb7e7[0];end         assign jebdc77 = ead17f6,vx8bfb1 = fn71dda; initial begin kfbe35f = $fopen(".fred"); $fdisplay( kfbe35f, "%3h\n%3h", (fnf63ba >> 4) & fpbaf71, (fnf63ba >> (tj8eebd+4)) & fpbaf71 ); $fclose(kfbe35f); $readmemh(".fred", ay776be); end always @ (jebdc77) begin nedaf8d = ay776be[1]; for (jcf1afd=0; jcf1afd<th5fd8e; jcf1afd=jcf1afd+1) begin fn71dda[jcf1afd] = jebdc77[nedaf8d]; thd7c6b = ^(nedaf8d & ay776be[0]); nedaf8d = {nedaf8d, thd7c6b}; end end\r
+endmodule\r
+`timescale 1 ns / 100 ps\r
+module wwdef10 (       xwcf5fb,\r
+                       rst_n,\r
+                       hbec4c2,\r
+                       gq10304,\r
+                       lf81821,\r
+                       rvc10f,\r
+                       mr6087e,\r
+                       je43f4,\r
+                       cm62617,\r
+                       ukfd10 );\r
+input        xwcf5fb;\r
+input        rst_n;\r
+input        hbec4c2;\r
+input [7:0]  gq10304;\r
+input        lf81821;\r
+input        rvc10f;\r
+input        mr6087e;\r
+input        je43f4;\r
+input        cm62617;\r
+output [9:0] ukfd10;\r
+reg  [9:0]   ukfd10;\r
+reg  [7:0]   wj7f18d;\r
+reg          czf8c6d;\r
+wire         yxc636d;\r
+reg [9:6]    ou31b6d;\r
+reg [5:0]    ks8db69;\r
+reg [9:6]    kq6db49;\r
+reg [5:0]    ww6da48;\r
+reg          os6d240, ho69201, cm4900b, vi48058, th402c2;\r
+reg          xy1616, dob0b2, ho58593, xjc2c9b, fp164de;\r
+reg xyb26f6;\r
+reg [7 : 0] fc937b3;\r
+reg zz9bd9a;\r
+reg icdecd7;\r
+reg fnf66b9;\r
+reg qib35cf;\r
+reg cb9ae79;\r
+reg [7 : 0] jpd73cd;\r
+reg cob9e6e;\r
+reg xwcf371;\r
+reg [9 : 6] lq79b8b;\r
+reg [5 : 0] thcdc5b;\r
+reg [9 : 6] hb6e2df;\r
+reg [5 : 0] bl716fe;\r
+reg jr8b7f6;\r
+reg en5bfb7;\r
+reg xwdfdbd;\r
+reg tufedeb;\r
+reg blf6f5a;\r
+reg hqb7ad6;\r
+reg dobd6b2;\r
+reg byeb592;\r
+reg fn5ac92;\r
+reg gbd6497;\r
+reg [2047:0] ead17f6;\r
+wire [23:0] vx8bfb1;\r
+localparam th5fd8e = 24,nefec77 = 32'hfdffd30b;\r
+localparam [31:0] fnf63ba = nefec77;\r
+localparam tj8eebd = nefec77 & 4'hf;\r
+localparam [11:0] fpbaf71 = 'h7ff;\r
+wire [(1 << tj8eebd) -1:0] jebdc77;\r
+reg [th5fd8e-1:0] fn71dda;\r
+reg [tj8eebd-1:0] ay776be [0:1];\r
+reg [tj8eebd-1:0] nedaf8d;\r
+reg thd7c6b;\r
+integer kfbe35f;\r
+integer jcf1afd;\r
+always @(posedge xwcf5fb or negedge rst_n)  begin    if (rst_n == 1'b0)      czf8c6d <= 1'b0;    else      czf8c6d <= gbd6497;  end\r
+assign yxc636d = zz9bd9a ? icdecd7 : cob9e6e;\r
+always @(posedge xwcf5fb or negedge rst_n)  begin    if (rst_n == 1'b0)      ukfd10    <= 10'b00_0000_0000;    else      ukfd10    <= {hb6e2df[9:6], bl716fe[5:0]};  end\r
+always @(fc937b3 or fnf66b9 or qib35cf or xwcf371 or cb9ae79)\r
+begin  if(cb9ae79 && !xwcf371)    begin      if (fnf66b9)        wj7f18d = {fc937b3[7:6], 1'b1, fc937b3[4:0]};      if (qib35cf)        wj7f18d = 8'b110_00101;      else        wj7f18d = fc937b3;    end  else    wj7f18d = fc937b3;\r
+end\r
+always@(jpd73cd or xyb26f6)\r
+begin: lq47926\r
+case (jpd73cd[3:0])  4'b0000 :  begin      ks8db69[0] = jpd73cd[0];    ks8db69[1] = 1;    ks8db69[2] = 1;    ks8db69[3] = jpd73cd[3];    ks8db69[4] = jpd73cd[4];    ks8db69[5] = jpd73cd[4];    os6d240 = jpd73cd[4];    ho69201 = !jpd73cd[4];    cm4900b = !jpd73cd[4];    vi48058 = jpd73cd[4];  end  4'b1000 , 4'b0100 , 4'b0010 , 4'b0001 :  begin           if (jpd73cd[4] == 0)  begin      ks8db69[0] = jpd73cd[0];      ks8db69[1] = jpd73cd[1];      ks8db69[2] = jpd73cd[2];      ks8db69[3] = jpd73cd[3];      ks8db69[4] = 1;      ks8db69[5] = 0;      os6d240 = jpd73cd[4];      ho69201 = !jpd73cd[4];      cm4900b = !jpd73cd[4];      vi48058 = jpd73cd[4];    end    else if (jpd73cd[3] == 0)  begin      ks8db69[0] = jpd73cd[0];      ks8db69[1] = jpd73cd[1];      ks8db69[2] = jpd73cd[2];      ks8db69[3] = jpd73cd[3];      ks8db69[4] = jpd73cd[4];      ks8db69[5] = 1;      os6d240 = 0;      ho69201 = 0;      cm4900b = 0;      vi48058 = 0;    end    else begin      ks8db69[0] = jpd73cd[0];      ks8db69[1] = jpd73cd[1];      ks8db69[2] = 1;      ks8db69[3] = jpd73cd[3];      ks8db69[4] = 0;      ks8db69[5] = 0;      os6d240 = 0;      ho69201 = 1;      cm4900b = 1;      vi48058 = 0;    end  end  4'b1100 : begin    ks8db69[0] = jpd73cd[0];    ks8db69[1] = jpd73cd[1];    ks8db69[2] = jpd73cd[2];    ks8db69[3] = jpd73cd[3];    ks8db69[4] = jpd73cd[4];    if (xyb26f6 == 1 && jpd73cd[4] == 1)  begin           os6d240 = xyb26f6;      ho69201 = !xyb26f6;      cm4900b = 0;      vi48058 = 1;      ks8db69[5] = 1;    end    else begin      os6d240 = 0;      ho69201 = 0;      cm4900b = 0;      vi48058 = 0;      if (jpd73cd[4] == 0)        ks8db69[5] = 1;      else        ks8db69[5] = 0;    end  end  4'b0011 , 4'b1010 , 4'b0101 , 4'b1001 , 4'b0110 :  begin     ks8db69[0] = jpd73cd[0];    ks8db69[1] = jpd73cd[1];    ks8db69[2] = jpd73cd[2];    ks8db69[3] = jpd73cd[3];    ks8db69[4] = jpd73cd[4];    os6d240 = 0;    ho69201 = 0;    cm4900b = 0;    vi48058 = 0;    if (jpd73cd[4] == 0)      ks8db69[5] = 1;    else      ks8db69[5] = 0;  end  4'b1111:  begin        ks8db69[0] = jpd73cd[0];    ks8db69[1] = 0;    ks8db69[2] = jpd73cd[2];    ks8db69[3] = 0;    ks8db69[4] = jpd73cd[4];    ks8db69[5] = jpd73cd[4];    os6d240 = jpd73cd[4];    ho69201 = !jpd73cd[4];    cm4900b = !jpd73cd[4];    vi48058 = jpd73cd[4];  end  4'b0111 :  begin    ks8db69[0] = jpd73cd[0];    ks8db69[1] = jpd73cd[1];    ks8db69[2] = jpd73cd[2];    ks8db69[3] = jpd73cd[3];    ks8db69[4] = jpd73cd[4];    ks8db69[5] = 0;    ho69201 = 0;    os6d240 = jpd73cd[4];    cm4900b = 0;    vi48058 = 1;  end  4'b1101 , 4'b1011 , 4'b1110 :  begin      ks8db69[0] = jpd73cd[0];    ks8db69[1] = jpd73cd[1];    ks8db69[2] = jpd73cd[2];    ks8db69[3] = jpd73cd[3];    ks8db69[4] = jpd73cd[4];    ks8db69[5] = 0;    ho69201 = 0;    os6d240 = jpd73cd[4];    cm4900b = 0;    vi48058 = jpd73cd[4];  end  default : begin    ks8db69[5:0] = 0;    os6d240 = 0;    ho69201 = 0;    cm4900b = 0;    vi48058 = 0;  end\r
+endcase\r
+end\r
+always@(jr8b7f6 or en5bfb7 or xwdfdbd or tufedeb or xwcf371 or thcdc5b)\r
+begin: mee5e64\r
+if ((xwdfdbd && xwcf371) || (tufedeb && !xwcf371) ||   (!xwdfdbd && !tufedeb))  begin  ww6da48[5:0] = thcdc5b[5:0];  if (!jr8b7f6 && !en5bfb7)    th402c2 = xwcf371;  else    th402c2 = jr8b7f6;\r
+end\r
+else  begin  ww6da48[0] = !thcdc5b[0];  ww6da48[1] = !thcdc5b[1];  ww6da48[2] = !thcdc5b[2];  ww6da48[3] = !thcdc5b[3];  ww6da48[4] = !thcdc5b[4];  ww6da48[5] = !thcdc5b[5];  if (!jr8b7f6 && !en5bfb7)    th402c2 = xwcf371;  else    th402c2 = !jr8b7f6;\r
+end\r
+end\r
+always@(jpd73cd or xyb26f6 or bl716fe or blf6f5a)\r
+begin: bn9b0c8\r
+case (jpd73cd[7:5])  3'b000 : begin    ou31b6d[6] = jpd73cd[5];    ou31b6d[7] = !jpd73cd[6];    ou31b6d[8] = jpd73cd[7];    ou31b6d[9] = 0;    ho58593 = 1;    xjc2c9b = 0;    xy1616 = 0;    dob0b2 = 1;  end  3'b001 , 3'b010 , 3'b101 , 3'b110 : begin    ou31b6d[6] = jpd73cd[5];    ou31b6d[7] = jpd73cd[6];    ou31b6d[8] = jpd73cd[7];    ou31b6d[9] = !jpd73cd[7];    if (xyb26f6 == 1)      ho58593 = 1;    else      ho58593 = 0;    xjc2c9b = 0;    xy1616 = 0;    dob0b2 = 0;  end  3'b011 : begin    ou31b6d[6] = jpd73cd[5];    ou31b6d[7] = jpd73cd[6];    ou31b6d[8] = jpd73cd[7];    ou31b6d[9] = 0;    ho58593 = 0;    xjc2c9b = 1;    xy1616 = 0;    dob0b2 = 0;  end  3'b100 : begin    ou31b6d[6] = jpd73cd[5];    ou31b6d[7] = jpd73cd[6];    ou31b6d[8] = jpd73cd[7];    ou31b6d[9] = 0;    ho58593 = 1;    xjc2c9b = 0;    xy1616 = 0;    dob0b2 = 1;  end  3'b111 : begin    if ((bl716fe[4] == 1 && bl716fe[5] == 1 && blf6f5a == 0) ||      (bl716fe[4] == 0 && bl716fe[5] == 0 && blf6f5a == 1) || (xyb26f6 == 1))  begin      ou31b6d[6] = 0;      ou31b6d[7] = jpd73cd[6];      ou31b6d[8] = jpd73cd[7];      ou31b6d[9] = 1;      ho58593 = 0;      xjc2c9b = 1;      xy1616 = 1;      dob0b2 = 0;    end    else begin      ou31b6d[6] = jpd73cd[5];      ou31b6d[7] = jpd73cd[6];      ou31b6d[8] = jpd73cd[7];      ou31b6d[9] = 0;      ho58593 = 0;      xjc2c9b = 1;      xy1616 = 1;      dob0b2 = 0;    end  end  default : begin    ou31b6d[6] = jpd73cd[5];    ou31b6d[7] = jpd73cd[6];    ou31b6d[8] = jpd73cd[7];    ou31b6d[9] = 0;    ho58593 = 0;    xjc2c9b = 0;    xy1616 = 0;    dob0b2 = 0;  end\r
+endcase\r
+end\r
+always@(hqb7ad6 or dobd6b2 or byeb592 or fn5ac92 or blf6f5a or lq79b8b)\r
+begin: jrbfef8\r
+if ((byeb592 && blf6f5a) || (fn5ac92 && !blf6f5a) ||   (!byeb592 && !fn5ac92))  begin  kq6db49[9:6] = lq79b8b[9:6];  if (!hqb7ad6 && !dobd6b2)    fp164de = blf6f5a;  else    fp164de = hqb7ad6;\r
+end\r
+else  begin  kq6db49[6] = !lq79b8b[6];  kq6db49[7] = !lq79b8b[7];  kq6db49[8] = !lq79b8b[8];  kq6db49[9] = !lq79b8b[9];  if (!hqb7ad6 && !dobd6b2)    fp164de = blf6f5a;  else    fp164de = !hqb7ad6;\r
+end\r
+end\r
+always@* begin xyb26f6<=vx8bfb1[0];fc937b3<={gq10304>>1,vx8bfb1[1]};zz9bd9a<=vx8bfb1[2];icdecd7<=vx8bfb1[3];fnf66b9<=vx8bfb1[4];qib35cf<=vx8bfb1[5];cb9ae79<=vx8bfb1[6];jpd73cd<={wj7f18d>>1,vx8bfb1[7]};cob9e6e<=vx8bfb1[8];xwcf371<=vx8bfb1[9];lq79b8b<={ou31b6d>>1,vx8bfb1[10]};thcdc5b<={ks8db69>>1,vx8bfb1[11]};hb6e2df<={kq6db49>>1,vx8bfb1[12]};bl716fe<={ww6da48>>1,vx8bfb1[13]};jr8b7f6<=vx8bfb1[14];en5bfb7<=vx8bfb1[15];xwdfdbd<=vx8bfb1[16];tufedeb<=vx8bfb1[17];blf6f5a<=vx8bfb1[18];hqb7ad6<=vx8bfb1[19];dobd6b2<=vx8bfb1[20];byeb592<=vx8bfb1[21];fn5ac92<=vx8bfb1[22];gbd6497<=vx8bfb1[23];end\r
+always@* begin ead17f6[2047]<=gq10304[0];ead17f6[2046]<=lf81821;ead17f6[2044]<=rvc10f;ead17f6[2040]<=mr6087e;ead17f6[2032]<=je43f4;ead17f6[2016]<=cm62617;ead17f6[1985]<=wj7f18d[0];ead17f6[1922]<=czf8c6d;ead17f6[1796]<=yxc636d;ead17f6[1544]<=ou31b6d[6];ead17f6[1302]<=ho58593;ead17f6[1115]<=fp164de;ead17f6[1105]<=vi48058;ead17f6[1041]<=ks8db69[0];ead17f6[1023]<=hbec4c2;ead17f6[651]<=dob0b2;ead17f6[557]<=xjc2c9b;ead17f6[552]<=cm4900b;ead17f6[325]<=xy1616;ead17f6[276]<=ho69201;ead17f6[162]<=th402c2;ead17f6[138]<=os6d240;ead17f6[69]<=ww6da48[0];ead17f6[34]<=kq6db49[6];end         assign jebdc77 = ead17f6,vx8bfb1 = fn71dda; initial begin kfbe35f = $fopen(".fred"); $fdisplay( kfbe35f, "%3h\n%3h", (fnf63ba >> 4) & fpbaf71, (fnf63ba >> (tj8eebd+4)) & fpbaf71 ); $fclose(kfbe35f); $readmemh(".fred", ay776be); end always @ (jebdc77) begin nedaf8d = ay776be[1]; for (jcf1afd=0; jcf1afd<th5fd8e; jcf1afd=jcf1afd+1) begin fn71dda[jcf1afd] = jebdc77[nedaf8d]; thd7c6b = ^(nedaf8d & ay776be[0]); nedaf8d = {nedaf8d, thd7c6b}; end end\r
+endmodule\r
+`timescale 1 ns / 100 ps\r
+module sgmii_channel_smi_core (\r
+   tx_clk_125 ,\r
+   serdes_recovered_clk ,\r
+   rx_clk_125 ,\r
+   rst_n ,\r
+   gbe_mode ,\r
+   sgmii_mode ,\r
+   signal_detect ,\r
+   debug_link_timer_short,\r
+   force_isolate,\r
+   force_loopback,\r
+   force_unidir,\r
+   operational_rate,\r
+   rx_compensation_err,\r
+   ctc_drop_flag,\r
+   ctc_add_flag,\r
+   an_link_ok,\r
+`ifdef SGMII_YES_SINGLE_CLOCK\r
+   tx_clock_enable_sink ,\r
+   tx_clock_enable_source ,\r
+   rx_clock_enable_sink ,\r
+   rx_clock_enable_source ,\r
+`else\r
+   tx_clk_mii ,\r
+   rx_clk_mii ,\r
+`endif\r
+   rx_data ,\r
+   rx_kcntl ,\r
+   rx_even ,\r
+   rx_disp_err ,\r
+   rx_cv_err ,\r
+   rx_err_decode_mode ,\r
+   tx_d ,\r
+   tx_en ,\r
+   tx_er ,\r
+   mr_adv_ability ,\r
+   mr_an_enable ,\r
+   mr_main_reset ,\r
+   mr_restart_an ,\r
+   mr_an_complete ,\r
+   mr_lp_adv_ability ,\r
+   mr_page_rx ,\r
+   rx_d ,\r
+   rx_dv ,\r
+   rx_er ,\r
+   col ,\r
+   crs ,\r
+   tx_data,\r
+   tx_kcntl,\r
+   tx_disparity_cntl,\r
+   xmit_autoneg\r
+   ) ;\r
+input         tx_clk_125 ;\r
+input         serdes_recovered_clk ;\r
+input         rx_clk_125 ;\r
+`ifdef SGMII_YES_SINGLE_CLOCK\r
+input  tx_clock_enable_sink;\r
+output tx_clock_enable_source;\r
+input  rx_clock_enable_sink;\r
+output rx_clock_enable_source;\r
+`else\r
+input tx_clk_mii;\r
+input rx_clk_mii;\r
+`endif\r
+input         rst_n ;\r
+input         signal_detect ;\r
+input         gbe_mode ;\r
+input         sgmii_mode ;\r
+input         debug_link_timer_short ;\r
+input         force_isolate ;\r
+input         force_loopback ;\r
+input         force_unidir ;\r
+input [1:0]   operational_rate;\r
+output        rx_compensation_err;\r
+output        ctc_drop_flag;\r
+output        ctc_add_flag;\r
+output        an_link_ok;\r
+input [7:0]   rx_data ;\r
+input         rx_kcntl ;\r
+input         rx_even ;\r
+input         rx_disp_err ;\r
+input         rx_cv_err ;\r
+input         rx_err_decode_mode ;\r
+input [7:0]   tx_d ;\r
+input         tx_en ;\r
+input         tx_er ;\r
+input [15:0]  mr_adv_ability;\r
+input         mr_an_enable;\r
+input         mr_main_reset;\r
+input         mr_restart_an;\r
+output        mr_an_complete;\r
+output [15:0] mr_lp_adv_ability;\r
+output        mr_page_rx;\r
+output [7:0]   rx_d ;\r
+output         rx_dv ;\r
+output         rx_er ;\r
+output         col ;\r
+output         crs ;\r
+output [7:0]   tx_data ;\r
+output         tx_kcntl ;\r
+output         tx_disparity_cntl ;\r
+output         xmit_autoneg ;\r
+`ifdef SGMII_YES_ENC\r
+wire [7:0]      wl1813f ;\r
+wire            lqc09fd ;\r
+wire            yk5ca12 ;\r
+`endif\r
+wire [1:0]      tu69a7f ;\r
+wire [15:0]     xj45a69 ;\r
+wire [15:0]     jr2d34f ;\r
+wire [15:0]     mr_adv_ability ;\r
+wire [15:0]     mr_lp_adv_ability ;\r
+wire tj3d21d;\r
+wire [7:0] eafa8aa;\r
+wire icd4550;\r
+wire zma2a81;\r
+wire rx_compensation_err;\r
+wire hdaa059;\r
+wire bl502ce;\r
+wire xl81677;\r
+wire dob3be;\r
+wire go59df3;\r
+wire an_link_ok;\r
+reg hq1e17d;\r
+reg qgf0bea;\r
+reg cb85f51;\r
+reg vk2fa8d;\r
+reg kq7d46b;\r
+reg eaea358;\r
+reg qi5e51 ;\r
+reg do2f289 ;\r
+reg tu7944a ;\r
+reg zkca252 ;\r
+reg cz51293 ;\r
+reg do8949d ;\r
+reg fn4a4ea ;\r
+wire [7:0] xw52757;\r
+wire ls93aba;\r
+wire wy9d5d3;\r
+wire [7:0] kqeae99;\r
+wire by574c9;\r
+wire tjba64a;\r
+wire end3257;\r
+wire pu992bc;\r
+wire ctc_drop_flag;\r
+wire ctc_add_flag;\r
+reg by578e6;\r
+reg ukbc733;\r
+wire [7:0] jpe3998;\r
+wire rv1ccc7;\r
+wire vve663e;\r
+reg ep331f6;\r
+reg ie98fb5;\r
+reg blc7da8;\r
+`ifndef SGMII_YES_SINGLE_CLOCK\r
+reg ie3ed46;\r
+reg rtf6a30;\r
+`endif\r
+parameter DYNAMIC_LT_10MBPS = 340;\r
+parameter DYNAMIC_HT_10MBPS = 680;\r
+parameter DYNAMIC_LT_100MBPS = 34;\r
+parameter DYNAMIC_HT_100MBPS = 68;\r
+parameter DYNAMIC_LT_1000MBPS = 16;\r
+parameter DYNAMIC_HT_1000MBPS = 32;\r
+parameter STATIC_LO_THRESH = 16;\r
+parameter STATIC_HI_THRESH = 32;\r
+parameter LINK_TIMER_SH = 21'h1fff01;\r
+`ifndef SGMII_YES_SINGLE_CLOCK\r
+`endif\r
+`ifdef SGMII_YES_SINGLE_CLOCK\r
+`else\r
+`endif\r
+`ifdef SGMII_YES_CTC_DYNAMIC\r
+`endif\r
+`ifdef SGMII_YES_CTC_STATIC\r
+`endif\r
+`ifdef SGMII_NO_CTC\r
+`endif\r
+`ifdef SGMII_YES_ENC\r
+`else\r
+`endif\r
+`ifdef SGMII_YES_ENC\r
+`else\r
+`endif\r
+reg rt6b020;\r
+reg oh2c505;\r
+reg ww4c23c;\r
+reg rt5ffdd;\r
+reg zkc0833;\r
+reg wwff778;\r
+reg go6282d;\r
+reg [1 : 0] ead41f5;\r
+reg [7 : 0] fa69a8f;\r
+reg jc4d47a;\r
+reg ep8f4a4;\r
+reg ecac00;\r
+reg kq56000;\r
+reg ntb0000;\r
+reg [7 : 0] an80006;\r
+reg qt7099a;\r
+reg db84cd5;\r
+reg co5a5e;\r
+reg ri14169;\r
+reg vxa0b4b;\r
+reg [1 : 0] qt7a525;\r
+reg [15 : 0] ym387;\r
+reg [15 : 0] ls1c38;\r
+reg al6a3d2;\r
+reg [7 : 0] al70e1b;\r
+reg co870dd;\r
+reg xl386e9;\r
+reg gbc374e;\r
+reg ba1ba75;\r
+reg bldd3ab;\r
+reg ble9d5f;\r
+reg en4eafe;\r
+reg icfae0d;\r
+reg rtd7068;\r
+reg pub8346;\r
+reg suc1a32;\r
+reg uxd191;\r
+reg ic68c8c;\r
+reg do25e9c;\r
+reg pu2f4e2;\r
+reg mr7a712;\r
+reg ald3895;\r
+reg ng9c4ad;\r
+reg she256b;\r
+reg gd12b5c;\r
+reg [7 : 0] kf95ae5;\r
+reg lsad72c;\r
+reg ld6b963;\r
+reg [7 : 0] ic5cb1f;\r
+reg yke58f8;\r
+reg cb2c7c0;\r
+reg ps63e05;\r
+reg ks1f02b;\r
+reg qtf8158;\r
+reg byc0ac4;\r
+reg [7 : 0] mg5623;\r
+reg sw2b118;\r
+reg jc588c0;\r
+reg goc4602;\r
+reg yz23010;\r
+reg cb18084;\r
+reg [2047:0] ead17f6;\r
+wire [60:0] vx8bfb1;\r
+`ifdef SGMII_YES_SINGLE_CLOCK\r
+`else\r
+`endif\r
+`ifdef SGMII_YES_ENC\r
+`endif\r
+`ifndef SGMII_YES_SINGLE_CLOCK\r
+`endif\r
+`ifndef SGMII_YES_SINGLE_CLOCK\r
+`endif\r
+`ifdef SGMII_YES_SINGLE_CLOCK\r
+`else\r
+`endif\r
+`ifdef SGMII_YES_CTC_DYNAMIC\r
+`endif\r
+`ifdef SGMII_YES_CTC_STATIC\r
+`endif\r
+`ifdef SGMII_NO_CTC\r
+`endif\r
+`ifdef SGMII_YES_ENC\r
+`else\r
+`endif\r
+`ifdef SGMII_YES_ENC\r
+`else\r
+`endif\r
+localparam th5fd8e = 61,nefec77 = 32'hfdffca8b;\r
+localparam [31:0] fnf63ba = nefec77;\r
+localparam tj8eebd = nefec77 & 4'hf;\r
+localparam [11:0] fpbaf71 = 'h7ff;\r
+wire [(1 << tj8eebd) -1:0] jebdc77;\r
+reg [th5fd8e-1:0] fn71dda;\r
+reg [tj8eebd-1:0] ay776be [0:1];\r
+reg [tj8eebd-1:0] nedaf8d;\r
+reg thd7c6b;\r
+integer kfbe35f;\r
+integer jcf1afd;\r
+`ifdef SGMII_YES_SINGLE_CLOCK\r
+`else\r
+`endif\r
+`ifdef SGMII_YES_ENC\r
+`endif\r
+`ifndef SGMII_YES_SINGLE_CLOCK\r
+`endif\r
+`ifndef SGMII_YES_SINGLE_CLOCK\r
+`endif\r
+`ifdef SGMII_YES_SINGLE_CLOCK\r
+`else\r
+`endif\r
+`ifdef SGMII_YES_CTC_DYNAMIC\r
+`endif\r
+`ifdef SGMII_YES_CTC_STATIC\r
+`endif\r
+`ifdef SGMII_NO_CTC\r
+`endif\r
+`ifdef SGMII_YES_ENC\r
+`else\r
+`endif\r
+`ifdef SGMII_YES_ENC\r
+`else\r
+`endif\r
+`ifdef SGMII_YES_SINGLE_CLOCK\r
+`else\r
+`endif\r
+`ifdef SGMII_YES_ENC\r
+`endif\r
+`ifndef SGMII_YES_SINGLE_CLOCK\r
+`endif\r
+assign bl502ce = ({ep8f4a4, kq56000, ecac00} == 3'b100) ? 1'b1 : 1'b0;\r
+assign xl81677 = ({ep8f4a4, kq56000, ecac00} == 3'b111) ? 1'b1 : 1'b0;\r
+assign dob3be = ba1ba75 | bldd3ab;\r
+assign go59df3 = kq56000 | ecac00;\r
+assign tj3d21d = (ntb0000) ? ble9d5f : en4eafe;\r
+always @(posedge tx_clk_125 or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        ep331f6 <= 1'b0;        end     else begin      ep331f6 <= ~goc4602;    end\r
+end\r
+always @(posedge rx_clk_125 or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        ie98fb5 <= 1'b0;        end     else begin      ie98fb5 <= ~yz23010;    end\r
+end\r
+always @(posedge serdes_recovered_clk or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        blc7da8 <= 1'b0;        end     else begin      blc7da8 <= ~cb18084;    end\r
+end\r
+`ifndef SGMII_YES_SINGLE_CLOCK\r
+       always @(posedge tx_clk_mii or negedge rst_n)   begin   if (rst_n == 1'b0) begin        ie3ed46 <= 1'b0;        end     else begin      ie3ed46 <= ~ie3ed46;    end     end     always @(posedge rx_clk_mii or negedge rst_n)   begin   if (rst_n == 1'b0) begin        rtf6a30 <= 1'b0;        end     else begin      rtf6a30 <= ~rtf6a30;    end     end\r
+`endif\r
+`ifdef SGMII_YES_SINGLE_CLOCK\r
+       rv9e7a xl32b67 (   .rst_n               ( rst_n ) ,   .gbe_mode            ( rt6b020 ) ,   .xwcf5fb                 ( tx_clk_125 ) ,   .mr7afdb   ( tx_clock_enable_sink ) ,   .yxcc8f0 ( tx_clock_enable_source ) ,   .wje7ecc                ( ead41f5 ) ,   .force_isolate       ( zkc0833 ) ,   .fc3f1d7             ( an80006 ) ,   .wjf8ebb              ( db84cd5 ) ,   .dzc75dd               ( qt7099a ) ,   .dzd777a            ( xw52757 ) ,   .irbbbd6             ( ls93aba ) ,   .rtddeb4              ( wy9d5d3 )    );  xwcf593 fn6e2a4 (   .rst_n               ( rst_n ) ,   .gbe_mode            ( rt6b020 ) ,   .force_isolate       ( zkc0833 ) ,   .xwcf5fb                 ( rx_clk_125 ) ,   .mr7afdb   ( rx_clock_enable_sink ) ,   .yxcc8f0 ( rx_clock_enable_source ) ,   .wje7ecc                ( ead41f5 ) ,   .fc3f1d7             ( ic5cb1f ) ,   .wjf8ebb              ( yke58f8 ) ,   .dzc75dd               ( cb2c7c0 ) ,   .ym3111a              ( ps63e05 ) ,   .ie888d0              ( ks1f02b ) ,   .dzd777a            ( rx_d ) ,   .irbbbd6             ( rx_er ) ,   .rtddeb4              ( rx_dv ),   .vxc81f             ( col ) ,   .xj640ff             ( crs )    );\r
+`else\r
+       pf6bfe4 xl32b67 (   .rst_n           ( rst_n ) ,   .gbe_mode        ( rt6b020 ) ,   .zxfc9f8          ( tx_clk_mii ) ,   .zke4fc7         ( ead41f5 ) ,   .force_isolate   ( zkc0833 ) ,   .fc3f1d7         ( an80006 ) ,   .wjf8ebb          ( db84cd5 ) ,   .dzc75dd           ( qt7099a ) ,   .do3aeef         ( tx_clk_125 ) ,   .dzd777a        ( xw52757 ) ,   .irbbbd6         ( ls93aba ) ,   .rtddeb4          ( wy9d5d3 )    );       gq2bcea fn6e2a4 (   .rst_n           ( rst_n ) ,   .gbe_mode        ( rt6b020 ) ,   .force_isolate   ( zkc0833 ) ,   .zxfc9f8          ( rx_clk_125 ) ,   .fc3f1d7         ( ic5cb1f ) ,   .wjf8ebb          ( yke58f8 ) ,   .dzc75dd           ( cb2c7c0 ) ,   .ym3111a          ( ps63e05 ) ,   .ie888d0          ( ks1f02b ) ,   .do3aeef         ( rx_clk_mii ) ,   .wl2340c        ( ead41f5 ) ,   .dzd777a        ( rx_d ) ,   .irbbbd6         ( rx_er ) ,   .rtddeb4          ( rx_dv ),   .vxc81f         ( col ) ,   .xj640ff         ( crs )    );\r
+`endif\r
+`ifdef SGMII_YES_CTC_DYNAMIC\r
+                               vk96fe1 # (.DYNAMIC_HT_1000MBPS(DYNAMIC_HT_1000MBPS), .DYNAMIC_LT_1000MBPS(DYNAMIC_LT_1000MBPS),  .DYNAMIC_HT_100MBPS (DYNAMIC_HT_100MBPS),  .DYNAMIC_LT_100MBPS (DYNAMIC_LT_100MBPS),  .DYNAMIC_HT_10MBPS  (DYNAMIC_HT_10MBPS),   .DYNAMIC_LT_10MBPS  (DYNAMIC_LT_10MBPS)) hbf39cf (  .rst_n (rst_n),  .mr_main_reset (gd12b5c),  .an_link_ok (an_link_ok),  .lqe16b6 (co5a5e),  .gbe_mode (rt6b020),  .operational_rate (ead41f5),  .kdd6cdf (serdes_recovered_clk),  .oub66fd (fa69a8f),  .ksb37e9 (jc4d47a),  .hd9bf49 (al6a3d2),  .vidfa4f (rx_clk_125),  .enfd27b (eafa8aa),  .lde93dc (icd4550),  .ic49ee7 (zma2a81),  .xj4f739 (rx_compensation_err),  .ctc_drop_flag (ctc_drop_flag),  .ctc_add_flag (ctc_add_flag)  );\r
+`endif\r
+`ifdef SGMII_YES_CTC_STATIC\r
+                               tw86c28 # (.STATIC_HI_THRESH(STATIC_HI_THRESH), .STATIC_LO_THRESH(STATIC_LO_THRESH)) hbf39cf (  .rst_n (rst_n),  .mr_main_reset (gd12b5c),  .kdd6cdf (serdes_recovered_clk),  .oub66fd (fa69a8f),  .ksb37e9 (jc4d47a),  .hd9bf49 (al6a3d2),  .vidfa4f (rx_clk_125),  .enfd27b (eafa8aa),  .lde93dc (icd4550),  .ic49ee7 (zma2a81),  .xj4f739 (rx_compensation_err),  .ctc_drop_flag (ctc_drop_flag),  .ctc_add_flag (ctc_add_flag)  );\r
+`endif\r
+`ifdef SGMII_NO_CTC\r
+                               zxdd74c  hbf39cf (  .rst_n (rst_n),  .mr_main_reset (gd12b5c),  .kdd6cdf (serdes_recovered_clk),  .oub66fd (fa69a8f),  .ksb37e9 (jc4d47a),  .hd9bf49 (al6a3d2),  .vidfa4f (rx_clk_125),  .enfd27b (eafa8aa),  .lde93dc (icd4550),  .ic49ee7 (zma2a81),  .xj4f739 (rx_compensation_err)  );\r
+assign ctc_drop_flag = 1'b0;\r
+assign ctc_add_flag = 1'b0;\r
+`endif\r
+always @(posedge rx_clk_125 or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        by578e6 <= 1'b0;        ukbc733 <= 1'b0;        end     else begin      by578e6 <= wwff778;     ukbc733 <= qtf8158;     end\r
+end\r
+`ifdef SGMII_YES_ENC\r
+       assign jpe3998  = byc0ac4 ? wl1813f  : al70e1b; assign rv1ccc7 = byc0ac4 ? lqc09fd : co870dd;   assign vve663e   = byc0ac4 ? 1'b0         : xl386e9;\r
+`else\r
+       assign jpe3998  = byc0ac4 ? tx_data      : al70e1b;     assign rv1ccc7 = byc0ac4 ? tx_kcntl     : co870dd;      assign vve663e   = byc0ac4 ? 1'b0         : xl386e9;\r
+`endif\r
+enc9ddb enc9ddb (      .hb500c1         ( rx_clk_125 ) ,   .rst_n           ( rst_n ) ,   .mr_main_reset   ( gd12b5c ) ,      .signal_detect     ( ww4c23c ) ,   .rx_data         ( mg5623 ) ,   .rx_kcntl        ( sw2b118 ) ,   .tj3d21d          ( jc588c0 ) ,      .ira1445     ( ira1445 ) ,   .rx_even         ( hdaa059 )   );\r
+gqa018 gqa018 (      .hb500c1         ( rx_clk_125 ) ,   .rst_n           ( rst_n ) ,   .mr_main_reset   ( gd12b5c ) ,   .sgmii_mode      ( oh2c505 ) ,   .gbe_mode        ( rt6b020 ) ,   .qif9e9     ( mr_adv_ability[12] ) ,       .rx_data         ( mg5623 ) ,   .rx_kcntl        ( sw2b118 ) ,   .tj3d21d          ( jc588c0 ) ,   .ira1445     ( ira1445 ) ,   .rx_even         ( gbc374e ) ,   .tu69a7f            ( qt7a525 ) ,      .xj45a69( xj45a69 ) ,   .vieee84  ( vieee84 ) ,   .kq77423    ( kq77423 ) ,   .hdba119 ( hdba119 ) ,   .lqd08cf     ( kqeae99 ) ,   .vx8467a     ( tjba64a ) ,   .oh233d6      ( by574c9 )   );\r
+   uk1087d # (.LINK_TIMER_SH(LINK_TIMER_SH)) uk1087d (      .xwcf5fb                ( tx_clk_125 ) ,      .rst_n              ( rst_n ) ,      .gbe_mode           ( rt6b020 ) ,      .sgmii_mode         ( oh2c505 ) ,      .force_unidir       ( go6282d ) ,      .mr_main_reset      ( gd12b5c  ) ,      .mr_restart_an      ( vxa0b4b  ) ,      .mr_an_enable       ( co5a5e ) ,      .mr_adv_ability     ( mr_adv_ability ) ,      .mr_lp_adv_ability  ( mr_lp_adv_ability ) ,      .mr_page_rx         ( mr_page_rx ) ,      .mr_an_complete     ( mr_an_complete ) ,      .ou2150a   ( rt5ffdd ) ,      .ira1445        ( ira1445 ) ,      .gqa22d       ( hdba119 ) ,      .gb51169          ( kq77423 ) ,      .ie88b4d        ( vieee84 ) ,      .xj45a69      ( ym387 ) ,      .jr2d34f      ( jr2d34f ) ,      .tu69a7f               ( tu69a7f ),      .an_link_ok         ( an_link_ok )      );\r
+`ifdef SGMII_YES_ENC\r
+                               zm4120 zm4120 (  .xwcf5fb             ( tx_clk_125 ) ,  .rst_n           ( rst_n ) ,  .mr_main_reset   ( gd12b5c ),  .force_unidir    ( go6282d ),  .mt1265d           ( kf95ae5 ) ,  .tx_en           ( ld6b963 ) ,  .tx_er           ( lsad72c ) ,  .tu69a7f            ( qt7a525 ) ,  .jr2d34f   ( ls1c38 ) ,  .zk5d898           ( wl1813f ) ,  .hbec4c2         ( lqc09fd ),  .cm62617    ( yk5ca12 )  );\r
+                               wwdef10  wwdef10 (  .xwcf5fb (tx_clk_125),  .rst_n (rst_n),  .hbec4c2 (lqc09fd),  .gq10304 (wl1813f),  .lf81821 (1'b0),  .rvc10f (1'b0),  .mr6087e (1'b0),  .je43f4 (1'b1),  .cm62617 (yk5ca12),  .ukfd10  ({tx_disparity_cntl, tx_kcntl, tx_data})     );\r
+`else\r
+                               zm4120 zm4120 (  .xwcf5fb             ( tx_clk_125 ) ,  .rst_n           ( rst_n ) ,  .mr_main_reset   ( gd12b5c ),  .force_unidir    ( go6282d ),  .mt1265d           ( kf95ae5 ) ,  .tx_en           ( ld6b963 ) ,  .tx_er           ( lsad72c ) ,  .tu69a7f            ( qt7a525 ) ,  .jr2d34f   ( ls1c38 ) ,  .zk5d898           ( tx_data ) ,  .hbec4c2         ( tx_kcntl ),  .cm62617    ( tx_disparity_cntl )  );\r
+`endif\r
+assign end3257 = rx_dv & qt7099a;\r
+assign pu992bc = rx_dv;\r
+assign xmit_autoneg = ((qt7a525==2'b01)||(qt7a525==2'b00)) ? 1'b1 : 1'b0;\r
+always @(posedge tx_clk_125 or negedge rst_n)\r
+begin  if (rst_n == 1'b0) begin        hq1e17d <= 1'b0;        qgf0bea <= 1'b0;        cb85f51 <= 1'b0;        vk2fa8d <= 1'b0;        kq7d46b <= 1'b0;        eaea358 <= 1'b0;        qi5e51 <= 1'b1; do2f289 <= 1'b1;        tu7944a <= 1'b1;        zkca252 <= 1'b1;        cz51293 <= 1'b1;        do8949d <= 1'b1;        fn4a4ea <= 1'b1;        end     else begin              hq1e17d <= rt6b020;     qgf0bea <= icfae0d;     qi5e51 <= ri14169;      do2f289 <= do25e9c;             cb85f51 <= rtd7068;             vk2fa8d <= rtd7068 & (~pub8346);                kq7d46b <= ~rtd7068 & (pub8346);                eaea358 <= suc1a32 || uxd191;           tu7944a <= pu2f4e2 | ic68c8c;   zkca252 <= mr7a712;     cz51293 <= ald3895;     do8949d <= ng9c4ad;     fn4a4ea <= mr7a712 | ald3895 | ng9c4ad | she256b;       end\r
+end\r
+always@* begin rt6b020<=vx8bfb1[0];oh2c505<=vx8bfb1[1];ww4c23c<=vx8bfb1[2];rt5ffdd<=vx8bfb1[3];zkc0833<=vx8bfb1[4];wwff778<=vx8bfb1[5];go6282d<=vx8bfb1[6];ead41f5<={operational_rate>>1,vx8bfb1[7]};fa69a8f<={rx_data>>1,vx8bfb1[8]};jc4d47a<=vx8bfb1[9];ep8f4a4<=vx8bfb1[10];ecac00<=vx8bfb1[11];kq56000<=vx8bfb1[12];ntb0000<=vx8bfb1[13];an80006<={tx_d>>1,vx8bfb1[14]};qt7099a<=vx8bfb1[15];db84cd5<=vx8bfb1[16];co5a5e<=vx8bfb1[17];ri14169<=vx8bfb1[18];vxa0b4b<=vx8bfb1[19];qt7a525<={tu69a7f>>1,vx8bfb1[20]};ym387<={xj45a69>>1,vx8bfb1[21]};ls1c38<={jr2d34f>>1,vx8bfb1[22]};al6a3d2<=vx8bfb1[23];al70e1b<={eafa8aa>>1,vx8bfb1[24]};co870dd<=vx8bfb1[25];xl386e9<=vx8bfb1[26];gbc374e<=vx8bfb1[27];ba1ba75<=vx8bfb1[28];bldd3ab<=vx8bfb1[29];ble9d5f<=vx8bfb1[30];en4eafe<=vx8bfb1[31];icfae0d<=vx8bfb1[32];rtd7068<=vx8bfb1[33];pub8346<=vx8bfb1[34];suc1a32<=vx8bfb1[35];uxd191<=vx8bfb1[36];ic68c8c<=vx8bfb1[37];do25e9c<=vx8bfb1[38];pu2f4e2<=vx8bfb1[39];mr7a712<=vx8bfb1[40];ald3895<=vx8bfb1[41];ng9c4ad<=vx8bfb1[42];she256b<=vx8bfb1[43];gd12b5c<=vx8bfb1[44];kf95ae5<={xw52757>>1,vx8bfb1[45]};lsad72c<=vx8bfb1[46];ld6b963<=vx8bfb1[47];ic5cb1f<={kqeae99>>1,vx8bfb1[48]};yke58f8<=vx8bfb1[49];cb2c7c0<=vx8bfb1[50];ps63e05<=vx8bfb1[51];ks1f02b<=vx8bfb1[52];qtf8158<=vx8bfb1[53];byc0ac4<=vx8bfb1[54];mg5623<={jpe3998>>1,vx8bfb1[55]};sw2b118<=vx8bfb1[56];jc588c0<=vx8bfb1[57];goc4602<=vx8bfb1[58];yz23010<=vx8bfb1[59];cb18084<=vx8bfb1[60];end\r
+always@* begin ead17f6[2047]<=sgmii_mode;ead17f6[2046]<=signal_detect;ead17f6[2044]<=debug_link_timer_short;ead17f6[2040]<=force_isolate;ead17f6[2032]<=force_loopback;ead17f6[2017]<=force_unidir;ead17f6[1987]<=operational_rate[0];ead17f6[1926]<=rx_data[0];ead17f6[1805]<=vk2fa8d;ead17f6[1804]<=rx_kcntl;ead17f6[1803]<=tj3d21d;ead17f6[1761]<=hq1e17d;ead17f6[1668]<=cz51293;ead17f6[1562]<=kq7d46b;ead17f6[1560]<=rx_even;ead17f6[1558]<=eafa8aa[0];ead17f6[1550]<=tx_er;ead17f6[1475]<=qgf0bea;ead17f6[1464]<=dob3be;ead17f6[1288]<=do8949d;ead17f6[1242]<=ep331f6;ead17f6[1076]<=eaea358;ead17f6[1072]<=rx_disp_err;ead17f6[1069]<=icd4550;ead17f6[1056]<=xw52757[0];ead17f6[1052]<=mr_an_enable;ead17f6[1028]<=tjba64a;ead17f6[1023]<=gbe_mode;ead17f6[902]<=cb85f51;ead17f6[901]<=jr2d34f[0];ead17f6[880]<=go59df3;ead17f6[874]<=blc7da8;ead17f6[834]<=zkca252;ead17f6[775]<=tx_en;ead17f6[732]<=xl81677;ead17f6[621]<=vve663e;ead17f6[528]<=fn4a4ea;ead17f6[514]<=by574c9;ead17f6[450]<=xj45a69[0];ead17f6[437]<=ie98fb5;ead17f6[417]<=tu7944a;ead17f6[387]<=tx_d[0];ead17f6[366]<=bl502ce;ead17f6[310]<=rv1ccc7;ead17f6[257]<=kqeae99[0];ead17f6[225]<=tu69a7f[0];ead17f6[208]<=do2f289;ead17f6[193]<=rx_err_decode_mode;ead17f6[183]<=hdaa059;ead17f6[155]<=jpe3998[0];ead17f6[128]<=wy9d5d3;ead17f6[112]<=mr_restart_an;ead17f6[104]<=qi5e51;ead17f6[96]<=rx_cv_err;ead17f6[91]<=zma2a81;ead17f6[77]<=ukbc733;ead17f6[64]<=ls93aba;ead17f6[56]<=mr_main_reset;ead17f6[38]<=by578e6;ead17f6[19]<=pu992bc;ead17f6[9]<=end3257;end         assign jebdc77 = ead17f6,vx8bfb1 = fn71dda; initial begin kfbe35f = $fopen(".fred"); $fdisplay( kfbe35f, "%3h\n%3h", (fnf63ba >> 4) & fpbaf71, (fnf63ba >> (tj8eebd+4)) & fpbaf71 ); $fclose(kfbe35f); $readmemh(".fred", ay776be); end always @ (jebdc77) begin nedaf8d = ay776be[1]; for (jcf1afd=0; jcf1afd<th5fd8e; jcf1afd=jcf1afd+1) begin fn71dda[jcf1afd] = jebdc77[nedaf8d]; thd7c6b = ^(nedaf8d & ay776be[0]); nedaf8d = {nedaf8d, thd7c6b}; end end\r
+endmodule\r

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_core.ngo b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_core.ngo
new file mode 100644 (file)
index 0000000..108b0d4
Binary files /dev/null and b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_core.ngo differ

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_core.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_core.v
new file mode 100644 (file)
index 0000000..d26445c
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_core.v
@@ -0,0 +1,230 @@
+//**************************************************************************\r
+// *************************************************************************\r
+// *                LATTICE SEMICONDUCTOR CONFIDENTIAL                     *\r
+// *                         PROPRIETARY NOTE                              *\r
+// *                                                                       *\r
+// *  This software contains information confidential and proprietary      *\r
+// *  to Lattice Semiconductor Corporation.  It shall not be reproduced    *\r
+// *  in whole or in part, or transferred to other documents, or disclosed *\r
+// *  to third parties, or used for any purpose other than that for which  *\r
+// *  it was obtained, without the prior written consent of Lattice        *\r
+// *  Semiconductor Corporation.  All rights reserved.                     *\r
+// *                                                                       *\r
+// *************************************************************************\r
+//**************************************************************************\r
+\r
+`define SGMII_YES_SINGLE_CLOCK\r
+\r
+module sgmii_channel_smi_core (\r
+\r
+       // Control Interface\r
+       rst_n,\r
+       signal_detect,\r
+       gbe_mode,\r
+       sgmii_mode,\r
+       operational_rate,\r
+       debug_link_timer_short,\r
+       force_isolate,\r
+       force_loopback,\r
+       force_unidir,\r
+\r
+       rx_compensation_err,\r
+       ctc_drop_flag,\r
+       ctc_add_flag,\r
+       an_link_ok,\r
+\r
+       // G/MII Interface\r
+`ifdef SGMII_YES_SINGLE_CLOCK\r
+       tx_clock_enable_sink ,\r
+       tx_clock_enable_source ,\r
+\r
+       rx_clock_enable_sink ,\r
+       rx_clock_enable_source ,\r
+`else\r
+       tx_clk_mii ,\r
+       rx_clk_mii ,\r
+`endif\r
+       tx_clk_125,\r
+       tx_d,\r
+       tx_en,\r
+       tx_er,\r
+\r
+       rx_clk_125,\r
+       rx_d,\r
+       rx_dv,\r
+       rx_er,\r
+       col,\r
+       crs,\r
+\r
+       // 8-bit Interface\r
+       tx_data,\r
+       tx_kcntl,\r
+       tx_disparity_cntl,\r
+       xmit_autoneg,\r
+\r
+       serdes_recovered_clk,\r
+       rx_data,\r
+       rx_kcntl,\r
+       rx_even ,\r
+       rx_disp_err ,\r
+       rx_cv_err ,\r
+       rx_err_decode_mode ,\r
+\r
+       // Managment Control Outputs\r
+       mr_an_complete,\r
+       mr_page_rx,\r
+       mr_lp_adv_ability,\r
+\r
+       // Managment Control Inputs\r
+       mr_main_reset,\r
+       mr_an_enable,\r
+       mr_restart_an,\r
+       mr_adv_ability\r
+       );\r
+\r
+\r
+\r
+// Control Interface\r
+input         rst_n ;\r
+input         signal_detect ;\r
+input         gbe_mode ;\r
+input         sgmii_mode ;\r
+input [1:0]   operational_rate ;\r
+input         debug_link_timer_short ;\r
+input         force_isolate ;\r
+input         force_loopback ;\r
+input         force_unidir ;\r
+\r
+output        rx_compensation_err ;\r
+output        ctc_drop_flag ;\r
+output        ctc_add_flag ;\r
+output        an_link_ok ;\r
+\r
+// G/MII Interface\r
+`ifdef SGMII_YES_SINGLE_CLOCK\r
+  input       tx_clock_enable_sink;\r
+  output      tx_clock_enable_source;\r
+\r
+  input       rx_clock_enable_sink;\r
+  output      rx_clock_enable_source;\r
+`else\r
+  input       tx_clk_mii;\r
+  input       rx_clk_mii;\r
+`endif\r
+\r
+input         tx_clk_125 ;\r
+input [7:0]   tx_d ;\r
+input         tx_en ;\r
+input         tx_er ;\r
+\r
+input          rx_clk_125 ;\r
+output [7:0]   rx_d ;\r
+output         rx_dv ;\r
+output         rx_er ;\r
+output         col ;\r
+output         crs ;\r
+\r
+// 8-bit Interface\r
+output [7:0]   tx_data ;\r
+output         tx_kcntl;\r
+output         tx_disparity_cntl;\r
+output         xmit_autoneg;\r
+\r
+input         serdes_recovered_clk ;\r
+input [7:0]   rx_data  ;\r
+input         rx_even ;\r
+input         rx_kcntl;\r
+input         rx_disp_err ; // Displarity error on "rx_data".\r
+input         rx_cv_err ;   // Code error on "rx_data".\r
+input         rx_err_decode_mode ;\r
+\r
+// Managment Control Outputs\r
+output         mr_an_complete;\r
+output         mr_page_rx;\r
+output [15:0]  mr_lp_adv_ability;\r
+\r
+// Managment Control Inputs\r
+input          mr_main_reset;\r
+input          mr_an_enable;\r
+input          mr_restart_an;\r
+input [15:0]   mr_adv_ability;\r
+\r
+\r
+parameter STATIC_HI_THRESH = 32;\r
+parameter STATIC_LO_THRESH = 16;\r
+parameter LINK_TIMER_SH    = 21'h1fff01;\r
+\r
+       \r
+\r
+// SGMII PCS\r
+sgmii_pcs_gda_001 # (.STATIC_HI_THRESH(STATIC_HI_THRESH), .STATIC_LO_THRESH(STATIC_LO_THRESH), .LINK_TIMER_SH(LINK_TIMER_SH)) sgmii_pcs_gda_001 (\r
+   // Clock and Reset\r
+   .rst_n                  ( rst_n ) ,\r
+   .signal_detect          ( signal_detect ) ,\r
+   .gbe_mode               ( gbe_mode ) ,\r
+   .sgmii_mode             ( sgmii_mode ) ,\r
+   .operational_rate       ( operational_rate ) ,\r
+   .debug_link_timer_short ( debug_link_timer_short ) ,\r
+   .force_isolate          ( force_isolate ) ,\r
+   .force_loopback         ( force_loopback ) ,\r
+   .force_unidir           ( force_unidir ) ,\r
+\r
+   .rx_compensation_err    ( rx_compensation_err ) ,\r
+   .ctc_drop_flag          ( ctc_drop_flag ) ,\r
+   .ctc_add_flag           ( ctc_add_flag ) ,\r
+   .an_link_ok             ( an_link_ok ) ,\r
+\r
+`ifdef SGMII_YES_SINGLE_CLOCK\r
+   .tx_clock_enable_sink   ( tx_clock_enable_sink ),\r
+   .tx_clock_enable_source ( tx_clock_enable_source ),\r
+\r
+   .rx_clock_enable_sink   ( rx_clock_enable_sink ),\r
+   .rx_clock_enable_source ( rx_clock_enable_source ),\r
+`else\r
+   .tx_clk_mii             ( tx_clk_mii ),\r
+   .rx_clk_mii             ( rx_clk_mii ),\r
+`endif\r
+\r
+   // GMII TX Inputs\r
+   .tx_clk_125      ( tx_clk_125 ) ,\r
+   .tx_d            ( tx_d) ,\r
+   .tx_en           ( tx_en) ,\r
+   .tx_er           ( tx_er) ,\r
+\r
+   // GMII RX Outputs\r
+   // To GMII/MAC interface\r
+   .rx_clk_125      ( rx_clk_125 ) ,\r
+   .rx_d            ( rx_d ) ,\r
+   .rx_dv           ( rx_dv ) ,\r
+   .rx_er           ( rx_er ) ,\r
+   .col             ( col ) ,\r
+   .crs             ( crs ) ,\r
+                  \r
+   // 8BI TX Outputs\r
+   .tx_data           ( tx_data) ,\r
+   .tx_kcntl          ( tx_kcntl) ,\r
+   .tx_disparity_cntl ( tx_disparity_cntl) ,\r
+   .xmit_autoneg      ( xmit_autoneg) ,\r
+\r
+   // 8BI RX Inputs\r
+   .serdes_recovered_clk ( serdes_recovered_clk ) ,\r
+   .rx_data              ( rx_data ) ,\r
+   .rx_kcntl             ( rx_kcntl ) ,\r
+   .rx_even              ( rx_even ) ,\r
+   .rx_disp_err          ( rx_disp_err ) ,\r
+   .rx_cv_err            ( rx_cv_err ) ,\r
+   .rx_err_decode_mode   ( rx_err_decode_mode ) ,\r
+\r
+   // Management Interface  I/O\r
+   .mr_adv_ability    (mr_adv_ability),\r
+   .mr_an_enable      (mr_an_enable), \r
+   .mr_main_reset     (mr_main_reset),  \r
+   .mr_restart_an     (mr_restart_an),   \r
+\r
+   .mr_an_complete    (mr_an_complete),   \r
+   .mr_lp_adv_ability (mr_lp_adv_ability), \r
+   .mr_page_rx        (mr_page_rx)\r
+   );\r
+\r
+\r
+endmodule\r

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_core_bb.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_core_bb.v
new file mode 100644 (file)
index 0000000..553fb71
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_core_bb.v
@@ -0,0 +1,152 @@
+//**************************************************************************\r
+// *************************************************************************\r
+// *                LATTICE SEMICONDUCTOR CONFIDENTIAL                     *\r
+// *                         PROPRIETARY NOTE                              *\r
+// *                                                                       *\r
+// *  This software contains information confidential and proprietary      *\r
+// *  to Lattice Semiconductor Corporation.  It shall not be reproduced    *\r
+// *  in whole or in part, or transferred to other documents, or disclosed *\r
+// *  to third parties, or used for any purpose other than that for which  *\r
+// *  it was obtained, without the prior written consent of Lattice        *\r
+// *  Semiconductor Corporation.  All rights reserved.                     *\r
+// *                                                                       *\r
+// *************************************************************************\r
+//**************************************************************************\r
+\r
+`define SGMII_YES_SINGLE_CLOCK\r
+\r
+module sgmii_channel_smi_core (\r
+\r
+       // Control Interface\r
+       rst_n,\r
+       signal_detect,\r
+       gbe_mode,\r
+       sgmii_mode,\r
+       operational_rate,\r
+       debug_link_timer_short,\r
+       force_isolate,\r
+       force_loopback,\r
+       force_unidir,\r
+\r
+       rx_compensation_err,\r
+       ctc_drop_flag,\r
+       ctc_add_flag,\r
+       an_link_ok,\r
+\r
+       // G/MII Interface\r
+`ifdef SGMII_YES_SINGLE_CLOCK\r
+       tx_clock_enable_sink ,\r
+       tx_clock_enable_source ,\r
+\r
+       rx_clock_enable_sink ,\r
+       rx_clock_enable_source ,\r
+`else\r
+       tx_clk_mii ,\r
+       rx_clk_mii ,\r
+`endif\r
+       tx_clk_125,\r
+       tx_d,\r
+       tx_en,\r
+       tx_er,\r
+\r
+       rx_clk_125,\r
+       rx_d,\r
+       rx_dv,\r
+       rx_er,\r
+       col,\r
+       crs,\r
+\r
+       // 8-bit Interface\r
+       tx_data,\r
+       tx_kcntl,\r
+       tx_disparity_cntl,\r
+       xmit_autoneg,\r
+\r
+       serdes_recovered_clk,\r
+       rx_data,\r
+       rx_kcntl,\r
+       rx_even ,\r
+       rx_disp_err ,\r
+       rx_cv_err ,\r
+       rx_err_decode_mode ,\r
+\r
+       // Managment Control Outputs\r
+       mr_an_complete,\r
+       mr_page_rx,\r
+       mr_lp_adv_ability,\r
+\r
+       // Managment Control Inputs\r
+       mr_main_reset,\r
+       mr_an_enable,\r
+       mr_restart_an,\r
+       mr_adv_ability\r
+       );\r
+\r
+\r
+\r
+// Control Interface\r
+input         rst_n ;\r
+input         signal_detect ;\r
+input         gbe_mode ;\r
+input         sgmii_mode ;\r
+input [1:0]   operational_rate ;\r
+input         debug_link_timer_short ;\r
+input         force_isolate ;\r
+input         force_loopback ;\r
+input         force_unidir ;\r
+\r
+output        rx_compensation_err ;\r
+output        ctc_drop_flag ;\r
+output        ctc_add_flag ;\r
+output        an_link_ok ;\r
+\r
+// G/MII Interface\r
+`ifdef SGMII_YES_SINGLE_CLOCK\r
+  input       tx_clock_enable_sink;\r
+  output      tx_clock_enable_source;\r
+\r
+  input       rx_clock_enable_sink;\r
+  output      rx_clock_enable_source;\r
+`else\r
+  input       tx_clk_mii;\r
+  input       rx_clk_mii;\r
+`endif\r
+\r
+input         tx_clk_125 ;\r
+input [7:0]   tx_d ;\r
+input         tx_en ;\r
+input         tx_er ;\r
+\r
+input          rx_clk_125 ;\r
+output [7:0]   rx_d ;\r
+output         rx_dv ;\r
+output         rx_er ;\r
+output         col ;\r
+output         crs ;\r
+\r
+// 8-bit Interface\r
+output [7:0]   tx_data ;\r
+output         tx_kcntl;\r
+output         tx_disparity_cntl;\r
+output         xmit_autoneg;\r
+\r
+input         serdes_recovered_clk ;\r
+input [7:0]   rx_data  ;\r
+input         rx_even ;\r
+input         rx_kcntl;\r
+input         rx_disp_err ; // Displarity error on "rx_data".\r
+input         rx_cv_err ;   // Code error on "rx_data".\r
+input         rx_err_decode_mode ;\r
+\r
+// Managment Control Outputs\r
+output         mr_an_complete;\r
+output         mr_page_rx;\r
+output [15:0]  mr_lp_adv_ability;\r
+\r
+// Managment Control Inputs\r
+input          mr_main_reset;\r
+input          mr_an_enable;\r
+input          mr_restart_an;\r
+input [15:0]   mr_adv_ability;\r
+\r
+endmodule\r

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_ngd.asd b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_ngd.asd
new file mode 100644 (file)
index 0000000..02edbf1
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_ngd.asd
@@ -0,0 +1,2 @@
+[ActiveSupport NGD]
+IP_1 = LSC_IP_SC_HT_SGMII

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_pcs.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_pcs.v
new file mode 100644 (file)
index 0000000..32eab38
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_pcs.v
@@ -0,0 +1,476 @@
+// Verilog netlist produced by program ASBGen: Ports rev. 2.30, Attr. rev. 2.70
+// Netlist written on Tue Apr 30 12:09:53 2019
+//
+// Verilog Description of module sgmii_channel_smi_pcs
+//
+
+`timescale 1ns/1ps
+module sgmii_channel_smi_pcs (hdoutp, hdoutn, hdinp, 
+            hdinn, rxrefclk, rx_pclk, txi_clk, tx_pclk, txdata, 
+            tx_k, xmit, tx_disp_correct, rxdata, rx_k, rx_disp_err, 
+            rx_cv_err, signal_detect_c, lsm_status_s, rx_cdr_lol_s, 
+            sli_rst, tx_pwrup_c, rx_pwrup_c, sci_wrdata, sci_addr, 
+            sci_rddata, sci_en_dual, sci_sel_dual, sci_en, sci_sel, 
+            sci_rd, sci_wrn, sci_int, cyawstn, serdes_pdb, pll_refclki, 
+            rsl_disable, rsl_rst, serdes_rst_dual_c, rst_dual_c, tx_serdes_rst_c, 
+            tx_pcs_rst_c, pll_lol, rx_serdes_rst_c, rx_pcs_rst_c);
+    output hdoutp;
+    output hdoutn;
+    input hdinp;
+    input hdinn;
+    input rxrefclk;
+    output rx_pclk;
+    input txi_clk;
+    output tx_pclk;
+    input [7:0]txdata;
+    input [0:0]tx_k;
+    input [0:0]xmit;
+    input [0:0]tx_disp_correct;
+    output [7:0]rxdata;
+    output [0:0]rx_k;
+    output [0:0]rx_disp_err;
+    output [0:0]rx_cv_err;
+    input signal_detect_c;
+    output lsm_status_s;
+    output rx_cdr_lol_s;
+    input sli_rst;
+    input tx_pwrup_c;
+    input rx_pwrup_c;
+    input [7:0]sci_wrdata;
+    input [5:0]sci_addr;
+    output [7:0]sci_rddata;
+    input sci_en_dual;
+    input sci_sel_dual;
+    input sci_en;
+    input sci_sel;
+    input sci_rd;
+    input sci_wrn;
+    output sci_int;
+    input cyawstn;
+    input serdes_pdb;
+    input pll_refclki;
+    input rsl_disable;
+    input rsl_rst;
+    input serdes_rst_dual_c;
+    input rst_dual_c;
+    input tx_serdes_rst_c;
+    input tx_pcs_rst_c;
+    output pll_lol;
+    input rx_serdes_rst_c;
+    input rx_pcs_rst_c;
+    
+    
+    wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, 
+        n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, 
+        n22, n23, n24, n25, n26, n27, n28, n29, rsl_tx_pcs_rst_c, 
+        rsl_rx_pcs_rst_c, rsl_rx_serdes_rst_c, rsl_rst_dual_c, rsl_serdes_rst_dual_c, 
+        rsl_tx_serdes_rst_c, n30, n31, n32, n33, n34, n35, n36, 
+        n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, 
+        n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, 
+        n57, n60, n61, n62, n63, n64, n65, n66, n67, n68, 
+        n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, 
+        n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, 
+        n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, 
+        n99, n100, n101, n102, n103, n104, n105, n116, n117, 
+        n118, n119, n120, n121, n122, n123, n124, n125, n126, 
+        _Z;
+    
+    DCUA DCU0_inst (.CH0_HDINP(hdinp), .CH1_HDINP(1'b0), .CH0_HDINN(hdinn), 
+         .CH1_HDINN(1'b0), .D_TXBIT_CLKP_FROM_ND(1'b0), .D_TXBIT_CLKN_FROM_ND(1'b0), 
+         .D_SYNC_ND(1'b0), .D_TXPLL_LOL_FROM_ND(1'b0), .CH0_RX_REFCLK(rxrefclk), 
+         .CH1_RX_REFCLK(1'b0), .CH0_FF_RXI_CLK(rx_pclk), .CH1_FF_RXI_CLK(1'b1), 
+         .CH0_FF_TXI_CLK(txi_clk), .CH1_FF_TXI_CLK(1'b1), .CH0_FF_EBRD_CLK(1'b1), 
+         .CH1_FF_EBRD_CLK(1'b1), .CH0_FF_TX_D_0(txdata[0]), .CH1_FF_TX_D_0(1'b0), 
+         .CH0_FF_TX_D_1(txdata[1]), .CH1_FF_TX_D_1(1'b0), .CH0_FF_TX_D_2(txdata[2]), 
+         .CH1_FF_TX_D_2(1'b0), .CH0_FF_TX_D_3(txdata[3]), .CH1_FF_TX_D_3(1'b0), 
+         .CH0_FF_TX_D_4(txdata[4]), .CH1_FF_TX_D_4(1'b0), .CH0_FF_TX_D_5(txdata[5]), 
+         .CH1_FF_TX_D_5(1'b0), .CH0_FF_TX_D_6(txdata[6]), .CH1_FF_TX_D_6(1'b0), 
+         .CH0_FF_TX_D_7(txdata[7]), .CH1_FF_TX_D_7(1'b0), .CH0_FF_TX_D_8(tx_k[0]), 
+         .CH1_FF_TX_D_8(1'b0), .CH0_FF_TX_D_9(1'b0), .CH1_FF_TX_D_9(1'b0), 
+         .CH0_FF_TX_D_10(xmit[0]), .CH1_FF_TX_D_10(1'b0), .CH0_FF_TX_D_11(tx_disp_correct[0]), 
+         .CH1_FF_TX_D_11(1'b0), .CH0_FF_TX_D_12(1'b0), .CH1_FF_TX_D_12(1'b0), 
+         .CH0_FF_TX_D_13(1'b0), .CH1_FF_TX_D_13(1'b0), .CH0_FF_TX_D_14(1'b0), 
+         .CH1_FF_TX_D_14(1'b0), .CH0_FF_TX_D_15(1'b0), .CH1_FF_TX_D_15(1'b0), 
+         .CH0_FF_TX_D_16(1'b0), .CH1_FF_TX_D_16(1'b0), .CH0_FF_TX_D_17(1'b0), 
+         .CH1_FF_TX_D_17(1'b0), .CH0_FF_TX_D_18(1'b0), .CH1_FF_TX_D_18(1'b0), 
+         .CH0_FF_TX_D_19(1'b0), .CH1_FF_TX_D_19(1'b0), .CH0_FF_TX_D_20(1'b0), 
+         .CH1_FF_TX_D_20(1'b0), .CH0_FF_TX_D_21(1'b0), .CH1_FF_TX_D_21(1'b0), 
+         .CH0_FF_TX_D_22(1'b0), .CH1_FF_TX_D_22(1'b0), .CH0_FF_TX_D_23(1'b0), 
+         .CH1_FF_TX_D_23(1'b0), .CH0_FFC_EI_EN(1'b0), .CH1_FFC_EI_EN(1'b0), 
+         .CH0_FFC_PCIE_DET_EN(1'b0), .CH1_FFC_PCIE_DET_EN(1'b0), .CH0_FFC_PCIE_CT(1'b0), 
+         .CH1_FFC_PCIE_CT(1'b0), .CH0_FFC_SB_INV_RX(1'b0), .CH1_FFC_SB_INV_RX(1'b0), 
+         .CH0_FFC_ENABLE_CGALIGN(1'b0), .CH1_FFC_ENABLE_CGALIGN(1'b0), .CH0_FFC_SIGNAL_DETECT(signal_detect_c), 
+         .CH1_FFC_SIGNAL_DETECT(1'b0), .CH0_FFC_FB_LOOPBACK(1'b0), .CH1_FFC_FB_LOOPBACK(1'b0), 
+         .CH0_FFC_SB_PFIFO_LP(1'b0), .CH1_FFC_SB_PFIFO_LP(1'b0), .CH0_FFC_PFIFO_CLR(1'b0), 
+         .CH1_FFC_PFIFO_CLR(1'b0), .CH0_FFC_RATE_MODE_RX(1'b0), .CH1_FFC_RATE_MODE_RX(1'b0), 
+         .CH0_FFC_RATE_MODE_TX(1'b0), .CH1_FFC_RATE_MODE_TX(1'b0), .CH0_FFC_DIV11_MODE_RX(1'b0), 
+         .CH1_FFC_DIV11_MODE_RX(1'b0), .CH0_FFC_DIV11_MODE_TX(1'b0), .CH1_FFC_DIV11_MODE_TX(1'b0), 
+         .CH0_FFC_RX_GEAR_MODE(1'b0), .CH1_FFC_RX_GEAR_MODE(1'b0), .CH0_FFC_TX_GEAR_MODE(1'b0), 
+         .CH1_FFC_TX_GEAR_MODE(1'b0), .CH0_FFC_LDR_CORE2TX_EN(1'b0), .CH1_FFC_LDR_CORE2TX_EN(1'b0), 
+         .CH0_FFC_LANE_TX_RST(rsl_tx_pcs_rst_c), .CH1_FFC_LANE_TX_RST(1'b0), 
+         .CH0_FFC_LANE_RX_RST(rsl_rx_pcs_rst_c), .CH1_FFC_LANE_RX_RST(1'b0), 
+         .CH0_FFC_RRST(rsl_rx_serdes_rst_c), .CH1_FFC_RRST(1'b0), .CH0_FFC_TXPWDNB(tx_pwrup_c), 
+         .CH1_FFC_TXPWDNB(1'b0), .CH0_FFC_RXPWDNB(rx_pwrup_c), .CH1_FFC_RXPWDNB(1'b0), 
+         .CH0_LDR_CORE2TX(1'b0), .CH1_LDR_CORE2TX(1'b0), .D_SCIWDATA0(sci_wrdata[0]), 
+         .D_SCIWDATA1(sci_wrdata[1]), .D_SCIWDATA2(sci_wrdata[2]), .D_SCIWDATA3(sci_wrdata[3]), 
+         .D_SCIWDATA4(sci_wrdata[4]), .D_SCIWDATA5(sci_wrdata[5]), .D_SCIWDATA6(sci_wrdata[6]), 
+         .D_SCIWDATA7(sci_wrdata[7]), .D_SCIADDR0(sci_addr[0]), .D_SCIADDR1(sci_addr[1]), 
+         .D_SCIADDR2(sci_addr[2]), .D_SCIADDR3(sci_addr[3]), .D_SCIADDR4(sci_addr[4]), 
+         .D_SCIADDR5(sci_addr[5]), .D_SCIENAUX(sci_en_dual), .D_SCISELAUX(sci_sel_dual), 
+         .CH0_SCIEN(sci_en), .CH1_SCIEN(1'b0), .CH0_SCISEL(sci_sel), .CH1_SCISEL(1'b0), 
+         .D_SCIRD(sci_rd), .D_SCIWSTN(sci_wrn), .D_CYAWSTN(cyawstn), .D_FFC_SYNC_TOGGLE(1'b0), 
+         .D_FFC_DUAL_RST(rsl_rst_dual_c), .D_FFC_MACRO_RST(rsl_serdes_rst_dual_c), 
+         .D_FFC_MACROPDB(serdes_pdb), .D_FFC_TRST(rsl_tx_serdes_rst_c), 
+         .CH0_FFC_CDR_EN_BITSLIP(1'b0), .CH1_FFC_CDR_EN_BITSLIP(1'b0), .D_SCAN_ENABLE(1'b0), 
+         .D_SCAN_IN_0(1'b0), .D_SCAN_IN_1(1'b0), .D_SCAN_IN_2(1'b0), .D_SCAN_IN_3(1'b0), 
+         .D_SCAN_IN_4(1'b0), .D_SCAN_IN_5(1'b0), .D_SCAN_IN_6(1'b0), .D_SCAN_IN_7(1'b0), 
+         .D_SCAN_MODE(1'b0), .D_SCAN_RESET(1'b0), .D_CIN0(1'b0), .D_CIN1(1'b0), 
+         .D_CIN2(1'b0), .D_CIN3(1'b0), .D_CIN4(1'b0), .D_CIN5(1'b0), 
+         .D_CIN6(1'b0), .D_CIN7(1'b0), .D_CIN8(1'b0), .D_CIN9(1'b0), 
+         .D_CIN10(1'b0), .D_CIN11(1'b0), .CH0_HDOUTP(hdoutp), .CH1_HDOUTP(n61), 
+         .CH0_HDOUTN(hdoutn), .CH1_HDOUTN(n62), .D_TXBIT_CLKP_TO_ND(n1), 
+         .D_TXBIT_CLKN_TO_ND(n2), .D_SYNC_PULSE2ND(n3), .D_TXPLL_LOL_TO_ND(n4), 
+         .CH0_FF_RX_F_CLK(n5), .CH1_FF_RX_F_CLK(n63), .CH0_FF_RX_H_CLK(n6), 
+         .CH1_FF_RX_H_CLK(n64), .CH0_FF_TX_F_CLK(n7), .CH1_FF_TX_F_CLK(n65), 
+         .CH0_FF_TX_H_CLK(n8), .CH1_FF_TX_H_CLK(n66), .CH0_FF_RX_PCLK(rx_pclk), 
+         .CH1_FF_RX_PCLK(n67), .CH0_FF_TX_PCLK(tx_pclk), .CH1_FF_TX_PCLK(n68), 
+         .CH0_FF_RX_D_0(rxdata[0]), .CH1_FF_RX_D_0(n69), .CH0_FF_RX_D_1(rxdata[1]), 
+         .CH1_FF_RX_D_1(n70), .CH0_FF_RX_D_2(rxdata[2]), .CH1_FF_RX_D_2(n71), 
+         .CH0_FF_RX_D_3(rxdata[3]), .CH1_FF_RX_D_3(n72), .CH0_FF_RX_D_4(rxdata[4]), 
+         .CH1_FF_RX_D_4(n73), .CH0_FF_RX_D_5(rxdata[5]), .CH1_FF_RX_D_5(n74), 
+         .CH0_FF_RX_D_6(rxdata[6]), .CH1_FF_RX_D_6(n75), .CH0_FF_RX_D_7(rxdata[7]), 
+         .CH1_FF_RX_D_7(n76), .CH0_FF_RX_D_8(rx_k[0]), .CH1_FF_RX_D_8(n77), 
+         .CH0_FF_RX_D_9(rx_disp_err[0]), .CH1_FF_RX_D_9(n78), .CH0_FF_RX_D_10(rx_cv_err[0]), 
+         .CH1_FF_RX_D_10(n79), .CH0_FF_RX_D_11(n9), .CH1_FF_RX_D_11(n80), 
+         .CH0_FF_RX_D_12(n10), .CH1_FF_RX_D_12(n81), .CH0_FF_RX_D_13(n11), 
+         .CH1_FF_RX_D_13(n82), .CH0_FF_RX_D_14(n12), .CH1_FF_RX_D_14(n83), 
+         .CH0_FF_RX_D_15(n13), .CH1_FF_RX_D_15(n84), .CH0_FF_RX_D_16(n14), 
+         .CH1_FF_RX_D_16(n85), .CH0_FF_RX_D_17(n15), .CH1_FF_RX_D_17(n86), 
+         .CH0_FF_RX_D_18(n16), .CH1_FF_RX_D_18(n87), .CH0_FF_RX_D_19(n17), 
+         .CH1_FF_RX_D_19(n88), .CH0_FF_RX_D_20(n18), .CH1_FF_RX_D_20(n89), 
+         .CH0_FF_RX_D_21(n19), .CH1_FF_RX_D_21(n90), .CH0_FF_RX_D_22(n20), 
+         .CH1_FF_RX_D_22(n91), .CH0_FF_RX_D_23(n21), .CH1_FF_RX_D_23(n92), 
+         .CH0_FFS_PCIE_DONE(n22), .CH1_FFS_PCIE_DONE(n93), .CH0_FFS_PCIE_CON(n23), 
+         .CH1_FFS_PCIE_CON(n94), .CH0_FFS_RLOS(n95), .CH1_FFS_RLOS(n96), 
+         .CH0_FFS_LS_SYNC_STATUS(lsm_status_s), .CH1_FFS_LS_SYNC_STATUS(n97), 
+         .CH0_FFS_CC_UNDERRUN(n24), .CH1_FFS_CC_UNDERRUN(n98), .CH0_FFS_CC_OVERRUN(n25), 
+         .CH1_FFS_CC_OVERRUN(n99), .CH0_FFS_RXFBFIFO_ERROR(n26), .CH1_FFS_RXFBFIFO_ERROR(n100), 
+         .CH0_FFS_TXFBFIFO_ERROR(n27), .CH1_FFS_TXFBFIFO_ERROR(n101), .CH0_FFS_RLOL(rx_cdr_lol_s), 
+         .CH1_FFS_RLOL(n102), .CH0_FFS_SKP_ADDED(n28), .CH1_FFS_SKP_ADDED(n103), 
+         .CH0_FFS_SKP_DELETED(n29), .CH1_FFS_SKP_DELETED(n104), .CH0_LDR_RX2CORE(n105), 
+         .CH1_LDR_RX2CORE(n116), .D_SCIRDATA0(sci_rddata[0]), .D_SCIRDATA1(sci_rddata[1]), 
+         .D_SCIRDATA2(sci_rddata[2]), .D_SCIRDATA3(sci_rddata[3]), .D_SCIRDATA4(sci_rddata[4]), 
+         .D_SCIRDATA5(sci_rddata[5]), .D_SCIRDATA6(sci_rddata[6]), .D_SCIRDATA7(sci_rddata[7]), 
+         .D_SCIINT(sci_int), .D_SCAN_OUT_0(n30), .D_SCAN_OUT_1(n31), .D_SCAN_OUT_2(n32), 
+         .D_SCAN_OUT_3(n33), .D_SCAN_OUT_4(n34), .D_SCAN_OUT_5(n35), .D_SCAN_OUT_6(n36), 
+         .D_SCAN_OUT_7(n37), .D_COUT0(n38), .D_COUT1(n39), .D_COUT2(n40), 
+         .D_COUT3(n41), .D_COUT4(n42), .D_COUT5(n43), .D_COUT6(n44), 
+         .D_COUT7(n45), .D_COUT8(n46), .D_COUT9(n47), .D_COUT10(n48), 
+         .D_COUT11(n49), .D_COUT12(n50), .D_COUT13(n51), .D_COUT14(n52), 
+         .D_COUT15(n53), .D_COUT16(n54), .D_COUT17(n55), .D_COUT18(n56), 
+         .D_COUT19(n57), .D_REFCLKI(pll_refclki), .D_FFS_PLOL(n60)) /* synthesis LOC=DCU0 CHAN=CH0 */ ;
+    defparam DCU0_inst.D_MACROPDB = "0b1";
+    defparam DCU0_inst.D_IB_PWDNB = "0b1";
+    defparam DCU0_inst.D_XGE_MODE = "0b0";
+    defparam DCU0_inst.D_LOW_MARK = "0d4";
+    defparam DCU0_inst.D_HIGH_MARK = "0d12";
+    defparam DCU0_inst.D_BUS8BIT_SEL = "0b0";
+    defparam DCU0_inst.D_CDR_LOL_SET = "0b00";
+    defparam DCU0_inst.D_TXPLL_PWDNB = "0b1";
+    defparam DCU0_inst.D_BITCLK_LOCAL_EN = "0b1";
+    defparam DCU0_inst.D_BITCLK_ND_EN = "0b0";
+    defparam DCU0_inst.D_BITCLK_FROM_ND_EN = "0b0";
+    defparam DCU0_inst.D_SYNC_LOCAL_EN = "0b1";
+    defparam DCU0_inst.D_SYNC_ND_EN = "0b0";
+    defparam DCU0_inst.CH0_UC_MODE = "0b0";
+    defparam DCU0_inst.CH0_PCIE_MODE = "0b0";
+    defparam DCU0_inst.CH0_RIO_MODE = "0b0";
+    defparam DCU0_inst.CH0_WA_MODE = "0b0";
+    defparam DCU0_inst.CH0_INVERT_RX = "0b0";
+    defparam DCU0_inst.CH0_INVERT_TX = "0b0";
+    defparam DCU0_inst.CH0_PRBS_SELECTION = "0b0";
+    defparam DCU0_inst.CH0_GE_AN_ENABLE = "0b1";
+    defparam DCU0_inst.CH0_PRBS_LOCK = "0b0";
+    defparam DCU0_inst.CH0_PRBS_ENABLE = "0b0";
+    defparam DCU0_inst.CH0_ENABLE_CG_ALIGN = "0b1";
+    defparam DCU0_inst.CH0_TX_GEAR_MODE = "0b0";
+    defparam DCU0_inst.CH0_RX_GEAR_MODE = "0b0";
+    defparam DCU0_inst.CH0_PCS_DET_TIME_SEL = "0b00";
+    defparam DCU0_inst.CH0_PCIE_EI_EN = "0b0";
+    defparam DCU0_inst.CH0_TX_GEAR_BYPASS = "0b0";
+    defparam DCU0_inst.CH0_ENC_BYPASS = "0b0";
+    defparam DCU0_inst.CH0_SB_BYPASS = "0b0";
+    defparam DCU0_inst.CH0_RX_SB_BYPASS = "0b0";
+    defparam DCU0_inst.CH0_WA_BYPASS = "0b0";
+    defparam DCU0_inst.CH0_DEC_BYPASS = "0b0";
+    defparam DCU0_inst.CH0_CTC_BYPASS = "0b1";
+    defparam DCU0_inst.CH0_RX_GEAR_BYPASS = "0b0";
+    defparam DCU0_inst.CH0_LSM_DISABLE = "0b0";
+    defparam DCU0_inst.CH0_MATCH_2_ENABLE = "0b0";
+    defparam DCU0_inst.CH0_MATCH_4_ENABLE = "0b0";
+    defparam DCU0_inst.CH0_MIN_IPG_CNT = "0b11";
+    defparam DCU0_inst.CH0_CC_MATCH_1 = "0x000";
+    defparam DCU0_inst.CH0_CC_MATCH_2 = "0x000";
+    defparam DCU0_inst.CH0_CC_MATCH_3 = "0x000";
+    defparam DCU0_inst.CH0_CC_MATCH_4 = "0x000";
+    defparam DCU0_inst.CH0_UDF_COMMA_MASK = "0x3ff";
+    defparam DCU0_inst.CH0_UDF_COMMA_A = "0x283";
+    defparam DCU0_inst.CH0_UDF_COMMA_B = "0x17C";
+    defparam DCU0_inst.CH0_RX_DCO_CK_DIV = "0b000";
+    defparam DCU0_inst.CH0_RCV_DCC_EN = "0b0";
+    defparam DCU0_inst.CH0_TPWDNB = "0b1";
+    defparam DCU0_inst.CH0_RATE_MODE_TX = "0b1";
+    defparam DCU0_inst.CH0_RTERM_TX = "0d19";
+    defparam DCU0_inst.CH0_TX_CM_SEL = "0b00";
+    defparam DCU0_inst.CH0_TDRV_PRE_EN = "0b0";
+    defparam DCU0_inst.CH0_TDRV_SLICE0_SEL = "0b01";
+    defparam DCU0_inst.CH0_TDRV_SLICE1_SEL = "0b00";
+    defparam DCU0_inst.CH0_TDRV_SLICE2_SEL = "0b01";
+    defparam DCU0_inst.CH0_TDRV_SLICE3_SEL = "0b01";
+    defparam DCU0_inst.CH0_TDRV_SLICE4_SEL = "0b01";
+    defparam DCU0_inst.CH0_TDRV_SLICE5_SEL = "0b00";
+    defparam DCU0_inst.CH0_TDRV_SLICE0_CUR = "0b011";
+    defparam DCU0_inst.CH0_TDRV_SLICE1_CUR = "0b000";
+    defparam DCU0_inst.CH0_TDRV_SLICE2_CUR = "0b11";
+    defparam DCU0_inst.CH0_TDRV_SLICE3_CUR = "0b11";
+    defparam DCU0_inst.CH0_TDRV_SLICE4_CUR = "0b11";
+    defparam DCU0_inst.CH0_TDRV_SLICE5_CUR = "0b00";
+    defparam DCU0_inst.CH0_TDRV_DAT_SEL = "0b00";
+    defparam DCU0_inst.CH0_TX_DIV11_SEL = "0b0";
+    defparam DCU0_inst.CH0_RPWDNB = "0b1";
+    defparam DCU0_inst.CH0_RATE_MODE_RX = "0b1";
+    defparam DCU0_inst.CH0_RX_DIV11_SEL = "0b0";
+    defparam DCU0_inst.CH0_SEL_SD_RX_CLK = "0b1";
+    defparam DCU0_inst.CH0_FF_RX_H_CLK_EN = "0b0";
+    defparam DCU0_inst.CH0_FF_RX_F_CLK_DIS = "0b0";
+    defparam DCU0_inst.CH0_FF_TX_H_CLK_EN = "0b0";
+    defparam DCU0_inst.CH0_FF_TX_F_CLK_DIS = "0b0";
+    defparam DCU0_inst.CH0_TDRV_POST_EN = "0b0";
+    defparam DCU0_inst.CH0_TX_POST_SIGN = "0b0";
+    defparam DCU0_inst.CH0_TX_PRE_SIGN = "0b0";
+    defparam DCU0_inst.CH0_REQ_LVL_SET = "0b01";
+    defparam DCU0_inst.CH0_REQ_EN = "0b1";
+    defparam DCU0_inst.CH0_RTERM_RX = "0d22";
+    defparam DCU0_inst.CH0_RXTERM_CM = "0b11";
+    defparam DCU0_inst.CH0_PDEN_SEL = "0b1";
+    defparam DCU0_inst.CH0_RXIN_CM = "0b11";
+    defparam DCU0_inst.CH0_LEQ_OFFSET_SEL = "0b0";
+    defparam DCU0_inst.CH0_LEQ_OFFSET_TRIM = "0b000";
+    defparam DCU0_inst.CH0_RLOS_SEL = "0b1";
+    defparam DCU0_inst.CH0_RX_LOS_LVL = "0b010";
+    defparam DCU0_inst.CH0_RX_LOS_CEQ = "0b11";
+    defparam DCU0_inst.CH0_RX_LOS_HYST_EN = "0b0";
+    defparam DCU0_inst.CH0_RX_LOS_EN = "0b0";
+    defparam DCU0_inst.CH0_LDR_RX2CORE_SEL = "0b0";
+    defparam DCU0_inst.CH0_LDR_CORE2TX_SEL = "0b0";
+    defparam DCU0_inst.D_TX_MAX_RATE = "2.5";
+    defparam DCU0_inst.CH0_CDR_MAX_RATE = "2.5";
+    defparam DCU0_inst.CH0_TXAMPLITUDE = "0d6";
+    defparam DCU0_inst.CH0_TXDEPRE = "DISABLED";
+    defparam DCU0_inst.CH0_TXDEPOST = "DISABLED";
+    defparam DCU0_inst.CH0_PROTOCOL = "SGMII";
+    defparam DCU0_inst.D_ISETLOS = "0d0";
+    defparam DCU0_inst.D_SETIRPOLY_AUX = "0b00";
+    defparam DCU0_inst.D_SETICONST_AUX = "0b00";
+    defparam DCU0_inst.D_SETIRPOLY_CH = "0b00";
+    defparam DCU0_inst.D_SETICONST_CH = "0b00";
+    defparam DCU0_inst.D_REQ_ISET = "0b000";
+    defparam DCU0_inst.D_PD_ISET = "0b00";
+    defparam DCU0_inst.D_DCO_CALIB_TIME_SEL = "0b00";
+    defparam DCU0_inst.CH0_CDR_CNT4SEL = "0b00";
+    defparam DCU0_inst.CH0_CDR_CNT8SEL = "0b00";
+    defparam DCU0_inst.CH0_DCOATDCFG = "0b00";
+    defparam DCU0_inst.CH0_DCOATDDLY = "0b00";
+    defparam DCU0_inst.CH0_DCOBYPSATD = "0b1";
+    defparam DCU0_inst.CH0_DCOCALDIV = "0b001";
+    defparam DCU0_inst.CH0_DCOCTLGI = "0b010";
+    defparam DCU0_inst.CH0_DCODISBDAVOID = "0b0";
+    defparam DCU0_inst.CH0_DCOFLTDAC = "0b01";
+    defparam DCU0_inst.CH0_DCOFTNRG = "0b110";
+    defparam DCU0_inst.CH0_DCOIOSTUNE = "0b000";
+    defparam DCU0_inst.CH0_DCOITUNE = "0b00";
+    defparam DCU0_inst.CH0_DCOITUNE4LSB = "0b111";
+    defparam DCU0_inst.CH0_DCOIUPDNX2 = "0b1";
+    defparam DCU0_inst.CH0_DCONUOFLSB = "0b101";
+    defparam DCU0_inst.CH0_DCOSCALEI = "0b00";
+    defparam DCU0_inst.CH0_DCOSTARTVAL = "0b000";
+    defparam DCU0_inst.CH0_DCOSTEP = "0b00";
+    defparam DCU0_inst.CH0_BAND_THRESHOLD = "0d0";
+    defparam DCU0_inst.CH0_AUTO_FACQ_EN = "0b1";
+    defparam DCU0_inst.CH0_AUTO_CALIB_EN = "0b1";
+    defparam DCU0_inst.CH0_CALIB_CK_MODE = "0b0";
+    defparam DCU0_inst.CH0_REG_BAND_OFFSET = "0d0";
+    defparam DCU0_inst.CH0_REG_BAND_SEL = "0d0";
+    defparam DCU0_inst.CH0_REG_IDAC_SEL = "0d0";
+    defparam DCU0_inst.CH0_REG_IDAC_EN = "0b0";
+    defparam DCU0_inst.D_CMUSETISCL4VCO = "0b000";
+    defparam DCU0_inst.D_CMUSETI4VCO = "0b00";
+    defparam DCU0_inst.D_CMUSETINITVCT = "0b00";
+    defparam DCU0_inst.D_CMUSETZGM = "0b000";
+    defparam DCU0_inst.D_CMUSETP2AGM = "0b000";
+    defparam DCU0_inst.D_CMUSETP1GM = "0b000";
+    defparam DCU0_inst.D_CMUSETI4CPZ = "0d3";
+    defparam DCU0_inst.D_CMUSETI4CPP = "0d3";
+    defparam DCU0_inst.D_CMUSETICP4Z = "0b101";
+    defparam DCU0_inst.D_CMUSETICP4P = "0b01";
+    defparam DCU0_inst.D_CMUSETBIASI = "0b00";
+    defparam DCU0_inst.D_SETPLLRC = "0d1";
+    defparam DCU0_inst.CH0_RX_RATE_SEL = "0d8";
+    defparam DCU0_inst.D_REFCK_MODE = "0b000";
+    defparam DCU0_inst.D_TX_VCO_CK_DIV = "0b000";
+    defparam DCU0_inst.D_PLL_LOL_SET = "0b00";
+    defparam DCU0_inst.D_RG_EN = "0b0";
+    defparam DCU0_inst.D_RG_SET = "0b00";
+    assign n1 = 1'bz;
+    assign n2 = 1'bz;
+    assign n3 = 1'bz;
+    assign n4 = 1'bz;
+    assign n5 = 1'bz;
+    assign n6 = 1'bz;
+    assign n7 = 1'bz;
+    assign n8 = 1'bz;
+    assign n9 = 1'bz;
+    assign n10 = 1'bz;
+    assign n11 = 1'bz;
+    assign n12 = 1'bz;
+    assign n13 = 1'bz;
+    assign n14 = 1'bz;
+    assign n15 = 1'bz;
+    assign n16 = 1'bz;
+    assign n17 = 1'bz;
+    assign n18 = 1'bz;
+    assign n19 = 1'bz;
+    assign n20 = 1'bz;
+    assign n21 = 1'bz;
+    assign n22 = 1'bz;
+    assign n23 = 1'bz;
+    assign n24 = 1'bz;
+    assign n25 = 1'bz;
+    assign n26 = 1'bz;
+    assign n27 = 1'bz;
+    assign n28 = 1'bz;
+    assign n29 = 1'bz;
+    assign n30 = 1'bz;
+    assign n31 = 1'bz;
+    assign n32 = 1'bz;
+    assign n33 = 1'bz;
+    assign n34 = 1'bz;
+    assign n35 = 1'bz;
+    assign n36 = 1'bz;
+    assign n37 = 1'bz;
+    assign n38 = 1'bz;
+    assign n39 = 1'bz;
+    assign n40 = 1'bz;
+    assign n41 = 1'bz;
+    assign n42 = 1'bz;
+    assign n43 = 1'bz;
+    assign n44 = 1'bz;
+    assign n45 = 1'bz;
+    assign n46 = 1'bz;
+    assign n47 = 1'bz;
+    assign n48 = 1'bz;
+    assign n49 = 1'bz;
+    assign n50 = 1'bz;
+    assign n51 = 1'bz;
+    assign n52 = 1'bz;
+    assign n53 = 1'bz;
+    assign n54 = 1'bz;
+    assign n55 = 1'bz;
+    assign n56 = 1'bz;
+    assign n57 = 1'bz;
+    assign n60 = 1'bz;
+    assign n61 = 1'bz;
+    assign n62 = 1'bz;
+    assign n63 = 1'bz;
+    assign n64 = 1'bz;
+    assign n65 = 1'bz;
+    assign n66 = 1'bz;
+    assign n67 = 1'bz;
+    assign n68 = 1'bz;
+    assign n69 = 1'bz;
+    assign n70 = 1'bz;
+    assign n71 = 1'bz;
+    assign n72 = 1'bz;
+    assign n73 = 1'bz;
+    assign n74 = 1'bz;
+    assign n75 = 1'bz;
+    assign n76 = 1'bz;
+    assign n77 = 1'bz;
+    assign n78 = 1'bz;
+    assign n79 = 1'bz;
+    assign n80 = 1'bz;
+    assign n81 = 1'bz;
+    assign n82 = 1'bz;
+    assign n83 = 1'bz;
+    assign n84 = 1'bz;
+    assign n85 = 1'bz;
+    assign n86 = 1'bz;
+    assign n87 = 1'bz;
+    assign n88 = 1'bz;
+    assign n89 = 1'bz;
+    assign n90 = 1'bz;
+    assign n91 = 1'bz;
+    assign n92 = 1'bz;
+    assign n93 = 1'bz;
+    assign n94 = 1'bz;
+    assign n95 = 1'bz;
+    assign n96 = 1'bz;
+    assign n97 = 1'bz;
+    assign n98 = 1'bz;
+    assign n99 = 1'bz;
+    assign n100 = 1'bz;
+    assign n101 = 1'bz;
+    assign n102 = 1'bz;
+    assign n103 = 1'bz;
+    assign n104 = 1'bz;
+    assign n105 = 1'bz;
+    assign n116 = 1'bz;
+    sgmii_channel_smi_pcsrsl_core rsl_inst (.rui_rst(rsl_rst), .rui_serdes_rst_dual_c(serdes_rst_dual_c), 
+            .rui_rst_dual_c(rst_dual_c), .rui_rsl_disable(rsl_disable), 
+            .rui_tx_ref_clk(pll_refclki), .rui_tx_serdes_rst_c(tx_serdes_rst_c), 
+            .rui_tx_pcs_rst_c({3'b000, tx_pcs_rst_c}), .rdi_pll_lol(pll_lol), 
+            .rui_rx_ref_clk(rxrefclk), .rui_rx_serdes_rst_c({3'b000, rx_serdes_rst_c}), 
+            .rui_rx_pcs_rst_c({3'b000, rx_pcs_rst_c}), .rdi_rx_los_low_s({4'b0000}), 
+            .rdi_rx_cdr_lol_s({3'b000, rx_cdr_lol_s}), .rdo_serdes_rst_dual_c(rsl_serdes_rst_dual_c), 
+            .rdo_rst_dual_c(rsl_rst_dual_c), .ruo_tx_rdy(n117), .rdo_tx_serdes_rst_c(rsl_tx_serdes_rst_c), 
+            .rdo_tx_pcs_rst_c({n118, n119, n120, rsl_tx_pcs_rst_c}), 
+            .ruo_rx_rdy(n121), .rdo_rx_serdes_rst_c({n122, n123, n124, 
+            rsl_rx_serdes_rst_c}), .rdo_rx_pcs_rst_c({n125, n126, _Z, 
+            rsl_rx_pcs_rst_c}));
+    defparam rsl_inst.pnum_channels = 1;
+    defparam rsl_inst.pprotocol = "SGMII";
+    defparam rsl_inst.pserdes_mode = "RX AND TX";
+    defparam rsl_inst.pport_tx_rdy = "DISABLED";
+    defparam rsl_inst.pwait_tx_rdy = 3000;
+    defparam rsl_inst.pport_rx_rdy = "DISABLED";
+    defparam rsl_inst.pwait_rx_rdy = 3000;
+    assign n117 = 1'bz;
+    assign n118 = 1'bz;
+    assign n119 = 1'bz;
+    assign n120 = 1'bz;
+    assign n121 = 1'bz;
+    assign n122 = 1'bz;
+    assign n123 = 1'bz;
+    assign n124 = 1'bz;
+    assign n125 = 1'bz;
+    assign n126 = 1'bz;
+    assign _Z = 1'bz;
+    sgmii_channel_smi_pcssll_core sll_inst (.sli_rst(sli_rst), .sli_refclk(pll_refclki), 
+            .sli_pclk(tx_pclk), .sli_div2_rate(1'b0), .sli_div11_rate(1'b0), 
+            .sli_gear_mode(1'b0), .sli_cpri_mode({3'b000}), .sli_pcie_mode(1'b0), 
+            .slo_plol(pll_lol));
+    defparam sll_inst.PPROTOCOL = "SGMII";
+    defparam sll_inst.PLOL_SETTING = 0;
+    defparam sll_inst.PDYN_RATE_CTRL = "DISABLED";
+    defparam sll_inst.PPCIE_MAX_RATE = "2.5";
+    defparam sll_inst.PDIFF_VAL_LOCK = 19;
+    defparam sll_inst.PDIFF_VAL_UNLOCK = 39;
+    defparam sll_inst.PPCLK_TC = 65536;
+    defparam sll_inst.PDIFF_DIV11_VAL_LOCK = 0;
+    defparam sll_inst.PDIFF_DIV11_VAL_UNLOCK = 0;
+    defparam sll_inst.PPCLK_DIV11_TC = 0;
+    
+endmodule
+
+
+

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_pcs_bb.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_pcs_bb.v
new file mode 100644 (file)
index 0000000..eb97d6c
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_channel_smi_pcs_bb.v
@@ -0,0 +1,57 @@
+// Verilog netlist produced by program ASBGen: Ports rev. 2.22, Attr. rev. 2.25\r
+// Netlist written on Mon Mar 10 15:35:03 2014\r
+//\r
+// Verilog Description of module pcs_serdes\r
+//\r
+\r
+`timescale 1ns/1ps\r
+module sgmii_channel_smi_pcs (hdoutp, hdoutn, hdinp, hdinn, \r
+            rxrefclk, rx_pclk, tx_pclk, txdata, tx_k, xmit, tx_disp_correct, \r
+            rxdata, rx_k, rx_disp_err, rx_cv_err, lsm_status_s, rx_cdr_lol_s, \r
+            tx_pcs_rst_c, rx_pcs_rst_c, rx_serdes_rst_c, tx_pwrup_c, \r
+            rx_pwrup_c, sci_wrdata, sci_addr, sci_rddata, sci_en_dual, \r
+            sci_sel_dual, sci_en, sci_sel, sci_rd, sci_wrn, sci_int, \r
+            cyawstn,rst_dual_c, serdes_rst_dual_c, serdes_pdb, tx_serdes_rst_c, \r
+            pll_refclki, pll_lol)    /*synthesis syn_black_box black_box_pad_pin="hdoutp,hdoutn,hdinp,hdinn"*/;\r
+    output hdoutp;\r
+    output hdoutn;\r
+    input hdinp;\r
+    input hdinn;\r
+    input rxrefclk;\r
+    output rx_pclk;\r
+    output tx_pclk;\r
+    input [7:0]txdata;\r
+    input [0:0]tx_k;\r
+    input [0:0]xmit;\r
+    input [0:0]tx_disp_correct;\r
+    output [7:0]rxdata;\r
+    output [0:0]rx_k;\r
+    output [0:0]rx_disp_err;\r
+    output [0:0]rx_cv_err;\r
+    output lsm_status_s;\r
+    output rx_cdr_lol_s;\r
+    input tx_pcs_rst_c;\r
+    input rx_pcs_rst_c;\r
+    input rx_serdes_rst_c;\r
+    input tx_pwrup_c;\r
+    input rx_pwrup_c;\r
+    input [7:0]sci_wrdata;\r
+    input [5:0]sci_addr;\r
+    output [7:0]sci_rddata;\r
+    input sci_en_dual;\r
+    input sci_sel_dual;\r
+    input sci_en;\r
+    input sci_sel;\r
+    input sci_rd;\r
+    input sci_wrn;\r
+    output sci_int;\r
+    input cyawstn;\r
+    input rst_dual_c;\r
+    input serdes_rst_dual_c;\r
+    input serdes_pdb;\r
+    input tx_serdes_rst_c;\r
+    input pll_refclki;\r
+    output pll_lol;\r
+       \r
+\r
+endmodule\r

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_defines.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_defines.v
new file mode 100644 (file)
index 0000000..ef2ca4e
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_defines.v
@@ -0,0 +1,4 @@
+`define SGMII_NO_ENC
+`define SGMII_YES_CTC_DYNAMIC
+`define SGMII_YES_SINGLE_CLOCK
+`define SGMII_FIFO_FAMILY_ECP5

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs.lpc b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs.lpc
new file mode 100644 (file)
index 0000000..40438e0
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs.lpc
@@ -0,0 +1,97 @@
+[Device]
+Family=sa5p00m
+PartType=LFE5UM-85F
+PartName=LFE5UM-85F-8BG756C
+SpeedGrade=8
+Package=CABGA756
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=IPCFG
+CoreStatus=Demo
+CoreName=PCS
+CoreRevision=4.1
+ModuleName=sgmii_channel_smi_pcs
+SourceFormat=vhdl
+ParameterFileVersion=1.0
+Date=04/30/2019
+Time=12:09:53
+
+[Parameters]
+;ACHARA=0 00H
+;ACHARB=0 00H
+;ACHARM=0 00H
+;RXMCAENABLE=Disabled
+CDRLOLACTION=Full Recalibration
+CDRLOLRANGE=0
+CDR_MAX_RATE=2.5
+CDR_MULT=20X
+CDR_REF_RATE=125.0000
+CH_MODE=Rx and Tx
+Destination=Synplicity
+EDIF=1
+Expression=BusA(0 to 7)
+IO=0
+IO_TYPE=SGMII
+LEQ=1
+LOOPBACK=Disabled
+LOSPORT=Disabled
+NUM_CHS=1
+Order=Big Endian [MSB:LSB]
+PPORT_RX_RDY=Disabled
+PPORT_TX_RDY=Disabled
+PROTOCOL=SGMII
+PWAIT_RX_RDY=3000
+PWAIT_TX_RDY=3000
+RCSRC=Disabled
+REFCLK_RATE=125.0000
+RSTSEQSEL=Enabled
+RX8B10B=Enabled
+RXCOMMAA=1100000101
+RXCOMMAB=0011111010
+RXCOMMAM=1111111111
+RXCOUPLING=AC
+RXCTC=Disabled
+RXCTCBYTEN=0 00H
+RXCTCBYTEN1=0 00H
+RXCTCBYTEN2=0 00H
+RXCTCBYTEN3=0 00H
+RXCTCMATCHPATTERN=M1-S1
+RXDIFFTERM=50 ohms
+RXFIFO_ENABLE=Enabled
+RXINVPOL=Non-invert
+RXLDR=Off
+RXLOSTHRESHOLD=2
+RXLSM=Enabled
+RXSC=K28P5
+RXWA=Barrel Shift
+RX_DATA_WIDTH=8/10-Bit
+RX_FICLK_RATE=125.0000
+RX_LINE_RATE=1.2500
+RX_RATE_DIV=Div2 Rate
+SCIPORT=Enabled
+SOFTLOL=Enabled
+TX8B10B=Enabled
+TXAMPLITUDE=6
+TXDEPOST=Disabled
+TXDEPRE=Disabled
+TXDIFFTERM=50 ohms
+TXFIFO_ENABLE=Enabled
+TXINVPOL=Non-invert
+TXLDR=Off
+TXPLLLOLTHRESHOLD=0
+TXPLLMULT=20X
+TX_DATA_WIDTH=8/10-Bit
+TX_FICLK_RATE=125.0000
+TX_LINE_RATE=1.2500
+TX_MAX_RATE=2.5
+TX_RATE_DIV=Div2 Rate
+VHDL=0
+Verilog=1
+
+[SYSTEMPNR]
+LN0=DCU0_CH0
+
+

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs.v
new file mode 100644 (file)
index 0000000..32eab38
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs.v
@@ -0,0 +1,476 @@
+// Verilog netlist produced by program ASBGen: Ports rev. 2.30, Attr. rev. 2.70
+// Netlist written on Tue Apr 30 12:09:53 2019
+//
+// Verilog Description of module sgmii_channel_smi_pcs
+//
+
+`timescale 1ns/1ps
+module sgmii_channel_smi_pcs (hdoutp, hdoutn, hdinp, 
+            hdinn, rxrefclk, rx_pclk, txi_clk, tx_pclk, txdata, 
+            tx_k, xmit, tx_disp_correct, rxdata, rx_k, rx_disp_err, 
+            rx_cv_err, signal_detect_c, lsm_status_s, rx_cdr_lol_s, 
+            sli_rst, tx_pwrup_c, rx_pwrup_c, sci_wrdata, sci_addr, 
+            sci_rddata, sci_en_dual, sci_sel_dual, sci_en, sci_sel, 
+            sci_rd, sci_wrn, sci_int, cyawstn, serdes_pdb, pll_refclki, 
+            rsl_disable, rsl_rst, serdes_rst_dual_c, rst_dual_c, tx_serdes_rst_c, 
+            tx_pcs_rst_c, pll_lol, rx_serdes_rst_c, rx_pcs_rst_c);
+    output hdoutp;
+    output hdoutn;
+    input hdinp;
+    input hdinn;
+    input rxrefclk;
+    output rx_pclk;
+    input txi_clk;
+    output tx_pclk;
+    input [7:0]txdata;
+    input [0:0]tx_k;
+    input [0:0]xmit;
+    input [0:0]tx_disp_correct;
+    output [7:0]rxdata;
+    output [0:0]rx_k;
+    output [0:0]rx_disp_err;
+    output [0:0]rx_cv_err;
+    input signal_detect_c;
+    output lsm_status_s;
+    output rx_cdr_lol_s;
+    input sli_rst;
+    input tx_pwrup_c;
+    input rx_pwrup_c;
+    input [7:0]sci_wrdata;
+    input [5:0]sci_addr;
+    output [7:0]sci_rddata;
+    input sci_en_dual;
+    input sci_sel_dual;
+    input sci_en;
+    input sci_sel;
+    input sci_rd;
+    input sci_wrn;
+    output sci_int;
+    input cyawstn;
+    input serdes_pdb;
+    input pll_refclki;
+    input rsl_disable;
+    input rsl_rst;
+    input serdes_rst_dual_c;
+    input rst_dual_c;
+    input tx_serdes_rst_c;
+    input tx_pcs_rst_c;
+    output pll_lol;
+    input rx_serdes_rst_c;
+    input rx_pcs_rst_c;
+    
+    
+    wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, 
+        n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, 
+        n22, n23, n24, n25, n26, n27, n28, n29, rsl_tx_pcs_rst_c, 
+        rsl_rx_pcs_rst_c, rsl_rx_serdes_rst_c, rsl_rst_dual_c, rsl_serdes_rst_dual_c, 
+        rsl_tx_serdes_rst_c, n30, n31, n32, n33, n34, n35, n36, 
+        n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, 
+        n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, 
+        n57, n60, n61, n62, n63, n64, n65, n66, n67, n68, 
+        n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, 
+        n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, 
+        n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, 
+        n99, n100, n101, n102, n103, n104, n105, n116, n117, 
+        n118, n119, n120, n121, n122, n123, n124, n125, n126, 
+        _Z;
+    
+    DCUA DCU0_inst (.CH0_HDINP(hdinp), .CH1_HDINP(1'b0), .CH0_HDINN(hdinn), 
+         .CH1_HDINN(1'b0), .D_TXBIT_CLKP_FROM_ND(1'b0), .D_TXBIT_CLKN_FROM_ND(1'b0), 
+         .D_SYNC_ND(1'b0), .D_TXPLL_LOL_FROM_ND(1'b0), .CH0_RX_REFCLK(rxrefclk), 
+         .CH1_RX_REFCLK(1'b0), .CH0_FF_RXI_CLK(rx_pclk), .CH1_FF_RXI_CLK(1'b1), 
+         .CH0_FF_TXI_CLK(txi_clk), .CH1_FF_TXI_CLK(1'b1), .CH0_FF_EBRD_CLK(1'b1), 
+         .CH1_FF_EBRD_CLK(1'b1), .CH0_FF_TX_D_0(txdata[0]), .CH1_FF_TX_D_0(1'b0), 
+         .CH0_FF_TX_D_1(txdata[1]), .CH1_FF_TX_D_1(1'b0), .CH0_FF_TX_D_2(txdata[2]), 
+         .CH1_FF_TX_D_2(1'b0), .CH0_FF_TX_D_3(txdata[3]), .CH1_FF_TX_D_3(1'b0), 
+         .CH0_FF_TX_D_4(txdata[4]), .CH1_FF_TX_D_4(1'b0), .CH0_FF_TX_D_5(txdata[5]), 
+         .CH1_FF_TX_D_5(1'b0), .CH0_FF_TX_D_6(txdata[6]), .CH1_FF_TX_D_6(1'b0), 
+         .CH0_FF_TX_D_7(txdata[7]), .CH1_FF_TX_D_7(1'b0), .CH0_FF_TX_D_8(tx_k[0]), 
+         .CH1_FF_TX_D_8(1'b0), .CH0_FF_TX_D_9(1'b0), .CH1_FF_TX_D_9(1'b0), 
+         .CH0_FF_TX_D_10(xmit[0]), .CH1_FF_TX_D_10(1'b0), .CH0_FF_TX_D_11(tx_disp_correct[0]), 
+         .CH1_FF_TX_D_11(1'b0), .CH0_FF_TX_D_12(1'b0), .CH1_FF_TX_D_12(1'b0), 
+         .CH0_FF_TX_D_13(1'b0), .CH1_FF_TX_D_13(1'b0), .CH0_FF_TX_D_14(1'b0), 
+         .CH1_FF_TX_D_14(1'b0), .CH0_FF_TX_D_15(1'b0), .CH1_FF_TX_D_15(1'b0), 
+         .CH0_FF_TX_D_16(1'b0), .CH1_FF_TX_D_16(1'b0), .CH0_FF_TX_D_17(1'b0), 
+         .CH1_FF_TX_D_17(1'b0), .CH0_FF_TX_D_18(1'b0), .CH1_FF_TX_D_18(1'b0), 
+         .CH0_FF_TX_D_19(1'b0), .CH1_FF_TX_D_19(1'b0), .CH0_FF_TX_D_20(1'b0), 
+         .CH1_FF_TX_D_20(1'b0), .CH0_FF_TX_D_21(1'b0), .CH1_FF_TX_D_21(1'b0), 
+         .CH0_FF_TX_D_22(1'b0), .CH1_FF_TX_D_22(1'b0), .CH0_FF_TX_D_23(1'b0), 
+         .CH1_FF_TX_D_23(1'b0), .CH0_FFC_EI_EN(1'b0), .CH1_FFC_EI_EN(1'b0), 
+         .CH0_FFC_PCIE_DET_EN(1'b0), .CH1_FFC_PCIE_DET_EN(1'b0), .CH0_FFC_PCIE_CT(1'b0), 
+         .CH1_FFC_PCIE_CT(1'b0), .CH0_FFC_SB_INV_RX(1'b0), .CH1_FFC_SB_INV_RX(1'b0), 
+         .CH0_FFC_ENABLE_CGALIGN(1'b0), .CH1_FFC_ENABLE_CGALIGN(1'b0), .CH0_FFC_SIGNAL_DETECT(signal_detect_c), 
+         .CH1_FFC_SIGNAL_DETECT(1'b0), .CH0_FFC_FB_LOOPBACK(1'b0), .CH1_FFC_FB_LOOPBACK(1'b0), 
+         .CH0_FFC_SB_PFIFO_LP(1'b0), .CH1_FFC_SB_PFIFO_LP(1'b0), .CH0_FFC_PFIFO_CLR(1'b0), 
+         .CH1_FFC_PFIFO_CLR(1'b0), .CH0_FFC_RATE_MODE_RX(1'b0), .CH1_FFC_RATE_MODE_RX(1'b0), 
+         .CH0_FFC_RATE_MODE_TX(1'b0), .CH1_FFC_RATE_MODE_TX(1'b0), .CH0_FFC_DIV11_MODE_RX(1'b0), 
+         .CH1_FFC_DIV11_MODE_RX(1'b0), .CH0_FFC_DIV11_MODE_TX(1'b0), .CH1_FFC_DIV11_MODE_TX(1'b0), 
+         .CH0_FFC_RX_GEAR_MODE(1'b0), .CH1_FFC_RX_GEAR_MODE(1'b0), .CH0_FFC_TX_GEAR_MODE(1'b0), 
+         .CH1_FFC_TX_GEAR_MODE(1'b0), .CH0_FFC_LDR_CORE2TX_EN(1'b0), .CH1_FFC_LDR_CORE2TX_EN(1'b0), 
+         .CH0_FFC_LANE_TX_RST(rsl_tx_pcs_rst_c), .CH1_FFC_LANE_TX_RST(1'b0), 
+         .CH0_FFC_LANE_RX_RST(rsl_rx_pcs_rst_c), .CH1_FFC_LANE_RX_RST(1'b0), 
+         .CH0_FFC_RRST(rsl_rx_serdes_rst_c), .CH1_FFC_RRST(1'b0), .CH0_FFC_TXPWDNB(tx_pwrup_c), 
+         .CH1_FFC_TXPWDNB(1'b0), .CH0_FFC_RXPWDNB(rx_pwrup_c), .CH1_FFC_RXPWDNB(1'b0), 
+         .CH0_LDR_CORE2TX(1'b0), .CH1_LDR_CORE2TX(1'b0), .D_SCIWDATA0(sci_wrdata[0]), 
+         .D_SCIWDATA1(sci_wrdata[1]), .D_SCIWDATA2(sci_wrdata[2]), .D_SCIWDATA3(sci_wrdata[3]), 
+         .D_SCIWDATA4(sci_wrdata[4]), .D_SCIWDATA5(sci_wrdata[5]), .D_SCIWDATA6(sci_wrdata[6]), 
+         .D_SCIWDATA7(sci_wrdata[7]), .D_SCIADDR0(sci_addr[0]), .D_SCIADDR1(sci_addr[1]), 
+         .D_SCIADDR2(sci_addr[2]), .D_SCIADDR3(sci_addr[3]), .D_SCIADDR4(sci_addr[4]), 
+         .D_SCIADDR5(sci_addr[5]), .D_SCIENAUX(sci_en_dual), .D_SCISELAUX(sci_sel_dual), 
+         .CH0_SCIEN(sci_en), .CH1_SCIEN(1'b0), .CH0_SCISEL(sci_sel), .CH1_SCISEL(1'b0), 
+         .D_SCIRD(sci_rd), .D_SCIWSTN(sci_wrn), .D_CYAWSTN(cyawstn), .D_FFC_SYNC_TOGGLE(1'b0), 
+         .D_FFC_DUAL_RST(rsl_rst_dual_c), .D_FFC_MACRO_RST(rsl_serdes_rst_dual_c), 
+         .D_FFC_MACROPDB(serdes_pdb), .D_FFC_TRST(rsl_tx_serdes_rst_c), 
+         .CH0_FFC_CDR_EN_BITSLIP(1'b0), .CH1_FFC_CDR_EN_BITSLIP(1'b0), .D_SCAN_ENABLE(1'b0), 
+         .D_SCAN_IN_0(1'b0), .D_SCAN_IN_1(1'b0), .D_SCAN_IN_2(1'b0), .D_SCAN_IN_3(1'b0), 
+         .D_SCAN_IN_4(1'b0), .D_SCAN_IN_5(1'b0), .D_SCAN_IN_6(1'b0), .D_SCAN_IN_7(1'b0), 
+         .D_SCAN_MODE(1'b0), .D_SCAN_RESET(1'b0), .D_CIN0(1'b0), .D_CIN1(1'b0), 
+         .D_CIN2(1'b0), .D_CIN3(1'b0), .D_CIN4(1'b0), .D_CIN5(1'b0), 
+         .D_CIN6(1'b0), .D_CIN7(1'b0), .D_CIN8(1'b0), .D_CIN9(1'b0), 
+         .D_CIN10(1'b0), .D_CIN11(1'b0), .CH0_HDOUTP(hdoutp), .CH1_HDOUTP(n61), 
+         .CH0_HDOUTN(hdoutn), .CH1_HDOUTN(n62), .D_TXBIT_CLKP_TO_ND(n1), 
+         .D_TXBIT_CLKN_TO_ND(n2), .D_SYNC_PULSE2ND(n3), .D_TXPLL_LOL_TO_ND(n4), 
+         .CH0_FF_RX_F_CLK(n5), .CH1_FF_RX_F_CLK(n63), .CH0_FF_RX_H_CLK(n6), 
+         .CH1_FF_RX_H_CLK(n64), .CH0_FF_TX_F_CLK(n7), .CH1_FF_TX_F_CLK(n65), 
+         .CH0_FF_TX_H_CLK(n8), .CH1_FF_TX_H_CLK(n66), .CH0_FF_RX_PCLK(rx_pclk), 
+         .CH1_FF_RX_PCLK(n67), .CH0_FF_TX_PCLK(tx_pclk), .CH1_FF_TX_PCLK(n68), 
+         .CH0_FF_RX_D_0(rxdata[0]), .CH1_FF_RX_D_0(n69), .CH0_FF_RX_D_1(rxdata[1]), 
+         .CH1_FF_RX_D_1(n70), .CH0_FF_RX_D_2(rxdata[2]), .CH1_FF_RX_D_2(n71), 
+         .CH0_FF_RX_D_3(rxdata[3]), .CH1_FF_RX_D_3(n72), .CH0_FF_RX_D_4(rxdata[4]), 
+         .CH1_FF_RX_D_4(n73), .CH0_FF_RX_D_5(rxdata[5]), .CH1_FF_RX_D_5(n74), 
+         .CH0_FF_RX_D_6(rxdata[6]), .CH1_FF_RX_D_6(n75), .CH0_FF_RX_D_7(rxdata[7]), 
+         .CH1_FF_RX_D_7(n76), .CH0_FF_RX_D_8(rx_k[0]), .CH1_FF_RX_D_8(n77), 
+         .CH0_FF_RX_D_9(rx_disp_err[0]), .CH1_FF_RX_D_9(n78), .CH0_FF_RX_D_10(rx_cv_err[0]), 
+         .CH1_FF_RX_D_10(n79), .CH0_FF_RX_D_11(n9), .CH1_FF_RX_D_11(n80), 
+         .CH0_FF_RX_D_12(n10), .CH1_FF_RX_D_12(n81), .CH0_FF_RX_D_13(n11), 
+         .CH1_FF_RX_D_13(n82), .CH0_FF_RX_D_14(n12), .CH1_FF_RX_D_14(n83), 
+         .CH0_FF_RX_D_15(n13), .CH1_FF_RX_D_15(n84), .CH0_FF_RX_D_16(n14), 
+         .CH1_FF_RX_D_16(n85), .CH0_FF_RX_D_17(n15), .CH1_FF_RX_D_17(n86), 
+         .CH0_FF_RX_D_18(n16), .CH1_FF_RX_D_18(n87), .CH0_FF_RX_D_19(n17), 
+         .CH1_FF_RX_D_19(n88), .CH0_FF_RX_D_20(n18), .CH1_FF_RX_D_20(n89), 
+         .CH0_FF_RX_D_21(n19), .CH1_FF_RX_D_21(n90), .CH0_FF_RX_D_22(n20), 
+         .CH1_FF_RX_D_22(n91), .CH0_FF_RX_D_23(n21), .CH1_FF_RX_D_23(n92), 
+         .CH0_FFS_PCIE_DONE(n22), .CH1_FFS_PCIE_DONE(n93), .CH0_FFS_PCIE_CON(n23), 
+         .CH1_FFS_PCIE_CON(n94), .CH0_FFS_RLOS(n95), .CH1_FFS_RLOS(n96), 
+         .CH0_FFS_LS_SYNC_STATUS(lsm_status_s), .CH1_FFS_LS_SYNC_STATUS(n97), 
+         .CH0_FFS_CC_UNDERRUN(n24), .CH1_FFS_CC_UNDERRUN(n98), .CH0_FFS_CC_OVERRUN(n25), 
+         .CH1_FFS_CC_OVERRUN(n99), .CH0_FFS_RXFBFIFO_ERROR(n26), .CH1_FFS_RXFBFIFO_ERROR(n100), 
+         .CH0_FFS_TXFBFIFO_ERROR(n27), .CH1_FFS_TXFBFIFO_ERROR(n101), .CH0_FFS_RLOL(rx_cdr_lol_s), 
+         .CH1_FFS_RLOL(n102), .CH0_FFS_SKP_ADDED(n28), .CH1_FFS_SKP_ADDED(n103), 
+         .CH0_FFS_SKP_DELETED(n29), .CH1_FFS_SKP_DELETED(n104), .CH0_LDR_RX2CORE(n105), 
+         .CH1_LDR_RX2CORE(n116), .D_SCIRDATA0(sci_rddata[0]), .D_SCIRDATA1(sci_rddata[1]), 
+         .D_SCIRDATA2(sci_rddata[2]), .D_SCIRDATA3(sci_rddata[3]), .D_SCIRDATA4(sci_rddata[4]), 
+         .D_SCIRDATA5(sci_rddata[5]), .D_SCIRDATA6(sci_rddata[6]), .D_SCIRDATA7(sci_rddata[7]), 
+         .D_SCIINT(sci_int), .D_SCAN_OUT_0(n30), .D_SCAN_OUT_1(n31), .D_SCAN_OUT_2(n32), 
+         .D_SCAN_OUT_3(n33), .D_SCAN_OUT_4(n34), .D_SCAN_OUT_5(n35), .D_SCAN_OUT_6(n36), 
+         .D_SCAN_OUT_7(n37), .D_COUT0(n38), .D_COUT1(n39), .D_COUT2(n40), 
+         .D_COUT3(n41), .D_COUT4(n42), .D_COUT5(n43), .D_COUT6(n44), 
+         .D_COUT7(n45), .D_COUT8(n46), .D_COUT9(n47), .D_COUT10(n48), 
+         .D_COUT11(n49), .D_COUT12(n50), .D_COUT13(n51), .D_COUT14(n52), 
+         .D_COUT15(n53), .D_COUT16(n54), .D_COUT17(n55), .D_COUT18(n56), 
+         .D_COUT19(n57), .D_REFCLKI(pll_refclki), .D_FFS_PLOL(n60)) /* synthesis LOC=DCU0 CHAN=CH0 */ ;
+    defparam DCU0_inst.D_MACROPDB = "0b1";
+    defparam DCU0_inst.D_IB_PWDNB = "0b1";
+    defparam DCU0_inst.D_XGE_MODE = "0b0";
+    defparam DCU0_inst.D_LOW_MARK = "0d4";
+    defparam DCU0_inst.D_HIGH_MARK = "0d12";
+    defparam DCU0_inst.D_BUS8BIT_SEL = "0b0";
+    defparam DCU0_inst.D_CDR_LOL_SET = "0b00";
+    defparam DCU0_inst.D_TXPLL_PWDNB = "0b1";
+    defparam DCU0_inst.D_BITCLK_LOCAL_EN = "0b1";
+    defparam DCU0_inst.D_BITCLK_ND_EN = "0b0";
+    defparam DCU0_inst.D_BITCLK_FROM_ND_EN = "0b0";
+    defparam DCU0_inst.D_SYNC_LOCAL_EN = "0b1";
+    defparam DCU0_inst.D_SYNC_ND_EN = "0b0";
+    defparam DCU0_inst.CH0_UC_MODE = "0b0";
+    defparam DCU0_inst.CH0_PCIE_MODE = "0b0";
+    defparam DCU0_inst.CH0_RIO_MODE = "0b0";
+    defparam DCU0_inst.CH0_WA_MODE = "0b0";
+    defparam DCU0_inst.CH0_INVERT_RX = "0b0";
+    defparam DCU0_inst.CH0_INVERT_TX = "0b0";
+    defparam DCU0_inst.CH0_PRBS_SELECTION = "0b0";
+    defparam DCU0_inst.CH0_GE_AN_ENABLE = "0b1";
+    defparam DCU0_inst.CH0_PRBS_LOCK = "0b0";
+    defparam DCU0_inst.CH0_PRBS_ENABLE = "0b0";
+    defparam DCU0_inst.CH0_ENABLE_CG_ALIGN = "0b1";
+    defparam DCU0_inst.CH0_TX_GEAR_MODE = "0b0";
+    defparam DCU0_inst.CH0_RX_GEAR_MODE = "0b0";
+    defparam DCU0_inst.CH0_PCS_DET_TIME_SEL = "0b00";
+    defparam DCU0_inst.CH0_PCIE_EI_EN = "0b0";
+    defparam DCU0_inst.CH0_TX_GEAR_BYPASS = "0b0";
+    defparam DCU0_inst.CH0_ENC_BYPASS = "0b0";
+    defparam DCU0_inst.CH0_SB_BYPASS = "0b0";
+    defparam DCU0_inst.CH0_RX_SB_BYPASS = "0b0";
+    defparam DCU0_inst.CH0_WA_BYPASS = "0b0";
+    defparam DCU0_inst.CH0_DEC_BYPASS = "0b0";
+    defparam DCU0_inst.CH0_CTC_BYPASS = "0b1";
+    defparam DCU0_inst.CH0_RX_GEAR_BYPASS = "0b0";
+    defparam DCU0_inst.CH0_LSM_DISABLE = "0b0";
+    defparam DCU0_inst.CH0_MATCH_2_ENABLE = "0b0";
+    defparam DCU0_inst.CH0_MATCH_4_ENABLE = "0b0";
+    defparam DCU0_inst.CH0_MIN_IPG_CNT = "0b11";
+    defparam DCU0_inst.CH0_CC_MATCH_1 = "0x000";
+    defparam DCU0_inst.CH0_CC_MATCH_2 = "0x000";
+    defparam DCU0_inst.CH0_CC_MATCH_3 = "0x000";
+    defparam DCU0_inst.CH0_CC_MATCH_4 = "0x000";
+    defparam DCU0_inst.CH0_UDF_COMMA_MASK = "0x3ff";
+    defparam DCU0_inst.CH0_UDF_COMMA_A = "0x283";
+    defparam DCU0_inst.CH0_UDF_COMMA_B = "0x17C";
+    defparam DCU0_inst.CH0_RX_DCO_CK_DIV = "0b000";
+    defparam DCU0_inst.CH0_RCV_DCC_EN = "0b0";
+    defparam DCU0_inst.CH0_TPWDNB = "0b1";
+    defparam DCU0_inst.CH0_RATE_MODE_TX = "0b1";
+    defparam DCU0_inst.CH0_RTERM_TX = "0d19";
+    defparam DCU0_inst.CH0_TX_CM_SEL = "0b00";
+    defparam DCU0_inst.CH0_TDRV_PRE_EN = "0b0";
+    defparam DCU0_inst.CH0_TDRV_SLICE0_SEL = "0b01";
+    defparam DCU0_inst.CH0_TDRV_SLICE1_SEL = "0b00";
+    defparam DCU0_inst.CH0_TDRV_SLICE2_SEL = "0b01";
+    defparam DCU0_inst.CH0_TDRV_SLICE3_SEL = "0b01";
+    defparam DCU0_inst.CH0_TDRV_SLICE4_SEL = "0b01";
+    defparam DCU0_inst.CH0_TDRV_SLICE5_SEL = "0b00";
+    defparam DCU0_inst.CH0_TDRV_SLICE0_CUR = "0b011";
+    defparam DCU0_inst.CH0_TDRV_SLICE1_CUR = "0b000";
+    defparam DCU0_inst.CH0_TDRV_SLICE2_CUR = "0b11";
+    defparam DCU0_inst.CH0_TDRV_SLICE3_CUR = "0b11";
+    defparam DCU0_inst.CH0_TDRV_SLICE4_CUR = "0b11";
+    defparam DCU0_inst.CH0_TDRV_SLICE5_CUR = "0b00";
+    defparam DCU0_inst.CH0_TDRV_DAT_SEL = "0b00";
+    defparam DCU0_inst.CH0_TX_DIV11_SEL = "0b0";
+    defparam DCU0_inst.CH0_RPWDNB = "0b1";
+    defparam DCU0_inst.CH0_RATE_MODE_RX = "0b1";
+    defparam DCU0_inst.CH0_RX_DIV11_SEL = "0b0";
+    defparam DCU0_inst.CH0_SEL_SD_RX_CLK = "0b1";
+    defparam DCU0_inst.CH0_FF_RX_H_CLK_EN = "0b0";
+    defparam DCU0_inst.CH0_FF_RX_F_CLK_DIS = "0b0";
+    defparam DCU0_inst.CH0_FF_TX_H_CLK_EN = "0b0";
+    defparam DCU0_inst.CH0_FF_TX_F_CLK_DIS = "0b0";
+    defparam DCU0_inst.CH0_TDRV_POST_EN = "0b0";
+    defparam DCU0_inst.CH0_TX_POST_SIGN = "0b0";
+    defparam DCU0_inst.CH0_TX_PRE_SIGN = "0b0";
+    defparam DCU0_inst.CH0_REQ_LVL_SET = "0b01";
+    defparam DCU0_inst.CH0_REQ_EN = "0b1";
+    defparam DCU0_inst.CH0_RTERM_RX = "0d22";
+    defparam DCU0_inst.CH0_RXTERM_CM = "0b11";
+    defparam DCU0_inst.CH0_PDEN_SEL = "0b1";
+    defparam DCU0_inst.CH0_RXIN_CM = "0b11";
+    defparam DCU0_inst.CH0_LEQ_OFFSET_SEL = "0b0";
+    defparam DCU0_inst.CH0_LEQ_OFFSET_TRIM = "0b000";
+    defparam DCU0_inst.CH0_RLOS_SEL = "0b1";
+    defparam DCU0_inst.CH0_RX_LOS_LVL = "0b010";
+    defparam DCU0_inst.CH0_RX_LOS_CEQ = "0b11";
+    defparam DCU0_inst.CH0_RX_LOS_HYST_EN = "0b0";
+    defparam DCU0_inst.CH0_RX_LOS_EN = "0b0";
+    defparam DCU0_inst.CH0_LDR_RX2CORE_SEL = "0b0";
+    defparam DCU0_inst.CH0_LDR_CORE2TX_SEL = "0b0";
+    defparam DCU0_inst.D_TX_MAX_RATE = "2.5";
+    defparam DCU0_inst.CH0_CDR_MAX_RATE = "2.5";
+    defparam DCU0_inst.CH0_TXAMPLITUDE = "0d6";
+    defparam DCU0_inst.CH0_TXDEPRE = "DISABLED";
+    defparam DCU0_inst.CH0_TXDEPOST = "DISABLED";
+    defparam DCU0_inst.CH0_PROTOCOL = "SGMII";
+    defparam DCU0_inst.D_ISETLOS = "0d0";
+    defparam DCU0_inst.D_SETIRPOLY_AUX = "0b00";
+    defparam DCU0_inst.D_SETICONST_AUX = "0b00";
+    defparam DCU0_inst.D_SETIRPOLY_CH = "0b00";
+    defparam DCU0_inst.D_SETICONST_CH = "0b00";
+    defparam DCU0_inst.D_REQ_ISET = "0b000";
+    defparam DCU0_inst.D_PD_ISET = "0b00";
+    defparam DCU0_inst.D_DCO_CALIB_TIME_SEL = "0b00";
+    defparam DCU0_inst.CH0_CDR_CNT4SEL = "0b00";
+    defparam DCU0_inst.CH0_CDR_CNT8SEL = "0b00";
+    defparam DCU0_inst.CH0_DCOATDCFG = "0b00";
+    defparam DCU0_inst.CH0_DCOATDDLY = "0b00";
+    defparam DCU0_inst.CH0_DCOBYPSATD = "0b1";
+    defparam DCU0_inst.CH0_DCOCALDIV = "0b001";
+    defparam DCU0_inst.CH0_DCOCTLGI = "0b010";
+    defparam DCU0_inst.CH0_DCODISBDAVOID = "0b0";
+    defparam DCU0_inst.CH0_DCOFLTDAC = "0b01";
+    defparam DCU0_inst.CH0_DCOFTNRG = "0b110";
+    defparam DCU0_inst.CH0_DCOIOSTUNE = "0b000";
+    defparam DCU0_inst.CH0_DCOITUNE = "0b00";
+    defparam DCU0_inst.CH0_DCOITUNE4LSB = "0b111";
+    defparam DCU0_inst.CH0_DCOIUPDNX2 = "0b1";
+    defparam DCU0_inst.CH0_DCONUOFLSB = "0b101";
+    defparam DCU0_inst.CH0_DCOSCALEI = "0b00";
+    defparam DCU0_inst.CH0_DCOSTARTVAL = "0b000";
+    defparam DCU0_inst.CH0_DCOSTEP = "0b00";
+    defparam DCU0_inst.CH0_BAND_THRESHOLD = "0d0";
+    defparam DCU0_inst.CH0_AUTO_FACQ_EN = "0b1";
+    defparam DCU0_inst.CH0_AUTO_CALIB_EN = "0b1";
+    defparam DCU0_inst.CH0_CALIB_CK_MODE = "0b0";
+    defparam DCU0_inst.CH0_REG_BAND_OFFSET = "0d0";
+    defparam DCU0_inst.CH0_REG_BAND_SEL = "0d0";
+    defparam DCU0_inst.CH0_REG_IDAC_SEL = "0d0";
+    defparam DCU0_inst.CH0_REG_IDAC_EN = "0b0";
+    defparam DCU0_inst.D_CMUSETISCL4VCO = "0b000";
+    defparam DCU0_inst.D_CMUSETI4VCO = "0b00";
+    defparam DCU0_inst.D_CMUSETINITVCT = "0b00";
+    defparam DCU0_inst.D_CMUSETZGM = "0b000";
+    defparam DCU0_inst.D_CMUSETP2AGM = "0b000";
+    defparam DCU0_inst.D_CMUSETP1GM = "0b000";
+    defparam DCU0_inst.D_CMUSETI4CPZ = "0d3";
+    defparam DCU0_inst.D_CMUSETI4CPP = "0d3";
+    defparam DCU0_inst.D_CMUSETICP4Z = "0b101";
+    defparam DCU0_inst.D_CMUSETICP4P = "0b01";
+    defparam DCU0_inst.D_CMUSETBIASI = "0b00";
+    defparam DCU0_inst.D_SETPLLRC = "0d1";
+    defparam DCU0_inst.CH0_RX_RATE_SEL = "0d8";
+    defparam DCU0_inst.D_REFCK_MODE = "0b000";
+    defparam DCU0_inst.D_TX_VCO_CK_DIV = "0b000";
+    defparam DCU0_inst.D_PLL_LOL_SET = "0b00";
+    defparam DCU0_inst.D_RG_EN = "0b0";
+    defparam DCU0_inst.D_RG_SET = "0b00";
+    assign n1 = 1'bz;
+    assign n2 = 1'bz;
+    assign n3 = 1'bz;
+    assign n4 = 1'bz;
+    assign n5 = 1'bz;
+    assign n6 = 1'bz;
+    assign n7 = 1'bz;
+    assign n8 = 1'bz;
+    assign n9 = 1'bz;
+    assign n10 = 1'bz;
+    assign n11 = 1'bz;
+    assign n12 = 1'bz;
+    assign n13 = 1'bz;
+    assign n14 = 1'bz;
+    assign n15 = 1'bz;
+    assign n16 = 1'bz;
+    assign n17 = 1'bz;
+    assign n18 = 1'bz;
+    assign n19 = 1'bz;
+    assign n20 = 1'bz;
+    assign n21 = 1'bz;
+    assign n22 = 1'bz;
+    assign n23 = 1'bz;
+    assign n24 = 1'bz;
+    assign n25 = 1'bz;
+    assign n26 = 1'bz;
+    assign n27 = 1'bz;
+    assign n28 = 1'bz;
+    assign n29 = 1'bz;
+    assign n30 = 1'bz;
+    assign n31 = 1'bz;
+    assign n32 = 1'bz;
+    assign n33 = 1'bz;
+    assign n34 = 1'bz;
+    assign n35 = 1'bz;
+    assign n36 = 1'bz;
+    assign n37 = 1'bz;
+    assign n38 = 1'bz;
+    assign n39 = 1'bz;
+    assign n40 = 1'bz;
+    assign n41 = 1'bz;
+    assign n42 = 1'bz;
+    assign n43 = 1'bz;
+    assign n44 = 1'bz;
+    assign n45 = 1'bz;
+    assign n46 = 1'bz;
+    assign n47 = 1'bz;
+    assign n48 = 1'bz;
+    assign n49 = 1'bz;
+    assign n50 = 1'bz;
+    assign n51 = 1'bz;
+    assign n52 = 1'bz;
+    assign n53 = 1'bz;
+    assign n54 = 1'bz;
+    assign n55 = 1'bz;
+    assign n56 = 1'bz;
+    assign n57 = 1'bz;
+    assign n60 = 1'bz;
+    assign n61 = 1'bz;
+    assign n62 = 1'bz;
+    assign n63 = 1'bz;
+    assign n64 = 1'bz;
+    assign n65 = 1'bz;
+    assign n66 = 1'bz;
+    assign n67 = 1'bz;
+    assign n68 = 1'bz;
+    assign n69 = 1'bz;
+    assign n70 = 1'bz;
+    assign n71 = 1'bz;
+    assign n72 = 1'bz;
+    assign n73 = 1'bz;
+    assign n74 = 1'bz;
+    assign n75 = 1'bz;
+    assign n76 = 1'bz;
+    assign n77 = 1'bz;
+    assign n78 = 1'bz;
+    assign n79 = 1'bz;
+    assign n80 = 1'bz;
+    assign n81 = 1'bz;
+    assign n82 = 1'bz;
+    assign n83 = 1'bz;
+    assign n84 = 1'bz;
+    assign n85 = 1'bz;
+    assign n86 = 1'bz;
+    assign n87 = 1'bz;
+    assign n88 = 1'bz;
+    assign n89 = 1'bz;
+    assign n90 = 1'bz;
+    assign n91 = 1'bz;
+    assign n92 = 1'bz;
+    assign n93 = 1'bz;
+    assign n94 = 1'bz;
+    assign n95 = 1'bz;
+    assign n96 = 1'bz;
+    assign n97 = 1'bz;
+    assign n98 = 1'bz;
+    assign n99 = 1'bz;
+    assign n100 = 1'bz;
+    assign n101 = 1'bz;
+    assign n102 = 1'bz;
+    assign n103 = 1'bz;
+    assign n104 = 1'bz;
+    assign n105 = 1'bz;
+    assign n116 = 1'bz;
+    sgmii_channel_smi_pcsrsl_core rsl_inst (.rui_rst(rsl_rst), .rui_serdes_rst_dual_c(serdes_rst_dual_c), 
+            .rui_rst_dual_c(rst_dual_c), .rui_rsl_disable(rsl_disable), 
+            .rui_tx_ref_clk(pll_refclki), .rui_tx_serdes_rst_c(tx_serdes_rst_c), 
+            .rui_tx_pcs_rst_c({3'b000, tx_pcs_rst_c}), .rdi_pll_lol(pll_lol), 
+            .rui_rx_ref_clk(rxrefclk), .rui_rx_serdes_rst_c({3'b000, rx_serdes_rst_c}), 
+            .rui_rx_pcs_rst_c({3'b000, rx_pcs_rst_c}), .rdi_rx_los_low_s({4'b0000}), 
+            .rdi_rx_cdr_lol_s({3'b000, rx_cdr_lol_s}), .rdo_serdes_rst_dual_c(rsl_serdes_rst_dual_c), 
+            .rdo_rst_dual_c(rsl_rst_dual_c), .ruo_tx_rdy(n117), .rdo_tx_serdes_rst_c(rsl_tx_serdes_rst_c), 
+            .rdo_tx_pcs_rst_c({n118, n119, n120, rsl_tx_pcs_rst_c}), 
+            .ruo_rx_rdy(n121), .rdo_rx_serdes_rst_c({n122, n123, n124, 
+            rsl_rx_serdes_rst_c}), .rdo_rx_pcs_rst_c({n125, n126, _Z, 
+            rsl_rx_pcs_rst_c}));
+    defparam rsl_inst.pnum_channels = 1;
+    defparam rsl_inst.pprotocol = "SGMII";
+    defparam rsl_inst.pserdes_mode = "RX AND TX";
+    defparam rsl_inst.pport_tx_rdy = "DISABLED";
+    defparam rsl_inst.pwait_tx_rdy = 3000;
+    defparam rsl_inst.pport_rx_rdy = "DISABLED";
+    defparam rsl_inst.pwait_rx_rdy = 3000;
+    assign n117 = 1'bz;
+    assign n118 = 1'bz;
+    assign n119 = 1'bz;
+    assign n120 = 1'bz;
+    assign n121 = 1'bz;
+    assign n122 = 1'bz;
+    assign n123 = 1'bz;
+    assign n124 = 1'bz;
+    assign n125 = 1'bz;
+    assign n126 = 1'bz;
+    assign _Z = 1'bz;
+    sgmii_channel_smi_pcssll_core sll_inst (.sli_rst(sli_rst), .sli_refclk(pll_refclki), 
+            .sli_pclk(tx_pclk), .sli_div2_rate(1'b0), .sli_div11_rate(1'b0), 
+            .sli_gear_mode(1'b0), .sli_cpri_mode({3'b000}), .sli_pcie_mode(1'b0), 
+            .slo_plol(pll_lol));
+    defparam sll_inst.PPROTOCOL = "SGMII";
+    defparam sll_inst.PLOL_SETTING = 0;
+    defparam sll_inst.PDYN_RATE_CTRL = "DISABLED";
+    defparam sll_inst.PPCIE_MAX_RATE = "2.5";
+    defparam sll_inst.PDIFF_VAL_LOCK = 19;
+    defparam sll_inst.PDIFF_VAL_UNLOCK = 39;
+    defparam sll_inst.PPCLK_TC = 65536;
+    defparam sll_inst.PDIFF_DIV11_VAL_LOCK = 0;
+    defparam sll_inst.PDIFF_DIV11_VAL_UNLOCK = 0;
+    defparam sll_inst.PPCLK_DIV11_TC = 0;
+    
+endmodule
+
+
+

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs_softlogic.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs_softlogic.v
new file mode 100644 (file)
index 0000000..37a1f5b
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs_softlogic.v
@@ -0,0 +1,2003 @@
+
+
+//   ===========================================================================
+//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
+//   ---------------------------------------------------------------------------
+//   Copyright (c) 2016 by Lattice Semiconductor Corporation
+//   ALL RIGHTS RESERVED
+//   ------------------------------------------------------------------
+//
+//   Permission:
+//
+//      Lattice SG Pte. Ltd. grants permission to use this code
+//      pursuant to the terms of the Lattice Reference Design License Agreement.
+//
+//
+//   Disclaimer:
+//
+//      This VHDL or Verilog source code is intended as a design reference
+//      which illustrates how these types of functions can be implemented.
+//      It is the user's responsibility to verify their design for
+//      consistency and functionality through the use of formal
+//      verification methods.  Lattice provides no warranty
+//      regarding the use or functionality of this code.
+//
+//   ---------------------------------------------------------------------------
+//
+//                  Lattice SG Pte. Ltd.
+//                  101 Thomson Road, United Square #07-02
+//                  Singapore 307591
+//
+//
+//                  TEL: 1-800-Lattice (USA and Canada)
+//                       +65-6631-2000 (Singapore)
+//                       +1-503-268-8001 (other locations)
+//
+//                  web: http://www.latticesemi.com/
+//                  email: techsupport@latticesemi.com
+//
+//   ---------------------------------------------------------------------------
+//
+// =============================================================================
+//                         FILE DETAILS
+// Project               : RSL- Reset Sequence Logic
+// File                  : rsl_core.v
+// Title                 : Top-level file for RSL
+// Dependencies          : 1.
+//                       : 2.
+// Description           :
+// =============================================================================
+//                        REVISION HISTORY
+// Version               : 1.0
+// Author(s)             : BM
+// Mod. Date             : October 28, 2013
+// Changes Made          : Initial Creation
+// -----------------------------------------------------------------------------
+// Version               : 1.1
+// Author(s)             : BM
+// Mod. Date             : November 06, 2013
+// Changes Made          : Tx/Rx separation, ready port code exclusion
+// -----------------------------------------------------------------------------
+// Version               : 1.2
+// Author(s)             : BM
+// Mod. Date             : June 13, 2014
+// Changes Made          : Updated Rx PCS reset method
+// -----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
+// Version               : 1.3
+// Author(s)             : UA
+// Mod. Date             : Dec 19, 2014
+// Changes Made          : Added new parameter fro PCIE
+// -----------------------------------------------------------------------------
+// Version               : 1.31
+// Author(s)             : BM/UM
+// Mod. Date             : Feb 23, 2016
+// Changes Made          : Behavior of rx_rdy output modified. The output rx_rdy
+//                         and the rx_rdy wait counter are reset to zero on
+//                         LOL or LOS. Reverted back the counter value change for PCIE.
+// -----------------------------------------------------------------------------
+// Version               : 1.4
+// Author(s)             : EB
+// Mod. Date:            : March 21, 2017
+// Changes Made          :
+// -----------------------------------------------------------------------------
+// Version               : 1.5
+// Author(s)             : ES
+// Mod. Date:            : May 8, 2017
+// Changes Made          : Implemented common RSL behaviour as proposed by BM.
+// =============================================================================
+
+`timescale 1ns/10ps
+
+module sgmii_channel_smi_pcsrsl_core (
+      // ------------ Inputs
+      // Common
+      rui_rst,               // Active high reset for the RSL module
+      rui_serdes_rst_dual_c, // SERDES macro reset user command
+      rui_rst_dual_c,        // PCS dual reset user command
+      rui_rsl_disable,       // Active high signal that disables all reset outputs of RSL
+      // Tx
+      rui_tx_ref_clk,        // Tx reference clock
+      rui_tx_serdes_rst_c,   // Tx SERDES reset user command
+      rui_tx_pcs_rst_c,      // Tx lane reset user command
+      rdi_pll_lol,           // Tx PLL Loss of Lock status input from the SERDES
+      // Rx
+      rui_rx_ref_clk,        // Rx reference clock
+      rui_rx_serdes_rst_c,   // SERDES Receive channel reset user command
+      rui_rx_pcs_rst_c,      // Rx lane reset user command
+      rdi_rx_los_low_s,      // Receive loss of signal status input from SERDES
+      rdi_rx_cdr_lol_s,      // Receive CDR loss of lock status input from SERDES
+
+      // ------------ Outputs
+      // Common
+      rdo_serdes_rst_dual_c, // SERDES macro reset command output
+      rdo_rst_dual_c,        // PCS dual reset command output
+      // Tx
+      ruo_tx_rdy,            // Tx lane ready status output
+      rdo_tx_serdes_rst_c,   // SERDES Tx reset command output
+      rdo_tx_pcs_rst_c,      // PCS Tx lane reset command output
+      // Rx
+      ruo_rx_rdy,            // Rx lane ready status output
+      rdo_rx_serdes_rst_c,   // SERDES Rx channel reset command output
+      rdo_rx_pcs_rst_c       // PCS Rx lane reset command output
+      );
+
+// ------------ Module parameters
+`ifdef NUM_CHANNELS
+   parameter pnum_channels = `NUM_CHANNELS;    // 1,2,4
+`else
+   parameter pnum_channels = 1;
+`endif
+
+`ifdef PCIE
+   parameter pprotocol    = "PCIE";
+`else
+   parameter pprotocol    = "";
+`endif
+
+`ifdef RX_ONLY
+   parameter pserdes_mode    = "RX ONLY";
+`else
+   `ifdef TX_ONLY
+      parameter pserdes_mode = "TX ONLY";
+   `else
+      parameter pserdes_mode = "RX AND TX";
+   `endif
+`endif
+
+`ifdef PORT_TX_RDY
+   parameter pport_tx_rdy = "ENABLED";
+`else
+   parameter pport_tx_rdy = "DISABLED";
+`endif
+
+`ifdef WAIT_TX_RDY
+   parameter pwait_tx_rdy = `WAIT_TX_RDY;
+`else
+   parameter pwait_tx_rdy = 3000;
+`endif
+
+`ifdef PORT_RX_RDY
+   parameter pport_rx_rdy = "ENABLED";
+`else
+   parameter pport_rx_rdy = "DISABLED";
+`endif
+
+`ifdef WAIT_RX_RDY
+   parameter pwait_rx_rdy = `WAIT_RX_RDY;
+`else
+   parameter pwait_rx_rdy = 3000;
+`endif
+
+// ------------ Local parameters
+   localparam wa_num_cycles      = 1024;
+   localparam dac_num_cycles     = 3;
+   localparam lreset_pwidth      = 3;      // reset pulse width-1, default=4-1=3
+   localparam lwait_b4_trst      = 781250; // 5ms wait with worst-case Fmax=156 MHz
+   localparam lwait_b4_trst_s    = 781;    // for simulation
+   localparam lplol_cnt_width    = 20;     // width for lwait_b4_trst
+   localparam lwait_after_plol0  = 4;
+   localparam lwait_b4_rrst      = 180224; // total calibration time
+   localparam lrrst_wait_width   = 20;
+   localparam lwait_after_rrst   = 800000; // For CPRI- unused
+   localparam lwait_b4_rrst_s    = 460;    // wait cycles provided by design team
+   localparam lrlol_cnt_width    = 19;     // width for lwait_b4_rrst
+   localparam lwait_after_lols   = (16384 * dac_num_cycles) + wa_num_cycles;  // 16384 cycles * dac_num_cycles + 1024 cycles
+   localparam lwait_after_lols_s = 150;    // wait cycles provided by design team
+   localparam llols_cnt_width    = 18;     // lols count width
+   localparam lrdb_max           = 15;     // maximum debounce count
+   localparam ltxr_wait_width    = 12;     // width of tx ready wait counter
+   localparam lrxr_wait_width    = 12;     // width of tx ready wait counter
+
+// ------------ input ports
+   input                         rui_rst;
+   input                         rui_serdes_rst_dual_c;
+   input                         rui_rst_dual_c;
+   input                         rui_rsl_disable;
+
+   input                         rui_tx_ref_clk;
+   input                         rui_tx_serdes_rst_c;
+   input  [3:0]                  rui_tx_pcs_rst_c;
+   input                         rdi_pll_lol;
+
+   input                         rui_rx_ref_clk;
+   input  [3:0]                  rui_rx_serdes_rst_c;
+   input  [3:0]                  rui_rx_pcs_rst_c;
+   input  [3:0]                  rdi_rx_los_low_s;
+   input  [3:0]                  rdi_rx_cdr_lol_s;
+
+// ------------ output ports
+   output                        rdo_serdes_rst_dual_c;
+   output                        rdo_rst_dual_c;
+
+   output                        ruo_tx_rdy;
+   output                        rdo_tx_serdes_rst_c;
+   output [3:0]                  rdo_tx_pcs_rst_c;
+
+   output                        ruo_rx_rdy;
+   output [3:0]                  rdo_rx_serdes_rst_c;
+   output [3:0]                  rdo_rx_pcs_rst_c;
+
+// ------------ Internal registers and wires
+   // inputs
+   wire                          rui_rst;
+   wire                          rui_serdes_rst_dual_c;
+   wire                          rui_rst_dual_c;
+   wire                          rui_rsl_disable;
+   wire                          rui_tx_ref_clk;
+   wire                          rui_tx_serdes_rst_c;
+   wire   [3:0]                  rui_tx_pcs_rst_c;
+   wire                          rdi_pll_lol;
+   wire                          rui_rx_ref_clk;
+   wire   [3:0]                  rui_rx_serdes_rst_c;
+   wire   [3:0]                  rui_rx_pcs_rst_c;
+   wire   [3:0]                  rdi_rx_los_low_s;
+   wire   [3:0]                  rdi_rx_cdr_lol_s;
+
+   // outputs
+   wire                          rdo_serdes_rst_dual_c;
+   wire                          rdo_rst_dual_c;
+   wire                          ruo_tx_rdy;
+   wire                          rdo_tx_serdes_rst_c;
+   wire   [3:0]                  rdo_tx_pcs_rst_c;
+   wire                          ruo_rx_rdy;
+   wire   [3:0]                  rdo_rx_serdes_rst_c;
+   wire   [3:0]                  rdo_rx_pcs_rst_c;
+
+   // internal signals
+   // common
+   wire                          rsl_enable;
+   wire   [lplol_cnt_width-1:0]  wait_b4_trst;
+   wire   [lrlol_cnt_width-1:0]  wait_b4_rrst;
+   wire   [llols_cnt_width-1:0]  wait_after_lols;
+   reg                           pll_lol_p1;
+   reg                           pll_lol_p2;
+   reg                           pll_lol_p3;
+   // ------------ Tx
+   // rdo_tx_serdes_rst_c
+   reg    [lplol_cnt_width-1:0]  plol_cnt;
+   wire                          plol_cnt_tc;
+
+   reg    [2:0]                  txs_cnt;
+   reg                           txs_rst;
+   wire                          txs_cnt_tc;
+   // rdo_tx_pcs_rst_c
+   wire                          plol_fedge;
+   wire                          plol_redge;
+   reg                           waita_plol0;
+   reg    [2:0]                  plol0_cnt;
+   wire                          plol0_cnt_tc;
+   reg    [2:0]                  txp_cnt;
+   reg                           txp_rst;
+   wire                          txp_cnt_tc;
+   // ruo_tx_rdy
+   wire                          dual_or_serd_rst;
+   wire                          tx_any_pcs_rst;
+   wire                          tx_any_rst;
+   reg                           txsr_appd /* synthesis syn_keep=1 */;
+   reg                           txdpr_appd;
+   reg    [pnum_channels-1:0]    txpr_appd;
+   reg                           txr_wt_en;
+   reg    [ltxr_wait_width-1:0]  txr_wt_cnt;
+   wire                          txr_wt_tc;
+   reg                           ruo_tx_rdyr;
+
+   // ------------ Rx
+   wire                          comb_rlos;
+   wire                          comb_rlol;
+   //wire                          rlols;
+   wire                          rx_all_well;
+
+   //reg                           rlols_p1;
+   //reg                           rlols_p2;
+   //reg                           rlols_p3;
+
+   reg                           rlol_p1;
+   reg                           rlol_p2;
+   reg                           rlol_p3;
+   reg                           rlos_p1;
+   reg                           rlos_p2;
+   reg                           rlos_p3;
+
+   //reg    [3:0]                  rdb_cnt;
+   //wire                          rdb_cnt_max;
+   //wire                          rdb_cnt_zero;
+   //reg                           rlols_db;
+   //reg                           rlols_db_p1;
+
+   reg    [3:0]                  rlol_db_cnt;
+   wire                          rlol_db_cnt_max;
+   wire                          rlol_db_cnt_zero;
+   reg                           rlol_db;
+   reg                                  rlol_db_p1;
+
+   reg    [3:0]                  rlos_db_cnt;
+   wire                          rlos_db_cnt_max;
+   wire                          rlos_db_cnt_zero;
+   reg                           rlos_db;
+   reg                                  rlos_db_p1;
+
+   // rdo_rx_serdes_rst_c
+   reg    [lrlol_cnt_width-1:0]  rlol1_cnt;
+   wire                          rlol1_cnt_tc;
+   reg    [2:0]                  rxs_cnt;
+   reg                           rxs_rst;
+   wire                          rxs_cnt_tc;
+   reg    [lrrst_wait_width-1:0] rrst_cnt;
+   wire                          rrst_cnt_tc;
+   reg                           rrst_wait;
+   // rdo_rx_pcs_rst_c
+   //wire                          rlols_fedge;
+   //wire                          rlols_redge;
+   wire                          rlol_fedge;
+   wire                          rlol_redge;
+   wire                          rlos_fedge;
+   wire                          rlos_redge;
+
+   reg                           wait_calib;
+   reg                           waita_rlols0;
+   reg    [llols_cnt_width-1:0]  rlols0_cnt;
+   wire                          rlols0_cnt_tc;
+   reg    [2:0]                  rxp_cnt;
+   reg                           rxp_rst;
+   wire                          rxp_cnt_tc;
+
+   wire                          rx_any_serd_rst;
+   reg    [llols_cnt_width-1:0]  rlolsz_cnt;
+   wire                          rlolsz_cnt_tc;
+   reg [2:0]                    rxp_cnt2;
+   reg                           rxp_rst2;
+   wire                          rxp_cnt2_tc;
+   reg [15:0]                    data_loop_b_cnt;
+   reg                           data_loop_b;
+   wire                          data_loop_b_tc;
+
+   // ruo_rx_rdy
+   reg    [pnum_channels-1:0]    rxsr_appd;
+   reg    [pnum_channels-1:0]    rxpr_appd;
+   reg                           rxsdr_appd /* synthesis syn_keep=1 */;
+   reg                           rxdpr_appd;
+   wire                          rxsdr_or_sr_appd;
+   wire                          dual_or_rserd_rst;
+   wire                          rx_any_pcs_rst;
+   wire                          rx_any_rst;
+   reg                           rxr_wt_en;
+   reg    [lrxr_wait_width-1:0]  rxr_wt_cnt;
+   wire                          rxr_wt_tc;
+   reg                           ruo_rx_rdyr;
+
+// ==================================================================
+//                          Start of code
+// ==================================================================
+   assign rsl_enable = ~rui_rsl_disable;
+
+// ------------ rdo_serdes_rst_dual_c
+   assign rdo_serdes_rst_dual_c = (rui_rst&rsl_enable) | rui_serdes_rst_dual_c;
+
+// ------------ rdo_rst_dual_c
+   assign rdo_rst_dual_c = rui_rst_dual_c;
+
+// ------------ Setting counter values for RSL_SIM_MODE
+   `ifdef RSL_SIM_MODE
+      assign wait_b4_trst    = lwait_b4_trst_s;
+      assign wait_b4_rrst    = lwait_b4_rrst_s;
+      assign wait_after_lols = lwait_after_lols_s;
+   `else
+      assign wait_b4_trst    = lwait_b4_trst;
+      assign wait_b4_rrst    = lwait_b4_rrst;
+      assign wait_after_lols = lwait_after_lols;
+   `endif
+
+// ==================================================================
+//                                 Tx
+// ==================================================================
+   generate
+   if((pserdes_mode=="RX AND TX")||(pserdes_mode=="TX ONLY")) begin
+
+// ------------ Synchronizing pll_lol to the tx clock
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) begin
+         pll_lol_p1 <= 1'd0;
+         pll_lol_p2 <= 1'd0;
+         pll_lol_p3 <= 1'd0;
+      end
+      else begin
+         pll_lol_p1 <= rdi_pll_lol;
+         pll_lol_p2 <= pll_lol_p1;
+         pll_lol_p3 <= pll_lol_p2;
+      end
+   end
+
+// ------------ rdo_tx_serdes_rst_c
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         plol_cnt    <= 'd0;
+      else if((pll_lol_p2==0)||(plol_cnt_tc==1)||(rdo_tx_serdes_rst_c==1))
+         plol_cnt    <= 'd0;
+      else
+         plol_cnt    <= plol_cnt+1;
+   end
+   assign plol_cnt_tc = (plol_cnt==wait_b4_trst)?1'b1:1'b0;
+
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) begin
+         txs_cnt  <= 'd0;   // tx serdes reset pulse count
+         txs_rst  <= 1'b0;  // tx serdes reset
+      end
+      else if(plol_cnt_tc==1)
+         txs_rst  <= 1'b1;
+      else if(txs_cnt_tc==1) begin
+         txs_cnt  <= 'd0;
+         txs_rst  <= 1'b0;
+      end
+      else if(txs_rst==1)
+         txs_cnt  <= txs_cnt+1;
+   end
+   assign txs_cnt_tc = (txs_cnt==lreset_pwidth)?1'b1:1'b0;
+
+   assign rdo_tx_serdes_rst_c = (rsl_enable&txs_rst)| rui_tx_serdes_rst_c;
+
+// ------------ rdo_tx_pcs_rst_c
+   assign plol_fedge = ~pll_lol_p2 & pll_lol_p3;
+   assign plol_redge = pll_lol_p2 & ~pll_lol_p3;
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         waita_plol0  <= 1'd0;
+      else if(plol_fedge==1'b1)
+         waita_plol0  <= 1'b1;
+      else if((plol0_cnt_tc==1)||(plol_redge==1))
+         waita_plol0  <= 1'd0;
+   end
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         plol0_cnt    <= 'd0;
+      else if((pll_lol_p2==1)||(plol0_cnt_tc==1))
+         plol0_cnt    <= 'd0;
+      else if(waita_plol0==1'b1)
+         plol0_cnt    <= plol0_cnt+1;
+   end
+   assign plol0_cnt_tc = (plol0_cnt==lwait_after_plol0)?1'b1:1'b0;
+
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) begin
+         txp_cnt  <= 'd0;   // tx serdes reset pulse count
+         txp_rst  <= 1'b0;  // tx serdes reset
+      end
+      else if(plol0_cnt_tc==1)
+         txp_rst  <= 1'b1;
+      else if(txp_cnt_tc==1) begin
+         txp_cnt  <= 'd0;
+         txp_rst  <= 1'b0;
+      end
+      else if(txp_rst==1)
+         txp_cnt  <= txp_cnt+1;
+   end
+   assign txp_cnt_tc = (txp_cnt==lreset_pwidth)?1'b1:1'b0;
+
+   genvar i;
+   for(i=0;i<pnum_channels;i=i+1) begin : ifor
+      assign rdo_tx_pcs_rst_c[i] = (rsl_enable&txp_rst)| rui_tx_pcs_rst_c[i];
+   end
+   if(pnum_channels==1)
+      assign rdo_tx_pcs_rst_c[3:1] = 3'b000;
+   else if(pnum_channels==2)
+      assign rdo_tx_pcs_rst_c[3:2] = 2'b00;
+
+   // ------------ ruo_tx_rdy
+   if(pport_tx_rdy=="ENABLED") begin
+   assign dual_or_serd_rst = rdo_serdes_rst_dual_c|rdo_tx_serdes_rst_c;
+   assign tx_any_pcs_rst = rdo_rst_dual_c|(|rdo_tx_pcs_rst_c[pnum_channels-1:0]);
+   assign tx_any_rst = dual_or_serd_rst | tx_any_pcs_rst;
+
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         txsr_appd <= 1'b1; // tx serdes reset applied
+      else if(dual_or_serd_rst==1)
+         txsr_appd <= 1'b1;
+   end
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         txdpr_appd <= 1'b0; // tx dual (pcs) reset applied
+      else if(pll_lol_p2|rdo_serdes_rst_dual_c|rdo_tx_serdes_rst_c)
+         txdpr_appd <= 1'b0;
+      else if(rdo_rst_dual_c==1)
+         txdpr_appd <= 1'b1;
+   end
+
+   genvar m;
+   for(m=0;m<pnum_channels;m=m+1) begin :mfor
+      always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         txpr_appd[m] <= 1'b0; // tx pcs reset applied
+      else if(pll_lol_p2|rdo_serdes_rst_dual_c|rdo_tx_serdes_rst_c)
+         txpr_appd[m] <= 1'b0;
+      else if(txsr_appd&(rdo_tx_pcs_rst_c[m]|txdpr_appd))
+         txpr_appd[m] <= 1'b1;
+      end
+   end
+
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         txr_wt_en  <= 0;  // tx ready wait counter enable
+      else if((txr_wt_tc==1)||(dual_or_serd_rst==1))
+         txr_wt_en  <= 0;
+      else if((~ruo_tx_rdyr)&(~pll_lol_p2)&(&txpr_appd))
+         txr_wt_en  <= 1;
+   end
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         txr_wt_cnt  <= 'd0;  // tx ready wait count
+      else if((txr_wt_tc==1)||(tx_any_rst==1))
+         txr_wt_cnt  <= 'd0;
+      else if(txr_wt_en==1)
+         txr_wt_cnt  <= txr_wt_cnt+1;
+   end
+   assign txr_wt_tc = (txr_wt_cnt==pwait_tx_rdy)?1'b1:1'b0;
+
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         ruo_tx_rdyr <= 1'b0; // tx serdes reset applied
+      else if((tx_any_rst==1)||(pll_lol_p2==1))
+         ruo_tx_rdyr <= 1'b0;
+      else if(txr_wt_tc==1)
+         ruo_tx_rdyr <= 1'b1;
+   end
+   assign ruo_tx_rdy = ruo_tx_rdyr;
+   end         // if pport_tx_rdy
+   else
+      assign ruo_tx_rdy = 1'b0;
+   end         // generate if(Rx and Tx) or (Tx only)
+   else begin  // generate else (Rx only)
+      assign rdo_tx_serdes_rst_c = 1'b0;
+      assign rdo_tx_pcs_rst_c = 4'd0;
+      assign ruo_tx_rdy = 1'b0;
+   end
+   endgenerate
+
+// ==================================================================
+//                                 Rx
+// ==================================================================
+   generate
+   if((pserdes_mode=="RX AND TX")||(pserdes_mode=="RX ONLY")) begin
+   assign comb_rlos = |rdi_rx_los_low_s[pnum_channels-1:0];
+   assign comb_rlol = |rdi_rx_cdr_lol_s[pnum_channels-1:0];
+   //assign rlols     = comb_rlos|comb_rlol;
+
+   // ------------ Synchronizing rlols to the rx ref clock
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) begin
+        //rlols_p1    <= 1'd0;
+        //rlols_p2    <= 1'd0;
+        //rlols_p3    <= 1'd0;
+        //rlols_db_p1 <= 1'd1;
+
+        rlol_p1     <= 1'd0;
+        rlol_p2     <= 1'd0;
+        rlol_p3     <= 1'd0;
+        rlol_db_p1  <= 1'd1;
+
+        rlos_p1    <= 1'd0;
+        rlos_p2    <= 1'd0;
+        rlos_p3    <= 1'd0;
+        rlos_db_p1 <= 1'd1;
+      end
+      else begin
+        //rlols_p1    <= rlols;
+        //rlols_p2    <= rlols_p1;
+        //rlols_p3    <= rlols_p2;
+        //rlols_db_p1 <= rlols_db;
+
+        rlol_p1     <= comb_rlol;
+        rlol_p2     <= rlol_p1;
+        rlol_p3     <= rlol_p2;
+       rlol_db_p1  <= rlol_db;
+
+        rlos_p1    <= comb_rlos;
+        rlos_p2    <= rlos_p1;
+        rlos_p3    <= rlos_p2;
+        rlos_db_p1 <= rlos_db;
+      end
+   end
+   assign rx_all_well = ~rlol_db && ~rlos_db;
+
+//******************************************************************************
+// [ES:05.03.17] Unused registers for clean-up
+//------------------------------------------------------------------------------
+// ------------ Debouncing rlols
+//   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+//      if(rui_rst==1'b1) rdb_cnt  <= lrdb_max;
+//      else if(rlols_p2==1) begin
+//         if(!rdb_cnt_max) rdb_cnt <= rdb_cnt+1;
+//      end
+//      else if(!rdb_cnt_zero) rdb_cnt <= rdb_cnt-1;
+//   end
+//   assign rdb_cnt_max  = (rdb_cnt==lrdb_max);
+//   assign rdb_cnt_zero = (rdb_cnt==0);
+//   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+//      if(rui_rst==1'b1) rlols_db <= 1;
+//      else if(rdb_cnt_max)  rlols_db <= 1;
+//      else if(rdb_cnt_zero) rlols_db <= 0;
+//   end
+//******************************************************************************
+
+// ------------ Debouncing rlol
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) rlol_db_cnt  <= lrdb_max;
+      else if(rlol_p2==1) begin
+         if(!rlol_db_cnt_max) rlol_db_cnt <= rlol_db_cnt+1;
+      end
+      else if(!rlol_db_cnt_zero) rlol_db_cnt <= rlol_db_cnt-1;
+   end
+   assign rlol_db_cnt_max  = (rlol_db_cnt==lrdb_max);
+   assign rlol_db_cnt_zero = (rlol_db_cnt==0);
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) rlol_db <= 1;
+      else if(rlol_db_cnt_max)  rlol_db <= 1;
+      else if(rlol_db_cnt_zero) rlol_db <= 0;
+   end
+
+// ------------ Debouncing rlos
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) rlos_db_cnt  <= lrdb_max;
+      else if(rlos_p2==1) begin
+         if(!rlos_db_cnt_max) rlos_db_cnt <= rlos_db_cnt+1;
+      end
+      else if(!rlos_db_cnt_zero) rlos_db_cnt <= rlos_db_cnt-1;
+   end
+   assign rlos_db_cnt_max  = (rlos_db_cnt==lrdb_max);
+   assign rlos_db_cnt_zero = (rlos_db_cnt==0);
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) rlos_db <= 1;
+      else if(rlos_db_cnt_max)  rlos_db <= 1;
+      else if(rlos_db_cnt_zero) rlos_db <= 0;
+   end
+
+// ------------ Calib time trigger
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+     if (rui_rst==1'b1) begin
+       wait_calib <= 1'd1;
+     end
+     else begin
+       if (rlol1_cnt_tc) begin
+         if (rlol_db)
+           wait_calib <= 1'd1;
+         else
+           wait_calib <= 1'd0;
+       end
+       else if (rlos_redge)
+         wait_calib <= 1'd0;
+       else if (rlos_fedge) begin
+         wait_calib <= 1'd1;
+       end
+     end
+   end
+
+   //***************************************************************************
+   // Total calibration time counter
+   // - this covers the band calibration time (256 cycles * 64) and
+   //   DAC calibration time (16384 cycles * 10 bits)
+   //---------------------------------------------------------------------------
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+     if (rui_rst==1'b1) begin
+       rlol1_cnt  <= 'd0;  // Counting when Rx LOL is 1 and Rx LOS is 0
+     end
+     else begin
+       if(rxs_rst || rlol1_cnt_tc || rlos_redge)
+         rlol1_cnt  <= 'd0;
+       else if (wait_calib)
+         rlol1_cnt <= rlol1_cnt+1;
+     end
+   end
+   assign rlol1_cnt_tc = (rlol1_cnt==wait_b4_rrst);
+
+// ------------ rdo_rx_serdes_rst_c
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+     if (rui_rst==1'b1) begin
+       rxs_cnt  <= 'd0;   // rx serdes reset pulse count
+       rxs_rst  <= 1'b0;  // rx serdes reset
+     end
+     else begin
+       if (rlos_db)
+         rxs_rst <= 1'b0;
+       else if (rlol1_cnt_tc && rlol_db)
+         rxs_rst <= 1'b1;
+       else if (rxs_cnt_tc==1) begin
+         rxs_rst  <= 1'b0;
+       end
+
+       if (rxs_cnt_tc)
+         rxs_cnt <= 'd0;
+       else
+         if (rxs_rst==1)
+           rxs_cnt <= rxs_cnt+1;
+     end
+   end
+   assign rxs_cnt_tc  = (rxs_cnt==lreset_pwidth)?1'b1:1'b0;
+
+   //***************************************************************************
+   // [ES:05.03.17] Unused logic from CPRI rrst_wait
+   //---------------------------------------------------------------------------
+   // always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+   //    if(rui_rst==1'b1)
+   //       rrst_cnt    <= 'd0;
+   //    else if(rlol1_cnt_tc)
+   //       rrst_cnt    <= 'd0;
+   //    else if(rrst_wait)
+   //       rrst_cnt    <= rrst_cnt+1;
+   // end
+   // assign rrst_cnt_tc = (rrst_cnt==lwait_after_rrst) ? 1'b1 : 1'b0;
+   // always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+   //    if(rui_rst==1'b1)
+   //       rrst_wait    <= 0;
+   //    else if(pprotocol != "CPRI")
+   //       rrst_wait    <= 0;
+   //    else if(rlol1_cnt_tc)
+   //       rrst_wait    <= 1;
+   //    else if(rrst_cnt_tc==1)
+   //       rrst_wait    <= 0;
+   // end
+   //***************************************************************************
+
+   genvar j;
+   for(j=0;j<pnum_channels;j=j+1) begin :jfor
+      assign rdo_rx_serdes_rst_c[j] = (rsl_enable&rxs_rst)| rui_rx_serdes_rst_c[j];
+   end
+   if(pnum_channels==1)
+      assign rdo_rx_serdes_rst_c[3:1] = 3'b000;
+   else if(pnum_channels==2)
+      assign rdo_rx_serdes_rst_c[3:2] = 2'b00;
+
+// ------------ rdo_rx_pcs_rst_c
+   //assign rlols_fedge = ~rlols_db & rlols_db_p1;
+   //assign rlols_redge = rlols_db & ~rlols_db_p1;
+
+   assign rlol_fedge  = ~rlol_db & rlol_db_p1;
+   assign rlol_redge  = rlol_db & ~rlol_db_p1;
+   assign rlos_fedge  = ~rlos_db & rlos_db_p1;
+   assign rlos_redge  = rlos_db & ~rlos_db_p1;
+
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if (rui_rst==1'b1) begin
+        waita_rlols0 <= 1'd0;
+      end
+      else begin
+        if ((rlos_fedge && ~rlol_db) || (rlol_fedge && ~rlos_db))
+          waita_rlols0 <= 1'b1;
+        else if (rlos_redge || rlol_redge)
+          waita_rlols0 <= 1'd0;
+        else if (rlols0_cnt_tc==1)
+          waita_rlols0 <= 1'd0;
+      end
+   end
+
+   //***************************************************************************
+   // Post RLOL check before pcs_rst deassertion
+   // - allowance of 2-4 DAC calibration cycles + 1024 cycles for WA module
+   //   (word alignment).
+   //---------------------------------------------------------------------------
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+     if (rui_rst==1'b1) begin
+       rlols0_cnt <= 'd0;
+     end
+     else begin
+       if (rlol_redge || rlos_redge || rlols0_cnt_tc)
+         rlols0_cnt <= 'd0;
+       else if (waita_rlols0==1)
+         rlols0_cnt <= rlols0_cnt+1;
+     end
+   end
+   assign rlols0_cnt_tc   = (rlols0_cnt == wait_after_lols);
+   assign rx_any_serd_rst = rdo_serdes_rst_dual_c|(|rdo_rx_serdes_rst_c);
+
+   //***************************************************************************
+   // [ES:05.03.17] Unused registers for clean-up
+   //---------------------------------------------------------------------------
+   // always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+   //    if(rui_rst==1'b1)
+   //       rlolsz_cnt  <= 'd0;  // Counting when both Rx LOL is 0 and Rx LOS is 0
+   //    else if((rlol_db|rx_any_serd_rst)||(rlolsz_cnt_tc==1))
+   //       rlolsz_cnt  <= 'd0;
+   //    else if((rlolsz_cnt_tc==0)&&(rlol_db==0))
+   //       rlolsz_cnt  <= rlolsz_cnt+1;
+   // end
+   // assign rlolsz_cnt_tc = (rlolsz_cnt==wait_after_lols);
+   //***************************************************************************
+
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+     if (rui_rst==1'b1) begin
+       rxp_cnt2  <= 'd0;   // pcs serdes reset pulse count
+       rxp_rst2  <= 1'b1;  // rx pcs reset
+     end
+     else begin
+       if (rx_any_serd_rst || rlos_redge) begin
+         rxp_rst2 <= 1'b1;
+       end
+       else if (rlols0_cnt_tc) begin
+         rxp_rst2 <= 1'b0;
+       end
+       //***********************************************************************
+       // [ES:05.03.17] No need for pulse width
+       //-----------------------------------------------------------------------
+       // else if(rxp_cnt2_tc==1) begin
+       //   rxp_cnt2  <= 'd0;
+       //   rxp_rst2  <= 1'b0;
+       // end
+       //***********************************************************************
+       // [ES:05.03.17] No need for pulse width
+       //-----------------------------------------------------------------------
+       // else if (rxp_rst2==1)
+       //   rxp_cnt2 <= rxp_cnt2+1;
+       //***********************************************************************
+     end // else: !if(rui_rst==1'b1)
+   end // always @ (posedge rui_rx_ref_clk or posedge rui_rst)
+   //assign rxp_cnt2_tc = (rxp_cnt2==lreset_pwidth)?1'b1:1'b0;
+
+   //***************************************************************************
+   // [ES:05.03.17] No need for pulse width
+   //---------------------------------------------------------------------------
+   //else begin
+   //   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+   //      if(rui_rst==1'b1)
+   //         rxp_rst2  <= 1'b1;  // rx pcs reset
+   //      else if(rx_any_serd_rst)
+   //         rxp_rst2  <= 1'b1;
+   //      else if(rlolsz_cnt_tc==1)
+   //         rxp_rst2  <= 1'b0;
+   //   end
+   //end
+   //***************************************************************************
+
+   genvar k;
+   for(k=0;k<pnum_channels;k=k+1) begin: kfor
+      assign rdo_rx_pcs_rst_c[k] = (rsl_enable&rxp_rst2)| rui_rx_pcs_rst_c[k];
+   end
+   if(pnum_channels==1)
+      assign rdo_rx_pcs_rst_c[3:1] = 3'b000;
+   else if(pnum_channels==2)
+      assign rdo_rx_pcs_rst_c[3:2] = 2'b00;
+
+// ------------ ruo_rx_rdy
+   if(pport_rx_rdy=="ENABLED") begin
+   assign dual_or_rserd_rst = rdo_serdes_rst_dual_c|(|rdo_rx_serdes_rst_c[pnum_channels-1:0]);
+   assign rx_any_pcs_rst = rdo_rst_dual_c|(|rdo_rx_pcs_rst_c[pnum_channels-1:0]);
+   assign rx_any_rst = dual_or_rserd_rst | rx_any_pcs_rst;
+
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         rxsdr_appd <= 1'b1;  // Serdes dual reset (macro reset) applied
+      else if(rdo_serdes_rst_dual_c==1)
+         rxsdr_appd <= 1'b1;
+   end
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         rxdpr_appd <= 1'b0;  // Rx dual PCS reset (dual reset) applied
+      else if(~rx_all_well|dual_or_rserd_rst)
+         rxdpr_appd <= 1'b0;
+      else if(rdo_rst_dual_c==1)
+         rxdpr_appd <= 1'b1;
+   end
+
+   genvar l;
+   for(l=0;l<pnum_channels;l=l+1) begin : lfor
+      always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+         if(rui_rst==1'b1)
+            rxsr_appd[l] <= 1'b0; // rx serdes reset applied
+         else if(rdo_rx_serdes_rst_c[l]==1)
+            rxsr_appd[l] <= 1'b1;
+      end
+      always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         rxpr_appd[l] <= 1'b0; // rx pcs reset applied
+      else if(rdi_rx_los_low_s[l]|rdi_rx_cdr_lol_s[l]|rdo_serdes_rst_dual_c|rdo_rx_serdes_rst_c[l])
+         rxpr_appd[l] <= 1'b0;
+      else if(rxsdr_or_sr_appd&(~rx_all_well)&rdo_rx_pcs_rst_c[l])
+         rxpr_appd[l] <= 1'b1;
+      end
+   end
+
+   assign rxsdr_or_sr_appd = rxsdr_appd|(&rxsr_appd);
+
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         rxr_wt_en  <= 0;  // rx ready wait counter enable
+      //else if((rxr_wt_tc==1)||(dual_or_rserd_rst==1))
+      else if((rxr_wt_tc==1)||(dual_or_rserd_rst==1)||(rx_all_well==0)) // BM, 2/4/16
+         rxr_wt_en  <= 0;
+      else if(~ruo_rx_rdyr&rx_all_well&((&rxpr_appd)|rxdpr_appd))
+         rxr_wt_en  <= 1;
+   end
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         rxr_wt_cnt  <= 'd0;  // rx ready wait count
+      //else if((rxr_wt_tc==1)||(rx_any_rst==1))
+      else if((rxr_wt_tc==1)||(rx_any_rst==1)||(rx_all_well==0)) // BM, 2/4/16
+         rxr_wt_cnt  <= 'd0;
+      else if(rxr_wt_en==1)
+         rxr_wt_cnt  <= rxr_wt_cnt+1;
+   end
+   assign rxr_wt_tc = (rxr_wt_cnt==pwait_rx_rdy)?1'b1:1'b0;
+
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         ruo_rx_rdyr <= 1'b0; // rx serdes reset applied
+      else if((rx_any_rst==1)||(rx_all_well==0))
+         ruo_rx_rdyr <= 1'b0;
+      else if(rxr_wt_tc==1)
+         ruo_rx_rdyr <= 1'b1;
+   end
+   assign ruo_rx_rdy = ruo_rx_rdyr;
+   end         // if pport_rx_rdy
+   else
+      assign ruo_rx_rdy = 1'b0;
+   end // if ((pserdes_mode=="RX AND TX")||(pserdes_mode=="RX ONLY"))
+
+   else begin  // generate else (Tx only)
+      assign rdo_rx_serdes_rst_c = 4'd0;
+      assign rdo_rx_pcs_rst_c = 4'd0;
+      assign ruo_rx_rdy = 1'b0;
+   end // else: !if((pserdes_mode=="RX AND TX")||(pserdes_mode=="RX ONLY"))
+
+   endgenerate
+
+endmodule
+
+
+//   ===========================================================================
+//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
+//   ---------------------------------------------------------------------------
+//   Copyright (c) 2015 by Lattice Semiconductor Corporation
+//   ALL RIGHTS RESERVED 
+//   ------------------------------------------------------------------
+//
+//   Permission:
+//
+//      Lattice SG Pte. Ltd. grants permission to use this code
+//      pursuant to the terms of the Lattice Reference Design License Agreement. 
+//
+//
+//   Disclaimer:
+//
+//      This VHDL or Verilog source code is intended as a design reference
+//      which illustrates how these types of functions can be implemented.
+//      It is the user's responsibility to verify their design for
+//      consistency and functionality through the use of formal
+//      verification methods.  Lattice provides no warranty
+//      regarding the use or functionality of this code.
+//
+//   ---------------------------------------------------------------------------
+//
+//                  Lattice SG Pte. Ltd.
+//                  101 Thomson Road, United Square #07-02 
+//                  Singapore 307591
+//
+//
+//                  TEL: 1-800-Lattice (USA and Canada)
+//                       +65-6631-2000 (Singapore)
+//                       +1-503-268-8001 (other locations)
+//
+//                  web: http://www.latticesemi.com/
+//                  email: techsupport@latticesemi.com
+//
+//   ---------------------------------------------------------------------------
+//
+// =============================================================================
+//                         FILE DETAILS         
+// Project               : SLL - Soft Loss Of Lock(LOL) Logic
+// File                  : sll_core.v
+// Title                 : Top-level file for SLL 
+// Dependencies          : 1.
+//                       : 2.
+// Description           : 
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.0
+// Author(s)             : AV
+// Mod. Date             : March 2, 2015
+// Changes Made          : Initial Creation
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.1
+// Author(s)             : AV
+// Mod. Date             : June 8, 2015
+// Changes Made          : Following updates were made 
+//                       : 1. Changed all the PLOL status logic and FSM to run
+//                       :    on sli_refclk. 
+//                       : 2. Added the HB logic for presence of tx_pclk 
+//                       : 3. Changed the lparam assignment scheme for 
+//                       :    simulation purposes. 
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.2
+// Author(s)             : AV
+// Mod. Date             : June 24, 2015
+// Changes Made          : Updated the gearing logic for SDI dynamic rate change
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.3
+// Author(s)             : AV
+// Mod. Date             : July 14, 2015
+// Changes Made          : Added the logic for dynamic rate change in CPRI
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.4
+// Author(s)             : AV
+// Mod. Date             : August 21, 2015
+// Changes Made          : Added the logic for dynamic rate change of 5G CPRI & 
+//                         PCIe.
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.5
+// Author(s)             : ES/EB
+// Mod. Date             : March 21, 2017
+// Changes Made          : 1. Added pdiff_sync signal to syncrhonize pcount_diff 
+//                       :    to sli_refclk.
+//                       : 2. Updated terminal count logic for PCIe 5G
+//                       : 3. Modified checking of pcount_diff in SLL state
+//                       :    machine to cover actual count
+//                       :    (from 16-bits to 22-bits)
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.6
+// Author(s)             : ES
+// Mod. Date             : April 19, 2017
+// Changes Made          : 1. Added registered lock and unlock signal from
+//                            pdiff_sync to totally decouple pcount_diff from
+//                            SLL state machine.
+//                       : 2. Modified LPCLK_TC_4 to 1:1 clock ratio when CPRI
+//                            is operating @ 4.9125Gbps data rate.
+// =============================================================================
+`timescale 1ns/10ps
+
+module sgmii_channel_smi_pcssll_core ( 
+  //Reset and Clock inputs
+  sli_rst,         //Active high asynchronous reset input
+  sli_refclk,      //Refclk input to the Tx PLL
+  sli_pclk,        //Tx pclk output from the PCS
+  
+  //Control inputs
+  sli_div2_rate,   //Divide by 2 control; 0 - Full rate; 1 - Half rate
+  sli_div11_rate,  //Divide by 11 control; 0 - Full rate; 1 - Div by 11
+  sli_gear_mode,   //Gear mode control for PCS; 0 - 8/10; 1- 16/20
+  sli_cpri_mode,   //Mode of operation specific to CPRI protocol
+  sli_pcie_mode,   //Mode of operation specific to PCIe mode (2.5G or 5G)
+  
+  //LOL Output
+  slo_plol         //Tx PLL Loss of Lock output to the user logic
+  );
+  
+// Inputs
+input       sli_rst;
+input       sli_refclk;
+input       sli_pclk;
+input       sli_div2_rate;
+input       sli_div11_rate;
+input       sli_gear_mode;
+input [2:0] sli_cpri_mode;
+input       sli_pcie_mode;
+
+// Outputs
+output      slo_plol;
+
+
+// Parameters
+parameter PPROTOCOL              = "PCIE";     //Protocol selected by the User
+parameter PLOL_SETTING           = 0;          //PLL LOL setting. Possible values are 0,1,2,3
+parameter PDYN_RATE_CTRL         = "DISABLED"; //PCS Dynamic Rate control
+parameter PPCIE_MAX_RATE         = "2.5";      //PCIe max data rate
+parameter PDIFF_VAL_LOCK         = 20;         //Differential count value for Lock
+parameter PDIFF_VAL_UNLOCK       = 39;         //Differential count value for Unlock
+parameter PPCLK_TC               = 65535;      //Terminal count value for counter running on sli_pclk
+parameter PDIFF_DIV11_VAL_LOCK   = 3;          //Differential count value for Lock for SDI Div11
+parameter PDIFF_DIV11_VAL_UNLOCK = 3;          //Differential count value for Unlock for SDI Div11
+parameter PPCLK_DIV11_TC         = 2383;       //Terminal count value (SDI Div11) for counter running on sli_pclk
+
+
+// Local Parameters
+localparam [1:0]  LPLL_LOSS_ST         = 2'b00;       //PLL Loss state
+localparam [1:0]  LPLL_PRELOSS_ST      = 2'b01;       //PLL Pre-Loss state
+localparam [1:0]  LPLL_PRELOCK_ST      = 2'b10;       //PLL Pre-Lock state
+localparam [1:0]  LPLL_LOCK_ST         = 2'b11;       //PLL Lock state
+`ifdef RSL_SIM_MODE
+localparam [15:0] LRCLK_TC             = 16'd63;   //Terminal count value for counter running on sli_refclk
+`else
+localparam [15:0] LRCLK_TC             = 16'd65535;   //Terminal count value for counter running on sli_refclk
+`endif
+localparam [15:0] LRCLK_TC_PUL_WIDTH   = 16'd50;      //Pulse width for the Refclk terminal count pulse
+localparam [7:0]  LHB_WAIT_CNT         = 8'd255;      //Wait count for the Heartbeat signal
+
+// Local Parameters related to the CPRI dynamic modes
+// Terminal count values for the four CPRI modes
+localparam LPCLK_TC_0 = 32768;
+localparam LPCLK_TC_1 = 65536;
+localparam LPCLK_TC_2 = 131072;
+localparam LPCLK_TC_3 = 163840;
+localparam LPCLK_TC_4 = 65536;
+
+// Lock values count values for the four CPRI modes and four PLOL settings (4x5)
+// CPRI rate mode 0                CPRI rate mode 1                   CPRI rate mode 2                    CPRI rate mode 3                     CPRI rate mode 4
+localparam LPDIFF_LOCK_00 = 9;     localparam LPDIFF_LOCK_10 = 19;    localparam LPDIFF_LOCK_20 = 39;     localparam LPDIFF_LOCK_30 = 49;      localparam LPDIFF_LOCK_40 = 19;
+localparam LPDIFF_LOCK_01 = 9;     localparam LPDIFF_LOCK_11 = 19;    localparam LPDIFF_LOCK_21 = 39;     localparam LPDIFF_LOCK_31 = 49;      localparam LPDIFF_LOCK_41 = 19;
+localparam LPDIFF_LOCK_02 = 49;    localparam LPDIFF_LOCK_12 = 98;    localparam LPDIFF_LOCK_22 = 196;    localparam LPDIFF_LOCK_32 = 245;     localparam LPDIFF_LOCK_42 = 98;
+localparam LPDIFF_LOCK_03 = 131;   localparam LPDIFF_LOCK_13 = 262;   localparam LPDIFF_LOCK_23 = 524;    localparam LPDIFF_LOCK_33 = 655;     localparam LPDIFF_LOCK_43 = 262;
+
+// Unlock values count values for the four CPRI modes and four PLOL settings (4x5)
+// CPRI rate mode 0                  CPRI rate mode 1                      CPRI rate mode 2                       CPRI rate mode 3                         CPRI rate mode 4
+localparam LPDIFF_UNLOCK_00 = 19;    localparam LPDIFF_UNLOCK_10 = 39;     localparam LPDIFF_UNLOCK_20 = 78;      localparam LPDIFF_UNLOCK_30 = 98;        localparam LPDIFF_UNLOCK_40 = 39;
+localparam LPDIFF_UNLOCK_01 = 65;    localparam LPDIFF_UNLOCK_11 = 131;    localparam LPDIFF_UNLOCK_21 = 262;     localparam LPDIFF_UNLOCK_31 = 327;       localparam LPDIFF_UNLOCK_41 = 131;
+localparam LPDIFF_UNLOCK_02 = 72;    localparam LPDIFF_UNLOCK_12 = 144;    localparam LPDIFF_UNLOCK_22 = 288;     localparam LPDIFF_UNLOCK_32 = 360;       localparam LPDIFF_UNLOCK_42 = 144;
+localparam LPDIFF_UNLOCK_03 = 196;   localparam LPDIFF_UNLOCK_13 = 393;    localparam LPDIFF_UNLOCK_23 = 786;     localparam LPDIFF_UNLOCK_33 = 983;       localparam LPDIFF_UNLOCK_43 = 393;
+
+// Input and Output reg and wire declarations
+wire       sli_rst;
+wire       sli_refclk;
+wire       sli_pclk;
+wire       sli_div2_rate;
+wire       sli_div11_rate;
+wire       sli_gear_mode;
+wire [2:0] sli_cpri_mode;
+wire       sli_pcie_mode;
+wire       slo_plol;
+
+//-------------- Internal signals reg and wire declarations --------------------
+
+//Signals running on sli_refclk
+reg  [15:0] rcount;           //16-bit Counter
+reg         rtc_pul;          //Terminal count pulse
+reg         rtc_pul_p1;       //Terminal count pulse pipeline
+reg         rtc_ctrl;         //Terminal count pulse control
+
+reg  [7:0]  rhb_wait_cnt;     //Heartbeat wait counter
+
+//Heatbeat synchronization and pipeline registers
+wire        rhb_sync;
+reg         rhb_sync_p2;
+reg         rhb_sync_p1;
+
+//Pipeling registers for dynamic control mode
+wire        rgear;
+wire        rdiv2;
+wire        rdiv11;
+reg         rgear_p1;
+reg         rdiv2_p1;
+reg         rdiv11_p1;
+
+reg         rstat_pclk;        //Pclk presence/absence status
+
+reg  [21:0] rcount_tc;         //Tx_pclk terminal count register
+reg  [15:0] rdiff_comp_lock;   //Differential comparison value for Lock
+reg  [15:0] rdiff_comp_unlock; //Differential compariosn value for Unlock
+
+wire        rpcie_mode;        //PCIe mode signal synchronized to refclk
+reg         rpcie_mode_p1;     //PCIe mode pipeline register
+
+wire        rcpri_mod_ch_sync; //CPRI mode change synchronized to refclk
+reg         rcpri_mod_ch_p1;   //CPRI mode change pipeline register
+reg         rcpri_mod_ch_p2;   //CPRI mode change pipeline register
+reg         rcpri_mod_ch_st;   //CPRI mode change status
+
+reg  [1:0]  sll_state;         //Current-state register for LOL FSM
+
+reg         pll_lock;          //PLL Lock signal
+
+//Signals running on sli_pclk
+//Synchronization and pipeline registers
+wire        ppul_sync;
+reg         ppul_sync_p1;
+reg         ppul_sync_p2;
+reg         ppul_sync_p3;
+
+wire        pdiff_sync;
+reg         pdiff_sync_p1;
+   
+reg  [21:0] pcount;            //22-bit counter
+reg  [21:0] pcount_diff;       //Differential value between Tx_pclk counter and theoritical value
+
+//Heartbeat counter and heartbeat signal running on pclk
+reg  [2:0]  phb_cnt;
+reg         phb;
+
+//CPRI dynamic mode releated signals
+reg  [2:0]  pcpri_mode;
+reg         pcpri_mod_ch;
+
+//Assignment scheme changed mainly for simulation purpose
+wire [15:0] LRCLK_TC_w;
+assign LRCLK_TC_w = LRCLK_TC;
+
+reg         unlock;
+reg         lock;
+
+//Heartbeat synchronization
+sync # (.PDATA_RST_VAL(0)) phb_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (phb),
+  .data_out(rhb_sync)
+  );
+  
+  
+//Terminal count pulse synchronization
+sync # (.PDATA_RST_VAL(0)) rtc_sync_inst ( 
+  .clk     (sli_pclk),
+  .rst     (sli_rst),
+  .data_in (rtc_pul),
+  .data_out(ppul_sync)
+  );
+
+//Differential value logic update synchronization
+sync # (.PDATA_RST_VAL(0)) pdiff_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (ppul_sync),
+  .data_out(pdiff_sync)
+  );
+
+//Gear mode synchronization
+sync # (.PDATA_RST_VAL(0)) gear_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (sli_gear_mode),
+  .data_out(rgear)
+  );
+  
+//Div2 synchronization
+sync # (.PDATA_RST_VAL(0)) div2_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (sli_div2_rate),
+  .data_out(rdiv2)
+  );
+  
+//Div11 synchronization
+sync # (.PDATA_RST_VAL(0)) div11_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (sli_div11_rate),
+  .data_out(rdiv11)
+  );
+  
+//CPRI mode change synchronization
+sync # (.PDATA_RST_VAL(0)) cpri_mod_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (pcpri_mod_ch),
+  .data_out(rcpri_mod_ch_sync)
+  );
+  
+//PCIe mode change synchronization
+sync # (.PDATA_RST_VAL(0)) pcie_mod_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (sli_pcie_mode),
+  .data_out(rpcie_mode)
+  );  
+
+// =============================================================================
+// Synchronized Lock/Unlock signals
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    unlock        <= 1'b0;
+    lock          <= 1'b0;
+    pdiff_sync_p1 <= 1'b0;
+  end
+  else begin
+    pdiff_sync_p1 <= pdiff_sync;
+    if (unlock) begin
+      unlock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : unlock;
+    end
+    else begin
+      unlock <= pdiff_sync ? (pcount_diff[21:0] > {6'd0, rdiff_comp_unlock}) : 1'b0;
+    end
+    if (lock) begin
+      lock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : lock;
+    end
+    else begin
+      lock <= pdiff_sync ? (pcount_diff[21:0] <= {6'd0, rdiff_comp_lock}) : 1'b0;
+    end
+  end
+end
+
+// =============================================================================
+// Refclk Counter, pulse generation logic and Heartbeat monitor logic
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rcount     <= 16'd0;
+    rtc_pul    <= 1'b0;
+    rtc_ctrl   <= 1'b0;
+    rtc_pul_p1 <= 1'b0;
+  end
+  else begin
+    //Counter logic
+    if ((rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin
+      if (rtc_ctrl == 1'b1) begin
+        rcount <= LRCLK_TC_PUL_WIDTH;
+      end  
+    end
+    else begin
+      if (rcount != LRCLK_TC_w) begin
+        rcount <= rcount + 1;
+      end
+      else begin
+        rcount <= 16'd0;   
+      end
+    end
+    
+    //Pulse control logic
+    if (rcount == LRCLK_TC_w - 1) begin
+      rtc_ctrl <= 1'b1;
+    end
+    
+    //Pulse Generation logic
+    if (rtc_ctrl == 1'b1) begin
+      if ((rcount == LRCLK_TC_w) || (rcount < LRCLK_TC_PUL_WIDTH)) begin
+        rtc_pul <= 1'b1;
+    end  
+      else begin
+        rtc_pul <= 1'b0;  
+      end
+    end
+    
+    rtc_pul_p1 <= rtc_pul;  
+  end  
+end
+
+
+// =============================================================================
+// Heartbeat synchronization & monitor logic and Dynamic mode pipeline logic 
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rhb_sync_p1     <= 1'b0;
+    rhb_sync_p2     <= 1'b0;
+    rhb_wait_cnt    <= 8'd0;
+    rstat_pclk      <= 1'b0;
+    rgear_p1        <= 1'b0;
+    rdiv2_p1        <= 1'b0;
+    rdiv11_p1       <= 1'b0;
+    rcpri_mod_ch_p1 <= 1'b0;
+    rcpri_mod_ch_p2 <= 1'b0;
+    rcpri_mod_ch_st <= 1'b0;
+    rpcie_mode_p1   <= 1'b0;
+    
+  end
+  else begin
+    //Pipeline stages for the Heartbeat
+    rhb_sync_p1 <= rhb_sync;
+    rhb_sync_p2 <= rhb_sync_p1;
+    
+    //Pipeline stages of the Dynamic rate control signals
+    rgear_p1  <= rgear;
+    rdiv2_p1  <= rdiv2;
+    rdiv11_p1 <= rdiv11;
+    
+    //Pipeline stage for PCIe mode
+    rpcie_mode_p1 <= rpcie_mode;
+    
+    //Pipeline stage for CPRI mode change
+    rcpri_mod_ch_p1 <= rcpri_mod_ch_sync;
+    rcpri_mod_ch_p2 <= rcpri_mod_ch_p1;
+    
+    //CPRI mode change status logic
+    if (rcpri_mod_ch_p1^rcpri_mod_ch_sync == 1'b1) begin
+      rcpri_mod_ch_st <= 1'b1;
+    end 
+    
+    //Heartbeat wait counter and monitor logic
+    if (rtc_ctrl == 1'b1) begin
+      if (rhb_sync_p1 == 1'b1 && rhb_sync_p2 == 1'b0) begin
+        rhb_wait_cnt <= 8'd0;
+        rstat_pclk   <= 1'b1;
+      end
+      else if (rhb_wait_cnt == LHB_WAIT_CNT) begin
+        rhb_wait_cnt <= 8'd0;
+        rstat_pclk   <= 1'b0;
+      end
+      else begin
+        rhb_wait_cnt <= rhb_wait_cnt + 1;
+      end
+    end
+  end  
+end
+
+
+// =============================================================================
+// Pipleline registers for the TC pulse and CPRI mode change logic
+// =============================================================================
+always @(posedge sli_pclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    ppul_sync_p1 <= 1'b0;
+    ppul_sync_p2 <= 1'b0;
+    ppul_sync_p3 <= 1'b0;
+    pcpri_mode   <= 3'b0;
+    pcpri_mod_ch <= 1'b0;
+  end
+  else begin
+    ppul_sync_p1 <= ppul_sync;
+    ppul_sync_p2 <= ppul_sync_p1;
+    ppul_sync_p3 <= ppul_sync_p2;
+    
+    //CPRI mode change logic
+    pcpri_mode <= sli_cpri_mode;
+    
+    if (pcpri_mode != sli_cpri_mode) begin
+      pcpri_mod_ch <= ~pcpri_mod_ch;
+    end 
+  end  
+end
+   
+
+// =============================================================================
+// Terminal count logic
+// =============================================================================
+
+//For SDI protocol with Dynamic rate control enabled
+generate
+if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "SDI")) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rcount_tc         <= 22'd0;
+    rdiff_comp_lock   <= 16'd0;
+    rdiff_comp_unlock <= 16'd0;
+  end
+  else begin
+    //Terminal count logic
+    //Div by 11 is enabled
+    if (rdiv11 == 1'b1) begin
+      //Gear mode is 16/20
+      if (rgear == 1'b1) begin
+        rcount_tc         <= PPCLK_DIV11_TC;
+        rdiff_comp_lock   <= PDIFF_DIV11_VAL_LOCK;
+        rdiff_comp_unlock <= PDIFF_DIV11_VAL_UNLOCK;
+      end
+      else begin
+        rcount_tc         <= {PPCLK_DIV11_TC[20:0], 1'b0};
+        rdiff_comp_lock   <= {PDIFF_DIV11_VAL_LOCK[14:0], 1'b0};
+        rdiff_comp_unlock <= {PDIFF_DIV11_VAL_UNLOCK[14:0], 1'b0};
+      end
+    end
+    //Div by 2 is enabled
+    else if (rdiv2 == 1'b1) begin
+      //Gear mode is 16/20
+      if (rgear == 1'b1) begin
+        rcount_tc         <= {1'b0,PPCLK_TC[21:1]};
+        rdiff_comp_lock   <= {1'b0,PDIFF_VAL_LOCK[15:1]};
+        rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]};
+      end
+      else begin
+        rcount_tc         <= PPCLK_TC;
+        rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+        rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+      end
+    end
+    //Both div by 11 and div by 2 are disabled
+    else begin
+      //Gear mode is 16/20
+      if (rgear == 1'b1) begin
+        rcount_tc         <= PPCLK_TC;
+        rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+        rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+      end
+      else begin
+        rcount_tc         <= {PPCLK_TC[20:0],1'b0};
+        rdiff_comp_lock   <= {PDIFF_VAL_LOCK[14:0],1'b0};
+        rdiff_comp_unlock <= {PDIFF_VAL_UNLOCK[14:0],1'b0};
+      end
+    end
+  end  
+end
+end
+endgenerate
+
+//For G8B10B protocol with Dynamic rate control enabled
+generate
+if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "G8B10B")) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rcount_tc         <= 22'd0;
+    rdiff_comp_lock   <= 16'd0;
+    rdiff_comp_unlock <= 16'd0;
+  end
+  else begin
+    //Terminal count logic
+    //Div by 2 is enabled
+    if (rdiv2 == 1'b1) begin
+      rcount_tc         <= {1'b0,PPCLK_TC[21:1]};
+      rdiff_comp_lock   <= {1'b0,PDIFF_VAL_LOCK[15:1]};
+      rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]};
+    end
+    else begin
+      rcount_tc         <= PPCLK_TC;
+      rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+      rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+    end
+  end  
+end
+end
+endgenerate
+
+
+//For CPRI protocol with Dynamic rate control is disabled
+generate
+if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "CPRI")) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rcount_tc         <= 22'd0;
+    rdiff_comp_lock   <= 16'd0;
+    rdiff_comp_unlock <= 16'd0;
+  end
+  else begin
+    //Terminal count logic for CPRI protocol
+    //Only if there is a change in the rate mode from the default
+    if (rcpri_mod_ch_st == 1'b1) begin
+      if (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) begin
+        case(sli_cpri_mode)
+          3'd0 : begin //For 0.6Gbps
+            rcount_tc         <= LPCLK_TC_0;
+            case(PLOL_SETTING)
+              'd0 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_00;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_00;
+              end
+              
+              'd1 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_01;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_01;
+              end
+              
+              'd2 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_02;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_02;
+              end
+              
+              'd3 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_03;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_03;
+              end
+              
+              default : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_00;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_00;
+              end
+            endcase
+          end
+          
+          3'd1 : begin //For 1.2Gbps
+            rcount_tc         <= LPCLK_TC_1;
+            case(PLOL_SETTING)
+              'd0 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_10;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_10;
+              end
+              
+              'd1 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_11;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_11;
+              end
+              
+              'd2 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_12;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_12;
+              end
+              
+              'd3 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_13;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_13;
+              end
+              
+              default : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_10;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_10;
+              end
+            endcase
+          end
+          
+          3'd2 : begin //For 2.4Gbps
+            rcount_tc         <= LPCLK_TC_2;
+            case(PLOL_SETTING)
+              'd0 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_20;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_20;
+              end
+              
+              'd1 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_21;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_21;
+              end
+              
+              'd2 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_22;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_22;
+              end
+              
+              'd3 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_23;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_23;
+              end
+              
+              default : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_20;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_20;
+              end
+            endcase
+          end
+          
+          3'd3 : begin //For 3.07Gbps
+            rcount_tc         <= LPCLK_TC_3;
+            case(PLOL_SETTING)
+              'd0 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_30;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_30;
+              end
+              
+              'd1 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_31;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_31;
+              end
+              
+              'd2 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_32;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_32;
+              end
+              
+              'd3 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_33;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_33;
+              end
+            endcase
+          end    
+              
+          3'd4 : begin //For 4.9125bps
+            rcount_tc         <= LPCLK_TC_4;
+            case(PLOL_SETTING)
+              'd0 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_40;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_40;
+              end
+              
+              'd1 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_41;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_41;
+              end
+              
+              'd2 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_42;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_42;
+              end
+              
+              'd3 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_43;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_43;
+              end  
+            
+              default : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_40;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_40;
+              end
+            endcase
+          end
+        
+          default : begin
+            rcount_tc         <= LPCLK_TC_0;
+            rdiff_comp_lock   <= LPDIFF_LOCK_00;
+            rdiff_comp_unlock <= LPDIFF_UNLOCK_00;
+          end
+        endcase
+      end
+    end
+    else begin
+      //If there is no change in the CPRI rate mode from default
+      rcount_tc         <= PPCLK_TC;
+      rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+      rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+    end  
+  end  
+end
+end
+endgenerate
+
+//For PCIe protocol with Dynamic rate control disabled
+generate
+if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "PCIE")) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rcount_tc         <= 22'd0;
+    rdiff_comp_lock   <= 16'd0;
+    rdiff_comp_unlock <= 16'd0;
+  end
+  else begin
+    //Terminal count logic
+    if (PPCIE_MAX_RATE == "2.5") begin
+      //2.5G mode is enabled
+      rcount_tc         <= PPCLK_TC;
+      rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+      rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+    end
+    else begin
+      //5G mode is enabled
+      if (rpcie_mode == 1'b1) begin
+        rcount_tc         <= PPCLK_TC;
+        rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+        rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+      end
+      else begin
+        //2.5G mode is enabled
+        rcount_tc         <= {1'b0,PPCLK_TC[21:1]};
+        rdiff_comp_lock   <= {1'b0,PDIFF_VAL_LOCK[15:1]};
+        rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]};
+      end 
+    end          
+  end  
+end
+end
+endgenerate
+
+//For all protocols other than CPRI & PCIe
+generate
+if ((PDYN_RATE_CTRL == "DISABLED") && ((PPROTOCOL != "CPRI") && (PPROTOCOL != "PCIE"))) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rcount_tc         <= 22'd0;
+    rdiff_comp_lock   <= 16'd0;
+    rdiff_comp_unlock <= 16'd0;
+  end
+  else begin
+    //Terminal count logic for all protocols other than CPRI & PCIe
+    rcount_tc         <= PPCLK_TC;
+    rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+    rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+  end  
+end
+end
+endgenerate
+
+
+// =============================================================================
+// Tx_pclk counter, Heartbeat and Differential value logic
+// =============================================================================
+always @(posedge sli_pclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    pcount      <= 22'd0;
+    pcount_diff <= 22'd65535;
+    phb_cnt     <= 3'd0;
+    phb         <= 1'b0;
+  end
+  else begin
+    //Counter logic
+    if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin
+      pcount <= 22'd0;
+    end
+    else begin
+      pcount <= pcount + 1;
+    end
+    
+    //Heartbeat logic
+    phb_cnt <= phb_cnt + 1;
+    
+    if ((phb_cnt < 3'd4) && (phb_cnt >= 3'd0)) begin
+      phb <= 1'b1;
+    end  
+    else begin
+      phb <= 1'b0;  
+    end 
+    
+    //Differential value logic
+    if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin
+      pcount_diff <= rcount_tc + ~(pcount) + 1;
+    end  
+    else if (ppul_sync_p2 == 1'b1 && ppul_sync_p3 == 1'b0) begin
+      if (pcount_diff[21] == 1'b1) begin
+        pcount_diff <= ~(pcount_diff) + 1;
+      end
+    end
+  end  
+end
+
+
+// =============================================================================
+// State transition logic for SLL FSM
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    sll_state <= LPLL_LOSS_ST; 
+  end
+  else begin
+    //Reasons to declare an immediate loss - Absence of Tx_pclk, Dynamic rate change for SDI or CPRI
+    if ((rstat_pclk == 1'b0) || (rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || 
+    (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin
+      sll_state <= LPLL_LOSS_ST;
+    end
+    else begin  
+      case(sll_state)
+        LPLL_LOSS_ST : begin
+          if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin
+            if (unlock) begin
+              sll_state <= LPLL_LOSS_ST;
+            end
+            else if (lock) begin
+              if (PLOL_SETTING == 2'd0) begin
+                sll_state <= LPLL_PRELOCK_ST;
+              end
+              else begin
+                sll_state <= LPLL_LOCK_ST;
+              end
+            end
+          end
+        end
+        
+        LPLL_LOCK_ST : begin
+          if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin
+            if (lock) begin
+              sll_state <= LPLL_LOCK_ST;
+            end
+            else begin
+              if (PLOL_SETTING == 2'd0) begin
+                sll_state <= LPLL_LOSS_ST;
+              end
+              else begin
+                sll_state <= LPLL_PRELOSS_ST;
+              end
+            end
+          end
+        end
+        
+        LPLL_PRELOCK_ST : begin
+          if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin
+            if (lock) begin
+              sll_state <= LPLL_LOCK_ST;
+            end
+            else begin
+              sll_state <= LPLL_PRELOSS_ST;
+            end
+          end
+        end
+        
+        LPLL_PRELOSS_ST : begin
+          if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin
+            if (unlock) begin
+              sll_state <= LPLL_PRELOSS_ST;
+            end
+            else if (lock) begin
+              sll_state <= LPLL_LOCK_ST;
+            end
+          end
+        end
+        
+        default: begin
+          sll_state <= LPLL_LOSS_ST;
+        end
+      endcase
+    end  
+  end  
+end
+
+
+// =============================================================================
+// Logic for Tx PLL Lock
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    pll_lock <= 1'b0; 
+  end
+  else begin
+    case(sll_state)
+      LPLL_LOSS_ST : begin
+        pll_lock <= 1'b0;
+      end
+      
+      LPLL_LOCK_ST : begin
+        pll_lock <= 1'b1;
+      end
+      
+      LPLL_PRELOSS_ST : begin
+        pll_lock <= 1'b0;
+      end
+      
+      default: begin
+        pll_lock <= 1'b0;
+      end
+    endcase
+  end  
+end
+
+assign slo_plol = ~(pll_lock);
+
+endmodule  
+
+
+//   ===========================================================================
+//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
+//   ---------------------------------------------------------------------------
+//   Copyright (c) 2015 by Lattice Semiconductor Corporation
+//   ALL RIGHTS RESERVED 
+//   ------------------------------------------------------------------
+//
+//   Permission:
+//
+//      Lattice SG Pte. Ltd. grants permission to use this code
+//      pursuant to the terms of the Lattice Reference Design License Agreement. 
+//
+//
+//   Disclaimer:
+//
+//      This VHDL or Verilog source code is intended as a design reference
+//      which illustrates how these types of functions can be implemented.
+//      It is the user's responsibility to verify their design for
+//      consistency and functionality through the use of formal
+//      verification methods.  Lattice provides no warranty
+//      regarding the use or functionality of this code.
+//
+//   ---------------------------------------------------------------------------
+//
+//                  Lattice SG Pte. Ltd.
+//                  101 Thomson Road, United Square #07-02 
+//                  Singapore 307591
+//
+//
+//                  TEL: 1-800-Lattice (USA and Canada)
+//                       +65-6631-2000 (Singapore)
+//                       +1-503-268-8001 (other locations)
+//
+//                  web: http://www.latticesemi.com/
+//                  email: techsupport@latticesemi.com
+//
+//   ---------------------------------------------------------------------------
+//
+// =============================================================================
+//                         FILE DETAILS
+// Project               : Synchronizer Logic
+// File                  : sync.v
+// Title                 : Synchronizer module
+// Description           : 
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.0
+// Author(s)             : AV
+// Mod. Date             : July 7, 2015
+// Changes Made          : Initial Creation
+// -----------------------------------------------------------------------------
+// Version               : 1.1
+// Author(s)             : EB
+// Mod. Date             : March 21, 2017
+// Changes Made          : 
+// =============================================================================
+
+`ifndef PCS_SYNC_MODULE
+`define PCS_SYNC_MODULE
+module sync ( 
+  clk,
+  rst,
+  data_in,
+  data_out
+  );
+  
+input  clk;                  //Clock in which the async data needs to be synchronized to
+input  rst;                  //Active high reset
+input  data_in;              //Asynchronous data
+output data_out;             //Synchronized data
+
+parameter PDATA_RST_VAL = 0; //Reset value for the registers
+
+reg data_p1;
+reg data_p2;
+
+// =============================================================================
+// Synchronization logic
+// =============================================================================
+always @(posedge clk or posedge rst) begin
+  if (rst == 1'b1) begin
+    data_p1 <= PDATA_RST_VAL;
+    data_p2 <= PDATA_RST_VAL; 
+  end
+  else begin
+    data_p1 <= data_in;
+    data_p2 <= data_p1;
+  end  
+end
+
+assign data_out = data_p2; 
+
+endmodule    
+`endif
+

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/models/ecp5um/pmi_fifo_dc/pmi_fifo_dc.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/models/ecp5um/pmi_fifo_dc/pmi_fifo_dc.v
new file mode 100644 (file)
index 0000000..01ea781
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/models/ecp5um/pmi_fifo_dc/pmi_fifo_dc.v
@@ -0,0 +1,629 @@
+// --------------------------------------------------------------------
+// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
+// --------------------------------------------------------------------
+// Copyright (c) 2005-2010 by Lattice Semiconductor Corporation
+// --------------------------------------------------------------------
+//
+//
+//                     Lattice Semiconductor Corporation
+//                     5555 NE Foore Court
+//                     Hillsboro, OR 97214
+//                     U.S.A.
+//
+//                     TEL: 1-800-Lattice  (USA and Canada)
+//                          1-408-826-6000 (other locations)
+//
+//                     web: http://www.latticesemi.com/
+//                     email: techsupport@latticesemi.com
+//
+// --------------------------------------------------------------------
+//
+// Simulation Library File for FIFO Dual Clock PMI Block
+//
+// Parameter Definition
+//Name                        Value                                    Default
+/*
+------------------------------------------------------------------------------
+pmi_data_width_w            <integer>                                      18
+pmi_data_width_r            <integer>                                      18
+pmi_data_depth_w            <integer>                                     256
+pmi_data_depth_r            <integer>                                     256
+pmi_full_flag               <integer>                                     256
+pmi_empty_flag              <integer>                                       0
+pmi_almost_full_flag        <integer>                                     252
+pmi_almost_empty_flag       <integer>                                       4
+pmi_regmode               "reg"|"noreg"|"outreg"|"outreg_rden"           "reg"
+pmi_resetmode             "async"|"sync"                               "async"
+pmi_family  "EC"|"XP"|"XP2"|"SC"|"SCM"|"ECP"|"ECP2"|"ECP2M"|"ECP3"|"XO"|"XO2"|"LPTM"  "EC"
+pmi_implementation         "EBR"|"LUT"                                   "EBR"
+------------------------------------------------------------------------------
+WARNING: Do not change the default parameters in this model. Parameter 
+redefinition must be done using defparam or in-line (#) paramater 
+redefinition in a top level file that instantiates this model.
+
+NOTE: The purpose of RPReset (Read Point Reset) is to indicate a retransmit, 
+and it is more commonly used in "packetized" communications. In this 
+application, the user must keep careful track of when the packet is written 
+into or read from fifo.
+
+RPReset does not affect the write port, nor any data that has been written 
+into the fifo.  However, using RPReset imposes two restrictions on the write 
+operation:
+
+  - Packet size must not exceed the maximum FIFO depth.
+
+  - The write pointer should be reset (using Reset) before writing each new 
+    packet to replace the previous one.
+
+ 
+These restrictions prevent the read and write pointers from recirculating 
+around the address space and back to location 0 at any time during packet 
+storage.  Such a pointer wraparound would lose the packet's original starting
+point from which to retransmit.  These restrictions are only required when 
+using the retransmit function.
+
+*/
+// fpga\verilog\pkg\versclibs\data\pmi\pmi_fifo_dc.v 1.26 07-NOV-2012 18:51:50 PYAO
+
+`timescale 1ns / 1ps
+module pmi_fifo_dc #(
+                    parameter pmi_data_width_w = 18,
+                    parameter pmi_data_width_r = 18,
+                    parameter pmi_data_depth_w = 256,
+                    parameter pmi_data_depth_r = 256,
+                    parameter pmi_full_flag = 256,
+                    parameter pmi_empty_flag = 0,
+                    parameter pmi_almost_full_flag = 252,
+                    parameter pmi_almost_empty_flag = 4,
+                    parameter pmi_regmode = "reg",
+                    parameter pmi_resetmode = "async",
+                    parameter pmi_family = "EC" ,
+                    parameter module_type = "pmi_fifo_dc",
+                         parameter pmi_implementation = "EBR"
+                    )
+
+  (input  [pmi_data_width_w-1:0] Data,
+   input WrClock,
+   input RdClock,
+   input WrEn,
+   input RdEn,
+   input Reset,
+   input RPReset,
+   output reg [pmi_data_width_r-1:0] Q = 0,
+   output Empty,
+   output Full,
+   output AlmostEmpty,
+   output AlmostFull)/*synthesis syn_black_box */;
+
+//pragma translate_off
+   localparam pmi_array_size_w = pmi_data_width_w * pmi_data_depth_w;
+   localparam pmi_array_size_r = pmi_data_width_r * pmi_data_depth_r;
+
+   localparam r_w_ratio = pmi_data_width_w/pmi_data_width_r;
+   localparam w_r_ratio = pmi_data_width_r/pmi_data_width_w;
+   
+//   tri1       GSR_sig = GSR_INST.GSRNET;
+//   tri1       PUR_sig = PUR_INST.PURNET;
+//   reg                             SRN;
+   wire RST_sig, RPRST_sig;
+
+   reg [pmi_array_size_w-1:0] fifo_mem = {pmi_array_size_w{1'b0}};
+
+   reg [pmi_data_width_w-1:0] Data_reg = 0;
+   reg [pmi_data_width_w-1:0] Data_reg_sync = 0;
+   reg [pmi_data_width_w-1:0] Data_reg_async = 0;
+   reg [pmi_data_width_r-1:0] Q_reg = 0;
+   reg [pmi_data_width_r-1:0] Q_reg_sync = 0;
+   reg [pmi_data_width_r-1:0] Q_reg_async = 0;
+   reg [pmi_data_width_r-1:0] Q_node = 0;
+   reg [pmi_data_width_r-1:0] Q_int = 0;
+
+   localparam pmi_addr_width_w = 
+               (pmi_data_depth_w == 2) ? 1 : (pmi_data_depth_w == 4) ? 2 : (pmi_data_depth_w == 8) ? 3 :
+               (pmi_data_depth_w == 16) ? 4 : (pmi_data_depth_w == 32) ? 5 : (pmi_data_depth_w == 64) ? 6 :
+               (pmi_data_depth_w == 128) ? 7 : (pmi_data_depth_w == 256) ? 8 : (pmi_data_depth_w == 512) ? 9 :
+               (pmi_data_depth_w == 1024) ? 10 : (pmi_data_depth_w == 2048) ? 11 : (pmi_data_depth_w == 4096) ? 12 :
+               (pmi_data_depth_w == 8192) ? 13 : (pmi_data_depth_w == 16384) ? 14 : (pmi_data_depth_w == 32768) ? 15 :
+               (pmi_data_depth_w == 65536) ? 16 : 17 ;
+
+   localparam pmi_addr_width_r = 
+               (pmi_data_depth_r == 2) ? 1 : (pmi_data_depth_r == 4) ? 2 : (pmi_data_depth_r == 8) ? 3 :
+               (pmi_data_depth_r == 16) ? 4 : (pmi_data_depth_r == 32) ? 5 : (pmi_data_depth_r == 64) ? 6 :
+               (pmi_data_depth_r == 128) ? 7 : (pmi_data_depth_r == 256) ? 8 : (pmi_data_depth_r == 512) ? 9 :
+               (pmi_data_depth_r == 1024) ? 10 : (pmi_data_depth_r == 2048) ? 11 : (pmi_data_depth_r == 4096) ? 12 :
+               (pmi_data_depth_r == 8192) ? 13 : (pmi_data_depth_r == 16384) ? 14 : (pmi_data_depth_r == 32768) ? 15 :
+               (pmi_data_depth_r == 65536) ? 16 : 17 ;
+
+   localparam bit_ptr_extra_width_w = 
+               (pmi_data_width_w == 1) ? 0 : (pmi_data_width_w == 2) ? 1 : (pmi_data_width_w <= 4) ? 2 :
+               (pmi_data_width_w <= 8) ? 3: (pmi_data_width_w <= 16) ? 4 : (pmi_data_width_w <= 32) ? 5 :
+               (pmi_data_width_w <= 64) ? 6 : (pmi_data_width_w <= 128) ? 7 : 8;
+
+   localparam bit_ptr_width = pmi_addr_width_w + bit_ptr_extra_width_w;
+
+   reg [pmi_addr_width_w:0] wr_pointer = {(pmi_addr_width_w+1){1'b1}};
+   reg [pmi_addr_width_r:0] rd_pointer = {(pmi_addr_width_r+1){1'b1}};
+   reg [pmi_addr_width_w:0] wr_pointer_sync = {(pmi_addr_width_w+1){1'b1}};
+   reg [pmi_addr_width_r:0] rd_pointer_sync = {(pmi_addr_width_r+1){1'b1}};
+   reg [pmi_addr_width_w:0] wr_pointer_sync1 = {(pmi_addr_width_w+1){1'b1}}, wr_pointer_sync2 = {(pmi_addr_width_w+1){1'b1}};
+   reg [pmi_addr_width_r:0] rd_pointer_sync1 = {(pmi_addr_width_r+1){1'b1}}, rd_pointer_sync2 = {(pmi_addr_width_r+1){1'b1}};
+
+   reg [bit_ptr_width:0] wr_pointer_lsb = 0, rd_pointer_lsb = 0;
+   reg [bit_ptr_width:0] wr_pointer_bit = 0, wr_pointer_sync_bit = 0;
+   reg [bit_ptr_width:0] rd_pointer_bit = 0, rd_pointer_sync_bit = 0;
+
+   wire [pmi_addr_width_w:0] wr_pointer_1 = wr_pointer + 1;
+   wire [pmi_addr_width_r:0] rd_pointer_1 = rd_pointer + 1;
+
+   reg [pmi_addr_width_w:0] wr_pointer_var, wr_pointer_sync_var;
+   reg [pmi_addr_width_r:0] rd_pointer_var, rd_pointer_sync_var;
+
+   wire [bit_ptr_width:0] fifo_words_used_syncr, fifo_words_used_syncw;
+   wire [bit_ptr_width:0] ae_ptr, empty_ptr, af_ptr, full_ptr;
+
+   integer i, j;
+
+   reg RPRST_reg1 = 0;
+
+
+//For SC/M
+//Task to check if proper fifo depth is set.
+   task sc_depth_check (input integer depth_w, depth_r);
+      begin
+        if ((depth_w != 2) && (depth_w != 4) && (depth_w != 8) && (depth_w != 16) && (depth_w != 32) && (depth_w != 64)&& (depth_w != 128) && (depth_w != 256) && (depth_w!= 512) && (depth_w != 1024) && (depth_w != 2048) && (depth_w != 4096) && (depth_w != 8192) && (depth_w != 16384) && (depth_w != 32768) && (depth_w != 65536) && (depth_w != 131072))
+          begin
+             $display("\nError! Invalid Write Port Depth!");
+             $display("\nValid values are: 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536, 131072.");
+             $stop;
+          end
+        
+        if ((depth_r != 2) && (depth_r != 4) && (depth_r != 8) && (depth_r != 16) && (depth_r != 32) && (depth_r != 64)&& (depth_r != 128) && (depth_r != 256) && (depth_r!= 512) && (depth_r != 1024) && (depth_r != 2048) && (depth_r != 4096) && (depth_r != 8192) && (depth_r != 16384) && (depth_r != 32768) && (depth_r != 65536) && (depth_r != 131072))
+          begin
+             $display("\nError! Invalid Read Port Depth!");
+             $display("\nValid values are: 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536, 131072.");
+             $stop;
+          end
+      end
+   endtask // sc_depth_check
+
+//For XO
+//Task to check if proper fifo depth is set.
+   task xo_depth_check (input integer depth_w, depth_r);
+      begin
+        if ((depth_w != 2) && (depth_w != 4) && (depth_w != 8) && (depth_w != 16) && (depth_w != 32) && (depth_w != 64)&& (depth_w != 128) && (depth_w != 256) && (depth_w!= 512) && (depth_w != 1024) && (depth_w != 2048) && (depth_w != 4096) && (depth_w != 8192) && (depth_w != 16384))
+          begin
+             $display("\nError! Invalid Write Port Depth!");
+             $display("\nValid values are: 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384.");
+             $stop;
+          end
+        
+        if ((depth_r != 2) && (depth_r != 4) && (depth_r != 8) && (depth_r != 16) && (depth_r != 32) && (depth_r != 64)&& (depth_r != 128) && (depth_r != 256) && (depth_r!= 512) && (depth_r != 1024) && (depth_r != 2048) && (depth_r != 4096) && (depth_r != 8192) && (depth_r != 16384))
+          begin
+             $display("\nError! Invalid Read Port Depth!");
+             $display("\nValid values are: 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384.");
+             $stop;
+          end
+      end
+   endtask // xo_depth_check
+
+//Task to check if Depth * Width are same for read and write ports
+   task sc_array_check (input integer array_w, array_r);
+      begin
+        if (array_w != array_r)
+          begin
+             $display("\nError! Total value of (Depth * Width) must be the same for read set and write set ports.");
+             $stop;
+          end
+      end
+   endtask // sc_array_check
+   
+
+//For All Other families
+//Task to check if proper fifo depth is set.
+   task ec_depth_check (input integer depth_w, depth_r, width_w, width_r);
+   begin
+         if (depth_w > 8192 && pmi_implementation == "LUT")
+         begin
+             $display("\nError! Fifo depth is too large! Maximum Fifo depth can be 8192.");
+             $stop;
+         end
+         else if (depth_w > 65536 && (pmi_family == "EC" || pmi_family == "XP" || pmi_family == "ECP"))
+         begin
+             $display("\nError! Fifo depth is too large! Maximum Fifo depth can be 65536.");
+             $stop;
+         end
+         else if (depth_w > 131072)
+         begin
+             $display("\nError! Fifo depth is too large! Maximum Fifo depth can be 131072.");
+             $stop;
+         end
+        
+         if ((depth_w != 2) && (depth_w != 4) && (depth_w != 8) && (depth_w != 16) && (depth_w != 32) && (depth_w != 64)&& (depth_w != 128) && (depth_w != 256) && (depth_w!= 512) && (depth_w != 1024) && (depth_w != 2048) && (depth_w != 4096) && (depth_w != 8192) && (depth_w != 16384) && (depth_w != 32768) && (depth_w != 65536) && (depth_w != 131072)/* && (depth_w != 262144) && (depth_w != 524288)*/)
+         begin
+             $display("\nError! Fifo depth can only be power of 2!");
+             $stop;
+         end
+   end
+   endtask // ec_depth_check
+
+// Error Checks
+   initial begin
+      if (pmi_empty_flag != 0)
+       begin
+          $display("\nError! Empty Flag must be set to 0!");
+          $stop;
+       end
+
+      if (pmi_full_flag !== pmi_data_depth_w)
+       begin
+          $display("\nError! Full Flag must equal the total depth of the FIFO!");
+          $stop;
+       end
+
+      if ( ( ((pmi_family != "SC") && (pmi_family != "SCM") &&
+              (pmi_family != "XO") && (pmi_family != "XO2") && (pmi_family != "LPTM")) ||
+             (pmi_implementation == "LUT") ) && (pmi_resetmode == "sync") )
+       begin
+          $display("\nError! Synchronous Reset is not supported for this family or implementation!");
+          $stop;
+       end
+
+      if ( ((pmi_family == "SC") || (pmi_family == "SCM") ||
+            (pmi_family == "XO") || (pmi_family == "XO2") || (pmi_family == "LPTM")) &&
+           (pmi_implementation == "EBR") ) begin
+        sc_array_check(pmi_array_size_w, pmi_array_size_r);
+        end
+
+      if ( ((pmi_family == "SC") || (pmi_family == "SCM")) &&
+           (pmi_implementation == "EBR") ) begin
+        sc_depth_check(pmi_data_depth_w, pmi_data_depth_r);
+        end
+
+      if ( ((pmi_family == "XO") || (pmi_family == "XO2") || (pmi_family == "LPTM")) &&
+           (pmi_implementation == "EBR") ) begin
+        xo_depth_check(pmi_data_depth_w, pmi_data_depth_r);
+        end
+
+      if ( ((pmi_family != "SC") && (pmi_family != "SCM") &&
+            (pmi_family != "XO") && (pmi_family != "XO2") && (pmi_family != "LPTM")) ||
+           (pmi_implementation == "LUT") ) begin
+        ec_depth_check(pmi_data_depth_w, pmi_data_depth_r, pmi_data_width_w, pmi_data_width_r);
+      end
+
+   end // initial begin
+   
+//Following commented out code for pmi_gsr is for future compatibility
+/*   always @ (GSR_sig or PUR_sig ) begin
+    if (pmi_gsr == "enable") begin
+      SRN = GSR_sig & PUR_sig ;
+    end
+    else if (pmi_gsr == "disable")
+      SRN = PUR_sig;
+   end
+
+   not INST0  (SR1, SRN);
+   or  INST1  (RST_sig, Reset, SR1);
+   or  INST2  (RPRST_sig, RPReset, SR1);
+
+ always @(SR1 or Data)
+     begin
+       if (SR1 == 1)
+         begin
+             assign Data_reg = 0;
+             assign Q_reg = 0;
+         end
+       else
+         begin
+             deassign Data_reg;
+             deassign Q_reg;
+         end
+     end // always @ (SR1 or Data)
+*/
+   buf INST1 (RST_sig, Reset);
+   buf INST2 (RPRST_sig, RPReset);
+   
+   always @(posedge WrClock)
+     begin
+            RPRST_reg1 <= RPRST_sig;
+     end
+
+   always @(RST_sig or RPRST_sig or RPRST_reg1)
+     begin
+       if (RST_sig == 1)
+         begin
+            assign wr_pointer = {(pmi_addr_width_w+1){1'b1}};
+            assign wr_pointer_sync = {(pmi_addr_width_w+1){1'b1}};
+            assign wr_pointer_sync1 = {(pmi_addr_width_w+1){1'b1}};
+            assign wr_pointer_sync2 = {(pmi_addr_width_w+1){1'b1}};
+        assign wr_pointer_lsb = 0;
+        assign wr_pointer_bit = 0;
+        assign wr_pointer_sync_bit = 0;
+         end
+       else
+         begin
+            deassign wr_pointer;
+            deassign wr_pointer_sync;
+            deassign wr_pointer_sync1;
+            deassign wr_pointer_sync2;
+        deassign wr_pointer_lsb;
+        deassign wr_pointer_bit;
+        deassign wr_pointer_sync_bit;
+         end // else: !if(RST_sig == 1)
+       
+       if (RST_sig == 1 || RPRST_sig == 1)
+         begin
+            assign rd_pointer = {(pmi_addr_width_r+1){1'b1}};
+        assign rd_pointer_lsb = 0;
+        assign rd_pointer_bit = 0;
+         end
+       else
+         begin
+            deassign rd_pointer;
+        deassign rd_pointer_lsb;
+        deassign rd_pointer_bit;
+         end // else: !if(RPRST_sig == 1 || RST_sig == 1)
+
+       if (RPRST_reg1 == 1 || RST_sig == 1)
+         begin
+            assign rd_pointer_sync = {(pmi_addr_width_r+1){1'b1}};
+            assign rd_pointer_sync1 = {(pmi_addr_width_r+1){1'b1}};
+            assign rd_pointer_sync2 = {(pmi_addr_width_r+1){1'b1}};
+            assign rd_pointer_sync_bit = 0;
+         end
+       else
+         begin
+            deassign rd_pointer_sync;
+            deassign rd_pointer_sync1;
+            deassign rd_pointer_sync2;
+            deassign rd_pointer_sync_bit;
+         end
+     end 
+
+   //Additional Warning checks for RPRST Usage
+/*
+   always @(RPRST_sig)
+     begin
+       if (wr_pointer > pmi_data_depth_w)
+         begin
+            $display("\nWarning! Illegal Operation! RPReset is being asserted when the packet size has exceeded fifo depth!");
+            $display("\nSimulation mismatches are possible at time: %d !", $time);
+            $display("\nPlease refer to the header information of pmi_fifo_dc.v model for proper RPReset usage.");
+         end
+     end // always @ (RPRST_sig)
+*/
+
+//Asynchronous Reset
+   always @(posedge RST_sig or posedge WrClock)
+     begin
+       if (RST_sig == 1)
+         begin
+             Data_reg_async <= 0;
+         end
+       else
+         begin
+             if (WrEn == 1 && Full != 1)
+               Data_reg_async <= Data;
+         end
+     end
+
+//Synchronous Reset
+   always @(posedge WrClock)
+     begin
+       if (RST_sig == 1)
+         begin
+             Data_reg_sync <= 0;
+         end
+       else
+         begin
+             if (WrEn == 1 && Full != 1)
+               Data_reg_sync <= Data;
+         end
+     end
+
+//Choice between Async and Sync Reset   
+   always @(Data_reg_sync or Data_reg_async)
+     begin
+       if (pmi_resetmode == "async")
+          Data_reg = Data_reg_async;
+       else
+          Data_reg = Data_reg_sync;
+     end
+
+//Write and Read Pointers
+
+always @(posedge WrClock)
+   begin
+       if (WrEn == 1)
+         begin
+            if (Full != 1)
+            begin
+              wr_pointer <= wr_pointer_1;
+              wr_pointer_lsb <= (wr_pointer_1 % pmi_data_depth_w) * pmi_data_width_w;
+            end
+         end
+   end
+
+always @(posedge RdClock)
+   begin
+       if (RdEn == 1)
+         begin
+            if (Empty != 1)
+            begin
+                   rd_pointer <= rd_pointer_1;
+                   rd_pointer_lsb <= (rd_pointer_1 % pmi_data_depth_r) * pmi_data_width_r;
+            end // if (Empty != 1)
+         end // if (RdEn == 1)
+   end // always @ (posedge RdClock)
+
+
+//Synchronization Logic
+     
+//Sync Write Pointer to Rd Clock
+//Delayed by 2 clock cycles for EC based families   
+   always @(posedge RdClock)
+    if ( ((pmi_family == "SC") || (pmi_family == "SCM") ||
+          (pmi_family == "XO") || (pmi_family == "XO2") || (pmi_family == "LPTM")) &&
+         (pmi_implementation == "EBR") )
+        begin
+           wr_pointer_sync <= wr_pointer;
+        end
+    else begin
+           wr_pointer_sync1 <= wr_pointer;
+           wr_pointer_sync2 <= wr_pointer_sync1;
+           wr_pointer_sync <= wr_pointer_sync2;
+    end
+
+//Sync Read Pointer to Wr Clock
+//Delayed by 2 clock cycles for EC based families.
+//For SC and XO, rd_pointer_sync depends on the adjusted rd_pointer
+//which depends on pmi_data_depth_w and pmi_data_depth_r
+   
+   always @(posedge WrClock)
+    if ( ((pmi_family == "SC") || (pmi_family == "SCM") ||
+          (pmi_family == "XO") || (pmi_family == "XO2") || (pmi_family == "LPTM")) &&
+         (pmi_implementation == "EBR") )
+        begin
+           rd_pointer_sync <= rd_pointer;
+        end
+    else begin
+           rd_pointer_sync1 <= rd_pointer;
+           rd_pointer_sync2 <= rd_pointer_sync1;
+           rd_pointer_sync <= rd_pointer_sync2;
+    end
+
+   //Write Data into FIFO
+   always @(Data_reg, wr_pointer, wr_pointer_lsb)
+     begin
+                for (i = 0; i < pmi_data_width_w; i = i + 1)
+                  fifo_mem[wr_pointer_lsb + i] = Data_reg[i];
+     end
+
+   //Read from FIFO
+   always @(rd_pointer, rd_pointer_lsb, posedge RST_sig, posedge RPRST_sig) begin
+      if (RST_sig == 1'b1 || RPRST_sig == 1'b1)
+        Q_node = 0;
+      else if (RST_sig == 0 && RPRST_sig == 0) begin
+                 for (j = 0; j < pmi_data_width_r; j = j + 1)
+                   Q_node[j] = fifo_mem[rd_pointer_lsb + j];
+          end // if (RST_sig == 0 && RPRST_sig == 0)
+   end // always @ (rd_pointer, posedge RST_sig, posedge RPRST_sig)
+   
+             
+//Asynchronous Reset   
+   always @(posedge RST_sig or posedge RPRST_sig or posedge RdClock)
+     begin
+       if (RST_sig == 1 || RPRST_sig == 1)
+         begin
+             Q_reg_async <= 0;
+         end
+       else
+         begin
+         if (pmi_regmode == "outreg_rden")
+             begin
+             if (RdEn == 1)             //cr45303
+               Q_reg_async <= Q_node;
+             end
+             else
+         begin
+               Q_reg_async <= Q_node;
+         end
+         end
+     end
+
+//Synchronous Reset   
+   always @(posedge RdClock)
+     begin
+       if (RST_sig == 1 || RPRST_sig == 1)
+         begin
+             Q_reg_sync <= 0;
+         end
+       else
+         begin
+         if (pmi_regmode == "outreg_rden")
+         begin
+            if (RdEn == 1)             //cr45303
+               Q_reg_sync <= Q_node;
+         end
+         else
+         begin
+               Q_reg_sync <= Q_node;
+         end
+         end
+     end
+
+//Choice between Async and Sync Reset      
+   always @(Q_reg_sync or Q_reg_async)
+     begin
+       if (pmi_resetmode == "async")
+          Q_reg = Q_reg_async;
+       else
+          Q_reg = Q_reg_sync;
+     end
+   
+   always @(Q_reg or Q_node)
+     begin
+       if (pmi_regmode == "noreg")
+         begin
+             Q_int = Q_node;
+         end
+       else
+         begin
+             Q_int = Q_reg;
+         end
+     end
+   
+   always @(Q_int)
+     begin
+        Q = Q_int ;
+     end
+
+
+//Flag Generation
+
+  always @(wr_pointer)
+  begin
+     wr_pointer_var = wr_pointer + 1;
+     wr_pointer_bit <= wr_pointer_var * pmi_data_width_w;
+  end
+
+  always @(wr_pointer_sync, posedge RPRST_sig, posedge RdClock)
+  begin
+     if (RPRST_sig == 1)
+        wr_pointer_sync_bit <= 0;
+     else
+     begin
+        wr_pointer_sync_var = wr_pointer_sync + 1;
+        wr_pointer_sync_bit <= wr_pointer_sync_var * pmi_data_width_w;
+     end
+  end
+
+  always @(rd_pointer)
+  begin
+     rd_pointer_var = rd_pointer + 1;
+     rd_pointer_bit <= rd_pointer_var * pmi_data_width_r;
+  end
+
+  always @(rd_pointer_sync)
+  begin
+     rd_pointer_sync_var = rd_pointer_sync + 1;
+     rd_pointer_sync_bit <= rd_pointer_sync_var * pmi_data_width_r;
+  end
+
+  assign fifo_words_used_syncr = (wr_pointer_sync_bit < pmi_array_size_w) && (rd_pointer_bit >= pmi_array_size_w) ?
+    (wr_pointer_sync_bit + pmi_array_size_w) - (rd_pointer_bit - pmi_array_size_w) : wr_pointer_sync_bit - rd_pointer_bit;
+  assign fifo_words_used_syncw = (wr_pointer_bit < pmi_array_size_w) && (rd_pointer_sync_bit >= pmi_array_size_w) ?
+    (wr_pointer_bit + pmi_array_size_w) - (rd_pointer_sync_bit - pmi_array_size_w) : wr_pointer_bit - rd_pointer_sync_bit;
+
+  assign ae_ptr = (pmi_almost_empty_flag * pmi_data_width_r) + (pmi_data_width_r - 1);
+  assign empty_ptr = pmi_data_width_r - 1;
+  assign af_ptr = (pmi_almost_full_flag * pmi_data_width_w) - (pmi_data_width_w - 1);
+  assign full_ptr = pmi_array_size_w - (pmi_data_width_w - 1);
+
+  assign Empty = (fifo_words_used_syncr <= empty_ptr);
+  assign AlmostEmpty = (fifo_words_used_syncr <= ae_ptr);
+  assign AlmostFull = (fifo_words_used_syncw >= af_ptr);
+  assign Full = (fifo_words_used_syncw >= full_ptr);
+//pragma translate_on
+
+endmodule
+

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/readme.htm b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/readme.htm
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+</script>\r
+\r
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+</script>\r
+\r
+<script language="JavaScript"  type="text/javascript" src="whver.js">\r
+</script>\r
+\r
+<script language="javascript1.2"  type="text/javascript" src="whproxy.js">\r
+</script>\r
+\r
+<script language="javascript1.2"  type="text/javascript" src="whutils.js">\r
+</script>\r
+\r
+<script language="javascript1.2"  type="text/javascript" src="whtopic.js">\r
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+<!--\r
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+       }\r
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+\r
+       if (window.setRelStartPage)\r
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+\r
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+\r
+}\r
+else\r
+       if (window.gbIE4)\r
+               document.location.reload();\r
+//-->\r
+</script>\r
+<!--[if gte mso 9]><xml>\r
+ <o:shapedefaults v:ext="edit" spidmax="1026"/>\r
+</xml><![endif]--><!--[if gte mso 9]><xml>\r
+ <o:shapelayout v:ext="edit">\r
+  <o:idmap v:ext="edit" data="1"/>\r
+ </o:shapelayout></xml><![endif]-->\r
+</head>\r
+\r
+<!--(Body)==========================================================-->\r
+\r
+<body lang=EN-IN link=blue vlink=blue style='tab-interval:36.0pt'>\r
+\r
+<div class=WordSection1>\r
+\r
+<div style='mso-element:para-border-div;border:none;border-bottom:solid windowtext 1.0pt;\r
+mso-border-bottom-alt:solid windowtext .75pt;padding:0cm 0cm 0cm 0cm'>\r
+\r
+<p class=MsoNormal style='margin-bottom:12.0pt;border:none;mso-border-bottom-alt:\r
+solid windowtext .75pt;padding:0cm;mso-padding-alt:0cm 0cm 0cm 0cm'><b><span\r
+lang=EN-US style='font-size:24.0pt;font-family:"Verdana","sans-serif";\r
+color:#ED6F25;mso-font-kerning:18.0pt;mso-ansi-language:EN-US'>SGMII/Gb\r
+Ethernet PCS ReadMe<o:p></o:p></span></b></p>\r
+\r
+<p class=MsoNormal style='margin-bottom:12.0pt;border:none;mso-border-bottom-alt:\r
+solid windowtext .75pt;padding:0cm;mso-padding-alt:0cm 0cm 0cm 0cm'><span\r
+lang=EN-US style='color:navy;mso-ansi-language:EN-US'><o:p>&nbsp;</o:p></span></p>\r
+\r
+<p class=MsoNormal style='margin-bottom:12.0pt;border:none;mso-border-bottom-alt:\r
+solid windowtext .75pt;padding:0cm;mso-padding-alt:0cm 0cm 0cm 0cm'><b><span\r
+lang=EN-US style='font-size:18.0pt;font-family:"Arial","sans-serif";mso-ansi-language:\r
+EN-US'>General Information</span></b><span lang=EN-US style='mso-ansi-language:\r
+EN-US'><o:p></o:p></span></p>\r
+\r
+</div>\r
+\r
+<p class=MsoNormal style='margin-bottom:12.0pt'><span lang=EN-US\r
+style='mso-ansi-language:EN-US'><br>\r
+</span><b><span lang=EN-US style='font-family:"Arial","sans-serif";mso-ansi-language:\r
+EN-US'>Copyright Notice</span></b><span lang=EN-US style='mso-ansi-language:\r
+EN-US'><o:p></o:p></span></p>\r
+\r
+<table class=MsoNormalTable border=0 cellpadding=0 width="80%"\r
+ style='width:80.0%;mso-cellspacing:1.5pt;mso-yfti-tbllook:1184;mso-padding-alt:\r
+ 0cm 0cm 0cm 0cm'>\r
+ <tr style='mso-yfti-irow:0;mso-yfti-firstrow:yes;mso-yfti-lastrow:yes'>\r
+  <td style='padding:.75pt .75pt .75pt .75pt'>\r
+  <p><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Copyright\r
+  2000-2014© Lattice Semiconductor Corporation. ALL RIGHTS RESERVED. This\r
+  confidential and proprietary software may be used only as authorized by a licensing\r
+  agreement from Lattice Semiconductor Corporation. The entire notice above\r
+  must be reproduced on all authorized copies and copies may only be made to\r
+  the extent permitted by a licensing agreement from Lattice Semiconductor\r
+  Corporation.<o:p></o:p></span></p>\r
+  </td>\r
+ </tr>\r
+</table>\r
+\r
+<div style='mso-element:para-border-div;border:none;border-bottom:solid windowtext 1.0pt;\r
+mso-border-bottom-alt:solid windowtext .75pt;padding:0cm 0cm 0cm 0cm'>\r
+\r
+<p class=MsoNormal style='margin-bottom:12.0pt;border:none;mso-border-bottom-alt:\r
+solid windowtext .75pt;padding:0cm;mso-padding-alt:0cm 0cm 0cm 0cm'><span\r
+lang=EN-US style='mso-ansi-language:EN-US'><br>\r
+</span><b><span lang=EN-US style='font-size:18.0pt;font-family:"Arial","sans-serif";\r
+mso-ansi-language:EN-US'>Contacting Lattice</span></b><span lang=EN-US\r
+style='mso-ansi-language:EN-US'><o:p></o:p></span></p>\r
+\r
+</div>\r
+\r
+<p class=MsoNormal><span lang=EN-US style='mso-ansi-language:EN-US'><o:p>&nbsp;</o:p></span></p>\r
+\r
+<table class=MsoNormalTable border=1 cellspacing=0 cellpadding=0 width=450\r
+ style='width:337.5pt;mso-cellspacing:0cm;margin-left:9.0pt;border:solid silver 1.0pt;\r
+ mso-border-alt:solid silver .75pt;mso-yfti-tbllook:1184;mso-padding-alt:0cm 0cm 0cm 0cm;\r
+ border-spacing: 0px;border-spacing: 0px' x-use-null-cells>\r
+ <col class=whs6><col class=whs7>\r
+ <tr style='mso-yfti-irow:0;mso-yfti-firstrow:yes;x-cell-content-align: top'>\r
+  <td width=100 valign=top style='width:75.0pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><!--(Table)=========================================================--><span\r
+  style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Mail:<o:p></o:p></span></p>\r
+  </td>\r
+  <td width=300 valign=top style='width:225.0pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Lattice\r
+  Semiconductor Corporation<br>\r
+<st1:address w:st="on"><st1:Street w:st="on">5555 NE Moore Court</st1:Street><br>\r
+<st1:City w:st="on">Hillsboro</st1:City>, <st1:State w:st="on">OR</st1:State>\r
+   &nbsp;<st1:PostalCode w:st="on">97124</st1:PostalCode><br>\r
+<st1:country-region w:st="on">U.S.A.<u1:p></u1:p></st1:country-region></st1:address><o:p></o:p></span></p>\r
+  </td>\r
+ </tr>\r
+ <tr style='mso-yfti-irow:1;x-cell-content-align: top'>\r
+  <td width=100 valign=top style='width:75.0pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Telephone:<o:p></o:p></span></p>\r
+  </td>\r
+  <td width=300 valign=top style='width:225.0pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>1-800-Lattice\r
+  (<st1:country-region w:st="on">USA</st1:country-region> and <st1:country-region\r
+  w:st="on"><st1:place w:st="on">Canada</st1:place></st1:country-region>)<u1:p></u1:p><o:p></o:p></span></p>\r
+  </td>\r
+ </tr>\r
+ <tr style='mso-yfti-irow:2;x-cell-content-align: top'>\r
+  <td width=100 valign=top style='width:75.0pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table>&nbsp;</p>\r
+  </td>\r
+  <td width=300 valign=top style='width:225.0pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>1-503-268-8001\r
+  (other locations)<u1:p></u1:p><o:p></o:p></span></p>\r
+  </td>\r
+ </tr>\r
+ <tr style='mso-yfti-irow:3;x-cell-content-align: top'>\r
+  <td width=100 valign=top style='width:75.0pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Website:<o:p></o:p></span></p>\r
+  </td>\r
+  <td width=300 valign=top style='width:225.0pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span style='font-size:10.0pt;font-family:"Verdana","sans-serif";\r
+  color:#013C9A'><a href="http://www.latticesemi.com" target="_blank"><span\r
+  style='color:#013C9A'>http://www.latticesemi.com</span></a><u1:p></u1:p><o:p></o:p></span></p>\r
+  </td>\r
+ </tr>\r
+ <tr style='mso-yfti-irow:4;mso-yfti-lastrow:yes;x-cell-content-align: top'>\r
+  <td width=100 valign=top style='width:75.0pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>E-mail:<o:p></o:p></span></p>\r
+  </td>\r
+  <td width=300 valign=top style='width:225.0pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span style='font-size:10.0pt;font-family:"Verdana","sans-serif";\r
+  color:#013C9A'><a href="mailto:techsupport@latticesemi.com"><span\r
+  style='color:#013C9A'>techsupport@latticesemi.com</span></a><u1:p></u1:p><o:p></o:p></span></p>\r
+  </td>\r
+ </tr>\r
+</table>\r
+\r
+<p class=MsoNormal style='margin-bottom:12.0pt'><span lang=EN-US\r
+style='mso-ansi-language:EN-US'><o:p>&nbsp;</o:p></span></p>\r
+\r
+<div style='mso-element:para-border-div;border:none;border-bottom:solid windowtext 1.0pt;\r
+mso-border-bottom-alt:solid windowtext .75pt;padding:0cm 0cm 0cm 0cm'>\r
+\r
+<p class=MsoNormal style='margin-bottom:12.0pt;border:none;mso-border-bottom-alt:\r
+solid windowtext .75pt;padding:0cm;mso-padding-alt:0cm 0cm 0cm 0cm'><b><span\r
+lang=EN-US style='font-size:18.0pt;font-family:"Arial","sans-serif";mso-ansi-language:\r
+EN-US'>IP Module Information</span></b><span lang=EN-US style='mso-ansi-language:\r
+EN-US'><o:p></o:p></span></p>\r
+\r
+</div>\r
+\r
+<p class=MsoNormal style='margin-bottom:12.0pt'><span lang=EN-US\r
+style='mso-ansi-language:EN-US'><br>\r
+</span><b><span lang=EN-US style='font-family:"Arial","sans-serif";mso-ansi-language:\r
+EN-US'>About this Module</span></b><span lang=EN-US style='mso-ansi-language:\r
+EN-US'> <o:p></o:p></span></p>\r
+\r
+<table class=MsoNormalTable border=1 cellspacing=0 cellpadding=0 width=450\r
+ style='width:337.5pt;mso-cellspacing:0cm;margin-left:9.0pt;border:solid silver 1.0pt;\r
+ mso-border-alt:solid silver .75pt;mso-yfti-tbllook:1184;mso-padding-alt:0cm 0cm 0cm 0cm;\r
+ border-spacing: 0px;border-spacing: 0px' x-use-null-cells>\r
+ <col><col>\r
+ <tr style='mso-yfti-irow:0;mso-yfti-firstrow:yes;x-cell-content-align: top'>\r
+  <td width=300 valign=top style='width:225.0pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><!--(Table)=========================================================--><span\r
+  style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>IP Name:<o:p></o:p></span></p>\r
+  </td>\r
+  <td width=300 valign=top style='width:225.0pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=MsoNormal><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>SGMII/Gb\r
+  Ethernet PCS</span></p>\r
+  </td>\r
+ </tr>\r
+ <tr style='mso-yfti-irow:1;x-cell-content-align: top'>\r
+  <td width=300 valign=top style='width:225.0pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>IP\r
+  Version:<o:p></o:p></span></p>\r
+  </td>\r
+  <td width=300 valign=top style='width:225.0pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>4.1</span></p>\r
+  </td>\r
+ </tr>\r
+ <tr style='mso-yfti-irow:2;x-cell-content-align: top'>\r
+  <td width=300 valign=top style='width:225.0pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>IP\r
+  Release Date:<o:p></o:p></span></p>\r
+  </td>\r
+  <td width=300 valign=top style='width:225.0pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>June\r
+  2015</span></p>\r
+  </td>\r
+ </tr>\r
+ <tr style='mso-yfti-irow:3;mso-yfti-lastrow:yes;x-cell-content-align: top'>\r
+  <td width=300 valign=top style='width:225.0pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Target\r
+  Technology:<o:p></o:p></span></p>\r
+  </td>\r
+  <td width=300 valign=top style='width:225.0pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>LatticeECP3,ECP5UM<o:p></o:p></span></p>\r
+  </td>\r
+ </tr>\r
+</table>\r
+\r
+<p class=MsoNormal style='margin-bottom:12.0pt'><span lang=EN-US\r
+style='mso-ansi-language:EN-US'><br>\r
+</span><b><span lang=EN-US style='font-family:"Arial","sans-serif";mso-ansi-language:\r
+EN-US'>Software Requirements</span></b><span lang=EN-US style='mso-ansi-language:\r
+EN-US'><o:p></o:p></span></p>\r
+\r
+<table class=MsoNormalTable border=1 cellspacing=0 cellpadding=0 width=612\r
+ style='width:459.05pt;mso-cellspacing:0cm;margin-left:9.0pt;border:solid silver 1.0pt;\r
+ mso-border-alt:solid silver .75pt;mso-yfti-tbllook:1184;mso-padding-alt:0cm 0cm 0cm 0cm;\r
+ border-spacing: 0px;border-spacing: 0px' x-use-null-cells>\r
+ <col><col>\r
+ <tr style='mso-yfti-irow:0;mso-yfti-firstrow:yes;x-cell-content-align: top'>\r
+  <td width=221 valign=top style='width:165.85pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><!--(Table)=========================================================--><span\r
+  style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Synthesis Tools\r
+  Supported:<o:p></o:p></span></p>\r
+  </td>\r
+  <td width=391 valign=top style='width:293.2pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span class=SpellE><span style='font-size:10.0pt;font-family:\r
+  "Verdana","sans-serif"'>Synplify</span></span><span style='font-size:10.0pt;\r
+  font-family:"Verdana","sans-serif"'> Pro I-2014.03L-SP1<br>\r
+  Lattice Synthesis Engine (ECP5UM only)<br>\r
+  </>Precision RTL Synthesis 2010a_Update2.254(ECP3/Windows only)<o:p></o:p></span></p>\r
+  </td>\r
+ </tr>\r
+ <tr style='mso-yfti-irow:1;x-cell-content-align: top'>\r
+  <td width=221 valign=top style='width:165.85pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Simulation\r
+  Tools Supported:<o:p></o:p></span></p>\r
+  </td>\r
+  <td width=391 valign=top style='width:293.2pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Active-HDL\r
+  9.3SP1(Windows only)<br>\r
+  ModelSim SE 10.2c</span></p>\r
+  </td>\r
+ </tr>\r
+ <tr style='mso-yfti-irow:2;mso-yfti-lastrow:yes;x-cell-content-align: top'>\r
+  <td width=221 valign=top style='width:165.85pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Lattice\r
+  Tool Supported:<o:p></o:p></span></p>\r
+  </td>\r
+  <td width=391 valign=top style='width:293.2pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Diamond\r
+  3.5</span></p>\r
+  </td>\r
+ </tr>\r
+</table>\r
+\r
+<p><span lang=EN-US style='mso-ansi-language:EN-US'>&nbsp;<o:p></o:p></span></p>\r
+\r
+<div style='mso-element:para-border-div;border:none;border-bottom:solid windowtext 1.0pt;\r
+mso-border-bottom-alt:solid windowtext .75pt;padding:0cm 0cm 0cm 0cm'>\r
+\r
+<p class=MsoNormal style='margin-bottom:12.0pt;border:none;mso-border-bottom-alt:\r
+solid windowtext .75pt;padding:0cm;mso-padding-alt:0cm 0cm 0cm 0cm'><a\r
+name=implementing></a><b><span lang=EN-US style='font-size:18.0pt;font-family:\r
+"Arial","sans-serif";mso-ansi-language:EN-US'>Implementing the IP Module Using\r
+Diamond SW</span></b><span lang=EN-US style='mso-ansi-language:EN-US'><o:p></o:p></span></p>\r
+\r
+</div>\r
+\r
+<p class=MsoNormal style='margin-bottom:12.0pt'><span lang=EN-US\r
+style='mso-ansi-language:EN-US'><br>\r
+</span><b><span lang=EN-US style='font-family:"Arial","sans-serif";mso-ansi-language:\r
+EN-US'>Instantiating the Core</span></b><span lang=EN-US style='mso-ansi-language:\r
+EN-US'><o:p></o:p></span></p>\r
+\r
+<table class=MsoNormalTable border=0 cellpadding=0 width="80%"\r
+ style='width:80.0%;mso-cellspacing:1.5pt;mso-yfti-tbllook:1184;mso-padding-alt:\r
+ 0cm 0cm 0cm 0cm'>\r
+ <tr style='mso-yfti-irow:0;mso-yfti-firstrow:yes;mso-yfti-lastrow:yes'>\r
+  <td style='padding:.75pt .75pt .75pt .75pt'>\r
+  <p><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>The\r
+  generated SGMII core package includes black-box (&lt;user_name&gt;_bb.v) and\r
+  instance (&lt;username&gt;_inst.v) templates that can be used to instantiate\r
+  the core in a top-level design. <o:p></o:p></span></p>\r
+  <p><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>An\r
+  example RTL top-level reference source file(top_smi.v[vhd]) that can be used\r
+  as an instantiation template for the IP core is provided in <i>&lt;project_dir&gt;\sgmii_pcs_eval\&lt;username&gt;\src\rtl\top\[device]</i>.\r
+  Users may also use this top-level reference as the starting template for the\r
+  top-level for their complete design.</span></p>\r
+  </td>\r
+ </tr>\r
+</table>\r
+\r
+<p class=MsoNormal style='margin-bottom:12.0pt'><span lang=EN-US\r
+style='mso-ansi-language:EN-US'><br>\r
+</span><b><span lang=EN-US style='font-family:"Arial","sans-serif";mso-ansi-language:\r
+EN-US'>Hardware Evaluation</span></b><span lang=EN-US style='mso-ansi-language:\r
+EN-US'><o:p></o:p></span></p>\r
+\r
+<table class=MsoNormalTable border=0 cellpadding=0 width="80%"\r
+ style='width:80.0%;mso-cellspacing:1.5pt;mso-yfti-tbllook:1184;mso-padding-alt:\r
+ 0cm 0cm 0cm 0cm'>\r
+ <tr style='mso-yfti-irow:0;mso-yfti-firstrow:yes;mso-yfti-lastrow:yes'>\r
+  <td style='padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=MsoBodyText>Lattice's IP hardware evaluation capability makes it\r
+  possible to create IP cores that operate in hardware for a limited period of\r
+  time (approximately four hours) without requiring the purchase on an IP\r
+  license. The hardware evaluation capability is enabled by default. It can be\r
+  disabled by right clicking on &quot;Build Database&quot; in the &quot;Process\r
+  for current sources&quot; window of the Project Navigator. The setting is\r
+  called &quot;Hardware Evaluation&quot; and the options are &quot;Enable&quot;\r
+  or &quot;Disable&quot;.<br>\r
+  <span style='mso-spacerun:yes'>   </span><br>\r
+  When the Hardware Evaluation feature is enabled in the design, it will\r
+  generate a programming file that may be downloaded into the device. After\r
+  initialization, the IP core will be operational for approximately four hours.\r
+  After four hours, the device will stop working and it will be necessary to\r
+  reprogram the device to re-enable operation. This hardware evaluation\r
+  capability is only enabled if the core has not been licensed. During\r
+  implementation, a license check is performed. If the hardware evaluation\r
+  feature is disabled, a pop-up window will be displayed indicating a license\r
+  failure. <span class=SpellE>Click&quot;OK</span>&quot; in the window and the\r
+  bitstream will not be generated. If a license is detected, no pop-up window\r
+  is displayed and core generation is completed with no restrictions. </p>\r
+  <p class=MsoNormal>&nbsp;</p>\r
+  </td>\r
+ </tr>\r
+</table>\r
+\r
+<p class=MsoNormal><span lang=EN-US style='mso-ansi-language:EN-US'><br>\r
+</span><b><span lang=EN-US style='font-family:"Arial","sans-serif";mso-ansi-language:\r
+EN-US'>Implementing the core only design in a Top-Level Design</span></b><span\r
+lang=EN-US style='mso-ansi-language:EN-US'><o:p></o:p></span></p>\r
+\r
+<table class=MsoNormalTable border=0 cellpadding=0 width="80%"\r
+ style='width:80.0%;mso-cellspacing:1.5pt;mso-yfti-tbllook:1184;mso-padding-alt:\r
+ 0cm 0cm 0cm 0cm'>\r
+ <tr style='mso-yfti-irow:0;mso-yfti-firstrow:yes'>\r
+  <td style='padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=MsoNormal><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>As\r
+  described previously, the top-level file <span class=SpellE><i>top_pcs</i>_core_only.v</span>\r
+  provided in <i>&lt;<span class=SpellE>project_dir</span>&gt;\<span\r
+  class=SpellE>sgmii_pcs_eval</span>\&lt;username&gt;\<span class=SpellE>src</span>\<span\r
+  class=SpellE>rtl</span>\top\[device]</i> supports the ability to implement\r
+  just the SGMII IP core. <o:p></o:p></span></p>\r
+  <p><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Push-button\r
+  top-level implementation of this top-level is supported via the Diamond\r
+  project file &lt;username&gt;_<span class=SpellE>core_only_eval.ldf</span>\r
+  located in <i>&lt;<span class=SpellE>project_dir</span>&gt;\<span\r
+  class=SpellE>sgmii_pcs_eval</span>\&lt;username&gt;\<span class=SpellE>impl</span>\<span\r
+  class=SpellE>core_only</span>\[vendor]</i>. <o:p></o:p></span></p>\r
+  <p><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>This\r
+  design is intended only to provide an accurate indication of the device\r
+  utilization associated with the core itself and should not be used as an actual\r
+  implementation example.</span></p>\r
+  </td>\r
+ </tr>\r
+ <tr style='mso-yfti-irow:1;mso-yfti-lastrow:yes'>\r
+  <td style='padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=MsoNormal><br>\r
+  <span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>To use the\r
+  project file:<o:p></o:p></span></p>\r
+  <ul type=disc>\r
+   <li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l1 level1 lfo1;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Select<i> </i>File-&gt;Open-&gt;Project\r
+       in Lattice Diamond.</span> <span style='font-size:10.0pt;font-family:\r
+       "Verdana","sans-serif"'><o:p></o:p></span></li>\r
+   <li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l1 level1 lfo1;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Browse to <i>&lt;<span\r
+       class=SpellE>project_dir</span>&gt;\<span class=SpellE>sgmii_pcs_eval</span>\&lt;username&gt;\<span\r
+       class=SpellE>impl</span>\<span class=SpellE>core_only</span>\[vendor]</i>\r
+       in the Open Project dialog box.</span> <span style='font-size:10.0pt;\r
+       font-family:"Verdana","sans-serif"'><o:p></o:p></span></li>\r
+   <li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l1 level1 lfo1;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Select and\r
+       open &lt;username&gt;_<span class=SpellE>core_only_eval.ldf.At</span>\r
+       this point, all of the files needed to support top-level synthesis and\r
+       implementation will be imported to the project.</span> <span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'><o:p></o:p></span></li>\r
+   <li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l1 level1 lfo1;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Implement\r
+       the complete design via the standard Lattice Diamond GUI flow.<o:p></o:p></span></li>\r
+  </ul>\r
+  <p class=MsoNormal style='margin-left:36.0pt'><span style='font-size:10.0pt;\r
+  font-family:"Verdana","sans-serif"'><o:p>&nbsp;</o:p></span></p>\r
+  </td>\r
+ </tr>\r
+</table>\r
+\r
+<p class=MsoNormal><b><span lang=EN-US style='font-family:"Arial","sans-serif";\r
+mso-ansi-language:EN-US'><o:p>&nbsp;</o:p></span></b></p>\r
+\r
+<p class=MsoNormal><b><span lang=EN-US style='font-family:"Arial","sans-serif";\r
+mso-ansi-language:EN-US'>Implementing the reference design in a Top-Level\r
+Design</span></b><span lang=EN-US style='mso-ansi-language:EN-US'><o:p></o:p></span></p>\r
+\r
+<table class=MsoNormalTable border=0 cellpadding=0 width="80%"\r
+ style='width:80.0%;mso-cellspacing:1.5pt;mso-yfti-tbllook:1184;mso-padding-alt:\r
+ 0cm 0cm 0cm 0cm'>\r
+ <tr style='mso-yfti-irow:0;mso-yfti-firstrow:yes'>\r
+  <td style='padding:.75pt .75pt .75pt .75pt'>\r
+  <p><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Push-button\r
+  top-level implementation of a sample reference design is also supported via\r
+  the Diamond project file &lt;username&gt;_<span class=SpellE>reference_eval.ldf</span>\r
+  located in <i>&lt;<span class=SpellE>project_dir</span>&gt;\<span\r
+  class=SpellE>sgmii_pcs_eval</span>\&lt;username&gt;\<span class=SpellE>impl</span>\reference\[vendor]</i>.\r
+  <o:p></o:p></span></p>\r
+  </td>\r
+ </tr>\r
+ <tr style='mso-yfti-irow:1;mso-yfti-lastrow:yes'>\r
+  <td style='padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=MsoNormal><br>\r
+  <span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>To use the\r
+  project file:<o:p></o:p></span></p>\r
+  <ul type=disc>\r
+   <li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l1 level1 lfo1;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Select\r
+       File-&gt;Open-&gt;Project in Lattice Diamond.</span> <span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'><o:p></o:p></span></li>\r
+   <li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l1 level1 lfo1;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Browse to <i>&lt;<span\r
+       class=SpellE>project_dir</span>&gt;\<span class=SpellE>sgmii_pcs_eval</span>\&lt;username&gt;\<span\r
+       class=SpellE>impl</span>\reference\[vendor]</i> in the Open Project\r
+       dialog box.</span> <span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'><o:p></o:p></span></li>\r
+   <li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l1 level1 lfo1;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Select and\r
+       open &lt;username&gt;_<span class=SpellE>reference_eval.ldf.At</span>\r
+       this point, all of the files needed to support top-level synthesis and\r
+       implementation will be imported to the project.</span> <span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'><o:p></o:p></span></li>\r
+   <li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l1 level1 lfo1;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Implement\r
+       the complete design via the standard Lattice Diamond GUI flow.<o:p></o:p></span></li>\r
+  </ul>\r
+  <p class=MsoNormal style='margin-left:36.0pt'><span style='font-size:10.0pt;\r
+  font-family:"Verdana","sans-serif"'><o:p>&nbsp;</o:p></span></p>\r
+  </td>\r
+ </tr>\r
+</table>\r
+\r
+<p style='margin-bottom:12.0pt'><span lang=EN-US style='mso-ansi-language:EN-US'><br>\r
+</span><b><span lang=EN-US style='font-family:"Arial","sans-serif";mso-ansi-language:\r
+EN-US'>Running Functional and <st1:Street w:st="on"><st1:address w:st="on">Post\r
+  Route</st1:address></st1:Street> Timing Simulation</span></b><span\r
+lang=EN-US style='mso-ansi-language:EN-US'><o:p></o:p></span></p>\r
+\r
+<table class=MsoNormalTable border=0 cellpadding=0 width="80%"\r
+ style='width:80.0%;mso-cellspacing:1.5pt;mso-yfti-tbllook:1184;mso-padding-alt:\r
+ 0cm 0cm 0cm 0cm'>\r
+ <tr style='mso-yfti-irow:0;mso-yfti-firstrow:yes'>\r
+  <td style='padding:.75pt .75pt .75pt .75pt'>\r
+  <p><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>The\r
+  functional simulation includes a configuration-specific behavioral model of\r
+  the <i>SGMII</i>, which is instantiated in an FPGA top level along with some\r
+  test logic (PLLs, and registers with Read/Write Interface). This FPGA top is\r
+  instantiated in an eval testbench that configures FPGA test logic registers\r
+  and <i>SGMII</i> IP core registers. The testbench files can be found in <i>&lt;<span\r
+  class=SpellE>project_dir</span>&gt;\<span class=SpellE>sgmii_pcs_eval</span>\<span\r
+  class=SpellE>testbench</span></i>. <o:p></o:p></span></p>\r
+  </td>\r
+ </tr>\r
+ <tr style='mso-yfti-irow:1;mso-yfti-lastrow:yes'>\r
+  <td style='padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=MsoNormal><span class=style31><span style='font-size:10.0pt'>Functional\r
+  Simulation</span></span><br>\r
+  <span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>The\r
+  generated IP core package includes the configuration-specific behavior model\r
+  (&lt;username&gt;_beh.v) for functional simulation. ModelSim simulation is\r
+  supported via testbench files provided in <i>&lt;<span class=SpellE>project_dir</span>&gt;\<span\r
+  class=SpellE>sgmii_pcs_eval</span>\<span class=SpellE>testbench</span></i>.\r
+  Models required for simulation are provided in the <i>&lt;<span class=SpellE>project_dir</span>&gt;\<span\r
+  class=SpellE>sgmii_pcs_eval</span>\models\[device]</i> folder. <br>\r
+  Users may run the eval simulation by doing the following with </span><strong>ModelSim\r
+  SE</strong><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>:<span\r
+  class=style31><o:p></o:p></span></span></p>\r
+  <ul type=disc>\r
+   <li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l3 level1 lfo2;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Open\r
+       ModelSim.</span> </li>\r
+   <li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l3 level1 lfo2;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Under the <i>File</i>\r
+       tab, select <i>Change Directory</i></span> <span style='font-size:10.0pt;\r
+       font-family:"Verdana","sans-serif"'><o:p></o:p></span></li>\r
+   <li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l3 level1 lfo2;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Set the\r
+       directory to &lt;<span class=SpellE>project_dir</span>&gt;\<span\r
+       class=SpellE><i>sgmii_pcs_eval</i></span>\&lt;username&gt;\<span\r
+       class=SpellE>sim</span>\<span class=SpellE>modelsim</span>.</span> <span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'><o:p></o:p></span></li>\r
+   <li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l3 level1 lfo2;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Select OK.</span>\r
+       <span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'><o:p></o:p></span></li>\r
+   <li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l3 level1 lfo2;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Under the\r
+       Tools tab, select TCL, then select Execute Macro.</span> <span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'><o:p></o:p></span></li>\r
+   <li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l3 level1 lfo2;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Select file\r
+       &lt;username&gt;_reference_eval_se.do for ModelSim SE.</span></li>\r
+  </ul>\r
+  <p><span class=msonormal00><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Users\r
+  may run the eval simulation by doing the following with </span></span><strong>Active-HDL</strong><span\r
+  class=msonormal00><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>:</span></span></p>\r
+  <ul type=disc>\r
+   <li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l0 level1 lfo3;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Open\r
+       Active-HDL.<o:p></o:p></span></li>\r
+   <li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l0 level1 lfo3;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Under the <i>tools</i>\r
+       tab, select <i>Execute Macro...</i><o:p></o:p></span></li>\r
+   <li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l0 level1 lfo3;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Select file\r
+       &lt;project_dir&gt;\<i>sgmii_pcs_eval</i>\&lt;username&gt;\sim\aldec\&lt;username&gt;_reference_eval.do<o:p></o:p></span></li>\r
+  </ul>\r
+  <p><b><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;font-family:\r
+  "Verdana","sans-serif"'>Post Route Timing Simulation<o:p></o:p></span></b></p>\r
+  <p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span\r
+  style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>No post route\r
+  timing simulation is supported in this version.<o:p></o:p></span></p>\r
+  </td>\r
+ </tr>\r
+</table>\r
+\r
+<p class=MsoNormal><span lang=EN-US style='mso-ansi-language:EN-US'><o:p>&nbsp;</o:p></span></p>\r
+\r
+<p class=MsoNormal><span lang=EN-US style='mso-ansi-language:EN-US'><br>\r
+</span><b><span lang=EN-US style='font-family:"Arial","sans-serif";mso-ansi-language:\r
+EN-US'>Reference Information</span></b><span lang=EN-US style='mso-ansi-language:\r
+EN-US'><br>\r
+</span><span lang=EN-US style='font-size:10.0pt;font-family:"Verdana","sans-serif";\r
+mso-ansi-language:EN-US'><br>\r
+<span class=GramE>The</span> following documents provide more information on\r
+implementing this core:<o:p></o:p></span></p>\r
+\r
+<ul type=disc>\r
+ <li class=MsoNormal style='color:blue;mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+     auto;mso-list:l2 level1 lfo4;tab-stops:list 36.0pt'><span lang=EN-US\r
+     style='font-size:10.0pt;font-family:"Verdana","sans-serif";color:#013C9A;\r
+     mso-ansi-language:EN-US'><a\r
+     href="http://www.latticesemi.com/documents/IPUG60.pdf" target="_blank">User<span\r
+     style='mso-bidi-font-family:Verdana'>\92s Guide</span></a></span><span\r
+     class=MsoHyperlink><o:p></o:p></span></li>\r
+ <li class=MsoNormal style='color:#013C9A;mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+     auto;mso-list:l2 level1 lfo4;tab-stops:list 36.0pt'><span lang=EN-US\r
+     style='font-size:10.0pt;font-family:"Verdana","sans-serif";mso-ansi-language:\r
+     EN-US'><a\r
+     href="http://www.latticesemi.com/dynamic/view_document.cfm?document_id=18503"\r
+     target="_blank"><span class=SpellE><span style='color:#013C9A'>IPexpress</span></span><span\r
+     style='color:#013C9A'> Quick Start Guide</span></a> </span><o:p></o:p></li>\r
+</ul>\r
+\r
+<p class=MsoNormal><span lang=EN-US style='color:#013C9A;mso-ansi-language:\r
+EN-US'><script language="javascript1.2"  type="text/javascript">\r
+<!--\r
+if (window.writeIntopicBar)\r
+       writeIntopicBar(0);\r
+//-->\r
+</script></span><span lang=EN-US style='mso-ansi-language:EN-US'><o:p>&nbsp;</o:p></span></p>\r
+\r
+</div>\r
+\r
+</body>\r
+\r
+</html>\r

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/impl/core_only/synplify/sgmii_channel_smi_core_only_eval.ldf b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/impl/core_only/synplify/sgmii_channel_smi_core_only_eval.ldf
new file mode 100644 (file)
index 0000000..bb391d4
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/impl/core_only/synplify/sgmii_channel_smi_core_only_eval.ldf
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<BaliProject version="3.2" title="sgmii_channel_smi_core_only_eval" device="LFE5UM-85F-8BG756C" synthesis="synplify" default_implementation="sgmii_channel_smi_top_pcs_core_only">
+    <Implementation title="sgmii_channel_smi_top_pcs_core_only" dir="sgmii_channel_smi_top_pcs_core_only" description="sgmii_channel_smi_top_pcs_core_only" default_strategy="sgmii_channel_smi_core_only_eval">
+        <Options>
+     <Option name="top" value="top_pcs_core_only"/>
+     </Options>
+<Source name="../../../../../sgmii_channel_smi_core_bb.v" type="Verilog"/>
+<Source name="../../../src/rtl/top/ecp5um/top_pcs_core_only.v" type="Verilog"/>
+        <Source name="sgmii_channel_smi_core_only_eval.lpf" type="Logic Preference"/>
+    </Implementation>
+    <Strategy name="sgmii_channel_smi_core_only_eval" file="sgmii_channel_smi_core_only_eval.sty"/>
+</BaliProject>

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/impl/core_only/synplify/sgmii_channel_smi_core_only_eval.lpf b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/impl/core_only/synplify/sgmii_channel_smi_core_only_eval.lpf
new file mode 100644 (file)
index 0000000..1310d50
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/impl/core_only/synplify/sgmii_channel_smi_core_only_eval.lpf
@@ -0,0 +1,5 @@
+block RESETPATHS;\r
+block ASYNCPATHS;\r
+FREQUENCY NET "tx_clk_125_c" 125.0 MHz PAR_ADJ 25;\r
+FREQUENCY NET "rx_clk_125_c" 125.0 MHz PAR_ADJ 25;\r
+FREQUENCY NET "serdes_recovered_clk_c" 125.0 MHz PAR_ADJ 25;\r

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/impl/core_only/synplify/sgmii_channel_smi_core_only_eval.sty b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/impl/core_only/synplify/sgmii_channel_smi_core_only_eval.sty
new file mode 100644 (file)
index 0000000..b7c8175
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/impl/core_only/synplify/sgmii_channel_smi_core_only_eval.sty
@@ -0,0 +1,8 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE strategy>
+<Strategy version="1.0" predefined="0" description="" label="sgmii_channel_smi_core_only_eval">
+    <Property name="PROP_BD_EdfHardtimer" value="Disable" time="0"/>
+    <Property name="PROP_BD_EdfInLibPath" value="../../../../../" time="0"/>
+    <Property name="PROP_LST_EdfInLibPath" value="../../../../../" time="0"/>
+    <Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup With Hold Analysis on IOs" time="0"/>
+</Strategy>

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/impl/reference/synplify/sgmii_channel_smi_reference_eval.ldf b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/impl/reference/synplify/sgmii_channel_smi_reference_eval.ldf
new file mode 100644 (file)
index 0000000..2218a5e
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/impl/reference/synplify/sgmii_channel_smi_reference_eval.ldf
@@ -0,0 +1,16 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<BaliProject version="3.2" title="sgmii_channel_smi_reference_eval" device="LFE5UM-85F-8BG756C" synthesis="synplify" default_implementation="sgmii_channel_smi_reference_eval_hb">
+    <Implementation title="sgmii_channel_smi_reference_eval_hb" dir="sgmii_channel_smi_reference_eval_hb" description="sgmii_channel_smi_reference_eval_hb" default_strategy="sgmii_channel_smi_reference_eval">
+        <Options>
+            <Option name="top" value="top_hb"/>
+        </Options>
+<Source name="../../../src/rtl/template/ecp5um/register_interface_hb.v" type="Verilog"/>
+<Source name="../../../src/rtl/template/ecp5um/rate_resolution.v" type="Verilog"/>
+<Source name="../../../../../sgmii_pcs_eval/models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs_softlogic.v" type="Verilog"/>
+<Source name="../../../../../sgmii_pcs_eval/models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs.v" type="Verilog"/>
+<Source name="../../../../../sgmii_channel_smi.vhd" type="VHDL"/>
+<Source name="../../../src/rtl/top/ecp5um/top_hb.v" type="Verilog"/>
+        <Source name="sgmii_channel_smi_reference_eval.lpf" type="Logic Preference"/>
+    </Implementation>
+ <Strategy name="sgmii_channel_smi_reference_eval" file="sgmii_channel_smi_reference_eval.sty"/>
+</BaliProject>

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/impl/reference/synplify/sgmii_channel_smi_reference_eval.lpf b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/impl/reference/synplify/sgmii_channel_smi_reference_eval.lpf
new file mode 100644 (file)
index 0000000..c34d25a
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/impl/reference/synplify/sgmii_channel_smi_reference_eval.lpf
@@ -0,0 +1,9 @@
+block RESETPATHS;\r
+block ASYNCPATHS;\r
+#\r
+FREQUENCY NET "in_clk_125_c" 125.0 MHz PAR_ADJ 25;\r
+FREQUENCY NET "out_clk_125_c" 125.0 MHz PAR_ADJ 25;\r
+FREQUENCY NET "hclk_c" 50.0 MHz PAR_ADJ 25;\r
+FREQUENCY NET "*serdes_recovered_clk" 125.0 MHz PAR_ADJ 25;\r
+#\r
+#\r

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/impl/reference/synplify/sgmii_channel_smi_reference_eval.sty b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/impl/reference/synplify/sgmii_channel_smi_reference_eval.sty
new file mode 100644 (file)
index 0000000..97aabce
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/impl/reference/synplify/sgmii_channel_smi_reference_eval.sty
@@ -0,0 +1,8 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE strategy>
+<Strategy version="1.0" predefined="0" description="" label="sgmii_channel_smi_reference_eval">
+  <Property name="PROP_BD_EdfInLibPath" value="../../../../../" time="0"/>
+  <Property name="PROP_LST_EdfInLibPath" value="../../../../../" time="0"/>
+    <Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup With Hold Analysis on IOs" time="0"/>
+    <Property name="PROP_PAR_PlcIterParDes" value="5" time="0"/>
+</Strategy>

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/sim/modelsim/sgmii_channel_smi_reference_eval_se.do b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/sim/modelsim/sgmii_channel_smi_reference_eval_se.do
new file mode 100644 (file)
index 0000000..9991117
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/sim/modelsim/sgmii_channel_smi_reference_eval_se.do
@@ -0,0 +1,76 @@
+if {!0} {
+    vlib work 
+}
+vmap work work
+vmap ecp5u_black_boxes "/home/soft/lattice/diamond/3.10_x64/cae_library/simulation/blackbox/ecp5u_black_boxes" 
+
+# compile the IP core ###############
+vlog -novopt -y /home/soft/lattice/diamond/3.10_x64/cae_library/simulation/verilog/ecp5u +libext+.v ../../../../sgmii_channel_smi_beh.v
+vcom ../../../../sgmii_channel_smi.vhd
+
+# compile components of an sgmii channel ###############
+vlog -novopt -y /home/soft/lattice/diamond/3.10_x64/cae_library/simulation/verilog/ecp5u +libext+.v ../../src/rtl/template/ecp5um/register_interface_hb.v  
+vlog -novopt -y /home/soft/lattice/diamond/3.10_x64/cae_library/simulation/verilog/ecp5u +libext+.v ../../src/rtl/template/ecp5um/rate_resolution.v 
+
+# compile top level hardware components ###############
+vlog +define+RSL_SIM_MODE -novopt -y /home/soft/lattice/diamond/3.10_x64/cae_library/simulation/verilog/ecp5u +libext+.v ../../../models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs_softlogic.v  
+vlog -novopt -y /home/soft/lattice/diamond/3.10_x64/cae_library/simulation/verilog/ecp5u +libext+.v ../../../models/ecp5um/pcs_serdes/sgmii_channel_smi_pcs.v  
+vlog -novopt -y /home/soft/lattice/diamond/3.10_x64/cae_library/simulation/verilog/ecp5u +libext+.v ../../../models/ecp5um/pmi_fifo_dc/pmi_fifo_dc.v  
+
+# compile top level wrapper ###############
+vlog -novopt -y /home/soft/lattice/diamond/3.10_x64/cae_library/simulation/verilog/ecp5u +libext+.v ../../src/rtl/top/ecp5um/top_hb.v  
+
+# compile testbench components of sgmii_node ###############
+vlog -novopt -y /home/soft/lattice/diamond/3.10_x64/cae_library/simulation/verilog/ecp5u +libext+.v ../../../testbench/sgmii_node.v  
+
+# compile testbench components of mii monitor ###############
+vlog -novopt -y /home/soft/lattice/diamond/3.10_x64/cae_library/simulation/verilog/ecp5u +libext+.v ../../../testbench/port_parser_mii.v  
+vlog -novopt -y /home/soft/lattice/diamond/3.10_x64/cae_library/simulation/verilog/ecp5u +libext+.v ../../../testbench/port_monitor.v  
+vlog -novopt -y /home/soft/lattice/diamond/3.10_x64/cae_library/simulation/verilog/ecp5u +libext+.v ../../../testbench/mii_monitor.v  
+
+# compile the testbench ###############
+vlog -novopt -y /home/soft/lattice/diamond/3.10_x64/cae_library/simulation/verilog/ecp5u +libext+.v ../../../testbench/tb_hb.v 
+
+
+#start the simulator
+vsim -novopt -t ps -L ecp5u_black_boxes tb -l testcase.log
+
+
+# list waves
+view wave
+onerror {resume}
+add wave -divider {Control Signals}
+add wave -format Logic -radix hexadecimal sim:/tb/top/rst_n
+add wave -format Logic -radix hexadecimal sim:/tb/top/sgmii_mode
+add wave -divider {Host Bus Signals}
+add wave -format Logic -radix hexadecimal sim:/tb/top/hcs_n
+add wave -format Logic -radix hexadecimal sim:/tb/top/hwrite_n
+add wave -format Logic -radix hexadecimal sim:/tb/top/haddr
+add wave -format Logic -radix hexadecimal sim:/tb/top/hdatain
+add wave -format Logic -radix hexadecimal sim:/tb/top/hdataout
+add wave -format Logic -radix hexadecimal sim:/tb/top/hready_n
+add wave -divider {(G)MII Inbound Signals}
+add wave -format Logic -radix hexadecimal sim:/tb/top/in_ce_source
+add wave -format Logic -radix hexadecimal sim:/tb/top/in_ce_sink
+add wave -format Logic -radix hexadecimal sim:/tb/top/en_in_mii
+add wave -format Literal -radix hexadecimal sim:/tb/top/data_in_mii
+add wave -format Logic -radix hexadecimal sim:/tb/top/err_in_mii
+add wave -divider {(G)MII Outbound Signals}
+add wave -format Logic -radix hexadecimal sim:/tb/top/out_ce_source
+add wave -format Logic -radix hexadecimal sim:/tb/top/out_ce_sink
+add wave -format Logic -radix hexadecimal sim:/tb/top/dv_out_mii
+add wave -format Literal -radix hexadecimal sim:/tb/top/data_out_mii
+add wave -format Logic -radix hexadecimal sim:/tb/top/err_out_mii
+add wave -format Logic -radix hexadecimal sim:/tb/top/col_out_mii
+add wave -format Logic -radix hexadecimal sim:/tb/top/crs_out_mii
+add wave -divider {SERDES Outbound Signals}
+add wave -format Logic -radix hexadecimal sim:/tb/top/hdoutp0
+add wave -format Logic -radix hexadecimal sim:/tb/top/hdoutn0
+add wave -divider {SERDES Inbound Signals}
+add wave -format Logic -radix hexadecimal sim:/tb/top/hdinp0
+add wave -format Logic -radix hexadecimal sim:/tb/top/hdinn0
+
+
+# run simulation cycles
+run -all
+

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/src/rtl/template/ecp5um/rate_resolution.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/src/rtl/template/ecp5um/rate_resolution.v
new file mode 100644 (file)
index 0000000..b9edbef
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/src/rtl/template/ecp5um/rate_resolution.v
@@ -0,0 +1,66 @@
+//**************************************************************************\r
+// *************************************************************************\r
+// *                LATTICE SEMICONDUCTOR CONFIDENTIAL                     *\r
+// *                         PROPRIETARY NOTE                              *\r
+// *                                                                       *\r
+// *  This software contains information confidential and proprietary      *\r
+// *  to Lattice Semiconductor Corporation.  It shall not be reproduced    *\r
+// *  in whole or in part, or transferred to other documents, or disclosed *\r
+// *  to third parties, or used for any purpose other than that for which  *\r
+// *  it was obtained, without the prior written consent of Lattice        *\r
+// *  Semiconductor Corporation.  All rights reserved.                     *\r
+// *                                                                       *\r
+// *************************************************************************\r
+//**************************************************************************\r
+\r
+`timescale 1ns/100ps\r
+\r
+module rate_resolution (\r
+       gbe_mode,\r
+       sgmii_mode,\r
+       an_enable,\r
+       advertised_rate,\r
+       link_partner_rate,\r
+       non_an_rate,\r
+\r
+       operational_rate\r
+);\r
+\r
+input gbe_mode;\r
+input sgmii_mode;\r
+input an_enable;\r
+input [1:0] advertised_rate; // 00=10Mbps    01=100Mbps    10=1Gbps\r
+input [1:0] link_partner_rate;\r
+input [1:0] non_an_rate;\r
+\r
+output [1:0] operational_rate;\r
+reg [1:0] operational_rate;\r
+\r
+\r
+\r
+always @(gbe_mode or sgmii_mode or an_enable or advertised_rate or link_partner_rate or non_an_rate) begin\r
+       if (gbe_mode) begin\r
+               operational_rate <= 2'b10; // 1Gbps\r
+       end\r
+       else begin\r
+               if (an_enable) begin\r
+                       if (sgmii_mode) begin\r
+                               // PHY Mode\r
+                               operational_rate <= advertised_rate;\r
+                       end\r
+                       else begin\r
+                               // MAC Mode\r
+                               operational_rate <= link_partner_rate;\r
+                       end\r
+               end\r
+               else begin\r
+                       // If auto-negotiation disabled, then this becomes active rate\r
+                       operational_rate <= non_an_rate;\r
+               end\r
+       end\r
+end\r
+\r
+\r
+\r
+endmodule\r
+\r

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/src/rtl/template/ecp5um/register_interface_hb.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/src/rtl/template/ecp5um/register_interface_hb.v
new file mode 100644 (file)
index 0000000..028d806
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/src/rtl/template/ecp5um/register_interface_hb.v
@@ -0,0 +1,1393 @@
+//**************************************************************************\r
+// *************************************************************************\r
+// *                LATTICE SEMICONDUCTOR CONFIDENTIAL                     *\r
+// *                         PROPRIETARY NOTE                              *\r
+// *                                                                       *\r
+// *  This software contains information confidential and proprietary      *\r
+// *  to Lattice Semiconductor Corporation.  It shall not be reproduced    *\r
+// *  in whole or in part, or transferred to other documents, or disclosed *\r
+// *  to third parties, or used for any purpose other than that for which  *\r
+// *  it was obtained, without the prior written consent of Lattice        *\r
+// *  Semiconductor Corporation.  All rights reserved.                     *\r
+// *                                                                       *\r
+// *************************************************************************\r
+//**************************************************************************\r
+\r
+`timescale 1ns/100ps\r
+\r
+module register_interface_hb (\r
+\r
+       // Control Signals\r
+       rst_n,\r
+       hclk,\r
+       gbe_mode,\r
+       sgmii_mode,\r
+\r
+       // Host Bus\r
+       hcs_n,\r
+       hwrite_n,\r
+       haddr,\r
+       hdatain,\r
+\r
+       hdataout,\r
+       hready_n,\r
+\r
+       // Register Inputs\r
+       mr_stat_1000base_x_fd,\r
+       mr_stat_1000base_x_hd,\r
+       mr_stat_1000base_t_fd,\r
+       mr_stat_1000base_t_hd,\r
+\r
+       mr_stat_100base_t4,\r
+       mr_stat_100base_x_fd,\r
+       mr_stat_100base_x_hd,\r
+       mr_stat_10mbps_fd,\r
+       mr_stat_10mbps_hd,\r
+       mr_stat_100base_t2_fd,\r
+       mr_stat_100base_t2_hd,\r
+\r
+       mr_stat_extended_stat,\r
+       mr_stat_unidir_able,\r
+       mr_stat_preamb_supr,\r
+       mr_stat_an_complete,\r
+       mr_stat_remote_fault,\r
+       mr_stat_an_able,\r
+       mr_stat_link_stat,\r
+       mr_stat_jab_det,\r
+       mr_stat_extended_cap,\r
+\r
+       mr_page_rx,\r
+       mr_lp_adv_ability,\r
+\r
+       // Register Outputs\r
+       mr_main_reset,\r
+       mr_loopback_enable,\r
+       mr_speed_selection,\r
+       mr_an_enable,\r
+       mr_power_down,\r
+       mr_isolate,\r
+       mr_restart_an,\r
+       mr_duplex_mode,\r
+       mr_col_test,\r
+       mr_unidir_enable,\r
+       mr_adv_ability\r
+       );\r
+\r
+\r
+input          rst_n ;\r
+input          hclk ;\r
+input          gbe_mode ;\r
+input          sgmii_mode ;\r
+\r
+input           hcs_n;\r
+input           hwrite_n;\r
+input    [5:0]  haddr;\r
+input    [7:0]  hdatain;\r
+\r
+output   [7:0]  hdataout;\r
+output          hready_n;\r
+\r
+input           mr_stat_1000base_x_fd;\r
+input           mr_stat_1000base_x_hd;\r
+input           mr_stat_1000base_t_fd;\r
+input           mr_stat_1000base_t_hd;\r
+\r
+input           mr_stat_100base_t4;\r
+input           mr_stat_100base_x_fd;\r
+input           mr_stat_100base_x_hd;\r
+input           mr_stat_10mbps_fd;\r
+input           mr_stat_10mbps_hd;\r
+input           mr_stat_100base_t2_fd;\r
+input           mr_stat_100base_t2_hd;\r
+\r
+input           mr_stat_extended_stat;\r
+input           mr_stat_unidir_able;\r
+input           mr_stat_preamb_supr;\r
+input           mr_stat_an_complete;\r
+input           mr_stat_remote_fault;\r
+input           mr_stat_an_able;\r
+input           mr_stat_link_stat;\r
+input           mr_stat_jab_det;\r
+input           mr_stat_extended_cap;\r
+\r
+input          mr_page_rx;\r
+input [15:0]   mr_lp_adv_ability;\r
+\r
+output                 mr_main_reset;\r
+output                 mr_loopback_enable;\r
+output [1:0]   mr_speed_selection;\r
+output                 mr_an_enable;\r
+output                 mr_power_down;\r
+output                 mr_isolate;\r
+output                 mr_restart_an;\r
+output                 mr_duplex_mode;\r
+output                 mr_col_test;\r
+output                 mr_unidir_enable;\r
+output [15:0]  mr_adv_ability;\r
+\r
+regs_hb   regs (\r
+       .rst_n (rst_n),\r
+       .hclk (hclk),\r
+\r
+       .gbe_mode (gbe_mode),\r
+       .sgmii_mode (sgmii_mode),\r
+\r
+       .hcs_n (hcs_n),\r
+       .hwrite_n (hwrite_n),\r
+       .haddr (haddr),\r
+       .hdatain (hdatain),\r
+\r
+       .hdataout (hdataout),\r
+       .hready_n (hready_n),\r
+\r
+       .mr_stat_1000base_x_fd (mr_stat_1000base_x_fd),\r
+       .mr_stat_1000base_x_hd (mr_stat_1000base_x_hd),\r
+       .mr_stat_1000base_t_fd (mr_stat_1000base_t_fd),\r
+       .mr_stat_1000base_t_hd (mr_stat_1000base_t_hd),\r
+\r
+       .mr_stat_100base_t4 (mr_stat_100base_t4),\r
+       .mr_stat_100base_x_fd (mr_stat_100base_x_fd),\r
+       .mr_stat_100base_x_hd (mr_stat_100base_x_hd),\r
+       .mr_stat_10mbps_fd (mr_stat_10mbps_fd),\r
+       .mr_stat_10mbps_hd (mr_stat_10mbps_hd),\r
+       .mr_stat_100base_t2_fd (mr_stat_100base_t2_fd),\r
+       .mr_stat_100base_t2_hd (mr_stat_100base_t2_hd),\r
+\r
+       .mr_stat_extended_stat (mr_stat_extended_stat),\r
+       .mr_stat_unidir_able (mr_stat_unidir_able),\r
+       .mr_stat_preamb_supr (mr_stat_preamb_supr),\r
+       .mr_stat_an_complete (mr_stat_an_complete),\r
+       .mr_stat_remote_fault (mr_stat_remote_fault),\r
+       .mr_stat_an_able (mr_stat_an_able),\r
+       .mr_stat_link_stat (mr_stat_link_stat),\r
+       .mr_stat_jab_det (mr_stat_jab_det),\r
+       .mr_stat_extended_cap (mr_stat_extended_cap),\r
+\r
+       .mr_page_rx (mr_page_rx),\r
+       .mr_lp_adv_ability (mr_lp_adv_ability),\r
+\r
+       .mr_main_reset (mr_main_reset),\r
+       .mr_loopback_enable (mr_loopback_enable),\r
+       .mr_speed_selection (mr_speed_selection),\r
+       .mr_an_enable (mr_an_enable),\r
+       .mr_power_down (mr_power_down),\r
+       .mr_isolate (mr_isolate),\r
+       .mr_restart_an (mr_restart_an),\r
+       .mr_duplex_mode (mr_duplex_mode),\r
+       .mr_col_test (mr_col_test),\r
+       .mr_unidir_enable (mr_unidir_enable),\r
+\r
+       .mr_adv_ability (mr_adv_ability)\r
+);\r
+endmodule\r
+\r
+\r
+\r
+\r
+\r
+\r
+module register_0_hb (\r
+       rst_n,\r
+       clk, \r
+       gbe_mode, \r
+       cs_0,\r
+       cs_1,\r
+       write,\r
+       ready,\r
+       data_in,\r
+\r
+       data_out,\r
+       mr_main_reset,\r
+       mr_loopback_enable,\r
+       mr_speed_selection,\r
+       mr_an_enable,\r
+       mr_power_down,\r
+       mr_isolate,\r
+       mr_restart_an,\r
+       mr_duplex_mode,\r
+       mr_col_test,\r
+       mr_unidir_enable\r
+);\r
+\r
+input           rst_n;\r
+input           clk;\r
+input           gbe_mode;\r
+input           cs_0;\r
+input           cs_1;\r
+input           write;\r
+input           ready;\r
+input  [15:0]   data_in;\r
+\r
+output [15:0]   data_out;\r
+output          mr_main_reset; // bit D15 // R/W // Self Clearing\r
+output          mr_loopback_enable;    // bit D14 // R/W\r
+output [1:0]    mr_speed_selection;    // bit D13 LSB     bit D6 MSB  // R/W\r
+output          mr_an_enable;  // bit D12 // R/W\r
+output          mr_power_down;         // bit D11 // R/W\r
+output          mr_isolate;            // bit D10 // R/W\r
+output          mr_restart_an; // bit D09 // R/W // Self Clearing\r
+output          mr_duplex_mode;                // bit D08 // STUCK HIGH\r
+output          mr_col_test;           // bit D08 // STUCK LOW\r
+output          mr_unidir_enable;      // bit D05 // STUCK LOW\r
+\r
+reg [15:0]      data_out;\r
+reg             mr_main_reset;\r
+reg            mr_loopback_enable;\r
+reg [1:0]      mr_speed_selection;\r
+reg             mr_an_enable;\r
+reg            mr_power_down = 1'b0;\r
+reg            mr_isolate;\r
+reg             mr_restart_an;\r
+reg            mr_duplex_mode;\r
+reg            mr_col_test;\r
+reg            mr_unidir_enable;\r
+reg            m_m_r;\r
+reg            m_r_a;\r
+reg            gbe_mode_d1;\r
+reg            gbe_mode_d2;\r
+\r
+\r
+\r
+// Deboggle\r
+always @(posedge clk or negedge rst_n) begin\r
+       if (rst_n == 1'b0) begin\r
+               gbe_mode_d1 <= 0;\r
+               gbe_mode_d2 <= 0;\r
+       end\r
+       else begin\r
+               gbe_mode_d1 <= gbe_mode;\r
+               gbe_mode_d2 <= gbe_mode_d1;\r
+       end\r
+end\r
+\r
+\r
+\r
+// Write Operations\r
+\r
+       // Low Portion of Register[D7:D0] has no\r
+       // implemented bits.  Therefore, no write\r
+       // operations here.\r
+\r
+       // High Portion of Register[D15:D8]\r
+       always @(posedge clk or negedge rst_n) begin\r
+               if (rst_n == 1'b0) begin\r
+                       mr_main_reset <= 1'b0;\r
+                       mr_loopback_enable <= 1'b0;\r
+                       mr_speed_selection <= 2'b10;\r
+                       mr_an_enable <= 1'b1;\r
+                       mr_power_down <= 1'b0;\r
+                       mr_isolate <= 1'b0;\r
+                       mr_restart_an <= 1'b0;\r
+                       mr_duplex_mode <= 1'b1;\r
+                       mr_col_test <= 1'b0;\r
+                       mr_unidir_enable <= 1'b0;\r
+                       m_m_r <= 0;\r
+                       m_r_a <= 0;\r
+               end\r
+               else begin\r
+\r
+                       // defaults\r
+                       mr_duplex_mode <= 1'b1;   // STUCK HIGH\r
+                       mr_col_test <= 1'b0;      // STUCK LOW\r
+\r
+                       // Do the Writes\r
+                       if (cs_1 && ready && write) begin\r
+                               mr_main_reset <= data_in[15];\r
+                               mr_loopback_enable      <= data_in[14];\r
+                               mr_an_enable <= data_in[12];\r
+                               mr_power_down           <= data_in[11];\r
+                               mr_isolate              <= data_in[10];\r
+                               mr_restart_an <= data_in[9];\r
+                       end\r
+\r
+\r
+                       // Manage Writes to Speed Selection Based on GBE MODE\r
+                       if (gbe_mode_d2) begin\r
+                               mr_speed_selection[1:0] <= 2'b10; // STUCK AT 1GBPS\r
+                       end\r
+                       else begin\r
+                               if (cs_1 && ready && write) begin\r
+                                       mr_speed_selection[0]   <= data_in[13];\r
+                               end\r
+                               if (cs_0 && ready && write) begin\r
+                                       mr_speed_selection[1]   <= data_in[6];\r
+                                       mr_unidir_enable        <= data_in[5];\r
+                               end\r
+                       end\r
+\r
+\r
+\r
+                       // Delay the Self Clearing Register Bits\r
+                       m_m_r <= mr_main_reset;\r
+                       m_r_a <= mr_restart_an;\r
+\r
+                       // Do the Self Clearing\r
+                       if (m_m_r)\r
+                               mr_main_reset <= 0;\r
+\r
+                       if (m_r_a)\r
+                               mr_restart_an <= 0;\r
+               end\r
+       end\r
+\r
+\r
+\r
+\r
+\r
+// Read Operations\r
+       always @(*) begin\r
+                       data_out[7] <= mr_col_test;\r
+                       data_out[6] <= mr_speed_selection[1];\r
+                       data_out[5] <= mr_unidir_enable;\r
+                       data_out[4] <= 1'b0;\r
+                       data_out[3] <= 1'b0;\r
+                       data_out[2] <= 1'b0;\r
+                       data_out[1] <= 1'b0;\r
+                       data_out[0] <= 1'b0;\r
+\r
+                       data_out[15] <= mr_main_reset;\r
+                       data_out[14] <= mr_loopback_enable;\r
+                       data_out[13] <= mr_speed_selection[0];\r
+                       data_out[12] <= mr_an_enable;\r
+                       data_out[11] <= mr_power_down;\r
+                       data_out[10] <= mr_isolate;\r
+                       data_out[9]  <= mr_restart_an;\r
+                       data_out[8]  <= mr_duplex_mode;\r
+       end\r
+endmodule\r
+\r
+module register_1_hb (\r
+       rst_n,\r
+       clk,\r
+       cs_0,\r
+       cs_1,\r
+       write,\r
+       ready,\r
+\r
+\r
+       mr_stat_100base_t4,\r
+       mr_stat_100base_x_fd,\r
+       mr_stat_100base_x_hd,\r
+       mr_stat_10mbps_fd,\r
+       mr_stat_10mbps_hd,\r
+       mr_stat_100base_t2_fd,\r
+       mr_stat_100base_t2_hd,\r
+\r
+       mr_stat_extended_stat,\r
+       mr_stat_unidir_able,\r
+       mr_stat_preamb_supr,\r
+       mr_stat_an_complete,\r
+       mr_stat_remote_fault,\r
+       mr_stat_an_able,\r
+       mr_stat_link_stat,\r
+       mr_stat_jab_det,\r
+       mr_stat_extended_cap,\r
+\r
+       data_out\r
+);\r
+\r
+input           rst_n;\r
+input           clk;\r
+input           cs_0;\r
+input           cs_1;\r
+input           write;\r
+input           ready;\r
+input           mr_stat_100base_t4;    // bit D15 // Read-Only\r
+input           mr_stat_100base_x_fd;  // bit D14 // Read-Only\r
+input           mr_stat_100base_x_hd;  // bit D13 // Read-Only\r
+input           mr_stat_10mbps_fd;     // bit D12 // Read-Only\r
+input           mr_stat_10mbps_hd;     // bit D11 // Read-Only\r
+input           mr_stat_100base_t2_fd; // bit D10 // Read-Only\r
+input           mr_stat_100base_t2_hd; // bit D9  // Read-Only\r
+\r
+input           mr_stat_extended_stat; // bit D8  // Read-Only\r
+input           mr_stat_unidir_able;   // bit D7  // Read-Only\r
+input           mr_stat_preamb_supr;   // bit D6  // Read-Only\r
+input           mr_stat_an_complete;   // bit D5  // Read-Only\r
+input           mr_stat_remote_fault;  // bit D4  // Read-Only\r
+input           mr_stat_an_able;       // bit D3  // Read-Only\r
+input           mr_stat_link_stat;     // bit D2  // Read-Only // Latch-On-Zero // Clear-On-Read\r
+input           mr_stat_jab_det;       // bit D1  // Read-Only\r
+input           mr_stat_extended_cap;  // bit D0  // Read-Only\r
+\r
+output [15:0]   data_out;\r
+\r
+reg [15:0]      data_out;\r
+\r
+reg            link_stat_d1;\r
+reg            link_stat_d2;\r
+reg             clear_on_read;\r
+reg             read_detect;\r
+reg             rd_d1;\r
+reg             rd_d2;\r
+reg            allow_link_stat;\r
+reg            link_ok_status;\r
+// metastability filter\r
+       always @(posedge clk or negedge rst_n) begin\r
+               if (rst_n == 1'b0) begin\r
+                       link_stat_d1 <= 1'b0;\r
+                       link_stat_d2 <= 1'b0;\r
+               end\r
+               else begin\r
+                       link_stat_d1 <= mr_stat_link_stat;\r
+                       link_stat_d2 <= link_stat_d1;\r
+               end\r
+       end\r
+\r
+// generate clear-on-read signal\r
+       always @(posedge clk or negedge rst_n) begin\r
+               if (rst_n == 1'b0) begin\r
+                       clear_on_read <= 1'b0;\r
+                       read_detect <= 1'b0;\r
+                       rd_d1 <= 1'b0;\r
+                       rd_d2 <= 1'b0;\r
+               end\r
+               else begin\r
+                       if (!write && ready && cs_0)\r
+                               read_detect <= 1'b1;\r
+                       else \r
+                               read_detect <= 1'b0;\r
+\r
+                       rd_d1 <= read_detect;\r
+                       rd_d2 <= rd_d1;\r
+\r
+                       // assert on falling edge of rd_d2\r
+                       clear_on_read <= !rd_d1 & rd_d2;\r
+               end\r
+       end\r
+\r
+\r
+// Latch and Clear\r
+       always @(posedge clk or negedge rst_n) begin\r
+               if (rst_n == 1'b0) begin\r
+                       allow_link_stat <= 1'b0;\r
+                       link_ok_status <= 1'b0;\r
+               end\r
+               else begin\r
+\r
+                       case (allow_link_stat)\r
+                               1'b0: begin\r
+                                       if (clear_on_read) begin\r
+                                               allow_link_stat<= 1'b1;\r
+                                       end\r
+                               end\r
+\r
+                               1'b1: begin\r
+                                       if (!link_stat_d2) begin\r
+                                               allow_link_stat <= 1'b0;\r
+                                       end\r
+                               end\r
+                       endcase\r
+\r
+\r
+                       if (allow_link_stat) begin\r
+                               // allow status shoot-thru after clear-on-read\r
+                               link_ok_status <= link_stat_d2;\r
+                       end\r
+                       else begin\r
+                               // force status low when link IS NOT_OKAY\r
+                               link_ok_status <= 1'b0;\r
+                       end\r
+\r
+               end\r
+       end\r
+\r
+\r
+// Read Operations\r
+\r
+       always @(*) begin\r
+                       data_out[7] <= mr_stat_unidir_able;\r
+                       data_out[6] <= mr_stat_preamb_supr;\r
+                       data_out[5] <= mr_stat_an_complete;\r
+                       data_out[4] <= mr_stat_remote_fault;\r
+                       data_out[3] <= mr_stat_an_able;\r
+                       data_out[2] <= link_ok_status;\r
+                       data_out[1] <= mr_stat_jab_det;\r
+                       data_out[0] <= mr_stat_extended_cap;\r
+\r
+                       data_out[15] <= mr_stat_100base_t4;\r
+                       data_out[14] <= mr_stat_100base_x_fd;\r
+                       data_out[13] <= mr_stat_100base_x_hd;\r
+                       data_out[12] <= mr_stat_10mbps_fd;\r
+                       data_out[11] <= mr_stat_10mbps_hd;\r
+                       data_out[10] <= mr_stat_100base_t2_fd;\r
+                       data_out[9]  <= mr_stat_100base_t2_hd;\r
+                       data_out[8]  <= mr_stat_extended_stat;\r
+       end\r
+endmodule\r
+\r
+module register_4_hb (\r
+       rst_n,\r
+       clk, \r
+       gbe_mode,\r
+       sgmii_mode,\r
+       cs_0,\r
+       cs_1,\r
+       write,\r
+       ready,\r
+       data_in,\r
+\r
+       data_out,\r
+       mr_adv_ability\r
+);\r
+\r
+parameter [15:0] initval_gbe = 16'h0020;\r
+parameter [15:0] initval_phy = 16'hd801;\r
+parameter [15:0] initval_mac = 16'h4001;\r
+\r
+input           rst_n;\r
+input           clk;\r
+input           gbe_mode;\r
+input           sgmii_mode;\r
+input           cs_0;\r
+input           cs_1;\r
+input           write;\r
+input           ready;\r
+input  [15:0]   data_in;\r
+\r
+output [15:0]   data_out;\r
+output [15:0]   mr_adv_ability; // When sgmii_mode == 1 == PHY\r
+                               // all bits D15-D0 are R/W,\r
+                               ///////////////////////////////////\r
+                               // D15 = Link Status (1=up, 0=down)\r
+                               // D14 = Can be written but has no effect\r
+                               //           on autonegotiation.  Instead\r
+                               //           the autonegotiation state machine\r
+                               //           controls the utilization of this bit.\r
+                               // D12 = Duplex Mode (1=full, 0=half)\r
+                               // D11:10 = Speed (11=reserved)\r
+                               //                (10=1000Mbps)\r
+                               //                (01=100 Mbps)\r
+                               //                (00=10  Mbps)\r
+                               // D0 = 1\r
+                               // all other bits = 0\r
+                               ///////////////////////////////////\r
+                               //When sgmii_mode == 0 = MAC\r
+                               // all bits D15-D0 are R/W,\r
+                               // D14 = Can be written but has no effect\r
+                               //           on autonegotiation.  Instead\r
+                               //           the autonegotiation state machine\r
+                               //           controls the utilization of this bit.\r
+                               // D0 = 1\r
+                               // all other bits = 0\r
+                               ///////////////////////////////////\r
+\r
+\r
+reg [15:0]      data_out;\r
+reg [15:0]      mr_adv_ability;\r
+reg             rst_d1;\r
+reg             rst_d2;\r
+reg             rst_d3;\r
+reg             rst_d4;\r
+reg             rst_d5;\r
+reg             rst_d6;\r
+reg             rst_d7;\r
+reg             rst_d8;\r
+reg             sync_reset;\r
+reg             sgmii_mode_d1;\r
+reg             sgmii_mode_d2;\r
+reg             sgmii_mode_d3;\r
+reg             sgmii_mode_d4;\r
+reg             sgmii_mode_change;\r
+reg            gbe_mode_d1;\r
+reg            gbe_mode_d2;\r
+reg            gbe_mode_d3;\r
+reg            gbe_mode_d4;\r
+reg            gbe_mode_change;\r
+\r
+// generate a synchronous reset signal\r
+//    note: this method is used so that\r
+//          an initval can be applied during\r
+//         device run-time, instead of at compile time\r
+always @(posedge clk or negedge rst_n) begin\r
+       if (rst_n == 1'b0) begin\r
+               rst_d1 <= 0;\r
+               rst_d2 <= 0;\r
+               rst_d3 <= 0;\r
+               rst_d4 <= 0;\r
+               rst_d5 <= 0;\r
+               rst_d6 <= 0;\r
+               rst_d7 <= 0;\r
+               rst_d8 <= 0;\r
+               sync_reset <= 0;\r
+       end\r
+       else begin\r
+               rst_d1 <= 1;\r
+               rst_d2 <= rst_d1;\r
+               rst_d3 <= rst_d2;\r
+               rst_d4 <= rst_d3;\r
+               rst_d5 <= rst_d4;\r
+               rst_d6 <= rst_d5;\r
+               rst_d7 <= rst_d6;\r
+               rst_d8 <= rst_d7;\r
+\r
+               // asserts on rising edge of rst_d8\r
+               sync_reset <= !rst_d8 & rst_d7; \r
+       end\r
+end\r
+\r
+\r
+// Detect change in sgmii_mode\r
+always @(posedge clk or negedge rst_n) begin\r
+       if (rst_n == 1'b0) begin\r
+               sgmii_mode_d1 <= 0;\r
+               sgmii_mode_d2 <= 0;\r
+               sgmii_mode_d3 <= 0;\r
+               sgmii_mode_d4 <= 0;\r
+               sgmii_mode_change <= 0;\r
+       end\r
+       else begin\r
+\r
+               // deboggle\r
+               sgmii_mode_d1 <= sgmii_mode;\r
+               sgmii_mode_d2 <= sgmii_mode_d1;\r
+\r
+               // delay \r
+               sgmii_mode_d3 <= sgmii_mode_d2;\r
+               sgmii_mode_d4 <= sgmii_mode_d3;\r
+\r
+               // detect change\r
+               if (sgmii_mode_d3 != sgmii_mode_d4)\r
+                       sgmii_mode_change <= 1;\r
+               else\r
+                       sgmii_mode_change <= 0;\r
+       end\r
+end\r
+\r
+\r
+// Detect change in gbe_mode\r
+always @(posedge clk or negedge rst_n) begin\r
+       if (rst_n == 1'b0) begin\r
+               gbe_mode_d1 <= 0;\r
+               gbe_mode_d2 <= 0;\r
+               gbe_mode_d3 <= 0;\r
+               gbe_mode_d4 <= 0;\r
+               gbe_mode_change <= 0;\r
+       end\r
+       else begin\r
+\r
+               // deboggle\r
+               gbe_mode_d1 <= gbe_mode;\r
+               gbe_mode_d2 <= gbe_mode_d1;\r
+\r
+               // delay \r
+               gbe_mode_d3 <= gbe_mode_d2;\r
+               gbe_mode_d4 <= gbe_mode_d3;\r
+\r
+               // detect change\r
+               if (gbe_mode_d3 != gbe_mode_d4)\r
+                       gbe_mode_change <= 1;\r
+               else\r
+                       gbe_mode_change <= 0;\r
+       end\r
+end\r
+\r
+\r
+// Write Operations\r
+       // Low Portion of Register[D7:D0]\r
+       always @(posedge clk or negedge rst_n) begin\r
+               if (rst_n == 1'b0) begin\r
+                       mr_adv_ability[7:0] <= 8'h01;\r
+               end\r
+               else if (sync_reset || sgmii_mode_change || gbe_mode_change) begin\r
+                       if (gbe_mode_d4)\r
+                               mr_adv_ability[7:0] <= initval_gbe[7:0];\r
+                       else if (sgmii_mode)\r
+                               mr_adv_ability[7:0] <= initval_phy[7:0];\r
+                       else\r
+                               mr_adv_ability[7:0] <= initval_mac[7:0];\r
+               end\r
+               else begin\r
+                       if (cs_0 && ready && write && (sgmii_mode || gbe_mode)) begin\r
+                               mr_adv_ability[7:0] <= data_in[7:0];\r
+                       end\r
+               end\r
+       end\r
+\r
+\r
+       // High Portion of Register[D15:D8]\r
+       always @(posedge clk or negedge rst_n) begin\r
+               if (rst_n == 1'b0) begin\r
+                       mr_adv_ability[15:8] <= 8'h40; // default\r
+               end\r
+               else if (sync_reset || sgmii_mode_change || gbe_mode_change) begin\r
+                       if (gbe_mode_d4)\r
+                               mr_adv_ability[15:8] <= initval_gbe[15:8];\r
+                       else if (sgmii_mode)\r
+                               mr_adv_ability[15:8] <= initval_phy[15:8];\r
+                       else\r
+                               mr_adv_ability[15:8] <= initval_mac[15:8];\r
+               end\r
+               else begin\r
+                       if (cs_1 && ready && write && (sgmii_mode || gbe_mode)) begin\r
+                               mr_adv_ability[15:8] <= data_in[15:8];\r
+                       end\r
+               end\r
+       end\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+// Read Operations\r
+\r
+       always @(*) begin\r
+                       data_out[7:0] <= mr_adv_ability[7:0];\r
+                       data_out[15:8] <= mr_adv_ability[15:8];\r
+       end\r
+\r
+endmodule\r
+\r
+\r
+\r
+\r
+\r
+\r
+module register_5_hb (\r
+       rst_n,\r
+       mr_lp_adv_ability,\r
+       cs_0,\r
+       cs_1,\r
+       ready,\r
+\r
+       data_out\r
+);\r
+\r
+input           rst_n;\r
+input           cs_0;\r
+input           cs_1;\r
+input           ready;\r
+input  [15:0]   mr_lp_adv_ability;\r
+                               // This entire register is read-only\r
+                               ///////////////////////////////////\r
+                               // When sgmii_mode == 0 == MAC\r
+                               ///////////////////////////////////\r
+                               // D15 = PHY Link Status (1=up, 0=down)\r
+                               // D14 = PHY Autonegotiation Handshake\r
+                               // D12 = PHY Duplex Mode (1=full, 0=half)\r
+                               // D11:10 = PHY Speed (11=reserved)\r
+                               //                    (10=1000Mbps)\r
+                               //                    (01=100 Mbps)\r
+                               //                    (00=10  Mbps)\r
+                               // D0 = 1\r
+                               // all other bits = 0\r
+                               ///////////////////////////////////\r
+                               //When sgmii_mode == 1 = PHY\r
+                               // D14 = MAC Autonegotiation Handshake\r
+                               // D0 = 1\r
+                               // all other bits = 0\r
+                               ///////////////////////////////////\r
+output [15:0]   data_out;\r
+\r
+reg [15:0]      data_out;\r
+\r
+// Read Operations\r
+\r
+       always @(*) begin\r
+                       data_out[7:0] <= mr_lp_adv_ability[7:0];\r
+                       data_out[15:8] <= mr_lp_adv_ability[15:8];\r
+       end\r
+endmodule\r
+\r
+module register_6_hb (\r
+       rst_n,\r
+       clk,\r
+       mr_page_rx,\r
+       cs_0,\r
+       cs_1,\r
+       write,\r
+       ready,\r
+\r
+       data_out\r
+);\r
+\r
+input           rst_n;\r
+input           clk;\r
+input           cs_0;\r
+input           cs_1;\r
+input           write;\r
+input           ready;\r
+input           mr_page_rx;\r
+output [15:0]   data_out;\r
+\r
+reg [15:0]      data_out;\r
+reg             mr_page_rx_latched;\r
+reg             clear_on_read;\r
+reg             read_detect;\r
+reg             rd_d1;\r
+reg             rd_d2;\r
+\r
+// generate clear-on-read signal\r
+       always @(posedge clk or negedge rst_n) begin\r
+               if (rst_n == 1'b0) begin\r
+                       clear_on_read <= 0;\r
+                       read_detect <= 0;\r
+                       rd_d1 <= 0;\r
+                       rd_d2 <= 0;\r
+               end\r
+               else begin\r
+                       if (!write && ready && cs_0)\r
+                               read_detect <= 1;\r
+                       else \r
+                               read_detect <= 0;\r
+\r
+                       rd_d1 <= read_detect;\r
+                       rd_d2 <= rd_d1;\r
+\r
+                       // assert on falling edge of rd_d2\r
+                       clear_on_read <= !rd_d1 & rd_d2;\r
+               end\r
+       end\r
+\r
+\r
+// Latch and Clear\r
+       always @(posedge clk or negedge rst_n) begin\r
+               if (rst_n == 1'b0) begin\r
+                       mr_page_rx_latched <= 0;\r
+               end\r
+               else begin\r
+                       if (clear_on_read)\r
+                               mr_page_rx_latched <= 0;\r
+                       else if (mr_page_rx)\r
+                               mr_page_rx_latched <= 1;\r
+               end\r
+       end\r
+\r
+\r
+// Read Operations\r
+\r
+       always @(*) begin\r
+                       data_out[15:2] <= 14'd0;\r
+                       data_out[1] <= mr_page_rx_latched;\r
+                       data_out[0] <= 0;\r
+       end\r
+endmodule\r
+\r
+\r
+module register_f_hb (\r
+       rst_n,\r
+       cs_0,\r
+       cs_1,\r
+\r
+       mr_stat_1000base_x_fd,\r
+       mr_stat_1000base_x_hd,\r
+       mr_stat_1000base_t_fd,\r
+       mr_stat_1000base_t_hd,\r
+\r
+       data_out\r
+);\r
+\r
+input           rst_n;\r
+input           cs_0;\r
+input           cs_1;\r
+\r
+input           mr_stat_1000base_x_fd; // bit D15 // Read-Only\r
+input           mr_stat_1000base_x_hd; // bit D14 // Read-Only\r
+input           mr_stat_1000base_t_fd; // bit D13 // Read-Only\r
+input           mr_stat_1000base_t_hd; // bit D12 // Read-Only\r
+\r
+output [15:0]   data_out;\r
+\r
+reg [15:0]      data_out;\r
+\r
+\r
+// Read Operations\r
+\r
+       always @(*) begin\r
+                       data_out[7] <= 1'b0;\r
+                       data_out[6] <= 1'b0;\r
+                       data_out[5] <= 1'b0;\r
+                       data_out[4] <= 1'b0;\r
+                       data_out[3] <= 1'b0;\r
+                       data_out[2] <= 1'b0;\r
+                       data_out[1] <= 1'b0;\r
+                       data_out[0] <= 1'b0;\r
+\r
+                       data_out[15] <= mr_stat_1000base_x_fd;\r
+                       data_out[14] <= mr_stat_1000base_x_hd;\r
+                       data_out[13] <= mr_stat_1000base_t_fd;\r
+                       data_out[12] <= mr_stat_1000base_t_hd;\r
+                       data_out[11] <= 1'b0;\r
+                       data_out[10] <= 1'b0;\r
+                       data_out[9]  <= 1'b0;\r
+                       data_out[8]  <= 1'b0;\r
+       end\r
+endmodule\r
+\r
+\r
+module regs_hb (\r
+       rst_n,\r
+       hclk,\r
+       gbe_mode,\r
+       sgmii_mode,\r
+       hcs_n,\r
+       hwrite_n,\r
+       haddr,\r
+       hdatain,\r
+\r
+       hdataout,\r
+       hready_n,\r
+\r
+       mr_stat_1000base_x_fd,\r
+       mr_stat_1000base_x_hd,\r
+       mr_stat_1000base_t_fd,\r
+       mr_stat_1000base_t_hd,\r
+\r
+       mr_stat_100base_t4,\r
+       mr_stat_100base_x_fd,\r
+       mr_stat_100base_x_hd,\r
+       mr_stat_10mbps_fd,\r
+       mr_stat_10mbps_hd,\r
+       mr_stat_100base_t2_fd,\r
+       mr_stat_100base_t2_hd,\r
+\r
+       mr_stat_extended_stat,\r
+       mr_stat_unidir_able,\r
+       mr_stat_preamb_supr,\r
+       mr_stat_an_complete,\r
+       mr_stat_remote_fault,\r
+       mr_stat_an_able,\r
+       mr_stat_link_stat,\r
+       mr_stat_jab_det,\r
+       mr_stat_extended_cap,\r
+\r
+       mr_page_rx,\r
+       mr_lp_adv_ability,\r
+\r
+       mr_main_reset,\r
+       mr_loopback_enable,\r
+       mr_speed_selection,\r
+       mr_an_enable,\r
+       mr_power_down,\r
+       mr_isolate,\r
+       mr_restart_an,\r
+       mr_duplex_mode,\r
+       mr_col_test,\r
+       mr_unidir_enable,\r
+       mr_adv_ability\r
+);\r
+\r
+input           rst_n;\r
+input           hclk;\r
+input           gbe_mode;\r
+input           sgmii_mode;\r
+input           hcs_n;\r
+input           hwrite_n;\r
+input    [5:0]  haddr;\r
+input    [7:0]  hdatain;\r
+\r
+output   [7:0]  hdataout;\r
+output          hready_n;\r
+\r
+input           mr_stat_1000base_x_fd;\r
+input           mr_stat_1000base_x_hd;\r
+input           mr_stat_1000base_t_fd;\r
+input           mr_stat_1000base_t_hd;\r
+\r
+input           mr_stat_100base_t4;\r
+input           mr_stat_100base_x_fd;\r
+input           mr_stat_100base_x_hd;\r
+input           mr_stat_10mbps_fd;\r
+input           mr_stat_10mbps_hd;\r
+input           mr_stat_100base_t2_fd;\r
+input           mr_stat_100base_t2_hd;\r
+\r
+input           mr_stat_extended_stat;\r
+input           mr_stat_unidir_able;\r
+input           mr_stat_preamb_supr;\r
+input           mr_stat_an_complete;\r
+input           mr_stat_remote_fault;\r
+input           mr_stat_an_able;\r
+input           mr_stat_link_stat;\r
+input           mr_stat_jab_det;\r
+input           mr_stat_extended_cap;\r
+\r
+input           mr_page_rx;\r
+input    [15:0] mr_lp_adv_ability;\r
+\r
+output          mr_main_reset;\r
+output          mr_loopback_enable;\r
+output [1:0]    mr_speed_selection;\r
+output          mr_an_enable;\r
+output          mr_power_down;\r
+output          mr_isolate;\r
+output          mr_restart_an;\r
+output          mr_duplex_mode;\r
+output          mr_col_test;\r
+output          mr_unidir_enable;\r
+output   [15:0] mr_adv_ability;\r
+\r
+///////////////////////////////////\r
+\r
+\r
+\r
+reg   [7:0]  hdataout;\r
+reg hr;\r
+reg hready_n;\r
+\r
+reg hcs_n_delayed;\r
+\r
+wire reg0_cs_0;\r
+wire reg0_cs_1;\r
+\r
+wire reg1_cs_0;\r
+wire reg1_cs_1;\r
+\r
+wire reg4_cs_0;\r
+wire reg4_cs_1;\r
+\r
+wire reg5_cs_0;\r
+wire reg5_cs_1;\r
+\r
+wire reg6_cs_0;\r
+wire reg6_cs_1;\r
+\r
+wire regf_cs_0;\r
+wire regf_cs_1;\r
+\r
+wire [15:0] data_out_reg_0;\r
+wire [15:0] data_out_reg_1;\r
+wire [15:0] data_out_reg_4;\r
+wire [15:0] data_out_reg_5;\r
+wire [15:0] data_out_reg_6;\r
+wire [15:0] data_out_reg_f;\r
+\r
+\r
+\r
+register_addr_decoder ad_dec (\r
+       .rst_n(rst_n),\r
+       .addr(haddr),\r
+       .cs_in(~hcs_n),\r
+\r
+       .reg0_cs_0 (reg0_cs_0),\r
+       .reg0_cs_1 (reg0_cs_1),\r
+       .reg1_cs_0 (reg1_cs_0),\r
+       .reg1_cs_1 (reg1_cs_1),\r
+       .reg4_cs_0 (reg4_cs_0),\r
+       .reg4_cs_1 (reg4_cs_1),\r
+       .reg5_cs_0 (reg5_cs_0),\r
+       .reg5_cs_1 (reg5_cs_1),\r
+       .reg6_cs_0 (reg6_cs_0),\r
+       .reg6_cs_1 (reg6_cs_1),\r
+       .regf_cs_0 (regf_cs_0),\r
+       .regf_cs_1 (regf_cs_1)\r
+);\r
+\r
+\r
+register_0_hb   register_0 (\r
+       .rst_n (rst_n),\r
+       .clk (hclk), \r
+       .gbe_mode (gbe_mode),\r
+       .cs_0 (reg0_cs_0),\r
+       .cs_1 (reg0_cs_1),\r
+       .write (~hwrite_n),\r
+       .ready (1'b1),\r
+       .data_in ({hdatain, hdatain}),\r
+\r
+       .data_out (data_out_reg_0),\r
+       .mr_main_reset (mr_main_reset),\r
+       .mr_loopback_enable (mr_loopback_enable),\r
+       .mr_speed_selection (mr_speed_selection),\r
+       .mr_an_enable (mr_an_enable),\r
+       .mr_power_down (mr_power_down),\r
+       .mr_isolate (mr_isolate),\r
+       .mr_restart_an (mr_restart_an),\r
+       .mr_duplex_mode (mr_duplex_mode),\r
+       .mr_col_test (mr_col_test),\r
+       .mr_unidir_enable (mr_unidir_enable)\r
+);\r
+\r
+\r
+register_1_hb   register_1 (\r
+       .rst_n (rst_n),\r
+       .clk (hclk), \r
+       .cs_0 (reg1_cs_0),\r
+       .cs_1 (reg1_cs_1),\r
+       .write (~hwrite_n),\r
+       .ready (1'b1),\r
+\r
+       .mr_stat_100base_t4 (mr_stat_100base_t4),\r
+       .mr_stat_100base_x_fd (mr_stat_100base_x_fd),\r
+       .mr_stat_100base_x_hd (mr_stat_100base_x_hd),\r
+       .mr_stat_10mbps_fd (mr_stat_10mbps_fd),\r
+       .mr_stat_10mbps_hd (mr_stat_10mbps_hd),\r
+       .mr_stat_100base_t2_fd (mr_stat_100base_t2_fd),\r
+       .mr_stat_100base_t2_hd (mr_stat_100base_t2_hd),\r
+\r
+       .mr_stat_extended_stat (mr_stat_extended_stat),\r
+       .mr_stat_unidir_able (mr_stat_unidir_able),\r
+       .mr_stat_preamb_supr (mr_stat_preamb_supr),\r
+       .mr_stat_an_complete (mr_stat_an_complete),\r
+       .mr_stat_remote_fault (mr_stat_remote_fault),\r
+       .mr_stat_an_able (mr_stat_an_able),\r
+       .mr_stat_link_stat (mr_stat_link_stat),\r
+       .mr_stat_jab_det (mr_stat_jab_det),\r
+       .mr_stat_extended_cap (mr_stat_extended_cap),\r
+\r
+       .data_out (data_out_reg_1)\r
+);\r
+\r
+\r
+register_4_hb   register_4 (\r
+       .rst_n (rst_n),\r
+       .clk (hclk), \r
+       .gbe_mode (gbe_mode),\r
+       .sgmii_mode (sgmii_mode),\r
+       .cs_0 (reg4_cs_0),\r
+       .cs_1 (reg4_cs_1),\r
+       .write (~hwrite_n),\r
+       .ready (1'b1),\r
+       .data_in ({hdatain, hdatain}),\r
+\r
+       .data_out (data_out_reg_4),\r
+       .mr_adv_ability (mr_adv_ability)\r
+);\r
+\r
+\r
+register_5_hb   register_5 (\r
+       .rst_n (rst_n),\r
+       .mr_lp_adv_ability (mr_lp_adv_ability),\r
+       .cs_0 (reg5_cs_0),\r
+       .cs_1 (reg5_cs_1),\r
+       .ready (1'b1),\r
+\r
+       .data_out (data_out_reg_5)\r
+);\r
+\r
+\r
+register_6_hb   register_6 (\r
+       .rst_n (rst_n),\r
+       .clk (hclk), \r
+       .mr_page_rx (mr_page_rx),\r
+       .cs_0 (reg6_cs_0),\r
+       .cs_1 (reg6_cs_1),\r
+       .write (~hwrite_n),\r
+       .ready (1'b1),\r
+\r
+       .data_out (data_out_reg_6)\r
+);\r
+\r
+\r
+\r
+register_f_hb   register_f (\r
+       .rst_n (rst_n),\r
+       .cs_0 (regf_cs_0),\r
+       .cs_1 (regf_cs_1),\r
+\r
+       .mr_stat_1000base_x_fd (mr_stat_1000base_x_fd),\r
+       .mr_stat_1000base_x_hd (mr_stat_1000base_x_hd),\r
+       .mr_stat_1000base_t_fd (mr_stat_1000base_t_fd),\r
+       .mr_stat_1000base_t_hd (mr_stat_1000base_t_hd),\r
+\r
+       .data_out (data_out_reg_f)\r
+);\r
+\r
+\r
+// generate an ack\r
+always @(posedge hclk or negedge rst_n) begin\r
+       if (rst_n == 1'b0) begin\r
+               hcs_n_delayed <= 1'b1;\r
+               hr <= 1'b1;\r
+               hready_n <= 1'b1;\r
+       end\r
+       else begin\r
+               hcs_n_delayed <= hcs_n;\r
+\r
+               //assert on falling edge of delayed chip select\r
+               hr <= ~hcs_n & hcs_n_delayed;\r
+               hready_n <= ~hr;\r
+       end\r
+end\r
+\r
+\r
+\r
+// Mux Register Read-Data Outputs\r
+always @(posedge hclk or negedge rst_n)\r
+begin\r
+       if (rst_n == 1'b0) begin\r
+               hdataout <= 8'd0;\r
+       end\r
+       else begin\r
+               case (haddr[5:0])\r
+\r
+                       6'd0:\r
+                         begin\r
+                               hdataout <= data_out_reg_0[7:0];\r
+                         end\r
+\r
+\r
+                       6'd1:\r
+                         begin\r
+                               hdataout <= data_out_reg_0[15:8];\r
+                         end\r
+\r
+                       /////////////////////////////////////////////\r
+\r
+                       6'd2:\r
+                         begin\r
+                               hdataout <= data_out_reg_1[7:0];\r
+                         end\r
+\r
+\r
+                       6'd3:\r
+                         begin\r
+                               hdataout <= data_out_reg_1[15:8];\r
+                         end\r
+\r
+                       /////////////////////////////////////////////\r
+\r
+                       6'd8:\r
+                         begin\r
+                               hdataout <= data_out_reg_4[7:0];\r
+                         end\r
+\r
+\r
+                       6'd9:\r
+                         begin\r
+                               hdataout <= data_out_reg_4[15:8];\r
+                         end\r
+\r
+                       /////////////////////////////////////////////\r
+\r
+                       6'd10:\r
+                         begin\r
+                               hdataout <= data_out_reg_5[7:0];\r
+                         end\r
+\r
+\r
+                       6'd11:\r
+                         begin\r
+                               hdataout <= data_out_reg_5[15:8];\r
+                         end\r
+\r
+                       /////////////////////////////////////////////\r
+\r
+                       6'd12:\r
+                         begin\r
+                               hdataout <= data_out_reg_6[7:0];\r
+                         end\r
+\r
+\r
+                       6'd13:\r
+                         begin\r
+                               hdataout <= data_out_reg_6[15:8];\r
+                         end\r
+\r
+                       /////////////////////////////////////////////\r
+\r
+                       6'd30:\r
+                         begin\r
+                               hdataout <= data_out_reg_f[7:0];\r
+                         end\r
+\r
+\r
+                       6'd31:\r
+                         begin\r
+                               hdataout <= data_out_reg_f[15:8];\r
+                         end\r
+\r
+                       /////////////////////////////////////////////\r
+\r
+                       default:\r
+                         begin\r
+                               hdataout <= 8'd0;\r
+                         end\r
+               endcase\r
+       end\r
+end\r
+\r
+endmodule\r
+\r
+module register_addr_decoder (\r
+       rst_n,\r
+       addr,\r
+       cs_in,\r
+\r
+       reg0_cs_0,\r
+       reg0_cs_1,\r
+\r
+       reg1_cs_0,\r
+       reg1_cs_1,\r
+\r
+       reg4_cs_0,\r
+       reg4_cs_1,\r
+\r
+       reg5_cs_0,\r
+       reg5_cs_1,\r
+\r
+       reg6_cs_0,\r
+       reg6_cs_1,\r
+\r
+       regf_cs_0,\r
+       regf_cs_1\r
+);\r
+\r
+input           rst_n;\r
+input           cs_in;\r
+input [5:0]     addr;\r
+\r
+output          reg0_cs_0;\r
+output          reg0_cs_1;\r
+\r
+output          reg1_cs_0;\r
+output          reg1_cs_1;\r
+\r
+output          reg4_cs_0;\r
+output          reg4_cs_1;\r
+\r
+output          reg5_cs_0;\r
+output          reg5_cs_1;\r
+\r
+output          reg6_cs_0;\r
+output          reg6_cs_1;\r
+\r
+output          regf_cs_0;\r
+output          regf_cs_1;\r
+\r
+//////////////////////////\r
+\r
+wire             reg0_cs_0;\r
+wire             reg0_cs_1;\r
+\r
+wire             reg1_cs_0;\r
+wire             reg1_cs_1;\r
+\r
+wire             reg4_cs_0;\r
+wire             reg4_cs_1;\r
+\r
+wire             reg5_cs_0;\r
+wire             reg5_cs_1;\r
+\r
+wire             reg6_cs_0;\r
+wire             reg6_cs_1;\r
+\r
+wire             regf_cs_0;\r
+wire             regf_cs_1;\r
+\r
+//////////////////////////\r
+\r
+assign reg0_cs_0 = (addr == 6'h00) ? cs_in : 1'b0;\r
+assign reg0_cs_1 = (addr == 6'h01) ? cs_in : 1'b0;\r
+\r
+assign reg1_cs_0 = (addr == 6'h02) ? cs_in : 1'b0;\r
+assign reg1_cs_1 = (addr == 6'h03) ? cs_in : 1'b0;\r
+\r
+assign reg4_cs_0 = (addr == 6'h08) ? cs_in : 1'b0;\r
+assign reg4_cs_1 = (addr == 6'h09) ? cs_in : 1'b0;\r
+\r
+assign reg5_cs_0 = (addr == 6'h0a) ? cs_in : 1'b0;\r
+assign reg5_cs_1 = (addr == 6'h0b) ? cs_in : 1'b0;\r
+\r
+assign reg6_cs_0 = (addr == 6'h0c) ? cs_in : 1'b0;\r
+assign reg6_cs_1 = (addr == 6'h0d) ? cs_in : 1'b0;\r
+\r
+assign regf_cs_0 = (addr == 6'h1e) ? cs_in : 1'b0;\r
+assign regf_cs_1 = (addr == 6'h1f) ? cs_in : 1'b0;\r
+\r
+\r
+endmodule\r
+\r

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/src/rtl/template/ecp5um/sgmii_channel_smi.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/src/rtl/template/ecp5um/sgmii_channel_smi.v
new file mode 100644 (file)
index 0000000..54ee87a
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/src/rtl/template/ecp5um/sgmii_channel_smi.v
@@ -0,0 +1,280 @@
+//**************************************************************************\r
+// *************************************************************************\r
+// *                LATTICE SEMICONDUCTOR CONFIDENTIAL                     *\r
+// *                         PROPRIETARY NOTE                              *\r
+// *                                                                       *\r
+// *  This software contains information confidential and proprietary      *\r
+// *  to Lattice Semiconductor Corporation.  It shall not be reproduced    *\r
+// *  in whole or in part, or transferred to other documents, or disclosed *\r
+// *  to third parties, or used for any purpose other than that for which  *\r
+// *  it was obtained, without the prior written consent of Lattice        *\r
+// *  Semiconductor Corporation.  All rights reserved.                     *\r
+// *                                                                       *\r
+// *************************************************************************\r
+//**************************************************************************\r
+\r
+`timescale 1ns/100ps\r
+\r
+module sgmii_channel_smi (\r
+\r
+       // Control Interface\r
+       rst_n,\r
+       gbe_mode,\r
+       sgmii_mode,\r
+       signal_detect,\r
+       debug_link_timer_short,\r
+       rx_compensation_err,\r
+\r
+       // G/MII Interface\r
+       in_clk_gmii,\r
+       in_clk_mii,\r
+       data_in_mii,\r
+       en_in_mii,\r
+       err_in_mii,\r
+\r
+       out_clk_gmii,\r
+       out_clk_mii,\r
+       data_out_mii,\r
+       dv_out_mii,\r
+       err_out_mii,\r
+       col_out_mii,\r
+       crs_out_mii,\r
+\r
+       // 8-bit Interface\r
+       data_out_8bi,\r
+       kcntl_out_8bi,\r
+       disparity_cntl_out_8bi,\r
+\r
+       serdes_recovered_clk,\r
+       data_in_8bi,\r
+       kcntl_in_8bi,\r
+       even_in_8bi,\r
+       disp_err_in_8bi,\r
+       cv_err_in_8bi,\r
+       err_decode_mode_8bi,\r
+\r
+       // MDIO Port\r
+       mdc,\r
+       mdio,\r
+       port_id\r
+   );\r
+\r
+\r
+\r
+// I/O Declarations\r
+input         rst_n ;       // System Reset, Active Low\r
+input         signal_detect ;\r
+input         gbe_mode ;  // GBE Mode   (0=SGMII    1=GBE)\r
+input         sgmii_mode ;  // SGMII PCS Mode   (0=MAC    1=PHY)\r
+input         debug_link_timer_short ;  // (0=NORMAL    1=SHORT)\r
+output        rx_compensation_err;  // Active high pulse indicating RX_CTC_FIFO either underflowed or overflowed\r
+\r
+input         in_clk_mii ;      // G/MII Transmit clock 2.5Mhz/25Mhz/125Mhz \r
+input [7:0]   data_in_mii ;        // G/MII Tx data\r
+input         en_in_mii ;       // G/MII data valid\r
+input         err_in_mii ;       // G/MII Tx error\r
+\r
+input         out_clk_mii ;      // G/MII Receice clock 2.5Mhz/25Mhz/125MHz \r
+output [7:0]   data_out_mii ;       // G/MII Rx data\r
+output         dv_out_mii ;      // G/MII Rx data valid\r
+output         err_out_mii ;      // G/MII Rx error\r
+output         col_out_mii ;        // G/MII collision detect \r
+output         crs_out_mii ;        // G/MII carrier sense detect \r
+\r
+output [7:0]   data_out_8bi ;            // 8BI Tx Data\r
+output         kcntl_out_8bi ;           // 8BI Tx Kcntl\r
+output         disparity_cntl_out_8bi ;  // 8BI Tx Kcntl\r
+\r
+input         serdes_recovered_clk ;\r
+input [7:0]   data_in_8bi  ;     // 8BI Rx Data\r
+input         kcntl_in_8bi ;     // 8BI Rx Kcntl\r
+input         even_in_8bi ;      // 8BI Rx Even\r
+input         disp_err_in_8bi ;  // 8BI Rx Disparity Error\r
+input         cv_err_in_8bi ;    // 8BI Rx Coding Violation Error\r
+input         err_decode_mode_8bi ; // 8BI Error Decode Mode (0=NORMAL,  1=DECODE_MODE)\r
+\r
+input         in_clk_gmii ;     // GMII Transmit clock 125Mhz\r
+input         out_clk_gmii ;     // GMII Receive clock 125Mhz\r
+\r
+input          mdc;\r
+inout          mdio;\r
+input [4:0]    port_id;\r
+\r
+\r
+wire           mdin;\r
+wire           mdout;\r
+wire           mdout_en;\r
+\r
+// Internal Signals \r
+\r
+wire           mr_an_complete;\r
+wire           mr_page_rx;\r
+wire [15:0]    mr_lp_adv_ability;\r
+\r
+wire           mr_main_reset;\r
+wire           mr_an_enable;\r
+wire           mr_restart_an;\r
+wire [15:0]    mr_adv_ability;\r
+wire           mr_loopback_enable;\r
+wire [1:0]     mr_speed_selection;\r
+wire           mr_power_down;\r
+wire           mr_isolate;\r
+wire           mr_duplex_mode;\r
+wire           mr_col_test;\r
+wire           mr_unidir_enable;\r
+wire           an_link_ok;\r
+\r
+wire [1:0]     operational_rate;\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+// SGMII PCS\r
+USER_NAME USER_NAME_U (\r
+       // Clock and Reset\r
+       .rst_n (rst_n ),\r
+       .signal_detect (signal_detect),\r
+       .gbe_mode (gbe_mode),\r
+       .sgmii_mode (sgmii_mode),\r
+       .debug_link_timer_short (debug_link_timer_short), \r
+       .force_isolate (mr_isolate), \r
+       .force_loopback (mr_loopback_enable), \r
+       .force_unidir (mr_unidir_enable), \r
+       .operational_rate (operational_rate),\r
+       .rx_compensation_err (rx_compensation_err),\r
+       .ctc_drop_flag (),\r
+       .ctc_add_flag (),\r
+       .an_link_ok (an_link_ok),\r
+       .tx_clk_125 (in_clk_gmii),\r
+       .serdes_recovered_clk (serdes_recovered_clk),\r
+       .rx_clk_125 (out_clk_gmii),\r
+\r
+       // Control\r
+\r
+\r
+       // (G)MII TX Port\r
+       .tx_clk_mii (in_clk_mii),\r
+       .tx_d (data_in_mii),\r
+       .tx_en (en_in_mii),\r
+       .tx_er (err_in_mii),\r
+\r
+       // (G)MII RX Port\r
+       .rx_clk_mii (out_clk_mii),\r
+       .rx_d (data_out_mii),\r
+       .rx_dv (dv_out_mii),\r
+       .rx_er (err_out_mii),\r
+       .col (col_out_mii),\r
+       .crs (crs_out_mii),\r
+                  \r
+       // 8BI TX Port\r
+       .tx_data (data_out_8bi),\r
+       .tx_kcntl (kcntl_out_8bi),\r
+       .tx_disparity_cntl (disparity_cntl_out_8bi),\r
+       .xmit_autoneg (),\r
+\r
+       // 8BI RX Port\r
+       .rx_data (data_in_8bi),\r
+       .rx_kcntl (kcntl_in_8bi),\r
+       .rx_even (even_in_8bi),\r
+       .rx_disp_err (disp_err_in_8bi),\r
+       .rx_cv_err (cv_err_in_8bi),\r
+       .rx_err_decode_mode (err_decode_mode_8bi),\r
+\r
+       // Management Interface  I/O\r
+       .mr_adv_ability (mr_adv_ability),\r
+       .mr_an_enable (mr_an_enable), \r
+       .mr_main_reset (mr_main_reset),  \r
+       .mr_restart_an (mr_restart_an),   \r
+\r
+       .mr_an_complete (mr_an_complete),   \r
+       .mr_lp_adv_ability (mr_lp_adv_ability), \r
+       .mr_page_rx (mr_page_rx)\r
+       );\r
+\r
+\r
+\r
+// SMI Register Interface for SGMII IP Core\r
+register_interface_smi   ri (\r
+\r
+       // Control Signals\r
+       .rst_n (rst_n),\r
+       .gbe_mode (gbe_mode),\r
+       .sgmii_mode (sgmii_mode),\r
+\r
+       // MDIO Port\r
+       .mdc (mdc),\r
+       .mdin (mdin),\r
+       .mdout (mdout),\r
+       .mdout_en (mdout_en),\r
+       .port_id (port_id),\r
+\r
+       // Register Outputs\r
+       .mr_main_reset (mr_main_reset),\r
+       .mr_loopback_enable (mr_loopback_enable),\r
+       .mr_speed_selection (mr_speed_selection),\r
+       .mr_an_enable (mr_an_enable),\r
+       .mr_power_down (mr_power_down),\r
+       .mr_isolate (mr_isolate),\r
+       .mr_restart_an (mr_restart_an),\r
+       .mr_duplex_mode (mr_duplex_mode),\r
+       .mr_col_test (mr_col_test),\r
+       .mr_unidir_enable (mr_unidir_enable),\r
+\r
+       .mr_adv_ability (mr_adv_ability),\r
+\r
+       // Register Inputs\r
+       .mr_stat_1000base_x_fd (1'b1),  // SUPPORTED \r
+       .mr_stat_1000base_x_hd (1'b0),\r
+       .mr_stat_1000base_t_fd (1'b0),\r
+       .mr_stat_1000base_t_hd (1'b0),\r
+\r
+       .mr_stat_100base_t4 (1'b0),\r
+       .mr_stat_100base_x_fd (1'b0),\r
+       .mr_stat_100base_x_hd (1'b0),\r
+       .mr_stat_10mbps_fd (1'b0),\r
+       .mr_stat_10mbps_hd (1'b0),\r
+       .mr_stat_100base_t2_fd (1'b0),\r
+       .mr_stat_100base_t2_hd (1'b0),\r
+\r
+       .mr_stat_extended_stat (1'b1),  // SUPPORTED\r
+       .mr_stat_unidir_able (mr_unidir_enable),\r
+       .mr_stat_preamb_supr (1'b0),\r
+       .mr_stat_an_complete (mr_an_complete),\r
+       .mr_stat_remote_fault (1'b0),\r
+       .mr_stat_an_able (1'b1),        // SUPPORTED\r
+       .mr_stat_link_stat (an_link_ok),\r
+       .mr_stat_jab_det (1'b0),\r
+       .mr_stat_extended_cap (1'b0),\r
+\r
+       .mr_page_rx (mr_page_rx),\r
+       .mr_lp_adv_ability (mr_lp_adv_ability)\r
+       );\r
+\r
+\r
+\r
+// (G)MII Rate Resolution for SGMII IP Core\r
+rate_resolution   rate_resolution (\r
+       .gbe_mode (gbe_mode),\r
+       .sgmii_mode (sgmii_mode),\r
+       .an_enable (mr_an_enable),\r
+       .advertised_rate (mr_adv_ability[11:10]),\r
+       .link_partner_rate (mr_lp_adv_ability[11:10]),\r
+       .non_an_rate (mr_speed_selection), // speed selected when auto-negotiation disabled\r
+\r
+       .operational_rate (operational_rate)\r
+);\r
+\r
+\r
+\r
+\r
+\r
+// Bidirectional Assignments\r
+assign mdio = mdout_en ? mdout : 1'bz; // MDIO Output\r
+assign mdin = mdio;                   // MDIO Input\r
+\r
+endmodule\r
+\r

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/src/rtl/top/ecp5um/top_hb.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/src/rtl/top/ecp5um/top_hb.v
new file mode 100644 (file)
index 0000000..cba77f6
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/src/rtl/top/ecp5um/top_hb.v
@@ -0,0 +1,404 @@
+//**************************************************************************\r
+// *************************************************************************\r
+// *                LATTICE SEMICONDUCTOR CONFIDENTIAL                     *\r
+// *                         PROPRIETARY NOTE                              *\r
+// *                                                                       *\r
+// *  This software contains information confidential and proprietary      *\r
+// *  to Lattice Semiconductor Corporation.  It shall not be reproduced    *\r
+// *  in whole or in part, or transferred to other documents, or disclosed *\r
+// *  to third parties, or used for any purpose other than that for which  *\r
+// *  it was obtained, without the prior written consent of Lattice        *\r
+// *  Semiconductor Corporation.  All rights reserved.                     *\r
+// *                                                                       *\r
+// *************************************************************************\r
+//**************************************************************************\r
+\r
+`timescale 1ns/100ps\r
+\r
+module top_hb (\r
+\r
+       // G/MII Interface\r
+       data_in_mii,\r
+       en_in_mii,\r
+       err_in_mii,\r
+\r
+       data_out_mii,\r
+       dv_out_mii,\r
+       err_out_mii,\r
+       col_out_mii,\r
+       crs_out_mii,\r
+\r
+       // GB Timing References\r
+       in_clk_125,\r
+       in_ce_sink,\r
+       in_ce_source,\r
+       out_clk_125,\r
+       out_ce_sink,\r
+       out_ce_source,\r
+\r
+       // SERIAL GMII Interface \r
+       refclkp,\r
+       refclkn,\r
+       hdinp0, \r
+       hdinn0, \r
+       hdoutp0, \r
+       hdoutn0,\r
+       \r
+       // Control Interface\r
+       gbe_mode,\r
+       sgmii_mode,\r
+       rst_n,\r
+\r
+       // Host Bus\r
+       hclk,\r
+       hcs_n,\r
+       hwrite_n,\r
+       haddr,\r
+       hdatain,\r
+\r
+       hdataout,\r
+       hready_n,\r
+       \r
+       //Debug Port\r
+       debug_link_timer_short,\r
+       mr_an_complete\r
+       );\r
+\r
+\r
+\r
+// I/O Declarations\r
+input          rst_n;          // System Reset, Active Low\r
+input          hclk;\r
+input           gbe_mode ;      // GBE Mode       (0=SGMII  1=GBE)\r
+input           sgmii_mode ;    // SGMII PCS Mode (0=MAC    1=PHY)\r
+\r
+input          in_clk_125 ;    // GMII Input Data Path clock 125Mhz\r
+input          in_ce_sink ;\r
+output         in_ce_source ;\r
+input [7:0]    data_in_mii;    // G/MII Incoming Data\r
+input          en_in_mii;      // G/MII Incoming Data Valid\r
+input          err_in_mii;     // G/MII Incoming Error\r
+\r
+input          out_clk_125 ;    // GMII Output Data Path clock 125Mhz\r
+input          out_ce_sink ;\r
+output         out_ce_source ;\r
+output [7:0]   data_out_mii;   // G/MII Outgoing Data\r
+output         dv_out_mii;     // G/MII Outgoing Data Valid\r
+output         err_out_mii;    // G/MII Outgoing Error\r
+output         col_out_mii;    // G/MII Collision Detect \r
+output         crs_out_mii;    // G/MII Carrier Sense Detect \r
+\r
+input          refclkp;\r
+input          refclkn;\r
+// exemplar attribute refclkp NOPAD true\r
+// exemplar attribute refclkn NOPAD true\r
+\r
+input          hdinp0;         // Incoming SGMII (on SERDES)\r
+input          hdinn0;         // Incoming SGMII (on SERDES)\r
+// exemplar attribute hdinp0 NOPAD true\r
+// exemplar attribute hdinn0 NOPAD true\r
+\r
+output         hdoutp0;        // Outgoing SGMII (on SERDES)\r
+output         hdoutn0;        // Outgoing SGMII (on SERDES)\r
+// exemplar attribute hdoutp0 NOPAD true\r
+// exemplar attribute hdoutn0 NOPAD true\r
+\r
+input           hcs_n;\r
+input           hwrite_n;\r
+input    [5:0]  haddr;\r
+input    [7:0]  hdatain;\r
+\r
+output   [7:0]  hdataout;\r
+output          hready_n;\r
+\r
+input            debug_link_timer_short;\r
+output          mr_an_complete;\r
+\r
+// Primary G/MII Outputs -- Latched Before Leaving FPGA\r
+reg [7:0]      data_out_mii;\r
+reg            dv_out_mii;\r
+reg            err_out_mii;\r
+reg            col_out_mii;\r
+reg            crs_out_mii;\r
+\r
+// G/MII Signals from input latches to SGMII channel\r
+reg [7:0]      data_buf2chan;\r
+reg            en_buf2chan;\r
+reg            err_buf2chan;\r
+\r
+// G/MII Signals from SGMII channel to output latches\r
+wire [7:0]     data_chan2buf;\r
+wire           dv_chan2buf;\r
+wire           err_chan2buf;\r
+wire           col_chan2buf;\r
+wire           crs_chan2buf;\r
+\r
+//  8-bit Interface Signals from SGMII channel to QuadPCS/SERDES\r
+//wire [7:0]   data_chan2quad;\r
+//wire                 kcntl_chan2quad;\r
+//wire                 disparity_cntl_chan2quad;\r
+//wire                 xmit_autoneg;\r
+\r
+//  8-bit Interface Signals from QuadPCS/SERDES to SGMII channel\r
+//wire [7:0]   data_quad2chan;\r
+//wire         kcntl_quad2chan;\r
+//wire         disp_err_quad2chan;\r
+//wire         cv_err_quad2chan;\r
+//wire         link_status;\r
+//wire         serdes_recovered_clk;\r
+wire           clk_125;\r
+\r
+// Misc Signals\r
+wire mdin;\r
+wire mdout;\r
+wire mdout_en;\r
+\r
+wire mr_an_enable;\r
+wire mr_restart_an;\r
+wire [15:0] mr_adv_ability;\r
+\r
+wire mr_an_complete;\r
+wire mr_page_rx;\r
+wire [15:0] mr_lp_adv_ability;\r
+wire mr_main_reset;\r
+wire mr_loopback_enable;\r
+wire [1:0] mr_speed_selection;\r
+wire mr_power_down;\r
+wire mr_isolate;\r
+wire mr_duplex_mode;\r
+wire mr_col_test;\r
+wire mr_unidir_enable;\r
+wire an_link_ok;\r
+\r
+wire debug_link_timer_short;\r
+wire [1:0] operational_rate;\r
+\r
+wire tx_pll_lol;\r
+wire rx_cdr_lol;\r
+wire quad_rst;\r
+wire tx_pcs_rst;\r
+wire rx_pcs_rst;\r
+wire rx_serdes_rst;\r
+\r
+wire nc_1;\r
+wire nc_2;\r
+wire nc_3;\r
+\r
+wire sli_rst;\r
+wire serdes_rst_dual_c;\r
+wire tx_serdes_rst_c;\r
+wire serdes_pdb;\r
+wire tx_pwrup_c;\r
+\r
+assign sli_rst = serdes_rst_dual_c ||  tx_serdes_rst_c ||  (!serdes_pdb) ||  (!tx_pwrup_c);\r
+  \r
+\r
+//  Active High Reset\r
+wire           rst;\r
+assign rst = ~rst_n;\r
+\r
+// Instantiate Global Reset Controller\r
+GSR GSR_INST   (.GSR(rst_n));\r
+PUR PUR_INST   (.PUR(1'b1));\r
+\r
+// Buffer Incoming MII Data at Primary I/O\r
+always @(posedge in_clk_125 or negedge rst_n)\r
+begin\r
+       if (rst_n == 1'b0) begin\r
+               data_buf2chan <= 8'd0;\r
+               en_buf2chan <= 0;\r
+               err_buf2chan <= 0;\r
+       end\r
+       else begin\r
+               data_buf2chan <= data_in_mii;\r
+               en_buf2chan <= en_in_mii;\r
+               err_buf2chan <= err_in_mii;\r
+       end\r
+end \r
+\r
+// Buffer Outgoing MII Data at Primary I/O\r
+always @(posedge out_clk_125 or negedge rst_n)\r
+begin\r
+       if (rst_n == 1'b0) begin\r
+               data_out_mii <= 8'd0;\r
+               dv_out_mii <= 0;\r
+               err_out_mii <= 0;\r
+               col_out_mii <= 0;\r
+               crs_out_mii <= 0;\r
+       end\r
+       else begin\r
+               data_out_mii <= data_chan2buf;\r
+               dv_out_mii <= dv_chan2buf;\r
+               err_out_mii <= err_chan2buf;\r
+               col_out_mii <= col_chan2buf;\r
+               crs_out_mii <= crs_chan2buf;\r
+       end\r
+end \r
+\r
+\r
+// Host Bus Register Interface for SGMII IP Core\r
+register_interface_hb   ri (\r
+\r
+       // Control Signals\r
+       .rst_n (rst_n),\r
+       .hclk (hclk),\r
+       .gbe_mode (gbe_mode),\r
+       .sgmii_mode (sgmii_mode),\r
+\r
+       // Host Bus\r
+       .hcs_n (hcs_n),\r
+       .hwrite_n (hwrite_n),\r
+       .haddr (haddr),\r
+       .hdatain (hdatain),\r
+\r
+       .hdataout (hdataout),\r
+       .hready_n (hready_n),\r
+\r
+       // Register Outputs\r
+       .mr_main_reset (mr_main_reset),\r
+       .mr_loopback_enable (mr_loopback_enable),\r
+       .mr_speed_selection (mr_speed_selection),\r
+       .mr_an_enable (mr_an_enable),\r
+       .mr_power_down (mr_power_down),\r
+       .mr_isolate (mr_isolate),\r
+       .mr_restart_an (mr_restart_an),\r
+       .mr_duplex_mode (mr_duplex_mode),\r
+       .mr_col_test (mr_col_test),\r
+       .mr_unidir_enable (mr_unidir_enable),\r
+\r
+       .mr_adv_ability (mr_adv_ability),\r
+\r
+       // Register Inputs\r
+       .mr_stat_1000base_x_fd (1'b1),  // SUPPORTED \r
+       .mr_stat_1000base_x_hd (1'b0),\r
+       .mr_stat_1000base_t_fd (1'b0),\r
+       .mr_stat_1000base_t_hd (1'b0),\r
+\r
+       .mr_stat_100base_t4 (1'b0),\r
+       .mr_stat_100base_x_fd (1'b0),\r
+       .mr_stat_100base_x_hd (1'b0),\r
+       .mr_stat_10mbps_fd (1'b0),\r
+       .mr_stat_10mbps_hd (1'b0),\r
+       .mr_stat_100base_t2_fd (1'b0),\r
+       .mr_stat_100base_t2_hd (1'b0),\r
+\r
+       .mr_stat_extended_stat (1'b1),  // SUPPORTED\r
+       .mr_stat_unidir_able (mr_unidir_enable),\r
+       .mr_stat_preamb_supr (1'b0),\r
+       .mr_stat_an_complete (mr_an_complete),\r
+       .mr_stat_remote_fault (1'b0),\r
+       .mr_stat_an_able (1'b1),        // SUPPORTED\r
+       .mr_stat_link_stat (an_link_ok),\r
+       .mr_stat_jab_det (1'b0),\r
+       .mr_stat_extended_cap (1'b0),\r
+\r
+       .mr_page_rx (mr_page_rx),\r
+       .mr_lp_adv_ability (mr_lp_adv_ability)\r
+       );\r
+\r
+\r
+\r
+// (G)MII Rate Resolution for SGMII IP Core\r
+rate_resolution   rate_resolution (\r
+       .gbe_mode (gbe_mode),\r
+       .sgmii_mode (sgmii_mode),\r
+       .an_enable (mr_an_enable),\r
+       .advertised_rate (mr_adv_ability[11:10]),\r
+       .link_partner_rate (mr_lp_adv_ability[11:10]),\r
+       .non_an_rate (mr_speed_selection), // speed selected when auto-negotiation disabled\r
+\r
+       .operational_rate (operational_rate)\r
+);\r
+\r
+ILVDS ILVDS_X (\r
+  .A (refclkp), \r
+  .AN(refclkn), \r
+  .Z (clk_125)); \r
+\r
+sgmii_channel_smi u_sgmii(\r
+\r
+//-----------USERNAME CORE-------------PART PORTS\r
+       // Control Interface\r
+       .rst_n (rst_n),\r
+       .gbe_mode (gbe_mode),\r
+       .sgmii_mode (sgmii_mode),\r
+       .operational_rate (operational_rate),\r
+       .debug_link_timer_short (debug_link_timer_short), \r
+       .force_isolate (mr_isolate), \r
+       .force_loopback (mr_loopback_enable), \r
+       .force_unidir (mr_unidir_enable), \r
+  .tx_clock_enable_sink (in_ce_sink),\r
+       .tx_clock_enable_source (in_ce_source),\r
+       .rx_clock_enable_sink (out_ce_sink),\r
+       .rx_clock_enable_source (out_ce_source),\r
+\r
+       \r
+       .an_link_ok (an_link_ok),\r
+\r
+       // G/MII Interface\r
+       .tx_d(data_buf2chan),\r
+       .tx_en (en_buf2chan),\r
+       .tx_er (err_buf2chan),\r
+  .tx_clk_125(in_clk_125),\r
+  .rx_clk_125(out_clk_125),\r
+  .rx_d (data_chan2buf),\r
+       .rx_dv (dv_chan2buf),\r
+       .rx_er (err_chan2buf),\r
+       .col (col_chan2buf),\r
+       .crs (crs_chan2buf),\r
+       \r
+       // Managment Control Outputs\r
+       .mr_an_complete (mr_an_complete),   \r
+       .mr_lp_adv_ability (mr_lp_adv_ability), \r
+       .mr_page_rx (mr_page_rx),\r
+\r
+       // Managment Control Inputs\r
+       .mr_adv_ability (mr_adv_ability),\r
+       .mr_an_enable (mr_an_enable), \r
+       .mr_main_reset (mr_main_reset),  \r
+       .mr_restart_an (mr_restart_an), \r
+       \r
+//-----------USERNAME PCS-------------PART PORTS       \r
+       .hdinp(hdinp0), \r
+       .hdinn(hdinn0), \r
+       // outputs\r
+       .hdoutp(hdoutp0), \r
+       .hdoutn(hdoutn0), \r
+       \r
+  .sli_rst           (sli_rst),\r
+  .serdes_rst_dual_c (serdes_rst_dual_c),\r
+  .tx_serdes_rst_c   (tx_serdes_rst_c),\r
+  .serdes_pdb        (serdes_pdb),\r
+  .tx_pwrup_c        (tx_pwrup_c),\r
+  \r
+  \r
+  .pll_refclki (clk_125), \r
+  .rxrefclk    (clk_125), \r
+       \r
+       //SCI interface\r
+       .cyawstn      (1'b0),\r
+       .sci_en       (1'b0),\r
+       .sci_en_dual  (1'b0),\r
+       .sci_sel_dual (1'b0),\r
+       .sci_sel      (1'b0),\r
+       .sci_wrdata   (8'd0),\r
+       .sci_addr     (6'd0),\r
+       .sci_rddata   (),\r
+       .sci_rd       (1'b0),\r
+       .sci_wrn      (1'b1),\r
+       .sci_int      (),\r
+\r
+  .rx_cdr_lol_s    (rx_cdr_lol),\r
+        \r
+  .tx_pcs_rst_c    (1'b0),\r
+  .rx_pcs_rst_c    (1'b0),\r
+  .rx_serdes_rst_c (1'b0),\r
+      \r
+  .rst_dual_c      (~rst_n),\r
+  .pll_lol         (tx_pll_lol),\r
+  \r
+  //New added\r
+  .mr_power_down(mr_power_down)\r
+);\r
+endmodule\r
+\r

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/src/rtl/top/ecp5um/top_pcs_core_only.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/src/rtl/top/ecp5um/top_pcs_core_only.v
new file mode 100644 (file)
index 0000000..df7a705
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/sgmii_channel_smi/src/rtl/top/ecp5um/top_pcs_core_only.v
@@ -0,0 +1,203 @@
+//**************************************************************************\r
+// *************************************************************************\r
+// *                LATTICE SEMICONDUCTOR CONFIDENTIAL                     *\r
+// *                         PROPRIETARY NOTE                              *\r
+// *                                                                       *\r
+// *  This software contains information confidential and proprietary      *\r
+// *  to Lattice Semiconductor Corporation.  It shall not be reproduced    *\r
+// *  in whole or in part, or transferred to other documents, or disclosed *\r
+// *  to third parties, or used for any purpose other than that for which  *\r
+// *  it was obtained, without the prior written consent of Lattice        *\r
+// *  Semiconductor Corporation.  All rights reserved.                     *\r
+// *                                                                       *\r
+// *************************************************************************\r
+//**************************************************************************\r
+\r
+module top_pcs_core_only (\r
+\r
+       // Control Interface\r
+       rst_n,\r
+       signal_detect,\r
+       gbe_mode,\r
+       sgmii_mode,\r
+       force_isolate,\r
+       force_loopback,\r
+       force_unidir,\r
+       operational_rate,\r
+\r
+       rx_compensation_err,\r
+       ctc_drop_flag,\r
+       ctc_add_flag,\r
+       an_link_ok,\r
+\r
+       // G/MII Interface\r
+       tx_clk_125,\r
+       tx_clock_enable_source,\r
+       tx_clock_enable_sink,\r
+       tx_d,\r
+       tx_en,\r
+       tx_er,\r
+\r
+       rx_clk_125,\r
+       rx_clock_enable_source,\r
+       rx_clock_enable_sink,\r
+       rx_d,\r
+       rx_dv,\r
+       rx_er,\r
+       col,\r
+       crs,\r
+\r
+       // 8-bit Interface\r
+       tx_data,\r
+       tx_kcntl,\r
+       tx_disparity_cntl,\r
+       xmit_autoneg,\r
+\r
+       serdes_recovered_clk,\r
+       rx_data,\r
+       rx_kcntl,\r
+       rx_disp_err ,\r
+       rx_cv_err ,\r
+\r
+       // Managment Control Outputs\r
+       mr_an_complete,\r
+       mr_page_rx,\r
+       mr_lp_adv_ability,\r
+\r
+       // Managment Control Inputs\r
+       mr_main_reset,\r
+       mr_an_enable,\r
+       mr_restart_an,\r
+       mr_adv_ability\r
+       );\r
+\r
+\r
+\r
+// Control Interface\r
+input         rst_n ;\r
+input         signal_detect ;\r
+input         gbe_mode ;\r
+input         sgmii_mode ;\r
+input         force_isolate ;\r
+input         force_loopback ;\r
+input         force_unidir ;\r
+input [1:0]   operational_rate ;\r
+\r
+output         rx_compensation_err ;\r
+output         ctc_drop_flag ;\r
+output         ctc_add_flag ;\r
+output         an_link_ok ;\r
+\r
+// G/MII Interface\r
+input         tx_clk_125 ;\r
+output        tx_clock_enable_source ;\r
+input         tx_clock_enable_sink ;\r
+input [7:0]   tx_d ;\r
+input         tx_en ;\r
+input         tx_er ;\r
+\r
+input          rx_clk_125 ;\r
+output         rx_clock_enable_source ;\r
+input          rx_clock_enable_sink ;\r
+output [7:0]   rx_d ;\r
+output         rx_dv ;\r
+output         rx_er ;\r
+output         col ;\r
+output         crs ;\r
+\r
+// 8-bit Interface\r
+output [7:0]   tx_data ;\r
+output         tx_kcntl;\r
+output         tx_disparity_cntl;\r
+output         xmit_autoneg;\r
+\r
+input         serdes_recovered_clk ;\r
+input [7:0]   rx_data  ;\r
+input         rx_kcntl;\r
+input         rx_disp_err ; // Displarity error on "rx_data".\r
+input         rx_cv_err ;   // Code error on "rx_data".\r
+\r
+// Managment Control Outputs\r
+output         mr_an_complete;\r
+output         mr_page_rx;\r
+output [15:0]  mr_lp_adv_ability;\r
+\r
+// Managment Control Inputs\r
+input          mr_main_reset;\r
+input          mr_an_enable;\r
+input          mr_restart_an;\r
+input [15:0]   mr_adv_ability;\r
+\r
+\r
+\r
+// Instantiate Global Reset Controller\r
+GSR GSR_INST   (.GSR(rst_n));\r
+PUR PUR_INST   (.PUR(1'b1));\r
+       \r
+\r
+// SGMII PCS\r
+sgmii_channel_smi_core sgmii_channel_smi_core (\r
+   // Clock and Reset\r
+   .rst_n                  ( rst_n ) ,\r
+   .signal_detect          ( signal_detect ) ,\r
+   .gbe_mode               ( gbe_mode ) ,\r
+   .sgmii_mode             ( sgmii_mode ) ,\r
+   .force_isolate          ( force_isolate ) ,\r
+   .force_loopback         ( force_loopback ) ,\r
+   .force_unidir           ( force_unidir ) ,\r
+   .operational_rate       ( operational_rate ) ,\r
+   .debug_link_timer_short ( 1'b0 ) ,\r
+\r
+   .rx_compensation_err    ( rx_compensation_err ) ,\r
+   .ctc_drop_flag          ( ctc_drop_flag ) ,\r
+   .ctc_add_flag           ( ctc_add_flag ) ,\r
+   .an_link_ok             ( an_link_ok ) ,\r
+\r
+   .tx_clk_125             ( tx_clk_125 ) ,\r
+   .tx_clock_enable_source ( tx_clock_enable_source ) ,\r
+   .tx_clock_enable_sink   ( tx_clock_enable_sink ) ,\r
+   .serdes_recovered_clk   ( serdes_recovered_clk ) ,\r
+   .rx_clk_125             ( rx_clk_125 ) ,\r
+   .rx_clock_enable_source ( rx_clock_enable_source ) ,\r
+   .rx_clock_enable_sink   ( rx_clock_enable_sink ) ,\r
+\r
+   // GMII TX Inputs\r
+   .tx_d            ( tx_d) ,\r
+   .tx_en           ( tx_en) ,\r
+   .tx_er           ( tx_er) ,\r
+\r
+   // GMII RX Outputs\r
+   // To GMII/MAC interface\r
+   .rx_d            ( rx_d ) ,\r
+   .rx_dv           ( rx_dv ) ,\r
+   .rx_er           ( rx_er ) ,\r
+   .col             ( col ) ,\r
+   .crs             ( crs ) ,\r
+                  \r
+   // 8BI TX Outputs\r
+   .tx_data           ( tx_data) ,\r
+   .tx_kcntl          ( tx_kcntl) ,\r
+   .tx_disparity_cntl ( tx_disparity_cntl) ,\r
+   .xmit_autoneg      ( xmit_autoneg) ,\r
+\r
+   // 8BI RX Inputs\r
+   .rx_data         ( rx_data ) ,\r
+   .rx_kcntl        ( rx_kcntl ) ,\r
+   .rx_even         ( 1'b0 ) ,\r
+   .rx_disp_err     ( rx_disp_err ) ,\r
+   .rx_cv_err       ( rx_cv_err ) ,\r
+   .rx_err_decode_mode ( 1'b0 ) ,\r
+\r
+   // Management Interface  I/O\r
+   .mr_adv_ability (mr_adv_ability),\r
+   .mr_an_enable (mr_an_enable), \r
+   .mr_main_reset (mr_main_reset),  \r
+   .mr_restart_an (mr_restart_an),   \r
+\r
+   .mr_an_complete (mr_an_complete),   \r
+   .mr_lp_adv_ability (mr_lp_adv_ability), \r
+   .mr_page_rx (mr_page_rx)\r
+   );\r
+\r
+\r
+endmodule\r

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/testbench/mii_monitor.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/testbench/mii_monitor.v
new file mode 100644 (file)
index 0000000..bc0e2a7
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/testbench/mii_monitor.v
@@ -0,0 +1,118 @@
+//**************************************************************************\r
+// *************************************************************************\r
+// *                LATTICE SEMICONDUCTOR CONFIDENTIAL                     *\r
+// *                         PROPRIETARY NOTE                              *\r
+// *                                                                       *\r
+// *  This software contains information confidential and proprietary      *\r
+// *  to Lattice Semiconductor Corporation.  It shall not be reproduced    *\r
+// *  in whole or in part, or transferred to other documents, or disclosed *\r
+// *  to third parties, or used for any purpose other than that for which  *\r
+// *  it was obtained, without the prior written consent of Lattice        *\r
+// *  Semiconductor Corporation.  All rights reserved.                     *\r
+// *                                                                       *\r
+// *************************************************************************\r
+//**************************************************************************\r
+\r
+//`timescale 1ns/100ps\r
+`timescale 1ps/1ps\r
+\r
+module mii_monitor (\r
+       rst_n,\r
+       clk,\r
+       GBspeed,\r
+\r
+       data_in_ref,\r
+       dv_in_ref,\r
+       err_in_ref,\r
+\r
+       data_in_dut,\r
+       dv_in_dut,\r
+       err_in_dut\r
+);\r
+\r
+input       rst_n;\r
+input       clk;\r
+input  GBspeed;\r
+\r
+input [7:0] data_in_ref;\r
+input       dv_in_ref;\r
+input       err_in_ref;\r
+\r
+input [7:0] data_in_dut;\r
+input       dv_in_dut;\r
+input       err_in_dut;\r
+\r
+\r
+\r
+wire [16:0] len_ref_pp;\r
+wire len_write_ref_pp;\r
+\r
+wire [7:0] data_ref_pp;\r
+wire err_ref_pp;\r
+wire data_write_ref_pp;\r
+\r
+wire [16:0] len_dut_pp;\r
+wire len_write_dut_pp;\r
+\r
+wire [7:0] data_dut_pp;\r
+wire err_dut_pp;\r
+wire data_write_dut_pp;\r
+\r
+wire dv_in_dut;\r
+wire [7:0] data_in_dut;\r
+wire err_in_dut;\r
+\r
+\r
+port_parser_mii   pp_ref (\r
+       .rst_n (rst_n),\r
+       .clk (clk),\r
+       .GBspeed (GBspeed),\r
+       .enable_in (dv_in_ref),\r
+       .data_in (data_in_ref),\r
+       .err_in (err_in_ref),\r
+\r
+       .err_out (err_ref_pp),\r
+       .data_out (data_ref_pp),\r
+       .length_out (len_ref_pp),\r
+       .dat_wr (data_write_ref_pp),\r
+       .len_wr (len_write_ref_pp)\r
+);\r
+\r
+port_parser_mii   pp_dut (\r
+       .rst_n (rst_n),\r
+       .clk (clk),\r
+       .GBspeed (GBspeed),\r
+       .enable_in (dv_in_dut),\r
+       .data_in (data_in_dut),\r
+       .err_in (err_in_dut),\r
+\r
+       .err_out (err_dut_pp),\r
+       .data_out (data_dut_pp),\r
+       .length_out (len_dut_pp),\r
+       .dat_wr (data_write_dut_pp),\r
+       .len_wr (len_write_dut_pp)\r
+);\r
+\r
+\r
+\r
+\r
+port_monitor   port_monitor (\r
+       .rst_n (rst_n),\r
+       .clk (clk),\r
+\r
+       .len_in_ref (len_ref_pp),\r
+       .len_write_en_ref (len_write_ref_pp),\r
+\r
+       .data_in_ref (data_ref_pp),\r
+       .data_write_en_ref (data_write_ref_pp),\r
+       .err_in_ref (err_ref_pp),\r
+\r
+       .len_in_dut (len_dut_pp),\r
+       .len_write_en_dut (len_write_dut_pp),\r
+\r
+       .data_in_dut (data_dut_pp),\r
+       .data_write_en_dut (data_write_dut_pp),\r
+       .err_in_dut (err_dut_pp)\r
+);\r
+\r
+endmodule\r

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/testbench/port_monitor.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/testbench/port_monitor.v
new file mode 100644 (file)
index 0000000..53e1391
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/testbench/port_monitor.v
@@ -0,0 +1,827 @@
+//**************************************************************************\r
+// *************************************************************************\r
+// *                LATTICE SEMICONDUCTOR CONFIDENTIAL                     *\r
+// *                         PROPRIETARY NOTE                              *\r
+// *                                                                       *\r
+// *  This software contains information confidential and proprietary      *\r
+// *  to Lattice Semiconductor Corporation.  It shall not be reproduced    *\r
+// *  in whole or in part, or transferred to other documents, or disclosed *\r
+// *  to third parties, or used for any purpose other than that for which  *\r
+// *  it was obtained, without the prior written consent of Lattice        *\r
+// *  Semiconductor Corporation.  All rights reserved.                     *\r
+// *                                                                       *\r
+// *************************************************************************\r
+//**************************************************************************\r
+\r
+//`timescale 1ns/100ps\r
+`timescale 1ps/1ps\r
+\r
+module port_monitor (\r
+       rst_n,\r
+       clk,\r
+\r
+       len_in_ref,\r
+       len_write_en_ref,\r
+\r
+       data_in_ref,\r
+       data_write_en_ref,\r
+       err_in_ref,\r
+\r
+       len_in_dut,\r
+       len_write_en_dut,\r
+\r
+       data_in_dut,\r
+       data_write_en_dut,\r
+       err_in_dut\r
+);\r
+\r
+input       rst_n;\r
+input       clk;\r
+\r
+input [16:0] len_in_ref;\r
+input len_write_en_ref;\r
+\r
+input [7:0] data_in_ref;\r
+input       data_write_en_ref;\r
+input       err_in_ref;\r
+\r
+input [16:0] len_in_dut;\r
+input len_write_en_dut;\r
+\r
+input [7:0] data_in_dut;\r
+input       data_write_en_dut;\r
+input       err_in_dut;\r
+\r
+/////////////////////////\r
+\r
+parameter \r
+       READY           = 4'd0,\r
+       CHECK_DUT_LEN   = 4'd1,\r
+       PREAMBLE_REF    = 4'd2,\r
+       PREAMBLE_DUT    = 4'd3,\r
+       DEST_ADD        = 4'd4,\r
+       SRC_ADD         = 4'd5,\r
+       LEN             = 4'd6,\r
+       SEQ_NUM         = 4'd7,\r
+       PAYLD           = 4'd8,\r
+       CHECK_FCS       = 4'd9,\r
+       CHECK_CAR_EXT   = 4'd10,\r
+       SUMMARY         = 4'd11;\r
+reg [3:0]         fsm;\r
+\r
+integer i;\r
+integer preamb_count_ref;\r
+integer preamb_count_dut;\r
+\r
+reg  [15:0] payld_count_ref;\r
+reg  [15:0] payld_count_dut;\r
+\r
+reg  [47:0] dest_add_ref;\r
+reg  [47:0] dest_add_dut;\r
+\r
+reg  [47:0] src_add_ref;\r
+reg  [47:0] src_add_dut;\r
+\r
+reg  [15:0] fr_len_ref;\r
+reg  [15:0] fr_len_dut;\r
+\r
+reg  [7:0] seq_num_ref;\r
+reg  [7:0] seq_num_dut;\r
+\r
+reg  [31:0] fcs_dut;\r
+\r
+reg  [31:0] FCS_d0_ref;\r
+reg  [31:0] FCS_d1_ref;\r
+reg  [31:0] FCS_d2_ref;\r
+reg  [31:0] FCS_d3_ref;\r
+reg  [31:0] FCS_d4_ref;\r
+\r
+reg  [31:0] FCS_d0_dut;\r
+reg  [31:0] FCS_d1_dut;\r
+reg  [31:0] FCS_d2_dut;\r
+reg  [31:0] FCS_d3_dut;\r
+reg  [31:0] FCS_d4_dut;\r
+\r
+reg  [7:0] data_in_ref_d1;\r
+reg  [7:0] data_in_ref_d2;\r
+reg  [7:0] data_in_ref_d3;\r
+reg  [7:0] data_in_ref_d4;\r
+\r
+reg [16:0] len_ref_fifo [0:2560];\r
+reg [7:0] data_ref_fifo [0:256000];\r
+reg err_ref_fifo [0:256000];\r
+\r
+reg [16:0] len_dut_fifo [0:2560];\r
+reg [7:0] data_dut_fifo [0:256000];\r
+reg err_dut_fifo [0:256000];\r
+\r
+integer hr, tr; // head for ref fifo, tail for ref fifo\r
+integer hd, td; // head for dut fifo, tail for dut fifo\r
+\r
+integer l_hr, l_tr; // head for ref length fifo, tail for ref length fifo\r
+integer l_hd, l_td; // head for dut length fifo, tail for dut length fifo\r
+\r
+integer words_available_ref;\r
+integer words_available_dut;\r
+integer len_words_available_ref;\r
+integer len_words_available_dut;\r
+\r
+reg data_read_en_ref;\r
+reg data_read_en_dut;\r
+reg len_read_en_ref;\r
+reg len_read_en_dut;\r
+reg [16:0] total_len_ref;\r
+reg [16:0] total_len_dut;\r
+\r
+reg [16:0] total_count_ref;\r
+reg [16:0] total_count_dut;\r
+\r
+wire [16:0] len_ref_fifo_out;\r
+wire  [7:0] data_ref_fifo_out;\r
+wire err_ref_fifo_out;\r
+\r
+wire [16:0] len_dut_fifo_out;\r
+wire  [7:0] data_dut_fifo_out;\r
+wire err_dut_fifo_out;\r
+wire read_inhibit_ref;\r
+wire read_inhibit_dut;\r
+reg data_mismatch;\r
+reg capt_first_mismatch;\r
+reg [7:0] data_capt_ref;\r
+reg [7:0] data_capt_dut;\r
+reg [15:0] mismatch_byte_num;\r
+\r
+reg fcs_fail_ref;\r
+reg fcs_fail_dut;\r
+\r
+reg dest_add_fail;\r
+reg src_add_fail;\r
+reg fr_len_fail;\r
+reg seq_num_fail;\r
+reg car_ext_dut;\r
+\r
+\r
+\r
+// capture incoming data\r
+always @(posedge clk or negedge rst_n)\r
+begin\r
+       if (rst_n == 1'b0) begin\r
+               hr <= 0; // head for ref fifo\r
+               tr <= 0; // tail for ref fifo\r
+\r
+               hd <= 0; // head for dut fifo\r
+               td <= 0; // tail for dut fifo\r
+\r
+               l_hr <= 0; // head for ref length fifo\r
+               l_tr <= 0; // tail for ref length fifo\r
+\r
+               l_hd <= 0; // head for dut length fifo\r
+               l_td <= 0; // tail for dut length fifo\r
+\r
+               words_available_ref <= 0;\r
+               words_available_dut <= 0;\r
+               len_words_available_ref <= 0;\r
+               len_words_available_dut <= 0;\r
+       end\r
+\r
+       else begin\r
+\r
+               // defaults\r
+               words_available_ref <= hr - tr;\r
+               words_available_dut <= hd - td;\r
+               len_words_available_ref <= l_hr - l_tr;\r
+               len_words_available_dut <= l_hd - l_td;\r
+\r
+               ////////////////////////\r
+               // FIFO WRITES\r
+               ////////////////////////\r
+\r
+               // capture reference data\r
+               if (data_write_en_ref) begin\r
+                       data_ref_fifo[hr] <= data_in_ref;\r
+                       err_ref_fifo[hr] <= err_in_ref;\r
+                       if (hr == 256000) begin\r
+                               hr <= 0;\r
+                       end\r
+                       else begin\r
+                               hr <= hr + 1;\r
+                       end\r
+               end\r
+\r
+               // capture dut data\r
+               if (data_write_en_dut) begin\r
+                       data_dut_fifo[hd] <= data_in_dut;\r
+                       err_dut_fifo[hd] <= err_in_dut;\r
+                       if (hd == 256000) begin\r
+                               hd <= 0;\r
+                       end\r
+                       else begin\r
+                               hd <= hd + 1;\r
+                       end\r
+               end\r
+\r
+               // capture reference lengths\r
+               if (len_write_en_ref) begin\r
+                       len_ref_fifo[l_hr] <= len_in_ref;\r
+                       if (l_hr == 2560) begin\r
+                               l_hr <= 0;\r
+                       end\r
+                       else begin\r
+                               l_hr <= l_hr + 1;\r
+                       end\r
+               end\r
+\r
+               // capture dut lengths\r
+               if (len_write_en_dut) begin\r
+                       len_dut_fifo[l_hd] <= len_in_dut;\r
+                       if (l_hd == 2560) begin\r
+                               l_hd <= 0;\r
+                       end\r
+                       else begin\r
+                               l_hd <= l_hd + 1;\r
+                       end\r
+               end\r
+\r
+               /////////////////////////////\r
+               // FIFO READ ADDRESS CONTROL\r
+               /////////////////////////////\r
+               if (data_read_en_ref) begin\r
+                       if (tr == 256000) begin\r
+                               tr <= 0;\r
+                       end\r
+                       else begin\r
+                               tr <= tr + 1;\r
+                       end\r
+               end\r
+               if (data_read_en_dut) begin\r
+                       if (td == 256000) begin\r
+                               td <= 0;\r
+                       end\r
+                       else begin\r
+                               td <= td + 1;\r
+                       end\r
+               end\r
+               if (len_read_en_ref) begin\r
+                       if (l_tr == 2560) begin\r
+                               l_tr <= 0;\r
+                       end\r
+                       else begin\r
+                               l_tr <= l_tr + 1;\r
+                       end\r
+               end\r
+               if (len_read_en_dut) begin\r
+                       if (l_td == 2560) begin\r
+                               l_td <= 0;\r
+                       end\r
+                       else begin\r
+                               l_td <= l_td + 1;\r
+                       end\r
+               end\r
+\r
+\r
+\r
+\r
+       end\r
+end\r
+\r
+\r
+always @(posedge clk or negedge rst_n)\r
+begin\r
+       if (rst_n == 1'b0) begin\r
+               fsm <= READY;\r
+               i  <= 0;\r
+               preamb_count_ref  <= 0;\r
+               preamb_count_dut  <= 0;\r
+\r
+               payld_count_ref  <= 0;\r
+               payld_count_dut  <= 0;\r
+\r
+               dest_add_ref  <= 0;\r
+               dest_add_dut  <= 0;\r
+\r
+               src_add_ref  <= 0;\r
+               src_add_dut  <= 0;\r
+\r
+               fr_len_ref  <= 0;\r
+               fr_len_dut  <= 0;\r
+\r
+               seq_num_ref  <= 0;\r
+               seq_num_dut  <= 0;\r
+\r
+               fcs_dut  <= 0;\r
+\r
+               FCS_d0_ref  <= 0;\r
+               FCS_d1_ref  <= 0;\r
+               FCS_d2_ref  <= 0;\r
+               FCS_d3_ref  <= 0;\r
+               FCS_d4_ref  <= 0;\r
+\r
+               FCS_d0_dut  <= 0;\r
+               FCS_d1_dut  <= 0;\r
+               FCS_d2_dut  <= 0;\r
+               FCS_d3_dut  <= 0;\r
+               FCS_d4_dut  <= 0;\r
+\r
+               data_in_ref_d1  <= 0;\r
+               data_in_ref_d2  <= 0;\r
+               data_in_ref_d3  <= 0;\r
+               data_in_ref_d4  <= 0;\r
+\r
+               data_read_en_ref <= 0;\r
+               data_read_en_dut <= 0;\r
+               len_read_en_ref <= 0;\r
+               len_read_en_dut <= 0;\r
+\r
+               total_len_ref <= 0;\r
+               total_len_dut <= 0;\r
+\r
+               total_count_ref <= 0;\r
+               total_count_dut <= 0;\r
+\r
+               data_mismatch <= 0;\r
+               capt_first_mismatch <= 0;\r
+               data_capt_ref <= 0;\r
+               data_capt_dut <= 0;\r
+               mismatch_byte_num <= 0;\r
+\r
+               fcs_fail_ref <= 0;\r
+               fcs_fail_dut <= 0;\r
+\r
+               car_ext_dut <= 0;\r
+\r
+               end\r
+       else begin\r
+\r
+               // defaults\r
+               FCS_d1_ref <= FCS_d0_ref;\r
+               FCS_d2_ref <= FCS_d1_ref;\r
+               FCS_d3_ref <= FCS_d2_ref;\r
+               FCS_d4_ref <= FCS_d3_ref;\r
+\r
+               FCS_d1_dut <= FCS_d0_dut;\r
+               FCS_d2_dut <= FCS_d1_dut;\r
+               FCS_d3_dut <= FCS_d2_dut;\r
+               FCS_d4_dut <= FCS_d3_dut;\r
+\r
+               data_in_ref_d1 <= data_in_ref;\r
+               data_in_ref_d2 <= data_in_ref_d1;\r
+               data_in_ref_d3 <= data_in_ref_d2;\r
+               data_in_ref_d4 <= data_in_ref_d3;\r
+\r
+               data_read_en_ref <= 0;\r
+               data_read_en_dut <= 0;\r
+               len_read_en_ref <= 0;\r
+               len_read_en_dut <= 0;\r
+\r
+               data_mismatch <= 0;\r
+\r
+               case(fsm)\r
+                       READY:\r
+                         begin\r
+                               preamb_count_ref  <= 0;\r
+                               preamb_count_dut  <= 0;\r
+\r
+                               payld_count_ref  <= 0;\r
+                               payld_count_dut  <= 0;\r
+\r
+                               dest_add_ref  <= 0;\r
+                               dest_add_dut  <= 0;\r
+\r
+                               src_add_ref  <= 0;\r
+                               src_add_dut  <= 0;\r
+\r
+                               fr_len_ref  <= 0;\r
+                               fr_len_dut  <= 0;\r
+\r
+                               seq_num_ref  <= 0;\r
+                               seq_num_dut  <= 0;\r
+\r
+                               fcs_dut  <= 0;\r
+\r
+                               FCS_d0_ref  <= 0;\r
+                               FCS_d0_dut  <= 0;\r
+\r
+                               total_count_ref <= 0;\r
+                               total_count_dut <= 0;\r
+\r
+                               data_mismatch <= 0;\r
+                               capt_first_mismatch <= 0;\r
+                               data_capt_ref <= 0;\r
+                               data_capt_dut <= 0;\r
+                               mismatch_byte_num <= 0;\r
+\r
+                               fcs_fail_ref <= 0;\r
+                               fcs_fail_dut <= 0;\r
+\r
+                               car_ext_dut <= 0;\r
+                               \r
+                               if (len_words_available_ref > 0) begin\r
+                                 len_read_en_ref <= 1;\r
+                                 total_len_ref <= len_ref_fifo_out;\r
+                                 fsm <= CHECK_DUT_LEN;\r
+                               end\r
+                         end\r
+\r
+                       CHECK_DUT_LEN:\r
+                         begin\r
+\r
+                               if (len_words_available_dut > 0) begin\r
+                                 len_read_en_dut <= 1;\r
+                                 total_len_dut <= len_dut_fifo_out;\r
+\r
+                                 data_read_en_ref <= 1;\r
+\r
+                                 fsm <= PREAMBLE_REF;\r
+                               end\r
+\r
+                         end\r
+\r
+                       PREAMBLE_REF:\r
+                         begin\r
+                               total_count_ref <= total_count_ref + 1;\r
+\r
+                               if (data_ref_fifo_out == 8'hd5) begin\r
+                                 data_read_en_ref <= 0;\r
+                                 data_read_en_dut <= 1;\r
+                                 fsm <= PREAMBLE_DUT;\r
+                               end\r
+                               else begin\r
+                                 data_read_en_ref <= 1;\r
+                                 preamb_count_ref <= preamb_count_ref + 1;\r
+                               end\r
+                         end\r
+\r
+\r
+                       PREAMBLE_DUT:\r
+                         begin\r
+                               total_count_dut <= total_count_dut + 1;\r
+                               data_read_en_dut <= 1;\r
+\r
+                               if (data_dut_fifo_out == 8'hd5) begin\r
+                                 data_read_en_ref <= 1;\r
+                                 i <= 1;\r
+                                 fsm <= DEST_ADD;\r
+                               end\r
+                               else begin\r
+                                 preamb_count_dut <= preamb_count_dut + 1;\r
+                               end\r
+                         end\r
+\r
+\r
+\r
+                       DEST_ADD:\r
+                         begin\r
+                               data_read_en_ref <= ~read_inhibit_ref;\r
+                               data_read_en_dut <= ~read_inhibit_dut;\r
+\r
+                               if (!read_inhibit_ref) begin\r
+                                       total_count_ref <= total_count_ref + 1;\r
+                               end \r
+\r
+                               if (!read_inhibit_dut) begin\r
+                                       total_count_dut <= total_count_dut + 1;\r
+                               end \r
+\r
+                               i <= i + 1;\r
+                               case (i)\r
+                                       1: begin dest_add_ref[47:40] <= data_ref_fifo_out; FCS_d0_ref <= FCS_d0_ref + data_ref_fifo_out; end\r
+                                       2: begin dest_add_ref[39:32] <= data_ref_fifo_out; FCS_d0_ref <= FCS_d0_ref + data_ref_fifo_out; end\r
+                                       3: begin dest_add_ref[31:24] <= data_ref_fifo_out; FCS_d0_ref <= FCS_d0_ref + data_ref_fifo_out; end\r
+                                       4: begin dest_add_ref[23:16] <= data_ref_fifo_out; FCS_d0_ref <= FCS_d0_ref + data_ref_fifo_out; end\r
+                                       5: begin dest_add_ref[15:8]  <= data_ref_fifo_out; FCS_d0_ref <= FCS_d0_ref + data_ref_fifo_out; end\r
+                                       6: begin dest_add_ref[7:0]   <= data_ref_fifo_out; FCS_d0_ref <= FCS_d0_ref + data_ref_fifo_out; end\r
+                                       default: dest_add_ref<= dest_add_ref;\r
+                               endcase\r
+                               case (i)\r
+                                       1: begin dest_add_dut[47:40] <= data_dut_fifo_out; FCS_d0_dut <= FCS_d0_dut + data_dut_fifo_out; end\r
+                                       2: begin dest_add_dut[39:32] <= data_dut_fifo_out; FCS_d0_dut <= FCS_d0_dut + data_dut_fifo_out; end\r
+                                       3: begin dest_add_dut[31:24] <= data_dut_fifo_out; FCS_d0_dut <= FCS_d0_dut + data_dut_fifo_out; end\r
+                                       4: begin dest_add_dut[23:16] <= data_dut_fifo_out; FCS_d0_dut <= FCS_d0_dut + data_dut_fifo_out; end\r
+                                       5: begin dest_add_dut[15:8]  <= data_dut_fifo_out; FCS_d0_dut <= FCS_d0_dut + data_dut_fifo_out; end\r
+                                       6: begin dest_add_dut[7:0]   <= data_dut_fifo_out; FCS_d0_dut <= FCS_d0_dut + data_dut_fifo_out; end\r
+                                       default: dest_add_dut<= dest_add_dut;\r
+                               endcase\r
+\r
+                               if (i == 6) begin\r
+                                 i <= 1;\r
+                                 fsm <= SRC_ADD;\r
+                               end\r
+                         end\r
+\r
+                       SRC_ADD:\r
+                         begin\r
+                               data_read_en_ref <= ~read_inhibit_ref;\r
+                               data_read_en_dut <= ~read_inhibit_dut;\r
+\r
+                               if (!read_inhibit_ref) begin\r
+                                       total_count_ref <= total_count_ref + 1;\r
+                               end \r
+\r
+                               if (!read_inhibit_dut) begin\r
+                                       total_count_dut <= total_count_dut + 1;\r
+                               end \r
+\r
+                               i <= i + 1;\r
+                               case (i)\r
+                                       1: begin src_add_ref[47:40] <= data_ref_fifo_out; FCS_d0_ref <= FCS_d0_ref + data_ref_fifo_out; end\r
+                                       2: begin src_add_ref[39:32] <= data_ref_fifo_out; FCS_d0_ref <= FCS_d0_ref + data_ref_fifo_out; end\r
+                                       3: begin src_add_ref[31:24] <= data_ref_fifo_out; FCS_d0_ref <= FCS_d0_ref + data_ref_fifo_out; end\r
+                                       4: begin src_add_ref[23:16] <= data_ref_fifo_out; FCS_d0_ref <= FCS_d0_ref + data_ref_fifo_out; end\r
+                                       5: begin src_add_ref[15:8]  <= data_ref_fifo_out; FCS_d0_ref <= FCS_d0_ref + data_ref_fifo_out; end\r
+                                       6: begin src_add_ref[7:0]   <= data_ref_fifo_out; FCS_d0_ref <= FCS_d0_ref + data_ref_fifo_out; end\r
+                                       default: src_add_ref<= src_add_ref;\r
+                               endcase\r
+                               case (i)\r
+                                       1: begin src_add_dut[47:40] <= data_dut_fifo_out; FCS_d0_dut <= FCS_d0_dut + data_dut_fifo_out; end\r
+                                       2: begin src_add_dut[39:32] <= data_dut_fifo_out; FCS_d0_dut <= FCS_d0_dut + data_dut_fifo_out; end\r
+                                       3: begin src_add_dut[31:24] <= data_dut_fifo_out; FCS_d0_dut <= FCS_d0_dut + data_dut_fifo_out; end\r
+                                       4: begin src_add_dut[23:16] <= data_dut_fifo_out; FCS_d0_dut <= FCS_d0_dut + data_dut_fifo_out; end\r
+                                       5: begin src_add_dut[15:8]  <= data_dut_fifo_out; FCS_d0_dut <= FCS_d0_dut + data_dut_fifo_out; end\r
+                                       6: begin src_add_dut[7:0]   <= data_dut_fifo_out; FCS_d0_dut <= FCS_d0_dut + data_dut_fifo_out; end\r
+                                       default: src_add_dut<= src_add_dut;\r
+                               endcase\r
+                               if (i == 6) begin\r
+                                 i <= 1;\r
+                                 fsm <= LEN;\r
+                               end\r
+                         end\r
+\r
+                       LEN:\r
+                         begin\r
+                               data_read_en_ref <= ~read_inhibit_ref;\r
+                               data_read_en_dut <= ~read_inhibit_dut;\r
+\r
+                               if (!read_inhibit_ref) begin\r
+                                       total_count_ref <= total_count_ref + 1;\r
+                               end \r
+\r
+                               if (!read_inhibit_dut) begin\r
+                                       total_count_dut <= total_count_dut + 1;\r
+                               end \r
+\r
+                               i <= i + 1;\r
+                               case (i)\r
+                                       1: begin fr_len_ref[15:8]  <= data_ref_fifo_out; FCS_d0_ref <= FCS_d0_ref + data_ref_fifo_out; end\r
+                                       2: begin fr_len_ref[7:0]   <= data_ref_fifo_out; FCS_d0_ref <= FCS_d0_ref + data_ref_fifo_out; end\r
+                                       default: fr_len_ref <= fr_len_ref;\r
+                               endcase\r
+                               case (i)\r
+                                       1: begin fr_len_dut[15:8]  <= data_dut_fifo_out; FCS_d0_dut <= FCS_d0_dut + data_dut_fifo_out; end\r
+                                       2: begin fr_len_dut[7:0]   <= data_dut_fifo_out; FCS_d0_dut <= FCS_d0_dut + data_dut_fifo_out; end\r
+                                       default: fr_len_dut <= fr_len_dut;\r
+                               endcase\r
+                               if (i == 2) begin\r
+                                 i <= 1;\r
+                                 fsm <= SEQ_NUM;\r
+                               end\r
+                         end\r
+\r
+                       SEQ_NUM:\r
+                         begin\r
+                               data_read_en_ref <= ~read_inhibit_ref;\r
+                               data_read_en_dut <= ~read_inhibit_dut;\r
+\r
+                               if (!read_inhibit_ref) begin\r
+                                       total_count_ref <= total_count_ref + 1;\r
+                               end \r
+\r
+                               if (!read_inhibit_dut) begin\r
+                                       total_count_dut <= total_count_dut + 1;\r
+                               end \r
+\r
+                               seq_num_ref  <= data_ref_fifo_out;\r
+                               FCS_d0_ref <= FCS_d0_ref + data_ref_fifo_out;\r
+                               payld_count_ref <= 2;\r
+\r
+                               seq_num_dut  <= data_dut_fifo_out;\r
+                               FCS_d0_dut <= FCS_d0_dut + data_dut_fifo_out;\r
+                               payld_count_dut <= 2;\r
+\r
+                               fsm <= PAYLD;\r
+                         end\r
+\r
+                       PAYLD:\r
+                         begin\r
+                               data_read_en_ref <= ~read_inhibit_ref;\r
+                               data_read_en_dut <= ~read_inhibit_dut;\r
+\r
+                               if (!read_inhibit_ref) begin\r
+                                       total_count_ref <= total_count_ref + 1;\r
+                               end \r
+\r
+                               if (!read_inhibit_dut) begin\r
+                                       total_count_dut <= total_count_dut + 1;\r
+                               end \r
+\r
+                               FCS_d0_ref <= FCS_d0_ref + data_ref_fifo_out;\r
+                               FCS_d0_dut <= FCS_d0_dut + data_dut_fifo_out;\r
+\r
+                               //if (total_count_ref >= (total_len_ref - 5)) begin\r
+                               if (payld_count_ref == (fr_len_ref)) begin\r
+                                 i <= 1;\r
+                                 fsm <= CHECK_FCS;\r
+                               end\r
+                               else begin\r
+                                       payld_count_ref <= payld_count_ref + 1;\r
+                                       payld_count_dut <= payld_count_dut + 1;\r
+                               end\r
+\r
+                               if (data_ref_fifo_out != data_dut_fifo_out) begin\r
+\r
+                                       if (!capt_first_mismatch) begin\r
+                                               capt_first_mismatch <= 1;\r
+                                               data_capt_ref <= data_ref_fifo_out;\r
+                                               data_capt_dut <= data_dut_fifo_out;\r
+                                               mismatch_byte_num <= payld_count_ref;\r
+                                       end\r
+\r
+                                       data_mismatch <= 1;\r
+                               end\r
+\r
+                         end\r
+\r
+                       CHECK_FCS:\r
+                         begin\r
+                               if ((i >= 1) && (i <= 3)) begin\r
+                                       data_read_en_ref <= ~read_inhibit_ref;\r
+                                       data_read_en_dut <= ~read_inhibit_dut;\r
+                               end\r
+\r
+                               if (!read_inhibit_ref) begin\r
+                                       total_count_ref <= total_count_ref + 1;\r
+                               end \r
+\r
+                               if (!read_inhibit_dut) begin\r
+                                       total_count_dut <= total_count_dut + 1;\r
+                               end \r
+\r
+                               case (i)\r
+                                       1: begin if (FCS_d0_ref[31:24] != data_ref_fifo_out) fcs_fail_ref <= 1; end\r
+                                       2: begin if (FCS_d0_ref[23:16] != data_ref_fifo_out) fcs_fail_ref <= 1; end\r
+                                       3: begin if (FCS_d0_ref[15:8]  != data_ref_fifo_out) fcs_fail_ref <= 1; end\r
+                                       4: begin if (FCS_d0_ref[7:0]   != data_ref_fifo_out) fcs_fail_ref <= 1; end\r
+                                       default: fcs_fail_ref <= fcs_fail_ref;\r
+                               endcase\r
+                               case (i)\r
+                                       1: begin fcs_dut[31:24] <= data_dut_fifo_out; if (FCS_d0_dut[31:24] != data_dut_fifo_out) fcs_fail_dut <= 1; end\r
+                                       2: begin fcs_dut[23:16] <= data_dut_fifo_out; if (FCS_d0_dut[23:16] != data_dut_fifo_out) fcs_fail_dut <= 1; end\r
+                                       3: begin fcs_dut[15:8]  <= data_dut_fifo_out; if (FCS_d0_dut[15:8]  != data_dut_fifo_out) fcs_fail_dut <= 1; end\r
+                                       4: begin fcs_dut[7:0]   <= data_dut_fifo_out; if (FCS_d0_dut[7:0]   != data_dut_fifo_out) fcs_fail_dut <= 1; end\r
+                                       default: fcs_fail_dut <= fcs_fail_dut;\r
+                               endcase\r
+\r
+                               i <= i + 1;\r
+\r
+                               if (i == 4) begin\r
+                                       if ((total_len_dut - total_count_dut) > 1) begin\r
+                                               data_read_en_dut <= 1;\r
+                                               fsm <= CHECK_CAR_EXT;\r
+                                       end\r
+                                       else begin\r
+                                               fsm <= SUMMARY;\r
+                                       end\r
+                               end\r
+                         end\r
+\r
+                       CHECK_CAR_EXT:\r
+                         begin\r
+\r
+                               if (!read_inhibit_dut) begin\r
+                                       total_count_dut <= total_count_dut + 1;\r
+                               end \r
+\r
+                               if ((data_dut_fifo_out == 8'h0f) && (err_dut_fifo_out == 1'b1)) begin\r
+                                       car_ext_dut <= 1;\r
+                               end\r
+\r
+\r
+                               if ((total_len_dut - total_count_dut) > 1) begin\r
+                                       data_read_en_dut <= 1;\r
+                               end\r
+                               else begin\r
+                                       fsm <= SUMMARY;\r
+                               end\r
+\r
+                         end\r
+\r
+                       SUMMARY:\r
+                         begin\r
+                               if (dest_add_fail || src_add_fail || fr_len_fail || seq_num_fail || capt_first_mismatch || fcs_fail_dut) begin\r
+                                       $display("PORT MONITOR: recvd frame : ***** FAILED ***** @ %t", $time);\r
+                                       if (dest_add_fail) begin\r
+                                               $display("         expected_dest_addr 0x%0h : actual_dest_addr 0x%0h", dest_add_ref, dest_add_dut);\r
+                                       end\r
+                                       if (src_add_fail) begin\r
+                                               $display("         expected_src_addr 0x%0h : actual_src_addr 0x%0h", src_add_ref, src_add_dut);\r
+                                       end\r
+                                       if (fr_len_fail) begin\r
+                                               $display("         expected_frame_length 0x%0h : actual_frame_length 0x%0h", fr_len_ref, fr_len_dut);\r
+                                       end\r
+                                       if (seq_num_fail) begin\r
+                                               $display("         expected_sequence_number 0x%0h : actual_sequence_number 0x%0h", seq_num_ref, seq_num_dut);\r
+                                       end\r
+                                       if (capt_first_mismatch) begin\r
+                                               $display("         expected_data 0x%0h : actual_data 0x%0h    @ byte_number %d", data_capt_ref, data_capt_dut, mismatch_byte_num);\r
+                                       end\r
+                                       if (fcs_fail_dut) begin\r
+                                               $display("         expected_FCS 0x%0h : actual_FCS 0x%0h", FCS_d0_ref, fcs_dut);\r
+                                       end\r
+                               end\r
+                               else if (car_ext_dut) begin\r
+                                       $display("\tPORT MONITOR: recvd frame :        GOOD  ---- CARRIER EXTENSION PRESENT ----        @ %t", $time);\r
+                               end\r
+\r
+                               else begin\r
+                                       $display("\tPORT MONITOR: recvd frame :        GOOD        @ %t", $time);\r
+                               end\r
+\r
+                               //$display("--------------------------------------------------");\r
+                               $display("         preamble_size %0d", preamb_count_dut);\r
+                               $display("         dest_addr 0x%0h : src_addr 0x%0h", dest_add_dut, src_add_dut);\r
+                               $display("         sequence_num %0d : payload_len %0d : FCS 0x%0h ", seq_num_dut, payld_count_dut, FCS_d0_dut);\r
+                               $display("                                                  ");\r
+\r
+                               fsm <= READY;\r
+                         end\r
+\r
+\r
+\r
+                       default :\r
+                         begin\r
+                               fsm <= READY;\r
+                         end\r
+               endcase\r
+       end\r
+end \r
+\r
+always @(*) begin\r
+\r
+       if (dest_add_ref == dest_add_dut) \r
+               dest_add_fail <= 0;\r
+       else\r
+               dest_add_fail <= 1;\r
+\r
+\r
+       if (src_add_ref == src_add_dut) \r
+               src_add_fail <= 0;\r
+       else\r
+               src_add_fail <= 1;\r
+\r
+\r
+       if (fr_len_ref == fr_len_dut) \r
+               fr_len_fail <= 0;\r
+       else\r
+               fr_len_fail <= 1;\r
+\r
+\r
+       if (seq_num_ref == seq_num_dut) \r
+               seq_num_fail <= 0;\r
+       else\r
+               seq_num_fail <= 1;\r
+\r
+\r
+end\r
+\r
+\r
+// assign FIFO data out\r
+assign len_ref_fifo_out = len_ref_fifo[l_tr];\r
+assign  data_ref_fifo_out = data_ref_fifo [tr];\r
+assign err_ref_fifo_out = err_ref_fifo [tr];\r
+\r
+assign len_dut_fifo_out = len_dut_fifo[l_td];\r
+assign  data_dut_fifo_out = data_dut_fifo [td];\r
+assign err_dut_fifo_out = err_dut_fifo [td];\r
+\r
+// continuous assignments\r
+assign read_inhibit_ref = (total_count_ref <= total_len_ref) ? 0 : 1;\r
+assign read_inhibit_dut = (total_count_dut <= total_len_dut) ? 0 : 1;\r
+\r
+\r
+// synopsys translate_off\r
+reg  [(22*8):1] fsm_monitor; \r
+always @(*) begin\r
+   case (fsm)\r
+      READY            : fsm_monitor = "READY";\r
+      CHECK_DUT_LEN    : fsm_monitor = "CHECK_DUT_LEN";\r
+      PREAMBLE_REF     : fsm_monitor = "PREAMBLE_REF";         \r
+      PREAMBLE_DUT     : fsm_monitor = "PREAMBLE_DUT";         \r
+      DEST_ADD         : fsm_monitor = "DEST_ADD";\r
+      SRC_ADD          : fsm_monitor = "SRC_ADD";\r
+      LEN              : fsm_monitor = "LEN";\r
+      SEQ_NUM          : fsm_monitor = "SEQ_NUM";\r
+      PAYLD            : fsm_monitor = "PAYLD";         \r
+      CHECK_FCS                : fsm_monitor = "CHECK_FCS";         \r
+      CHECK_CAR_EXT    : fsm_monitor = "CHECK_CAR_EXT";         \r
+      SUMMARY          : fsm_monitor = "SUMMARY";             \r
+\r
+      default          : fsm_monitor = "***ERROR***";\r
+   endcase\r
+end\r
+// synopsys translate_on\r
+\r
+\r
+endmodule\r
+// =============================================================================\r
+\r
+\r
+\r

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/testbench/port_parser_mii.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/testbench/port_parser_mii.v
new file mode 100644 (file)
index 0000000..972508c
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/testbench/port_parser_mii.v
@@ -0,0 +1,237 @@
+//**************************************************************************\r
+// *************************************************************************\r
+// *                LATTICE SEMICONDUCTOR CONFIDENTIAL                     *\r
+// *                         PROPRIETARY NOTE                              *\r
+// *                                                                       *\r
+// *  This software contains information confidential and proprietary      *\r
+// *  to Lattice Semiconductor Corporation.  It shall not be reproduced    *\r
+// *  in whole or in part, or transferred to other documents, or disclosed *\r
+// *  to third parties, or used for any purpose other than that for which  *\r
+// *  it was obtained, without the prior written consent of Lattice        *\r
+// *  Semiconductor Corporation.  All rights reserved.                     *\r
+// *                                                                       *\r
+// *************************************************************************\r
+//**************************************************************************\r
+\r
+//`timescale 1ns/100ps\r
+`timescale 1ps/1ps\r
+\r
+module port_parser_mii (\r
+       rst_n,\r
+       clk,\r
+       enable_in,\r
+       data_in,\r
+       err_in,\r
+       GBspeed,\r
+\r
+       err_out,\r
+       data_out,\r
+       length_out,\r
+       dat_wr,\r
+       len_wr\r
+);\r
+\r
+input       rst_n;\r
+input       clk;\r
+input       enable_in;\r
+input       err_in;\r
+input [7:0] data_in;\r
+input  GBspeed;\r
+\r
+output err_out;\r
+output [7:0] data_out;\r
+output [16:0] length_out;\r
+output dat_wr;\r
+output len_wr;\r
+\r
+reg err_out;\r
+reg [7:0] data_out;\r
+reg dat_wr;\r
+reg len_wr;\r
+\r
+reg [16:0] count;\r
+\r
+parameter \r
+    SEEK_EN    = 3'd0,\r
+    DO_WRITE_LO        = 3'd1,\r
+    DO_WRITE_HI        = 3'd2,\r
+    CAR_EXT_LO = 3'd3,\r
+    CAR_EXT_HI = 3'd4,\r
+    DO_WRITE_GB        = 3'd5,\r
+    CAR_EXT_GB = 3'd6;\r
+reg [2:0]          cfsm;\r
+\r
+\r
+\r
+always @(posedge clk or negedge rst_n)\r
+begin\r
+       if (rst_n == 1'b0) begin\r
+               cfsm <= SEEK_EN;\r
+               count <= 17'd0;\r
+               data_out <= 8'd0;\r
+               err_out <= 1'b0;\r
+               dat_wr <= 1'b0;\r
+               len_wr <= 1'b0;\r
+       end\r
+       else begin\r
+               // defaults\r
+               //data_out <= data_in;\r
+               err_out <= err_in;\r
+               dat_wr <= 1'b0;\r
+               len_wr <= 1'b0;\r
+\r
+               case(cfsm)\r
+                       SEEK_EN:\r
+                         begin\r
+                               count <= 17'd1;\r
+                               if (enable_in) begin\r
+                                       if (GBspeed) begin\r
+                                               // 1GBPS Mode\r
+                                               dat_wr <= 1'b1;\r
+                                               data_out <= data_in;\r
+                                               cfsm <= DO_WRITE_GB;\r
+                                       end\r
+                                       else begin\r
+                                               // 100MBPS or 10MBPS Mode\r
+                                               data_out[3:0] <= data_in[3:0];\r
+                                               cfsm <= DO_WRITE_HI;\r
+                                       end\r
+                               end\r
+                         end\r
+\r
+\r
+\r
+\r
+\r
+                       DO_WRITE_LO:\r
+                         begin\r
+                               data_out[3:0] <= data_in[3:0];\r
+\r
+                               if (enable_in) begin\r
+                                       count <= count + 1;\r
+                                       cfsm <= DO_WRITE_HI;\r
+                               end\r
+                               else begin\r
+                                       if (err_in) begin\r
+                                               count <= count + 1;\r
+                                               cfsm <= CAR_EXT_HI;\r
+                                       end\r
+                                       else begin\r
+                                               cfsm <= DO_WRITE_HI;\r
+                                       end\r
+                               end\r
+                         end\r
+                       DO_WRITE_HI:\r
+                         begin\r
+                               if (enable_in) begin\r
+                                       dat_wr <= 1'b1;\r
+                                       data_out[7:4] <= data_in[3:0];\r
+                                       cfsm <= DO_WRITE_LO;\r
+                               end\r
+                               else begin\r
+                                       if (err_in) begin\r
+                                               dat_wr <= 1'b1;\r
+                                               cfsm <= CAR_EXT_LO;\r
+                                       end\r
+                                       else begin\r
+                                               len_wr <= 1'b1;\r
+                                               cfsm <= SEEK_EN;\r
+                                       end\r
+                               end\r
+                         end\r
+\r
+\r
+\r
+                       CAR_EXT_LO:\r
+                         begin\r
+                               if (err_in) begin\r
+                                       count <= count + 1;\r
+                               end\r
+                               data_out[3:0] <= data_in[3:0];\r
+                               cfsm <= CAR_EXT_HI;\r
+                         end\r
+                       CAR_EXT_HI:\r
+                         begin\r
+                               if (err_in) begin\r
+                                       dat_wr <= 1'b1;\r
+                                       data_out[7:4] <= data_in[3:0];\r
+                                       cfsm <= CAR_EXT_LO;\r
+                               end\r
+                               else begin\r
+                                       len_wr <= 1'b1;\r
+                                       cfsm <= SEEK_EN;\r
+                               end\r
+                         end\r
+\r
+\r
+                       DO_WRITE_GB:\r
+                         begin\r
+                               data_out <= data_in;\r
+                               if (enable_in) begin\r
+                                       dat_wr <= 1'b1;\r
+                                       count <= count + 1;\r
+                               end\r
+                               else begin\r
+                                       if (err_in) begin\r
+                                               dat_wr <= 1'b1;\r
+                                               count <= count + 1;\r
+                                               cfsm <= CAR_EXT_GB;\r
+                                       end\r
+                                       else begin\r
+                                               len_wr <= 1'b1;\r
+                                               cfsm <= SEEK_EN;\r
+                                       end\r
+                               end\r
+                         end\r
+                       CAR_EXT_GB:\r
+                         begin\r
+                               data_out <= data_in;\r
+                               if (err_in) begin\r
+                                       dat_wr <= 1'b1;\r
+                                       count <= count + 1;\r
+                                       cfsm <= CAR_EXT_GB;\r
+                               end\r
+                               else begin\r
+                                       len_wr <= 1'b1;\r
+                                       cfsm <= SEEK_EN;\r
+                               end\r
+                         end\r
+\r
+\r
+\r
+\r
+                       default :\r
+                         begin\r
+                               cfsm <= SEEK_EN;\r
+                         end\r
+               endcase\r
+       end\r
+end \r
+\r
+\r
+assign length_out = count;\r
+\r
+\r
+\r
+// synopsys translate_off\r
+reg  [(22*8):1] cfsm_monitor; \r
+always @(*) begin\r
+   case (cfsm)\r
+      SEEK_EN          : cfsm_monitor = "SEEK_EN";\r
+      DO_WRITE_LO      : cfsm_monitor = "DO_WRITE_LO";\r
+      DO_WRITE_HI      : cfsm_monitor = "DO_WRITE_HI";         \r
+      CAR_EXT_LO       : cfsm_monitor = "CAR_EXT_LO";         \r
+      CAR_EXT_HI       : cfsm_monitor = "CAR_EXT_HI";\r
+      DO_WRITE_GB      : cfsm_monitor = "DO_WRITE_GB";\r
+      CAR_EXT_GB       : cfsm_monitor = "CAR_EXT_GB";\r
+\r
+      default          : cfsm_monitor = "***ERROR***";\r
+   endcase\r
+end\r
+// synopsys translate_on\r
+\r
+endmodule\r
+// =============================================================================\r
+\r
+\r
+\r

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/testbench/sgmii_node.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/testbench/sgmii_node.v
new file mode 100644 (file)
index 0000000..914fafc
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/testbench/sgmii_node.v
@@ -0,0 +1,302 @@
+//**************************************************************************\r
+// *************************************************************************\r
+// *                LATTICE SEMICONDUCTOR CONFIDENTIAL                     *\r
+// *                         PROPRIETARY NOTE                              *\r
+// *                                                                       *\r
+// *  This software contains information confidential and proprietary      *\r
+// *  to Lattice Semiconductor Corporation.  It shall not be reproduced    *\r
+// *  in whole or in part, or transferred to other documents, or disclosed *\r
+// *  to third parties, or used for any purpose other than that for which  *\r
+// *  it was obtained, without the prior written consent of Lattice        *\r
+// *  Semiconductor Corporation.  All rights reserved.                     *\r
+// *                                                                       *\r
+// *************************************************************************\r
+//**************************************************************************\r
+\r
+`timescale 1ns/100ps\r
+\r
+module sgmii_node (\r
+       // Control Interface\r
+       gbe_mode,\r
+       sgmii_mode,\r
+       force_loopback,\r
+       rst_n,\r
+       phy_speed,\r
+\r
+       // G/MII Interface\r
+       data_in_mii,\r
+       en_in_mii,\r
+       err_in_mii,\r
+\r
+       data_out_mii,\r
+       dv_out_mii,\r
+       err_out_mii,\r
+\r
+       // GMII Timing References\r
+       tx_clk_125,\r
+       tx_ce_sink,\r
+       tx_ce_source,\r
+\r
+       rx_clk_125,\r
+       rx_ce_sink,\r
+       rx_ce_source,\r
+\r
+       // SERIAL GMII Interface \r
+       refclkp,\r
+       refclkn,\r
+       hdinp0, \r
+       hdinn0, \r
+       hdoutp0, \r
+       hdoutn0\r
+       );\r
+\r
+\r
+\r
+// I/O Declarations\r
+input          rst_n;          // System Reset, Active Low\r
+input           gbe_mode ;      // GBE Mode       (0=SGMII  1=GBE)\r
+input           sgmii_mode ;    // SGMII PCS Mode (0=MAC    1=PHY)\r
+input           force_loopback ;\r
+input [1:0]    phy_speed;\r
+\r
+input          refclkp, refclkn ;\r
+input          tx_clk_125 ;    // GMII Transmit clock 125Mhz\r
+input          tx_ce_sink ;\r
+output         tx_ce_source ;\r
+\r
+input [7:0]    data_in_mii;    // G/MII Incoming Data\r
+input          en_in_mii;      // G/MII Incoming Data Valid\r
+input          err_in_mii;     // G/MII Incoming Error\r
+\r
+input          rx_clk_125 ;    // GMII Receive clock 125Mhz\r
+input          rx_ce_sink ;\r
+output         rx_ce_source ;\r
+\r
+output [7:0]   data_out_mii;   // G/MII Outgoing Data\r
+output         dv_out_mii;     // G/MII Outgoing Data Valid\r
+output         err_out_mii;    // G/MII Outgoing Error\r
+\r
+input          hdinp0;         // Incoming SGMII (on SERDES)\r
+input          hdinn0;         // Incoming SGMII (on SERDES)\r
+\r
+output         hdoutp0;        // Outgoing SGMII (on SERDES)\r
+output         hdoutn0;        // Outgoing SGMII (on SERDES)\r
+\r
+\r
+\r
+//  8-bit Interface Signals from SGMII channel to QuadPCS/SERDES\r
+wire [7:0]     data_chan2quad;\r
+wire           kcntl_chan2quad;\r
+wire           disparity_cntl_chan2quad;\r
+\r
+//  8-bit Interface Signals from QuadPCS/SERDES to SGMII channel\r
+wire [7:0]     data_quad2chan;\r
+wire           kcntl_quad2chan;\r
+wire           disp_err_quad2chan;\r
+wire           cv_err_quad2chan;\r
+wire           link_status;\r
+wire           serdes_recovered_clk;\r
+wire           refclk2fpga;\r
+wire           xmit_autoneg;\r
+\r
+wire adv_link_status;\r
+wire adv_duplex_mode;\r
+wire [1:0] adv_link_speed;\r
+\r
+//  Active High Reset\r
+wire           rst;\r
+assign rst = ~rst_n;\r
+\r
+\r
+wire debug_link_timer_short;\r
+wire [1:0] operational_rate;\r
+wire [15:0] mr_lp_adv_ability;\r
+wire mr_an_complete;\r
+\r
+\r
+wire sli_rst;\r
+assign sli_rst = ~rst_n;\r
+\r
+\r
+// Control Advertised Ability\r
+//     When in PHY mode, choose appropriate values\r
+//     When in MAC mode, always set to zeros\r
+assign adv_link_status = gbe_mode ? 1'b0 : sgmii_mode ? 1'b1 : 1'b0;\r
+assign adv_duplex_mode = gbe_mode ? 1'b0 : sgmii_mode ? 1'b1 : 1'b0;\r
+assign adv_link_speed  = gbe_mode ? 2'd0 : sgmii_mode ? phy_speed : 2'd0;\r
+wire [7:0] gbe_bits;\r
+assign gbe_bits        = gbe_mode ? 8'h20 : 8'h01;\r
+\r
+assign debug_link_timer_short = 1'b0;  //0= normal operation\r
+                                       // when running simulation\r
+                                       // will override this value to 1'b1\r
+                                       // so that autonegotion completes\r
+\r
+// Instantiate Global Reset Controller\r
+GSR GSR_INST   (.GSR(rst_n));\r
+PUR PUR_INST   (.PUR(1'b1));\r
+\r
+// Instantiate SGMII IP Core\r
+sgmii_channel_smi_core u_sgmii_core (\r
+       // Clock and Reset\r
+       .rst_n (rst_n ),\r
+       .tx_clk_125 (tx_clk_125),\r
+       .tx_clock_enable_sink (tx_ce_sink),\r
+       .tx_clock_enable_source (tx_ce_source),\r
+       .rx_clk_125 (rx_clk_125),\r
+       .rx_clock_enable_sink (rx_ce_sink),\r
+       .rx_clock_enable_source (rx_ce_source),\r
+\r
+       // Control\r
+       .gbe_mode (gbe_mode),\r
+       .sgmii_mode (sgmii_mode),\r
+       .debug_link_timer_short (debug_link_timer_short), \r
+       .force_isolate (1'b0), \r
+       .force_loopback (force_loopback), \r
+       .force_unidir (1'b0), \r
+       .operational_rate (operational_rate),\r
+       .rx_compensation_err (),\r
+       .ctc_drop_flag (),\r
+       .ctc_add_flag (),\r
+       .an_link_ok (),\r
+\r
+\r
+       // (G)MII TX Port\r
+       .tx_d (data_in_mii),\r
+       .tx_en (en_in_mii),\r
+       .tx_er (err_in_mii),\r
+\r
+       // (G)MII RX Port\r
+       .rx_d (data_out_mii),\r
+       .rx_dv (dv_out_mii),\r
+       .rx_er (err_out_mii),\r
+       .col (),\r
+       .crs (),\r
+                  \r
+       // 8BI TX Port\r
+       .tx_data (data_chan2quad),\r
+       .tx_kcntl (kcntl_chan2quad),\r
+       .tx_disparity_cntl (disparity_cntl_chan2quad),\r
+\r
+       // 8BI RX Port\r
+       .signal_detect (link_status),\r
+       .serdes_recovered_clk (serdes_recovered_clk),\r
+       .rx_data (data_quad2chan),\r
+       .rx_kcntl (kcntl_quad2chan),\r
+       .rx_even (1'b0), // Signal Not Used in Normal Mode\r
+       .rx_disp_err (disp_err_quad2chan),\r
+       .rx_cv_err (cv_err_quad2chan),\r
+       .rx_err_decode_mode (1'b0), // 0= Normal Mode, always tie low for SC Familiy\r
+       .xmit_autoneg (xmit_autoneg),\r
+\r
+       // Management Interface  I/O\r
+       .mr_adv_ability ({adv_link_status, 2'd0, adv_duplex_mode, adv_link_speed, 2'd0, gbe_bits}),\r
+       .mr_an_enable (1'b1), \r
+       .mr_main_reset (1'b0),  \r
+       .mr_restart_an (1'b0),   \r
+\r
+       .mr_an_complete (mr_an_complete),   \r
+       .mr_lp_adv_ability (mr_lp_adv_ability), \r
+       .mr_page_rx ()\r
+       );\r
+\r
+\r
+// (G)MII Rate Resolution for SGMII IP Core\r
+rate_resolution   rate_resolution (\r
+       .gbe_mode (gbe_mode),\r
+       .sgmii_mode (sgmii_mode),\r
+       .an_enable (1'b1),\r
+       .advertised_rate (phy_speed),\r
+       .link_partner_rate (mr_lp_adv_ability[11:10]),\r
+       .non_an_rate (2'b10), // 1Gbps is rate when auto-negotiation disabled\r
+\r
+       .operational_rate (operational_rate)\r
+);\r
+\r
+wire refclk;\r
+ILVDS ILVDS_X (\r
+  .A (refclkp), \r
+  .AN(refclkn), \r
+  .Z (refclk)); \r
+\r
+assign refclk2fpga = refclk;\r
+\r
+// QUAD ASB 8B10B + SERDES\r
+            \r
+sgmii_channel_smi_pcs u_sgmii_pcs (\r
+\r
+// Global Clocks and Resets\r
+       // inputs\r
+       .rst_dual_c(~rst_n), \r
+       .serdes_rst_dual_c(~rst_n), \r
+       .pll_refclki(refclk), \r
+  .rxrefclk(refclk),\r
+  .sli_rst(sli_rst),\r
+\r
+// fpga tx datapath signals\r
+       // inputs\r
+       .tx_pcs_rst_c(1'b0), \r
+       .txdata(data_chan2quad), \r
+       .tx_k(kcntl_chan2quad), \r
+       .tx_disp_correct(disparity_cntl_chan2quad),\r
+  \r
+  .txi_clk(tx_clk_125), \r
+\r
+       // outputs\r
+       .tx_pclk(), \r
+\r
+// fpga rx datapath signals\r
+       // inputs\r
+       .rx_pcs_rst_c(1'b0), \r
+       .xmit(xmit_autoneg), \r
+  .signal_detect_c(1'b1),\r
+\r
+       // outputs\r
+       .rx_pclk(serdes_recovered_clk),\r
+       .rxdata(data_quad2chan), \r
+       .rx_k(kcntl_quad2chan), \r
+       .rx_disp_err(disp_err_quad2chan), \r
+       .rx_cv_err(cv_err_quad2chan), \r
+       .lsm_status_s(link_status), \r
+       .rx_cdr_lol_s(rx_cdr_lol), \r
+\r
+// serdes signals\r
+       // inputs\r
+       .rx_serdes_rst_c(1'b0), \r
+       .tx_serdes_rst_c(~rst_n), \r
+\r
+       .hdinp(hdinp0), \r
+       .hdinn(hdinn0), \r
+\r
+       // outputs\r
+       .hdoutp(hdoutp0), \r
+       .hdoutn(hdoutn0),\r
+  \r
+  //SCI interface\r
+       .cyawstn      (1'b0),\r
+       .sci_en       (1'b0),\r
+       .sci_en_dual  (1'b0),\r
+       .sci_sel_dual (1'b0),\r
+       .sci_sel      (1'b0),\r
+       .sci_wrdata   (8'd0),\r
+       .sci_addr     (6'd0),\r
+       .sci_rddata   (),\r
+       .sci_rd       (1'b0),\r
+       .sci_wrn      (1'b1),\r
+       .sci_int      (), \r
+\r
+// misc control signals\r
+       // inputs\r
+  .rsl_disable (1'b0),\r
+  .rsl_rst     (~rst_n),\r
+       .tx_pwrup_c  (1'b1), // powerup tx channel\r
+       .rx_pwrup_c  (1'b1), // power up rx channel\r
+  .serdes_pdb  (1'b1),\r
+\r
+       // outputs\r
+       .pll_lol()\r
+);\r
+\r
+\r
+endmodule\r
+\r

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/testbench/tb_hb.v b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/testbench/tb_hb.v
new file mode 100644 (file)
index 0000000..fc6aae5
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/sgmii_pcs_eval/testbench/tb_hb.v
@@ -0,0 +1,924 @@
+//**************************************************************************\r
+// *************************************************************************\r
+// *                LATTICE SEMICONDUCTOR CONFIDENTIAL                     *\r
+// *                         PROPRIETARY NOTE                              *\r
+// *                                                                       *\r
+// *  This software contains information confidential and proprietary      *\r
+// *  to Lattice Semiconductor Corporation.  It shall not be reproduced    *\r
+// *  in whole or in part, or transferred to other documents, or disclosed *\r
+// *  to third parties, or used for any purpose other than that for which  *\r
+// *  it was obtained, without the prior written consent of Lattice        *\r
+// *  Semiconductor Corporation.  All rights reserved.                     *\r
+// *                                                                       *\r
+// *************************************************************************\r
+//**************************************************************************\r
+\r
+`timescale 1ps/1ps\r
+\r
+module tb ;\r
+\r
+reg        clk_125 ;\r
+reg        hclk ;\r
+wire  hready_n;\r
+wire [7:0] hdataout;\r
+reg [9:0] haddr;\r
+reg [7:0] hdatain;\r
+reg hcs_n;\r
+reg hread_n;\r
+reg hwrite_n;\r
+reg hdataout_en_n;\r
+\r
+reg        rst_n ;\r
+reg        rst_tb_n;\r
+\r
+reg         clk_25;\r
+reg         clk_12_5;\r
+reg         clk_2_5;\r
+reg         clk_1_25;\r
+reg [3:0]   clk_count;\r
+reg [5:0]   sclk_count;\r
+\r
+///////////////////////\r
+\r
+reg [7:0]   drv_data;\r
+reg         drv_en;\r
+reg         drv_er;\r
+\r
+wire [7:0]   local_tx_d;\r
+wire         local_tx_en;\r
+wire         local_tx_er;\r
+\r
+wire [7:0]   mn_data;\r
+wire         mn_dv;\r
+wire         mn_er;\r
+\r
+wire [7:0]   mon_data;\r
+wire         mon_dv;\r
+wire         mon_er;\r
+\r
+///////////////////////\r
+\r
+wire [7:0]   local_rx_d;\r
+wire         local_rx_dv;\r
+wire         local_rx_er;\r
+\r
+reg            clk_mii;\r
+reg            clk_drvmon;\r
+reg [1:0]      adv_speed;\r
+reg [1:0]      mii_speed;\r
+reg            dut_sgmii_mode;\r
+reg            dut_gbe_mode;\r
+reg            GBspeed_drvmon;\r
+reg            force_loopback;\r
+\r
+\r
+//////////////////////////////////////////////////////////////////////////////\r
+\r
+initial\r
+begin\r
+   clk_125 = 1'b0 ;\r
+   hclk     = 1'b0 ;\r
+   $timeformat (-9 ,1 , "ns", 10);\r
+end\r
+\r
+// 125 Mhz clock Generation\r
+always #4000 clk_125 = ~clk_125 ;\r
+\r
+// HCLK Clock Generation\r
+always #10000 hclk = ~hclk ;\r
+\r
+// 25Mhz Clock Generation\r
+always @(posedge clk_125 or negedge rst_tb_n)\r
+begin\r
+       if (rst_tb_n == 1'b0) begin\r
+               clk_count <= 4'd0;\r
+               clk_25 <= 1'd0;\r
+               clk_12_5 <= 1'd0;\r
+       end\r
+       else begin\r
+\r
+               // These statements implement a "divide by 5"\r
+               if (clk_count == 4'd4)\r
+                       clk_count <= 4'd0;\r
+               else\r
+                       clk_count <= clk_count + 1;\r
+\r
+\r
+               if ((clk_count==4'd1) || (clk_count==4'd4))\r
+                       clk_25 <= ~clk_25;\r
+\r
+               if ((clk_25 == 1'd0) && (clk_count == 4'd1))\r
+                       clk_12_5 <= ~clk_12_5;\r
+\r
+\r
+       end\r
+end \r
+\r
+\r
+\r
+// 2.5Mhz Clock Generation\r
+always @(posedge clk_125 or negedge rst_tb_n)\r
+begin\r
+       if (rst_tb_n == 1'b0) begin\r
+               sclk_count <= 0;\r
+               clk_2_5 <= 0;\r
+               clk_1_25 <= 0;\r
+       end\r
+       else begin\r
+\r
+               // These statements implement a "divide by 50"\r
+               if (sclk_count == 49)\r
+                       sclk_count <= 0;\r
+               else\r
+                       sclk_count <= sclk_count + 1;\r
+\r
+\r
+               if ((sclk_count==24) || (sclk_count==49))\r
+                       clk_2_5 <= ~clk_2_5;\r
+\r
+               if ((clk_2_5 == 0) && (sclk_count == 1))\r
+                       clk_1_25 <= ~clk_1_25;\r
+\r
+       end\r
+end \r
+\r
+\r
+// choose mii clock based on DUT_MII_SPEED\r
+always @(*)\r
+begin\r
+       if (mii_speed == 2'b01)\r
+               clk_mii = 1'b1;\r
+       else if (mii_speed == 2'b00)\r
+               clk_mii = 1'b1;\r
+       else\r
+               clk_mii = 1'b1;\r
+end\r
+\r
+// choose driver and monitor clock\r
+always @(*)\r
+begin\r
+       if (mii_speed == 2'b01)\r
+               clk_drvmon = clk_12_5;\r
+       else if (mii_speed == 2'b00)\r
+               clk_drvmon = clk_1_25;\r
+       else\r
+               clk_drvmon = clk_125;\r
+end\r
+\r
+\r
+GSR GSR_INST   (.GSR(rst_n));\r
+PUR PUR_INST   (.PUR(1'b1));\r
+OLVDS O_CLK_BUF (.A(clk_125), .Z(clk_125_p), .ZN(clk_125_n));\r
+\r
+//////////////////////////////////////////////////////////////////////////////\r
+\r
+// Device Under Test (DUT)\r
+top_hb top (\r
+   .rst_n ( rst_n ) ,\r
+   .gbe_mode ( dut_gbe_mode ) ,\r
+   .sgmii_mode ( dut_sgmii_mode ) ,\r
+\r
+   .hclk (hclk),\r
+   .hcs_n (hcs_n),\r
+   .hwrite_n (hwrite_n),\r
+   .haddr (haddr[5:0]),\r
+   .hdatain (hdatain),\r
+\r
+   .hdataout (hdataout),\r
+   .hready_n (hready_n),\r
+\r
+   // G/MII Interface\r
+   .data_in_mii ( {local_tx_d} ) ,\r
+   .en_in_mii ( local_tx_en ) ,\r
+   .err_in_mii ( local_tx_er ) ,\r
+                  \r
+   .data_out_mii ( local_rx_d ) ,\r
+   .dv_out_mii ( local_rx_dv ) ,\r
+   .err_out_mii ( local_rx_er ) ,\r
+   .col_out_mii (  ) ,\r
+   .crs_out_mii (  ) ,\r
+\r
+   .debug_link_timer_short(1'b1),\r
+   .mr_an_complete(mr_an_complete),\r
+\r
+   // GMII Clocks\r
+   .in_clk_125    ( clk_125 ) ,\r
+   .in_ce_sink    ( clock_enable ) ,\r
+   .in_ce_source  ( clock_enable ) ,\r
+   .out_clk_125   ( clk_125 ) ,\r
+   .out_ce_sink   ( clock_enable ) ,\r
+   .out_ce_source ( ) ,\r
+\r
+   // SERDES Interface\r
+   .refclkp ( clk_125_p ) ,\r
+   .refclkn ( clk_125_n ) ,\r
+   .hdoutp0 ( local_serdes_p ) ,\r
+   .hdoutn0 ( local_serdes_n ) ,\r
+   .hdinp0 ( remote_serdes_p ),\r
+   .hdinn0 ( remote_serdes_n )\r
+   );\r
+\r
+\r
+// Loopback DUT (G)MII Interface\r
+assign local_tx_d = local_rx_d;\r
+assign local_tx_en = local_rx_dv;\r
+assign local_tx_er = local_rx_er;\r
+\r
+\r
+// Testbench SGMII Channel\r
+sgmii_node sgmii_node (\r
+       // Control Interface\r
+       .rst_n (rst_n) ,\r
+       .gbe_mode (dut_gbe_mode) ,\r
+       .sgmii_mode (~dut_sgmii_mode) ,\r
+       .force_loopback (force_loopback) ,\r
+       .phy_speed (adv_speed) ,\r
+\r
+       // G/MII Interface\r
+       .data_in_mii (drv_data),\r
+       .en_in_mii (drv_en),\r
+       .err_in_mii (drv_er),\r
+\r
+       .data_out_mii (mon_data),\r
+       .dv_out_mii (mon_dv),\r
+       .err_out_mii (mon_er),\r
+\r
+       // GB Timing References\r
+       .tx_clk_125 (clk_125) ,\r
+       .tx_ce_source () ,\r
+       .tx_ce_sink (clock_enable) ,\r
+\r
+       .rx_clk_125 (clk_125) ,\r
+       .rx_ce_source () ,\r
+       .rx_ce_sink (clock_enable) ,\r
+                  \r
+       // SERDES Interface\r
+       .refclkp (clk_125_p) ,\r
+       .refclkn (clk_125_n) ,\r
+       .hdoutp0 (remote_serdes_p) ,\r
+       .hdoutn0 (remote_serdes_n) ,\r
+       .hdinp0 (local_serdes_p ),\r
+       .hdinn0 (local_serdes_n )\r
+);\r
+\r
+\r
+\r
+\r
+\r
+\r
+// Compare MII In/Out Ports of DUT\r
+mii_monitor   mii_monitor (\r
+       .rst_n (rst_n),\r
+       .clk (clk_drvmon),\r
+       .GBspeed (GBspeed_drvmon) ,\r
+\r
+       .data_in_ref (drv_data),\r
+       .dv_in_ref (drv_en),\r
+       .err_in_ref (drv_er),\r
+\r
+       .data_in_dut (mon_data),\r
+       .dv_in_dut (mon_dv),\r
+       .err_in_dut (mon_er)\r
+);\r
+\r
+\r
+\r
+//////////////////////////////////////////////////////////////////////////////\r
+\r
+// THIS BLOCK CONTROLS TEST SCRIPT FLOW\r
+initial\r
+begin\r
+       rst_tb_n   = 1'b0 ;\r
+       rst_n = 0;\r
+\r
+       haddr = 10'd0;\r
+       hdatain = 8'd0;\r
+       hcs_n = 1'b1;\r
+       hread_n = 1'b1;\r
+       hwrite_n = 1'b1;\r
+       hdataout_en_n = 1'b1;\r
+\r
+       drv_data = 8'd0;\r
+       drv_en = 1'd0;\r
+       drv_er = 1'd0;\r
+\r
+       force_loopback = 1'b0;\r
+\r
+       // the following lines allow short autonegotiation timer to operate\r
+       force sgmii_node.debug_link_timer_short = 1'b1 ;\r
+  \r
+  // For the Soft LOL and RSL logic in simulation\r
+  @(posedge clk_125);\r
+  force tb.top.u_sgmii.u_sgmii_pcs.sll_inst.LRCLK_TC_w = 16'd100;\r
+  force tb.top.u_sgmii.u_sgmii_pcs.sll_inst.rcount_tc  = 22'd100;\r
+  force tb.sgmii_node.u_sgmii_pcs.sll_inst.LRCLK_TC_w  = 16'd100;\r
+  force tb.sgmii_node.u_sgmii_pcs.sll_inst.rcount_tc   = 22'd100;\r
+\r
+/////// SET SGMII MODE  == 1GB Rate /////////////////////////////////////////////////////////////////////\r
+\r
+       GBspeed_drvmon = 1;\r
+       mii_speed = 2'b10; // 1GB\r
+       adv_speed = 2'b10; // 1GB\r
+       dut_sgmii_mode = 1'b0; // MAC\r
+       dut_gbe_mode = 1'b0;   // SGMII\r
+\r
+       #1000000               // Wait for 100 nanoseconds\r
+       $display(" ") ;\r
+       $display(" !!!!!!!!!!  Starting SGMII Tests  !!!!!!!!!!");\r
+       $display(" ") ;\r
+       $display(" ") ;\r
+       $display(" ") ;\r
+       $display(" ") ;\r
+       $display("    MII operating @ 1Gbps in SGMII Mode") ;\r
+       $display(" ") ;\r
+       $display("    Device Under Test operating in SGMII MAC mode") ;\r
+       $display(" ") ;\r
+\r
+\r
+       // release testbench reset\r
+       #1000000               // Wait for 100 nanoseconds\r
+       rst_tb_n   <= 1'b1 ;\r
+\r
+       // Perform Device Resets\r
+       #1000000               // Wait for 1 microsecond\r
+       rst_n = 0;             // Apply reset\r
+       #1000000               // Wait for 1 microsecond\r
+       rst_n = 1;             // Release reset\r
+       #1000000               // Wait for 1 microsecond\r
+\r
+\r
+////////////////////\r
+\r
+       #1000000               // Wait for 1 microsecond\r
+\r
+       @(posedge hclk);\r
+// Quick Check of SGMII Management Registers\r
+       $display(" TEST#1 of 3 : Check SGMII Management Registers before Autonegotiaion Completes ");\r
+\r
+       hb_read (10'h000, 8'h00, 8'h00); // Reg 0\r
+       hb_read (10'h001, 8'h00, 8'h00);\r
+       $display("  ") ;\r
+\r
+       hb_read (10'h002, 8'h00, 8'h00); // Reg 1\r
+       hb_read (10'h003, 8'h00, 8'h00);\r
+       $display("  ") ;\r
+\r
+       hb_read (10'h008, 8'h00, 8'h00); // Reg 4\r
+       hb_read (10'h009, 8'h00, 8'h00);\r
+       $display("  ") ;\r
+\r
+       hb_read (10'h00A, 8'h00, 8'h00); // Reg 5\r
+       hb_read (10'h00B, 8'h00, 8'h00);\r
+       $display("  ") ;\r
+\r
+       hb_read (10'h00C, 8'h00, 8'h00); // Reg 6\r
+       hb_read (10'h00D, 8'h00, 8'h00);\r
+       $display("  ") ;\r
+\r
+\r
+// Wait for Auto Negotiation to Complete\r
+       wait (mr_an_complete) \r
+\r
+       @(posedge hclk);\r
+// Quick Check of SGMII Management Registers\r
+       #2000000              // Wait for 2.00 microseconds\r
+       $display(" TEST#2 of 3 : Check SGMII Management Registers after Autonegotiaion Completes ");\r
+\r
+       hb_read (10'h000, 8'h40, 8'hFF); // Reg 0\r
+       hb_read (10'h001, 8'h11, 8'hFF);\r
+       $display("  ") ;\r
+\r
+       hb_read (10'h002, 8'h2C, 8'h00); // Reg 1\r
+       hb_read (10'h003, 8'h00, 8'h00);\r
+\r
+       hb_read (10'h002, 8'h2C, 8'hFF); // Reg 1 Re-Read\r
+       hb_read (10'h003, 8'h01, 8'hFF);\r
+       $display("  ") ;\r
+\r
+       hb_read (10'h008, 8'h01, 8'hFF); // Reg 4\r
+       hb_read (10'h009, 8'h40, 8'hFF);\r
+       $display("  ") ;\r
+\r
+       hb_read (10'h00A, 8'h01, 8'hFF); // Reg 5\r
+       hb_read (10'h00B, 8'hD8, 8'hFF);\r
+       $display("  ") ;\r
+\r
+       hb_read (10'h00C, 8'h02, 8'hFF); // Reg 6\r
+       hb_read (10'h00D, 8'h00, 8'hFF);\r
+\r
+       hb_read (10'h01E, 8'h00, 8'hFF); // Reg F\r
+       hb_read (10'h01F, 8'h80, 8'hFF);\r
+       $display("  ") ;\r
+\r
+\r
+       #10000000              // Wait for 10.00 microseconds\r
+\r
+\r
+       @(posedge clk_drvmon );\r
+// Send 4 Ethernet Frames\r
+       $display(" TEST#3 of 3 : Send 4 ethernet frames");\r
+       //send_local_gmii_frame (preamble size, dest addr, src addr, payload len, sequence number); \r
+       send_mii_frame (7, 'h112233445566, 'h778899aabbcc, 512, 0); \r
+       send_mii_frame (7, 'h112233445566, 'h778899aabbcc, 512, 1); \r
+       send_mii_frame (7, 'h112233445566, 'h778899aabbcc, 512, 2); \r
+       send_mii_frame (7, 'h112233445566, 'h778899aabbcc, 512, 3); \r
+\r
+       repeat (2000) @(posedge clk_drvmon );\r
+\r
+\r
+\r
+       $display("\n\n\n\n") ;\r
+       $display(" TEST#4  : Test Loopback Function");\r
+       force_loopback = 1'b1;\r
+       repeat (500) @(posedge clk_drvmon );\r
+\r
+       send_mii_frame (7, 'h112233445566, 'h778899aabbcc, 512, 4); \r
+       repeat (500) @(posedge clk_drvmon );\r
+\r
+       force_loopback = 1'b0;\r
+       repeat (500) @(posedge clk_drvmon );\r
+\r
+       send_mii_frame (7, 'h112233445566, 'h778899aabbcc, 512, 5); \r
+       repeat (1000) @(posedge clk_drvmon );\r
+\r
+\r
+\r
+\r
+\r
+\r
+       $display("\n\n\n\n") ;\r
+       $display(" TEST#5  : Test Isolate Function");\r
+       hb_write (10'h001, 8'h15);\r
+       hb_read (10'h000, 8'h40, 8'hFF);\r
+       hb_read (10'h001, 8'h15, 8'hFF);\r
+\r
+       send_mii_frame (7, 'h112233445566, 'h778899aabbcc, 512, 6); \r
+       repeat (500) @(posedge clk_drvmon );\r
+\r
+       hb_write (10'h001, 8'h11);\r
+       hb_read (10'h000, 8'h40, 8'hFF);\r
+       hb_read (10'h001, 8'h11, 8'hFF);\r
+\r
+       repeat (500) @(posedge clk_drvmon );\r
+\r
+       send_mii_frame (7, 'h112233445566, 'h778899aabbcc, 512, 7); \r
+       repeat (1000) @(posedge clk_drvmon );\r
+       $display("**** Expected Frame Mismatch Failure, Due to Isolate Function****");\r
+\r
+\r
+\r
+\r
+\r
+       $display("\n\n\n\n") ;\r
+       $display(" !!!!!!!!!!  Testbench Done.  All Tests Completed  !!!!!!!!!!");\r
+       $stop ;\r
+end\r
+\r
+// END OF TEST SCRIPT FLOW ////////////////////////////////////////////////////////////\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+//////////////////////////////////////////////////////////////////////////////\r
+task send_mii_frame ;\r
+input [7:0]   preamble_len; // Total number of bytes\r
+input [47:0]  dest_add;\r
+input [47:0]  src_add;\r
+input [15:0]  payld_len;\r
+input [15:0]  sequence_num;\r
+\r
+integer    i;\r
+reg[31:0]  j;\r
+reg [31:0] FCS;\r
+\r
+begin\r
+\r
+// Put Preamble ///////////////////\r
+for(i = 0; i < preamble_len; i = i+1) begin\r
+       if (GBspeed_drvmon) begin\r
+               drv_en = #1 1'b1;   \r
+               drv_er = #1 1'b0;   \r
+               drv_data  = #1 8'h55;\r
+               FCS  = #1 32'd0;\r
+               @(posedge clk_drvmon);\r
+       end\r
+       else begin\r
+               drv_en = #1 1'b1;   \r
+               drv_er = #1 1'b0;   \r
+               drv_data  = #1 8'h05;\r
+               FCS  = #1 32'd0;\r
+               @(posedge clk_drvmon);\r
+               drv_en = #1 1'b1;   \r
+               drv_er = #1 1'b0;   \r
+               drv_data  = #1 8'h05;\r
+               FCS  = #1 32'd0;\r
+               @(posedge clk_drvmon);\r
+       end\r
+end\r
+\r
+// Put SFD ////////////////////////\r
+       if (GBspeed_drvmon) begin\r
+               drv_en = #1 1'b1;   \r
+               drv_er = #1 1'b0;   \r
+               drv_data  = #1 8'hd5;\r
+               @(posedge clk_drvmon);\r
+       end\r
+       else begin\r
+               drv_en = #1 1'b1;   \r
+               drv_er = #1 1'b0;   \r
+               drv_data  = #1 8'h05; // low nibble\r
+               @(posedge clk_drvmon);\r
+               drv_en = #1 1'b1;   \r
+               drv_er = #1 1'b0;   \r
+               drv_data  = #1 8'h0d; // high nibble\r
+               @(posedge clk_drvmon);\r
+       end\r
+\r
+// Put Destination Address ///////////////////////\r
+for(i = 0; i < 6; i = i+1) begin\r
+\r
+       drv_en = #1 1'b1;   \r
+       drv_er = #1 1'b0;   \r
+\r
+       if (GBspeed_drvmon) begin\r
+               case (i)\r
+                       0: begin drv_data  = #1 dest_add[47:40]; FCS = #1 (FCS + dest_add[47:40]);  @(posedge clk_drvmon); end\r
+                       1: begin drv_data  = #1 dest_add[39:32]; FCS = #1 (FCS + dest_add[39:32]);  @(posedge clk_drvmon); end\r
+                       2: begin drv_data  = #1 dest_add[31:24]; FCS = #1 (FCS + dest_add[31:24]);  @(posedge clk_drvmon); end\r
+                       3: begin drv_data  = #1 dest_add[23:16]; FCS = #1 (FCS + dest_add[23:16]);  @(posedge clk_drvmon); end\r
+                       4: begin drv_data  = #1 dest_add[15:8];  FCS = #1 (FCS + dest_add[15:8]);   @(posedge clk_drvmon); end\r
+                       5: begin drv_data  = #1 dest_add[7:0];   FCS = #1 (FCS + dest_add[7:0]);    @(posedge clk_drvmon); end\r
+               endcase\r
+\r
+       end\r
+       else begin\r
+               case (i)\r
+                       0:  begin \r
+                               drv_data  = #1 {4'd0, dest_add[43:40]};\r
+                               @(posedge clk_drvmon);\r
+                               drv_data  = #1 {4'd0, dest_add[47:44]}; FCS = #1 (FCS + dest_add[47:40]);\r
+                               @(posedge clk_drvmon);\r
+                           end\r
+\r
+                       1:  begin \r
+                               drv_data  = #1 {4'd0, dest_add[35:32]};\r
+                               @(posedge clk_drvmon);\r
+                               drv_data  = #1 {4'd0, dest_add[39:36]}; FCS = #1 (FCS + dest_add[39:32]);\r
+                               @(posedge clk_drvmon);\r
+                           end\r
+\r
+                       2:  begin \r
+                               drv_data  = #1 {4'd0, dest_add[27:24]};\r
+                               @(posedge clk_drvmon);\r
+                               drv_data  = #1 {4'd0, dest_add[31:28]}; FCS = #1 (FCS + dest_add[31:24]);\r
+                               @(posedge clk_drvmon);\r
+                           end\r
+\r
+                       3:  begin \r
+                               drv_data  = #1 {4'd0, dest_add[19:16]};\r
+                               @(posedge clk_drvmon);\r
+                               drv_data  = #1 {4'd0, dest_add[23:20]}; FCS = #1 (FCS + dest_add[23:16]);\r
+                               @(posedge clk_drvmon);\r
+                           end\r
+\r
+                       4:  begin \r
+                               drv_data  = #1 {4'd0, dest_add[11:8]};\r
+                               @(posedge clk_drvmon);\r
+                               drv_data  = #1 {4'd0, dest_add[15:12]}; FCS = #1 (FCS + dest_add[15:8]);\r
+                               @(posedge clk_drvmon);\r
+                           end\r
+\r
+                       5: begin \r
+                               drv_data  = #1 {4'd0, dest_add[3:0]};\r
+                               @(posedge clk_drvmon);\r
+                               drv_data  = #1 {4'd0, dest_add[7:4]};   FCS = #1 (FCS + dest_add[7:0]);\r
+                               @(posedge clk_drvmon);\r
+                           end\r
+               endcase\r
+       end\r
+end\r
+\r
+// Put Source Address ///////////////////////\r
+for(i = 0; i < 6; i = i+1) begin\r
+\r
+       drv_en = #1 1'b1;   \r
+       drv_er = #1 1'b0;   \r
+\r
+       if (GBspeed_drvmon) begin\r
+               case (i)\r
+                       0: begin drv_data  = #1 src_add[47:40]; FCS = #1 (FCS + src_add[47:40]);  @(posedge clk_drvmon); end\r
+                       1: begin drv_data  = #1 src_add[39:32]; FCS = #1 (FCS + src_add[39:32]);  @(posedge clk_drvmon); end\r
+                       2: begin drv_data  = #1 src_add[31:24]; FCS = #1 (FCS + src_add[31:24]);  @(posedge clk_drvmon); end\r
+                       3: begin drv_data  = #1 src_add[23:16]; FCS = #1 (FCS + src_add[23:16]);  @(posedge clk_drvmon); end\r
+                       4: begin drv_data  = #1 src_add[15:8];  FCS = #1 (FCS + src_add[15:8]);   @(posedge clk_drvmon); end\r
+                       5: begin drv_data  = #1 src_add[7:0];   FCS = #1 (FCS + src_add[7:0]);    @(posedge clk_drvmon); end\r
+               endcase\r
+\r
+       end\r
+       else begin\r
+               case (i)\r
+                       0:  begin \r
+                               drv_data  = #1 {4'd0, src_add[43:40]};\r
+                               @(posedge clk_drvmon);\r
+                               drv_data  = #1 {4'd0, src_add[47:44]}; FCS = #1 (FCS + src_add[47:40]);\r
+                               @(posedge clk_drvmon);\r
+                           end\r
+\r
+                       1:  begin \r
+                               drv_data  = #1 {4'd0, src_add[35:32]};\r
+                               @(posedge clk_drvmon);\r
+                               drv_data  = #1 {4'd0, src_add[39:36]}; FCS = #1 (FCS + src_add[39:32]);\r
+                               @(posedge clk_drvmon);\r
+                           end\r
+\r
+                       2:  begin \r
+                               drv_data  = #1 {4'd0, src_add[27:24]};\r
+                               @(posedge clk_drvmon);\r
+                               drv_data  = #1 {4'd0, src_add[31:28]}; FCS = #1 (FCS + src_add[31:24]);\r
+                               @(posedge clk_drvmon);\r
+                           end\r
+\r
+                       3:  begin \r
+                               drv_data  = #1 {4'd0, src_add[19:16]};\r
+                               @(posedge clk_drvmon);\r
+                               drv_data  = #1 {4'd0, src_add[23:20]}; FCS = #1 (FCS + src_add[23:16]);\r
+                               @(posedge clk_drvmon);\r
+                           end\r
+\r
+                       4:  begin \r
+                               drv_data  = #1 {4'd0, src_add[11:8]};\r
+                               @(posedge clk_drvmon);\r
+                               drv_data  = #1 {4'd0, src_add[15:12]}; FCS = #1 (FCS + src_add[15:8]);\r
+                               @(posedge clk_drvmon);\r
+                           end\r
+\r
+                       5: begin \r
+                               drv_data  = #1 {4'd0, src_add[3:0]};\r
+                               @(posedge clk_drvmon);\r
+                               drv_data  = #1 {4'd0, src_add[7:4]};   FCS = #1 (FCS + src_add[7:0]);\r
+                               @(posedge clk_drvmon);\r
+                           end\r
+               endcase\r
+       end\r
+end\r
+\r
+// Put Length ////////////////////////\r
+       if (GBspeed_drvmon) begin\r
+               drv_en = #1 1'b1;   \r
+               drv_er = #1 1'b0;   \r
+               drv_data  = #1 payld_len[15:8];\r
+               FCS  = #1 FCS + payld_len[15:8];\r
+               @(posedge clk_drvmon);\r
+               drv_en = #1 1'b1;   \r
+               drv_er = #1 1'b0;   \r
+               drv_data  = #1 payld_len[7:0];\r
+               FCS  = #1 FCS + payld_len[7:0];\r
+               @(posedge clk_drvmon);\r
+       end\r
+       else begin\r
+               drv_en = #1 1'b1;   \r
+               drv_er = #1 1'b0;   \r
+               drv_data  = #1 {4'd0, payld_len[11:8]};\r
+               @(posedge clk_drvmon);\r
+               drv_en = #1 1'b1;   \r
+               drv_er = #1 1'b0;   \r
+               drv_data  = #1 {4'd0, payld_len[15:12]};\r
+               FCS  = #1 FCS + payld_len[15:8];\r
+               @(posedge clk_drvmon);\r
+\r
+               drv_en = #1 1'b1;   \r
+               drv_er = #1 1'b0;   \r
+               drv_data  = #1 {4'd0, payld_len[3:0]};\r
+               @(posedge clk_drvmon);\r
+               drv_en = #1 1'b1;   \r
+               drv_er = #1 1'b0;   \r
+               drv_data  = #1 {4'd0, payld_len[7:4]};\r
+               FCS  = #1 FCS + payld_len[7:0];\r
+               @(posedge clk_drvmon);\r
+       end\r
+\r
+// Put Sequence Num (part of the payload) ////\r
+       if (GBspeed_drvmon) begin\r
+               drv_en = #1 1'b1;   \r
+               drv_er = #1 1'b0;   \r
+               drv_data  = #1 sequence_num[7:0];\r
+               FCS  = #1 FCS + sequence_num[7:0];\r
+               @(posedge clk_drvmon);\r
+       end\r
+       else begin\r
+               drv_en = #1 1'b1;   \r
+               drv_er = #1 1'b0;   \r
+               drv_data  = #1 {4'd0, sequence_num[3:0]};\r
+               @(posedge clk_drvmon);\r
+               drv_en = #1 1'b1;   \r
+               drv_er = #1 1'b0;   \r
+               drv_data  = #1 {4'd0, sequence_num[7:4]};\r
+               FCS  = #1 FCS + sequence_num[7:0];\r
+               @(posedge clk_drvmon);\r
+       end\r
+\r
+// Put Payload ///////////////////////\r
+for(j = 1; j < payld_len; j = j+1) begin\r
+       if (GBspeed_drvmon) begin\r
+               drv_en = #1 1'b1;   \r
+               drv_er = #1 1'b0;   \r
+               drv_data  = #1 j;\r
+               FCS  = #1 FCS + j[7:0];\r
+               @(posedge clk_drvmon);\r
+       end\r
+       else begin\r
+               drv_en = #1 1'b1;   \r
+               drv_er = #1 1'b0;   \r
+               drv_data  = #1 {4'd0, j[3:0]}; // low nibble\r
+               @(posedge clk_drvmon);\r
+\r
+               drv_en = #1 1'b1;   \r
+               drv_er = #1 1'b0;   \r
+               drv_data  = #1 {4'd0, j[7:4]}; // high nibble\r
+               FCS  = #1 FCS + j[7:0];\r
+               @(posedge clk_drvmon);\r
+       end\r
+end\r
+\r
+// Put FCS ///////////////////////\r
+       if (GBspeed_drvmon) begin\r
+               drv_en = #1 1'b1;   \r
+               drv_er = #1 1'b0;   \r
+               drv_data  = #1 FCS[31:24];\r
+               @(posedge clk_drvmon);\r
+               drv_en = #1 1'b1;   \r
+               drv_er = #1 1'b0;   \r
+               drv_data  = #1 FCS[23:16];\r
+               @(posedge clk_drvmon);\r
+               drv_en = #1 1'b1;   \r
+               drv_er = #1 1'b0;   \r
+               drv_data  = #1 FCS[15:8];\r
+               @(posedge clk_drvmon);\r
+               drv_en = #1 1'b1;   \r
+               drv_er = #1 1'b0;   \r
+               drv_data  = #1 FCS[7:0];\r
+               @(posedge clk_drvmon);\r
+       end\r
+       else begin\r
+               drv_en = #1 1'b1;   \r
+               drv_er = #1 1'b0;   \r
+               drv_data  = #1 {4'd0, FCS[27:24]};\r
+               @(posedge clk_drvmon);\r
+               drv_en = #1 1'b1;   \r
+               drv_er = #1 1'b0;   \r
+               drv_data  = #1 {4'd0, FCS[31:28]};\r
+               @(posedge clk_drvmon);\r
+\r
+               drv_en = #1 1'b1;   \r
+               drv_er = #1 1'b0;   \r
+               drv_data  = #1 {4'd0, FCS[19:16]};\r
+               @(posedge clk_drvmon);\r
+               drv_en = #1 1'b1;   \r
+               drv_er = #1 1'b0;   \r
+               drv_data  = #1 {4'd0, FCS[23:20]};\r
+               @(posedge clk_drvmon);\r
+\r
+               drv_en = #1 1'b1;   \r
+               drv_er = #1 1'b0;   \r
+               drv_data  = #1 {4'd0, FCS[11:8]};\r
+               @(posedge clk_drvmon);\r
+               drv_en = #1 1'b1;   \r
+               drv_er = #1 1'b0;   \r
+               drv_data  = #1 {4'd0, FCS[15:12]};\r
+               @(posedge clk_drvmon);\r
+\r
+               drv_en = #1 1'b1;   \r
+               drv_er = #1 1'b0;   \r
+               drv_data  = #1 {4'd0, FCS[3:0]};\r
+               @(posedge clk_drvmon);\r
+               drv_en = #1 1'b1;   \r
+               drv_er = #1 1'b0;   \r
+               drv_data  = #1 {4'd0, FCS[7:4]};\r
+               @(posedge clk_drvmon);\r
+       end\r
+\r
+// Put Carrier Extension ///////////////////////\r
+//\r
+//\r
+////////////////////////////////////////////////\r
+\r
+// Put Inter packet gap ///////////\r
+for(i = 1; i <= 12; i = i+1) begin\r
+       drv_en = #1 1'b0;   \r
+       drv_er = #1 1'b0;\r
+       @(posedge clk_drvmon);\r
+end\r
+\r
+\r
+\r
+end\r
+endtask\r
+\r
+\r
+\r
+\r
+\r
+task hb_write;\r
+\r
+input [9:0] address;\r
+input [7:0] data;\r
+\r
+begin\r
+      @(posedge hclk);\r
+      \r
+      #1\r
+      haddr[9:0] = address[9:0];\r
+      hdatain[7:0] = data[7:0];\r
+\r
+      hcs_n = 1'b0; // assert\r
+      hread_n = 1'b1;\r
+      hwrite_n = 1'b0; // assert\r
+      hdataout_en_n = 1'b1;\r
+\r
+      // wait for an acknowledge\r
+      @ (negedge hready_n); \r
+\r
+      @(posedge hclk);\r
+      #1\r
+      hcs_n = 1'b1; \r
+      hread_n = 1'b1;\r
+      hwrite_n = 1'b1;\r
+      hdataout_en_n = 1'b1;\r
+\r
+      @(posedge hclk);\r
+      #1\r
+      hcs_n = 1'b1; \r
+      hread_n = 1'b1;\r
+      hwrite_n = 1'b1;\r
+      hdataout_en_n = 1'b1;\r
+end\r
+\r
+endtask\r
+\r
+\r
+\r
+\r
+\r
+task hb_read;\r
+\r
+input [9:0] address;\r
+input [7:0] expected_data;\r
+input [7:0] mask;\r
+\r
+reg [7:0]  read_data;\r
+\r
+begin\r
+      @(posedge hclk);\r
+      \r
+      #1\r
+      haddr[9:0] = address[9:0];\r
+\r
+      hcs_n = 1'b0; // assert\r
+      hread_n = 1'b0;\r
+      hwrite_n = 1'b1;\r
+      hdataout_en_n = 1'b0; // assert\r
+\r
+      // wait for an acknowledge\r
+      @ (negedge hready_n); \r
+\r
+      @(posedge hclk);\r
+      #1\r
+      read_data[7:0] = hdataout[7:0];\r
+      hcs_n = 1'b1; \r
+      hread_n = 1'b1;\r
+      hwrite_n = 1'b1;\r
+      hdataout_en_n = 1'b1;\r
+\r
+      if ((read_data & mask) != (expected_data & mask)) begin\r
+         $display ("ERROR : Read-data mismatch at address %h", address) ;\r
+         $display ("      : Expected Data : %h. Read Data : %h.", (expected_data & mask), read_data ) ;\r
+      end\r
+      else begin\r
+         $display (" INFO : Read Check Passed at address %h", address) ;\r
+      end\r
+\r
+\r
+      @(posedge hclk);\r
+      #1\r
+      hcs_n = 1'b1; \r
+      hread_n = 1'b1;\r
+      hwrite_n = 1'b1;\r
+      hdataout_en_n = 1'b1;\r
+end\r
+\r
+endtask\r
+\r
+\r
+\r
+\r
+\r
+endmodule\r
+// =============================================================================\r
+\r

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/stdout.log.bak.1 b/gbe/cores/sgmii/sgmii_channel_smi/stdout.log.bak.1
new file mode 100644 (file)
index 0000000..2960279
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/stdout.log.bak.1
@@ -0,0 +1,75 @@
+Running in Lattice mode
+
+Starting:    /home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/mbin/synbatch
+Install:     /home/soft/lattice/diamond/3.10_x64/synpbase
+Hostname:    lxhadeb07
+Date:        Mon Apr 29 14:09:33 2019
+Version:     M-2017.03L-SP1-1
+
+Arguments:   -product synplify_pro -batch syn_results/sgmii_channel_smi.prj
+ProductType: synplify_pro
+
+
+
+
+log file: "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srr"
+Running: syn_results in foreground
+
+Running sgmii_channel_smi|syn_results
+
+Running: compile (Compile) on sgmii_channel_smi|syn_results
+# Mon Apr 29 14:09:33 2019
+
+Running: compile_flow (Compile Process) on sgmii_channel_smi|syn_results
+# Mon Apr 29 14:09:33 2019
+
+Running: compiler (Compile Input) on sgmii_channel_smi|syn_results
+# Mon Apr 29 14:09:33 2019
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/synwork/sgmii_channel_smi_comp.srs to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srs
+
+compiler completed
+# Mon Apr 29 14:09:36 2019
+
+Return Code: 0
+Run Time:00h:00m:03s
+
+Running: multi_srs_gen (Multi-srs Generator) on sgmii_channel_smi|syn_results
+# Mon Apr 29 14:09:36 2019
+
+multi_srs_gen completed
+# Mon Apr 29 14:09:36 2019
+
+Return Code: 0
+Run Time:00h:00m:00s
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/synwork/sgmii_channel_smi_mult.srs to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srs
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srf
+Complete: Compile Process on sgmii_channel_smi|syn_results
+
+Running: premap (Pre-mapping) on sgmii_channel_smi|syn_results
+# Mon Apr 29 14:09:36 2019
+
+premap completed with warnings
+# Mon Apr 29 14:09:37 2019
+
+Return Code: 1
+Run Time:00h:00m:01s
+Complete: Compile on sgmii_channel_smi|syn_results
+
+Running: map (Map) on sgmii_channel_smi|syn_results
+# Mon Apr 29 14:09:37 2019
+License granted for 4 parallel jobs
+
+Running: fpga_mapper (Map & Optimize) on sgmii_channel_smi|syn_results
+# Mon Apr 29 14:09:37 2019
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/synwork/sgmii_channel_smi_m.srm to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srm
+
+fpga_mapper completed with warnings
+# Mon Apr 29 14:09:40 2019
+
+Return Code: 1
+Run Time:00h:00m:03s
+Complete: Map on sgmii_channel_smi|syn_results
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srf
+Complete: Logic Synthesis on sgmii_channel_smi|syn_results
+exit status=0
+exit status=0

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/stdout.log.bak.2 b/gbe/cores/sgmii/sgmii_channel_smi/stdout.log.bak.2
new file mode 100644 (file)
index 0000000..1ac7cca
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/stdout.log.bak.2
@@ -0,0 +1,75 @@
+Running in Lattice mode
+
+Starting:    /home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/mbin/synbatch
+Install:     /home/soft/lattice/diamond/3.10_x64/synpbase
+Hostname:    lxhadeb07
+Date:        Mon Apr 29 14:08:39 2019
+Version:     M-2017.03L-SP1-1
+
+Arguments:   -product synplify_pro -batch syn_results/sgmii_channel_smi.prj
+ProductType: synplify_pro
+
+
+
+
+log file: "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srr"
+Running: syn_results in foreground
+
+Running sgmii_channel_smi|syn_results
+
+Running: compile (Compile) on sgmii_channel_smi|syn_results
+# Mon Apr 29 14:08:39 2019
+
+Running: compile_flow (Compile Process) on sgmii_channel_smi|syn_results
+# Mon Apr 29 14:08:39 2019
+
+Running: compiler (Compile Input) on sgmii_channel_smi|syn_results
+# Mon Apr 29 14:08:39 2019
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/synwork/sgmii_channel_smi_comp.srs to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srs
+
+compiler completed
+# Mon Apr 29 14:08:41 2019
+
+Return Code: 0
+Run Time:00h:00m:02s
+
+Running: multi_srs_gen (Multi-srs Generator) on sgmii_channel_smi|syn_results
+# Mon Apr 29 14:08:41 2019
+
+multi_srs_gen completed
+# Mon Apr 29 14:08:42 2019
+
+Return Code: 0
+Run Time:00h:00m:01s
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/synwork/sgmii_channel_smi_mult.srs to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srs
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srf
+Complete: Compile Process on sgmii_channel_smi|syn_results
+
+Running: premap (Pre-mapping) on sgmii_channel_smi|syn_results
+# Mon Apr 29 14:08:42 2019
+
+premap completed with warnings
+# Mon Apr 29 14:08:43 2019
+
+Return Code: 1
+Run Time:00h:00m:01s
+Complete: Compile on sgmii_channel_smi|syn_results
+
+Running: map (Map) on sgmii_channel_smi|syn_results
+# Mon Apr 29 14:08:43 2019
+License granted for 4 parallel jobs
+
+Running: fpga_mapper (Map & Optimize) on sgmii_channel_smi|syn_results
+# Mon Apr 29 14:08:43 2019
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/synwork/sgmii_channel_smi_m.srm to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srm
+
+fpga_mapper completed with warnings
+# Mon Apr 29 14:08:46 2019
+
+Return Code: 1
+Run Time:00h:00m:03s
+Complete: Map on sgmii_channel_smi|syn_results
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srf
+Complete: Logic Synthesis on sgmii_channel_smi|syn_results
+exit status=0
+exit status=0

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/stdout.log.bak.3 b/gbe/cores/sgmii/sgmii_channel_smi/stdout.log.bak.3
new file mode 100644 (file)
index 0000000..1ac7cca
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/stdout.log.bak.3
@@ -0,0 +1,75 @@
+Running in Lattice mode
+
+Starting:    /home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/mbin/synbatch
+Install:     /home/soft/lattice/diamond/3.10_x64/synpbase
+Hostname:    lxhadeb07
+Date:        Mon Apr 29 14:08:39 2019
+Version:     M-2017.03L-SP1-1
+
+Arguments:   -product synplify_pro -batch syn_results/sgmii_channel_smi.prj
+ProductType: synplify_pro
+
+
+
+
+log file: "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srr"
+Running: syn_results in foreground
+
+Running sgmii_channel_smi|syn_results
+
+Running: compile (Compile) on sgmii_channel_smi|syn_results
+# Mon Apr 29 14:08:39 2019
+
+Running: compile_flow (Compile Process) on sgmii_channel_smi|syn_results
+# Mon Apr 29 14:08:39 2019
+
+Running: compiler (Compile Input) on sgmii_channel_smi|syn_results
+# Mon Apr 29 14:08:39 2019
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/synwork/sgmii_channel_smi_comp.srs to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srs
+
+compiler completed
+# Mon Apr 29 14:08:41 2019
+
+Return Code: 0
+Run Time:00h:00m:02s
+
+Running: multi_srs_gen (Multi-srs Generator) on sgmii_channel_smi|syn_results
+# Mon Apr 29 14:08:41 2019
+
+multi_srs_gen completed
+# Mon Apr 29 14:08:42 2019
+
+Return Code: 0
+Run Time:00h:00m:01s
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/synwork/sgmii_channel_smi_mult.srs to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srs
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srf
+Complete: Compile Process on sgmii_channel_smi|syn_results
+
+Running: premap (Pre-mapping) on sgmii_channel_smi|syn_results
+# Mon Apr 29 14:08:42 2019
+
+premap completed with warnings
+# Mon Apr 29 14:08:43 2019
+
+Return Code: 1
+Run Time:00h:00m:01s
+Complete: Compile on sgmii_channel_smi|syn_results
+
+Running: map (Map) on sgmii_channel_smi|syn_results
+# Mon Apr 29 14:08:43 2019
+License granted for 4 parallel jobs
+
+Running: fpga_mapper (Map & Optimize) on sgmii_channel_smi|syn_results
+# Mon Apr 29 14:08:43 2019
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/synwork/sgmii_channel_smi_m.srm to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srm
+
+fpga_mapper completed with warnings
+# Mon Apr 29 14:08:46 2019
+
+Return Code: 1
+Run Time:00h:00m:03s
+Complete: Map on sgmii_channel_smi|syn_results
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srf
+Complete: Logic Synthesis on sgmii_channel_smi|syn_results
+exit status=0
+exit status=0

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/stdout.log.bak.4 b/gbe/cores/sgmii/sgmii_channel_smi/stdout.log.bak.4
new file mode 100644 (file)
index 0000000..a285c50
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/stdout.log.bak.4
@@ -0,0 +1,75 @@
+Running in Lattice mode
+
+Starting:    /home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/mbin/synbatch
+Install:     /home/soft/lattice/diamond/3.10_x64/synpbase
+Hostname:    lxhadeb07
+Date:        Mon Apr 29 13:36:21 2019
+Version:     M-2017.03L-SP1-1
+
+Arguments:   -product synplify_pro -batch syn_results/sgmii_channel_smi.prj
+ProductType: synplify_pro
+
+
+
+
+log file: "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srr"
+Running: syn_results in foreground
+
+Running sgmii_channel_smi|syn_results
+
+Running: compile (Compile) on sgmii_channel_smi|syn_results
+# Mon Apr 29 13:36:21 2019
+
+Running: compile_flow (Compile Process) on sgmii_channel_smi|syn_results
+# Mon Apr 29 13:36:21 2019
+
+Running: compiler (Compile Input) on sgmii_channel_smi|syn_results
+# Mon Apr 29 13:36:21 2019
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/synwork/sgmii_channel_smi_comp.srs to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srs
+
+compiler completed
+# Mon Apr 29 13:36:24 2019
+
+Return Code: 0
+Run Time:00h:00m:03s
+
+Running: multi_srs_gen (Multi-srs Generator) on sgmii_channel_smi|syn_results
+# Mon Apr 29 13:36:24 2019
+
+multi_srs_gen completed
+# Mon Apr 29 13:36:24 2019
+
+Return Code: 0
+Run Time:00h:00m:00s
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/synwork/sgmii_channel_smi_mult.srs to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srs
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srf
+Complete: Compile Process on sgmii_channel_smi|syn_results
+
+Running: premap (Pre-mapping) on sgmii_channel_smi|syn_results
+# Mon Apr 29 13:36:24 2019
+
+premap completed with warnings
+# Mon Apr 29 13:36:25 2019
+
+Return Code: 1
+Run Time:00h:00m:01s
+Complete: Compile on sgmii_channel_smi|syn_results
+
+Running: map (Map) on sgmii_channel_smi|syn_results
+# Mon Apr 29 13:36:25 2019
+License granted for 4 parallel jobs
+
+Running: fpga_mapper (Map & Optimize) on sgmii_channel_smi|syn_results
+# Mon Apr 29 13:36:25 2019
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/synwork/sgmii_channel_smi_m.srm to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srm
+
+fpga_mapper completed with warnings
+# Mon Apr 29 13:36:28 2019
+
+Return Code: 1
+Run Time:00h:00m:03s
+Complete: Map on sgmii_channel_smi|syn_results
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srf
+Complete: Logic Synthesis on sgmii_channel_smi|syn_results
+exit status=0
+exit status=0

diff --git a/gbe/cores/sgmii/sgmii_channel_smi/stdout.log.bak.5 b/gbe/cores/sgmii/sgmii_channel_smi/stdout.log.bak.5
new file mode 100644 (file)
index 0000000..a285c50
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_channel_smi/stdout.log.bak.5
@@ -0,0 +1,75 @@
+Running in Lattice mode
+
+Starting:    /home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/mbin/synbatch
+Install:     /home/soft/lattice/diamond/3.10_x64/synpbase
+Hostname:    lxhadeb07
+Date:        Mon Apr 29 13:36:21 2019
+Version:     M-2017.03L-SP1-1
+
+Arguments:   -product synplify_pro -batch syn_results/sgmii_channel_smi.prj
+ProductType: synplify_pro
+
+
+
+
+log file: "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srr"
+Running: syn_results in foreground
+
+Running sgmii_channel_smi|syn_results
+
+Running: compile (Compile) on sgmii_channel_smi|syn_results
+# Mon Apr 29 13:36:21 2019
+
+Running: compile_flow (Compile Process) on sgmii_channel_smi|syn_results
+# Mon Apr 29 13:36:21 2019
+
+Running: compiler (Compile Input) on sgmii_channel_smi|syn_results
+# Mon Apr 29 13:36:21 2019
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/synwork/sgmii_channel_smi_comp.srs to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srs
+
+compiler completed
+# Mon Apr 29 13:36:24 2019
+
+Return Code: 0
+Run Time:00h:00m:03s
+
+Running: multi_srs_gen (Multi-srs Generator) on sgmii_channel_smi|syn_results
+# Mon Apr 29 13:36:24 2019
+
+multi_srs_gen completed
+# Mon Apr 29 13:36:24 2019
+
+Return Code: 0
+Run Time:00h:00m:00s
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/synwork/sgmii_channel_smi_mult.srs to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srs
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srf
+Complete: Compile Process on sgmii_channel_smi|syn_results
+
+Running: premap (Pre-mapping) on sgmii_channel_smi|syn_results
+# Mon Apr 29 13:36:24 2019
+
+premap completed with warnings
+# Mon Apr 29 13:36:25 2019
+
+Return Code: 1
+Run Time:00h:00m:01s
+Complete: Compile on sgmii_channel_smi|syn_results
+
+Running: map (Map) on sgmii_channel_smi|syn_results
+# Mon Apr 29 13:36:25 2019
+License granted for 4 parallel jobs
+
+Running: fpga_mapper (Map & Optimize) on sgmii_channel_smi|syn_results
+# Mon Apr 29 13:36:25 2019
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/synwork/sgmii_channel_smi_m.srm to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srm
+
+fpga_mapper completed with warnings
+# Mon Apr 29 13:36:28 2019
+
+Return Code: 1
+Run Time:00h:00m:03s
+Complete: Map on sgmii_channel_smi|syn_results
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_channel_smi/syn_results/sgmii_channel_smi.srf
+Complete: Logic Synthesis on sgmii_channel_smi|syn_results
+exit status=0
+exit status=0

diff --git a/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5.cmd b/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5.cmd
new file mode 100644 (file)
index 0000000..438b319
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5.cmd
@@ -0,0 +1,18 @@
+PROJECT: sgmii_ecp5
+               working_path: "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results"
+               module: sgmii_ecp5
+               verilog_file_list: "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd" "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v"
+               vlog_std_v2001: true
+               constraint_file_name: "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.fdc"
+               suffix_name: edn
+               output_file_name: sgmii_ecp5
+               write_prf: true
+               disable_io_insertion: true
+               force_gsr: false
+               frequency: 100
+               fanout_limit: 50
+               retiming: false
+               pipe: false
+               part: LFE5UM-85F
+               speed_grade: 8
+               

diff --git a/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5.cst b/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5.cst
new file mode 100644 (file)
index 0000000..571fc3a
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5.cst
@@ -0,0 +1,3 @@
+Date=05/10/2019
+Time=09:02:05
+

diff --git a/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5.fdc b/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5.fdc
new file mode 100644 (file)
index 0000000..5424a21
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5.fdc
@@ -0,0 +1,3 @@
+###==== Start Generation
+
+define_attribute  {i:Lane0} {loc} {DCU1_CH1}

diff --git a/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5.lpc b/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5.lpc
new file mode 100644 (file)
index 0000000..24a8719
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5.lpc
@@ -0,0 +1,97 @@
+[Device]
+Family=ecp5um
+OperatingCondition=COM
+Package=CABGA756
+PartName=LFE5UM-85F-8BG756C
+PartType=LFE5UM-85F
+SpeedGrade=8
+Status=P
+[IP]
+CoreName=PCS
+CoreRevision=8.2
+CoreStatus=Demo
+CoreType=LPM
+Date=05/10/2019
+ModuleName=sgmii_ecp5
+ParameterFileVersion=1.0
+SourceFormat=vhdl
+Time=09:02:05
+VendorName=Lattice Semiconductor Corporation
+[Parameters]
+;ACHARA=0 00H
+;ACHARB=0 00H
+;ACHARM=0 00H
+;RXMCAENABLE=Disabled
+CDRLOLACTION=Full Recalibration
+CDRLOLRANGE=0
+CDR_MAX_RATE=1.25
+CDR_MULT=10X
+CDR_REF_RATE=125.0000
+CH_MODE=Rx and Tx
+Destination=Synplicity
+EDIF=1
+Expression=BusA(0 to 7)
+IO=0
+IO_TYPE=GbE
+LEQ=0
+LOOPBACK=Disabled
+LOSPORT=Enabled
+NUM_CHS=1
+Order=Big Endian [MSB:LSB]
+PPORT_RX_RDY=Enabled
+PPORT_TX_RDY=Enabled
+PROTOCOL=GbE
+PWAIT_RX_RDY=3000
+PWAIT_TX_RDY=3000
+RCSRC=Disabled
+REFCLK_RATE=125.0000
+RSTSEQSEL=Enabled
+RX8B10B=Enabled
+RXCOMMAA=1010000011
+RXCOMMAB=0101111100
+RXCOMMAM=1111111111
+RXCOUPLING=AC
+RXCTC=Enabled
+RXCTCBYTEN=0 00H
+RXCTCBYTEN1=0 00H
+RXCTCBYTEN2=1 BCH
+RXCTCBYTEN3=0 50H
+RXCTCMATCHPATTERN=M2-S2
+RXDIFFTERM=50 ohms
+RXFIFO_ENABLE=Enabled
+RXINVPOL=Non-invert
+RXLDR=Off
+RXLOSTHRESHOLD=2
+RXLSM=Enabled
+RXSC=K28P5
+RXWA=Barrel Shift
+RX_DATA_WIDTH=8/10-Bit
+RX_FICLK_RATE=125.0000
+RX_LINE_RATE=1.2500
+RX_RATE_DIV=Full Rate
+SCIPORT=Enabled
+SOFTLOL=Enabled
+TX8B10B=Enabled
+TXAMPLITUDE=1100
+TXDEPOST=Disabled
+TXDEPRE=Disabled
+TXDIFFTERM=50 ohms
+TXFIFO_ENABLE=Enabled
+TXINVPOL=Non-invert
+TXLDR=Off
+TXPLLLOLTHRESHOLD=0
+TXPLLMULT=10X
+TX_DATA_WIDTH=8/10-Bit
+TX_FICLK_RATE=125.0000
+TX_LINE_RATE=1.2500
+TX_MAX_RATE=1.25
+TX_RATE_DIV=Full Rate
+VHDL=1
+Verilog=0
+[FilesGenerated]
+sgmii_ecp5.pp=pp
+sgmii_ecp5.sym=sym
+sgmii_ecp5.tft=tft
+sgmii_ecp5.txt=pcs_module
+[SYSTEMPNR]
+LN0=DCU1_CH1

diff --git a/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5.ngd b/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5.ngd
new file mode 100644 (file)
index 0000000..fd4d8d5
Binary files /dev/null and b/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5.ngd differ

diff --git a/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5.ngo b/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5.ngo
new file mode 100644 (file)
index 0000000..f9dbbf3
Binary files /dev/null and b/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5.ngo differ

diff --git a/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5.vhd b/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5.vhd
new file mode 100644 (file)
index 0000000..5cb3267
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5.vhd
@@ -0,0 +1,433 @@
+
+--
+-- Verific VHDL Description of module DCUA
+--
+
+-- DCUA is a black-box. Cannot print a valid VHDL entity description for it
+
+--
+-- Verific VHDL Description of module sgmii_ecp5rsl_core
+--
+
+-- sgmii_ecp5rsl_core is a black-box. Cannot print a valid VHDL entity description for it
+
+--
+-- Verific VHDL Description of module sgmii_ecp5sll_core
+--
+
+-- sgmii_ecp5sll_core is a black-box. Cannot print a valid VHDL entity description for it
+
+--
+-- Verific VHDL Description of module sgmii_ecp5
+--
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+library ecp5um ;
+use ecp5um.components.all ;
+
+entity sgmii_ecp5 is
+    port (hdoutp: out std_logic;
+        hdoutn: out std_logic;
+        hdinp: in std_logic;
+        hdinn: in std_logic;
+        rxrefclk: in std_logic;
+        tx_pclk: out std_logic;
+        txi_clk: in std_logic;
+        txdata: in std_logic_vector(7 downto 0);
+        tx_k: in std_logic_vector(0 downto 0);
+        xmit: in std_logic_vector(0 downto 0);
+        tx_disp_correct: in std_logic_vector(0 downto 0);
+        rxdata: out std_logic_vector(7 downto 0);
+        rx_k: out std_logic_vector(0 downto 0);
+        rx_disp_err: out std_logic_vector(0 downto 0);
+        rx_cv_err: out std_logic_vector(0 downto 0);
+        signal_detect_c: in std_logic;
+        rx_los_low_s: out std_logic;
+        lsm_status_s: out std_logic;
+        ctc_urun_s: out std_logic;
+        ctc_orun_s: out std_logic;
+        rx_cdr_lol_s: out std_logic;
+        ctc_ins_s: out std_logic;
+        ctc_del_s: out std_logic;
+        sli_rst: in std_logic;
+        tx_pwrup_c: in std_logic;
+        rx_pwrup_c: in std_logic;
+        sci_wrdata: in std_logic_vector(7 downto 0);
+        sci_addr: in std_logic_vector(5 downto 0);
+        sci_rddata: out std_logic_vector(7 downto 0);
+        sci_en_dual: in std_logic;
+        sci_sel_dual: in std_logic;
+        sci_en: in std_logic;
+        sci_sel: in std_logic;
+        sci_rd: in std_logic;
+        sci_wrn: in std_logic;
+        sci_int: out std_logic;
+        cyawstn: in std_logic;
+        serdes_pdb: in std_logic;
+        pll_refclki: in std_logic;
+        rsl_disable: in std_logic;
+        rsl_rst: in std_logic;
+        serdes_rst_dual_c: in std_logic;
+        rst_dual_c: in std_logic;
+        tx_serdes_rst_c: in std_logic;
+        tx_pcs_rst_c: in std_logic;
+        pll_lol: out std_logic;
+        rsl_tx_rdy: out std_logic;
+        rx_serdes_rst_c: in std_logic;
+        rx_pcs_rst_c: in std_logic;
+        rsl_rx_rdy: out std_logic
+    );
+    
+end entity sgmii_ecp5;
+
+architecture v1 of sgmii_ecp5 is 
+    component sgmii_ecp5rsl_core is
+        generic (pnum_channels: integer := 1;
+            pprotocol: string := "GBE";
+            pserdes_mode: string := "RX AND TX";
+            pport_tx_rdy: string := "ENABLED";
+            pwait_tx_rdy: integer := 3000;
+            pport_rx_rdy: string := "ENABLED";
+            pwait_rx_rdy: integer := 3000);
+        port (rui_rst: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(132)
+            rui_serdes_rst_dual_c: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(133)
+            rui_rst_dual_c: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(134)
+            rui_rsl_disable: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(135)
+            rui_tx_ref_clk: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(137)
+            rui_tx_serdes_rst_c: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(138)
+            rui_tx_pcs_rst_c: in std_logic_vector(3 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(139)
+            rdi_pll_lol: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(140)
+            rui_rx_ref_clk: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(142)
+            rui_rx_serdes_rst_c: in std_logic_vector(3 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(143)
+            rui_rx_pcs_rst_c: in std_logic_vector(3 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(144)
+            rdi_rx_los_low_s: in std_logic_vector(3 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(145)
+            rdi_rx_cdr_lol_s: in std_logic_vector(3 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(146)
+            rdo_serdes_rst_dual_c: out std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(149)
+            rdo_rst_dual_c: out std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(150)
+            ruo_tx_rdy: out std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(152)
+            rdo_tx_serdes_rst_c: out std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(153)
+            rdo_tx_pcs_rst_c: out std_logic_vector(3 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(154)
+            ruo_rx_rdy: out std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(156)
+            rdo_rx_serdes_rst_c: out std_logic_vector(3 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(157)
+            rdo_rx_pcs_rst_c: out std_logic_vector(3 downto 0)   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(158)
+        );
+        
+    end component sgmii_ecp5rsl_core; -- syn_black_box=1    -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(88)
+    component sgmii_ecp5sll_core is
+        generic (PPROTOCOL: string := "GBE";
+            PLOL_SETTING: integer := 0;
+            PDYN_RATE_CTRL: string := "DISABLED";
+            PPCIE_MAX_RATE: string := "2.5";
+            PDIFF_VAL_LOCK: integer := 39;
+            PDIFF_VAL_UNLOCK: integer := 78;
+            PPCLK_TC: integer := 131072;
+            PDIFF_DIV11_VAL_LOCK: integer := 0;
+            PDIFF_DIV11_VAL_UNLOCK: integer := 0;
+            PPCLK_DIV11_TC: integer := 0);
+        port (sli_rst: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(125)
+            sli_refclk: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(126)
+            sli_pclk: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(127)
+            sli_div2_rate: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(128)
+            sli_div11_rate: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(129)
+            sli_gear_mode: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(130)
+            sli_cpri_mode: in std_logic_vector(2 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(131)
+            sli_pcie_mode: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(132)
+            slo_plol: out std_logic   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(135)
+        );
+        
+    end component sgmii_ecp5sll_core; -- syn_black_box=1    -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(107)
+    signal n45,n44,n1,n2,n3,n4,tx_pclk_c,n5,n6,n7,n8,n9,n10,n11,
+        n12,n13,rx_los_low_s_c,n14,n15,rx_cdr_lol_s_c,rsl_tx_pcs_rst_c,
+        rsl_rx_pcs_rst_c,rsl_rx_serdes_rst_c,rsl_rst_dual_c,rsl_serdes_rst_dual_c,
+        rsl_tx_serdes_rst_c,n16,n17,n18,n19,n20,n21,n22,n23,n24,n25,
+        n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37,n38,n39,
+        n40,n41,n42,n43,n46,n103,n102,n47,n48,n49,n50,n51,n52,n53,
+        n54,n55,n56,n57,n58,n59,n60,n61,n62,n63,n64,n65,n66,n67,
+        n68,n69,n70,n71,n72,n73,n74,n75,n76,n77,n78,n79,n80,n81,
+        n82,n83,n84,n85,n86,n87,n88,n89,n90,n91,n92,n93,n94,n95,
+        n96,n97,n98,n99,n100,n101,n112,n111,n110,pll_lol_c,n122,n121,
+        n113,n114,n115,n116,n117,n118,n119,n120,\_Z\,n124,n123,gnd,
+        pwr : std_logic; 
+    attribute LOC : string;
+    attribute LOC of DCU1_inst : label is "DCU1";
+    attribute CHAN : string;
+    attribute CHAN of DCU1_inst : label is "CH1";
+begin
+    tx_pclk <= tx_pclk_c;
+    rx_los_low_s <= rx_los_low_s_c;
+    rx_cdr_lol_s <= rx_cdr_lol_s_c;
+    pll_lol <= pll_lol_c;
+    DCU1_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1",
+        D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0",
+        D_CDR_LOL_SET=>"0b00",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1",
+        D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1",
+        D_SYNC_ND_EN=>"0b0",CH1_UC_MODE=>"0b0",CH1_PCIE_MODE=>"0b0",CH1_RIO_MODE=>"0b0",
+        CH1_WA_MODE=>"0b0",CH1_INVERT_RX=>"0b0",CH1_INVERT_TX=>"0b0",CH1_PRBS_SELECTION=>"0b0",
+        CH1_GE_AN_ENABLE=>"0b0",CH1_PRBS_LOCK=>"0b0",CH1_PRBS_ENABLE=>"0b0",
+        CH1_ENABLE_CG_ALIGN=>"0b1",CH1_TX_GEAR_MODE=>"0b0",CH1_RX_GEAR_MODE=>"0b0",
+        CH1_PCS_DET_TIME_SEL=>"0b00",CH1_PCIE_EI_EN=>"0b0",CH1_TX_GEAR_BYPASS=>"0b0",
+        CH1_ENC_BYPASS=>"0b0",CH1_SB_BYPASS=>"0b0",CH1_RX_SB_BYPASS=>"0b0",
+        CH1_WA_BYPASS=>"0b0",CH1_DEC_BYPASS=>"0b0",CH1_CTC_BYPASS=>"0b0",
+        CH1_RX_GEAR_BYPASS=>"0b0",CH1_LSM_DISABLE=>"0b0",CH1_MATCH_2_ENABLE=>"0b1",
+        CH1_MATCH_4_ENABLE=>"0b0",CH1_MIN_IPG_CNT=>"0b11",CH1_CC_MATCH_1=>"0x000",
+        CH1_CC_MATCH_2=>"0x000",CH1_CC_MATCH_3=>"0x1BC",CH1_CC_MATCH_4=>"0x050",
+        CH1_UDF_COMMA_MASK=>"0x3ff",CH1_UDF_COMMA_A=>"0x283",CH1_UDF_COMMA_B=>"0x17C",
+        CH1_RX_DCO_CK_DIV=>"0b010",CH1_RCV_DCC_EN=>"0b0",CH1_TPWDNB=>"0b1",
+        CH1_RATE_MODE_TX=>"0b0",CH1_RTERM_TX=>"0d19",CH1_TX_CM_SEL=>"0b00",
+        CH1_TDRV_PRE_EN=>"0b0",CH1_TDRV_SLICE0_SEL=>"0b01",CH1_TDRV_SLICE1_SEL=>"0b00",
+        CH1_TDRV_SLICE2_SEL=>"0b01",CH1_TDRV_SLICE3_SEL=>"0b01",CH1_TDRV_SLICE4_SEL=>"0b01",
+        CH1_TDRV_SLICE5_SEL=>"0b01",CH1_TDRV_SLICE0_CUR=>"0b101",CH1_TDRV_SLICE1_CUR=>"0b000",
+        CH1_TDRV_SLICE2_CUR=>"0b11",CH1_TDRV_SLICE3_CUR=>"0b11",CH1_TDRV_SLICE4_CUR=>"0b11",
+        CH1_TDRV_SLICE5_CUR=>"0b00",CH1_TDRV_DAT_SEL=>"0b00",CH1_TX_DIV11_SEL=>"0b0",
+        CH1_RPWDNB=>"0b1",CH1_RATE_MODE_RX=>"0b0",CH1_RX_DIV11_SEL=>"0b0",
+        CH1_SEL_SD_RX_CLK=>"0b0",CH1_FF_RX_H_CLK_EN=>"0b0",CH1_FF_RX_F_CLK_DIS=>"0b0",
+        CH1_FF_TX_H_CLK_EN=>"0b0",CH1_FF_TX_F_CLK_DIS=>"0b0",CH1_TDRV_POST_EN=>"0b0",
+        CH1_TX_POST_SIGN=>"0b0",CH1_TX_PRE_SIGN=>"0b0",CH1_REQ_LVL_SET=>"0b00",
+        CH1_REQ_EN=>"0b1",CH1_RTERM_RX=>"0d22",CH1_RXTERM_CM=>"0b11",CH1_PDEN_SEL=>"0b1",
+        CH1_RXIN_CM=>"0b11",CH1_LEQ_OFFSET_SEL=>"0b0",CH1_LEQ_OFFSET_TRIM=>"0b000",
+        CH1_RLOS_SEL=>"0b1",CH1_RX_LOS_LVL=>"0b010",CH1_RX_LOS_CEQ=>"0b11",
+        CH1_RX_LOS_HYST_EN=>"0b0",CH1_RX_LOS_EN=>"0b1",CH1_LDR_RX2CORE_SEL=>"0b0",
+        CH1_LDR_CORE2TX_SEL=>"0b0",D_TX_MAX_RATE=>"1.25",CH1_CDR_MAX_RATE=>"1.25",
+        CH1_TXAMPLITUDE=>"0d1100",CH1_TXDEPRE=>"DISABLED",CH1_TXDEPOST=>"DISABLED",
+        CH1_PROTOCOL=>"GBE",D_ISETLOS=>"0d0",D_SETIRPOLY_AUX=>"0b00",D_SETICONST_AUX=>"0b00",
+        D_SETIRPOLY_CH=>"0b00",D_SETICONST_CH=>"0b00",D_REQ_ISET=>"0b000",
+        D_PD_ISET=>"0b00",D_DCO_CALIB_TIME_SEL=>"0b00",CH1_CDR_CNT4SEL=>"0b00",
+        CH1_CDR_CNT8SEL=>"0b00",CH1_DCOATDCFG=>"0b00",CH1_DCOATDDLY=>"0b00",
+        CH1_DCOBYPSATD=>"0b1",CH1_DCOCALDIV=>"0b001",CH1_DCOCTLGI=>"0b010",
+        CH1_DCODISBDAVOID=>"0b0",CH1_DCOFLTDAC=>"0b01",CH1_DCOFTNRG=>"0b110",
+        CH1_DCOIOSTUNE=>"0b000",CH1_DCOITUNE=>"0b00",CH1_DCOITUNE4LSB=>"0b111",
+        CH1_DCOIUPDNX2=>"0b1",CH1_DCONUOFLSB=>"0b101",CH1_DCOSCALEI=>"0b00",
+        CH1_DCOSTARTVAL=>"0b000",CH1_DCOSTEP=>"0b00",CH1_BAND_THRESHOLD=>"0d0",
+        CH1_AUTO_FACQ_EN=>"0b1",CH1_AUTO_CALIB_EN=>"0b1",CH1_CALIB_CK_MODE=>"0b0",
+        CH1_REG_BAND_OFFSET=>"0d0",CH1_REG_BAND_SEL=>"0d0",CH1_REG_IDAC_SEL=>"0d0",
+        CH1_REG_IDAC_EN=>"0b0",D_CMUSETISCL4VCO=>"0b000",D_CMUSETI4VCO=>"0b00",
+        D_CMUSETINITVCT=>"0b00",D_CMUSETZGM=>"0b000",D_CMUSETP2AGM=>"0b000",
+        D_CMUSETP1GM=>"0b000",D_CMUSETI4CPZ=>"0d3",D_CMUSETI4CPP=>"0d3",D_CMUSETICP4Z=>"0b101",
+        D_CMUSETICP4P=>"0b01",D_CMUSETBIASI=>"0b00",D_SETPLLRC=>"0d1",CH1_RX_RATE_SEL=>"0d8",
+        D_REFCK_MODE=>"0b001",D_TX_VCO_CK_DIV=>"0b010",D_PLL_LOL_SET=>"0b00",
+        D_RG_EN=>"0b0",D_RG_SET=>"0b00")
+     port map (CH0_HDINP=>n103,CH1_HDINP=>hdinp,CH0_HDINN=>n103,CH1_HDINN=>hdinn,
+    D_TXBIT_CLKP_FROM_ND=>n44,D_TXBIT_CLKN_FROM_ND=>n44,D_SYNC_ND=>n44,D_TXPLL_LOL_FROM_ND=>n44,
+    CH0_RX_REFCLK=>n103,CH1_RX_REFCLK=>rxrefclk,CH0_FF_RXI_CLK=>n102,CH1_FF_RXI_CLK=>tx_pclk_c,
+    CH0_FF_TXI_CLK=>n102,CH1_FF_TXI_CLK=>txi_clk,CH0_FF_EBRD_CLK=>n102,CH1_FF_EBRD_CLK=>tx_pclk_c,
+    CH0_FF_TX_D_0=>n103,CH1_FF_TX_D_0=>txdata(0),CH0_FF_TX_D_1=>n103,CH1_FF_TX_D_1=>txdata(1),
+    CH0_FF_TX_D_2=>n103,CH1_FF_TX_D_2=>txdata(2),CH0_FF_TX_D_3=>n103,CH1_FF_TX_D_3=>txdata(3),
+    CH0_FF_TX_D_4=>n103,CH1_FF_TX_D_4=>txdata(4),CH0_FF_TX_D_5=>n103,CH1_FF_TX_D_5=>txdata(5),
+    CH0_FF_TX_D_6=>n103,CH1_FF_TX_D_6=>txdata(6),CH0_FF_TX_D_7=>n103,CH1_FF_TX_D_7=>txdata(7),
+    CH0_FF_TX_D_8=>n103,CH1_FF_TX_D_8=>tx_k(0),CH0_FF_TX_D_9=>n103,CH1_FF_TX_D_9=>n44,
+    CH0_FF_TX_D_10=>n103,CH1_FF_TX_D_10=>xmit(0),CH0_FF_TX_D_11=>n103,CH1_FF_TX_D_11=>tx_disp_correct(0),
+    CH0_FF_TX_D_12=>n103,CH1_FF_TX_D_12=>n103,CH0_FF_TX_D_13=>n103,CH1_FF_TX_D_13=>n103,
+    CH0_FF_TX_D_14=>n103,CH1_FF_TX_D_14=>n103,CH0_FF_TX_D_15=>n103,CH1_FF_TX_D_15=>n103,
+    CH0_FF_TX_D_16=>n103,CH1_FF_TX_D_16=>n103,CH0_FF_TX_D_17=>n103,CH1_FF_TX_D_17=>n103,
+    CH0_FF_TX_D_18=>n103,CH1_FF_TX_D_18=>n103,CH0_FF_TX_D_19=>n103,CH1_FF_TX_D_19=>n103,
+    CH0_FF_TX_D_20=>n103,CH1_FF_TX_D_20=>n103,CH0_FF_TX_D_21=>n103,CH1_FF_TX_D_21=>n44,
+    CH0_FF_TX_D_22=>n103,CH1_FF_TX_D_22=>n103,CH0_FF_TX_D_23=>n103,CH1_FF_TX_D_23=>n103,
+    CH0_FFC_EI_EN=>n103,CH1_FFC_EI_EN=>n44,CH0_FFC_PCIE_DET_EN=>n103,CH1_FFC_PCIE_DET_EN=>n44,
+    CH0_FFC_PCIE_CT=>n103,CH1_FFC_PCIE_CT=>n44,CH0_FFC_SB_INV_RX=>n103,CH1_FFC_SB_INV_RX=>n103,
+    CH0_FFC_ENABLE_CGALIGN=>n103,CH1_FFC_ENABLE_CGALIGN=>n103,CH0_FFC_SIGNAL_DETECT=>n103,
+    CH1_FFC_SIGNAL_DETECT=>signal_detect_c,CH0_FFC_FB_LOOPBACK=>n103,CH1_FFC_FB_LOOPBACK=>n44,
+    CH0_FFC_SB_PFIFO_LP=>n103,CH1_FFC_SB_PFIFO_LP=>n44,CH0_FFC_PFIFO_CLR=>n103,
+    CH1_FFC_PFIFO_CLR=>n44,CH0_FFC_RATE_MODE_RX=>n103,CH1_FFC_RATE_MODE_RX=>n44,
+    CH0_FFC_RATE_MODE_TX=>n103,CH1_FFC_RATE_MODE_TX=>n44,CH0_FFC_DIV11_MODE_RX=>n103,
+    CH1_FFC_DIV11_MODE_RX=>n44,CH0_FFC_DIV11_MODE_TX=>n103,CH1_FFC_DIV11_MODE_TX=>n44,
+    CH0_FFC_RX_GEAR_MODE=>n103,CH1_FFC_RX_GEAR_MODE=>n44,CH0_FFC_TX_GEAR_MODE=>n103,
+    CH1_FFC_TX_GEAR_MODE=>n44,CH0_FFC_LDR_CORE2TX_EN=>n103,CH1_FFC_LDR_CORE2TX_EN=>n103,
+    CH0_FFC_LANE_TX_RST=>n103,CH1_FFC_LANE_TX_RST=>rsl_tx_pcs_rst_c,CH0_FFC_LANE_RX_RST=>n103,
+    CH1_FFC_LANE_RX_RST=>rsl_rx_pcs_rst_c,CH0_FFC_RRST=>n103,CH1_FFC_RRST=>rsl_rx_serdes_rst_c,
+    CH0_FFC_TXPWDNB=>n103,CH1_FFC_TXPWDNB=>tx_pwrup_c,CH0_FFC_RXPWDNB=>n103,
+    CH1_FFC_RXPWDNB=>rx_pwrup_c,CH0_LDR_CORE2TX=>n103,CH1_LDR_CORE2TX=>n103,
+    D_SCIWDATA0=>sci_wrdata(0),D_SCIWDATA1=>sci_wrdata(1),D_SCIWDATA2=>sci_wrdata(2),
+    D_SCIWDATA3=>sci_wrdata(3),D_SCIWDATA4=>sci_wrdata(4),D_SCIWDATA5=>sci_wrdata(5),
+    D_SCIWDATA6=>sci_wrdata(6),D_SCIWDATA7=>sci_wrdata(7),D_SCIADDR0=>sci_addr(0),
+    D_SCIADDR1=>sci_addr(1),D_SCIADDR2=>sci_addr(2),D_SCIADDR3=>sci_addr(3),
+    D_SCIADDR4=>sci_addr(4),D_SCIADDR5=>sci_addr(5),D_SCIENAUX=>sci_en_dual,
+    D_SCISELAUX=>sci_sel_dual,CH0_SCIEN=>n103,CH1_SCIEN=>sci_en,CH0_SCISEL=>n103,
+    CH1_SCISEL=>sci_sel,D_SCIRD=>sci_rd,D_SCIWSTN=>sci_wrn,D_CYAWSTN=>cyawstn,
+    D_FFC_SYNC_TOGGLE=>n103,D_FFC_DUAL_RST=>rsl_rst_dual_c,D_FFC_MACRO_RST=>rsl_serdes_rst_dual_c,
+    D_FFC_MACROPDB=>serdes_pdb,D_FFC_TRST=>rsl_tx_serdes_rst_c,CH0_FFC_CDR_EN_BITSLIP=>n103,
+    CH1_FFC_CDR_EN_BITSLIP=>n44,D_SCAN_ENABLE=>n44,D_SCAN_IN_0=>n44,D_SCAN_IN_1=>n44,
+    D_SCAN_IN_2=>n44,D_SCAN_IN_3=>n44,D_SCAN_IN_4=>n44,D_SCAN_IN_5=>n44,
+    D_SCAN_IN_6=>n44,D_SCAN_IN_7=>n44,D_SCAN_MODE=>n44,D_SCAN_RESET=>n44,
+    D_CIN0=>n44,D_CIN1=>n44,D_CIN2=>n44,D_CIN3=>n44,D_CIN4=>n44,D_CIN5=>n44,
+    D_CIN6=>n44,D_CIN7=>n44,D_CIN8=>n44,D_CIN9=>n44,D_CIN10=>n44,D_CIN11=>n44,
+    CH0_HDOUTP=>n47,CH1_HDOUTP=>hdoutp,CH0_HDOUTN=>n48,CH1_HDOUTN=>hdoutn,
+    D_TXBIT_CLKP_TO_ND=>n1,D_TXBIT_CLKN_TO_ND=>n2,D_SYNC_PULSE2ND=>n3,D_TXPLL_LOL_TO_ND=>n4,
+    CH0_FF_RX_F_CLK=>n49,CH1_FF_RX_F_CLK=>n5,CH0_FF_RX_H_CLK=>n50,CH1_FF_RX_H_CLK=>n6,
+    CH0_FF_TX_F_CLK=>n51,CH1_FF_TX_F_CLK=>n7,CH0_FF_TX_H_CLK=>n52,CH1_FF_TX_H_CLK=>n8,
+    CH0_FF_RX_PCLK=>n53,CH1_FF_RX_PCLK=>n9,CH0_FF_TX_PCLK=>n54,CH1_FF_TX_PCLK=>tx_pclk_c,
+    CH0_FF_RX_D_0=>n55,CH1_FF_RX_D_0=>rxdata(0),CH0_FF_RX_D_1=>n56,CH1_FF_RX_D_1=>rxdata(1),
+    CH0_FF_RX_D_2=>n57,CH1_FF_RX_D_2=>rxdata(2),CH0_FF_RX_D_3=>n58,CH1_FF_RX_D_3=>rxdata(3),
+    CH0_FF_RX_D_4=>n59,CH1_FF_RX_D_4=>rxdata(4),CH0_FF_RX_D_5=>n60,CH1_FF_RX_D_5=>rxdata(5),
+    CH0_FF_RX_D_6=>n61,CH1_FF_RX_D_6=>rxdata(6),CH0_FF_RX_D_7=>n62,CH1_FF_RX_D_7=>rxdata(7),
+    CH0_FF_RX_D_8=>n63,CH1_FF_RX_D_8=>rx_k(0),CH0_FF_RX_D_9=>n64,CH1_FF_RX_D_9=>rx_disp_err(0),
+    CH0_FF_RX_D_10=>n65,CH1_FF_RX_D_10=>rx_cv_err(0),CH0_FF_RX_D_11=>n66,
+    CH1_FF_RX_D_11=>n10,CH0_FF_RX_D_12=>n67,CH1_FF_RX_D_12=>n68,CH0_FF_RX_D_13=>n69,
+    CH1_FF_RX_D_13=>n70,CH0_FF_RX_D_14=>n71,CH1_FF_RX_D_14=>n72,CH0_FF_RX_D_15=>n73,
+    CH1_FF_RX_D_15=>n74,CH0_FF_RX_D_16=>n75,CH1_FF_RX_D_16=>n76,CH0_FF_RX_D_17=>n77,
+    CH1_FF_RX_D_17=>n78,CH0_FF_RX_D_18=>n79,CH1_FF_RX_D_18=>n80,CH0_FF_RX_D_19=>n81,
+    CH1_FF_RX_D_19=>n82,CH0_FF_RX_D_20=>n83,CH1_FF_RX_D_20=>n84,CH0_FF_RX_D_21=>n85,
+    CH1_FF_RX_D_21=>n86,CH0_FF_RX_D_22=>n87,CH1_FF_RX_D_22=>n88,CH0_FF_RX_D_23=>n89,
+    CH1_FF_RX_D_23=>n11,CH0_FFS_PCIE_DONE=>n90,CH1_FFS_PCIE_DONE=>n12,CH0_FFS_PCIE_CON=>n91,
+    CH1_FFS_PCIE_CON=>n13,CH0_FFS_RLOS=>n92,CH1_FFS_RLOS=>rx_los_low_s_c,
+    CH0_FFS_LS_SYNC_STATUS=>n93,CH1_FFS_LS_SYNC_STATUS=>lsm_status_s,CH0_FFS_CC_UNDERRUN=>n94,
+    CH1_FFS_CC_UNDERRUN=>ctc_urun_s,CH0_FFS_CC_OVERRUN=>n95,CH1_FFS_CC_OVERRUN=>ctc_orun_s,
+    CH0_FFS_RXFBFIFO_ERROR=>n96,CH1_FFS_RXFBFIFO_ERROR=>n14,CH0_FFS_TXFBFIFO_ERROR=>n97,
+    CH1_FFS_TXFBFIFO_ERROR=>n15,CH0_FFS_RLOL=>n98,CH1_FFS_RLOL=>rx_cdr_lol_s_c,
+    CH0_FFS_SKP_ADDED=>n99,CH1_FFS_SKP_ADDED=>ctc_ins_s,CH0_FFS_SKP_DELETED=>n100,
+    CH1_FFS_SKP_DELETED=>ctc_del_s,CH0_LDR_RX2CORE=>n101,CH1_LDR_RX2CORE=>n112,
+    D_SCIRDATA0=>sci_rddata(0),D_SCIRDATA1=>sci_rddata(1),D_SCIRDATA2=>sci_rddata(2),
+    D_SCIRDATA3=>sci_rddata(3),D_SCIRDATA4=>sci_rddata(4),D_SCIRDATA5=>sci_rddata(5),
+    D_SCIRDATA6=>sci_rddata(6),D_SCIRDATA7=>sci_rddata(7),D_SCIINT=>sci_int,
+    D_SCAN_OUT_0=>n16,D_SCAN_OUT_1=>n17,D_SCAN_OUT_2=>n18,D_SCAN_OUT_3=>n19,
+    D_SCAN_OUT_4=>n20,D_SCAN_OUT_5=>n21,D_SCAN_OUT_6=>n22,D_SCAN_OUT_7=>n23,
+    D_COUT0=>n24,D_COUT1=>n25,D_COUT2=>n26,D_COUT3=>n27,D_COUT4=>n28,D_COUT5=>n29,
+    D_COUT6=>n30,D_COUT7=>n31,D_COUT8=>n32,D_COUT9=>n33,D_COUT10=>n34,D_COUT11=>n35,
+    D_COUT12=>n36,D_COUT13=>n37,D_COUT14=>n38,D_COUT15=>n39,D_COUT16=>n40,
+    D_COUT17=>n41,D_COUT18=>n42,D_COUT19=>n43,D_REFCLKI=>pll_refclki,D_FFS_PLOL=>n46);
+    n45 <= '1' ;
+    n44 <= '0' ;
+    n1 <= 'Z' ;
+    n2 <= 'Z' ;
+    n3 <= 'Z' ;
+    n4 <= 'Z' ;
+    n5 <= 'Z' ;
+    n6 <= 'Z' ;
+    n7 <= 'Z' ;
+    n8 <= 'Z' ;
+    n9 <= 'Z' ;
+    n10 <= 'Z' ;
+    n11 <= 'Z' ;
+    n12 <= 'Z' ;
+    n13 <= 'Z' ;
+    n14 <= 'Z' ;
+    n15 <= 'Z' ;
+    n16 <= 'Z' ;
+    n17 <= 'Z' ;
+    n18 <= 'Z' ;
+    n19 <= 'Z' ;
+    n20 <= 'Z' ;
+    n21 <= 'Z' ;
+    n22 <= 'Z' ;
+    n23 <= 'Z' ;
+    n24 <= 'Z' ;
+    n25 <= 'Z' ;
+    n26 <= 'Z' ;
+    n27 <= 'Z' ;
+    n28 <= 'Z' ;
+    n29 <= 'Z' ;
+    n30 <= 'Z' ;
+    n31 <= 'Z' ;
+    n32 <= 'Z' ;
+    n33 <= 'Z' ;
+    n34 <= 'Z' ;
+    n35 <= 'Z' ;
+    n36 <= 'Z' ;
+    n37 <= 'Z' ;
+    n38 <= 'Z' ;
+    n39 <= 'Z' ;
+    n40 <= 'Z' ;
+    n41 <= 'Z' ;
+    n42 <= 'Z' ;
+    n43 <= 'Z' ;
+    n46 <= 'Z' ;
+    n103 <= '0' ;
+    n102 <= '1' ;
+    n47 <= 'Z' ;
+    n48 <= 'Z' ;
+    n49 <= 'Z' ;
+    n50 <= 'Z' ;
+    n51 <= 'Z' ;
+    n52 <= 'Z' ;
+    n53 <= 'Z' ;
+    n54 <= 'Z' ;
+    n55 <= 'Z' ;
+    n56 <= 'Z' ;
+    n57 <= 'Z' ;
+    n58 <= 'Z' ;
+    n59 <= 'Z' ;
+    n60 <= 'Z' ;
+    n61 <= 'Z' ;
+    n62 <= 'Z' ;
+    n63 <= 'Z' ;
+    n64 <= 'Z' ;
+    n65 <= 'Z' ;
+    n66 <= 'Z' ;
+    n67 <= 'Z' ;
+    n68 <= 'Z' ;
+    n69 <= 'Z' ;
+    n70 <= 'Z' ;
+    n71 <= 'Z' ;
+    n72 <= 'Z' ;
+    n73 <= 'Z' ;
+    n74 <= 'Z' ;
+    n75 <= 'Z' ;
+    n76 <= 'Z' ;
+    n77 <= 'Z' ;
+    n78 <= 'Z' ;
+    n79 <= 'Z' ;
+    n80 <= 'Z' ;
+    n81 <= 'Z' ;
+    n82 <= 'Z' ;
+    n83 <= 'Z' ;
+    n84 <= 'Z' ;
+    n85 <= 'Z' ;
+    n86 <= 'Z' ;
+    n87 <= 'Z' ;
+    n88 <= 'Z' ;
+    n89 <= 'Z' ;
+    n90 <= 'Z' ;
+    n91 <= 'Z' ;
+    n92 <= 'Z' ;
+    n93 <= 'Z' ;
+    n94 <= 'Z' ;
+    n95 <= 'Z' ;
+    n96 <= 'Z' ;
+    n97 <= 'Z' ;
+    n98 <= 'Z' ;
+    n99 <= 'Z' ;
+    n100 <= 'Z' ;
+    n101 <= 'Z' ;
+    n112 <= 'Z' ;
+    rsl_inst: component sgmii_ecp5rsl_core port map (rui_rst=>rsl_rst,rui_serdes_rst_dual_c=>serdes_rst_dual_c,
+            rui_rst_dual_c=>rst_dual_c,rui_rsl_disable=>rsl_disable,rui_tx_ref_clk=>pll_refclki,
+            rui_tx_serdes_rst_c=>tx_serdes_rst_c,rui_tx_pcs_rst_c(3)=>n122,
+            rui_tx_pcs_rst_c(2)=>n122,rui_tx_pcs_rst_c(1)=>n122,rui_tx_pcs_rst_c(0)=>tx_pcs_rst_c,
+            rdi_pll_lol=>pll_lol_c,rui_rx_ref_clk=>rxrefclk,rui_rx_serdes_rst_c(3)=>n122,
+            rui_rx_serdes_rst_c(2)=>n122,rui_rx_serdes_rst_c(1)=>n122,rui_rx_serdes_rst_c(0)=>rx_serdes_rst_c,
+            rui_rx_pcs_rst_c(3)=>n122,rui_rx_pcs_rst_c(2)=>n122,rui_rx_pcs_rst_c(1)=>n122,
+            rui_rx_pcs_rst_c(0)=>rx_pcs_rst_c,rdi_rx_los_low_s(3)=>n122,rdi_rx_los_low_s(2)=>n122,
+            rdi_rx_los_low_s(1)=>n122,rdi_rx_los_low_s(0)=>rx_los_low_s_c,
+            rdi_rx_cdr_lol_s(3)=>n122,rdi_rx_cdr_lol_s(2)=>n122,rdi_rx_cdr_lol_s(1)=>n122,
+            rdi_rx_cdr_lol_s(0)=>rx_cdr_lol_s_c,rdo_serdes_rst_dual_c=>rsl_serdes_rst_dual_c,
+            rdo_rst_dual_c=>rsl_rst_dual_c,ruo_tx_rdy=>rsl_tx_rdy,rdo_tx_serdes_rst_c=>rsl_tx_serdes_rst_c,
+            rdo_tx_pcs_rst_c(3)=>n113,rdo_tx_pcs_rst_c(2)=>n114,rdo_tx_pcs_rst_c(1)=>n115,
+            rdo_tx_pcs_rst_c(0)=>rsl_tx_pcs_rst_c,ruo_rx_rdy=>rsl_rx_rdy,rdo_rx_serdes_rst_c(3)=>n116,
+            rdo_rx_serdes_rst_c(2)=>n117,rdo_rx_serdes_rst_c(1)=>n118,rdo_rx_serdes_rst_c(0)=>rsl_rx_serdes_rst_c,
+            rdo_rx_pcs_rst_c(3)=>n119,rdo_rx_pcs_rst_c(2)=>n120,rdo_rx_pcs_rst_c(1)=>\_Z\,
+            rdo_rx_pcs_rst_c(0)=>rsl_rx_pcs_rst_c);
+    n111 <= '1' ;
+    n110 <= '0' ;
+    n122 <= '0' ;
+    n121 <= '1' ;
+    n113 <= 'Z' ;
+    n114 <= 'Z' ;
+    n115 <= 'Z' ;
+    n116 <= 'Z' ;
+    n117 <= 'Z' ;
+    n118 <= 'Z' ;
+    n119 <= 'Z' ;
+    n120 <= 'Z' ;
+    \_Z\ <= 'Z' ;
+    sll_inst: component sgmii_ecp5sll_core port map (sli_rst=>sli_rst,sli_refclk=>pll_refclki,
+            sli_pclk=>tx_pclk_c,sli_div2_rate=>gnd,sli_div11_rate=>gnd,sli_gear_mode=>gnd,
+            sli_cpri_mode(2)=>gnd,sli_cpri_mode(1)=>gnd,sli_cpri_mode(0)=>gnd,
+            sli_pcie_mode=>gnd,slo_plol=>pll_lol_c);
+    n124 <= '1' ;
+    n123 <= '0' ;
+    gnd <= '0' ;
+    pwr <= '1' ;
+    
+end architecture v1;
+

diff --git a/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5_ngd.asd b/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5_ngd.asd
new file mode 100644 (file)
index 0000000..c265c78
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5_ngd.asd
@@ -0,0 +1 @@
+[ActiveSupport NGD]

diff --git a/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v b/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v
new file mode 100644 (file)
index 0000000..69a023d
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v
@@ -0,0 +1,2003 @@
+
+
+//   ===========================================================================
+//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
+//   ---------------------------------------------------------------------------
+//   Copyright (c) 2016 by Lattice Semiconductor Corporation
+//   ALL RIGHTS RESERVED
+//   ------------------------------------------------------------------
+//
+//   Permission:
+//
+//      Lattice SG Pte. Ltd. grants permission to use this code
+//      pursuant to the terms of the Lattice Reference Design License Agreement.
+//
+//
+//   Disclaimer:
+//
+//      This VHDL or Verilog source code is intended as a design reference
+//      which illustrates how these types of functions can be implemented.
+//      It is the user's responsibility to verify their design for
+//      consistency and functionality through the use of formal
+//      verification methods.  Lattice provides no warranty
+//      regarding the use or functionality of this code.
+//
+//   ---------------------------------------------------------------------------
+//
+//                  Lattice SG Pte. Ltd.
+//                  101 Thomson Road, United Square #07-02
+//                  Singapore 307591
+//
+//
+//                  TEL: 1-800-Lattice (USA and Canada)
+//                       +65-6631-2000 (Singapore)
+//                       +1-503-268-8001 (other locations)
+//
+//                  web: http://www.latticesemi.com/
+//                  email: techsupport@latticesemi.com
+//
+//   ---------------------------------------------------------------------------
+//
+// =============================================================================
+//                         FILE DETAILS
+// Project               : RSL- Reset Sequence Logic
+// File                  : rsl_core.v
+// Title                 : Top-level file for RSL
+// Dependencies          : 1.
+//                       : 2.
+// Description           :
+// =============================================================================
+//                        REVISION HISTORY
+// Version               : 1.0
+// Author(s)             : BM
+// Mod. Date             : October 28, 2013
+// Changes Made          : Initial Creation
+// -----------------------------------------------------------------------------
+// Version               : 1.1
+// Author(s)             : BM
+// Mod. Date             : November 06, 2013
+// Changes Made          : Tx/Rx separation, ready port code exclusion
+// -----------------------------------------------------------------------------
+// Version               : 1.2
+// Author(s)             : BM
+// Mod. Date             : June 13, 2014
+// Changes Made          : Updated Rx PCS reset method
+// -----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
+// Version               : 1.3
+// Author(s)             : UA
+// Mod. Date             : Dec 19, 2014
+// Changes Made          : Added new parameter fro PCIE
+// -----------------------------------------------------------------------------
+// Version               : 1.31
+// Author(s)             : BM/UM
+// Mod. Date             : Feb 23, 2016
+// Changes Made          : Behavior of rx_rdy output modified. The output rx_rdy
+//                         and the rx_rdy wait counter are reset to zero on
+//                         LOL or LOS. Reverted back the counter value change for PCIE.
+// -----------------------------------------------------------------------------
+// Version               : 1.4
+// Author(s)             : EB
+// Mod. Date:            : March 21, 2017
+// Changes Made          :
+// -----------------------------------------------------------------------------
+// Version               : 1.5
+// Author(s)             : ES
+// Mod. Date:            : May 8, 2017
+// Changes Made          : Implemented common RSL behaviour as proposed by BM.
+// =============================================================================
+
+`timescale 1ns/10ps
+
+module sgmii_ecp5rsl_core (
+      // ------------ Inputs
+      // Common
+      rui_rst,               // Active high reset for the RSL module
+      rui_serdes_rst_dual_c, // SERDES macro reset user command
+      rui_rst_dual_c,        // PCS dual reset user command
+      rui_rsl_disable,       // Active high signal that disables all reset outputs of RSL
+      // Tx
+      rui_tx_ref_clk,        // Tx reference clock
+      rui_tx_serdes_rst_c,   // Tx SERDES reset user command
+      rui_tx_pcs_rst_c,      // Tx lane reset user command
+      rdi_pll_lol,           // Tx PLL Loss of Lock status input from the SERDES
+      // Rx
+      rui_rx_ref_clk,        // Rx reference clock
+      rui_rx_serdes_rst_c,   // SERDES Receive channel reset user command
+      rui_rx_pcs_rst_c,      // Rx lane reset user command
+      rdi_rx_los_low_s,      // Receive loss of signal status input from SERDES
+      rdi_rx_cdr_lol_s,      // Receive CDR loss of lock status input from SERDES
+
+      // ------------ Outputs
+      // Common
+      rdo_serdes_rst_dual_c, // SERDES macro reset command output
+      rdo_rst_dual_c,        // PCS dual reset command output
+      // Tx
+      ruo_tx_rdy,            // Tx lane ready status output
+      rdo_tx_serdes_rst_c,   // SERDES Tx reset command output
+      rdo_tx_pcs_rst_c,      // PCS Tx lane reset command output
+      // Rx
+      ruo_rx_rdy,            // Rx lane ready status output
+      rdo_rx_serdes_rst_c,   // SERDES Rx channel reset command output
+      rdo_rx_pcs_rst_c       // PCS Rx lane reset command output
+      );
+
+// ------------ Module parameters
+`ifdef NUM_CHANNELS
+   parameter pnum_channels = `NUM_CHANNELS;    // 1,2,4
+`else
+   parameter pnum_channels = 1;
+`endif
+
+`ifdef PCIE
+   parameter pprotocol    = "PCIE";
+`else
+   parameter pprotocol    = "";
+`endif
+
+`ifdef RX_ONLY
+   parameter pserdes_mode    = "RX ONLY";
+`else
+   `ifdef TX_ONLY
+      parameter pserdes_mode = "TX ONLY";
+   `else
+      parameter pserdes_mode = "RX AND TX";
+   `endif
+`endif
+
+`ifdef PORT_TX_RDY
+   parameter pport_tx_rdy = "ENABLED";
+`else
+   parameter pport_tx_rdy = "DISABLED";
+`endif
+
+`ifdef WAIT_TX_RDY
+   parameter pwait_tx_rdy = `WAIT_TX_RDY;
+`else
+   parameter pwait_tx_rdy = 3000;
+`endif
+
+`ifdef PORT_RX_RDY
+   parameter pport_rx_rdy = "ENABLED";
+`else
+   parameter pport_rx_rdy = "DISABLED";
+`endif
+
+`ifdef WAIT_RX_RDY
+   parameter pwait_rx_rdy = `WAIT_RX_RDY;
+`else
+   parameter pwait_rx_rdy = 3000;
+`endif
+
+// ------------ Local parameters
+   localparam wa_num_cycles      = 1024;
+   localparam dac_num_cycles     = 3;
+   localparam lreset_pwidth      = 3;      // reset pulse width-1, default=4-1=3
+   localparam lwait_b4_trst      = 781250; // 5ms wait with worst-case Fmax=156 MHz
+   localparam lwait_b4_trst_s    = 781;    // for simulation
+   localparam lplol_cnt_width    = 20;     // width for lwait_b4_trst
+   localparam lwait_after_plol0  = 4;
+   localparam lwait_b4_rrst      = 180224; // total calibration time
+   localparam lrrst_wait_width   = 20;
+   localparam lwait_after_rrst   = 800000; // For CPRI- unused
+   localparam lwait_b4_rrst_s    = 460;    // wait cycles provided by design team
+   localparam lrlol_cnt_width    = 19;     // width for lwait_b4_rrst
+   localparam lwait_after_lols   = (16384 * dac_num_cycles) + wa_num_cycles;  // 16384 cycles * dac_num_cycles + 1024 cycles
+   localparam lwait_after_lols_s = 150;    // wait cycles provided by design team
+   localparam llols_cnt_width    = 18;     // lols count width
+   localparam lrdb_max           = 15;     // maximum debounce count
+   localparam ltxr_wait_width    = 12;     // width of tx ready wait counter
+   localparam lrxr_wait_width    = 12;     // width of tx ready wait counter
+
+// ------------ input ports
+   input                         rui_rst;
+   input                         rui_serdes_rst_dual_c;
+   input                         rui_rst_dual_c;
+   input                         rui_rsl_disable;
+
+   input                         rui_tx_ref_clk;
+   input                         rui_tx_serdes_rst_c;
+   input  [3:0]                  rui_tx_pcs_rst_c;
+   input                         rdi_pll_lol;
+
+   input                         rui_rx_ref_clk;
+   input  [3:0]                  rui_rx_serdes_rst_c;
+   input  [3:0]                  rui_rx_pcs_rst_c;
+   input  [3:0]                  rdi_rx_los_low_s;
+   input  [3:0]                  rdi_rx_cdr_lol_s;
+
+// ------------ output ports
+   output                        rdo_serdes_rst_dual_c;
+   output                        rdo_rst_dual_c;
+
+   output                        ruo_tx_rdy;
+   output                        rdo_tx_serdes_rst_c;
+   output [3:0]                  rdo_tx_pcs_rst_c;
+
+   output                        ruo_rx_rdy;
+   output [3:0]                  rdo_rx_serdes_rst_c;
+   output [3:0]                  rdo_rx_pcs_rst_c;
+
+// ------------ Internal registers and wires
+   // inputs
+   wire                          rui_rst;
+   wire                          rui_serdes_rst_dual_c;
+   wire                          rui_rst_dual_c;
+   wire                          rui_rsl_disable;
+   wire                          rui_tx_ref_clk;
+   wire                          rui_tx_serdes_rst_c;
+   wire   [3:0]                  rui_tx_pcs_rst_c;
+   wire                          rdi_pll_lol;
+   wire                          rui_rx_ref_clk;
+   wire   [3:0]                  rui_rx_serdes_rst_c;
+   wire   [3:0]                  rui_rx_pcs_rst_c;
+   wire   [3:0]                  rdi_rx_los_low_s;
+   wire   [3:0]                  rdi_rx_cdr_lol_s;
+
+   // outputs
+   wire                          rdo_serdes_rst_dual_c;
+   wire                          rdo_rst_dual_c;
+   wire                          ruo_tx_rdy;
+   wire                          rdo_tx_serdes_rst_c;
+   wire   [3:0]                  rdo_tx_pcs_rst_c;
+   wire                          ruo_rx_rdy;
+   wire   [3:0]                  rdo_rx_serdes_rst_c;
+   wire   [3:0]                  rdo_rx_pcs_rst_c;
+
+   // internal signals
+   // common
+   wire                          rsl_enable;
+   wire   [lplol_cnt_width-1:0]  wait_b4_trst;
+   wire   [lrlol_cnt_width-1:0]  wait_b4_rrst;
+   wire   [llols_cnt_width-1:0]  wait_after_lols;
+   reg                           pll_lol_p1;
+   reg                           pll_lol_p2;
+   reg                           pll_lol_p3;
+   // ------------ Tx
+   // rdo_tx_serdes_rst_c
+   reg    [lplol_cnt_width-1:0]  plol_cnt;
+   wire                          plol_cnt_tc;
+
+   reg    [2:0]                  txs_cnt;
+   reg                           txs_rst;
+   wire                          txs_cnt_tc;
+   // rdo_tx_pcs_rst_c
+   wire                          plol_fedge;
+   wire                          plol_redge;
+   reg                           waita_plol0;
+   reg    [2:0]                  plol0_cnt;
+   wire                          plol0_cnt_tc;
+   reg    [2:0]                  txp_cnt;
+   reg                           txp_rst;
+   wire                          txp_cnt_tc;
+   // ruo_tx_rdy
+   wire                          dual_or_serd_rst;
+   wire                          tx_any_pcs_rst;
+   wire                          tx_any_rst;
+   reg                           txsr_appd /* synthesis syn_keep=1 */;
+   reg                           txdpr_appd;
+   reg    [pnum_channels-1:0]    txpr_appd;
+   reg                           txr_wt_en;
+   reg    [ltxr_wait_width-1:0]  txr_wt_cnt;
+   wire                          txr_wt_tc;
+   reg                           ruo_tx_rdyr;
+
+   // ------------ Rx
+   wire                          comb_rlos;
+   wire                          comb_rlol;
+   //wire                          rlols;
+   wire                          rx_all_well;
+
+   //reg                           rlols_p1;
+   //reg                           rlols_p2;
+   //reg                           rlols_p3;
+
+   reg                           rlol_p1;
+   reg                           rlol_p2;
+   reg                           rlol_p3;
+   reg                           rlos_p1;
+   reg                           rlos_p2;
+   reg                           rlos_p3;
+
+   //reg    [3:0]                  rdb_cnt;
+   //wire                          rdb_cnt_max;
+   //wire                          rdb_cnt_zero;
+   //reg                           rlols_db;
+   //reg                           rlols_db_p1;
+
+   reg    [3:0]                  rlol_db_cnt;
+   wire                          rlol_db_cnt_max;
+   wire                          rlol_db_cnt_zero;
+   reg                           rlol_db;
+   reg                                  rlol_db_p1;
+
+   reg    [3:0]                  rlos_db_cnt;
+   wire                          rlos_db_cnt_max;
+   wire                          rlos_db_cnt_zero;
+   reg                           rlos_db;
+   reg                                  rlos_db_p1;
+
+   // rdo_rx_serdes_rst_c
+   reg    [lrlol_cnt_width-1:0]  rlol1_cnt;
+   wire                          rlol1_cnt_tc;
+   reg    [2:0]                  rxs_cnt;
+   reg                           rxs_rst;
+   wire                          rxs_cnt_tc;
+   reg    [lrrst_wait_width-1:0] rrst_cnt;
+   wire                          rrst_cnt_tc;
+   reg                           rrst_wait;
+   // rdo_rx_pcs_rst_c
+   //wire                          rlols_fedge;
+   //wire                          rlols_redge;
+   wire                          rlol_fedge;
+   wire                          rlol_redge;
+   wire                          rlos_fedge;
+   wire                          rlos_redge;
+
+   reg                           wait_calib;
+   reg                           waita_rlols0;
+   reg    [llols_cnt_width-1:0]  rlols0_cnt;
+   wire                          rlols0_cnt_tc;
+   reg    [2:0]                  rxp_cnt;
+   reg                           rxp_rst;
+   wire                          rxp_cnt_tc;
+
+   wire                          rx_any_serd_rst;
+   reg    [llols_cnt_width-1:0]  rlolsz_cnt;
+   wire                          rlolsz_cnt_tc;
+   reg [2:0]                    rxp_cnt2;
+   reg                           rxp_rst2;
+   wire                          rxp_cnt2_tc;
+   reg [15:0]                    data_loop_b_cnt;
+   reg                           data_loop_b;
+   wire                          data_loop_b_tc;
+
+   // ruo_rx_rdy
+   reg    [pnum_channels-1:0]    rxsr_appd;
+   reg    [pnum_channels-1:0]    rxpr_appd;
+   reg                           rxsdr_appd /* synthesis syn_keep=1 */;
+   reg                           rxdpr_appd;
+   wire                          rxsdr_or_sr_appd;
+   wire                          dual_or_rserd_rst;
+   wire                          rx_any_pcs_rst;
+   wire                          rx_any_rst;
+   reg                           rxr_wt_en;
+   reg    [lrxr_wait_width-1:0]  rxr_wt_cnt;
+   wire                          rxr_wt_tc;
+   reg                           ruo_rx_rdyr;
+
+// ==================================================================
+//                          Start of code
+// ==================================================================
+   assign rsl_enable = ~rui_rsl_disable;
+
+// ------------ rdo_serdes_rst_dual_c
+   assign rdo_serdes_rst_dual_c = (rui_rst&rsl_enable) | rui_serdes_rst_dual_c;
+
+// ------------ rdo_rst_dual_c
+   assign rdo_rst_dual_c = rui_rst_dual_c;
+
+// ------------ Setting counter values for RSL_SIM_MODE
+   `ifdef RSL_SIM_MODE
+      assign wait_b4_trst    = lwait_b4_trst_s;
+      assign wait_b4_rrst    = lwait_b4_rrst_s;
+      assign wait_after_lols = lwait_after_lols_s;
+   `else
+      assign wait_b4_trst    = lwait_b4_trst;
+      assign wait_b4_rrst    = lwait_b4_rrst;
+      assign wait_after_lols = lwait_after_lols;
+   `endif
+
+// ==================================================================
+//                                 Tx
+// ==================================================================
+   generate
+   if((pserdes_mode=="RX AND TX")||(pserdes_mode=="TX ONLY")) begin
+
+// ------------ Synchronizing pll_lol to the tx clock
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) begin
+         pll_lol_p1 <= 1'd0;
+         pll_lol_p2 <= 1'd0;
+         pll_lol_p3 <= 1'd0;
+      end
+      else begin
+         pll_lol_p1 <= rdi_pll_lol;
+         pll_lol_p2 <= pll_lol_p1;
+         pll_lol_p3 <= pll_lol_p2;
+      end
+   end
+
+// ------------ rdo_tx_serdes_rst_c
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         plol_cnt    <= 'd0;
+      else if((pll_lol_p2==0)||(plol_cnt_tc==1)||(rdo_tx_serdes_rst_c==1))
+         plol_cnt    <= 'd0;
+      else
+         plol_cnt    <= plol_cnt+1;
+   end
+   assign plol_cnt_tc = (plol_cnt==wait_b4_trst)?1'b1:1'b0;
+
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) begin
+         txs_cnt  <= 'd0;   // tx serdes reset pulse count
+         txs_rst  <= 1'b0;  // tx serdes reset
+      end
+      else if(plol_cnt_tc==1)
+         txs_rst  <= 1'b1;
+      else if(txs_cnt_tc==1) begin
+         txs_cnt  <= 'd0;
+         txs_rst  <= 1'b0;
+      end
+      else if(txs_rst==1)
+         txs_cnt  <= txs_cnt+1;
+   end
+   assign txs_cnt_tc = (txs_cnt==lreset_pwidth)?1'b1:1'b0;
+
+   assign rdo_tx_serdes_rst_c = (rsl_enable&txs_rst)| rui_tx_serdes_rst_c;
+
+// ------------ rdo_tx_pcs_rst_c
+   assign plol_fedge = ~pll_lol_p2 & pll_lol_p3;
+   assign plol_redge = pll_lol_p2 & ~pll_lol_p3;
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         waita_plol0  <= 1'd0;
+      else if(plol_fedge==1'b1)
+         waita_plol0  <= 1'b1;
+      else if((plol0_cnt_tc==1)||(plol_redge==1))
+         waita_plol0  <= 1'd0;
+   end
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         plol0_cnt    <= 'd0;
+      else if((pll_lol_p2==1)||(plol0_cnt_tc==1))
+         plol0_cnt    <= 'd0;
+      else if(waita_plol0==1'b1)
+         plol0_cnt    <= plol0_cnt+1;
+   end
+   assign plol0_cnt_tc = (plol0_cnt==lwait_after_plol0)?1'b1:1'b0;
+
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) begin
+         txp_cnt  <= 'd0;   // tx serdes reset pulse count
+         txp_rst  <= 1'b0;  // tx serdes reset
+      end
+      else if(plol0_cnt_tc==1)
+         txp_rst  <= 1'b1;
+      else if(txp_cnt_tc==1) begin
+         txp_cnt  <= 'd0;
+         txp_rst  <= 1'b0;
+      end
+      else if(txp_rst==1)
+         txp_cnt  <= txp_cnt+1;
+   end
+   assign txp_cnt_tc = (txp_cnt==lreset_pwidth)?1'b1:1'b0;
+
+   genvar i;
+   for(i=0;i<pnum_channels;i=i+1) begin : ifor
+      assign rdo_tx_pcs_rst_c[i] = (rsl_enable&txp_rst)| rui_tx_pcs_rst_c[i];
+   end
+   if(pnum_channels==1)
+      assign rdo_tx_pcs_rst_c[3:1] = 3'b000;
+   else if(pnum_channels==2)
+      assign rdo_tx_pcs_rst_c[3:2] = 2'b00;
+
+   // ------------ ruo_tx_rdy
+   if(pport_tx_rdy=="ENABLED") begin
+   assign dual_or_serd_rst = rdo_serdes_rst_dual_c|rdo_tx_serdes_rst_c;
+   assign tx_any_pcs_rst = rdo_rst_dual_c|(|rdo_tx_pcs_rst_c[pnum_channels-1:0]);
+   assign tx_any_rst = dual_or_serd_rst | tx_any_pcs_rst;
+
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         txsr_appd <= 1'b1; // tx serdes reset applied
+      else if(dual_or_serd_rst==1)
+         txsr_appd <= 1'b1;
+   end
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         txdpr_appd <= 1'b0; // tx dual (pcs) reset applied
+      else if(pll_lol_p2|rdo_serdes_rst_dual_c|rdo_tx_serdes_rst_c)
+         txdpr_appd <= 1'b0;
+      else if(rdo_rst_dual_c==1)
+         txdpr_appd <= 1'b1;
+   end
+
+   genvar m;
+   for(m=0;m<pnum_channels;m=m+1) begin :mfor
+      always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         txpr_appd[m] <= 1'b0; // tx pcs reset applied
+      else if(pll_lol_p2|rdo_serdes_rst_dual_c|rdo_tx_serdes_rst_c)
+         txpr_appd[m] <= 1'b0;
+      else if(txsr_appd&(rdo_tx_pcs_rst_c[m]|txdpr_appd))
+         txpr_appd[m] <= 1'b1;
+      end
+   end
+
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         txr_wt_en  <= 0;  // tx ready wait counter enable
+      else if((txr_wt_tc==1)||(dual_or_serd_rst==1))
+         txr_wt_en  <= 0;
+      else if((~ruo_tx_rdyr)&(~pll_lol_p2)&(&txpr_appd))
+         txr_wt_en  <= 1;
+   end
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         txr_wt_cnt  <= 'd0;  // tx ready wait count
+      else if((txr_wt_tc==1)||(tx_any_rst==1))
+         txr_wt_cnt  <= 'd0;
+      else if(txr_wt_en==1)
+         txr_wt_cnt  <= txr_wt_cnt+1;
+   end
+   assign txr_wt_tc = (txr_wt_cnt==pwait_tx_rdy)?1'b1:1'b0;
+
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         ruo_tx_rdyr <= 1'b0; // tx serdes reset applied
+      else if((tx_any_rst==1)||(pll_lol_p2==1))
+         ruo_tx_rdyr <= 1'b0;
+      else if(txr_wt_tc==1)
+         ruo_tx_rdyr <= 1'b1;
+   end
+   assign ruo_tx_rdy = ruo_tx_rdyr;
+   end         // if pport_tx_rdy
+   else
+      assign ruo_tx_rdy = 1'b0;
+   end         // generate if(Rx and Tx) or (Tx only)
+   else begin  // generate else (Rx only)
+      assign rdo_tx_serdes_rst_c = 1'b0;
+      assign rdo_tx_pcs_rst_c = 4'd0;
+      assign ruo_tx_rdy = 1'b0;
+   end
+   endgenerate
+
+// ==================================================================
+//                                 Rx
+// ==================================================================
+   generate
+   if((pserdes_mode=="RX AND TX")||(pserdes_mode=="RX ONLY")) begin
+   assign comb_rlos = |rdi_rx_los_low_s[pnum_channels-1:0];
+   assign comb_rlol = |rdi_rx_cdr_lol_s[pnum_channels-1:0];
+   //assign rlols     = comb_rlos|comb_rlol;
+
+   // ------------ Synchronizing rlols to the rx ref clock
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) begin
+        //rlols_p1    <= 1'd0;
+        //rlols_p2    <= 1'd0;
+        //rlols_p3    <= 1'd0;
+        //rlols_db_p1 <= 1'd1;
+
+        rlol_p1     <= 1'd0;
+        rlol_p2     <= 1'd0;
+        rlol_p3     <= 1'd0;
+        rlol_db_p1  <= 1'd1;
+
+        rlos_p1    <= 1'd0;
+        rlos_p2    <= 1'd0;
+        rlos_p3    <= 1'd0;
+        rlos_db_p1 <= 1'd1;
+      end
+      else begin
+        //rlols_p1    <= rlols;
+        //rlols_p2    <= rlols_p1;
+        //rlols_p3    <= rlols_p2;
+        //rlols_db_p1 <= rlols_db;
+
+        rlol_p1     <= comb_rlol;
+        rlol_p2     <= rlol_p1;
+        rlol_p3     <= rlol_p2;
+       rlol_db_p1  <= rlol_db;
+
+        rlos_p1    <= comb_rlos;
+        rlos_p2    <= rlos_p1;
+        rlos_p3    <= rlos_p2;
+        rlos_db_p1 <= rlos_db;
+      end
+   end
+   assign rx_all_well = ~rlol_db && ~rlos_db;
+
+//******************************************************************************
+// [ES:05.03.17] Unused registers for clean-up
+//------------------------------------------------------------------------------
+// ------------ Debouncing rlols
+//   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+//      if(rui_rst==1'b1) rdb_cnt  <= lrdb_max;
+//      else if(rlols_p2==1) begin
+//         if(!rdb_cnt_max) rdb_cnt <= rdb_cnt+1;
+//      end
+//      else if(!rdb_cnt_zero) rdb_cnt <= rdb_cnt-1;
+//   end
+//   assign rdb_cnt_max  = (rdb_cnt==lrdb_max);
+//   assign rdb_cnt_zero = (rdb_cnt==0);
+//   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+//      if(rui_rst==1'b1) rlols_db <= 1;
+//      else if(rdb_cnt_max)  rlols_db <= 1;
+//      else if(rdb_cnt_zero) rlols_db <= 0;
+//   end
+//******************************************************************************
+
+// ------------ Debouncing rlol
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) rlol_db_cnt  <= lrdb_max;
+      else if(rlol_p2==1) begin
+         if(!rlol_db_cnt_max) rlol_db_cnt <= rlol_db_cnt+1;
+      end
+      else if(!rlol_db_cnt_zero) rlol_db_cnt <= rlol_db_cnt-1;
+   end
+   assign rlol_db_cnt_max  = (rlol_db_cnt==lrdb_max);
+   assign rlol_db_cnt_zero = (rlol_db_cnt==0);
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) rlol_db <= 1;
+      else if(rlol_db_cnt_max)  rlol_db <= 1;
+      else if(rlol_db_cnt_zero) rlol_db <= 0;
+   end
+
+// ------------ Debouncing rlos
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) rlos_db_cnt  <= lrdb_max;
+      else if(rlos_p2==1) begin
+         if(!rlos_db_cnt_max) rlos_db_cnt <= rlos_db_cnt+1;
+      end
+      else if(!rlos_db_cnt_zero) rlos_db_cnt <= rlos_db_cnt-1;
+   end
+   assign rlos_db_cnt_max  = (rlos_db_cnt==lrdb_max);
+   assign rlos_db_cnt_zero = (rlos_db_cnt==0);
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) rlos_db <= 1;
+      else if(rlos_db_cnt_max)  rlos_db <= 1;
+      else if(rlos_db_cnt_zero) rlos_db <= 0;
+   end
+
+// ------------ Calib time trigger
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+     if (rui_rst==1'b1) begin
+       wait_calib <= 1'd1;
+     end
+     else begin
+       if (rlol1_cnt_tc) begin
+         if (rlol_db)
+           wait_calib <= 1'd1;
+         else
+           wait_calib <= 1'd0;
+       end
+       else if (rlos_redge)
+         wait_calib <= 1'd0;
+       else if (rlos_fedge) begin
+         wait_calib <= 1'd1;
+       end
+     end
+   end
+
+   //***************************************************************************
+   // Total calibration time counter
+   // - this covers the band calibration time (256 cycles * 64) and
+   //   DAC calibration time (16384 cycles * 10 bits)
+   //---------------------------------------------------------------------------
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+     if (rui_rst==1'b1) begin
+       rlol1_cnt  <= 'd0;  // Counting when Rx LOL is 1 and Rx LOS is 0
+     end
+     else begin
+       if(rxs_rst || rlol1_cnt_tc || rlos_redge)
+         rlol1_cnt  <= 'd0;
+       else if (wait_calib)
+         rlol1_cnt <= rlol1_cnt+1;
+     end
+   end
+   assign rlol1_cnt_tc = (rlol1_cnt==wait_b4_rrst);
+
+// ------------ rdo_rx_serdes_rst_c
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+     if (rui_rst==1'b1) begin
+       rxs_cnt  <= 'd0;   // rx serdes reset pulse count
+       rxs_rst  <= 1'b0;  // rx serdes reset
+     end
+     else begin
+       if (rlos_db)
+         rxs_rst <= 1'b0;
+       else if (rlol1_cnt_tc && rlol_db)
+         rxs_rst <= 1'b1;
+       else if (rxs_cnt_tc==1) begin
+         rxs_rst  <= 1'b0;
+       end
+
+       if (rxs_cnt_tc)
+         rxs_cnt <= 'd0;
+       else
+         if (rxs_rst==1)
+           rxs_cnt <= rxs_cnt+1;
+     end
+   end
+   assign rxs_cnt_tc  = (rxs_cnt==lreset_pwidth)?1'b1:1'b0;
+
+   //***************************************************************************
+   // [ES:05.03.17] Unused logic from CPRI rrst_wait
+   //---------------------------------------------------------------------------
+   // always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+   //    if(rui_rst==1'b1)
+   //       rrst_cnt    <= 'd0;
+   //    else if(rlol1_cnt_tc)
+   //       rrst_cnt    <= 'd0;
+   //    else if(rrst_wait)
+   //       rrst_cnt    <= rrst_cnt+1;
+   // end
+   // assign rrst_cnt_tc = (rrst_cnt==lwait_after_rrst) ? 1'b1 : 1'b0;
+   // always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+   //    if(rui_rst==1'b1)
+   //       rrst_wait    <= 0;
+   //    else if(pprotocol != "CPRI")
+   //       rrst_wait    <= 0;
+   //    else if(rlol1_cnt_tc)
+   //       rrst_wait    <= 1;
+   //    else if(rrst_cnt_tc==1)
+   //       rrst_wait    <= 0;
+   // end
+   //***************************************************************************
+
+   genvar j;
+   for(j=0;j<pnum_channels;j=j+1) begin :jfor
+      assign rdo_rx_serdes_rst_c[j] = (rsl_enable&rxs_rst)| rui_rx_serdes_rst_c[j];
+   end
+   if(pnum_channels==1)
+      assign rdo_rx_serdes_rst_c[3:1] = 3'b000;
+   else if(pnum_channels==2)
+      assign rdo_rx_serdes_rst_c[3:2] = 2'b00;
+
+// ------------ rdo_rx_pcs_rst_c
+   //assign rlols_fedge = ~rlols_db & rlols_db_p1;
+   //assign rlols_redge = rlols_db & ~rlols_db_p1;
+
+   assign rlol_fedge  = ~rlol_db & rlol_db_p1;
+   assign rlol_redge  = rlol_db & ~rlol_db_p1;
+   assign rlos_fedge  = ~rlos_db & rlos_db_p1;
+   assign rlos_redge  = rlos_db & ~rlos_db_p1;
+
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if (rui_rst==1'b1) begin
+        waita_rlols0 <= 1'd0;
+      end
+      else begin
+        if ((rlos_fedge && ~rlol_db) || (rlol_fedge && ~rlos_db))
+          waita_rlols0 <= 1'b1;
+        else if (rlos_redge || rlol_redge)
+          waita_rlols0 <= 1'd0;
+        else if (rlols0_cnt_tc==1)
+          waita_rlols0 <= 1'd0;
+      end
+   end
+
+   //***************************************************************************
+   // Post RLOL check before pcs_rst deassertion
+   // - allowance of 2-4 DAC calibration cycles + 1024 cycles for WA module
+   //   (word alignment).
+   //---------------------------------------------------------------------------
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+     if (rui_rst==1'b1) begin
+       rlols0_cnt <= 'd0;
+     end
+     else begin
+       if (rlol_redge || rlos_redge || rlols0_cnt_tc)
+         rlols0_cnt <= 'd0;
+       else if (waita_rlols0==1)
+         rlols0_cnt <= rlols0_cnt+1;
+     end
+   end
+   assign rlols0_cnt_tc   = (rlols0_cnt == wait_after_lols);
+   assign rx_any_serd_rst = rdo_serdes_rst_dual_c|(|rdo_rx_serdes_rst_c);
+
+   //***************************************************************************
+   // [ES:05.03.17] Unused registers for clean-up
+   //---------------------------------------------------------------------------
+   // always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+   //    if(rui_rst==1'b1)
+   //       rlolsz_cnt  <= 'd0;  // Counting when both Rx LOL is 0 and Rx LOS is 0
+   //    else if((rlol_db|rx_any_serd_rst)||(rlolsz_cnt_tc==1))
+   //       rlolsz_cnt  <= 'd0;
+   //    else if((rlolsz_cnt_tc==0)&&(rlol_db==0))
+   //       rlolsz_cnt  <= rlolsz_cnt+1;
+   // end
+   // assign rlolsz_cnt_tc = (rlolsz_cnt==wait_after_lols);
+   //***************************************************************************
+
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+     if (rui_rst==1'b1) begin
+       rxp_cnt2  <= 'd0;   // pcs serdes reset pulse count
+       rxp_rst2  <= 1'b1;  // rx pcs reset
+     end
+     else begin
+       if (rx_any_serd_rst || rlos_redge) begin
+         rxp_rst2 <= 1'b1;
+       end
+       else if (rlols0_cnt_tc) begin
+         rxp_rst2 <= 1'b0;
+       end
+       //***********************************************************************
+       // [ES:05.03.17] No need for pulse width
+       //-----------------------------------------------------------------------
+       // else if(rxp_cnt2_tc==1) begin
+       //   rxp_cnt2  <= 'd0;
+       //   rxp_rst2  <= 1'b0;
+       // end
+       //***********************************************************************
+       // [ES:05.03.17] No need for pulse width
+       //-----------------------------------------------------------------------
+       // else if (rxp_rst2==1)
+       //   rxp_cnt2 <= rxp_cnt2+1;
+       //***********************************************************************
+     end // else: !if(rui_rst==1'b1)
+   end // always @ (posedge rui_rx_ref_clk or posedge rui_rst)
+   //assign rxp_cnt2_tc = (rxp_cnt2==lreset_pwidth)?1'b1:1'b0;
+
+   //***************************************************************************
+   // [ES:05.03.17] No need for pulse width
+   //---------------------------------------------------------------------------
+   //else begin
+   //   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+   //      if(rui_rst==1'b1)
+   //         rxp_rst2  <= 1'b1;  // rx pcs reset
+   //      else if(rx_any_serd_rst)
+   //         rxp_rst2  <= 1'b1;
+   //      else if(rlolsz_cnt_tc==1)
+   //         rxp_rst2  <= 1'b0;
+   //   end
+   //end
+   //***************************************************************************
+
+   genvar k;
+   for(k=0;k<pnum_channels;k=k+1) begin: kfor
+      assign rdo_rx_pcs_rst_c[k] = (rsl_enable&rxp_rst2)| rui_rx_pcs_rst_c[k];
+   end
+   if(pnum_channels==1)
+      assign rdo_rx_pcs_rst_c[3:1] = 3'b000;
+   else if(pnum_channels==2)
+      assign rdo_rx_pcs_rst_c[3:2] = 2'b00;
+
+// ------------ ruo_rx_rdy
+   if(pport_rx_rdy=="ENABLED") begin
+   assign dual_or_rserd_rst = rdo_serdes_rst_dual_c|(|rdo_rx_serdes_rst_c[pnum_channels-1:0]);
+   assign rx_any_pcs_rst = rdo_rst_dual_c|(|rdo_rx_pcs_rst_c[pnum_channels-1:0]);
+   assign rx_any_rst = dual_or_rserd_rst | rx_any_pcs_rst;
+
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         rxsdr_appd <= 1'b1;  // Serdes dual reset (macro reset) applied
+      else if(rdo_serdes_rst_dual_c==1)
+         rxsdr_appd <= 1'b1;
+   end
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         rxdpr_appd <= 1'b0;  // Rx dual PCS reset (dual reset) applied
+      else if(~rx_all_well|dual_or_rserd_rst)
+         rxdpr_appd <= 1'b0;
+      else if(rdo_rst_dual_c==1)
+         rxdpr_appd <= 1'b1;
+   end
+
+   genvar l;
+   for(l=0;l<pnum_channels;l=l+1) begin : lfor
+      always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+         if(rui_rst==1'b1)
+            rxsr_appd[l] <= 1'b0; // rx serdes reset applied
+         else if(rdo_rx_serdes_rst_c[l]==1)
+            rxsr_appd[l] <= 1'b1;
+      end
+      always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         rxpr_appd[l] <= 1'b0; // rx pcs reset applied
+      else if(rdi_rx_los_low_s[l]|rdi_rx_cdr_lol_s[l]|rdo_serdes_rst_dual_c|rdo_rx_serdes_rst_c[l])
+         rxpr_appd[l] <= 1'b0;
+      else if(rxsdr_or_sr_appd&(~rx_all_well)&rdo_rx_pcs_rst_c[l])
+         rxpr_appd[l] <= 1'b1;
+      end
+   end
+
+   assign rxsdr_or_sr_appd = rxsdr_appd|(&rxsr_appd);
+
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         rxr_wt_en  <= 0;  // rx ready wait counter enable
+      //else if((rxr_wt_tc==1)||(dual_or_rserd_rst==1))
+      else if((rxr_wt_tc==1)||(dual_or_rserd_rst==1)||(rx_all_well==0)) // BM, 2/4/16
+         rxr_wt_en  <= 0;
+      else if(~ruo_rx_rdyr&rx_all_well&((&rxpr_appd)|rxdpr_appd))
+         rxr_wt_en  <= 1;
+   end
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         rxr_wt_cnt  <= 'd0;  // rx ready wait count
+      //else if((rxr_wt_tc==1)||(rx_any_rst==1))
+      else if((rxr_wt_tc==1)||(rx_any_rst==1)||(rx_all_well==0)) // BM, 2/4/16
+         rxr_wt_cnt  <= 'd0;
+      else if(rxr_wt_en==1)
+         rxr_wt_cnt  <= rxr_wt_cnt+1;
+   end
+   assign rxr_wt_tc = (rxr_wt_cnt==pwait_rx_rdy)?1'b1:1'b0;
+
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         ruo_rx_rdyr <= 1'b0; // rx serdes reset applied
+      else if((rx_any_rst==1)||(rx_all_well==0))
+         ruo_rx_rdyr <= 1'b0;
+      else if(rxr_wt_tc==1)
+         ruo_rx_rdyr <= 1'b1;
+   end
+   assign ruo_rx_rdy = ruo_rx_rdyr;
+   end         // if pport_rx_rdy
+   else
+      assign ruo_rx_rdy = 1'b0;
+   end // if ((pserdes_mode=="RX AND TX")||(pserdes_mode=="RX ONLY"))
+
+   else begin  // generate else (Tx only)
+      assign rdo_rx_serdes_rst_c = 4'd0;
+      assign rdo_rx_pcs_rst_c = 4'd0;
+      assign ruo_rx_rdy = 1'b0;
+   end // else: !if((pserdes_mode=="RX AND TX")||(pserdes_mode=="RX ONLY"))
+
+   endgenerate
+
+endmodule
+
+
+//   ===========================================================================
+//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
+//   ---------------------------------------------------------------------------
+//   Copyright (c) 2015 by Lattice Semiconductor Corporation
+//   ALL RIGHTS RESERVED 
+//   ------------------------------------------------------------------
+//
+//   Permission:
+//
+//      Lattice SG Pte. Ltd. grants permission to use this code
+//      pursuant to the terms of the Lattice Reference Design License Agreement. 
+//
+//
+//   Disclaimer:
+//
+//      This VHDL or Verilog source code is intended as a design reference
+//      which illustrates how these types of functions can be implemented.
+//      It is the user's responsibility to verify their design for
+//      consistency and functionality through the use of formal
+//      verification methods.  Lattice provides no warranty
+//      regarding the use or functionality of this code.
+//
+//   ---------------------------------------------------------------------------
+//
+//                  Lattice SG Pte. Ltd.
+//                  101 Thomson Road, United Square #07-02 
+//                  Singapore 307591
+//
+//
+//                  TEL: 1-800-Lattice (USA and Canada)
+//                       +65-6631-2000 (Singapore)
+//                       +1-503-268-8001 (other locations)
+//
+//                  web: http://www.latticesemi.com/
+//                  email: techsupport@latticesemi.com
+//
+//   ---------------------------------------------------------------------------
+//
+// =============================================================================
+//                         FILE DETAILS         
+// Project               : SLL - Soft Loss Of Lock(LOL) Logic
+// File                  : sll_core.v
+// Title                 : Top-level file for SLL 
+// Dependencies          : 1.
+//                       : 2.
+// Description           : 
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.0
+// Author(s)             : AV
+// Mod. Date             : March 2, 2015
+// Changes Made          : Initial Creation
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.1
+// Author(s)             : AV
+// Mod. Date             : June 8, 2015
+// Changes Made          : Following updates were made 
+//                       : 1. Changed all the PLOL status logic and FSM to run
+//                       :    on sli_refclk. 
+//                       : 2. Added the HB logic for presence of tx_pclk 
+//                       : 3. Changed the lparam assignment scheme for 
+//                       :    simulation purposes. 
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.2
+// Author(s)             : AV
+// Mod. Date             : June 24, 2015
+// Changes Made          : Updated the gearing logic for SDI dynamic rate change
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.3
+// Author(s)             : AV
+// Mod. Date             : July 14, 2015
+// Changes Made          : Added the logic for dynamic rate change in CPRI
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.4
+// Author(s)             : AV
+// Mod. Date             : August 21, 2015
+// Changes Made          : Added the logic for dynamic rate change of 5G CPRI & 
+//                         PCIe.
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.5
+// Author(s)             : ES/EB
+// Mod. Date             : March 21, 2017
+// Changes Made          : 1. Added pdiff_sync signal to syncrhonize pcount_diff 
+//                       :    to sli_refclk.
+//                       : 2. Updated terminal count logic for PCIe 5G
+//                       : 3. Modified checking of pcount_diff in SLL state
+//                       :    machine to cover actual count
+//                       :    (from 16-bits to 22-bits)
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.6
+// Author(s)             : ES
+// Mod. Date             : April 19, 2017
+// Changes Made          : 1. Added registered lock and unlock signal from
+//                            pdiff_sync to totally decouple pcount_diff from
+//                            SLL state machine.
+//                       : 2. Modified LPCLK_TC_4 to 1:1 clock ratio when CPRI
+//                            is operating @ 4.9125Gbps data rate.
+// =============================================================================
+`timescale 1ns/10ps
+
+module sgmii_ecp5sll_core ( 
+  //Reset and Clock inputs
+  sli_rst,         //Active high asynchronous reset input
+  sli_refclk,      //Refclk input to the Tx PLL
+  sli_pclk,        //Tx pclk output from the PCS
+  
+  //Control inputs
+  sli_div2_rate,   //Divide by 2 control; 0 - Full rate; 1 - Half rate
+  sli_div11_rate,  //Divide by 11 control; 0 - Full rate; 1 - Div by 11
+  sli_gear_mode,   //Gear mode control for PCS; 0 - 8/10; 1- 16/20
+  sli_cpri_mode,   //Mode of operation specific to CPRI protocol
+  sli_pcie_mode,   //Mode of operation specific to PCIe mode (2.5G or 5G)
+  
+  //LOL Output
+  slo_plol         //Tx PLL Loss of Lock output to the user logic
+  );
+  
+// Inputs
+input       sli_rst;
+input       sli_refclk;
+input       sli_pclk;
+input       sli_div2_rate;
+input       sli_div11_rate;
+input       sli_gear_mode;
+input [2:0] sli_cpri_mode;
+input       sli_pcie_mode;
+
+// Outputs
+output      slo_plol;
+
+
+// Parameters
+parameter PPROTOCOL              = "PCIE";     //Protocol selected by the User
+parameter PLOL_SETTING           = 0;          //PLL LOL setting. Possible values are 0,1,2,3
+parameter PDYN_RATE_CTRL         = "DISABLED"; //PCS Dynamic Rate control
+parameter PPCIE_MAX_RATE         = "2.5";      //PCIe max data rate
+parameter PDIFF_VAL_LOCK         = 20;         //Differential count value for Lock
+parameter PDIFF_VAL_UNLOCK       = 39;         //Differential count value for Unlock
+parameter PPCLK_TC               = 65535;      //Terminal count value for counter running on sli_pclk
+parameter PDIFF_DIV11_VAL_LOCK   = 3;          //Differential count value for Lock for SDI Div11
+parameter PDIFF_DIV11_VAL_UNLOCK = 3;          //Differential count value for Unlock for SDI Div11
+parameter PPCLK_DIV11_TC         = 2383;       //Terminal count value (SDI Div11) for counter running on sli_pclk
+
+
+// Local Parameters
+localparam [1:0]  LPLL_LOSS_ST         = 2'b00;       //PLL Loss state
+localparam [1:0]  LPLL_PRELOSS_ST      = 2'b01;       //PLL Pre-Loss state
+localparam [1:0]  LPLL_PRELOCK_ST      = 2'b10;       //PLL Pre-Lock state
+localparam [1:0]  LPLL_LOCK_ST         = 2'b11;       //PLL Lock state
+`ifdef RSL_SIM_MODE
+localparam [15:0] LRCLK_TC             = 16'd63;   //Terminal count value for counter running on sli_refclk
+`else
+localparam [15:0] LRCLK_TC             = 16'd65535;   //Terminal count value for counter running on sli_refclk
+`endif
+localparam [15:0] LRCLK_TC_PUL_WIDTH   = 16'd50;      //Pulse width for the Refclk terminal count pulse
+localparam [7:0]  LHB_WAIT_CNT         = 8'd255;      //Wait count for the Heartbeat signal
+
+// Local Parameters related to the CPRI dynamic modes
+// Terminal count values for the four CPRI modes
+localparam LPCLK_TC_0 = 32768;
+localparam LPCLK_TC_1 = 65536;
+localparam LPCLK_TC_2 = 131072;
+localparam LPCLK_TC_3 = 163840;
+localparam LPCLK_TC_4 = 65536;
+
+// Lock values count values for the four CPRI modes and four PLOL settings (4x5)
+// CPRI rate mode 0                CPRI rate mode 1                   CPRI rate mode 2                    CPRI rate mode 3                     CPRI rate mode 4
+localparam LPDIFF_LOCK_00 = 9;     localparam LPDIFF_LOCK_10 = 19;    localparam LPDIFF_LOCK_20 = 39;     localparam LPDIFF_LOCK_30 = 49;      localparam LPDIFF_LOCK_40 = 19;
+localparam LPDIFF_LOCK_01 = 9;     localparam LPDIFF_LOCK_11 = 19;    localparam LPDIFF_LOCK_21 = 39;     localparam LPDIFF_LOCK_31 = 49;      localparam LPDIFF_LOCK_41 = 19;
+localparam LPDIFF_LOCK_02 = 49;    localparam LPDIFF_LOCK_12 = 98;    localparam LPDIFF_LOCK_22 = 196;    localparam LPDIFF_LOCK_32 = 245;     localparam LPDIFF_LOCK_42 = 98;
+localparam LPDIFF_LOCK_03 = 131;   localparam LPDIFF_LOCK_13 = 262;   localparam LPDIFF_LOCK_23 = 524;    localparam LPDIFF_LOCK_33 = 655;     localparam LPDIFF_LOCK_43 = 262;
+
+// Unlock values count values for the four CPRI modes and four PLOL settings (4x5)
+// CPRI rate mode 0                  CPRI rate mode 1                      CPRI rate mode 2                       CPRI rate mode 3                         CPRI rate mode 4
+localparam LPDIFF_UNLOCK_00 = 19;    localparam LPDIFF_UNLOCK_10 = 39;     localparam LPDIFF_UNLOCK_20 = 78;      localparam LPDIFF_UNLOCK_30 = 98;        localparam LPDIFF_UNLOCK_40 = 39;
+localparam LPDIFF_UNLOCK_01 = 65;    localparam LPDIFF_UNLOCK_11 = 131;    localparam LPDIFF_UNLOCK_21 = 262;     localparam LPDIFF_UNLOCK_31 = 327;       localparam LPDIFF_UNLOCK_41 = 131;
+localparam LPDIFF_UNLOCK_02 = 72;    localparam LPDIFF_UNLOCK_12 = 144;    localparam LPDIFF_UNLOCK_22 = 288;     localparam LPDIFF_UNLOCK_32 = 360;       localparam LPDIFF_UNLOCK_42 = 144;
+localparam LPDIFF_UNLOCK_03 = 196;   localparam LPDIFF_UNLOCK_13 = 393;    localparam LPDIFF_UNLOCK_23 = 786;     localparam LPDIFF_UNLOCK_33 = 983;       localparam LPDIFF_UNLOCK_43 = 393;
+
+// Input and Output reg and wire declarations
+wire       sli_rst;
+wire       sli_refclk;
+wire       sli_pclk;
+wire       sli_div2_rate;
+wire       sli_div11_rate;
+wire       sli_gear_mode;
+wire [2:0] sli_cpri_mode;
+wire       sli_pcie_mode;
+wire       slo_plol;
+
+//-------------- Internal signals reg and wire declarations --------------------
+
+//Signals running on sli_refclk
+reg  [15:0] rcount;           //16-bit Counter
+reg         rtc_pul;          //Terminal count pulse
+reg         rtc_pul_p1;       //Terminal count pulse pipeline
+reg         rtc_ctrl;         //Terminal count pulse control
+
+reg  [7:0]  rhb_wait_cnt;     //Heartbeat wait counter
+
+//Heatbeat synchronization and pipeline registers
+wire        rhb_sync;
+reg         rhb_sync_p2;
+reg         rhb_sync_p1;
+
+//Pipeling registers for dynamic control mode
+wire        rgear;
+wire        rdiv2;
+wire        rdiv11;
+reg         rgear_p1;
+reg         rdiv2_p1;
+reg         rdiv11_p1;
+
+reg         rstat_pclk;        //Pclk presence/absence status
+
+reg  [21:0] rcount_tc;         //Tx_pclk terminal count register
+reg  [15:0] rdiff_comp_lock;   //Differential comparison value for Lock
+reg  [15:0] rdiff_comp_unlock; //Differential compariosn value for Unlock
+
+wire        rpcie_mode;        //PCIe mode signal synchronized to refclk
+reg         rpcie_mode_p1;     //PCIe mode pipeline register
+
+wire        rcpri_mod_ch_sync; //CPRI mode change synchronized to refclk
+reg         rcpri_mod_ch_p1;   //CPRI mode change pipeline register
+reg         rcpri_mod_ch_p2;   //CPRI mode change pipeline register
+reg         rcpri_mod_ch_st;   //CPRI mode change status
+
+reg  [1:0]  sll_state;         //Current-state register for LOL FSM
+
+reg         pll_lock;          //PLL Lock signal
+
+//Signals running on sli_pclk
+//Synchronization and pipeline registers
+wire        ppul_sync;
+reg         ppul_sync_p1;
+reg         ppul_sync_p2;
+reg         ppul_sync_p3;
+
+wire        pdiff_sync;
+reg         pdiff_sync_p1;
+   
+reg  [21:0] pcount;            //22-bit counter
+reg  [21:0] pcount_diff;       //Differential value between Tx_pclk counter and theoritical value
+
+//Heartbeat counter and heartbeat signal running on pclk
+reg  [2:0]  phb_cnt;
+reg         phb;
+
+//CPRI dynamic mode releated signals
+reg  [2:0]  pcpri_mode;
+reg         pcpri_mod_ch;
+
+//Assignment scheme changed mainly for simulation purpose
+wire [15:0] LRCLK_TC_w;
+assign LRCLK_TC_w = LRCLK_TC;
+
+reg         unlock;
+reg         lock;
+
+//Heartbeat synchronization
+sync # (.PDATA_RST_VAL(0)) phb_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (phb),
+  .data_out(rhb_sync)
+  );
+  
+  
+//Terminal count pulse synchronization
+sync # (.PDATA_RST_VAL(0)) rtc_sync_inst ( 
+  .clk     (sli_pclk),
+  .rst     (sli_rst),
+  .data_in (rtc_pul),
+  .data_out(ppul_sync)
+  );
+
+//Differential value logic update synchronization
+sync # (.PDATA_RST_VAL(0)) pdiff_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (ppul_sync),
+  .data_out(pdiff_sync)
+  );
+
+//Gear mode synchronization
+sync # (.PDATA_RST_VAL(0)) gear_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (sli_gear_mode),
+  .data_out(rgear)
+  );
+  
+//Div2 synchronization
+sync # (.PDATA_RST_VAL(0)) div2_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (sli_div2_rate),
+  .data_out(rdiv2)
+  );
+  
+//Div11 synchronization
+sync # (.PDATA_RST_VAL(0)) div11_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (sli_div11_rate),
+  .data_out(rdiv11)
+  );
+  
+//CPRI mode change synchronization
+sync # (.PDATA_RST_VAL(0)) cpri_mod_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (pcpri_mod_ch),
+  .data_out(rcpri_mod_ch_sync)
+  );
+  
+//PCIe mode change synchronization
+sync # (.PDATA_RST_VAL(0)) pcie_mod_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (sli_pcie_mode),
+  .data_out(rpcie_mode)
+  );  
+
+// =============================================================================
+// Synchronized Lock/Unlock signals
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    unlock        <= 1'b0;
+    lock          <= 1'b0;
+    pdiff_sync_p1 <= 1'b0;
+  end
+  else begin
+    pdiff_sync_p1 <= pdiff_sync;
+    if (unlock) begin
+      unlock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : unlock;
+    end
+    else begin
+      unlock <= pdiff_sync ? (pcount_diff[21:0] > {6'd0, rdiff_comp_unlock}) : 1'b0;
+    end
+    if (lock) begin
+      lock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : lock;
+    end
+    else begin
+      lock <= pdiff_sync ? (pcount_diff[21:0] <= {6'd0, rdiff_comp_lock}) : 1'b0;
+    end
+  end
+end
+
+// =============================================================================
+// Refclk Counter, pulse generation logic and Heartbeat monitor logic
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rcount     <= 16'd0;
+    rtc_pul    <= 1'b0;
+    rtc_ctrl   <= 1'b0;
+    rtc_pul_p1 <= 1'b0;
+  end
+  else begin
+    //Counter logic
+    if ((rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin
+      if (rtc_ctrl == 1'b1) begin
+        rcount <= LRCLK_TC_PUL_WIDTH;
+      end  
+    end
+    else begin
+      if (rcount != LRCLK_TC_w) begin
+        rcount <= rcount + 1;
+      end
+      else begin
+        rcount <= 16'd0;   
+      end
+    end
+    
+    //Pulse control logic
+    if (rcount == LRCLK_TC_w - 1) begin
+      rtc_ctrl <= 1'b1;
+    end
+    
+    //Pulse Generation logic
+    if (rtc_ctrl == 1'b1) begin
+      if ((rcount == LRCLK_TC_w) || (rcount < LRCLK_TC_PUL_WIDTH)) begin
+        rtc_pul <= 1'b1;
+    end  
+      else begin
+        rtc_pul <= 1'b0;  
+      end
+    end
+    
+    rtc_pul_p1 <= rtc_pul;  
+  end  
+end
+
+
+// =============================================================================
+// Heartbeat synchronization & monitor logic and Dynamic mode pipeline logic 
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rhb_sync_p1     <= 1'b0;
+    rhb_sync_p2     <= 1'b0;
+    rhb_wait_cnt    <= 8'd0;
+    rstat_pclk      <= 1'b0;
+    rgear_p1        <= 1'b0;
+    rdiv2_p1        <= 1'b0;
+    rdiv11_p1       <= 1'b0;
+    rcpri_mod_ch_p1 <= 1'b0;
+    rcpri_mod_ch_p2 <= 1'b0;
+    rcpri_mod_ch_st <= 1'b0;
+    rpcie_mode_p1   <= 1'b0;
+    
+  end
+  else begin
+    //Pipeline stages for the Heartbeat
+    rhb_sync_p1 <= rhb_sync;
+    rhb_sync_p2 <= rhb_sync_p1;
+    
+    //Pipeline stages of the Dynamic rate control signals
+    rgear_p1  <= rgear;
+    rdiv2_p1  <= rdiv2;
+    rdiv11_p1 <= rdiv11;
+    
+    //Pipeline stage for PCIe mode
+    rpcie_mode_p1 <= rpcie_mode;
+    
+    //Pipeline stage for CPRI mode change
+    rcpri_mod_ch_p1 <= rcpri_mod_ch_sync;
+    rcpri_mod_ch_p2 <= rcpri_mod_ch_p1;
+    
+    //CPRI mode change status logic
+    if (rcpri_mod_ch_p1^rcpri_mod_ch_sync == 1'b1) begin
+      rcpri_mod_ch_st <= 1'b1;
+    end 
+    
+    //Heartbeat wait counter and monitor logic
+    if (rtc_ctrl == 1'b1) begin
+      if (rhb_sync_p1 == 1'b1 && rhb_sync_p2 == 1'b0) begin
+        rhb_wait_cnt <= 8'd0;
+        rstat_pclk   <= 1'b1;
+      end
+      else if (rhb_wait_cnt == LHB_WAIT_CNT) begin
+        rhb_wait_cnt <= 8'd0;
+        rstat_pclk   <= 1'b0;
+      end
+      else begin
+        rhb_wait_cnt <= rhb_wait_cnt + 1;
+      end
+    end
+  end  
+end
+
+
+// =============================================================================
+// Pipleline registers for the TC pulse and CPRI mode change logic
+// =============================================================================
+always @(posedge sli_pclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    ppul_sync_p1 <= 1'b0;
+    ppul_sync_p2 <= 1'b0;
+    ppul_sync_p3 <= 1'b0;
+    pcpri_mode   <= 3'b0;
+    pcpri_mod_ch <= 1'b0;
+  end
+  else begin
+    ppul_sync_p1 <= ppul_sync;
+    ppul_sync_p2 <= ppul_sync_p1;
+    ppul_sync_p3 <= ppul_sync_p2;
+    
+    //CPRI mode change logic
+    pcpri_mode <= sli_cpri_mode;
+    
+    if (pcpri_mode != sli_cpri_mode) begin
+      pcpri_mod_ch <= ~pcpri_mod_ch;
+    end 
+  end  
+end
+   
+
+// =============================================================================
+// Terminal count logic
+// =============================================================================
+
+//For SDI protocol with Dynamic rate control enabled
+generate
+if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "SDI")) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rcount_tc         <= 22'd0;
+    rdiff_comp_lock   <= 16'd0;
+    rdiff_comp_unlock <= 16'd0;
+  end
+  else begin
+    //Terminal count logic
+    //Div by 11 is enabled
+    if (rdiv11 == 1'b1) begin
+      //Gear mode is 16/20
+      if (rgear == 1'b1) begin
+        rcount_tc         <= PPCLK_DIV11_TC;
+        rdiff_comp_lock   <= PDIFF_DIV11_VAL_LOCK;
+        rdiff_comp_unlock <= PDIFF_DIV11_VAL_UNLOCK;
+      end
+      else begin
+        rcount_tc         <= {PPCLK_DIV11_TC[20:0], 1'b0};
+        rdiff_comp_lock   <= {PDIFF_DIV11_VAL_LOCK[14:0], 1'b0};
+        rdiff_comp_unlock <= {PDIFF_DIV11_VAL_UNLOCK[14:0], 1'b0};
+      end
+    end
+    //Div by 2 is enabled
+    else if (rdiv2 == 1'b1) begin
+      //Gear mode is 16/20
+      if (rgear == 1'b1) begin
+        rcount_tc         <= {1'b0,PPCLK_TC[21:1]};
+        rdiff_comp_lock   <= {1'b0,PDIFF_VAL_LOCK[15:1]};
+        rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]};
+      end
+      else begin
+        rcount_tc         <= PPCLK_TC;
+        rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+        rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+      end
+    end
+    //Both div by 11 and div by 2 are disabled
+    else begin
+      //Gear mode is 16/20
+      if (rgear == 1'b1) begin
+        rcount_tc         <= PPCLK_TC;
+        rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+        rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+      end
+      else begin
+        rcount_tc         <= {PPCLK_TC[20:0],1'b0};
+        rdiff_comp_lock   <= {PDIFF_VAL_LOCK[14:0],1'b0};
+        rdiff_comp_unlock <= {PDIFF_VAL_UNLOCK[14:0],1'b0};
+      end
+    end
+  end  
+end
+end
+endgenerate
+
+//For G8B10B protocol with Dynamic rate control enabled
+generate
+if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "G8B10B")) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rcount_tc         <= 22'd0;
+    rdiff_comp_lock   <= 16'd0;
+    rdiff_comp_unlock <= 16'd0;
+  end
+  else begin
+    //Terminal count logic
+    //Div by 2 is enabled
+    if (rdiv2 == 1'b1) begin
+      rcount_tc         <= {1'b0,PPCLK_TC[21:1]};
+      rdiff_comp_lock   <= {1'b0,PDIFF_VAL_LOCK[15:1]};
+      rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]};
+    end
+    else begin
+      rcount_tc         <= PPCLK_TC;
+      rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+      rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+    end
+  end  
+end
+end
+endgenerate
+
+
+//For CPRI protocol with Dynamic rate control is disabled
+generate
+if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "CPRI")) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rcount_tc         <= 22'd0;
+    rdiff_comp_lock   <= 16'd0;
+    rdiff_comp_unlock <= 16'd0;
+  end
+  else begin
+    //Terminal count logic for CPRI protocol
+    //Only if there is a change in the rate mode from the default
+    if (rcpri_mod_ch_st == 1'b1) begin
+      if (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) begin
+        case(sli_cpri_mode)
+          3'd0 : begin //For 0.6Gbps
+            rcount_tc         <= LPCLK_TC_0;
+            case(PLOL_SETTING)
+              'd0 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_00;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_00;
+              end
+              
+              'd1 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_01;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_01;
+              end
+              
+              'd2 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_02;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_02;
+              end
+              
+              'd3 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_03;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_03;
+              end
+              
+              default : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_00;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_00;
+              end
+            endcase
+          end
+          
+          3'd1 : begin //For 1.2Gbps
+            rcount_tc         <= LPCLK_TC_1;
+            case(PLOL_SETTING)
+              'd0 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_10;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_10;
+              end
+              
+              'd1 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_11;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_11;
+              end
+              
+              'd2 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_12;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_12;
+              end
+              
+              'd3 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_13;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_13;
+              end
+              
+              default : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_10;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_10;
+              end
+            endcase
+          end
+          
+          3'd2 : begin //For 2.4Gbps
+            rcount_tc         <= LPCLK_TC_2;
+            case(PLOL_SETTING)
+              'd0 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_20;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_20;
+              end
+              
+              'd1 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_21;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_21;
+              end
+              
+              'd2 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_22;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_22;
+              end
+              
+              'd3 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_23;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_23;
+              end
+              
+              default : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_20;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_20;
+              end
+            endcase
+          end
+          
+          3'd3 : begin //For 3.07Gbps
+            rcount_tc         <= LPCLK_TC_3;
+            case(PLOL_SETTING)
+              'd0 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_30;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_30;
+              end
+              
+              'd1 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_31;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_31;
+              end
+              
+              'd2 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_32;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_32;
+              end
+              
+              'd3 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_33;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_33;
+              end
+            endcase
+          end    
+              
+          3'd4 : begin //For 4.9125bps
+            rcount_tc         <= LPCLK_TC_4;
+            case(PLOL_SETTING)
+              'd0 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_40;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_40;
+              end
+              
+              'd1 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_41;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_41;
+              end
+              
+              'd2 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_42;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_42;
+              end
+              
+              'd3 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_43;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_43;
+              end  
+            
+              default : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_40;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_40;
+              end
+            endcase
+          end
+        
+          default : begin
+            rcount_tc         <= LPCLK_TC_0;
+            rdiff_comp_lock   <= LPDIFF_LOCK_00;
+            rdiff_comp_unlock <= LPDIFF_UNLOCK_00;
+          end
+        endcase
+      end
+    end
+    else begin
+      //If there is no change in the CPRI rate mode from default
+      rcount_tc         <= PPCLK_TC;
+      rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+      rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+    end  
+  end  
+end
+end
+endgenerate
+
+//For PCIe protocol with Dynamic rate control disabled
+generate
+if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "PCIE")) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rcount_tc         <= 22'd0;
+    rdiff_comp_lock   <= 16'd0;
+    rdiff_comp_unlock <= 16'd0;
+  end
+  else begin
+    //Terminal count logic
+    if (PPCIE_MAX_RATE == "2.5") begin
+      //2.5G mode is enabled
+      rcount_tc         <= PPCLK_TC;
+      rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+      rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+    end
+    else begin
+      //5G mode is enabled
+      if (rpcie_mode == 1'b1) begin
+        rcount_tc         <= PPCLK_TC;
+        rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+        rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+      end
+      else begin
+        //2.5G mode is enabled
+        rcount_tc         <= {1'b0,PPCLK_TC[21:1]};
+        rdiff_comp_lock   <= {1'b0,PDIFF_VAL_LOCK[15:1]};
+        rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]};
+      end 
+    end          
+  end  
+end
+end
+endgenerate
+
+//For all protocols other than CPRI & PCIe
+generate
+if ((PDYN_RATE_CTRL == "DISABLED") && ((PPROTOCOL != "CPRI") && (PPROTOCOL != "PCIE"))) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rcount_tc         <= 22'd0;
+    rdiff_comp_lock   <= 16'd0;
+    rdiff_comp_unlock <= 16'd0;
+  end
+  else begin
+    //Terminal count logic for all protocols other than CPRI & PCIe
+    rcount_tc         <= PPCLK_TC;
+    rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+    rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+  end  
+end
+end
+endgenerate
+
+
+// =============================================================================
+// Tx_pclk counter, Heartbeat and Differential value logic
+// =============================================================================
+always @(posedge sli_pclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    pcount      <= 22'd0;
+    pcount_diff <= 22'd65535;
+    phb_cnt     <= 3'd0;
+    phb         <= 1'b0;
+  end
+  else begin
+    //Counter logic
+    if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin
+      pcount <= 22'd0;
+    end
+    else begin
+      pcount <= pcount + 1;
+    end
+    
+    //Heartbeat logic
+    phb_cnt <= phb_cnt + 1;
+    
+    if ((phb_cnt < 3'd4) && (phb_cnt >= 3'd0)) begin
+      phb <= 1'b1;
+    end  
+    else begin
+      phb <= 1'b0;  
+    end 
+    
+    //Differential value logic
+    if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin
+      pcount_diff <= rcount_tc + ~(pcount) + 1;
+    end  
+    else if (ppul_sync_p2 == 1'b1 && ppul_sync_p3 == 1'b0) begin
+      if (pcount_diff[21] == 1'b1) begin
+        pcount_diff <= ~(pcount_diff) + 1;
+      end
+    end
+  end  
+end
+
+
+// =============================================================================
+// State transition logic for SLL FSM
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    sll_state <= LPLL_LOSS_ST; 
+  end
+  else begin
+    //Reasons to declare an immediate loss - Absence of Tx_pclk, Dynamic rate change for SDI or CPRI
+    if ((rstat_pclk == 1'b0) || (rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || 
+    (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin
+      sll_state <= LPLL_LOSS_ST;
+    end
+    else begin  
+      case(sll_state)
+        LPLL_LOSS_ST : begin
+          if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin
+            if (unlock) begin
+              sll_state <= LPLL_LOSS_ST;
+            end
+            else if (lock) begin
+              if (PLOL_SETTING == 2'd0) begin
+                sll_state <= LPLL_PRELOCK_ST;
+              end
+              else begin
+                sll_state <= LPLL_LOCK_ST;
+              end
+            end
+          end
+        end
+        
+        LPLL_LOCK_ST : begin
+          if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin
+            if (lock) begin
+              sll_state <= LPLL_LOCK_ST;
+            end
+            else begin
+              if (PLOL_SETTING == 2'd0) begin
+                sll_state <= LPLL_LOSS_ST;
+              end
+              else begin
+                sll_state <= LPLL_PRELOSS_ST;
+              end
+            end
+          end
+        end
+        
+        LPLL_PRELOCK_ST : begin
+          if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin
+            if (lock) begin
+              sll_state <= LPLL_LOCK_ST;
+            end
+            else begin
+              sll_state <= LPLL_PRELOSS_ST;
+            end
+          end
+        end
+        
+        LPLL_PRELOSS_ST : begin
+          if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin
+            if (unlock) begin
+              sll_state <= LPLL_PRELOSS_ST;
+            end
+            else if (lock) begin
+              sll_state <= LPLL_LOCK_ST;
+            end
+          end
+        end
+        
+        default: begin
+          sll_state <= LPLL_LOSS_ST;
+        end
+      endcase
+    end  
+  end  
+end
+
+
+// =============================================================================
+// Logic for Tx PLL Lock
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    pll_lock <= 1'b0; 
+  end
+  else begin
+    case(sll_state)
+      LPLL_LOSS_ST : begin
+        pll_lock <= 1'b0;
+      end
+      
+      LPLL_LOCK_ST : begin
+        pll_lock <= 1'b1;
+      end
+      
+      LPLL_PRELOSS_ST : begin
+        pll_lock <= 1'b0;
+      end
+      
+      default: begin
+        pll_lock <= 1'b0;
+      end
+    endcase
+  end  
+end
+
+assign slo_plol = ~(pll_lock);
+
+endmodule  
+
+
+//   ===========================================================================
+//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
+//   ---------------------------------------------------------------------------
+//   Copyright (c) 2015 by Lattice Semiconductor Corporation
+//   ALL RIGHTS RESERVED 
+//   ------------------------------------------------------------------
+//
+//   Permission:
+//
+//      Lattice SG Pte. Ltd. grants permission to use this code
+//      pursuant to the terms of the Lattice Reference Design License Agreement. 
+//
+//
+//   Disclaimer:
+//
+//      This VHDL or Verilog source code is intended as a design reference
+//      which illustrates how these types of functions can be implemented.
+//      It is the user's responsibility to verify their design for
+//      consistency and functionality through the use of formal
+//      verification methods.  Lattice provides no warranty
+//      regarding the use or functionality of this code.
+//
+//   ---------------------------------------------------------------------------
+//
+//                  Lattice SG Pte. Ltd.
+//                  101 Thomson Road, United Square #07-02 
+//                  Singapore 307591
+//
+//
+//                  TEL: 1-800-Lattice (USA and Canada)
+//                       +65-6631-2000 (Singapore)
+//                       +1-503-268-8001 (other locations)
+//
+//                  web: http://www.latticesemi.com/
+//                  email: techsupport@latticesemi.com
+//
+//   ---------------------------------------------------------------------------
+//
+// =============================================================================
+//                         FILE DETAILS
+// Project               : Synchronizer Logic
+// File                  : sync.v
+// Title                 : Synchronizer module
+// Description           : 
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.0
+// Author(s)             : AV
+// Mod. Date             : July 7, 2015
+// Changes Made          : Initial Creation
+// -----------------------------------------------------------------------------
+// Version               : 1.1
+// Author(s)             : EB
+// Mod. Date             : March 21, 2017
+// Changes Made          : 
+// =============================================================================
+
+`ifndef PCS_SYNC_MODULE
+`define PCS_SYNC_MODULE
+module sync ( 
+  clk,
+  rst,
+  data_in,
+  data_out
+  );
+  
+input  clk;                  //Clock in which the async data needs to be synchronized to
+input  rst;                  //Active high reset
+input  data_in;              //Asynchronous data
+output data_out;             //Synchronized data
+
+parameter PDATA_RST_VAL = 0; //Reset value for the registers
+
+reg data_p1;
+reg data_p2;
+
+// =============================================================================
+// Synchronization logic
+// =============================================================================
+always @(posedge clk or posedge rst) begin
+  if (rst == 1'b1) begin
+    data_p1 <= PDATA_RST_VAL;
+    data_p2 <= PDATA_RST_VAL; 
+  end
+  else begin
+    data_p1 <= data_in;
+    data_p2 <= data_p1;
+  end  
+end
+
+assign data_out = data_p2; 
+
+endmodule    
+`endif
+

diff --git a/gbe/cores/sgmii/sgmii_ecp5/stdout.log.bak.1 b/gbe/cores/sgmii/sgmii_ecp5/stdout.log.bak.1
new file mode 100644 (file)
index 0000000..085fe8a
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/stdout.log.bak.1
@@ -0,0 +1,75 @@
+Running in Lattice mode
+
+Starting:    /home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/mbin/synbatch
+Install:     /home/soft/lattice/diamond/3.10_x64/synpbase
+Hostname:    lxhadeb07
+Date:        Tue May  7 17:10:00 2019
+Version:     M-2017.03L-SP1-1
+
+Arguments:   -product synplify_pro -batch /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.prj
+ProductType: synplify_pro
+
+
+
+
+log file: "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr"
+Running: syn_results in foreground
+
+Running sgmii_ecp5|syn_results
+
+Running: compile (Compile) on sgmii_ecp5|syn_results
+# Tue May  7 17:10:01 2019
+
+Running: compile_flow (Compile Process) on sgmii_ecp5|syn_results
+# Tue May  7 17:10:01 2019
+
+Running: compiler (Compile Input) on sgmii_ecp5|syn_results
+# Tue May  7 17:10:01 2019
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srs
+
+compiler completed
+# Tue May  7 17:10:03 2019
+
+Return Code: 0
+Run Time:00h:00m:02s
+
+Running: multi_srs_gen (Multi-srs Generator) on sgmii_ecp5|syn_results
+# Tue May  7 17:10:03 2019
+
+multi_srs_gen completed
+# Tue May  7 17:10:04 2019
+
+Return Code: 0
+Run Time:00h:00m:01s
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult.srs to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srs
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srf
+Complete: Compile Process on sgmii_ecp5|syn_results
+
+Running: premap (Pre-mapping) on sgmii_ecp5|syn_results
+# Tue May  7 17:10:04 2019
+
+premap completed with warnings
+# Tue May  7 17:10:04 2019
+
+Return Code: 1
+Run Time:00h:00m:00s
+Complete: Compile on sgmii_ecp5|syn_results
+
+Running: map (Map) on sgmii_ecp5|syn_results
+# Tue May  7 17:10:04 2019
+License granted for 4 parallel jobs
+
+Running: fpga_mapper (Map & Optimize) on sgmii_ecp5|syn_results
+# Tue May  7 17:10:04 2019
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srm
+
+fpga_mapper completed with warnings
+# Tue May  7 17:10:08 2019
+
+Return Code: 1
+Run Time:00h:00m:04s
+Complete: Map on sgmii_ecp5|syn_results
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srf
+Complete: Logic Synthesis on sgmii_ecp5|syn_results
+exit status=0
+exit status=0

diff --git a/gbe/cores/sgmii/sgmii_ecp5/stdout.log.bak.2 b/gbe/cores/sgmii/sgmii_ecp5/stdout.log.bak.2
new file mode 100644 (file)
index 0000000..b9b8215
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/stdout.log.bak.2
@@ -0,0 +1,75 @@
+Running in Lattice mode
+
+Starting:    /home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/mbin/synbatch
+Install:     /home/soft/lattice/diamond/3.10_x64/synpbase
+Hostname:    lxhadeb07
+Date:        Tue May  7 16:13:41 2019
+Version:     M-2017.03L-SP1-1
+
+Arguments:   -product synplify_pro -batch /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.prj
+ProductType: synplify_pro
+
+
+
+
+log file: "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr"
+Running: syn_results in foreground
+
+Running sgmii_ecp5|syn_results
+
+Running: compile (Compile) on sgmii_ecp5|syn_results
+# Tue May  7 16:13:41 2019
+
+Running: compile_flow (Compile Process) on sgmii_ecp5|syn_results
+# Tue May  7 16:13:41 2019
+
+Running: compiler (Compile Input) on sgmii_ecp5|syn_results
+# Tue May  7 16:13:41 2019
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srs
+
+compiler completed
+# Tue May  7 16:13:44 2019
+
+Return Code: 0
+Run Time:00h:00m:03s
+
+Running: multi_srs_gen (Multi-srs Generator) on sgmii_ecp5|syn_results
+# Tue May  7 16:13:44 2019
+
+multi_srs_gen completed
+# Tue May  7 16:13:44 2019
+
+Return Code: 0
+Run Time:00h:00m:00s
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult.srs to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srs
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srf
+Complete: Compile Process on sgmii_ecp5|syn_results
+
+Running: premap (Pre-mapping) on sgmii_ecp5|syn_results
+# Tue May  7 16:13:44 2019
+
+premap completed with warnings
+# Tue May  7 16:13:45 2019
+
+Return Code: 1
+Run Time:00h:00m:01s
+Complete: Compile on sgmii_ecp5|syn_results
+
+Running: map (Map) on sgmii_ecp5|syn_results
+# Tue May  7 16:13:45 2019
+License granted for 4 parallel jobs
+
+Running: fpga_mapper (Map & Optimize) on sgmii_ecp5|syn_results
+# Tue May  7 16:13:45 2019
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srm
+
+fpga_mapper completed with warnings
+# Tue May  7 16:13:48 2019
+
+Return Code: 1
+Run Time:00h:00m:03s
+Complete: Map on sgmii_ecp5|syn_results
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srf
+Complete: Logic Synthesis on sgmii_ecp5|syn_results
+exit status=0
+exit status=0

diff --git a/gbe/cores/sgmii/sgmii_ecp5/stdout.log.bak.3 b/gbe/cores/sgmii/sgmii_ecp5/stdout.log.bak.3
new file mode 100644 (file)
index 0000000..c1fc835
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/stdout.log.bak.3
@@ -0,0 +1,76 @@
+Running in Lattice mode
+
+Starting:    /home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/mbin/synbatch
+Install:     /home/soft/lattice/diamond/3.10_x64/synpbase
+Hostname:    lxhadeb07
+Date:        Mon Apr 29 16:13:15 2019
+Version:     M-2017.03L-SP1-1
+
+Arguments:   -product synplify_pro -batch /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.prj
+ProductType: synplify_pro
+
+
+
+
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/backup/sgmii_ecp5.srr
+log file: "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr"
+Running: syn_results in foreground
+
+Running sgmii_ecp5|syn_results
+
+Running: compile (Compile) on sgmii_ecp5|syn_results
+# Mon Apr 29 16:13:16 2019
+
+Running: compile_flow (Compile Process) on sgmii_ecp5|syn_results
+# Mon Apr 29 16:13:16 2019
+
+Running: compiler (Compile Input) on sgmii_ecp5|syn_results
+# Mon Apr 29 16:13:16 2019
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srs
+
+compiler completed
+# Mon Apr 29 16:13:18 2019
+
+Return Code: 0
+Run Time:00h:00m:02s
+
+Running: multi_srs_gen (Multi-srs Generator) on sgmii_ecp5|syn_results
+# Mon Apr 29 16:13:18 2019
+
+multi_srs_gen completed
+# Mon Apr 29 16:13:18 2019
+
+Return Code: 0
+Run Time:00h:00m:00s
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult.srs to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srs
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srf
+Complete: Compile Process on sgmii_ecp5|syn_results
+
+Running: premap (Pre-mapping) on sgmii_ecp5|syn_results
+# Mon Apr 29 16:13:18 2019
+
+premap completed with warnings
+# Mon Apr 29 16:13:19 2019
+
+Return Code: 1
+Run Time:00h:00m:01s
+Complete: Compile on sgmii_ecp5|syn_results
+
+Running: map (Map) on sgmii_ecp5|syn_results
+# Mon Apr 29 16:13:19 2019
+License granted for 4 parallel jobs
+
+Running: fpga_mapper (Map & Optimize) on sgmii_ecp5|syn_results
+# Mon Apr 29 16:13:19 2019
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srm
+
+fpga_mapper completed with warnings
+# Mon Apr 29 16:13:22 2019
+
+Return Code: 1
+Run Time:00h:00m:03s
+Complete: Map on sgmii_ecp5|syn_results
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srf
+Complete: Logic Synthesis on sgmii_ecp5|syn_results
+exit status=0
+exit status=0

diff --git a/gbe/cores/sgmii/sgmii_ecp5/stdout.log.bak.4 b/gbe/cores/sgmii/sgmii_ecp5/stdout.log.bak.4
new file mode 100644 (file)
index 0000000..ebf331c
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/stdout.log.bak.4
@@ -0,0 +1,75 @@
+Running in Lattice mode
+
+Starting:    /home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/mbin/synbatch
+Install:     /home/soft/lattice/diamond/3.10_x64/synpbase
+Hostname:    lxhadeb07
+Date:        Wed Apr 24 09:44:47 2019
+Version:     M-2017.03L-SP1-1
+
+Arguments:   -product synplify_pro -batch /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.prj
+ProductType: synplify_pro
+
+
+
+
+log file: "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr"
+Running: syn_results in foreground
+
+Running sgmii_ecp5|syn_results
+
+Running: compile (Compile) on sgmii_ecp5|syn_results
+# Wed Apr 24 09:44:47 2019
+
+Running: compile_flow (Compile Process) on sgmii_ecp5|syn_results
+# Wed Apr 24 09:44:47 2019
+
+Running: compiler (Compile Input) on sgmii_ecp5|syn_results
+# Wed Apr 24 09:44:47 2019
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srs
+
+compiler completed
+# Wed Apr 24 09:44:50 2019
+
+Return Code: 0
+Run Time:00h:00m:03s
+
+Running: multi_srs_gen (Multi-srs Generator) on sgmii_ecp5|syn_results
+# Wed Apr 24 09:44:50 2019
+
+multi_srs_gen completed
+# Wed Apr 24 09:44:50 2019
+
+Return Code: 0
+Run Time:00h:00m:00s
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult.srs to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srs
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srf
+Complete: Compile Process on sgmii_ecp5|syn_results
+
+Running: premap (Pre-mapping) on sgmii_ecp5|syn_results
+# Wed Apr 24 09:44:50 2019
+
+premap completed with warnings
+# Wed Apr 24 09:44:51 2019
+
+Return Code: 1
+Run Time:00h:00m:01s
+Complete: Compile on sgmii_ecp5|syn_results
+
+Running: map (Map) on sgmii_ecp5|syn_results
+# Wed Apr 24 09:44:51 2019
+License granted for 4 parallel jobs
+
+Running: fpga_mapper (Map & Optimize) on sgmii_ecp5|syn_results
+# Wed Apr 24 09:44:51 2019
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srm
+
+fpga_mapper completed with warnings
+# Wed Apr 24 09:44:54 2019
+
+Return Code: 1
+Run Time:00h:00m:03s
+Complete: Map on sgmii_ecp5|syn_results
+Copied /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr to /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srf
+Complete: Logic Synthesis on sgmii_ecp5|syn_results
+exit status=0
+exit status=0

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/.recordref b/gbe/cores/sgmii/sgmii_ecp5/syn_results/.recordref
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/_CMD_.CML b/gbe/cores/sgmii/sgmii_ecp5/syn_results/_CMD_.CML
new file mode 100644 (file)
index 0000000..87a778c
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/_CMD_.CML
@@ -0,0 +1 @@
+ -osyn  /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs  -top  sgmii_ecp5  -hdllog  /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr  -encrypt  -mp  4  -verification_mode 0  -vhdl  -prodtype  synplify_pro  -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver  -encrypt  -pro  -dmgen  /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/dm  -lite -ui -fid2 -ram -sharing on -ll 2000 -autosm  -ignore_undefined_lib  -lib work /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd  -verilog  -prodtype  synplify_pro  -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver   -I /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/  -I /home/soft/lattice/diamond/3.10_x64/synpbase/lib   -v2001  -devicelib  /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v  -devicelib  /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v  -encrypt  -pro  -dmgen  /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/dm  -ui -fid2 -ram -sharing on -ll 2000 -autosm  -lib work /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v  -jobname  "compiler" 
\ No newline at end of file

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/_cmd._cml b/gbe/cores/sgmii/sgmii_ecp5/syn_results/_cmd._cml
new file mode 100644 (file)
index 0000000..225b64d
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/_cmd._cml
@@ -0,0 +1 @@
+-link    -encrypt        -top sgmii_ecp5 -osyn /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/layer0.srs /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/layer1.srs   
\ No newline at end of file

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/backup/sgmii_ecp5.srr b/gbe/cores/sgmii/sgmii_ecp5/syn_results/backup/sgmii_ecp5.srr
new file mode 100644 (file)
index 0000000..f6086bf
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/backup/sgmii_ecp5.srr
@@ -0,0 +1,1157 @@
+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
+#install: /home/soft/lattice/diamond/3.10_x64/synpbase
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Wed Apr 24 09:44:47 2019
+
+#Implementation: syn_results
+
+Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
+VHDL syntax check successful!
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Wed Apr 24 09:44:48 2019
+
+###########################################################]
+Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
+Verilog syntax check successful!
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Wed Apr 24 09:44:48 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
+VHDL syntax check successful!
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1.
+Post processing for work.sgmii_ecp5.v1
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB)
+
+
+Process completed successfully.
+# Wed Apr 24 09:44:48 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
+Verilog syntax check successful!
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work.
+
+       PDATA_RST_VAL=32'b00000000000000000000000000000000
+   Generated name = sync_0s
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work.
+
+       PPROTOCOL=24'b010001110100001001000101
+       PLOL_SETTING=32'b00000000000000000000000000000000
+       PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100
+       PPCIE_MAX_RATE=24'b001100100010111000110101
+       PDIFF_VAL_LOCK=32'b00000000000000000000000000100111
+       PDIFF_VAL_UNLOCK=32'b00000000000000000000000001001110
+       PPCLK_TC=32'b00000000000000100000000000000000
+       PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000
+       PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000
+       PPCLK_DIV11_TC=32'b00000000000000000000000000000000
+       LPLL_LOSS_ST=2'b00
+       LPLL_PRELOSS_ST=2'b01
+       LPLL_PRELOCK_ST=2'b10
+       LPLL_LOCK_ST=2'b11
+       LRCLK_TC=16'b1111111111111111
+       LRCLK_TC_PUL_WIDTH=16'b0000000000110010
+       LHB_WAIT_CNT=8'b11111111
+       LPCLK_TC_0=32'b00000000000000001000000000000000
+       LPCLK_TC_1=32'b00000000000000010000000000000000
+       LPCLK_TC_2=32'b00000000000000100000000000000000
+       LPCLK_TC_3=32'b00000000000000101000000000000000
+       LPCLK_TC_4=32'b00000000000000010000000000000000
+       LPDIFF_LOCK_00=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_10=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_20=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_30=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_40=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_01=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_11=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_21=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_31=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_41=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_02=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_12=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_22=32'b00000000000000000000000011000100
+       LPDIFF_LOCK_32=32'b00000000000000000000000011110101
+       LPDIFF_LOCK_42=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_03=32'b00000000000000000000000010000011
+       LPDIFF_LOCK_13=32'b00000000000000000000000100000110
+       LPDIFF_LOCK_23=32'b00000000000000000000001000001100
+       LPDIFF_LOCK_33=32'b00000000000000000000001010001111
+       LPDIFF_LOCK_43=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011
+       LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110
+       LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010
+       LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001
+       LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111
+       LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000
+       LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000
+       LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000
+       LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100
+       LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001
+       LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010
+       LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111
+       LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001
+   Generated name = sgmii_ecp5sll_core_Z1_layer1
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment.
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work.
+
+       pnum_channels=32'b00000000000000000000000000000001
+       pprotocol=24'b010001110100001001000101
+       pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
+       pport_tx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100
+       pwait_tx_rdy=32'b00000000000000000000101110111000
+       pport_rx_rdy=64'b0100010001001001010100110100000101000010010011000100010101000100
+       pwait_rx_rdy=32'b00000000000000000000101110111000
+       wa_num_cycles=32'b00000000000000000000010000000000
+       dac_num_cycles=32'b00000000000000000000000000000011
+       lreset_pwidth=32'b00000000000000000000000000000011
+       lwait_b4_trst=32'b00000000000010111110101111000010
+       lwait_b4_trst_s=32'b00000000000000000000001100001101
+       lplol_cnt_width=32'b00000000000000000000000000010100
+       lwait_after_plol0=32'b00000000000000000000000000000100
+       lwait_b4_rrst=32'b00000000000000101100000000000000
+       lrrst_wait_width=32'b00000000000000000000000000010100
+       lwait_after_rrst=32'b00000000000011000011010100000000
+       lwait_b4_rrst_s=32'b00000000000000000000000111001100
+       lrlol_cnt_width=32'b00000000000000000000000000010011
+       lwait_after_lols=32'b00000000000000001100010000000000
+       lwait_after_lols_s=32'b00000000000000000000000010010110
+       llols_cnt_width=32'b00000000000000000000000000010010
+       lrdb_max=32'b00000000000000000000000000001111
+       ltxr_wait_width=32'b00000000000000000000000000001100
+       lrxr_wait_width=32'b00000000000000000000000000001100
+   Generated name = sgmii_ecp5rsl_core_Z2_layer1
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":274:33:274:48|Removing wire dual_or_serd_rst, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":275:33:275:46|Removing wire tx_any_pcs_rst, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":276:33:276:42|Removing wire tx_any_rst, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":277:33:277:41|Object txsr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":278:33:278:42|Object txdpr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":279:33:279:41|Object txpr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":280:33:280:41|Object txr_wt_en is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":281:33:281:42|Object txr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":282:33:282:41|Removing wire txr_wt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":283:33:283:43|Object ruo_tx_rdyr is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":356:33:356:41|Object rxsr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":357:33:357:41|Object rxpr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":358:33:358:42|Object rxsdr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":359:33:359:42|Object rxdpr_appd is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":360:33:360:48|Removing wire rxsdr_or_sr_appd, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":361:33:361:49|Removing wire dual_or_rserd_rst, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":362:33:362:46|Removing wire rx_any_pcs_rst, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":363:33:363:42|Removing wire rx_any_rst, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":364:33:364:41|Object rxr_wt_en is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":365:33:365:42|Object rxr_wt_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":366:33:366:41|Removing wire rxr_wt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":367:33:367:43|Object ruo_rx_rdyr is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":507:10:507:10|Object m is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":880:10:880:10|Object l is declared but not assigned. Either assign a value or remove the declaration.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers.
+@N: CL201 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state.
+Extracted state machine for register sll_state
+State machine has 4 reachable states with original encodings of:
+   00
+   01
+   10
+   11
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 76MB)
+
+
+Process completed successfully.
+# Wed Apr 24 09:44:49 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+
+=======================================================================================
+For a summary of linker messages for components that did not bind, please see log file:
+@L: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.linkerlog
+=======================================================================================
+
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Apr 24 09:44:49 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Apr 24 09:44:49 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Wed Apr 24 09:44:50 2019
+
+###########################################################]
+Pre-mapping Report
+
+# Wed Apr 24 09:44:50 2019
+
+Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.fdc
+@L: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt 
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt" file 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)
+
+@N: BN362 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances.
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist sgmii_ecp5
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+
+Clock Summary
+******************
+
+          Start                                 Requested     Requested     Clock        Clock                   Clock
+Level     Clock                                 Frequency     Period        Type         Group                   Load 
+----------------------------------------------------------------------------------------------------------------------
+0 -       System                                100.0 MHz     10.000        system       system_clkgroup         0    
+                                                                                                                      
+0 -       sgmii_ecp5|pll_refclki                100.0 MHz     10.000        inferred     Inferred_clkgroup_0     76   
+                                                                                                                      
+0 -       sgmii_ecp5|rxrefclk                   100.0 MHz     10.000        inferred     Inferred_clkgroup_1     59   
+                                                                                                                      
+0 -       sgmii_ecp5|tx_pclk_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_2     53   
+======================================================================================================================
+
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 76 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 59 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   10 -> 10
+   11 -> 11
+@N: MO225 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 144MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Wed Apr 24 09:44:51 2019
+
+###########################################################]
+Map & Optimize Report
+
+# Wed Apr 24 09:44:51 2019
+
+Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB)
+
+Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   10 -> 10
+   11 -> 11
+@N: MO225 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] 
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 146MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
+
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+
+Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 146MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+   1           0h:00m:01s                   5.36ns              118 /       186
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+3 non-gated/non-generated clock tree(s) driving 186 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+=================================== Non-Gated/Non-Generated Clocks ====================================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                
+-------------------------------------------------------------------------------------------------------
+@K:CKID0001       pll_refclki         port                   74         rsl_inst.genblk1\.pll_lol_p1   
+@K:CKID0002       rxrefclk            port                   59         rsl_inst.genblk2\.rlol1_cnt[18]
+@K:CKID0003       DCU0_inst           DCUA                   53         sll_inst.pcount[21]            
+=======================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 109MB peak: 146MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 146MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.edn
+M-2017.03L-SP1-1
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 148MB peak: 150MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 148MB peak: 150MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 148MB peak: 150MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 149MB peak: 150MB)
+
+@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":150:4:150:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"
+@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"
+@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk"
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Wed Apr 24 09:44:54 2019
+#
+
+
+Top view:               sgmii_ecp5
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.fdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 4.079
+
+                                      Requested     Estimated       Requested     Estimated               Clock        Clock              
+Starting Clock                        Frequency     Frequency       Period        Period        Slack     Type         Group              
+------------------------------------------------------------------------------------------------------------------------------------------
+sgmii_ecp5|pll_refclki                100.0 MHz     168.9 MHz       10.000        5.921         4.079     inferred     Inferred_clkgroup_0
+sgmii_ecp5|rxrefclk                   100.0 MHz     170.5 MHz       10.000        5.864         4.136     inferred     Inferred_clkgroup_1
+sgmii_ecp5|tx_pclk_inferred_clock     100.0 MHz     237.5 MHz       10.000        4.211         5.789     inferred     Inferred_clkgroup_2
+System                                100.0 MHz     18518.5 MHz     10.000        0.054         9.946     system       system_clkgroup    
+==========================================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                                                                |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+Starting                           Ending                             |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+System                             sgmii_ecp5|rxrefclk                |  10.000      9.946  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             System                             |  10.000      8.385  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             sgmii_ecp5|pll_refclki             |  10.000      4.079  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             sgmii_ecp5|tx_pclk_inferred_clock  |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|rxrefclk                System                             |  10.000      8.283  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|rxrefclk                sgmii_ecp5|rxrefclk                |  10.000      4.136  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|tx_pclk_inferred_clock  sgmii_ecp5|pll_refclki             |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|tx_pclk_inferred_clock  sgmii_ecp5|tx_pclk_inferred_clock  |  10.000      5.789  |  No paths    -      |  No paths    -      |  No paths    -    
+============================================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|pll_refclki
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                   Starting                                                        Arrival          
+Instance                           Reference                  Type        Pin     Net              Time        Slack
+                                   Clock                                                                            
+--------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[1]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[1]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[6]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[6]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[7]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[7]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[12]     sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[12]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[2]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[2]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[3]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[3]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[4]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[4]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[5]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[5]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[8]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[8]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[9]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[9]      0.907       4.684
+====================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                   Starting                                                          Required          
+Instance                           Reference                  Type        Pin     Net                Time         Slack
+                                   Clock                                                                               
+-----------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[19]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[19]     9.946        4.079
+rsl_inst.genblk1\.plol_cnt[17]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[17]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[18]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[18]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[15]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[15]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[16]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[16]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[13]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[13]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[14]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[14]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[11]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[11]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[12]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[12]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[9]      sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[9]      9.946        4.383
+=======================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.867
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     4.079
+
+    Number of logic level(s):                15
+    Starting point:                          rsl_inst.genblk1\.plol_cnt[1] / Q
+    Ending point:                            rsl_inst.genblk1\.plol_cnt[19] / D
+    The start point is clocked by            sgmii_ecp5|pll_refclki [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|pll_refclki [rising] on pin CK
+
+Instance / Net                                        Pin      Pin               Arrival     No. of    
+Name                                     Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[1]            FD1S3DX      Q        Out     0.907     0.907       -         
+plol_cnt[1]                              Net          -        -       -         -           2         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     Z        Out     0.606     1.513       -         
+un1_plol_cnt_tc_10                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     Z        Out     0.606     2.119       -         
+un1_plol_cnt_tc_14                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     Z        Out     0.762     2.881       -         
+un1_plol_cnt_tc                          Net          -        -       -         -           5         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     B        In      0.000     2.881       -         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     Z        Out     0.840     3.721       -         
+plol_cnt                                 Net          -        -       -         -           21        
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.721       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.621       -         
+plol_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.621       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.682       -         
+plol_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.682       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.743       -         
+plol_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.743       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.804       -         
+plol_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.804       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.865       -         
+plol_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.865       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.926       -         
+plol_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.926       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.987       -         
+plol_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.987       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.048       -         
+plol_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.048       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.109       -         
+plol_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.109       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        COUT     Out     0.061     5.170       -         
+plol_cnt_cry[18]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        CIN      In      0.000     5.170       -         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        S0       Out     0.698     5.867       -         
+plol_cnt_s[19]                           Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt[19]           FD1S3DX      D        In      0.000     5.867       -         
+=======================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|rxrefclk
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                     Starting                                                       Arrival          
+Instance                             Reference               Type        Pin     Net                Time        Slack
+                                     Clock                                                                           
+---------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[14]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[14]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[15]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[15]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[16]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[16]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[17]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[17]      0.907       4.136
+rsl_inst.genblk2\.rlols0_cnt[7]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[7]      0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[8]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[8]      0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[9]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[9]      0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[10]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[10]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[11]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[11]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[14]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[14]     0.907       4.170
+=====================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                     Starting                                                         Required          
+Instance                             Reference               Type        Pin     Net                  Time         Slack
+                                     Clock                                                                              
+------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[17]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[17]      9.946        4.136
+rsl_inst.genblk2\.rlol1_cnt[18]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[18]      9.946        4.136
+rsl_inst.genblk2\.rlols0_cnt[17]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rlols0_cnt_s[17]     9.946        4.170
+rsl_inst.genblk2\.rlol1_cnt[15]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[15]      9.946        4.197
+rsl_inst.genblk2\.rlol1_cnt[16]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[16]      9.946        4.197
+rsl_inst.genblk2\.rlols0_cnt[15]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rlols0_cnt_s[15]     9.946        4.231
+rsl_inst.genblk2\.rlols0_cnt[16]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rlols0_cnt_s[16]     9.946        4.231
+rsl_inst.genblk2\.rlol1_cnt[13]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[13]      9.946        4.258
+rsl_inst.genblk2\.rlol1_cnt[14]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[14]      9.946        4.258
+rsl_inst.genblk2\.rlols0_cnt[13]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rlols0_cnt_s[13]     9.946        4.292
+========================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.809
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.136
+
+    Number of logic level(s):                14
+    Starting point:                          rsl_inst.genblk2\.rlol1_cnt[14] / Q
+    Ending point:                            rsl_inst.genblk2\.rlol1_cnt[18] / D
+    The start point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+
+Instance / Net                                         Pin      Pin               Arrival     No. of    
+Name                                      Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[14]           FD1P3DX      Q        Out     0.907     0.907       -         
+rlol1_cnt[14]                             Net          -        -       -         -           2         
+rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     Z        Out     0.606     1.513       -         
+rlol1_cnt_tc_1_10                         Net          -        -       -         -           1         
+rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     Z        Out     0.606     2.119       -         
+rlol1_cnt_tc_1_14                         Net          -        -       -         -           1         
+rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     Z        Out     0.768     2.887       -         
+rlol1_cnt_tc_1                            Net          -        -       -         -           6         
+rsl_inst.genblk2\.rlos_db_p1_RNIS0OP      ORCALUT4     A        In      0.000     2.887       -         
+rsl_inst.genblk2\.rlos_db_p1_RNIS0OP      ORCALUT4     Z        Out     0.837     3.724       -         
+rlol1_cnt                                 Net          -        -       -         -           20        
+rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.724       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.624       -         
+rlol1_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.624       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.685       -         
+rlol1_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.685       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.746       -         
+rlol1_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.746       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.807       -         
+rlol1_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.807       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.868       -         
+rlol1_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.868       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.929       -         
+rlol1_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.929       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.990       -         
+rlol1_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.990       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.051       -         
+rlol1_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.051       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.112       -         
+rlol1_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.112       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        S1       Out     0.698     5.809       -         
+rlol1_cnt_s[18]                           Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt[18]           FD1P3DX      D        In      0.000     5.809       -         
+========================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|tx_pclk_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                            Starting                                                                   Arrival          
+Instance                    Reference                             Type        Pin     Net              Time        Slack
+                            Clock                                                                                       
+------------------------------------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1       sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p1     1.098       5.789
+sll_inst.ppul_sync_p2       sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p2     1.098       5.789
+sll_inst.pcount_diff[0]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_0      0.985       6.147
+sll_inst.pcount[0]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[0]        0.955       6.178
+sll_inst.pcount_diff[1]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_1      0.955       6.239
+sll_inst.pcount_diff[2]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_2      0.955       6.239
+sll_inst.pcount[1]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[1]        0.907       6.287
+sll_inst.pcount[2]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[2]        0.907       6.287
+sll_inst.pcount_diff[3]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_3      0.955       6.300
+sll_inst.pcount_diff[4]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_4      0.955       6.300
+========================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                             Starting                                                                                  Required          
+Instance                     Reference                             Type        Pin     Net                             Time         Slack
+                             Clock                                                                                                       
+-----------------------------------------------------------------------------------------------------------------------------------------
+sll_inst.pcount[21]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[21]                    9.946        5.789
+sll_inst.pcount[19]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[19]                    9.946        5.850
+sll_inst.pcount[20]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[20]                    9.946        5.850
+sll_inst.pcount[17]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[17]                    9.946        5.911
+sll_inst.pcount[18]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[18]                    9.946        5.911
+sll_inst.pcount[15]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[15]                    9.946        5.972
+sll_inst.pcount[16]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[16]                    9.946        5.972
+sll_inst.pcount[13]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[13]                    9.946        6.033
+sll_inst.pcount[14]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[14]                    9.946        6.033
+sll_inst.pcount_diff[21]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3DX     D       un1_pcount_diff_1_s_21_0_S0     9.946        6.034
+=========================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      4.157
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 5.789
+
+    Number of logic level(s):                13
+    Starting point:                          sll_inst.ppul_sync_p1 / Q
+    Ending point:                            sll_inst.pcount[21] / D
+    The start point is clocked by            sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
+
+Instance / Net                             Pin      Pin               Arrival     No. of    
+Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1         FD1S3DX      Q        Out     1.098     1.098       -         
+ppul_sync_p1                  Net          -        -       -         -           25        
+sll_inst.pcount10_0_o3        ORCALUT4     A        In      0.000     1.098       -         
+sll_inst.pcount10_0_o3        ORCALUT4     Z        Out     0.851     1.950       -         
+N_8                           Net          -        -       -         -           25        
+sll_inst.pcount_cry_0[0]      CCU2C        A1       In      0.000     1.950       -         
+sll_inst.pcount_cry_0[0]      CCU2C        COUT     Out     0.900     2.850       -         
+pcount_cry[0]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[1]      CCU2C        CIN      In      0.000     2.850       -         
+sll_inst.pcount_cry_0[1]      CCU2C        COUT     Out     0.061     2.911       -         
+pcount_cry[2]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[3]      CCU2C        CIN      In      0.000     2.911       -         
+sll_inst.pcount_cry_0[3]      CCU2C        COUT     Out     0.061     2.972       -         
+pcount_cry[4]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[5]      CCU2C        CIN      In      0.000     2.972       -         
+sll_inst.pcount_cry_0[5]      CCU2C        COUT     Out     0.061     3.033       -         
+pcount_cry[6]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[7]      CCU2C        CIN      In      0.000     3.033       -         
+sll_inst.pcount_cry_0[7]      CCU2C        COUT     Out     0.061     3.094       -         
+pcount_cry[8]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[9]      CCU2C        CIN      In      0.000     3.094       -         
+sll_inst.pcount_cry_0[9]      CCU2C        COUT     Out     0.061     3.155       -         
+pcount_cry[10]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[11]     CCU2C        CIN      In      0.000     3.155       -         
+sll_inst.pcount_cry_0[11]     CCU2C        COUT     Out     0.061     3.216       -         
+pcount_cry[12]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[13]     CCU2C        CIN      In      0.000     3.216       -         
+sll_inst.pcount_cry_0[13]     CCU2C        COUT     Out     0.061     3.277       -         
+pcount_cry[14]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[15]     CCU2C        CIN      In      0.000     3.277       -         
+sll_inst.pcount_cry_0[15]     CCU2C        COUT     Out     0.061     3.338       -         
+pcount_cry[16]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[17]     CCU2C        CIN      In      0.000     3.338       -         
+sll_inst.pcount_cry_0[17]     CCU2C        COUT     Out     0.061     3.399       -         
+pcount_cry[18]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[19]     CCU2C        CIN      In      0.000     3.399       -         
+sll_inst.pcount_cry_0[19]     CCU2C        COUT     Out     0.061     3.460       -         
+pcount_cry[20]                Net          -        -       -         -           1         
+sll_inst.pcount_s_0[21]       CCU2C        CIN      In      0.000     3.460       -         
+sll_inst.pcount_s_0[21]       CCU2C        S0       Out     0.698     4.157       -         
+pcount_s[21]                  Net          -        -       -         -           1         
+sll_inst.pcount[21]           FD1S3DX      D        In      0.000     4.157       -         
+============================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                                 Arrival          
+Instance      Reference     Type     Pin              Net              Time        Slack
+              Clock                                                                     
+----------------------------------------------------------------------------------------
+DCU0_inst     System        DCUA     CH0_FFS_RLOL     rx_cdr_lol_s     0.000       9.946
+DCU0_inst     System        DCUA     CH0_FFS_RLOS     rx_los_low_s     0.000       9.946
+========================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                              Starting                                           Required          
+Instance                      Reference     Type        Pin     Net              Time         Slack
+                              Clock                                                                
+---------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol_p1     System        FD1S3DX     D       rx_cdr_lol_s     9.946        9.946
+rsl_inst.genblk2\.rlos_p1     System        FD1S3DX     D       rx_los_low_s     9.946        9.946
+===================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      0.000
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 9.946
+
+    Number of logic level(s):                0
+    Starting point:                          DCU0_inst / CH0_FFS_RLOL
+    Ending point:                            rsl_inst.genblk2\.rlol_p1 / D
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+
+Instance / Net                            Pin              Pin               Arrival     No. of    
+Name                          Type        Name             Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------------------
+DCU0_inst                     DCUA        CH0_FFS_RLOL     Out     0.000     0.000       -         
+rx_cdr_lol_s                  Net         -                -       -         -           2         
+rsl_inst.genblk2\.rlol_p1     FD1S3DX     D                In      0.000     0.000       -         
+===================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 149MB peak: 150MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 149MB peak: 150MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 186 of 24288 (1%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+CCU2C:          99
+DCUA:           1
+FD1P3BX:        20
+FD1P3DX:        60
+FD1S3BX:        10
+FD1S3DX:        96
+GSR:            1
+INV:            3
+ORCALUT4:       116
+PFUMX:          2
+PUR:            1
+VHI:            6
+VLO:            6
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 34MB peak: 150MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Wed Apr 24 09:44:54 2019
+
+###########################################################]

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/dm/layer0.xdm b/gbe/cores/sgmii/sgmii_ecp5/syn_results/dm/layer0.xdm
new file mode 100644 (file)
index 0000000..96ecede
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/dm/layer0.xdm
@@ -0,0 +1,546 @@
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diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/run_options.txt b/gbe/cores/sgmii/sgmii_ecp5/syn_results/run_options.txt
new file mode 100644 (file)
index 0000000..5110194
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/run_options.txt
@@ -0,0 +1,76 @@
+#--  Synopsys, Inc.
+#--  Version M-2017.03L-SP1-1
+#--  Project file /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/run_options.txt
+#--  Written on Fri May 10 09:02:09 2019
+
+
+#project files
+add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd"
+add_file -verilog "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v"
+add_file -fpga_constraint "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.fdc"
+
+
+
+#implementation: "syn_results"
+impl -add syn_results -type fpga
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+
+#device options
+set_option -technology ecp5um
+set_option -part LFE5UM_25F
+set_option -package MG285C
+set_option -speed_grade -6
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -top_module "sgmii_ecp5"
+
+# hdl_compiler_options
+set_option -distributed_compile 0
+
+# mapper_without_write_options
+set_option -frequency 100
+set_option -srs_instrumentation 1
+
+# mapper_options
+set_option -write_verilog 1
+set_option -write_vhdl 1
+
+# Lattice XP
+set_option -maxfan 50
+set_option -disable_io_insertion 1
+set_option -retiming 0
+set_option -pipe 0
+set_option -forcegsr false
+set_option -fix_gated_and_generated_clocks 1
+set_option -rw_check_on_ram 1
+set_option -update_models_cp 0
+set_option -syn_edif_array_rename 1
+set_option -Write_declared_clocks_only 1
+
+# NFilter
+set_option -no_sequential_opt 0
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "./sgmii_ecp5.edn"
+
+#set log file 
+set_option log_file "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srf" 
+impl -active "syn_results"

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/scemi_cfg.txt b/gbe/cores/sgmii/sgmii_ecp5/syn_results/scemi_cfg.txt
new file mode 100644 (file)
index 0000000..868d437
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/scemi_cfg.txt
@@ -0,0 +1,3 @@
+## UMR3 MESSAGE PORT CONFIGURATION FILE
+## ************************************
+XTOR_DPI_MSG_PORT_UMR_ADDR_VERSION=0

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/scratchproject.prs b/gbe/cores/sgmii/sgmii_ecp5/syn_results/scratchproject.prs
new file mode 100644 (file)
index 0000000..1406dc9
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/scratchproject.prs
@@ -0,0 +1,74 @@
+#--  Synopsys, Inc.
+#--  Version M-2017.03L-SP1-1
+#--  Project file /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/scratchproject.prs
+
+#project files
+add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd"
+add_file -verilog "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v"
+add_file -fpga_constraint "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.fdc"
+
+
+
+#implementation: "syn_results"
+impl -add /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results -type fpga
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+
+#device options
+set_option -technology ecp5um
+set_option -part LFE5UM_25F
+set_option -package MG285C
+set_option -speed_grade -6
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -top_module "sgmii_ecp5"
+
+# hdl_compiler_options
+set_option -distributed_compile 0
+
+# mapper_without_write_options
+set_option -frequency 100
+set_option -srs_instrumentation 1
+
+# mapper_options
+set_option -write_verilog 1
+set_option -write_vhdl 1
+
+# Lattice XP
+set_option -maxfan 50
+set_option -disable_io_insertion 1
+set_option -retiming 0
+set_option -pipe 0
+set_option -forcegsr false
+set_option -fix_gated_and_generated_clocks 1
+set_option -rw_check_on_ram 1
+set_option -update_models_cp 0
+set_option -syn_edif_array_rename 1
+set_option -Write_declared_clocks_only 1
+
+# NFilter
+set_option -no_sequential_opt 0
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.edn"
+
+#set log file 
+set_option log_file "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srf" 
+impl -active "syn_results"

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.areasrr b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.areasrr
new file mode 100644 (file)
index 0000000..c3d63b8
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.areasrr
@@ -0,0 +1,97 @@
+----------------------------------------------------------------------
+Report for cell sgmii_ecp5.v1
+
+Register bits: 221 of 24288 (1%)
+PIC Latch:       0
+I/O cells:       0
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                              CCU2C      113       100.0
+                               DCUA        1       100.0
+                            FD1P3BX       20       100.0
+                            FD1P3DX       92       100.0
+                            FD1S3BX       12       100.0
+                            FD1S3DX       97       100.0
+                                GSR        1       100.0
+                                INV        3       100.0
+                           ORCALUT4      154       100.0
+                              PFUMX        2       100.0
+                                PUR        1       100.0
+                                VHI        6       100.0
+                                VLO        6       100.0
+SUB MODULES 
+          sgmii_ecp5rsl_core_Z2_layer1        1       100.0
+          sgmii_ecp5sll_core_Z1_layer1        1       100.0
+                            sync_0s        1       100.0
+                          sync_0s_0        1       100.0
+                          sync_0s_6        1       100.0
+                            
+                         TOTAL           513           
+----------------------------------------------------------------------
+Report for cell sgmii_ecp5rsl_core_Z2_layer1.netlist
+     Instance path:  rsl_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                              CCU2C       51        45.1
+                            FD1P3BX        4        20.0
+                            FD1P3DX       74        80.4
+                            FD1S3BX       12       100.0
+                            FD1S3DX       37        38.1
+                           ORCALUT4      100        64.9
+                              PFUMX        2       100.0
+                                VHI        1        16.7
+                                VLO        1        16.7
+                            
+                         TOTAL           282           
+----------------------------------------------------------------------
+Report for cell sgmii_ecp5sll_core_Z1_layer1.netlist
+     Instance path:  sll_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                              CCU2C       62        54.9
+                            FD1P3BX       16        80.0
+                            FD1P3DX       18        19.6
+                            FD1S3DX       60        61.9
+                                INV        3       100.0
+                           ORCALUT4       54        35.1
+                                VHI        4        66.7
+                                VLO        4        66.7
+SUB MODULES 
+                            sync_0s        1       100.0
+                          sync_0s_0        1       100.0
+                          sync_0s_6        1       100.0
+                            
+                         TOTAL           224           
+----------------------------------------------------------------------
+Report for cell sync_0s_0.netlist
+  Original Cell name sync_0s
+     Instance path:  sll_inst.pdiff_sync_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                            FD1S3DX        2         2.1
+                                VHI        1        16.7
+                                VLO        1        16.7
+                            
+                         TOTAL             4           
+----------------------------------------------------------------------
+Report for cell sync_0s_6.netlist
+  Original Cell name sync_0s
+     Instance path:  sll_inst.rtc_sync_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                            FD1S3DX        2         2.1
+                                VHI        1        16.7
+                                VLO        1        16.7
+                            
+                         TOTAL             4           
+----------------------------------------------------------------------
+Report for cell sync_0s.netlist
+  Original Cell name sync_0s
+     Instance path:  sll_inst.phb_sync_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                            FD1S3DX        2         2.1
+                                VHI        1        16.7
+                                VLO        1        16.7
+                            
+                         TOTAL             4           

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.fse b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.fse
new file mode 100644 (file)
index 0000000..cc147f0
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.fse
@@ -0,0 +1,12 @@
+
+fsm_encoding {61801018011} sequential
+
+fsm_state_encoding {61801018011} LPLL_LOSS_ST {00}
+
+fsm_state_encoding {61801018011} LPLL_PRELOSS_ST {01}
+
+fsm_state_encoding {61801018011} LPLL_PRELOCK_ST {10}
+
+fsm_state_encoding {61801018011} LPLL_LOCK_ST {11}
+
+fsm_registers {61801018011} {sll_state[1]}  {sll_state[0]} 

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.htm b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.htm
new file mode 100644 (file)
index 0000000..31d89ed
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.htm
@@ -0,0 +1,9 @@
+<html>
+ <head>
+ <title>syntmp/sgmii_ecp5_srr.htm log file</title>
+ </head>
+ <frameset cols="20%, 80%">
+ <frame src="syntmp/sgmii_ecp5_toc.htm" name="tocFrame" />
+                                <frame src="syntmp/sgmii_ecp5_srr.htm" name="srrFrame"/>
+</frameset>
+ </html>

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.prj b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.prj
new file mode 100644 (file)
index 0000000..7f5b1db
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.prj
@@ -0,0 +1,47 @@
+#-- Lattice Semiconductor Corporation Ltd.
+#-- Synplify OEM project file /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.prj
+#-- Written on Fri May 10 09:02:08 2019
+
+
+#device options
+set_option -technology ecp5um
+set_option -part LFE5UM-85F
+set_option -speed_grade 8
+
+#use verilog 2001 standard option
+set_option -vlog_std v2001
+
+#map options
+set_option -frequency 100
+set_option -fanout_limit 50
+set_option -disable_io_insertion true
+set_option -retiming false
+set_option -pipe false
+set_option -pipe false
+set_option -force_gsr false
+
+#simulation options
+set_option -write_verilog true
+set_option -write_vhdl true
+
+#timing analysis options
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#-- add_file options
+add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd"
+add_file -verilog -lib work "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v"
+add_file -constraint {"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.fdc"}
+
+#-- top module name
+set_option -top_module sgmii_ecp5
+
+#-- set result format/file last
+project -result_file "sgmii_ecp5.edn"
+
+#-- error message log file
+project -log_file sgmii_ecp5.srf
+
+#-- run Synplify with 'arrange VHDL file'
+project -run

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srd b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srd
new file mode 100644 (file)
index 0000000..bc01018
Binary files /dev/null and b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srd differ

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srf b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srf
new file mode 100644 (file)
index 0000000..4b5ec97
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srf
@@ -0,0 +1,1137 @@
+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
+#install: /home/soft/lattice/diamond/3.10_x64/synpbase
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Fri May 10 09:02:09 2019
+
+#Implementation: syn_results
+
+Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
+VHDL syntax check successful!
+File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd changed - recompiling
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Fri May 10 09:02:09 2019
+
+###########################################################]
+Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
+Verilog syntax check successful!
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Fri May 10 09:02:10 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
+File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd changed - recompiling
+File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling
+VHDL syntax check successful!
+File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd changed - recompiling
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1.
+Post processing for work.sgmii_ecp5.v1
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB)
+
+
+Process completed successfully.
+# Fri May 10 09:02:10 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
+Verilog syntax check successful!
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work.
+
+       PDATA_RST_VAL=32'b00000000000000000000000000000000
+   Generated name = sync_0s
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work.
+
+       PPROTOCOL=24'b010001110100001001000101
+       PLOL_SETTING=32'b00000000000000000000000000000000
+       PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100
+       PPCIE_MAX_RATE=24'b001100100010111000110101
+       PDIFF_VAL_LOCK=32'b00000000000000000000000000100111
+       PDIFF_VAL_UNLOCK=32'b00000000000000000000000001001110
+       PPCLK_TC=32'b00000000000000100000000000000000
+       PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000
+       PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000
+       PPCLK_DIV11_TC=32'b00000000000000000000000000000000
+       LPLL_LOSS_ST=2'b00
+       LPLL_PRELOSS_ST=2'b01
+       LPLL_PRELOCK_ST=2'b10
+       LPLL_LOCK_ST=2'b11
+       LRCLK_TC=16'b1111111111111111
+       LRCLK_TC_PUL_WIDTH=16'b0000000000110010
+       LHB_WAIT_CNT=8'b11111111
+       LPCLK_TC_0=32'b00000000000000001000000000000000
+       LPCLK_TC_1=32'b00000000000000010000000000000000
+       LPCLK_TC_2=32'b00000000000000100000000000000000
+       LPCLK_TC_3=32'b00000000000000101000000000000000
+       LPCLK_TC_4=32'b00000000000000010000000000000000
+       LPDIFF_LOCK_00=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_10=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_20=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_30=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_40=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_01=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_11=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_21=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_31=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_41=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_02=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_12=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_22=32'b00000000000000000000000011000100
+       LPDIFF_LOCK_32=32'b00000000000000000000000011110101
+       LPDIFF_LOCK_42=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_03=32'b00000000000000000000000010000011
+       LPDIFF_LOCK_13=32'b00000000000000000000000100000110
+       LPDIFF_LOCK_23=32'b00000000000000000000001000001100
+       LPDIFF_LOCK_33=32'b00000000000000000000001010001111
+       LPDIFF_LOCK_43=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011
+       LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110
+       LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010
+       LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001
+       LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111
+       LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000
+       LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000
+       LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000
+       LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100
+       LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001
+       LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010
+       LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111
+       LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001
+   Generated name = sgmii_ecp5sll_core_Z1_layer1
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment.
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work.
+
+       pnum_channels=32'b00000000000000000000000000000001
+       pprotocol=24'b010001110100001001000101
+       pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
+       pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_tx_rdy=32'b00000000000000000000101110111000
+       pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_rx_rdy=32'b00000000000000000000101110111000
+       wa_num_cycles=32'b00000000000000000000010000000000
+       dac_num_cycles=32'b00000000000000000000000000000011
+       lreset_pwidth=32'b00000000000000000000000000000011
+       lwait_b4_trst=32'b00000000000010111110101111000010
+       lwait_b4_trst_s=32'b00000000000000000000001100001101
+       lplol_cnt_width=32'b00000000000000000000000000010100
+       lwait_after_plol0=32'b00000000000000000000000000000100
+       lwait_b4_rrst=32'b00000000000000101100000000000000
+       lrrst_wait_width=32'b00000000000000000000000000010100
+       lwait_after_rrst=32'b00000000000011000011010100000000
+       lwait_b4_rrst_s=32'b00000000000000000000000111001100
+       lrlol_cnt_width=32'b00000000000000000000000000010011
+       lwait_after_lols=32'b00000000000000001100010000000000
+       lwait_after_lols_s=32'b00000000000000000000000010010110
+       llols_cnt_width=32'b00000000000000000000000000010010
+       lrdb_max=32'b00000000000000000000000000001111
+       ltxr_wait_width=32'b00000000000000000000000000001100
+       lrxr_wait_width=32'b00000000000000000000000000001100
+   Generated name = sgmii_ecp5rsl_core_Z2_layer1
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers.
+@N: CL201 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state.
+Extracted state machine for register sll_state
+State machine has 4 reachable states with original encodings of:
+   00
+   01
+   10
+   11
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB)
+
+
+Process completed successfully.
+# Fri May 10 09:02:10 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/layer0.srs changed - recompiling
+File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/layer1.srs changed - recompiling
+
+=======================================================================================
+For a summary of linker messages for components that did not bind, please see log file:
+@L: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.linkerlog
+=======================================================================================
+
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 09:02:11 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 09:02:11 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 09:02:12 2019
+
+###########################################################]
+# Fri May 10 09:02:12 2019
+
+Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.fdc
+@L: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt 
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt" file 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)
+
+@N: BN362 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances.
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist sgmii_ecp5
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+
+Clock Summary
+******************
+
+          Start                                 Requested     Requested     Clock        Clock                   Clock
+Level     Clock                                 Frequency     Period        Type         Group                   Load 
+----------------------------------------------------------------------------------------------------------------------
+0 -       System                                100.0 MHz     10.000        system       system_clkgroup         0    
+                                                                                                                      
+0 -       sgmii_ecp5|pll_refclki                100.0 MHz     10.000        inferred     Inferred_clkgroup_0     93   
+                                                                                                                      
+0 -       sgmii_ecp5|rxrefclk                   100.0 MHz     10.000        inferred     Inferred_clkgroup_1     77   
+                                                                                                                      
+0 -       sgmii_ecp5|tx_pclk_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_2     53   
+======================================================================================================================
+
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   10 -> 10
+   11 -> 11
+@N: MO225 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 144MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Fri May 10 09:02:13 2019
+
+###########################################################]
+# Fri May 10 09:02:13 2019
+
+Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   10 -> 10
+   11 -> 11
+@N: MO225 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":909:3:909:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":527:3:527:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] 
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 145MB)
+
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+   1           0h:00m:01s                   4.90ns              155 /       221
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+3 non-gated/non-generated clock tree(s) driving 221 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+============================================= Non-Gated/Non-Generated Clocks =============================================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                                   
+--------------------------------------------------------------------------------------------------------------------------
+@K:CKID0001       pll_refclki         port                   91         rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]
+@K:CKID0002       rxrefclk            port                   77         rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]
+@K:CKID0003       DCU0_inst           DCUA                   53         sll_inst.pcount[21]                               
+==========================================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 149MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 149MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.edn
+M-2017.03L-SP1-1
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 152MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 152MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":162:4:162:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"
+@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"
+@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk"
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Fri May 10 09:02:16 2019
+#
+
+
+Top view:               sgmii_ecp5
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.fdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 4.043
+
+                                      Requested     Estimated     Requested     Estimated               Clock        Clock              
+Starting Clock                        Frequency     Frequency     Period        Period        Slack     Type         Group              
+----------------------------------------------------------------------------------------------------------------------------------------
+sgmii_ecp5|pll_refclki                100.0 MHz     168.9 MHz     10.000        5.921         4.079     inferred     Inferred_clkgroup_0
+sgmii_ecp5|rxrefclk                   100.0 MHz     167.9 MHz     10.000        5.957         4.043     inferred     Inferred_clkgroup_1
+sgmii_ecp5|tx_pclk_inferred_clock     100.0 MHz     237.5 MHz     10.000        4.211         5.789     inferred     Inferred_clkgroup_2
+System                                100.0 MHz     840.7 MHz     10.000        1.190         8.810     system       system_clkgroup    
+========================================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                                                                |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+Starting                           Ending                             |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+System                             sgmii_ecp5|rxrefclk                |  10.000      8.811  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             System                             |  10.000      8.253  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             sgmii_ecp5|pll_refclki             |  10.000      4.079  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             sgmii_ecp5|tx_pclk_inferred_clock  |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|rxrefclk                System                             |  10.000      8.277  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|rxrefclk                sgmii_ecp5|rxrefclk                |  10.000      4.043  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|tx_pclk_inferred_clock  sgmii_ecp5|pll_refclki             |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|tx_pclk_inferred_clock  sgmii_ecp5|tx_pclk_inferred_clock  |  10.000      5.789  |  No paths    -      |  No paths    -      |  No paths    -    
+============================================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|pll_refclki
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                   Starting                                                        Arrival          
+Instance                           Reference                  Type        Pin     Net              Time        Slack
+                                   Clock                                                                            
+--------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[2]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[2]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[3]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[3]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[17]     sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[17]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[19]     sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[19]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[1]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[1]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[4]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[4]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[5]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[5]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[6]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[6]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[7]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[7]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[8]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[8]      0.907       4.684
+====================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                   Starting                                                          Required          
+Instance                           Reference                  Type        Pin     Net                Time         Slack
+                                   Clock                                                                               
+-----------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[19]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[19]     9.946        4.079
+rsl_inst.genblk1\.plol_cnt[17]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[17]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[18]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[18]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[15]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[15]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[16]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[16]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[13]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[13]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[14]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[14]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[11]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[11]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[12]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[12]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[9]      sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[9]      9.946        4.383
+=======================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.867
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.079
+
+    Number of logic level(s):                15
+    Starting point:                          rsl_inst.genblk1\.plol_cnt[2] / Q
+    Ending point:                            rsl_inst.genblk1\.plol_cnt[19] / D
+    The start point is clocked by            sgmii_ecp5|pll_refclki [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|pll_refclki [rising] on pin CK
+
+Instance / Net                                        Pin      Pin               Arrival     No. of    
+Name                                     Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[2]            FD1S3DX      Q        Out     0.907     0.907       -         
+plol_cnt[2]                              Net          -        -       -         -           2         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     Z        Out     0.606     1.513       -         
+un1_plol_cnt_tc_10                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     Z        Out     0.606     2.119       -         
+un1_plol_cnt_tc_14                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     Z        Out     0.762     2.881       -         
+un1_plol_cnt_tc                          Net          -        -       -         -           5         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     B        In      0.000     2.881       -         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     Z        Out     0.840     3.721       -         
+plol_cnt                                 Net          -        -       -         -           21        
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.721       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.621       -         
+plol_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.621       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.682       -         
+plol_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.682       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.743       -         
+plol_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.743       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.804       -         
+plol_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.804       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.865       -         
+plol_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.865       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.926       -         
+plol_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.926       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.987       -         
+plol_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.987       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.048       -         
+plol_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.048       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.109       -         
+plol_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.109       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        COUT     Out     0.061     5.170       -         
+plol_cnt_cry[18]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        CIN      In      0.000     5.170       -         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        S0       Out     0.698     5.867       -         
+plol_cnt_s[19]                           Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt[19]           FD1S3DX      D        In      0.000     5.867       -         
+=======================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|rxrefclk
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                    Starting                                                      Arrival          
+Instance                            Reference               Type        Pin     Net               Time        Slack
+                                    Clock                                                                          
+-------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rxs_rst           sgmii_ecp5|rxrefclk     FD1P3DX     Q       rxs_rst           1.015       4.043
+rsl_inst.genblk2\.rlol1_cnt[7]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[7]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[8]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[8]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[9]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[9]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[10]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[10]     0.907       4.136
+rsl_inst.genblk2\.rlols0_cnt[1]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[1]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[2]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[2]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[3]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[3]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[4]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[4]     0.907       4.170
+rsl_inst.genblk2\.rlol1_cnt[0]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[0]      0.907       4.742
+===================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                              Starting                                                         Required          
+Instance                                      Reference               Type        Pin     Net                  Time         Slack
+                                              Clock                                                                              
+---------------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[11]     9.946        4.043
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[9]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[9]      9.946        4.104
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[10]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[10]     9.946        4.104
+rsl_inst.genblk2\.rlol1_cnt[17]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[17]      9.946        4.136
+rsl_inst.genblk2\.rlol1_cnt[18]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[18]      9.946        4.136
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[7]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[7]      9.946        4.165
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[8]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[8]      9.946        4.165
+rsl_inst.genblk2\.rlols0_cnt[17]              sgmii_ecp5|rxrefclk     FD1P3DX     D       rlols0_cnt_s[17]     9.946        4.170
+rsl_inst.genblk2\.rlol1_cnt[15]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[15]      9.946        4.197
+rsl_inst.genblk2\.rlol1_cnt[16]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[16]      9.946        4.197
+=================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.902
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     4.043
+
+    Number of logic level(s):                11
+    Starting point:                          rsl_inst.genblk2\.rxs_rst / Q
+    Ending point:                            rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] / D
+    The start point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+
+Instance / Net                                                  Pin      Pin               Arrival     No. of    
+Name                                               Type         Name     Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rxs_rst                          FD1P3DX      Q        Out     1.015     1.015       -         
+rxs_rst                                            Net          -        -       -         -           6         
+rsl_inst.rdo_rx_serdes_rst_c_1[0]                  ORCALUT4     B        In      0.000     1.015       -         
+rsl_inst.rdo_rx_serdes_rst_c_1[0]                  ORCALUT4     Z        Out     0.708     1.723       -         
+rsl_rx_serdes_rst_c                                Net          -        -       -         -           3         
+rsl_inst.dual_or_rserd_rst                         ORCALUT4     A        In      0.000     1.723       -         
+rsl_inst.dual_or_rserd_rst                         ORCALUT4     Z        Out     0.798     2.521       -         
+dual_or_rserd_rst                                  Net          -        -       -         -           9         
+rsl_inst.rx_any_rst                                ORCALUT4     A        In      0.000     2.521       -         
+rsl_inst.rx_any_rst                                ORCALUT4     Z        Out     0.660     3.181       -         
+rx_any_rst                                         Net          -        -       -         -           2         
+rsl_inst.rx_any_rst_RNIFD021                       ORCALUT4     A        In      0.000     3.181       -         
+rsl_inst.rx_any_rst_RNIFD021                       ORCALUT4     Z        Out     0.819     4.000       -         
+rxr_wt_cnt9                                        Net          -        -       -         -           14        
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0]     CCU2C        A1       In      0.000     4.000       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0]     CCU2C        COUT     Out     0.900     4.900       -         
+rxr_wt_cnt_cry[0]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1]     CCU2C        CIN      In      0.000     4.900       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1]     CCU2C        COUT     Out     0.061     4.961       -         
+rxr_wt_cnt_cry[2]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3]     CCU2C        CIN      In      0.000     4.961       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3]     CCU2C        COUT     Out     0.061     5.022       -         
+rxr_wt_cnt_cry[4]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5]     CCU2C        CIN      In      0.000     5.022       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5]     CCU2C        COUT     Out     0.061     5.083       -         
+rxr_wt_cnt_cry[6]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7]     CCU2C        CIN      In      0.000     5.083       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7]     CCU2C        COUT     Out     0.061     5.144       -         
+rxr_wt_cnt_cry[8]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9]     CCU2C        CIN      In      0.000     5.144       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9]     CCU2C        COUT     Out     0.061     5.205       -         
+rxr_wt_cnt_cry[10]                                 Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11]      CCU2C        CIN      In      0.000     5.205       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11]      CCU2C        S0       Out     0.698     5.902       -         
+rxr_wt_cnt_s[11]                                   Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11]          FD1P3DX      D        In      0.000     5.902       -         
+=================================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|tx_pclk_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                            Starting                                                                   Arrival          
+Instance                    Reference                             Type        Pin     Net              Time        Slack
+                            Clock                                                                                       
+------------------------------------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1       sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p1     1.098       5.789
+sll_inst.ppul_sync_p2       sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p2     1.098       5.789
+sll_inst.pcount_diff[0]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_0      0.985       6.147
+sll_inst.pcount[0]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[0]        0.955       6.178
+sll_inst.pcount_diff[1]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_1      0.955       6.239
+sll_inst.pcount_diff[2]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_2      0.955       6.239
+sll_inst.pcount[1]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[1]        0.907       6.287
+sll_inst.pcount[2]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[2]        0.907       6.287
+sll_inst.pcount_diff[3]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_3      0.955       6.300
+sll_inst.pcount_diff[4]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_4      0.955       6.300
+========================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                             Starting                                                                                  Required          
+Instance                     Reference                             Type        Pin     Net                             Time         Slack
+                             Clock                                                                                                       
+-----------------------------------------------------------------------------------------------------------------------------------------
+sll_inst.pcount[21]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[21]                    9.946        5.789
+sll_inst.pcount[19]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[19]                    9.946        5.850
+sll_inst.pcount[20]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[20]                    9.946        5.850
+sll_inst.pcount[17]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[17]                    9.946        5.911
+sll_inst.pcount[18]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[18]                    9.946        5.911
+sll_inst.pcount[15]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[15]                    9.946        5.972
+sll_inst.pcount[16]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[16]                    9.946        5.972
+sll_inst.pcount[13]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[13]                    9.946        6.033
+sll_inst.pcount[14]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[14]                    9.946        6.033
+sll_inst.pcount_diff[21]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3DX     D       un1_pcount_diff_1_s_21_0_S0     9.946        6.034
+=========================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      4.157
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 5.789
+
+    Number of logic level(s):                13
+    Starting point:                          sll_inst.ppul_sync_p1 / Q
+    Ending point:                            sll_inst.pcount[21] / D
+    The start point is clocked by            sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
+
+Instance / Net                             Pin      Pin               Arrival     No. of    
+Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1         FD1S3DX      Q        Out     1.098     1.098       -         
+ppul_sync_p1                  Net          -        -       -         -           25        
+sll_inst.pcount10_0_o3        ORCALUT4     A        In      0.000     1.098       -         
+sll_inst.pcount10_0_o3        ORCALUT4     Z        Out     0.851     1.950       -         
+N_8                           Net          -        -       -         -           25        
+sll_inst.pcount_cry_0[0]      CCU2C        A1       In      0.000     1.950       -         
+sll_inst.pcount_cry_0[0]      CCU2C        COUT     Out     0.900     2.850       -         
+pcount_cry[0]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[1]      CCU2C        CIN      In      0.000     2.850       -         
+sll_inst.pcount_cry_0[1]      CCU2C        COUT     Out     0.061     2.911       -         
+pcount_cry[2]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[3]      CCU2C        CIN      In      0.000     2.911       -         
+sll_inst.pcount_cry_0[3]      CCU2C        COUT     Out     0.061     2.972       -         
+pcount_cry[4]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[5]      CCU2C        CIN      In      0.000     2.972       -         
+sll_inst.pcount_cry_0[5]      CCU2C        COUT     Out     0.061     3.033       -         
+pcount_cry[6]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[7]      CCU2C        CIN      In      0.000     3.033       -         
+sll_inst.pcount_cry_0[7]      CCU2C        COUT     Out     0.061     3.094       -         
+pcount_cry[8]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[9]      CCU2C        CIN      In      0.000     3.094       -         
+sll_inst.pcount_cry_0[9]      CCU2C        COUT     Out     0.061     3.155       -         
+pcount_cry[10]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[11]     CCU2C        CIN      In      0.000     3.155       -         
+sll_inst.pcount_cry_0[11]     CCU2C        COUT     Out     0.061     3.216       -         
+pcount_cry[12]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[13]     CCU2C        CIN      In      0.000     3.216       -         
+sll_inst.pcount_cry_0[13]     CCU2C        COUT     Out     0.061     3.277       -         
+pcount_cry[14]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[15]     CCU2C        CIN      In      0.000     3.277       -         
+sll_inst.pcount_cry_0[15]     CCU2C        COUT     Out     0.061     3.338       -         
+pcount_cry[16]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[17]     CCU2C        CIN      In      0.000     3.338       -         
+sll_inst.pcount_cry_0[17]     CCU2C        COUT     Out     0.061     3.399       -         
+pcount_cry[18]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[19]     CCU2C        CIN      In      0.000     3.399       -         
+sll_inst.pcount_cry_0[19]     CCU2C        COUT     Out     0.061     3.460       -         
+pcount_cry[20]                Net          -        -       -         -           1         
+sll_inst.pcount_s_0[21]       CCU2C        CIN      In      0.000     3.460       -         
+sll_inst.pcount_s_0[21]       CCU2C        S0       Out     0.698     4.157       -         
+pcount_s[21]                  Net          -        -       -         -           1         
+sll_inst.pcount[21]           FD1S3DX      D        In      0.000     4.157       -         
+============================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                                 Arrival          
+Instance      Reference     Type     Pin              Net              Time        Slack
+              Clock                                                                     
+----------------------------------------------------------------------------------------
+DCU0_inst     System        DCUA     CH0_FFS_RLOL     rx_cdr_lol_s     0.000       8.810
+DCU0_inst     System        DCUA     CH0_FFS_RLOS     rx_los_low_s     0.000       8.810
+========================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                       Starting                                                            Required          
+Instance                                               Reference     Type        Pin     Net                               Time         Slack
+                                                       Clock                                                                                 
+---------------------------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     SP      un2_rdo_serdes_rst_dual_c_2_i     9.806        8.810
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     D       rxpr_appd_RNO[0]                  9.946        9.556
+rsl_inst.genblk2\.rlol_p1                              System        FD1S3DX     D       rx_cdr_lol_s                      9.946        9.946
+rsl_inst.genblk2\.rlos_p1                              System        FD1S3DX     D       rx_los_low_s                      9.946        9.946
+=============================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.194
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.806
+
+    - Propagation time:                      0.996
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 8.810
+
+    Number of logic level(s):                2
+    Starting point:                          DCU0_inst / CH0_FFS_RLOL
+    Ending point:                            rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+
+Instance / Net                                                            Pin              Pin               Arrival     No. of    
+Name                                                         Type         Name             Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------------------------------------------------------
+DCU0_inst                                                    DCUA         CH0_FFS_RLOL     Out     0.000     0.000       -         
+rx_cdr_lol_s                                                 Net          -                -       -         -           4         
+rsl_inst.un2_rdo_serdes_rst_dual_c_1_1                       ORCALUT4     A                In      0.000     0.000       -         
+rsl_inst.un2_rdo_serdes_rst_dual_c_1_1                       ORCALUT4     Z                Out     0.606     0.606       -         
+un2_rdo_serdes_rst_dual_c_1_1                                Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0]     ORCALUT4     B                In      0.000     0.606       -         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0]     ORCALUT4     Z                Out     0.390     0.996       -         
+un2_rdo_serdes_rst_dual_c_2_i                                Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]           FD1P3DX      SP               In      0.000     0.996       -         
+===================================================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 221 of 24288 (1%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+CCU2C:          113
+DCUA:           1
+FD1P3BX:        20
+FD1P3DX:        92
+FD1S3BX:        12
+FD1S3DX:        97
+GSR:            1
+INV:            3
+ORCALUT4:       154
+PFUMX:          2
+PUR:            1
+VHI:            6
+VLO:            6
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 153MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Fri May 10 09:02:16 2019
+
+###########################################################]

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srm b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srm
new file mode 100644 (file)
index 0000000..fc1b683
Binary files /dev/null and b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srm differ

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr
new file mode 100644 (file)
index 0000000..4b5ec97
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr
@@ -0,0 +1,1137 @@
+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
+#install: /home/soft/lattice/diamond/3.10_x64/synpbase
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Fri May 10 09:02:09 2019
+
+#Implementation: syn_results
+
+Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
+VHDL syntax check successful!
+File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd changed - recompiling
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Fri May 10 09:02:09 2019
+
+###########################################################]
+Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
+Verilog syntax check successful!
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Fri May 10 09:02:10 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
+File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd changed - recompiling
+File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling
+VHDL syntax check successful!
+File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd changed - recompiling
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1.
+Post processing for work.sgmii_ecp5.v1
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB)
+
+
+Process completed successfully.
+# Fri May 10 09:02:10 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
+Verilog syntax check successful!
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work.
+
+       PDATA_RST_VAL=32'b00000000000000000000000000000000
+   Generated name = sync_0s
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work.
+
+       PPROTOCOL=24'b010001110100001001000101
+       PLOL_SETTING=32'b00000000000000000000000000000000
+       PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100
+       PPCIE_MAX_RATE=24'b001100100010111000110101
+       PDIFF_VAL_LOCK=32'b00000000000000000000000000100111
+       PDIFF_VAL_UNLOCK=32'b00000000000000000000000001001110
+       PPCLK_TC=32'b00000000000000100000000000000000
+       PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000
+       PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000
+       PPCLK_DIV11_TC=32'b00000000000000000000000000000000
+       LPLL_LOSS_ST=2'b00
+       LPLL_PRELOSS_ST=2'b01
+       LPLL_PRELOCK_ST=2'b10
+       LPLL_LOCK_ST=2'b11
+       LRCLK_TC=16'b1111111111111111
+       LRCLK_TC_PUL_WIDTH=16'b0000000000110010
+       LHB_WAIT_CNT=8'b11111111
+       LPCLK_TC_0=32'b00000000000000001000000000000000
+       LPCLK_TC_1=32'b00000000000000010000000000000000
+       LPCLK_TC_2=32'b00000000000000100000000000000000
+       LPCLK_TC_3=32'b00000000000000101000000000000000
+       LPCLK_TC_4=32'b00000000000000010000000000000000
+       LPDIFF_LOCK_00=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_10=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_20=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_30=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_40=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_01=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_11=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_21=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_31=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_41=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_02=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_12=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_22=32'b00000000000000000000000011000100
+       LPDIFF_LOCK_32=32'b00000000000000000000000011110101
+       LPDIFF_LOCK_42=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_03=32'b00000000000000000000000010000011
+       LPDIFF_LOCK_13=32'b00000000000000000000000100000110
+       LPDIFF_LOCK_23=32'b00000000000000000000001000001100
+       LPDIFF_LOCK_33=32'b00000000000000000000001010001111
+       LPDIFF_LOCK_43=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011
+       LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110
+       LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010
+       LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001
+       LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111
+       LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000
+       LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000
+       LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000
+       LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100
+       LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001
+       LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010
+       LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111
+       LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001
+   Generated name = sgmii_ecp5sll_core_Z1_layer1
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment.
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work.
+
+       pnum_channels=32'b00000000000000000000000000000001
+       pprotocol=24'b010001110100001001000101
+       pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
+       pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_tx_rdy=32'b00000000000000000000101110111000
+       pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_rx_rdy=32'b00000000000000000000101110111000
+       wa_num_cycles=32'b00000000000000000000010000000000
+       dac_num_cycles=32'b00000000000000000000000000000011
+       lreset_pwidth=32'b00000000000000000000000000000011
+       lwait_b4_trst=32'b00000000000010111110101111000010
+       lwait_b4_trst_s=32'b00000000000000000000001100001101
+       lplol_cnt_width=32'b00000000000000000000000000010100
+       lwait_after_plol0=32'b00000000000000000000000000000100
+       lwait_b4_rrst=32'b00000000000000101100000000000000
+       lrrst_wait_width=32'b00000000000000000000000000010100
+       lwait_after_rrst=32'b00000000000011000011010100000000
+       lwait_b4_rrst_s=32'b00000000000000000000000111001100
+       lrlol_cnt_width=32'b00000000000000000000000000010011
+       lwait_after_lols=32'b00000000000000001100010000000000
+       lwait_after_lols_s=32'b00000000000000000000000010010110
+       llols_cnt_width=32'b00000000000000000000000000010010
+       lrdb_max=32'b00000000000000000000000000001111
+       ltxr_wait_width=32'b00000000000000000000000000001100
+       lrxr_wait_width=32'b00000000000000000000000000001100
+   Generated name = sgmii_ecp5rsl_core_Z2_layer1
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers.
+@N: CL201 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state.
+Extracted state machine for register sll_state
+State machine has 4 reachable states with original encodings of:
+   00
+   01
+   10
+   11
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB)
+
+
+Process completed successfully.
+# Fri May 10 09:02:10 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/layer0.srs changed - recompiling
+File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/layer1.srs changed - recompiling
+
+=======================================================================================
+For a summary of linker messages for components that did not bind, please see log file:
+@L: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.linkerlog
+=======================================================================================
+
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 09:02:11 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 09:02:11 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 09:02:12 2019
+
+###########################################################]
+# Fri May 10 09:02:12 2019
+
+Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.fdc
+@L: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt 
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt" file 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)
+
+@N: BN362 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances.
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist sgmii_ecp5
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+
+Clock Summary
+******************
+
+          Start                                 Requested     Requested     Clock        Clock                   Clock
+Level     Clock                                 Frequency     Period        Type         Group                   Load 
+----------------------------------------------------------------------------------------------------------------------
+0 -       System                                100.0 MHz     10.000        system       system_clkgroup         0    
+                                                                                                                      
+0 -       sgmii_ecp5|pll_refclki                100.0 MHz     10.000        inferred     Inferred_clkgroup_0     93   
+                                                                                                                      
+0 -       sgmii_ecp5|rxrefclk                   100.0 MHz     10.000        inferred     Inferred_clkgroup_1     77   
+                                                                                                                      
+0 -       sgmii_ecp5|tx_pclk_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_2     53   
+======================================================================================================================
+
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   10 -> 10
+   11 -> 11
+@N: MO225 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 144MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Fri May 10 09:02:13 2019
+
+###########################################################]
+# Fri May 10 09:02:13 2019
+
+Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   10 -> 10
+   11 -> 11
+@N: MO225 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":909:3:909:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":527:3:527:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] 
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 145MB)
+
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+   1           0h:00m:01s                   4.90ns              155 /       221
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+3 non-gated/non-generated clock tree(s) driving 221 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+============================================= Non-Gated/Non-Generated Clocks =============================================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                                   
+--------------------------------------------------------------------------------------------------------------------------
+@K:CKID0001       pll_refclki         port                   91         rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]
+@K:CKID0002       rxrefclk            port                   77         rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]
+@K:CKID0003       DCU0_inst           DCUA                   53         sll_inst.pcount[21]                               
+==========================================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 149MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 149MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.edn
+M-2017.03L-SP1-1
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 152MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 152MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":162:4:162:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"
+@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"
+@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk"
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Fri May 10 09:02:16 2019
+#
+
+
+Top view:               sgmii_ecp5
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.fdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 4.043
+
+                                      Requested     Estimated     Requested     Estimated               Clock        Clock              
+Starting Clock                        Frequency     Frequency     Period        Period        Slack     Type         Group              
+----------------------------------------------------------------------------------------------------------------------------------------
+sgmii_ecp5|pll_refclki                100.0 MHz     168.9 MHz     10.000        5.921         4.079     inferred     Inferred_clkgroup_0
+sgmii_ecp5|rxrefclk                   100.0 MHz     167.9 MHz     10.000        5.957         4.043     inferred     Inferred_clkgroup_1
+sgmii_ecp5|tx_pclk_inferred_clock     100.0 MHz     237.5 MHz     10.000        4.211         5.789     inferred     Inferred_clkgroup_2
+System                                100.0 MHz     840.7 MHz     10.000        1.190         8.810     system       system_clkgroup    
+========================================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                                                                |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+Starting                           Ending                             |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+System                             sgmii_ecp5|rxrefclk                |  10.000      8.811  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             System                             |  10.000      8.253  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             sgmii_ecp5|pll_refclki             |  10.000      4.079  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             sgmii_ecp5|tx_pclk_inferred_clock  |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|rxrefclk                System                             |  10.000      8.277  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|rxrefclk                sgmii_ecp5|rxrefclk                |  10.000      4.043  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|tx_pclk_inferred_clock  sgmii_ecp5|pll_refclki             |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|tx_pclk_inferred_clock  sgmii_ecp5|tx_pclk_inferred_clock  |  10.000      5.789  |  No paths    -      |  No paths    -      |  No paths    -    
+============================================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|pll_refclki
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                   Starting                                                        Arrival          
+Instance                           Reference                  Type        Pin     Net              Time        Slack
+                                   Clock                                                                            
+--------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[2]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[2]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[3]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[3]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[17]     sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[17]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[19]     sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[19]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[1]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[1]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[4]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[4]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[5]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[5]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[6]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[6]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[7]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[7]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[8]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[8]      0.907       4.684
+====================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                   Starting                                                          Required          
+Instance                           Reference                  Type        Pin     Net                Time         Slack
+                                   Clock                                                                               
+-----------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[19]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[19]     9.946        4.079
+rsl_inst.genblk1\.plol_cnt[17]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[17]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[18]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[18]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[15]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[15]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[16]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[16]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[13]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[13]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[14]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[14]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[11]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[11]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[12]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[12]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[9]      sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[9]      9.946        4.383
+=======================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.867
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.079
+
+    Number of logic level(s):                15
+    Starting point:                          rsl_inst.genblk1\.plol_cnt[2] / Q
+    Ending point:                            rsl_inst.genblk1\.plol_cnt[19] / D
+    The start point is clocked by            sgmii_ecp5|pll_refclki [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|pll_refclki [rising] on pin CK
+
+Instance / Net                                        Pin      Pin               Arrival     No. of    
+Name                                     Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[2]            FD1S3DX      Q        Out     0.907     0.907       -         
+plol_cnt[2]                              Net          -        -       -         -           2         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     Z        Out     0.606     1.513       -         
+un1_plol_cnt_tc_10                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     Z        Out     0.606     2.119       -         
+un1_plol_cnt_tc_14                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     Z        Out     0.762     2.881       -         
+un1_plol_cnt_tc                          Net          -        -       -         -           5         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     B        In      0.000     2.881       -         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     Z        Out     0.840     3.721       -         
+plol_cnt                                 Net          -        -       -         -           21        
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.721       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.621       -         
+plol_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.621       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.682       -         
+plol_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.682       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.743       -         
+plol_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.743       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.804       -         
+plol_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.804       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.865       -         
+plol_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.865       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.926       -         
+plol_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.926       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.987       -         
+plol_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.987       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.048       -         
+plol_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.048       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.109       -         
+plol_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.109       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        COUT     Out     0.061     5.170       -         
+plol_cnt_cry[18]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        CIN      In      0.000     5.170       -         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        S0       Out     0.698     5.867       -         
+plol_cnt_s[19]                           Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt[19]           FD1S3DX      D        In      0.000     5.867       -         
+=======================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|rxrefclk
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                    Starting                                                      Arrival          
+Instance                            Reference               Type        Pin     Net               Time        Slack
+                                    Clock                                                                          
+-------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rxs_rst           sgmii_ecp5|rxrefclk     FD1P3DX     Q       rxs_rst           1.015       4.043
+rsl_inst.genblk2\.rlol1_cnt[7]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[7]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[8]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[8]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[9]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[9]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[10]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[10]     0.907       4.136
+rsl_inst.genblk2\.rlols0_cnt[1]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[1]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[2]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[2]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[3]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[3]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[4]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[4]     0.907       4.170
+rsl_inst.genblk2\.rlol1_cnt[0]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[0]      0.907       4.742
+===================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                              Starting                                                         Required          
+Instance                                      Reference               Type        Pin     Net                  Time         Slack
+                                              Clock                                                                              
+---------------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[11]     9.946        4.043
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[9]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[9]      9.946        4.104
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[10]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[10]     9.946        4.104
+rsl_inst.genblk2\.rlol1_cnt[17]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[17]      9.946        4.136
+rsl_inst.genblk2\.rlol1_cnt[18]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[18]      9.946        4.136
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[7]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[7]      9.946        4.165
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[8]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[8]      9.946        4.165
+rsl_inst.genblk2\.rlols0_cnt[17]              sgmii_ecp5|rxrefclk     FD1P3DX     D       rlols0_cnt_s[17]     9.946        4.170
+rsl_inst.genblk2\.rlol1_cnt[15]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[15]      9.946        4.197
+rsl_inst.genblk2\.rlol1_cnt[16]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[16]      9.946        4.197
+=================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.902
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     4.043
+
+    Number of logic level(s):                11
+    Starting point:                          rsl_inst.genblk2\.rxs_rst / Q
+    Ending point:                            rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] / D
+    The start point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+
+Instance / Net                                                  Pin      Pin               Arrival     No. of    
+Name                                               Type         Name     Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rxs_rst                          FD1P3DX      Q        Out     1.015     1.015       -         
+rxs_rst                                            Net          -        -       -         -           6         
+rsl_inst.rdo_rx_serdes_rst_c_1[0]                  ORCALUT4     B        In      0.000     1.015       -         
+rsl_inst.rdo_rx_serdes_rst_c_1[0]                  ORCALUT4     Z        Out     0.708     1.723       -         
+rsl_rx_serdes_rst_c                                Net          -        -       -         -           3         
+rsl_inst.dual_or_rserd_rst                         ORCALUT4     A        In      0.000     1.723       -         
+rsl_inst.dual_or_rserd_rst                         ORCALUT4     Z        Out     0.798     2.521       -         
+dual_or_rserd_rst                                  Net          -        -       -         -           9         
+rsl_inst.rx_any_rst                                ORCALUT4     A        In      0.000     2.521       -         
+rsl_inst.rx_any_rst                                ORCALUT4     Z        Out     0.660     3.181       -         
+rx_any_rst                                         Net          -        -       -         -           2         
+rsl_inst.rx_any_rst_RNIFD021                       ORCALUT4     A        In      0.000     3.181       -         
+rsl_inst.rx_any_rst_RNIFD021                       ORCALUT4     Z        Out     0.819     4.000       -         
+rxr_wt_cnt9                                        Net          -        -       -         -           14        
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0]     CCU2C        A1       In      0.000     4.000       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0]     CCU2C        COUT     Out     0.900     4.900       -         
+rxr_wt_cnt_cry[0]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1]     CCU2C        CIN      In      0.000     4.900       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1]     CCU2C        COUT     Out     0.061     4.961       -         
+rxr_wt_cnt_cry[2]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3]     CCU2C        CIN      In      0.000     4.961       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3]     CCU2C        COUT     Out     0.061     5.022       -         
+rxr_wt_cnt_cry[4]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5]     CCU2C        CIN      In      0.000     5.022       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5]     CCU2C        COUT     Out     0.061     5.083       -         
+rxr_wt_cnt_cry[6]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7]     CCU2C        CIN      In      0.000     5.083       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7]     CCU2C        COUT     Out     0.061     5.144       -         
+rxr_wt_cnt_cry[8]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9]     CCU2C        CIN      In      0.000     5.144       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9]     CCU2C        COUT     Out     0.061     5.205       -         
+rxr_wt_cnt_cry[10]                                 Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11]      CCU2C        CIN      In      0.000     5.205       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11]      CCU2C        S0       Out     0.698     5.902       -         
+rxr_wt_cnt_s[11]                                   Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11]          FD1P3DX      D        In      0.000     5.902       -         
+=================================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|tx_pclk_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                            Starting                                                                   Arrival          
+Instance                    Reference                             Type        Pin     Net              Time        Slack
+                            Clock                                                                                       
+------------------------------------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1       sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p1     1.098       5.789
+sll_inst.ppul_sync_p2       sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p2     1.098       5.789
+sll_inst.pcount_diff[0]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_0      0.985       6.147
+sll_inst.pcount[0]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[0]        0.955       6.178
+sll_inst.pcount_diff[1]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_1      0.955       6.239
+sll_inst.pcount_diff[2]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_2      0.955       6.239
+sll_inst.pcount[1]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[1]        0.907       6.287
+sll_inst.pcount[2]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[2]        0.907       6.287
+sll_inst.pcount_diff[3]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_3      0.955       6.300
+sll_inst.pcount_diff[4]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_4      0.955       6.300
+========================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                             Starting                                                                                  Required          
+Instance                     Reference                             Type        Pin     Net                             Time         Slack
+                             Clock                                                                                                       
+-----------------------------------------------------------------------------------------------------------------------------------------
+sll_inst.pcount[21]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[21]                    9.946        5.789
+sll_inst.pcount[19]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[19]                    9.946        5.850
+sll_inst.pcount[20]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[20]                    9.946        5.850
+sll_inst.pcount[17]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[17]                    9.946        5.911
+sll_inst.pcount[18]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[18]                    9.946        5.911
+sll_inst.pcount[15]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[15]                    9.946        5.972
+sll_inst.pcount[16]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[16]                    9.946        5.972
+sll_inst.pcount[13]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[13]                    9.946        6.033
+sll_inst.pcount[14]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[14]                    9.946        6.033
+sll_inst.pcount_diff[21]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3DX     D       un1_pcount_diff_1_s_21_0_S0     9.946        6.034
+=========================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      4.157
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 5.789
+
+    Number of logic level(s):                13
+    Starting point:                          sll_inst.ppul_sync_p1 / Q
+    Ending point:                            sll_inst.pcount[21] / D
+    The start point is clocked by            sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
+
+Instance / Net                             Pin      Pin               Arrival     No. of    
+Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1         FD1S3DX      Q        Out     1.098     1.098       -         
+ppul_sync_p1                  Net          -        -       -         -           25        
+sll_inst.pcount10_0_o3        ORCALUT4     A        In      0.000     1.098       -         
+sll_inst.pcount10_0_o3        ORCALUT4     Z        Out     0.851     1.950       -         
+N_8                           Net          -        -       -         -           25        
+sll_inst.pcount_cry_0[0]      CCU2C        A1       In      0.000     1.950       -         
+sll_inst.pcount_cry_0[0]      CCU2C        COUT     Out     0.900     2.850       -         
+pcount_cry[0]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[1]      CCU2C        CIN      In      0.000     2.850       -         
+sll_inst.pcount_cry_0[1]      CCU2C        COUT     Out     0.061     2.911       -         
+pcount_cry[2]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[3]      CCU2C        CIN      In      0.000     2.911       -         
+sll_inst.pcount_cry_0[3]      CCU2C        COUT     Out     0.061     2.972       -         
+pcount_cry[4]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[5]      CCU2C        CIN      In      0.000     2.972       -         
+sll_inst.pcount_cry_0[5]      CCU2C        COUT     Out     0.061     3.033       -         
+pcount_cry[6]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[7]      CCU2C        CIN      In      0.000     3.033       -         
+sll_inst.pcount_cry_0[7]      CCU2C        COUT     Out     0.061     3.094       -         
+pcount_cry[8]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[9]      CCU2C        CIN      In      0.000     3.094       -         
+sll_inst.pcount_cry_0[9]      CCU2C        COUT     Out     0.061     3.155       -         
+pcount_cry[10]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[11]     CCU2C        CIN      In      0.000     3.155       -         
+sll_inst.pcount_cry_0[11]     CCU2C        COUT     Out     0.061     3.216       -         
+pcount_cry[12]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[13]     CCU2C        CIN      In      0.000     3.216       -         
+sll_inst.pcount_cry_0[13]     CCU2C        COUT     Out     0.061     3.277       -         
+pcount_cry[14]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[15]     CCU2C        CIN      In      0.000     3.277       -         
+sll_inst.pcount_cry_0[15]     CCU2C        COUT     Out     0.061     3.338       -         
+pcount_cry[16]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[17]     CCU2C        CIN      In      0.000     3.338       -         
+sll_inst.pcount_cry_0[17]     CCU2C        COUT     Out     0.061     3.399       -         
+pcount_cry[18]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[19]     CCU2C        CIN      In      0.000     3.399       -         
+sll_inst.pcount_cry_0[19]     CCU2C        COUT     Out     0.061     3.460       -         
+pcount_cry[20]                Net          -        -       -         -           1         
+sll_inst.pcount_s_0[21]       CCU2C        CIN      In      0.000     3.460       -         
+sll_inst.pcount_s_0[21]       CCU2C        S0       Out     0.698     4.157       -         
+pcount_s[21]                  Net          -        -       -         -           1         
+sll_inst.pcount[21]           FD1S3DX      D        In      0.000     4.157       -         
+============================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                                 Arrival          
+Instance      Reference     Type     Pin              Net              Time        Slack
+              Clock                                                                     
+----------------------------------------------------------------------------------------
+DCU0_inst     System        DCUA     CH0_FFS_RLOL     rx_cdr_lol_s     0.000       8.810
+DCU0_inst     System        DCUA     CH0_FFS_RLOS     rx_los_low_s     0.000       8.810
+========================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                       Starting                                                            Required          
+Instance                                               Reference     Type        Pin     Net                               Time         Slack
+                                                       Clock                                                                                 
+---------------------------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     SP      un2_rdo_serdes_rst_dual_c_2_i     9.806        8.810
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     D       rxpr_appd_RNO[0]                  9.946        9.556
+rsl_inst.genblk2\.rlol_p1                              System        FD1S3DX     D       rx_cdr_lol_s                      9.946        9.946
+rsl_inst.genblk2\.rlos_p1                              System        FD1S3DX     D       rx_los_low_s                      9.946        9.946
+=============================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.194
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.806
+
+    - Propagation time:                      0.996
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 8.810
+
+    Number of logic level(s):                2
+    Starting point:                          DCU0_inst / CH0_FFS_RLOL
+    Ending point:                            rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+
+Instance / Net                                                            Pin              Pin               Arrival     No. of    
+Name                                                         Type         Name             Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------------------------------------------------------
+DCU0_inst                                                    DCUA         CH0_FFS_RLOL     Out     0.000     0.000       -         
+rx_cdr_lol_s                                                 Net          -                -       -         -           4         
+rsl_inst.un2_rdo_serdes_rst_dual_c_1_1                       ORCALUT4     A                In      0.000     0.000       -         
+rsl_inst.un2_rdo_serdes_rst_dual_c_1_1                       ORCALUT4     Z                Out     0.606     0.606       -         
+un2_rdo_serdes_rst_dual_c_1_1                                Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0]     ORCALUT4     B                In      0.000     0.606       -         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0]     ORCALUT4     Z                Out     0.390     0.996       -         
+un2_rdo_serdes_rst_dual_c_2_i                                Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]           FD1P3DX      SP               In      0.000     0.996       -         
+===================================================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 221 of 24288 (1%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+CCU2C:          113
+DCUA:           1
+FD1P3BX:        20
+FD1P3DX:        92
+FD1S3BX:        12
+FD1S3DX:        97
+GSR:            1
+INV:            3
+ORCALUT4:       154
+PFUMX:          2
+PUR:            1
+VHI:            6
+VLO:            6
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 153MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Fri May 10 09:02:16 2019
+
+###########################################################]

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr.db b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr.db
new file mode 100644 (file)
index 0000000..8868cb2
Binary files /dev/null and b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr.db differ

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srs b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srs
new file mode 100644 (file)
index 0000000..ba6320d
Binary files /dev/null and b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srs differ

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.vhm b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.vhm
new file mode 100644 (file)
index 0000000..bbff63b
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.vhm
@@ -0,0 +1,6445 @@
+--
+-- Written by Synplicity
+-- Product Version "M-2017.03L-SP1-1"
+-- Program "Synplify Pro", Mapper "maplat, Build 1796R"
+-- Fri May 10 09:02:16 2019
+--
+
+--
+-- Written by Synplify Pro version Build 1796R
+-- Fri May 10 09:02:16 2019
+--
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library synplify;
+use synplify.components.all;
+library pmi;
+use pmi.pmi_components.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity sync_0s_0 is
+port(
+  ppul_sync :  in std_logic;
+  pdiff_sync :  out std_logic;
+  sli_rst :  in std_logic;
+  pll_refclki :  in std_logic);
+end sync_0s_0;
+
+architecture beh of sync_0s_0 is
+  signal DATA_P1 : std_logic ;
+  signal DATA_P2_QN_1 : std_logic ;
+  signal VCC : std_logic ;
+  signal DATA_P1_QN_1 : std_logic ;
+  signal GND : std_logic ;
+begin
+DATA_P2_REG_Z10: FD1S3DX port map (
+    D => DATA_P1,
+    CK => pll_refclki,
+    CD => sli_rst,
+    Q => pdiff_sync);
+DATA_P1_REG_Z12: FD1S3DX port map (
+    D => ppul_sync,
+    CK => pll_refclki,
+    CD => sli_rst,
+    Q => DATA_P1);
+VCC_0: VHI port map (
+    Z => VCC);
+II_GND: VLO port map (
+    Z => GND);
+end beh;
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library synplify;
+use synplify.components.all;
+library pmi;
+use pmi.pmi_components.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity sync_0s_6 is
+port(
+rtc_pul :  in std_logic;
+ppul_sync :  out std_logic;
+sli_rst :  in std_logic;
+tx_pclk :  in std_logic);
+end sync_0s_6;
+
+architecture beh of sync_0s_6 is
+signal DATA_P1 : std_logic ;
+signal DATA_P2_QN : std_logic ;
+signal VCC : std_logic ;
+signal DATA_P1_QN : std_logic ;
+signal GND : std_logic ;
+begin
+DATA_P2_REG_Z10: FD1S3DX port map (
+  D => DATA_P1,
+  CK => tx_pclk,
+  CD => sli_rst,
+  Q => ppul_sync);
+DATA_P1_REG_Z12: FD1S3DX port map (
+  D => rtc_pul,
+  CK => tx_pclk,
+  CD => sli_rst,
+  Q => DATA_P1);
+VCC_0: VHI port map (
+  Z => VCC);
+II_GND: VLO port map (
+  Z => GND);
+end beh;
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library synplify;
+use synplify.components.all;
+library pmi;
+use pmi.pmi_components.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity sync_0s is
+port(
+phb :  in std_logic;
+rhb_sync :  out std_logic;
+sli_rst :  in std_logic;
+pll_refclki :  in std_logic);
+end sync_0s;
+
+architecture beh of sync_0s is
+signal DATA_P1 : std_logic ;
+signal DATA_P2_QN_0 : std_logic ;
+signal VCC : std_logic ;
+signal DATA_P1_QN_0 : std_logic ;
+signal GND : std_logic ;
+begin
+DATA_P2_REG_Z10: FD1S3DX port map (
+D => DATA_P1,
+CK => pll_refclki,
+CD => sli_rst,
+Q => rhb_sync);
+DATA_P1_REG_Z12: FD1S3DX port map (
+D => phb,
+CK => pll_refclki,
+CD => sli_rst,
+Q => DATA_P1);
+VCC_0: VHI port map (
+Z => VCC);
+II_GND: VLO port map (
+Z => GND);
+end beh;
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library synplify;
+use synplify.components.all;
+library pmi;
+use pmi.pmi_components.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity sgmii_ecp5rsl_core_Z2_layer1 is
+port(
+rx_pcs_rst_c :  in std_logic;
+tx_pcs_rst_c :  in std_logic;
+tx_serdes_rst_c :  in std_logic;
+serdes_rst_dual_c :  in std_logic;
+rsl_tx_pcs_rst_c :  out std_logic;
+rsl_rx_serdes_rst_c :  out std_logic;
+rsl_serdes_rst_dual_c :  out std_logic;
+rsl_tx_serdes_rst_c :  out std_logic;
+rsl_tx_rdy :  out std_logic;
+pll_lock_i :  in std_logic;
+pll_refclki :  in std_logic;
+rsl_rx_rdy :  out std_logic;
+rsl_rst :  in std_logic;
+rxrefclk :  in std_logic;
+rsl_disable :  in std_logic;
+rx_serdes_rst_c :  in std_logic;
+rsl_rx_pcs_rst_c :  out std_logic;
+rst_dual_c :  in std_logic;
+rx_cdr_lol_s :  in std_logic;
+rx_los_low_s :  in std_logic);
+end sgmii_ecp5rsl_core_Z2_layer1;
+
+architecture beh of sgmii_ecp5rsl_core_Z2_layer1 is
+signal RXS_CNT : std_logic_vector(1 downto 0);
+signal RXS_CNT_3 : std_logic_vector(1 downto 0);
+signal RXPR_APPD_RNO : std_logic_vector(0 to 0);
+signal PLOL0_CNT : std_logic_vector(2 downto 0);
+signal PLOL0_CNT_3 : std_logic_vector(2 downto 0);
+signal RXSR_APPD : std_logic_vector(0 to 0);
+signal RXS_CNT_QN : std_logic_vector(1 downto 0);
+signal RLOS_DB_CNT : std_logic_vector(3 downto 0);
+signal RLOS_DB_CNT_QN : std_logic_vector(3 downto 0);
+signal RLOLS0_CNT_S : std_logic_vector(17 downto 0);
+signal RLOLS0_CNT : std_logic_vector(17 downto 0);
+signal RLOLS0_CNT_QN : std_logic_vector(17 downto 0);
+signal RLOL_DB_CNT : std_logic_vector(3 downto 0);
+signal RLOL_DB_CNT_QN : std_logic_vector(3 downto 0);
+signal RLOL1_CNT_S : std_logic_vector(18 downto 0);
+signal RLOL1_CNT : std_logic_vector(18 downto 0);
+signal RLOL1_CNT_QN : std_logic_vector(18 downto 0);
+signal RXR_WT_CNT_S : std_logic_vector(11 downto 0);
+signal RXR_WT_CNT : std_logic_vector(11 downto 0);
+signal RXR_WT_CNT_QN : std_logic_vector(11 downto 0);
+signal RXSR_APPD_QN : std_logic_vector(0 to 0);
+signal RXPR_APPD : std_logic_vector(0 to 0);
+signal RXPR_APPD_QN : std_logic_vector(0 to 0);
+signal TXS_CNT : std_logic_vector(1 downto 0);
+signal TXS_CNT_QN : std_logic_vector(1 downto 0);
+signal TXS_CNT_RNO : std_logic_vector(1 to 1);
+signal TXP_CNT : std_logic_vector(1 downto 0);
+signal TXP_CNT_QN : std_logic_vector(1 downto 0);
+signal TXP_CNT_RNO : std_logic_vector(1 to 1);
+signal PLOL_CNT_S : std_logic_vector(19 downto 0);
+signal PLOL_CNT : std_logic_vector(19 downto 0);
+signal PLOL_CNT_QN : std_logic_vector(19 downto 0);
+signal PLOL0_CNT_QN : std_logic_vector(2 downto 0);
+signal TXR_WT_CNT_S : std_logic_vector(11 downto 0);
+signal TXR_WT_CNT : std_logic_vector(11 downto 0);
+signal TXR_WT_CNT_QN : std_logic_vector(11 downto 0);
+signal TXPR_APPD : std_logic_vector(0 to 0);
+signal TXPR_APPD_QN : std_logic_vector(0 to 0);
+signal UN1_RLOL_DB_CNT_ZERO : std_logic_vector(0 to 0);
+signal UN1_RLOS_DB_CNT_ZERO : std_logic_vector(0 to 0);
+signal UN1_RLOL_DB_CNT_ZERO_BM : std_logic_vector(0 to 0);
+signal UN1_RLOL_DB_CNT_ZERO_AM : std_logic_vector(0 to 0);
+signal UN1_RLOS_DB_CNT_ZERO_BM : std_logic_vector(0 to 0);
+signal UN1_RLOS_DB_CNT_ZERO_AM : std_logic_vector(0 to 0);
+signal RLOL1_CNT_CRY : std_logic_vector(16 downto 0);
+signal RLOL1_CNT_CRY_0_S0 : std_logic_vector(0 to 0);
+signal RLOL1_CNT_CRY_0_COUT : std_logic_vector(17 to 17);
+signal RLOLS0_CNT_CRY : std_logic_vector(16 downto 0);
+signal RLOLS0_CNT_CRY_0_S0 : std_logic_vector(0 to 0);
+signal RLOLS0_CNT_S_0_COUT : std_logic_vector(17 to 17);
+signal RLOLS0_CNT_S_0_S1 : std_logic_vector(17 to 17);
+signal TXR_WT_CNT_CRY : std_logic_vector(10 downto 0);
+signal TXR_WT_CNT_CRY_0_S0 : std_logic_vector(0 to 0);
+signal TXR_WT_CNT_S_0_COUT : std_logic_vector(11 to 11);
+signal TXR_WT_CNT_S_0_S1 : std_logic_vector(11 to 11);
+signal RXR_WT_CNT_CRY : std_logic_vector(10 downto 0);
+signal RXR_WT_CNT_CRY_0_S0 : std_logic_vector(0 to 0);
+signal RXR_WT_CNT_S_0_COUT : std_logic_vector(11 to 11);
+signal RXR_WT_CNT_S_0_S1 : std_logic_vector(11 to 11);
+signal PLOL_CNT_CRY : std_logic_vector(18 downto 0);
+signal PLOL_CNT_CRY_0_S0 : std_logic_vector(0 to 0);
+signal PLOL_CNT_S_0_COUT : std_logic_vector(19 to 19);
+signal PLOL_CNT_S_0_S1 : std_logic_vector(19 to 19);
+signal RXS_RST : std_logic ;
+signal VCC : std_logic ;
+signal DUAL_OR_RSERD_RST : std_logic ;
+signal PLOL0_CNT9 : std_logic ;
+signal WAITA_PLOL0 : std_logic ;
+signal RLOS_DB_P1 : std_logic ;
+signal RLOS_DB : std_logic ;
+signal RXP_RST25 : std_logic ;
+signal RLOL_DB : std_logic ;
+signal UN1_RUI_RST_DUAL_C_1_1 : std_logic ;
+signal RX_ALL_WELL : std_logic ;
+signal RSL_RX_PCS_RST_C_10 : std_logic ;
+signal UN3_RX_ALL_WELL_2 : std_logic ;
+signal UN17_RXR_WT_TC : std_logic ;
+signal UN3_RX_ALL_WELL_1 : std_logic ;
+signal RX_ANY_RST : std_logic ;
+signal RXR_WT_CNT9 : std_logic ;
+signal UN1_RUI_RST_DUAL_C_1_I : std_logic ;
+signal RLOL1_CNT_TC_1 : std_logic ;
+signal \RLOL1_CNT_\ : std_logic ;
+signal RXR_WT_EN : std_logic ;
+signal RXR_WT_CNTE : std_logic ;
+signal RLOLS0_CNT_TC_1 : std_logic ;
+signal UN2_RLOS_REDGE_1_I : std_logic ;
+signal UN18_TXR_WT_TC : std_logic ;
+signal TX_ANY_RST : std_logic ;
+signal PLL_LOL_P2 : std_logic ;
+signal UN2_PLOL_FEDGE_5_I : std_logic ;
+signal N_2124_0 : std_logic ;
+signal WAITA_RLOLS06 : std_logic ;
+signal UN1_RLOLS0_CNT_TC : std_logic ;
+signal WAITA_RLOLS0 : std_logic ;
+signal WAITA_RLOLS0_QN : std_logic ;
+signal WAIT_CALIB_RNO : std_logic ;
+signal UN1_RLOS_FEDGE_1 : std_logic ;
+signal WAIT_CALIB : std_logic ;
+signal WAIT_CALIB_QN : std_logic ;
+signal RXS_RST6 : std_logic ;
+signal UN1_RXS_CNT_TC : std_logic ;
+signal RXS_RST_QN : std_logic ;
+signal RXP_RST2 : std_logic ;
+signal RXP_RST2_QN : std_logic ;
+signal RLOS_P1 : std_logic ;
+signal RLOS_P2 : std_logic ;
+signal RLOS_P2_QN : std_logic ;
+signal RLOS_P1_QN : std_logic ;
+signal RLOS_DB_P1_QN : std_logic ;
+signal RLOS_DB_CNT_AXB_0 : std_logic ;
+signal RLOS_DB_CNT_CRY_1_0_S0 : std_logic ;
+signal RLOS_DB_CNT_CRY_1_0_S1 : std_logic ;
+signal RLOS_DB_CNT_S_3_0_S0 : std_logic ;
+signal UN1_RLOS_DB_CNT_MAX : std_logic ;
+signal RLOS_DB_QN : std_logic ;
+signal RLOLS0_CNTE : std_logic ;
+signal RLOL_P1 : std_logic ;
+signal RLOL_P2 : std_logic ;
+signal RLOL_P2_QN : std_logic ;
+signal RLOL_P1_QN : std_logic ;
+signal RLOL_DB_P1 : std_logic ;
+signal RLOL_DB_P1_QN : std_logic ;
+signal RLOL_DB_CNT_AXB_0 : std_logic ;
+signal RLOL_DB_CNT_CRY_1_0_S0 : std_logic ;
+signal RLOL_DB_CNT_CRY_1_0_S1 : std_logic ;
+signal RLOL_DB_CNT_S_3_0_S0 : std_logic ;
+signal UN1_RLOL_DB_CNT_MAX : std_logic ;
+signal RLOL_DB_QN : std_logic ;
+signal RLOL1_CNTE : std_logic ;
+signal RXSDR_APPD_2 : std_logic ;
+signal RXSDR_APPD : std_logic ;
+signal RXSDR_APPD_QN : std_logic ;
+signal UN1_DUAL_OR_RSERD_RST_2_I : std_logic ;
+signal RXR_WT_EN_QN : std_logic ;
+signal RXDPR_APPD : std_logic ;
+signal RXDPR_APPD_QN : std_logic ;
+signal RSL_RX_RDY_9 : std_logic ;
+signal RUO_RX_RDYR_QN : std_logic ;
+signal UN2_RDO_SERDES_RST_DUAL_C_2_I : std_logic ;
+signal PLOL_FEDGE : std_logic ;
+signal UN1_PLOL0_CNT_TC_1_I : std_logic ;
+signal WAITA_PLOL0_QN : std_logic ;
+signal UN1_PLOL_CNT_TC : std_logic ;
+signal UN2_PLOL_CNT_TC : std_logic ;
+signal TXS_RST : std_logic ;
+signal TXS_RST_QN : std_logic ;
+signal N_10_I : std_logic ;
+signal UN9_PLOL0_CNT_TC : std_logic ;
+signal UN1_PLOL0_CNT_TC_1 : std_logic ;
+signal TXP_RST : std_logic ;
+signal TXP_RST_QN : std_logic ;
+signal N_11_I : std_logic ;
+signal PLL_LOL_P3 : std_logic ;
+signal PLL_LOL_P3_QN : std_logic ;
+signal PLL_LOL_P1 : std_logic ;
+signal PLL_LOL_P2_QN : std_logic ;
+signal PLL_LOL_P1_QN : std_logic ;
+signal TXSR_APPD_2 : std_logic ;
+signal TXSR_APPD : std_logic ;
+signal TXSR_APPD_QN : std_logic ;
+signal UN1_DUAL_OR_SERD_RST_1_1 : std_logic ;
+signal UN1_DUAL_OR_SERD_RST_1_I : std_logic ;
+signal TXR_WT_EN : std_logic ;
+signal TXR_WT_EN_QN : std_logic ;
+signal TXR_WT_CNTE : std_logic ;
+signal UN2_PLOL_FEDGE_2 : std_logic ;
+signal UN2_PLOL_FEDGE_3_I : std_logic ;
+signal TXDPR_APPD : std_logic ;
+signal TXDPR_APPD_QN : std_logic ;
+signal UN2_PLOL_FEDGE_5_1 : std_logic ;
+signal RSL_TX_RDY_8 : std_logic ;
+signal RUO_TX_RDYR_QN : std_logic ;
+signal UN2_PLOL_FEDGE_8_I : std_logic ;
+signal RLOS_REDGE : std_logic ;
+signal RLOLS0_CNT11_0 : std_logic ;
+signal RSL_TX_SERDES_RST_C_7 : std_logic ;
+signal \PLOL_CNT_\ : std_logic ;
+signal \RLOLS0_CNT_\ : std_logic ;
+signal UN8_RXS_CNT_TC : std_logic ;
+signal UN1_TXSR_APPD : std_logic ;
+signal RSL_SERDES_RST_DUAL_C_6 : std_logic ;
+signal UN3_RX_ALL_WELL_2_1 : std_logic ;
+signal UN1_RXSDR_OR_SR_APPD : std_logic ;
+signal UN2_RDO_SERDES_RST_DUAL_C_1_1 : std_logic ;
+signal RSL_RX_SERDES_RST_C_5 : std_logic ;
+signal RLOLS0_CNT_TC_1_10 : std_logic ;
+signal RLOLS0_CNT_TC_1_11 : std_logic ;
+signal RLOLS0_CNT_TC_1_12 : std_logic ;
+signal RLOLS0_CNT_TC_1_13 : std_logic ;
+signal UN1_PLOL_CNT_TC_11 : std_logic ;
+signal UN1_PLOL_CNT_TC_12 : std_logic ;
+signal UN1_PLOL_CNT_TC_13 : std_logic ;
+signal UN1_PLOL_CNT_TC_14 : std_logic ;
+signal RLOL1_CNT_TC_1_11 : std_logic ;
+signal RLOL1_CNT_TC_1_12 : std_logic ;
+signal RLOL1_CNT_TC_1_13 : std_logic ;
+signal RLOL1_CNT_TC_1_14 : std_logic ;
+signal TXSR_APPD_4 : std_logic ;
+signal RSL_TX_PCS_RST_C_4 : std_logic ;
+signal CO0_2 : std_logic ;
+signal UN18_TXR_WT_TC_6 : std_logic ;
+signal UN18_TXR_WT_TC_7 : std_logic ;
+signal UN18_TXR_WT_TC_8 : std_logic ;
+signal UN17_RXR_WT_TC_6 : std_logic ;
+signal UN17_RXR_WT_TC_7 : std_logic ;
+signal UN17_RXR_WT_TC_8 : std_logic ;
+signal RXSDR_APPD_4 : std_logic ;
+signal RLOLS0_CNT_TC_1_9 : std_logic ;
+signal UN1_PLOL_CNT_TC_10 : std_logic ;
+signal RLOL1_CNT_TC_1_10 : std_logic ;
+signal \TXR_WT_CNT_\ : std_logic ;
+signal RLOS_DB_CNT_CRY_0 : std_logic ;
+signal RLOS_DB_CNT_CRY_0_0_S0 : std_logic ;
+signal RLOS_DB_CNT_CRY_0_0_S1 : std_logic ;
+signal RLOS_DB_CNT_CRY_2 : std_logic ;
+signal RLOS_DB_CNT_S_3_0_COUT : std_logic ;
+signal RLOS_DB_CNT_S_3_0_S1 : std_logic ;
+signal RLOL_DB_CNT_CRY_0 : std_logic ;
+signal RLOL_DB_CNT_CRY_0_0_S0 : std_logic ;
+signal RLOL_DB_CNT_CRY_0_0_S1 : std_logic ;
+signal RLOL_DB_CNT_CRY_2 : std_logic ;
+signal RLOL_DB_CNT_S_3_0_COUT : std_logic ;
+signal RLOL_DB_CNT_S_3_0_S1 : std_logic ;
+signal GND : std_logic ;
+signal N_1 : std_logic ;
+signal N_2 : std_logic ;
+signal N_3 : std_logic ;
+signal N_4 : std_logic ;
+signal N_5 : std_logic ;
+signal N_6 : std_logic ;
+signal N_7 : std_logic ;
+begin
+\GENBLK2.RXS_CNT_RNO[0]\: LUT4 
+generic map(
+  init => X"2626"
+)
+port map (
+A => RXS_RST,
+B => RXS_CNT(0),
+C => RXS_CNT(1),
+D => VCC,
+Z => RXS_CNT_3(0));
+\GENBLK2.GENBLK3.LFOR[0].RXPR_APPD_RNO[0]\: LUT4 
+generic map(
+  init => X"0101"
+)
+port map (
+A => DUAL_OR_RSERD_RST,
+B => rx_los_low_s,
+C => rx_cdr_lol_s,
+D => VCC,
+Z => RXPR_APPD_RNO(0));
+\GENBLK1.PLOL0_CNT_RNO[1]\: LUT4 
+generic map(
+  init => X"1222"
+)
+port map (
+A => PLOL0_CNT(1),
+B => PLOL0_CNT9,
+C => WAITA_PLOL0,
+D => PLOL0_CNT(0),
+Z => PLOL0_CNT_3(1));
+\GENBLK2.RXP_RST2_RNO\: LUT4 
+generic map(
+  init => X"BABA"
+)
+port map (
+A => DUAL_OR_RSERD_RST,
+B => RLOS_DB_P1,
+C => RLOS_DB,
+D => VCC,
+Z => RXP_RST25);
+\GENBLK2.GENBLK3.RXDPR_APPD_RNO\: LUT4 
+generic map(
+  init => X"0101"
+)
+port map (
+A => DUAL_OR_RSERD_RST,
+B => RLOS_DB,
+C => RLOL_DB,
+D => VCC,
+Z => UN1_RUI_RST_DUAL_C_1_1);
+\GENBLK2.GENBLK3.RUO_RX_RDYR_RNO\: LUT4 
+generic map(
+  init => X"0002"
+)
+port map (
+A => RX_ALL_WELL,
+B => rst_dual_c,
+C => RSL_RX_PCS_RST_C_10,
+D => DUAL_OR_RSERD_RST,
+Z => UN3_RX_ALL_WELL_2);
+\GENBLK2.GENBLK3.RXR_WT_EN_RNO\: LUT4 
+generic map(
+  init => X"0404"
+)
+port map (
+A => UN17_RXR_WT_TC,
+B => RX_ALL_WELL,
+C => DUAL_OR_RSERD_RST,
+D => VCC,
+Z => UN3_RX_ALL_WELL_1);
+RX_ANY_RST_RNIFD021: LUT4 
+generic map(
+  init => X"FFFE"
+)
+port map (
+A => RX_ANY_RST,
+B => UN17_RXR_WT_TC,
+C => RLOS_DB,
+D => RLOL_DB,
+Z => RXR_WT_CNT9);
+\GENBLK2.GENBLK3.RXDPR_APPD_RNO_0\: LUT4 
+generic map(
+  init => X"FBFB"
+)
+port map (
+A => rst_dual_c,
+B => RX_ALL_WELL,
+C => DUAL_OR_RSERD_RST,
+D => VCC,
+Z => UN1_RUI_RST_DUAL_C_1_I);
+\GENBLK2.RXS_RST_RNIS0OP\: LUT4 
+generic map(
+  init => X"1011"
+)
+port map (
+A => RLOL1_CNT_TC_1,
+B => RXS_RST,
+C => RLOS_DB_P1,
+D => RLOS_DB,
+Z => \RLOL1_CNT_\);
+\GENBLK2.GENBLK3.RXR_WT_EN_RNIQF0H1\: LUT4 
+generic map(
+  init => X"FFEF"
+)
+port map (
+A => RXR_WT_EN,
+B => RX_ANY_RST,
+C => RX_ALL_WELL,
+D => UN17_RXR_WT_TC,
+Z => RXR_WT_CNTE);
+\GENBLK2.RXP_RST2_RNO_0\: LUT4 
+generic map(
+  init => X"EFEE"
+)
+port map (
+A => RLOLS0_CNT_TC_1,
+B => DUAL_OR_RSERD_RST,
+C => RLOS_DB_P1,
+D => RLOS_DB,
+Z => UN2_RLOS_REDGE_1_I);
+\GENBLK1.GENBLK2.RUO_TX_RDYR_RNO\: LUT4 
+generic map(
+  init => X"FEFE"
+)
+port map (
+A => UN18_TXR_WT_TC,
+B => TX_ANY_RST,
+C => PLL_LOL_P2,
+D => VCC,
+Z => UN2_PLOL_FEDGE_5_I);
+\GENBLK2.GENBLK3.LFOR[0].RXSR_APPD_RNO[0]\: LUT4 
+generic map(
+  init => X"EEFE"
+)
+port map (
+A => RXSR_APPD(0),
+B => rx_serdes_rst_c,
+C => RXS_RST,
+D => rsl_disable,
+Z => N_2124_0);
+\GENBLK2.WAITA_RLOLS0_REG_Z618\: FD1P3DX port map (
+D => WAITA_RLOLS06,
+SP => UN1_RLOLS0_CNT_TC,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => WAITA_RLOLS0);
+\GENBLK2.WAIT_CALIB_REG_Z620\: FD1P3BX port map (
+D => WAIT_CALIB_RNO,
+SP => UN1_RLOS_FEDGE_1,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => WAIT_CALIB);
+\GENBLK2.RXS_RST_REG_Z622\: FD1P3DX port map (
+D => RXS_RST6,
+SP => UN1_RXS_CNT_TC,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXS_RST);
+\GENBLK2.RXS_CNT[0]_REG_Z624\: FD1S3DX port map (
+D => RXS_CNT_3(0),
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXS_CNT(0));
+\GENBLK2.RXS_CNT[1]_REG_Z626\: FD1S3DX port map (
+D => RXS_CNT_3(1),
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXS_CNT(1));
+\GENBLK2.RXP_RST2_REG_Z628\: FD1P3BX port map (
+D => RXP_RST25,
+SP => UN2_RLOS_REDGE_1_I,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RXP_RST2);
+\GENBLK2.RLOS_P2_REG_Z630\: FD1S3DX port map (
+D => RLOS_P1,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOS_P2);
+\GENBLK2.RLOS_P1_REG_Z632\: FD1S3DX port map (
+D => rx_los_low_s,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOS_P1);
+\GENBLK2.RLOS_DB_P1_REG_Z634\: FD1S3BX port map (
+D => RLOS_DB,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOS_DB_P1);
+\GENBLK2.RLOS_DB_CNT[0]_REG_Z636\: FD1S3BX port map (
+D => RLOS_DB_CNT_AXB_0,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOS_DB_CNT(0));
+\GENBLK2.RLOS_DB_CNT[1]_REG_Z638\: FD1S3BX port map (
+D => RLOS_DB_CNT_CRY_1_0_S0,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOS_DB_CNT(1));
+\GENBLK2.RLOS_DB_CNT[2]_REG_Z640\: FD1S3BX port map (
+D => RLOS_DB_CNT_CRY_1_0_S1,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOS_DB_CNT(2));
+\GENBLK2.RLOS_DB_CNT[3]_REG_Z642\: FD1S3BX port map (
+D => RLOS_DB_CNT_S_3_0_S0,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOS_DB_CNT(3));
+\GENBLK2.RLOS_DB_REG_Z644\: FD1P3BX port map (
+D => RLOS_DB_CNT(1),
+SP => UN1_RLOS_DB_CNT_MAX,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOS_DB);
+\GENBLK2.RLOLS0_CNT[0]_REG_Z646\: FD1P3DX port map (
+D => RLOLS0_CNT_S(0),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(0));
+\GENBLK2.RLOLS0_CNT[1]_REG_Z648\: FD1P3DX port map (
+D => RLOLS0_CNT_S(1),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(1));
+\GENBLK2.RLOLS0_CNT[2]_REG_Z650\: FD1P3DX port map (
+D => RLOLS0_CNT_S(2),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(2));
+\GENBLK2.RLOLS0_CNT[3]_REG_Z652\: FD1P3DX port map (
+D => RLOLS0_CNT_S(3),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(3));
+\GENBLK2.RLOLS0_CNT[4]_REG_Z654\: FD1P3DX port map (
+D => RLOLS0_CNT_S(4),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(4));
+\GENBLK2.RLOLS0_CNT[5]_REG_Z656\: FD1P3DX port map (
+D => RLOLS0_CNT_S(5),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(5));
+\GENBLK2.RLOLS0_CNT[6]_REG_Z658\: FD1P3DX port map (
+D => RLOLS0_CNT_S(6),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(6));
+\GENBLK2.RLOLS0_CNT[7]_REG_Z660\: FD1P3DX port map (
+D => RLOLS0_CNT_S(7),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(7));
+\GENBLK2.RLOLS0_CNT[8]_REG_Z662\: FD1P3DX port map (
+D => RLOLS0_CNT_S(8),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(8));
+\GENBLK2.RLOLS0_CNT[9]_REG_Z664\: FD1P3DX port map (
+D => RLOLS0_CNT_S(9),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(9));
+\GENBLK2.RLOLS0_CNT[10]_REG_Z666\: FD1P3DX port map (
+D => RLOLS0_CNT_S(10),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(10));
+\GENBLK2.RLOLS0_CNT[11]_REG_Z668\: FD1P3DX port map (
+D => RLOLS0_CNT_S(11),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(11));
+\GENBLK2.RLOLS0_CNT[12]_REG_Z670\: FD1P3DX port map (
+D => RLOLS0_CNT_S(12),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(12));
+\GENBLK2.RLOLS0_CNT[13]_REG_Z672\: FD1P3DX port map (
+D => RLOLS0_CNT_S(13),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(13));
+\GENBLK2.RLOLS0_CNT[14]_REG_Z674\: FD1P3DX port map (
+D => RLOLS0_CNT_S(14),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(14));
+\GENBLK2.RLOLS0_CNT[15]_REG_Z676\: FD1P3DX port map (
+D => RLOLS0_CNT_S(15),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(15));
+\GENBLK2.RLOLS0_CNT[16]_REG_Z678\: FD1P3DX port map (
+D => RLOLS0_CNT_S(16),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(16));
+\GENBLK2.RLOLS0_CNT[17]_REG_Z680\: FD1P3DX port map (
+D => RLOLS0_CNT_S(17),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(17));
+\GENBLK2.RLOL_P2_REG_Z682\: FD1S3DX port map (
+D => RLOL_P1,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL_P2);
+\GENBLK2.RLOL_P1_REG_Z684\: FD1S3DX port map (
+D => rx_cdr_lol_s,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL_P1);
+\GENBLK2.RLOL_DB_P1_REG_Z686\: FD1S3BX port map (
+D => RLOL_DB,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOL_DB_P1);
+\GENBLK2.RLOL_DB_CNT[0]_REG_Z688\: FD1S3BX port map (
+D => RLOL_DB_CNT_AXB_0,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOL_DB_CNT(0));
+\GENBLK2.RLOL_DB_CNT[1]_REG_Z690\: FD1S3BX port map (
+D => RLOL_DB_CNT_CRY_1_0_S0,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOL_DB_CNT(1));
+\GENBLK2.RLOL_DB_CNT[2]_REG_Z692\: FD1S3BX port map (
+D => RLOL_DB_CNT_CRY_1_0_S1,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOL_DB_CNT(2));
+\GENBLK2.RLOL_DB_CNT[3]_REG_Z694\: FD1S3BX port map (
+D => RLOL_DB_CNT_S_3_0_S0,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOL_DB_CNT(3));
+\GENBLK2.RLOL_DB_REG_Z696\: FD1P3BX port map (
+D => RLOL_DB_CNT(1),
+SP => UN1_RLOL_DB_CNT_MAX,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOL_DB);
+\GENBLK2.RLOL1_CNT[0]_REG_Z698\: FD1P3DX port map (
+D => RLOL1_CNT_S(0),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(0));
+\GENBLK2.RLOL1_CNT[1]_REG_Z700\: FD1P3DX port map (
+D => RLOL1_CNT_S(1),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(1));
+\GENBLK2.RLOL1_CNT[2]_REG_Z702\: FD1P3DX port map (
+D => RLOL1_CNT_S(2),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(2));
+\GENBLK2.RLOL1_CNT[3]_REG_Z704\: FD1P3DX port map (
+D => RLOL1_CNT_S(3),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(3));
+\GENBLK2.RLOL1_CNT[4]_REG_Z706\: FD1P3DX port map (
+D => RLOL1_CNT_S(4),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(4));
+\GENBLK2.RLOL1_CNT[5]_REG_Z708\: FD1P3DX port map (
+D => RLOL1_CNT_S(5),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(5));
+\GENBLK2.RLOL1_CNT[6]_REG_Z710\: FD1P3DX port map (
+D => RLOL1_CNT_S(6),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(6));
+\GENBLK2.RLOL1_CNT[7]_REG_Z712\: FD1P3DX port map (
+D => RLOL1_CNT_S(7),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(7));
+\GENBLK2.RLOL1_CNT[8]_REG_Z714\: FD1P3DX port map (
+D => RLOL1_CNT_S(8),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(8));
+\GENBLK2.RLOL1_CNT[9]_REG_Z716\: FD1P3DX port map (
+D => RLOL1_CNT_S(9),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(9));
+\GENBLK2.RLOL1_CNT[10]_REG_Z718\: FD1P3DX port map (
+D => RLOL1_CNT_S(10),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(10));
+\GENBLK2.RLOL1_CNT[11]_REG_Z720\: FD1P3DX port map (
+D => RLOL1_CNT_S(11),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(11));
+\GENBLK2.RLOL1_CNT[12]_REG_Z722\: FD1P3DX port map (
+D => RLOL1_CNT_S(12),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(12));
+\GENBLK2.RLOL1_CNT[13]_REG_Z724\: FD1P3DX port map (
+D => RLOL1_CNT_S(13),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(13));
+\GENBLK2.RLOL1_CNT[14]_REG_Z726\: FD1P3DX port map (
+D => RLOL1_CNT_S(14),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(14));
+\GENBLK2.RLOL1_CNT[15]_REG_Z728\: FD1P3DX port map (
+D => RLOL1_CNT_S(15),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(15));
+\GENBLK2.RLOL1_CNT[16]_REG_Z730\: FD1P3DX port map (
+D => RLOL1_CNT_S(16),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(16));
+\GENBLK2.RLOL1_CNT[17]_REG_Z732\: FD1P3DX port map (
+D => RLOL1_CNT_S(17),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(17));
+\GENBLK2.RLOL1_CNT[18]_REG_Z734\: FD1P3DX port map (
+D => RLOL1_CNT_S(18),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(18));
+\GENBLK2.GENBLK3.RXSDR_APPD_REG_Z736\: FD1S3BX port map (
+D => RXSDR_APPD_2,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RXSDR_APPD);
+\GENBLK2.GENBLK3.RXR_WT_EN_REG_Z738\: FD1P3DX port map (
+D => UN3_RX_ALL_WELL_1,
+SP => UN1_DUAL_OR_RSERD_RST_2_I,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_EN);
+\GENBLK2.GENBLK3.RXR_WT_CNT[0]_REG_Z740\: FD1P3DX port map (
+D => RXR_WT_CNT_S(0),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(0));
+\GENBLK2.GENBLK3.RXR_WT_CNT[1]_REG_Z742\: FD1P3DX port map (
+D => RXR_WT_CNT_S(1),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(1));
+\GENBLK2.GENBLK3.RXR_WT_CNT[2]_REG_Z744\: FD1P3DX port map (
+D => RXR_WT_CNT_S(2),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(2));
+\GENBLK2.GENBLK3.RXR_WT_CNT[3]_REG_Z746\: FD1P3DX port map (
+D => RXR_WT_CNT_S(3),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(3));
+\GENBLK2.GENBLK3.RXR_WT_CNT[4]_REG_Z748\: FD1P3DX port map (
+D => RXR_WT_CNT_S(4),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(4));
+\GENBLK2.GENBLK3.RXR_WT_CNT[5]_REG_Z750\: FD1P3DX port map (
+D => RXR_WT_CNT_S(5),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(5));
+\GENBLK2.GENBLK3.RXR_WT_CNT[6]_REG_Z752\: FD1P3DX port map (
+D => RXR_WT_CNT_S(6),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(6));
+\GENBLK2.GENBLK3.RXR_WT_CNT[7]_REG_Z754\: FD1P3DX port map (
+D => RXR_WT_CNT_S(7),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(7));
+\GENBLK2.GENBLK3.RXR_WT_CNT[8]_REG_Z756\: FD1P3DX port map (
+D => RXR_WT_CNT_S(8),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(8));
+\GENBLK2.GENBLK3.RXR_WT_CNT[9]_REG_Z758\: FD1P3DX port map (
+D => RXR_WT_CNT_S(9),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(9));
+\GENBLK2.GENBLK3.RXR_WT_CNT[10]_REG_Z760\: FD1P3DX port map (
+D => RXR_WT_CNT_S(10),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(10));
+\GENBLK2.GENBLK3.RXR_WT_CNT[11]_REG_Z762\: FD1P3DX port map (
+D => RXR_WT_CNT_S(11),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(11));
+\GENBLK2.GENBLK3.RXDPR_APPD_REG_Z764\: FD1P3DX port map (
+D => UN1_RUI_RST_DUAL_C_1_1,
+SP => UN1_RUI_RST_DUAL_C_1_I,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXDPR_APPD);
+\GENBLK2.GENBLK3.RUO_RX_RDYR_REG_Z766\: FD1P3DX port map (
+D => UN3_RX_ALL_WELL_2,
+SP => RXR_WT_CNT9,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RSL_RX_RDY_9);
+\GENBLK2.GENBLK3.LFOR[0].RXSR_APPD[0]_REG_Z768\: FD1S3DX port map (
+D => N_2124_0,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXSR_APPD(0));
+\GENBLK2.GENBLK3.LFOR[0].RXPR_APPD[0]_REG_Z770\: FD1P3DX port map (
+D => RXPR_APPD_RNO(0),
+SP => UN2_RDO_SERDES_RST_DUAL_C_2_I,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXPR_APPD(0));
+\GENBLK1.WAITA_PLOL0_REG_Z772\: FD1P3DX port map (
+D => PLOL_FEDGE,
+SP => UN1_PLOL0_CNT_TC_1_I,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => WAITA_PLOL0);
+\GENBLK1.TXS_RST_REG_Z774\: FD1P3DX port map (
+D => UN1_PLOL_CNT_TC,
+SP => UN2_PLOL_CNT_TC,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXS_RST);
+\GENBLK1.TXS_CNT[0]_REG_Z776\: FD1S3DX port map (
+D => N_10_I,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXS_CNT(0));
+\GENBLK1.TXS_CNT[1]_REG_Z778\: FD1S3DX port map (
+D => TXS_CNT_RNO(1),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXS_CNT(1));
+\GENBLK1.TXP_RST_REG_Z780\: FD1P3DX port map (
+D => UN9_PLOL0_CNT_TC,
+SP => UN1_PLOL0_CNT_TC_1,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXP_RST);
+\GENBLK1.TXP_CNT[0]_REG_Z782\: FD1S3DX port map (
+D => N_11_I,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXP_CNT(0));
+\GENBLK1.TXP_CNT[1]_REG_Z784\: FD1S3DX port map (
+D => TXP_CNT_RNO(1),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXP_CNT(1));
+\GENBLK1.PLOL_CNT[0]_REG_Z786\: FD1S3DX port map (
+D => PLOL_CNT_S(0),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(0));
+\GENBLK1.PLOL_CNT[1]_REG_Z788\: FD1S3DX port map (
+D => PLOL_CNT_S(1),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(1));
+\GENBLK1.PLOL_CNT[2]_REG_Z790\: FD1S3DX port map (
+D => PLOL_CNT_S(2),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(2));
+\GENBLK1.PLOL_CNT[3]_REG_Z792\: FD1S3DX port map (
+D => PLOL_CNT_S(3),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(3));
+\GENBLK1.PLOL_CNT[4]_REG_Z794\: FD1S3DX port map (
+D => PLOL_CNT_S(4),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(4));
+\GENBLK1.PLOL_CNT[5]_REG_Z796\: FD1S3DX port map (
+D => PLOL_CNT_S(5),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(5));
+\GENBLK1.PLOL_CNT[6]_REG_Z798\: FD1S3DX port map (
+D => PLOL_CNT_S(6),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(6));
+\GENBLK1.PLOL_CNT[7]_REG_Z800\: FD1S3DX port map (
+D => PLOL_CNT_S(7),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(7));
+\GENBLK1.PLOL_CNT[8]_REG_Z802\: FD1S3DX port map (
+D => PLOL_CNT_S(8),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(8));
+\GENBLK1.PLOL_CNT[9]_REG_Z804\: FD1S3DX port map (
+D => PLOL_CNT_S(9),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(9));
+\GENBLK1.PLOL_CNT[10]_REG_Z806\: FD1S3DX port map (
+D => PLOL_CNT_S(10),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(10));
+\GENBLK1.PLOL_CNT[11]_REG_Z808\: FD1S3DX port map (
+D => PLOL_CNT_S(11),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(11));
+\GENBLK1.PLOL_CNT[12]_REG_Z810\: FD1S3DX port map (
+D => PLOL_CNT_S(12),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(12));
+\GENBLK1.PLOL_CNT[13]_REG_Z812\: FD1S3DX port map (
+D => PLOL_CNT_S(13),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(13));
+\GENBLK1.PLOL_CNT[14]_REG_Z814\: FD1S3DX port map (
+D => PLOL_CNT_S(14),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(14));
+\GENBLK1.PLOL_CNT[15]_REG_Z816\: FD1S3DX port map (
+D => PLOL_CNT_S(15),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(15));
+\GENBLK1.PLOL_CNT[16]_REG_Z818\: FD1S3DX port map (
+D => PLOL_CNT_S(16),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(16));
+\GENBLK1.PLOL_CNT[17]_REG_Z820\: FD1S3DX port map (
+D => PLOL_CNT_S(17),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(17));
+\GENBLK1.PLOL_CNT[18]_REG_Z822\: FD1S3DX port map (
+D => PLOL_CNT_S(18),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(18));
+\GENBLK1.PLOL_CNT[19]_REG_Z824\: FD1S3DX port map (
+D => PLOL_CNT_S(19),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(19));
+\GENBLK1.PLOL0_CNT[0]_REG_Z826\: FD1S3DX port map (
+D => PLOL0_CNT_3(0),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL0_CNT(0));
+\GENBLK1.PLOL0_CNT[1]_REG_Z828\: FD1S3DX port map (
+D => PLOL0_CNT_3(1),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL0_CNT(1));
+\GENBLK1.PLOL0_CNT[2]_REG_Z830\: FD1S3DX port map (
+D => PLOL0_CNT_3(2),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL0_CNT(2));
+\GENBLK1.PLL_LOL_P3_REG_Z832\: FD1S3DX port map (
+D => PLL_LOL_P2,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLL_LOL_P3);
+\GENBLK1.PLL_LOL_P2_REG_Z834\: FD1S3DX port map (
+D => PLL_LOL_P1,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLL_LOL_P2);
+\GENBLK1.PLL_LOL_P1_REG_Z836\: FD1S3DX port map (
+D => pll_lock_i,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLL_LOL_P1);
+\GENBLK1.GENBLK2.TXSR_APPD_REG_Z838\: FD1S3BX port map (
+D => TXSR_APPD_2,
+CK => pll_refclki,
+PD => rsl_rst,
+Q => TXSR_APPD);
+\GENBLK1.GENBLK2.TXR_WT_EN_REG_Z840\: FD1P3DX port map (
+D => UN1_DUAL_OR_SERD_RST_1_1,
+SP => UN1_DUAL_OR_SERD_RST_1_I,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_EN);
+\GENBLK1.GENBLK2.TXR_WT_CNT[0]_REG_Z842\: FD1P3DX port map (
+D => TXR_WT_CNT_S(0),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(0));
+\GENBLK1.GENBLK2.TXR_WT_CNT[1]_REG_Z844\: FD1P3DX port map (
+D => TXR_WT_CNT_S(1),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(1));
+\GENBLK1.GENBLK2.TXR_WT_CNT[2]_REG_Z846\: FD1P3DX port map (
+D => TXR_WT_CNT_S(2),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(2));
+\GENBLK1.GENBLK2.TXR_WT_CNT[3]_REG_Z848\: FD1P3DX port map (
+D => TXR_WT_CNT_S(3),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(3));
+\GENBLK1.GENBLK2.TXR_WT_CNT[4]_REG_Z850\: FD1P3DX port map (
+D => TXR_WT_CNT_S(4),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(4));
+\GENBLK1.GENBLK2.TXR_WT_CNT[5]_REG_Z852\: FD1P3DX port map (
+D => TXR_WT_CNT_S(5),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(5));
+\GENBLK1.GENBLK2.TXR_WT_CNT[6]_REG_Z854\: FD1P3DX port map (
+D => TXR_WT_CNT_S(6),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(6));
+\GENBLK1.GENBLK2.TXR_WT_CNT[7]_REG_Z856\: FD1P3DX port map (
+D => TXR_WT_CNT_S(7),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(7));
+\GENBLK1.GENBLK2.TXR_WT_CNT[8]_REG_Z858\: FD1P3DX port map (
+D => TXR_WT_CNT_S(8),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(8));
+\GENBLK1.GENBLK2.TXR_WT_CNT[9]_REG_Z860\: FD1P3DX port map (
+D => TXR_WT_CNT_S(9),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(9));
+\GENBLK1.GENBLK2.TXR_WT_CNT[10]_REG_Z862\: FD1P3DX port map (
+D => TXR_WT_CNT_S(10),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(10));
+\GENBLK1.GENBLK2.TXR_WT_CNT[11]_REG_Z864\: FD1P3DX port map (
+D => TXR_WT_CNT_S(11),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(11));
+\GENBLK1.GENBLK2.TXDPR_APPD_REG_Z866\: FD1P3DX port map (
+D => UN2_PLOL_FEDGE_2,
+SP => UN2_PLOL_FEDGE_3_I,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXDPR_APPD);
+\GENBLK1.GENBLK2.RUO_TX_RDYR_REG_Z868\: FD1P3DX port map (
+D => UN2_PLOL_FEDGE_5_1,
+SP => UN2_PLOL_FEDGE_5_I,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => RSL_TX_RDY_8);
+\GENBLK1.GENBLK2.MFOR[0].TXPR_APPD[0]_REG_Z870\: FD1P3DX port map (
+D => UN2_PLOL_FEDGE_2,
+SP => UN2_PLOL_FEDGE_8_I,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXPR_APPD(0));
+\GENBLK1.TXS_CNT_RNO[0]\: LUT4 
+generic map(
+  init => X"A6A6"
+)
+port map (
+A => TXS_CNT(0),
+B => TXS_RST,
+C => UN1_PLOL_CNT_TC,
+D => VCC,
+Z => N_10_I);
+\GENBLK1.TXS_CNT_RNO[1]\: LUT4 
+generic map(
+  init => X"CC6C"
+)
+port map (
+A => TXS_CNT(0),
+B => TXS_CNT(1),
+C => TXS_RST,
+D => UN1_PLOL_CNT_TC,
+Z => TXS_CNT_RNO(1));
+\GENBLK1.GENBLK2.TXR_WT_EN_RNO\: LUT4 
+generic map(
+  init => X"0F2F"
+)
+port map (
+A => TXPR_APPD(0),
+B => PLL_LOL_P2,
+C => UN1_DUAL_OR_SERD_RST_1_1,
+D => RSL_TX_RDY_8,
+Z => UN1_DUAL_OR_SERD_RST_1_I);
+\GENBLK2.RXS_RST6\: LUT4 
+generic map(
+  init => X"2020"
+)
+port map (
+A => RLOL_DB,
+B => RLOS_DB,
+C => RLOL1_CNT_TC_1,
+D => VCC,
+Z => RXS_RST6);
+\GENBLK2.WAIT_CALIB_RNIKRP81\: LUT4 
+generic map(
+  init => X"FFFE"
+)
+port map (
+A => RXS_RST,
+B => WAIT_CALIB,
+C => RLOL1_CNT_TC_1,
+D => RLOS_REDGE,
+Z => RLOL1_CNTE);
+\GENBLK2.WAITA_RLOLS0_RNI266C\: LUT4 
+generic map(
+  init => X"FEFE"
+)
+port map (
+A => RLOLS0_CNT11_0,
+B => WAITA_RLOLS0,
+C => RLOLS0_CNT_TC_1,
+D => VCC,
+Z => RLOLS0_CNTE);
+\GENBLK1.PLOL_CNT11_I\: LUT4 
+generic map(
+  init => X"0202"
+)
+port map (
+A => PLL_LOL_P2,
+B => UN1_PLOL_CNT_TC,
+C => RSL_TX_SERDES_RST_C_7,
+D => VCC,
+Z => \PLOL_CNT_\);
+\GENBLK2.RLOLS0_CNT11_I\: LUT4 
+generic map(
+  init => X"1111"
+)
+port map (
+A => RLOLS0_CNT11_0,
+B => RLOLS0_CNT_TC_1,
+C => VCC,
+D => VCC,
+Z => \RLOLS0_CNT_\);
+\GENBLK2.UN1_RXS_CNT_TC\: LUT4 
+generic map(
+  init => X"FEFC"
+)
+port map (
+A => RLOL_DB,
+B => RLOS_DB,
+C => UN8_RXS_CNT_TC,
+D => RLOL1_CNT_TC_1,
+Z => UN1_RXS_CNT_TC);
+\GENBLK2.WAIT_CALIB_RNO\: LUT4 
+generic map(
+  init => X"A3A3"
+)
+port map (
+A => RLOL_DB,
+B => RLOS_DB,
+C => RLOL1_CNT_TC_1,
+D => VCC,
+Z => WAIT_CALIB_RNO);
+\GENBLK1.GENBLK2.MFOR[0].TXPR_APPD_RNO[0]\: LUT4 
+generic map(
+  init => X"FFFE"
+)
+port map (
+A => UN1_TXSR_APPD,
+B => PLL_LOL_P2,
+C => RSL_SERDES_RST_DUAL_C_6,
+D => RSL_TX_SERDES_RST_C_7,
+Z => UN2_PLOL_FEDGE_8_I);
+\GENBLK2.GENBLK3.RXR_WT_EN_RNO_0\: LUT4 
+generic map(
+  init => X"FEFF"
+)
+port map (
+A => DUAL_OR_RSERD_RST,
+B => UN3_RX_ALL_WELL_2_1,
+C => UN17_RXR_WT_TC,
+D => RX_ALL_WELL,
+Z => UN1_DUAL_OR_RSERD_RST_2_I);
+\GENBLK2.GENBLK3.LFOR[0].RXPR_APPD_RNO_0[0]\: LUT4 
+generic map(
+  init => X"FFFB"
+)
+port map (
+A => UN1_RXSDR_OR_SR_APPD,
+B => UN2_RDO_SERDES_RST_DUAL_C_1_1,
+C => RSL_RX_SERDES_RST_C_5,
+D => RSL_SERDES_RST_DUAL_C_6,
+Z => UN2_RDO_SERDES_RST_DUAL_C_2_I);
+\GENBLK1.UN2_PLOL_CNT_TC\: LUT4 
+generic map(
+  init => X"F8F8"
+)
+port map (
+A => TXS_CNT(0),
+B => TXS_CNT(1),
+C => UN1_PLOL_CNT_TC,
+D => VCC,
+Z => UN2_PLOL_CNT_TC);
+\GENBLK1.GENBLK2.TXR_WT_EN_RNICEBT\: LUT4 
+generic map(
+  init => X"FEFE"
+)
+port map (
+A => TXR_WT_EN,
+B => UN18_TXR_WT_TC,
+C => TX_ANY_RST,
+D => VCC,
+Z => TXR_WT_CNTE);
+\GENBLK2.UN1_RLOS_FEDGE_1\: LUT4 
+generic map(
+  init => X"F6F6"
+)
+port map (
+A => RLOS_DB,
+B => RLOS_DB_P1,
+C => RLOL1_CNT_TC_1,
+D => VCC,
+Z => UN1_RLOS_FEDGE_1);
+\GENBLK2.UN1_RLOLS0_CNT_TC\: LUT4 
+generic map(
+  init => X"FEFE"
+)
+port map (
+A => RLOLS0_CNT11_0,
+B => WAITA_RLOLS06,
+C => RLOLS0_CNT_TC_1,
+D => VCC,
+Z => UN1_RLOLS0_CNT_TC);
+\GENBLK1.GENBLK2.TXDPR_APPD_RNO\: LUT4 
+generic map(
+  init => X"FFFE"
+)
+port map (
+A => PLL_LOL_P2,
+B => RSL_SERDES_RST_DUAL_C_6,
+C => RSL_TX_SERDES_RST_C_7,
+D => rst_dual_c,
+Z => UN2_PLOL_FEDGE_3_I);
+\GENBLK1.TXP_CNT_RNO[0]\: LUT4 
+generic map(
+  init => X"A6A6"
+)
+port map (
+A => TXP_CNT(0),
+B => TXP_RST,
+C => UN9_PLOL0_CNT_TC,
+D => VCC,
+Z => N_11_I);
+UN2_PLOL_FEDGE_5_1_Z890: LUT4 
+generic map(
+  init => X"1111"
+)
+port map (
+A => PLL_LOL_P2,
+B => TX_ANY_RST,
+C => VCC,
+D => VCC,
+Z => UN2_PLOL_FEDGE_5_1);
+UN1_DUAL_OR_SERD_RST_1_1_Z891: LUT4 
+generic map(
+  init => X"0101"
+)
+port map (
+A => UN18_TXR_WT_TC,
+B => RSL_SERDES_RST_DUAL_C_6,
+C => RSL_TX_SERDES_RST_C_7,
+D => VCC,
+Z => UN1_DUAL_OR_SERD_RST_1_1);
+\GENBLK1.TXP_CNT_RNO[1]\: LUT4 
+generic map(
+  init => X"CC6C"
+)
+port map (
+A => TXP_CNT(0),
+B => TXP_CNT(1),
+C => TXP_RST,
+D => UN9_PLOL0_CNT_TC,
+Z => TXP_CNT_RNO(1));
+RLOLS0_CNT_TC_1_Z893: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RLOLS0_CNT_TC_1_10,
+B => RLOLS0_CNT_TC_1_11,
+C => RLOLS0_CNT_TC_1_12,
+D => RLOLS0_CNT_TC_1_13,
+Z => RLOLS0_CNT_TC_1);
+\GENBLK1.UN1_PLOL_CNT_TC\: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => UN1_PLOL_CNT_TC_11,
+B => UN1_PLOL_CNT_TC_12,
+C => UN1_PLOL_CNT_TC_13,
+D => UN1_PLOL_CNT_TC_14,
+Z => UN1_PLOL_CNT_TC);
+RLOL1_CNT_TC_1_Z895: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RLOL1_CNT_TC_1_11,
+B => RLOL1_CNT_TC_1_12,
+C => RLOL1_CNT_TC_1_13,
+D => RLOL1_CNT_TC_1_14,
+Z => RLOL1_CNT_TC_1);
+\UN1_GENBLK2.RLOL_DB_CNT_AXB_0\: LUT4 
+generic map(
+  init => X"9999"
+)
+port map (
+A => RLOL_DB_CNT(0),
+B => UN1_RLOL_DB_CNT_ZERO(0),
+C => VCC,
+D => VCC,
+Z => RLOL_DB_CNT_AXB_0);
+\UN1_GENBLK2.RLOS_DB_CNT_AXB_0\: LUT4 
+generic map(
+  init => X"9999"
+)
+port map (
+A => RLOS_DB_CNT(0),
+B => UN1_RLOS_DB_CNT_ZERO(0),
+C => VCC,
+D => VCC,
+Z => RLOS_DB_CNT_AXB_0);
+\GENBLK1.WAITA_PLOL0_RNO\: LUT4 
+generic map(
+  init => X"F6F6"
+)
+port map (
+A => PLL_LOL_P2,
+B => PLL_LOL_P3,
+C => UN9_PLOL0_CNT_TC,
+D => VCC,
+Z => UN1_PLOL0_CNT_TC_1_I);
+\GENBLK1.GENBLK2.MFOR[0].UN1_TXSR_APPD\: LUT4 
+generic map(
+  init => X"C8C8"
+)
+port map (
+A => TXDPR_APPD,
+B => TXSR_APPD_4,
+C => RSL_TX_PCS_RST_C_4,
+D => VCC,
+Z => UN1_TXSR_APPD);
+\GENBLK1.GENBLK2.TXSR_APPD_2\: LUT4 
+generic map(
+  init => X"FEFE"
+)
+port map (
+A => TXSR_APPD_4,
+B => RSL_SERDES_RST_DUAL_C_6,
+C => RSL_TX_SERDES_RST_C_7,
+D => VCC,
+Z => TXSR_APPD_2);
+\GENBLK1.PLOL0_CNT_3[0]\: LUT4 
+generic map(
+  init => X"1414"
+)
+port map (
+A => PLOL0_CNT9,
+B => PLOL0_CNT(0),
+C => WAITA_PLOL0,
+D => VCC,
+Z => PLOL0_CNT_3(0));
+\GENBLK1.PLOL0_CNT_3[2]\: LUT4 
+generic map(
+  init => X"1320"
+)
+port map (
+A => CO0_2,
+B => PLOL0_CNT9,
+C => PLOL0_CNT(1),
+D => PLOL0_CNT(2),
+Z => PLOL0_CNT_3(2));
+\GENBLK1.GENBLK2.UN18_TXR_WT_TC\: LUT4 
+generic map(
+  init => X"8080"
+)
+port map (
+A => UN18_TXR_WT_TC_6,
+B => UN18_TXR_WT_TC_7,
+C => UN18_TXR_WT_TC_8,
+D => VCC,
+Z => UN18_TXR_WT_TC);
+UN2_PLOL_FEDGE_2_Z904: LUT4 
+generic map(
+  init => X"0101"
+)
+port map (
+A => PLL_LOL_P2,
+B => RSL_SERDES_RST_DUAL_C_6,
+C => RSL_TX_SERDES_RST_C_7,
+D => VCC,
+Z => UN2_PLOL_FEDGE_2);
+TX_ANY_RST_Z905: LUT4 
+generic map(
+  init => X"FFFE"
+)
+port map (
+A => RSL_SERDES_RST_DUAL_C_6,
+B => RSL_TX_PCS_RST_C_4,
+C => RSL_TX_SERDES_RST_C_7,
+D => rst_dual_c,
+Z => TX_ANY_RST);
+RX_ANY_RST_Z906: LUT4 
+generic map(
+  init => X"FEFE"
+)
+port map (
+A => DUAL_OR_RSERD_RST,
+B => RSL_RX_PCS_RST_C_10,
+C => rst_dual_c,
+D => VCC,
+Z => RX_ANY_RST);
+\GENBLK2.GENBLK3.UN17_RXR_WT_TC\: LUT4 
+generic map(
+  init => X"8080"
+)
+port map (
+A => UN17_RXR_WT_TC_6,
+B => UN17_RXR_WT_TC_7,
+C => UN17_RXR_WT_TC_8,
+D => VCC,
+Z => UN17_RXR_WT_TC);
+\UN1_RLOL_DB_CNT_ZERO_BM[0]_Z908\: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RLOL_DB_CNT(0),
+B => RLOL_DB_CNT(1),
+C => RLOL_DB_CNT(2),
+D => RLOL_DB_CNT(3),
+Z => UN1_RLOL_DB_CNT_ZERO_BM(0));
+\UN1_RLOL_DB_CNT_ZERO[0]_Z909\: PFUMX port map (
+ALUT => UN1_RLOL_DB_CNT_ZERO_BM(0),
+BLUT => UN1_RLOL_DB_CNT_ZERO_AM(0),
+C0 => RLOL_P2,
+Z => UN1_RLOL_DB_CNT_ZERO(0));
+\UN1_RLOS_DB_CNT_ZERO_BM[0]_Z910\: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RLOS_DB_CNT(0),
+B => RLOS_DB_CNT(1),
+C => RLOS_DB_CNT(2),
+D => RLOS_DB_CNT(3),
+Z => UN1_RLOS_DB_CNT_ZERO_BM(0));
+\UN1_RLOS_DB_CNT_ZERO[0]_Z911\: PFUMX port map (
+ALUT => UN1_RLOS_DB_CNT_ZERO_BM(0),
+BLUT => UN1_RLOS_DB_CNT_ZERO_AM(0),
+C0 => RLOS_P2,
+Z => UN1_RLOS_DB_CNT_ZERO(0));
+\GENBLK2.UN1_RLOL_DB_CNT_MAX\: LUT4 
+generic map(
+  init => X"8001"
+)
+port map (
+A => RLOL_DB_CNT(0),
+B => RLOL_DB_CNT(1),
+C => RLOL_DB_CNT(2),
+D => RLOL_DB_CNT(3),
+Z => UN1_RLOL_DB_CNT_MAX);
+\GENBLK2.UN1_RLOS_DB_CNT_MAX\: LUT4 
+generic map(
+  init => X"8001"
+)
+port map (
+A => RLOS_DB_CNT(0),
+B => RLOS_DB_CNT(1),
+C => RLOS_DB_CNT(2),
+D => RLOS_DB_CNT(3),
+Z => UN1_RLOS_DB_CNT_MAX);
+\GENBLK1.UN1_PLOL0_CNT_TC_1\: LUT4 
+generic map(
+  init => X"F8F8"
+)
+port map (
+A => TXP_CNT(0),
+B => TXP_CNT(1),
+C => UN9_PLOL0_CNT_TC,
+D => VCC,
+Z => UN1_PLOL0_CNT_TC_1);
+\GENBLK2.WAITA_RLOLS06\: LUT4 
+generic map(
+  init => X"0504"
+)
+port map (
+A => RLOL_DB,
+B => RLOL_DB_P1,
+C => RLOS_DB,
+D => RLOS_DB_P1,
+Z => WAITA_RLOLS06);
+\RXS_CNT_3[1]_Z916\: LUT4 
+generic map(
+  init => X"6464"
+)
+port map (
+A => RXS_CNT(0),
+B => RXS_CNT(1),
+C => RXS_RST,
+D => VCC,
+Z => RXS_CNT_3(1));
+\GENBLK2.GENBLK3.LFOR[0].UN1_RXSDR_OR_SR_APPD\: LUT4 
+generic map(
+  init => X"3200"
+)
+port map (
+A => RXSR_APPD(0),
+B => RX_ALL_WELL,
+C => RXSDR_APPD_4,
+D => RSL_RX_PCS_RST_C_10,
+Z => UN1_RXSDR_OR_SR_APPD);
+RLOLS0_CNT_TC_1_13_Z918: LUT4 
+generic map(
+  init => X"1010"
+)
+port map (
+A => RLOLS0_CNT(16),
+B => RLOLS0_CNT(17),
+C => RLOLS0_CNT_TC_1_9,
+D => VCC,
+Z => RLOLS0_CNT_TC_1_13);
+\GENBLK1.UN1_PLOL_CNT_TC_14\: LUT4 
+generic map(
+  init => X"0100"
+)
+port map (
+A => PLOL_CNT(4),
+B => PLOL_CNT(5),
+C => PLOL_CNT(18),
+D => UN1_PLOL_CNT_TC_10,
+Z => UN1_PLOL_CNT_TC_14);
+RLOL1_CNT_TC_1_14_Z920: LUT4 
+generic map(
+  init => X"0100"
+)
+port map (
+A => RLOL1_CNT(11),
+B => RLOL1_CNT(12),
+C => RLOL1_CNT(18),
+D => RLOL1_CNT_TC_1_10,
+Z => RLOL1_CNT_TC_1_14);
+\GENBLK2.GENBLK3.UN3_RX_ALL_WELL_2_1\: LUT4 
+generic map(
+  init => X"0E0E"
+)
+port map (
+A => RXPR_APPD(0),
+B => RXDPR_APPD,
+C => RSL_RX_RDY_9,
+D => VCC,
+Z => UN3_RX_ALL_WELL_2_1);
+RDO_SERDES_RST_DUAL_C: LUT4 
+generic map(
+  init => X"F4F4"
+)
+port map (
+A => rsl_disable,
+B => rsl_rst,
+C => serdes_rst_dual_c,
+D => VCC,
+Z => RSL_SERDES_RST_DUAL_C_6);
+RDO_TX_SERDES_RST_C: LUT4 
+generic map(
+  init => X"F4F4"
+)
+port map (
+A => rsl_disable,
+B => TXS_RST,
+C => tx_serdes_rst_c,
+D => VCC,
+Z => RSL_TX_SERDES_RST_C_7);
+\RDO_TX_PCS_RST_C_1[0]\: LUT4 
+generic map(
+  init => X"F4F4"
+)
+port map (
+A => rsl_disable,
+B => TXP_RST,
+C => tx_pcs_rst_c,
+D => VCC,
+Z => RSL_TX_PCS_RST_C_4);
+\RDO_RX_SERDES_RST_C_1[0]\: LUT4 
+generic map(
+  init => X"F4F4"
+)
+port map (
+A => rsl_disable,
+B => RXS_RST,
+C => rx_serdes_rst_c,
+D => VCC,
+Z => RSL_RX_SERDES_RST_C_5);
+\RDO_RX_PCS_RST_C_1[0]\: LUT4 
+generic map(
+  init => X"F4F4"
+)
+port map (
+A => rsl_disable,
+B => RXP_RST2,
+C => rx_pcs_rst_c,
+D => VCC,
+Z => RSL_RX_PCS_RST_C_10);
+\GENBLK1.UN9_PLOL0_CNT_TC\: LUT4 
+generic map(
+  init => X"1010"
+)
+port map (
+A => PLOL0_CNT(0),
+B => PLOL0_CNT(1),
+C => PLOL0_CNT(2),
+D => VCC,
+Z => UN9_PLOL0_CNT_TC);
+\GENBLK2.GENBLK3.UN17_RXR_WT_TC_6\: LUT4 
+generic map(
+  init => X"4000"
+)
+port map (
+A => RXR_WT_CNT(0),
+B => RXR_WT_CNT(8),
+C => RXR_WT_CNT(9),
+D => RXR_WT_CNT(11),
+Z => UN17_RXR_WT_TC_6);
+\GENBLK2.GENBLK3.UN17_RXR_WT_TC_7\: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RXR_WT_CNT(3),
+B => RXR_WT_CNT(4),
+C => RXR_WT_CNT(5),
+D => RXR_WT_CNT(7),
+Z => UN17_RXR_WT_TC_7);
+\GENBLK2.GENBLK3.UN17_RXR_WT_TC_8\: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RXR_WT_CNT(1),
+B => RXR_WT_CNT(2),
+C => RXR_WT_CNT(6),
+D => RXR_WT_CNT(10),
+Z => UN17_RXR_WT_TC_8);
+\GENBLK1.GENBLK2.UN18_TXR_WT_TC_6\: LUT4 
+generic map(
+  init => X"4000"
+)
+port map (
+A => TXR_WT_CNT(0),
+B => TXR_WT_CNT(8),
+C => TXR_WT_CNT(9),
+D => TXR_WT_CNT(11),
+Z => UN18_TXR_WT_TC_6);
+\GENBLK1.GENBLK2.UN18_TXR_WT_TC_7\: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => TXR_WT_CNT(3),
+B => TXR_WT_CNT(4),
+C => TXR_WT_CNT(5),
+D => TXR_WT_CNT(7),
+Z => UN18_TXR_WT_TC_7);
+\GENBLK1.GENBLK2.UN18_TXR_WT_TC_8\: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => TXR_WT_CNT(1),
+B => TXR_WT_CNT(2),
+C => TXR_WT_CNT(6),
+D => TXR_WT_CNT(10),
+Z => UN18_TXR_WT_TC_8);
+RLOLS0_CNT_TC_1_9_Z934: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RLOLS0_CNT(1),
+B => RLOLS0_CNT(2),
+C => RLOLS0_CNT(3),
+D => RLOLS0_CNT(4),
+Z => RLOLS0_CNT_TC_1_9);
+RLOLS0_CNT_TC_1_10_Z935: LUT4 
+generic map(
+  init => X"4000"
+)
+port map (
+A => RLOLS0_CNT(0),
+B => RLOLS0_CNT(10),
+C => RLOLS0_CNT(14),
+D => RLOLS0_CNT(15),
+Z => RLOLS0_CNT_TC_1_10);
+RLOLS0_CNT_TC_1_11_Z936: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RLOLS0_CNT(9),
+B => RLOLS0_CNT(11),
+C => RLOLS0_CNT(12),
+D => RLOLS0_CNT(13),
+Z => RLOLS0_CNT_TC_1_11);
+RLOLS0_CNT_TC_1_12_Z937: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RLOLS0_CNT(5),
+B => RLOLS0_CNT(6),
+C => RLOLS0_CNT(7),
+D => RLOLS0_CNT(8),
+Z => RLOLS0_CNT_TC_1_12);
+\GENBLK1.UN1_PLOL_CNT_TC_10\: LUT4 
+generic map(
+  init => X"1000"
+)
+port map (
+A => PLOL_CNT(2),
+B => PLOL_CNT(3),
+C => PLOL_CNT(17),
+D => PLOL_CNT(19),
+Z => UN1_PLOL_CNT_TC_10);
+\GENBLK1.UN1_PLOL_CNT_TC_11\: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => PLOL_CNT(13),
+B => PLOL_CNT(14),
+C => PLOL_CNT(15),
+D => PLOL_CNT(16),
+Z => UN1_PLOL_CNT_TC_11);
+\GENBLK1.UN1_PLOL_CNT_TC_12\: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => PLOL_CNT(7),
+B => PLOL_CNT(8),
+C => PLOL_CNT(9),
+D => PLOL_CNT(11),
+Z => UN1_PLOL_CNT_TC_12);
+\GENBLK1.UN1_PLOL_CNT_TC_13\: LUT4 
+generic map(
+  init => X"0008"
+)
+port map (
+A => PLOL_CNT(1),
+B => PLOL_CNT(6),
+C => PLOL_CNT(10),
+D => PLOL_CNT(12),
+Z => UN1_PLOL_CNT_TC_13);
+RLOL1_CNT_TC_1_10_Z942: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RLOL1_CNT(7),
+B => RLOL1_CNT(8),
+C => RLOL1_CNT(9),
+D => RLOL1_CNT(10),
+Z => RLOL1_CNT_TC_1_10);
+RLOL1_CNT_TC_1_11_Z943: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RLOL1_CNT(3),
+B => RLOL1_CNT(4),
+C => RLOL1_CNT(5),
+D => RLOL1_CNT(6),
+Z => RLOL1_CNT_TC_1_11);
+RLOL1_CNT_TC_1_12_Z944: LUT4 
+generic map(
+  init => X"0100"
+)
+port map (
+A => RLOL1_CNT(0),
+B => RLOL1_CNT(1),
+C => RLOL1_CNT(2),
+D => RLOL1_CNT(17),
+Z => RLOL1_CNT_TC_1_12);
+RLOL1_CNT_TC_1_13_Z945: LUT4 
+generic map(
+  init => X"0040"
+)
+port map (
+A => RLOL1_CNT(13),
+B => RLOL1_CNT(14),
+C => RLOL1_CNT(15),
+D => RLOL1_CNT(16),
+Z => RLOL1_CNT_TC_1_13);
+\GENBLK2.GENBLK3.RXSDR_APPD_2\: LUT4 
+generic map(
+  init => X"EEEE"
+)
+port map (
+A => RXSDR_APPD_4,
+B => serdes_rst_dual_c,
+C => VCC,
+D => VCC,
+Z => RXSDR_APPD_2);
+RX_ALL_WELL_Z947: LUT4 
+generic map(
+  init => X"1111"
+)
+port map (
+A => RLOL_DB,
+B => RLOS_DB,
+C => VCC,
+D => VCC,
+Z => RX_ALL_WELL);
+\GENBLK2.UN8_RXS_CNT_TC\: LUT4 
+generic map(
+  init => X"8888"
+)
+port map (
+A => RXS_CNT(0),
+B => RXS_CNT(1),
+C => VCC,
+D => VCC,
+Z => UN8_RXS_CNT_TC);
+PLOL_FEDGE_Z949: LUT4 
+generic map(
+  init => X"4444"
+)
+port map (
+A => PLL_LOL_P2,
+B => PLL_LOL_P3,
+C => VCC,
+D => VCC,
+Z => PLOL_FEDGE);
+RLOS_REDGE_Z950: LUT4 
+generic map(
+  init => X"2222"
+)
+port map (
+A => RLOS_DB,
+B => RLOS_DB_P1,
+C => VCC,
+D => VCC,
+Z => RLOS_REDGE);
+\GENBLK1.PLOL0_CNT_3_RNO[2]\: LUT4 
+generic map(
+  init => X"8888"
+)
+port map (
+A => PLOL0_CNT(0),
+B => WAITA_PLOL0,
+C => VCC,
+D => VCC,
+Z => CO0_2);
+UN2_RDO_SERDES_RST_DUAL_C_1_1_Z952: LUT4 
+generic map(
+  init => X"1111"
+)
+port map (
+A => rx_cdr_lol_s,
+B => rx_los_low_s,
+C => VCC,
+D => VCC,
+Z => UN2_RDO_SERDES_RST_DUAL_C_1_1);
+\UN1_RLOS_DB_CNT_ZERO_AM[0]_Z953\: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RLOS_DB_CNT(0),
+B => RLOS_DB_CNT(1),
+C => RLOS_DB_CNT(2),
+D => RLOS_DB_CNT(3),
+Z => UN1_RLOS_DB_CNT_ZERO_AM(0));
+\UN1_RLOL_DB_CNT_ZERO_AM[0]_Z954\: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RLOL_DB_CNT(0),
+B => RLOL_DB_CNT(1),
+C => RLOL_DB_CNT(2),
+D => RLOL_DB_CNT(3),
+Z => UN1_RLOL_DB_CNT_ZERO_AM(0));
+DUAL_OR_RSERD_RST_Z955: LUT4 
+generic map(
+  init => X"EEFE"
+)
+port map (
+A => RSL_RX_SERDES_RST_C_5,
+B => serdes_rst_dual_c,
+C => rsl_rst,
+D => rsl_disable,
+Z => DUAL_OR_RSERD_RST);
+\GENBLK1.PLOL0_CNT9\: LUT4 
+generic map(
+  init => X"AAAE"
+)
+port map (
+A => PLL_LOL_P2,
+B => PLOL0_CNT(2),
+C => PLOL0_CNT(1),
+D => PLOL0_CNT(0),
+Z => PLOL0_CNT9);
+\GENBLK2.RLOLS0_CNT11_0\: LUT4 
+generic map(
+  init => X"4F44"
+)
+port map (
+A => RLOL_DB_P1,
+B => RLOL_DB,
+C => RLOS_DB_P1,
+D => RLOS_DB,
+Z => RLOLS0_CNT11_0);
+\GENBLK1.GENBLK2.TXR_WT_CNT9_I\: LUT4 
+generic map(
+  init => X"1555"
+)
+port map (
+A => TX_ANY_RST,
+B => UN18_TXR_WT_TC_8,
+C => UN18_TXR_WT_TC_7,
+D => UN18_TXR_WT_TC_6,
+Z => \TXR_WT_CNT_\);
+\GENBLK2.RLOL1_CNT_CRY_0[0]\: CCU2C 
+generic map(
+  INIT0 => X"500c",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => \RLOL1_CNT_\,
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_7,
+COUT => RLOL1_CNT_CRY(0),
+S0 => RLOL1_CNT_CRY_0_S0(0),
+S1 => RLOL1_CNT_S(0));
+\GENBLK2.RLOL1_CNT_CRY_0[1]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOL1_CNT_\,
+B0 => RLOL1_CNT(1),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(2),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL1_CNT_CRY(0),
+COUT => RLOL1_CNT_CRY(2),
+S0 => RLOL1_CNT_S(1),
+S1 => RLOL1_CNT_S(2));
+\GENBLK2.RLOL1_CNT_CRY_0[3]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOL1_CNT_\,
+B0 => RLOL1_CNT(3),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(4),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL1_CNT_CRY(2),
+COUT => RLOL1_CNT_CRY(4),
+S0 => RLOL1_CNT_S(3),
+S1 => RLOL1_CNT_S(4));
+\GENBLK2.RLOL1_CNT_CRY_0[5]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOL1_CNT_\,
+B0 => RLOL1_CNT(5),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(6),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL1_CNT_CRY(4),
+COUT => RLOL1_CNT_CRY(6),
+S0 => RLOL1_CNT_S(5),
+S1 => RLOL1_CNT_S(6));
+\GENBLK2.RLOL1_CNT_CRY_0[7]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOL1_CNT_\,
+B0 => RLOL1_CNT(7),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(8),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL1_CNT_CRY(6),
+COUT => RLOL1_CNT_CRY(8),
+S0 => RLOL1_CNT_S(7),
+S1 => RLOL1_CNT_S(8));
+\GENBLK2.RLOL1_CNT_CRY_0[9]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOL1_CNT_\,
+B0 => RLOL1_CNT(9),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(10),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL1_CNT_CRY(8),
+COUT => RLOL1_CNT_CRY(10),
+S0 => RLOL1_CNT_S(9),
+S1 => RLOL1_CNT_S(10));
+\GENBLK2.RLOL1_CNT_CRY_0[11]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOL1_CNT_\,
+B0 => RLOL1_CNT(11),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(12),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL1_CNT_CRY(10),
+COUT => RLOL1_CNT_CRY(12),
+S0 => RLOL1_CNT_S(11),
+S1 => RLOL1_CNT_S(12));
+\GENBLK2.RLOL1_CNT_CRY_0[13]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOL1_CNT_\,
+B0 => RLOL1_CNT(13),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(14),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL1_CNT_CRY(12),
+COUT => RLOL1_CNT_CRY(14),
+S0 => RLOL1_CNT_S(13),
+S1 => RLOL1_CNT_S(14));
+\GENBLK2.RLOL1_CNT_CRY_0[15]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOL1_CNT_\,
+B0 => RLOL1_CNT(15),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(16),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL1_CNT_CRY(14),
+COUT => RLOL1_CNT_CRY(16),
+S0 => RLOL1_CNT_S(15),
+S1 => RLOL1_CNT_S(16));
+\GENBLK2.RLOL1_CNT_CRY_0[17]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"800a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOL1_CNT_\,
+B0 => RLOL1_CNT(17),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(18),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL1_CNT_CRY(16),
+COUT => RLOL1_CNT_CRY_0_COUT(17),
+S0 => RLOL1_CNT_S(17),
+S1 => RLOL1_CNT_S(18));
+\GENBLK2.RLOLS0_CNT_CRY_0[0]\: CCU2C 
+generic map(
+  INIT0 => X"500c",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => \RLOLS0_CNT_\,
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOLS0_CNT_\,
+B1 => RLOLS0_CNT(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_6,
+COUT => RLOLS0_CNT_CRY(0),
+S0 => RLOLS0_CNT_CRY_0_S0(0),
+S1 => RLOLS0_CNT_S(0));
+\GENBLK2.RLOLS0_CNT_CRY_0[1]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOLS0_CNT_\,
+B0 => RLOLS0_CNT(1),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOLS0_CNT_\,
+B1 => RLOLS0_CNT(2),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOLS0_CNT_CRY(0),
+COUT => RLOLS0_CNT_CRY(2),
+S0 => RLOLS0_CNT_S(1),
+S1 => RLOLS0_CNT_S(2));
+\GENBLK2.RLOLS0_CNT_CRY_0[3]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOLS0_CNT_\,
+B0 => RLOLS0_CNT(3),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOLS0_CNT_\,
+B1 => RLOLS0_CNT(4),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOLS0_CNT_CRY(2),
+COUT => RLOLS0_CNT_CRY(4),
+S0 => RLOLS0_CNT_S(3),
+S1 => RLOLS0_CNT_S(4));
+\GENBLK2.RLOLS0_CNT_CRY_0[5]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOLS0_CNT_\,
+B0 => RLOLS0_CNT(5),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOLS0_CNT_\,
+B1 => RLOLS0_CNT(6),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOLS0_CNT_CRY(4),
+COUT => RLOLS0_CNT_CRY(6),
+S0 => RLOLS0_CNT_S(5),
+S1 => RLOLS0_CNT_S(6));
+\GENBLK2.RLOLS0_CNT_CRY_0[7]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOLS0_CNT_\,
+B0 => RLOLS0_CNT(7),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOLS0_CNT_\,
+B1 => RLOLS0_CNT(8),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOLS0_CNT_CRY(6),
+COUT => RLOLS0_CNT_CRY(8),
+S0 => RLOLS0_CNT_S(7),
+S1 => RLOLS0_CNT_S(8));
+\GENBLK2.RLOLS0_CNT_CRY_0[9]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOLS0_CNT_\,
+B0 => RLOLS0_CNT(9),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOLS0_CNT_\,
+B1 => RLOLS0_CNT(10),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOLS0_CNT_CRY(8),
+COUT => RLOLS0_CNT_CRY(10),
+S0 => RLOLS0_CNT_S(9),
+S1 => RLOLS0_CNT_S(10));
+\GENBLK2.RLOLS0_CNT_CRY_0[11]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOLS0_CNT_\,
+B0 => RLOLS0_CNT(11),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOLS0_CNT_\,
+B1 => RLOLS0_CNT(12),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOLS0_CNT_CRY(10),
+COUT => RLOLS0_CNT_CRY(12),
+S0 => RLOLS0_CNT_S(11),
+S1 => RLOLS0_CNT_S(12));
+\GENBLK2.RLOLS0_CNT_CRY_0[13]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOLS0_CNT_\,
+B0 => RLOLS0_CNT(13),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOLS0_CNT_\,
+B1 => RLOLS0_CNT(14),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOLS0_CNT_CRY(12),
+COUT => RLOLS0_CNT_CRY(14),
+S0 => RLOLS0_CNT_S(13),
+S1 => RLOLS0_CNT_S(14));
+\GENBLK2.RLOLS0_CNT_CRY_0[15]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOLS0_CNT_\,
+B0 => RLOLS0_CNT(15),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOLS0_CNT_\,
+B1 => RLOLS0_CNT(16),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOLS0_CNT_CRY(14),
+COUT => RLOLS0_CNT_CRY(16),
+S0 => RLOLS0_CNT_S(15),
+S1 => RLOLS0_CNT_S(16));
+\GENBLK2.RLOLS0_CNT_S_0[17]\: CCU2C 
+generic map(
+  INIT0 => X"800a",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOLS0_CNT_\,
+B0 => RLOLS0_CNT(17),
+C0 => VCC,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => RLOLS0_CNT_CRY(16),
+COUT => RLOLS0_CNT_S_0_COUT(17),
+S0 => RLOLS0_CNT_S(17),
+S1 => RLOLS0_CNT_S_0_S1(17));
+\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[0]\: CCU2C 
+generic map(
+  INIT0 => X"500c",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => \TXR_WT_CNT_\,
+C0 => VCC,
+D0 => VCC,
+A1 => \TXR_WT_CNT_\,
+B1 => TXR_WT_CNT(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_5,
+COUT => TXR_WT_CNT_CRY(0),
+S0 => TXR_WT_CNT_CRY_0_S0(0),
+S1 => TXR_WT_CNT_S(0));
+\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[1]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \TXR_WT_CNT_\,
+B0 => TXR_WT_CNT(1),
+C0 => VCC,
+D0 => VCC,
+A1 => \TXR_WT_CNT_\,
+B1 => TXR_WT_CNT(2),
+C1 => VCC,
+D1 => VCC,
+CIN => TXR_WT_CNT_CRY(0),
+COUT => TXR_WT_CNT_CRY(2),
+S0 => TXR_WT_CNT_S(1),
+S1 => TXR_WT_CNT_S(2));
+\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[3]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \TXR_WT_CNT_\,
+B0 => TXR_WT_CNT(3),
+C0 => VCC,
+D0 => VCC,
+A1 => \TXR_WT_CNT_\,
+B1 => TXR_WT_CNT(4),
+C1 => VCC,
+D1 => VCC,
+CIN => TXR_WT_CNT_CRY(2),
+COUT => TXR_WT_CNT_CRY(4),
+S0 => TXR_WT_CNT_S(3),
+S1 => TXR_WT_CNT_S(4));
+\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[5]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \TXR_WT_CNT_\,
+B0 => TXR_WT_CNT(5),
+C0 => VCC,
+D0 => VCC,
+A1 => \TXR_WT_CNT_\,
+B1 => TXR_WT_CNT(6),
+C1 => VCC,
+D1 => VCC,
+CIN => TXR_WT_CNT_CRY(4),
+COUT => TXR_WT_CNT_CRY(6),
+S0 => TXR_WT_CNT_S(5),
+S1 => TXR_WT_CNT_S(6));
+\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[7]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \TXR_WT_CNT_\,
+B0 => TXR_WT_CNT(7),
+C0 => VCC,
+D0 => VCC,
+A1 => \TXR_WT_CNT_\,
+B1 => TXR_WT_CNT(8),
+C1 => VCC,
+D1 => VCC,
+CIN => TXR_WT_CNT_CRY(6),
+COUT => TXR_WT_CNT_CRY(8),
+S0 => TXR_WT_CNT_S(7),
+S1 => TXR_WT_CNT_S(8));
+\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[9]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \TXR_WT_CNT_\,
+B0 => TXR_WT_CNT(9),
+C0 => VCC,
+D0 => VCC,
+A1 => \TXR_WT_CNT_\,
+B1 => TXR_WT_CNT(10),
+C1 => VCC,
+D1 => VCC,
+CIN => TXR_WT_CNT_CRY(8),
+COUT => TXR_WT_CNT_CRY(10),
+S0 => TXR_WT_CNT_S(9),
+S1 => TXR_WT_CNT_S(10));
+\GENBLK1.GENBLK2.TXR_WT_CNT_S_0[11]\: CCU2C 
+generic map(
+  INIT0 => X"800a",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \TXR_WT_CNT_\,
+B0 => TXR_WT_CNT(11),
+C0 => VCC,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => TXR_WT_CNT_CRY(10),
+COUT => TXR_WT_CNT_S_0_COUT(11),
+S0 => TXR_WT_CNT_S(11),
+S1 => TXR_WT_CNT_S_0_S1(11));
+\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[0]\: CCU2C 
+generic map(
+  INIT0 => X"5003",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => RXR_WT_CNT9,
+C0 => VCC,
+D0 => VCC,
+A1 => RXR_WT_CNT9,
+B1 => RXR_WT_CNT(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_4,
+COUT => RXR_WT_CNT_CRY(0),
+S0 => RXR_WT_CNT_CRY_0_S0(0),
+S1 => RXR_WT_CNT_S(0));
+\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[1]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => RXR_WT_CNT9,
+B0 => RXR_WT_CNT(1),
+C0 => VCC,
+D0 => VCC,
+A1 => RXR_WT_CNT9,
+B1 => RXR_WT_CNT(2),
+C1 => VCC,
+D1 => VCC,
+CIN => RXR_WT_CNT_CRY(0),
+COUT => RXR_WT_CNT_CRY(2),
+S0 => RXR_WT_CNT_S(1),
+S1 => RXR_WT_CNT_S(2));
+\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[3]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => RXR_WT_CNT9,
+B0 => RXR_WT_CNT(3),
+C0 => VCC,
+D0 => VCC,
+A1 => RXR_WT_CNT9,
+B1 => RXR_WT_CNT(4),
+C1 => VCC,
+D1 => VCC,
+CIN => RXR_WT_CNT_CRY(2),
+COUT => RXR_WT_CNT_CRY(4),
+S0 => RXR_WT_CNT_S(3),
+S1 => RXR_WT_CNT_S(4));
+\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[5]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => RXR_WT_CNT9,
+B0 => RXR_WT_CNT(5),
+C0 => VCC,
+D0 => VCC,
+A1 => RXR_WT_CNT9,
+B1 => RXR_WT_CNT(6),
+C1 => VCC,
+D1 => VCC,
+CIN => RXR_WT_CNT_CRY(4),
+COUT => RXR_WT_CNT_CRY(6),
+S0 => RXR_WT_CNT_S(5),
+S1 => RXR_WT_CNT_S(6));
+\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[7]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => RXR_WT_CNT9,
+B0 => RXR_WT_CNT(7),
+C0 => VCC,
+D0 => VCC,
+A1 => RXR_WT_CNT9,
+B1 => RXR_WT_CNT(8),
+C1 => VCC,
+D1 => VCC,
+CIN => RXR_WT_CNT_CRY(6),
+COUT => RXR_WT_CNT_CRY(8),
+S0 => RXR_WT_CNT_S(7),
+S1 => RXR_WT_CNT_S(8));
+\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[9]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => RXR_WT_CNT9,
+B0 => RXR_WT_CNT(9),
+C0 => VCC,
+D0 => VCC,
+A1 => RXR_WT_CNT9,
+B1 => RXR_WT_CNT(10),
+C1 => VCC,
+D1 => VCC,
+CIN => RXR_WT_CNT_CRY(8),
+COUT => RXR_WT_CNT_CRY(10),
+S0 => RXR_WT_CNT_S(9),
+S1 => RXR_WT_CNT_S(10));
+\GENBLK2.GENBLK3.RXR_WT_CNT_S_0[11]\: CCU2C 
+generic map(
+  INIT0 => X"4005",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => RXR_WT_CNT9,
+B0 => RXR_WT_CNT(11),
+C0 => VCC,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => RXR_WT_CNT_CRY(10),
+COUT => RXR_WT_CNT_S_0_COUT(11),
+S0 => RXR_WT_CNT_S(11),
+S1 => RXR_WT_CNT_S_0_S1(11));
+\GENBLK1.PLOL_CNT_CRY_0[0]\: CCU2C 
+generic map(
+  INIT0 => X"500c",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => \PLOL_CNT_\,
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_3,
+COUT => PLOL_CNT_CRY(0),
+S0 => PLOL_CNT_CRY_0_S0(0),
+S1 => PLOL_CNT_S(0));
+\GENBLK1.PLOL_CNT_CRY_0[1]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(1),
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(2),
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(0),
+COUT => PLOL_CNT_CRY(2),
+S0 => PLOL_CNT_S(1),
+S1 => PLOL_CNT_S(2));
+\GENBLK1.PLOL_CNT_CRY_0[3]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(3),
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(4),
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(2),
+COUT => PLOL_CNT_CRY(4),
+S0 => PLOL_CNT_S(3),
+S1 => PLOL_CNT_S(4));
+\GENBLK1.PLOL_CNT_CRY_0[5]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(5),
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(6),
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(4),
+COUT => PLOL_CNT_CRY(6),
+S0 => PLOL_CNT_S(5),
+S1 => PLOL_CNT_S(6));
+\GENBLK1.PLOL_CNT_CRY_0[7]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(7),
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(8),
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(6),
+COUT => PLOL_CNT_CRY(8),
+S0 => PLOL_CNT_S(7),
+S1 => PLOL_CNT_S(8));
+\GENBLK1.PLOL_CNT_CRY_0[9]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(9),
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(10),
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(8),
+COUT => PLOL_CNT_CRY(10),
+S0 => PLOL_CNT_S(9),
+S1 => PLOL_CNT_S(10));
+\GENBLK1.PLOL_CNT_CRY_0[11]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(11),
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(12),
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(10),
+COUT => PLOL_CNT_CRY(12),
+S0 => PLOL_CNT_S(11),
+S1 => PLOL_CNT_S(12));
+\GENBLK1.PLOL_CNT_CRY_0[13]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(13),
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(14),
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(12),
+COUT => PLOL_CNT_CRY(14),
+S0 => PLOL_CNT_S(13),
+S1 => PLOL_CNT_S(14));
+\GENBLK1.PLOL_CNT_CRY_0[15]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(15),
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(16),
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(14),
+COUT => PLOL_CNT_CRY(16),
+S0 => PLOL_CNT_S(15),
+S1 => PLOL_CNT_S(16));
+\GENBLK1.PLOL_CNT_CRY_0[17]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(17),
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(18),
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(16),
+COUT => PLOL_CNT_CRY(18),
+S0 => PLOL_CNT_S(17),
+S1 => PLOL_CNT_S(18));
+\GENBLK1.PLOL_CNT_S_0[19]\: CCU2C 
+generic map(
+  INIT0 => X"800a",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(19),
+C0 => VCC,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(18),
+COUT => PLOL_CNT_S_0_COUT(19),
+S0 => PLOL_CNT_S(19),
+S1 => PLOL_CNT_S_0_S1(19));
+\UN1_GENBLK2.RLOS_DB_CNT_CRY_0_0\: CCU2C 
+generic map(
+  INIT0 => X"5003",
+  INIT1 => X"900a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => RLOS_DB_CNT(0),
+B1 => UN1_RLOS_DB_CNT_ZERO(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_2,
+COUT => RLOS_DB_CNT_CRY_0,
+S0 => RLOS_DB_CNT_CRY_0_0_S0,
+S1 => RLOS_DB_CNT_CRY_0_0_S1);
+\UN1_GENBLK2.RLOS_DB_CNT_CRY_1_0\: CCU2C 
+generic map(
+  INIT0 => X"e101",
+  INIT1 => X"e101",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RLOS_DB_CNT_ZERO(0),
+B0 => RLOS_P2,
+C0 => RLOS_DB_CNT(1),
+D0 => VCC,
+A1 => UN1_RLOS_DB_CNT_ZERO(0),
+B1 => RLOS_P2,
+C1 => RLOS_DB_CNT(2),
+D1 => VCC,
+CIN => RLOS_DB_CNT_CRY_0,
+COUT => RLOS_DB_CNT_CRY_2,
+S0 => RLOS_DB_CNT_CRY_1_0_S0,
+S1 => RLOS_DB_CNT_CRY_1_0_S1);
+\UN1_GENBLK2.RLOS_DB_CNT_S_3_0\: CCU2C 
+generic map(
+  INIT0 => X"a90a",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => RLOS_DB_CNT(3),
+B0 => RLOS_P2,
+C0 => UN1_RLOS_DB_CNT_ZERO(0),
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => RLOS_DB_CNT_CRY_2,
+COUT => RLOS_DB_CNT_S_3_0_COUT,
+S0 => RLOS_DB_CNT_S_3_0_S0,
+S1 => RLOS_DB_CNT_S_3_0_S1);
+\UN1_GENBLK2.RLOL_DB_CNT_CRY_0_0\: CCU2C 
+generic map(
+  INIT0 => X"5003",
+  INIT1 => X"900a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => RLOL_DB_CNT(0),
+B1 => UN1_RLOL_DB_CNT_ZERO(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_1,
+COUT => RLOL_DB_CNT_CRY_0,
+S0 => RLOL_DB_CNT_CRY_0_0_S0,
+S1 => RLOL_DB_CNT_CRY_0_0_S1);
+\UN1_GENBLK2.RLOL_DB_CNT_CRY_1_0\: CCU2C 
+generic map(
+  INIT0 => X"e101",
+  INIT1 => X"e101",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RLOL_DB_CNT_ZERO(0),
+B0 => RLOL_P2,
+C0 => RLOL_DB_CNT(1),
+D0 => VCC,
+A1 => UN1_RLOL_DB_CNT_ZERO(0),
+B1 => RLOL_P2,
+C1 => RLOL_DB_CNT(2),
+D1 => VCC,
+CIN => RLOL_DB_CNT_CRY_0,
+COUT => RLOL_DB_CNT_CRY_2,
+S0 => RLOL_DB_CNT_CRY_1_0_S0,
+S1 => RLOL_DB_CNT_CRY_1_0_S1);
+\UN1_GENBLK2.RLOL_DB_CNT_S_3_0\: CCU2C 
+generic map(
+  INIT0 => X"a90a",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => RLOL_DB_CNT(3),
+B0 => RLOL_P2,
+C0 => UN1_RLOL_DB_CNT_ZERO(0),
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL_DB_CNT_CRY_2,
+COUT => RLOL_DB_CNT_S_3_0_COUT,
+S0 => RLOL_DB_CNT_S_3_0_S0,
+S1 => RLOL_DB_CNT_S_3_0_S1);
+RXSDR_APPD_4 <= RXSDR_APPD;
+TXSR_APPD_4 <= TXSR_APPD;
+VCC_0: VHI port map (
+Z => VCC);
+II_GND: VLO port map (
+Z => GND);
+rsl_tx_pcs_rst_c <= RSL_TX_PCS_RST_C_4;
+rsl_rx_serdes_rst_c <= RSL_RX_SERDES_RST_C_5;
+rsl_serdes_rst_dual_c <= RSL_SERDES_RST_DUAL_C_6;
+rsl_tx_serdes_rst_c <= RSL_TX_SERDES_RST_C_7;
+rsl_tx_rdy <= RSL_TX_RDY_8;
+rsl_rx_rdy <= RSL_RX_RDY_9;
+rsl_rx_pcs_rst_c <= RSL_RX_PCS_RST_C_10;
+end beh;
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library synplify;
+use synplify.components.all;
+library pmi;
+use pmi.pmi_components.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity sgmii_ecp5sll_core_Z1_layer1 is
+port(
+tx_pclk :  in std_logic;
+sli_rst :  in std_logic;
+pll_refclki :  in std_logic;
+pll_lock_i :  out std_logic);
+end sgmii_ecp5sll_core_Z1_layer1;
+
+architecture beh of sgmii_ecp5sll_core_Z1_layer1 is
+signal PHB_CNT : std_logic_vector(2 downto 0);
+signal PHB_CNT_I : std_logic_vector(2 downto 0);
+signal RCOUNT : std_logic_vector(15 downto 0);
+signal PCOUNT : std_logic_vector(21 downto 0);
+signal UN1_PCOUNT_DIFF_I : std_logic_vector(0 to 0);
+signal SLL_STATE : std_logic_vector(1 downto 0);
+signal SLL_STATE_QN : std_logic_vector(1 downto 0);
+signal RHB_WAIT_CNT_S : std_logic_vector(7 downto 0);
+signal RHB_WAIT_CNT : std_logic_vector(7 downto 0);
+signal RHB_WAIT_CNT_QN : std_logic_vector(7 downto 0);
+signal RCOUNT_S : std_logic_vector(15 downto 0);
+signal RCOUNT_QN : std_logic_vector(15 downto 0);
+signal PHB_CNT_QN : std_logic_vector(2 downto 0);
+signal PHB_CNT_RNO : std_logic_vector(2 downto 1);
+signal PCOUNT_S : std_logic_vector(21 downto 0);
+signal PCOUNT_QN : std_logic_vector(21 downto 0);
+signal PCOUNT_DIFF_QN : std_logic_vector(21 downto 0);
+signal RDIFF_COMP_LOCK : std_logic_vector(2 to 2);
+signal RDIFF_COMP_LOCK_QN : std_logic_vector(2 to 2);
+signal UN1_PCOUNT_DIFF : std_logic_vector(0 to 0);
+signal PCOUNT_CRY : std_logic_vector(20 downto 0);
+signal PCOUNT_CRY_0_S0 : std_logic_vector(0 to 0);
+signal PCOUNT_S_0_COUT : std_logic_vector(21 to 21);
+signal PCOUNT_S_0_S1 : std_logic_vector(21 to 21);
+signal RCOUNT_CRY : std_logic_vector(14 downto 0);
+signal RCOUNT_CRY_0_S0 : std_logic_vector(0 to 0);
+signal RCOUNT_S_0_COUT : std_logic_vector(15 to 15);
+signal RCOUNT_S_0_S1 : std_logic_vector(15 to 15);
+signal RHB_WAIT_CNT_CRY : std_logic_vector(6 downto 0);
+signal RHB_WAIT_CNT_CRY_0_S0 : std_logic_vector(0 to 0);
+signal RHB_WAIT_CNT_S_0_COUT : std_logic_vector(7 to 7);
+signal RHB_WAIT_CNT_S_0_S1 : std_logic_vector(7 to 7);
+signal PLL_LOCK : std_logic ;
+signal RTC_CTRL4_0_A3_1 : std_logic ;
+signal UN13_LOCK_20 : std_logic ;
+signal PPUL_SYNC_P2 : std_logic ;
+signal PPUL_SYNC_P1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_20 : std_logic ;
+signal UN13_LOCK_19 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_19 : std_logic ;
+signal UN13_LOCK_18 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_18 : std_logic ;
+signal UN13_LOCK_17 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_17_0_RNO : std_logic ;
+signal UN13_LOCK_16 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_16 : std_logic ;
+signal UN13_LOCK_15 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_15 : std_logic ;
+signal UN13_LOCK_14 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_14 : std_logic ;
+signal UN13_LOCK_13 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_13 : std_logic ;
+signal UN13_LOCK_12 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_12 : std_logic ;
+signal UN13_LOCK_11 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_11 : std_logic ;
+signal UN13_LOCK_10 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_10 : std_logic ;
+signal UN13_LOCK_9 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_9 : std_logic ;
+signal UN13_LOCK_8 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_8 : std_logic ;
+signal UN13_LOCK_7 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_7 : std_logic ;
+signal UN13_LOCK_6 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_6 : std_logic ;
+signal UN13_LOCK_5 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_5 : std_logic ;
+signal UN13_LOCK_4 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_4 : std_logic ;
+signal UN13_LOCK_3 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_3 : std_logic ;
+signal UN13_LOCK_2 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_2 : std_logic ;
+signal UN13_LOCK_1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_1 : std_logic ;
+signal UN13_LOCK_21 : std_logic ;
+signal PPUL_SYNC_P3 : std_logic ;
+signal N_7 : std_logic ;
+signal UN13_LOCK_0 : std_logic ;
+signal RTC_CTRL4 : std_logic ;
+signal RTC_CTRL : std_logic ;
+signal VCC : std_logic ;
+signal N_2085_0 : std_logic ;
+signal UNLOCK_5 : std_logic ;
+signal UNLOCK_1_SQMUXA_I : std_logic ;
+signal UNLOCK : std_logic ;
+signal UNLOCK_QN : std_logic ;
+signal N_95_I : std_logic ;
+signal N_97_I : std_logic ;
+signal RTC_PUL : std_logic ;
+signal RTC_PUL_P1 : std_logic ;
+signal RTC_PUL_P1_QN : std_logic ;
+signal RTC_PUL5 : std_logic ;
+signal RTC_PUL_QN : std_logic ;
+signal RTC_CTRL_QN : std_logic ;
+signal RSTAT_PCLK_2 : std_logic ;
+signal RSTAT_PCLK : std_logic ;
+signal RSTAT_PCLK_QN : std_logic ;
+signal RHB_SYNC_P1 : std_logic ;
+signal RHB_SYNC_P2 : std_logic ;
+signal RHB_SYNC_P2_QN : std_logic ;
+signal RHB_SYNC : std_logic ;
+signal RHB_SYNC_P1_QN : std_logic ;
+signal PPUL_SYNC_P3_QN : std_logic ;
+signal PPUL_SYNC_P2_QN : std_logic ;
+signal PPUL_SYNC : std_logic ;
+signal PPUL_SYNC_P1_QN : std_logic ;
+signal N_53_I : std_logic ;
+signal PLL_LOCK_QN : std_logic ;
+signal PHB : std_logic ;
+signal PHB_QN : std_logic ;
+signal PDIFF_SYNC : std_logic ;
+signal PDIFF_SYNC_P1 : std_logic ;
+signal PDIFF_SYNC_P1_QN : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_1_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_1_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_3_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_3_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_5_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_5_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_7_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_7_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_9_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_9_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_11_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_11_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_13_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_13_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_15_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_15_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_17_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_17_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_19_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_19_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_S_21_0_S0 : std_logic ;
+signal LOCK_5 : std_logic ;
+signal LOCK_1_SQMUXA_I : std_logic ;
+signal LOCK : std_logic ;
+signal LOCK_QN : std_logic ;
+signal N_98 : std_logic ;
+signal RTC_PUL5_0_O3 : std_logic ;
+signal RTC_PUL5_0_A3_6 : std_logic ;
+signal RTC_PUL5_0_A3_7 : std_logic ;
+signal UN1_RCOUNT_1_0_A3 : std_logic ;
+signal RHB_WAIT_CNT12 : std_logic ;
+signal UN1_RHB_WAIT_CNT_4 : std_logic ;
+signal UN1_RHB_WAIT_CNT_5 : std_logic ;
+signal N_99 : std_logic ;
+signal RTC_CTRL4_0_A3_12_4 : std_logic ;
+signal RTC_CTRL4_0_A3_12_5 : std_logic ;
+signal RTC_CTRL4_10 : std_logic ;
+signal UN1_RCOUNT_1_0_A3_1 : std_logic ;
+signal N_6 : std_logic ;
+signal RTC_PUL5_0_A3_5 : std_logic ;
+signal N_8 : std_logic ;
+signal UN13_UNLOCK_CRY_21 : std_logic ;
+signal UN13_LOCK_CRY_21_I : std_logic ;
+signal \RHB_WAIT_CNT_\ : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_0_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_0_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_2 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_4 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_6 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_8 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_10 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_12 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_14 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_16 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_18 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_20 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_S_21_0_COUT : std_logic ;
+signal UN1_PCOUNT_DIFF_1_S_21_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_0 : std_logic ;
+signal UN13_LOCK_CRY_0_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_0_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_2 : std_logic ;
+signal UN13_LOCK_CRY_1_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_1_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_4 : std_logic ;
+signal UN13_LOCK_CRY_3_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_3_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_6 : std_logic ;
+signal UN13_LOCK_CRY_5_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_5_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_8 : std_logic ;
+signal UN13_LOCK_CRY_7_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_7_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_10 : std_logic ;
+signal UN13_LOCK_CRY_9_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_9_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_12 : std_logic ;
+signal UN13_LOCK_CRY_11_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_11_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_14 : std_logic ;
+signal UN13_LOCK_CRY_13_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_13_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_16 : std_logic ;
+signal UN13_LOCK_CRY_15_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_15_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_18 : std_logic ;
+signal UN13_LOCK_CRY_17_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_17_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_20 : std_logic ;
+signal UN13_LOCK_CRY_19_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_19_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_21_0_COUT : std_logic ;
+signal UN13_LOCK_CRY_21_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_0 : std_logic ;
+signal UN13_UNLOCK_CRY_0_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_0_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_2 : std_logic ;
+signal UN13_UNLOCK_CRY_1_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_1_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_4 : std_logic ;
+signal UN13_UNLOCK_CRY_3_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_3_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_6 : std_logic ;
+signal UN13_UNLOCK_CRY_5_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_5_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_8 : std_logic ;
+signal UN13_UNLOCK_CRY_7_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_7_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_10 : std_logic ;
+signal UN13_UNLOCK_CRY_9_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_9_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_12 : std_logic ;
+signal UN13_UNLOCK_CRY_11_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_11_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_14 : std_logic ;
+signal UN13_UNLOCK_CRY_13_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_13_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_16 : std_logic ;
+signal UN13_UNLOCK_CRY_15_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_15_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_18 : std_logic ;
+signal UN13_UNLOCK_CRY_17_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_17_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_20 : std_logic ;
+signal UN13_UNLOCK_CRY_19_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_19_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_21_0_COUT : std_logic ;
+signal UN13_UNLOCK_CRY_21_0_S0 : std_logic ;
+signal N_21 : std_logic ;
+signal N_20 : std_logic ;
+signal N_19 : std_logic ;
+signal N_18 : std_logic ;
+signal N_14 : std_logic ;
+signal GND : std_logic ;
+signal N_1 : std_logic ;
+signal N_2 : std_logic ;
+signal N_3 : std_logic ;
+signal N_4 : std_logic ;
+signal N_5 : std_logic ;
+signal N_9 : std_logic ;
+component sync_0s
+port(
+phb :  in std_logic;
+rhb_sync :  out std_logic;
+sli_rst :  in std_logic;
+pll_refclki :  in std_logic  );
+end component;
+component sync_0s_6
+port(
+rtc_pul :  in std_logic;
+ppul_sync :  out std_logic;
+sli_rst :  in std_logic;
+tx_pclk :  in std_logic  );
+end component;
+component sync_0s_0
+port(
+ppul_sync :  in std_logic;
+pdiff_sync :  out std_logic;
+sli_rst :  in std_logic;
+pll_refclki :  in std_logic  );
+end component;
+begin
+PHB_RNO: INV port map (
+A => PHB_CNT(2),
+Z => PHB_CNT_I(2));
+\PHB_CNT_RNO[0]\: INV port map (
+A => PHB_CNT(0),
+Z => PHB_CNT_I(0));
+PLL_LOCK_RNI6JK9: INV port map (
+A => PLL_LOCK,
+Z => pll_lock_i);
+RTC_CTRL4_0_A3_RNO: LUT4 
+generic map(
+  init => X"2000"
+)
+port map (
+A => RCOUNT(2),
+B => RCOUNT(0),
+C => RCOUNT(5),
+D => RCOUNT(4),
+Z => RTC_CTRL4_0_A3_1);
+UN1_PCOUNT_DIFF_1_CRY_19_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_20,
+B => PCOUNT(20),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_20);
+UN1_PCOUNT_DIFF_1_CRY_19_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_19,
+B => PCOUNT(19),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_19);
+UN1_PCOUNT_DIFF_1_CRY_17_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_18,
+B => PCOUNT(18),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_18);
+UN1_PCOUNT_DIFF_1_CRY_17_0_RNO_Z477: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_17,
+B => PCOUNT(17),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_CRY_17_0_RNO);
+UN1_PCOUNT_DIFF_1_CRY_15_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_16,
+B => PCOUNT(16),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_16);
+UN1_PCOUNT_DIFF_1_CRY_15_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_15,
+B => PCOUNT(15),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_15);
+UN1_PCOUNT_DIFF_1_CRY_13_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_14,
+B => PCOUNT(14),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_14);
+UN1_PCOUNT_DIFF_1_CRY_13_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_13,
+B => PCOUNT(13),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_13);
+UN1_PCOUNT_DIFF_1_CRY_11_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_12,
+B => PCOUNT(12),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_12);
+UN1_PCOUNT_DIFF_1_CRY_11_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_11,
+B => PCOUNT(11),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_11);
+UN1_PCOUNT_DIFF_1_CRY_9_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_10,
+B => PCOUNT(10),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_10);
+UN1_PCOUNT_DIFF_1_CRY_9_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_9,
+B => PCOUNT(9),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_9);
+UN1_PCOUNT_DIFF_1_CRY_7_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_8,
+B => PCOUNT(8),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_8);
+UN1_PCOUNT_DIFF_1_CRY_7_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_7,
+B => PCOUNT(7),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_7);
+UN1_PCOUNT_DIFF_1_CRY_5_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_6,
+B => PCOUNT(6),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_6);
+UN1_PCOUNT_DIFF_1_CRY_5_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_5,
+B => PCOUNT(5),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_5);
+UN1_PCOUNT_DIFF_1_CRY_3_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_4,
+B => PCOUNT(4),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_4);
+UN1_PCOUNT_DIFF_1_CRY_3_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_3,
+B => PCOUNT(3),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_3);
+UN1_PCOUNT_DIFF_1_CRY_1_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_2,
+B => PCOUNT(2),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_2);
+UN1_PCOUNT_DIFF_1_CRY_1_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_1,
+B => PCOUNT(1),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_1);
+PPUL_SYNC_P3_RNIU65C: LUT4 
+generic map(
+  init => X"2F20"
+)
+port map (
+A => UN13_LOCK_21,
+B => PPUL_SYNC_P3,
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => N_7);
+\PCOUNT_DIFF_RNO[0]\: LUT4 
+generic map(
+  init => X"FD20"
+)
+port map (
+A => PPUL_SYNC_P1,
+B => PPUL_SYNC_P2,
+C => PCOUNT(0),
+D => UN13_LOCK_0,
+Z => UN1_PCOUNT_DIFF_I(0));
+RTC_CTRL_0: LUT4 
+generic map(
+  init => X"EEEE"
+)
+port map (
+A => RTC_CTRL4,
+B => RTC_CTRL,
+C => VCC,
+D => VCC,
+Z => N_2085_0);
+UNLOCK_REG_Z498: FD1P3DX port map (
+D => UNLOCK_5,
+SP => UNLOCK_1_SQMUXA_I,
+CK => pll_refclki,
+CD => sli_rst,
+Q => UNLOCK);
+\SLL_STATE[0]_REG_Z500\: FD1S3DX port map (
+D => N_95_I,
+CK => pll_refclki,
+CD => sli_rst,
+Q => SLL_STATE(0));
+\SLL_STATE[1]_REG_Z502\: FD1S3DX port map (
+D => N_97_I,
+CK => pll_refclki,
+CD => sli_rst,
+Q => SLL_STATE(1));
+RTC_PUL_P1_REG_Z504: FD1S3DX port map (
+D => RTC_PUL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RTC_PUL_P1);
+RTC_PUL_REG_Z506: FD1P3DX port map (
+D => RTC_PUL5,
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RTC_PUL);
+RTC_CTRL_REG_Z508: FD1S3DX port map (
+D => N_2085_0,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RTC_CTRL);
+RSTAT_PCLK_REG_Z510: FD1P3DX port map (
+D => RSTAT_PCLK_2,
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RSTAT_PCLK);
+\RHB_WAIT_CNT[0]_REG_Z512\: FD1P3DX port map (
+D => RHB_WAIT_CNT_S(0),
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_WAIT_CNT(0));
+\RHB_WAIT_CNT[1]_REG_Z514\: FD1P3DX port map (
+D => RHB_WAIT_CNT_S(1),
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_WAIT_CNT(1));
+\RHB_WAIT_CNT[2]_REG_Z516\: FD1P3DX port map (
+D => RHB_WAIT_CNT_S(2),
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_WAIT_CNT(2));
+\RHB_WAIT_CNT[3]_REG_Z518\: FD1P3DX port map (
+D => RHB_WAIT_CNT_S(3),
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_WAIT_CNT(3));
+\RHB_WAIT_CNT[4]_REG_Z520\: FD1P3DX port map (
+D => RHB_WAIT_CNT_S(4),
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_WAIT_CNT(4));
+\RHB_WAIT_CNT[5]_REG_Z522\: FD1P3DX port map (
+D => RHB_WAIT_CNT_S(5),
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_WAIT_CNT(5));
+\RHB_WAIT_CNT[6]_REG_Z524\: FD1P3DX port map (
+D => RHB_WAIT_CNT_S(6),
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_WAIT_CNT(6));
+\RHB_WAIT_CNT[7]_REG_Z526\: FD1P3DX port map (
+D => RHB_WAIT_CNT_S(7),
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_WAIT_CNT(7));
+RHB_SYNC_P2_REG_Z528: FD1S3DX port map (
+D => RHB_SYNC_P1,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_SYNC_P2);
+RHB_SYNC_P1_REG_Z530: FD1S3DX port map (
+D => RHB_SYNC,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_SYNC_P1);
+\RCOUNT[0]_REG_Z532\: FD1S3DX port map (
+D => RCOUNT_S(0),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(0));
+\RCOUNT[1]_REG_Z534\: FD1S3DX port map (
+D => RCOUNT_S(1),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(1));
+\RCOUNT[2]_REG_Z536\: FD1S3DX port map (
+D => RCOUNT_S(2),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(2));
+\RCOUNT[3]_REG_Z538\: FD1S3DX port map (
+D => RCOUNT_S(3),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(3));
+\RCOUNT[4]_REG_Z540\: FD1S3DX port map (
+D => RCOUNT_S(4),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(4));
+\RCOUNT[5]_REG_Z542\: FD1S3DX port map (
+D => RCOUNT_S(5),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(5));
+\RCOUNT[6]_REG_Z544\: FD1S3DX port map (
+D => RCOUNT_S(6),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(6));
+\RCOUNT[7]_REG_Z546\: FD1S3DX port map (
+D => RCOUNT_S(7),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(7));
+\RCOUNT[8]_REG_Z548\: FD1S3DX port map (
+D => RCOUNT_S(8),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(8));
+\RCOUNT[9]_REG_Z550\: FD1S3DX port map (
+D => RCOUNT_S(9),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(9));
+\RCOUNT[10]_REG_Z552\: FD1S3DX port map (
+D => RCOUNT_S(10),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(10));
+\RCOUNT[11]_REG_Z554\: FD1S3DX port map (
+D => RCOUNT_S(11),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(11));
+\RCOUNT[12]_REG_Z556\: FD1S3DX port map (
+D => RCOUNT_S(12),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(12));
+\RCOUNT[13]_REG_Z558\: FD1S3DX port map (
+D => RCOUNT_S(13),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(13));
+\RCOUNT[14]_REG_Z560\: FD1S3DX port map (
+D => RCOUNT_S(14),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(14));
+\RCOUNT[15]_REG_Z562\: FD1S3DX port map (
+D => RCOUNT_S(15),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(15));
+PPUL_SYNC_P3_REG_Z564: FD1S3DX port map (
+D => PPUL_SYNC_P2,
+CK => tx_pclk,
+CD => sli_rst,
+Q => PPUL_SYNC_P3);
+PPUL_SYNC_P2_REG_Z566: FD1S3DX port map (
+D => PPUL_SYNC_P1,
+CK => tx_pclk,
+CD => sli_rst,
+Q => PPUL_SYNC_P2);
+PPUL_SYNC_P1_REG_Z568: FD1S3DX port map (
+D => PPUL_SYNC,
+CK => tx_pclk,
+CD => sli_rst,
+Q => PPUL_SYNC_P1);
+PLL_LOCK_REG_Z570: FD1S3DX port map (
+D => N_53_I,
+CK => pll_refclki,
+CD => sli_rst,
+Q => PLL_LOCK);
+\PHB_CNT[0]_REG_Z572\: FD1S3DX port map (
+D => PHB_CNT_I(0),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PHB_CNT(0));
+\PHB_CNT[1]_REG_Z574\: FD1S3DX port map (
+D => PHB_CNT_RNO(1),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PHB_CNT(1));
+\PHB_CNT[2]_REG_Z576\: FD1S3DX port map (
+D => PHB_CNT_RNO(2),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PHB_CNT(2));
+PHB_REG_Z578: FD1S3DX port map (
+D => PHB_CNT_I(2),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PHB);
+PDIFF_SYNC_P1_REG_Z580: FD1S3DX port map (
+D => PDIFF_SYNC,
+CK => pll_refclki,
+CD => sli_rst,
+Q => PDIFF_SYNC_P1);
+\PCOUNT[0]_REG_Z582\: FD1S3DX port map (
+D => PCOUNT_S(0),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(0));
+\PCOUNT_DIFF[0]_REG_Z584\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_I(0),
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_0);
+\PCOUNT[1]_REG_Z586\: FD1S3DX port map (
+D => PCOUNT_S(1),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(1));
+\PCOUNT_DIFF[1]_REG_Z588\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_1_0_S0,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_1);
+\PCOUNT_DIFF[2]_REG_Z590\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_1_0_S1,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_2);
+\PCOUNT[2]_REG_Z592\: FD1S3DX port map (
+D => PCOUNT_S(2),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(2));
+\PCOUNT_DIFF[3]_REG_Z594\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_3_0_S0,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_3);
+\PCOUNT[3]_REG_Z596\: FD1S3DX port map (
+D => PCOUNT_S(3),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(3));
+\PCOUNT_DIFF[4]_REG_Z598\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_3_0_S1,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_4);
+\PCOUNT[4]_REG_Z600\: FD1S3DX port map (
+D => PCOUNT_S(4),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(4));
+\PCOUNT_DIFF[5]_REG_Z602\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_5_0_S0,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_5);
+\PCOUNT[5]_REG_Z604\: FD1S3DX port map (
+D => PCOUNT_S(5),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(5));
+\PCOUNT[6]_REG_Z606\: FD1S3DX port map (
+D => PCOUNT_S(6),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(6));
+\PCOUNT_DIFF[6]_REG_Z608\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_5_0_S1,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_6);
+\PCOUNT[7]_REG_Z610\: FD1S3DX port map (
+D => PCOUNT_S(7),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(7));
+\PCOUNT_DIFF[7]_REG_Z612\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_7_0_S0,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_7);
+\PCOUNT[8]_REG_Z614\: FD1S3DX port map (
+D => PCOUNT_S(8),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(8));
+\PCOUNT_DIFF[8]_REG_Z616\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_7_0_S1,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_8);
+\PCOUNT_DIFF[9]_REG_Z618\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_9_0_S0,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_9);
+\PCOUNT[9]_REG_Z620\: FD1S3DX port map (
+D => PCOUNT_S(9),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(9));
+\PCOUNT[10]_REG_Z622\: FD1S3DX port map (
+D => PCOUNT_S(10),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(10));
+\PCOUNT_DIFF[10]_REG_Z624\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_9_0_S1,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_10);
+\PCOUNT_DIFF[11]_REG_Z626\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_11_0_S0,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_11);
+\PCOUNT[11]_REG_Z628\: FD1S3DX port map (
+D => PCOUNT_S(11),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(11));
+\PCOUNT[12]_REG_Z630\: FD1S3DX port map (
+D => PCOUNT_S(12),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(12));
+\PCOUNT_DIFF[12]_REG_Z632\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_11_0_S1,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_12);
+\PCOUNT_DIFF[13]_REG_Z634\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_13_0_S0,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_13);
+\PCOUNT[13]_REG_Z636\: FD1S3DX port map (
+D => PCOUNT_S(13),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(13));
+\PCOUNT_DIFF[14]_REG_Z638\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_13_0_S1,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_14);
+\PCOUNT[14]_REG_Z640\: FD1S3DX port map (
+D => PCOUNT_S(14),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(14));
+\PCOUNT[15]_REG_Z642\: FD1S3DX port map (
+D => PCOUNT_S(15),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(15));
+\PCOUNT_DIFF[15]_REG_Z644\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_15_0_S0,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_15);
+\PCOUNT[16]_REG_Z646\: FD1S3DX port map (
+D => PCOUNT_S(16),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(16));
+\PCOUNT_DIFF[16]_REG_Z648\: FD1P3DX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_15_0_S1,
+SP => N_7,
+CK => tx_pclk,
+CD => sli_rst,
+Q => UN13_LOCK_16);
+\PCOUNT_DIFF[17]_REG_Z650\: FD1P3DX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_17_0_S0,
+SP => N_7,
+CK => tx_pclk,
+CD => sli_rst,
+Q => UN13_LOCK_17);
+\PCOUNT[17]_REG_Z652\: FD1S3DX port map (
+D => PCOUNT_S(17),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(17));
+\PCOUNT_DIFF[18]_REG_Z654\: FD1P3DX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_17_0_S1,
+SP => N_7,
+CK => tx_pclk,
+CD => sli_rst,
+Q => UN13_LOCK_18);
+\PCOUNT[18]_REG_Z656\: FD1S3DX port map (
+D => PCOUNT_S(18),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(18));
+\PCOUNT[19]_REG_Z658\: FD1S3DX port map (
+D => PCOUNT_S(19),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(19));
+\PCOUNT_DIFF[19]_REG_Z660\: FD1P3DX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_19_0_S0,
+SP => N_7,
+CK => tx_pclk,
+CD => sli_rst,
+Q => UN13_LOCK_19);
+\PCOUNT[20]_REG_Z662\: FD1S3DX port map (
+D => PCOUNT_S(20),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(20));
+\PCOUNT_DIFF[20]_REG_Z664\: FD1P3DX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_19_0_S1,
+SP => N_7,
+CK => tx_pclk,
+CD => sli_rst,
+Q => UN13_LOCK_20);
+\PCOUNT_DIFF[21]_REG_Z666\: FD1P3DX port map (
+D => UN1_PCOUNT_DIFF_1_S_21_0_S0,
+SP => N_7,
+CK => tx_pclk,
+CD => sli_rst,
+Q => UN13_LOCK_21);
+\PCOUNT[21]_REG_Z668\: FD1S3DX port map (
+D => PCOUNT_S(21),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(21));
+LOCK_REG_Z670: FD1P3DX port map (
+D => LOCK_5,
+SP => LOCK_1_SQMUXA_I,
+CK => pll_refclki,
+CD => sli_rst,
+Q => LOCK);
+\GENBLK5.RDIFF_COMP_LOCK[2]_REG_Z672\: FD1S3DX port map (
+D => VCC,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RDIFF_COMP_LOCK(2));
+\SLL_STATE_RNO[0]\: LUT4 
+generic map(
+  init => X"E050"
+)
+port map (
+A => N_98,
+B => LOCK,
+C => RSTAT_PCLK,
+D => SLL_STATE(0),
+Z => N_95_I);
+RTC_PUL5_0_0: LUT4 
+generic map(
+  init => X"FF80"
+)
+port map (
+A => RTC_PUL5_0_O3,
+B => RTC_PUL5_0_A3_6,
+C => RTC_PUL5_0_A3_7,
+D => UN1_RCOUNT_1_0_A3,
+Z => RTC_PUL5);
+RSTAT_PCLK_2_IV: LUT4 
+generic map(
+  init => X"AEEE"
+)
+port map (
+A => RHB_WAIT_CNT12,
+B => RSTAT_PCLK,
+C => UN1_RHB_WAIT_CNT_4,
+D => UN1_RHB_WAIT_CNT_5,
+Z => RSTAT_PCLK_2);
+\SLL_STATE_RNO[1]\: LUT4 
+generic map(
+  init => X"8088"
+)
+port map (
+A => N_99,
+B => RSTAT_PCLK,
+C => SLL_STATE(1),
+D => UNLOCK,
+Z => N_97_I);
+RTC_CTRL4_0_A3: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RTC_CTRL4_0_A3_1,
+B => RTC_CTRL4_0_A3_12_4,
+C => RTC_CTRL4_0_A3_12_5,
+D => RTC_CTRL4_10,
+Z => RTC_CTRL4);
+UN1_RCOUNT_1_0_A3_Z678: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RTC_CTRL4_0_A3_12_4,
+B => RTC_CTRL4_0_A3_12_5,
+C => RTC_CTRL4_10,
+D => UN1_RCOUNT_1_0_A3_1,
+Z => UN1_RCOUNT_1_0_A3);
+LOCK_1_SQMUXA_I_Z679: LUT4 
+generic map(
+  init => X"7575"
+)
+port map (
+A => LOCK,
+B => PDIFF_SYNC,
+C => PDIFF_SYNC_P1,
+D => VCC,
+Z => LOCK_1_SQMUXA_I);
+UNLOCK_1_SQMUXA_I_Z680: LUT4 
+generic map(
+  init => X"4F4F"
+)
+port map (
+A => PDIFF_SYNC,
+B => PDIFF_SYNC_P1,
+C => UNLOCK,
+D => VCC,
+Z => UNLOCK_1_SQMUXA_I);
+RTC_PUL5_0_O3_Z681: LUT4 
+generic map(
+  init => X"AAAB"
+)
+port map (
+A => N_6,
+B => RCOUNT(1),
+C => RCOUNT(2),
+D => RCOUNT(3),
+Z => RTC_PUL5_0_O3);
+RTC_PUL5_0_A3_7_Z682: LUT4 
+generic map(
+  init => X"1010"
+)
+port map (
+A => RCOUNT(7),
+B => RCOUNT(8),
+C => RTC_PUL5_0_A3_5,
+D => VCC,
+Z => RTC_PUL5_0_A3_7);
+\SLL_STATE_NS_I_M4[1]\: LUT4 
+generic map(
+  init => X"EF20"
+)
+port map (
+A => LOCK,
+B => RTC_PUL,
+C => RTC_PUL_P1,
+D => SLL_STATE(1),
+Z => N_99);
+PLL_LOCK_RNO: LUT4 
+generic map(
+  init => X"8888"
+)
+port map (
+A => SLL_STATE(0),
+B => SLL_STATE(1),
+C => VCC,
+D => VCC,
+Z => N_53_I);
+\PHB_CNT_RNO[2]_Z685\: LUT4 
+generic map(
+  init => X"7878"
+)
+port map (
+A => PHB_CNT(0),
+B => PHB_CNT(1),
+C => PHB_CNT(2),
+D => VCC,
+Z => PHB_CNT_RNO(2));
+\SLL_STATE_NS_I_O4[0]\: LUT4 
+generic map(
+  init => X"BFBF"
+)
+port map (
+A => RTC_PUL,
+B => RTC_PUL_P1,
+C => SLL_STATE(1),
+D => VCC,
+Z => N_98);
+RTC_CTRL4_0_A3_10: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RCOUNT(1),
+B => RCOUNT(3),
+C => RCOUNT(6),
+D => RCOUNT(15),
+Z => RTC_CTRL4_10);
+UN1_RHB_WAIT_CNT_4_Z688: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RHB_WAIT_CNT(4),
+B => RHB_WAIT_CNT(5),
+C => RHB_WAIT_CNT(6),
+D => RHB_WAIT_CNT(7),
+Z => UN1_RHB_WAIT_CNT_4);
+UN1_RHB_WAIT_CNT_5_Z689: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RHB_WAIT_CNT(0),
+B => RHB_WAIT_CNT(1),
+C => RHB_WAIT_CNT(2),
+D => RHB_WAIT_CNT(3),
+Z => UN1_RHB_WAIT_CNT_5);
+RTC_CTRL4_0_A3_12_4_Z690: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RCOUNT(11),
+B => RCOUNT(12),
+C => RCOUNT(13),
+D => RCOUNT(14),
+Z => RTC_CTRL4_0_A3_12_4);
+RTC_CTRL4_0_A3_12_5_Z691: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RCOUNT(7),
+B => RCOUNT(8),
+C => RCOUNT(9),
+D => RCOUNT(10),
+Z => RTC_CTRL4_0_A3_12_5);
+RTC_PUL5_0_A3_5_Z692: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RCOUNT(6),
+B => RCOUNT(13),
+C => RCOUNT(14),
+D => RCOUNT(15),
+Z => RTC_PUL5_0_A3_5);
+RTC_PUL5_0_A3_6_Z693: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RCOUNT(9),
+B => RCOUNT(10),
+C => RCOUNT(11),
+D => RCOUNT(12),
+Z => RTC_PUL5_0_A3_6);
+PCOUNT10_0_O3: LUT4 
+generic map(
+  init => X"DDDD"
+)
+port map (
+A => PPUL_SYNC_P1,
+B => PPUL_SYNC_P2,
+C => VCC,
+D => VCC,
+Z => N_8);
+\PHB_CNT_RNO[1]_Z695\: LUT4 
+generic map(
+  init => X"6666"
+)
+port map (
+A => PHB_CNT(0),
+B => PHB_CNT(1),
+C => VCC,
+D => VCC,
+Z => PHB_CNT_RNO(1));
+RTC_CTRL4_0_O3: LUT4 
+generic map(
+  init => X"7777"
+)
+port map (
+A => RCOUNT(4),
+B => RCOUNT(5),
+C => VCC,
+D => VCC,
+Z => N_6);
+UNLOCK_5_Z697: LUT4 
+generic map(
+  init => X"8888"
+)
+port map (
+A => PDIFF_SYNC,
+B => UN13_UNLOCK_CRY_21,
+C => VCC,
+D => VCC,
+Z => UNLOCK_5);
+LOCK_5_Z698: LUT4 
+generic map(
+  init => X"8888"
+)
+port map (
+A => PDIFF_SYNC,
+B => UN13_LOCK_CRY_21_I,
+C => VCC,
+D => VCC,
+Z => LOCK_5);
+RHB_WAIT_CNT12_Z699: LUT4 
+generic map(
+  init => X"2222"
+)
+port map (
+A => RHB_SYNC_P1,
+B => RHB_SYNC_P2,
+C => VCC,
+D => VCC,
+Z => RHB_WAIT_CNT12);
+\UN1_PCOUNT_DIFF[0]_Z700\: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_0,
+B => PCOUNT(0),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF(0));
+UN1_RCOUNT_1_0_A3_1_Z701: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RCOUNT(2),
+B => RCOUNT(0),
+C => RCOUNT(5),
+D => RCOUNT(4),
+Z => UN1_RCOUNT_1_0_A3_1);
+RHB_SYNC_P2_RNIU9TG1: LUT4 
+generic map(
+  init => X"7077"
+)
+port map (
+A => UN1_RHB_WAIT_CNT_5,
+B => UN1_RHB_WAIT_CNT_4,
+C => RHB_SYNC_P2,
+D => RHB_SYNC_P1,
+Z => \RHB_WAIT_CNT_\);
+\PCOUNT_CRY_0[0]\: CCU2C 
+generic map(
+  INIT0 => X"500c",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => N_8,
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_9,
+COUT => PCOUNT_CRY(0),
+S0 => PCOUNT_CRY_0_S0(0),
+S1 => PCOUNT_S(0));
+\PCOUNT_CRY_0[1]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(1),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(2),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(0),
+COUT => PCOUNT_CRY(2),
+S0 => PCOUNT_S(1),
+S1 => PCOUNT_S(2));
+\PCOUNT_CRY_0[3]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(3),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(4),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(2),
+COUT => PCOUNT_CRY(4),
+S0 => PCOUNT_S(3),
+S1 => PCOUNT_S(4));
+\PCOUNT_CRY_0[5]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(5),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(6),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(4),
+COUT => PCOUNT_CRY(6),
+S0 => PCOUNT_S(5),
+S1 => PCOUNT_S(6));
+\PCOUNT_CRY_0[7]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(7),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(8),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(6),
+COUT => PCOUNT_CRY(8),
+S0 => PCOUNT_S(7),
+S1 => PCOUNT_S(8));
+\PCOUNT_CRY_0[9]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(9),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(10),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(8),
+COUT => PCOUNT_CRY(10),
+S0 => PCOUNT_S(9),
+S1 => PCOUNT_S(10));
+\PCOUNT_CRY_0[11]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(11),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(12),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(10),
+COUT => PCOUNT_CRY(12),
+S0 => PCOUNT_S(11),
+S1 => PCOUNT_S(12));
+\PCOUNT_CRY_0[13]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(13),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(14),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(12),
+COUT => PCOUNT_CRY(14),
+S0 => PCOUNT_S(13),
+S1 => PCOUNT_S(14));
+\PCOUNT_CRY_0[15]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(15),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(16),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(14),
+COUT => PCOUNT_CRY(16),
+S0 => PCOUNT_S(15),
+S1 => PCOUNT_S(16));
+\PCOUNT_CRY_0[17]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(17),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(18),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(16),
+COUT => PCOUNT_CRY(18),
+S0 => PCOUNT_S(17),
+S1 => PCOUNT_S(18));
+\PCOUNT_CRY_0[19]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(19),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(20),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(18),
+COUT => PCOUNT_CRY(20),
+S0 => PCOUNT_S(19),
+S1 => PCOUNT_S(20));
+\PCOUNT_S_0[21]\: CCU2C 
+generic map(
+  INIT0 => X"800a",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(21),
+C0 => VCC,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(20),
+COUT => PCOUNT_S_0_COUT(21),
+S0 => PCOUNT_S(21),
+S1 => PCOUNT_S_0_S1(21));
+\RCOUNT_CRY_0[0]\: CCU2C 
+generic map(
+  INIT0 => X"5003",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => UN1_RCOUNT_1_0_A3,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_RCOUNT_1_0_A3,
+B1 => RCOUNT(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_5,
+COUT => RCOUNT_CRY(0),
+S0 => RCOUNT_CRY_0_S0(0),
+S1 => RCOUNT_S(0));
+\RCOUNT_CRY_0[1]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RCOUNT_1_0_A3,
+B0 => RCOUNT(1),
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_RCOUNT_1_0_A3,
+B1 => RCOUNT(2),
+C1 => VCC,
+D1 => VCC,
+CIN => RCOUNT_CRY(0),
+COUT => RCOUNT_CRY(2),
+S0 => RCOUNT_S(1),
+S1 => RCOUNT_S(2));
+\RCOUNT_CRY_0[3]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RCOUNT_1_0_A3,
+B0 => RCOUNT(3),
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_RCOUNT_1_0_A3,
+B1 => RCOUNT(4),
+C1 => VCC,
+D1 => VCC,
+CIN => RCOUNT_CRY(2),
+COUT => RCOUNT_CRY(4),
+S0 => RCOUNT_S(3),
+S1 => RCOUNT_S(4));
+\RCOUNT_CRY_0[5]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RCOUNT_1_0_A3,
+B0 => RCOUNT(5),
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_RCOUNT_1_0_A3,
+B1 => RCOUNT(6),
+C1 => VCC,
+D1 => VCC,
+CIN => RCOUNT_CRY(4),
+COUT => RCOUNT_CRY(6),
+S0 => RCOUNT_S(5),
+S1 => RCOUNT_S(6));
+\RCOUNT_CRY_0[7]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RCOUNT_1_0_A3,
+B0 => RCOUNT(7),
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_RCOUNT_1_0_A3,
+B1 => RCOUNT(8),
+C1 => VCC,
+D1 => VCC,
+CIN => RCOUNT_CRY(6),
+COUT => RCOUNT_CRY(8),
+S0 => RCOUNT_S(7),
+S1 => RCOUNT_S(8));
+\RCOUNT_CRY_0[9]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RCOUNT_1_0_A3,
+B0 => RCOUNT(9),
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_RCOUNT_1_0_A3,
+B1 => RCOUNT(10),
+C1 => VCC,
+D1 => VCC,
+CIN => RCOUNT_CRY(8),
+COUT => RCOUNT_CRY(10),
+S0 => RCOUNT_S(9),
+S1 => RCOUNT_S(10));
+\RCOUNT_CRY_0[11]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RCOUNT_1_0_A3,
+B0 => RCOUNT(11),
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_RCOUNT_1_0_A3,
+B1 => RCOUNT(12),
+C1 => VCC,
+D1 => VCC,
+CIN => RCOUNT_CRY(10),
+COUT => RCOUNT_CRY(12),
+S0 => RCOUNT_S(11),
+S1 => RCOUNT_S(12));
+\RCOUNT_CRY_0[13]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RCOUNT_1_0_A3,
+B0 => RCOUNT(13),
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_RCOUNT_1_0_A3,
+B1 => RCOUNT(14),
+C1 => VCC,
+D1 => VCC,
+CIN => RCOUNT_CRY(12),
+COUT => RCOUNT_CRY(14),
+S0 => RCOUNT_S(13),
+S1 => RCOUNT_S(14));
+\RCOUNT_S_0[15]\: CCU2C 
+generic map(
+  INIT0 => X"4005",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RCOUNT_1_0_A3,
+B0 => RCOUNT(15),
+C0 => VCC,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => RCOUNT_CRY(14),
+COUT => RCOUNT_S_0_COUT(15),
+S0 => RCOUNT_S(15),
+S1 => RCOUNT_S_0_S1(15));
+\RHB_WAIT_CNT_CRY_0[0]\: CCU2C 
+generic map(
+  INIT0 => X"500c",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => \RHB_WAIT_CNT_\,
+C0 => VCC,
+D0 => VCC,
+A1 => \RHB_WAIT_CNT_\,
+B1 => RHB_WAIT_CNT(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_4,
+COUT => RHB_WAIT_CNT_CRY(0),
+S0 => RHB_WAIT_CNT_CRY_0_S0(0),
+S1 => RHB_WAIT_CNT_S(0));
+\RHB_WAIT_CNT_CRY_0[1]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RHB_WAIT_CNT_\,
+B0 => RHB_WAIT_CNT(1),
+C0 => VCC,
+D0 => VCC,
+A1 => \RHB_WAIT_CNT_\,
+B1 => RHB_WAIT_CNT(2),
+C1 => VCC,
+D1 => VCC,
+CIN => RHB_WAIT_CNT_CRY(0),
+COUT => RHB_WAIT_CNT_CRY(2),
+S0 => RHB_WAIT_CNT_S(1),
+S1 => RHB_WAIT_CNT_S(2));
+\RHB_WAIT_CNT_CRY_0[3]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RHB_WAIT_CNT_\,
+B0 => RHB_WAIT_CNT(3),
+C0 => VCC,
+D0 => VCC,
+A1 => \RHB_WAIT_CNT_\,
+B1 => RHB_WAIT_CNT(4),
+C1 => VCC,
+D1 => VCC,
+CIN => RHB_WAIT_CNT_CRY(2),
+COUT => RHB_WAIT_CNT_CRY(4),
+S0 => RHB_WAIT_CNT_S(3),
+S1 => RHB_WAIT_CNT_S(4));
+\RHB_WAIT_CNT_CRY_0[5]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RHB_WAIT_CNT_\,
+B0 => RHB_WAIT_CNT(5),
+C0 => VCC,
+D0 => VCC,
+A1 => \RHB_WAIT_CNT_\,
+B1 => RHB_WAIT_CNT(6),
+C1 => VCC,
+D1 => VCC,
+CIN => RHB_WAIT_CNT_CRY(4),
+COUT => RHB_WAIT_CNT_CRY(6),
+S0 => RHB_WAIT_CNT_S(5),
+S1 => RHB_WAIT_CNT_S(6));
+\RHB_WAIT_CNT_S_0[7]\: CCU2C 
+generic map(
+  INIT0 => X"800a",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RHB_WAIT_CNT_\,
+B0 => RHB_WAIT_CNT(7),
+C0 => VCC,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => RHB_WAIT_CNT_CRY(6),
+COUT => RHB_WAIT_CNT_S_0_COUT(7),
+S0 => RHB_WAIT_CNT_S(7),
+S1 => RHB_WAIT_CNT_S_0_S1(7));
+UN1_PCOUNT_DIFF_1_CRY_0_0: CCU2C 
+generic map(
+  INIT0 => X"5003",
+  INIT1 => X"500f",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF(0),
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => N_3,
+COUT => UN1_PCOUNT_DIFF_1_CRY_0,
+S0 => UN1_PCOUNT_DIFF_1_CRY_0_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_0_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_1_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_1,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_2,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_0,
+COUT => UN1_PCOUNT_DIFF_1_CRY_2,
+S0 => UN1_PCOUNT_DIFF_1_CRY_1_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_1_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_3_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_3,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_4,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_2,
+COUT => UN1_PCOUNT_DIFF_1_CRY_4,
+S0 => UN1_PCOUNT_DIFF_1_CRY_3_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_3_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_5_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_5,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_6,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_4,
+COUT => UN1_PCOUNT_DIFF_1_CRY_6,
+S0 => UN1_PCOUNT_DIFF_1_CRY_5_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_5_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_7_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_7,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_8,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_6,
+COUT => UN1_PCOUNT_DIFF_1_CRY_8,
+S0 => UN1_PCOUNT_DIFF_1_CRY_7_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_7_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_9_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_9,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_10,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_8,
+COUT => UN1_PCOUNT_DIFF_1_CRY_10,
+S0 => UN1_PCOUNT_DIFF_1_CRY_9_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_9_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_11_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_11,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_12,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_10,
+COUT => UN1_PCOUNT_DIFF_1_CRY_12,
+S0 => UN1_PCOUNT_DIFF_1_CRY_11_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_11_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_13_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_13,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_14,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_12,
+COUT => UN1_PCOUNT_DIFF_1_CRY_14,
+S0 => UN1_PCOUNT_DIFF_1_CRY_13_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_13_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_15_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_15,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_16,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_14,
+COUT => UN1_PCOUNT_DIFF_1_CRY_16,
+S0 => UN1_PCOUNT_DIFF_1_CRY_15_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_15_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_17_0: CCU2C 
+generic map(
+  INIT0 => X"b404",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => RDIFF_COMP_LOCK(2),
+C0 => UN1_PCOUNT_DIFF_1_CRY_17_0_RNO,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_18,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_16,
+COUT => UN1_PCOUNT_DIFF_1_CRY_18,
+S0 => UN1_PCOUNT_DIFF_1_CRY_17_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_17_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_19_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_19,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_20,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_18,
+COUT => UN1_PCOUNT_DIFF_1_CRY_20,
+S0 => UN1_PCOUNT_DIFF_1_CRY_19_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_19_0_S1);
+UN1_PCOUNT_DIFF_1_S_21_0: CCU2C 
+generic map(
+  INIT0 => X"350a",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => PCOUNT(21),
+B0 => UN13_LOCK_21,
+C0 => N_8,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_20,
+COUT => UN1_PCOUNT_DIFF_1_S_21_0_COUT,
+S0 => UN1_PCOUNT_DIFF_1_S_21_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_S_21_0_S1);
+UN13_LOCK_CRY_0_0: CCU2C 
+generic map(
+  INIT0 => X"5003",
+  INIT1 => X"900a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_0,
+B1 => RDIFF_COMP_LOCK(2),
+C1 => VCC,
+D1 => VCC,
+CIN => N_2,
+COUT => UN13_LOCK_CRY_0,
+S0 => UN13_LOCK_CRY_0_0_S0,
+S1 => UN13_LOCK_CRY_0_0_S1);
+UN13_LOCK_CRY_1_0: CCU2C 
+generic map(
+  INIT0 => X"900a",
+  INIT1 => X"900a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_1,
+B0 => RDIFF_COMP_LOCK(2),
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_2,
+B1 => RDIFF_COMP_LOCK(2),
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_0,
+COUT => UN13_LOCK_CRY_2,
+S0 => UN13_LOCK_CRY_1_0_S0,
+S1 => UN13_LOCK_CRY_1_0_S1);
+UN13_LOCK_CRY_3_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_3,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_4,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_2,
+COUT => UN13_LOCK_CRY_4,
+S0 => UN13_LOCK_CRY_3_0_S0,
+S1 => UN13_LOCK_CRY_3_0_S1);
+UN13_LOCK_CRY_5_0: CCU2C 
+generic map(
+  INIT0 => X"900a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_5,
+B0 => RDIFF_COMP_LOCK(2),
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_6,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_4,
+COUT => UN13_LOCK_CRY_6,
+S0 => UN13_LOCK_CRY_5_0_S0,
+S1 => UN13_LOCK_CRY_5_0_S1);
+UN13_LOCK_CRY_7_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_7,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_8,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_6,
+COUT => UN13_LOCK_CRY_8,
+S0 => UN13_LOCK_CRY_7_0_S0,
+S1 => UN13_LOCK_CRY_7_0_S1);
+UN13_LOCK_CRY_9_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_9,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_10,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_8,
+COUT => UN13_LOCK_CRY_10,
+S0 => UN13_LOCK_CRY_9_0_S0,
+S1 => UN13_LOCK_CRY_9_0_S1);
+UN13_LOCK_CRY_11_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_11,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_12,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_10,
+COUT => UN13_LOCK_CRY_12,
+S0 => UN13_LOCK_CRY_11_0_S0,
+S1 => UN13_LOCK_CRY_11_0_S1);
+UN13_LOCK_CRY_13_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_13,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_14,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_12,
+COUT => UN13_LOCK_CRY_14,
+S0 => UN13_LOCK_CRY_13_0_S0,
+S1 => UN13_LOCK_CRY_13_0_S1);
+UN13_LOCK_CRY_15_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_15,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_16,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_14,
+COUT => UN13_LOCK_CRY_16,
+S0 => UN13_LOCK_CRY_15_0_S0,
+S1 => UN13_LOCK_CRY_15_0_S1);
+UN13_LOCK_CRY_17_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_17,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_18,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_16,
+COUT => UN13_LOCK_CRY_18,
+S0 => UN13_LOCK_CRY_17_0_S0,
+S1 => UN13_LOCK_CRY_17_0_S1);
+UN13_LOCK_CRY_19_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_19,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_20,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_18,
+COUT => UN13_LOCK_CRY_20,
+S0 => UN13_LOCK_CRY_19_0_S0,
+S1 => UN13_LOCK_CRY_19_0_S1);
+UN13_LOCK_CRY_21_0: CCU2C 
+generic map(
+  INIT0 => X"500f",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_21,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_20,
+COUT => UN13_LOCK_CRY_21_0_COUT,
+S0 => UN13_LOCK_CRY_21_0_S0,
+S1 => UN13_LOCK_CRY_21_I);
+UN13_UNLOCK_CRY_0_0: CCU2C 
+generic map(
+  INIT0 => X"5003",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_0,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => N_1,
+COUT => UN13_UNLOCK_CRY_0,
+S0 => UN13_UNLOCK_CRY_0_0_S0,
+S1 => UN13_UNLOCK_CRY_0_0_S1);
+UN13_UNLOCK_CRY_1_0: CCU2C 
+generic map(
+  INIT0 => X"900a",
+  INIT1 => X"900a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_1,
+B0 => RDIFF_COMP_LOCK(2),
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_2,
+B1 => RDIFF_COMP_LOCK(2),
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_0,
+COUT => UN13_UNLOCK_CRY_2,
+S0 => UN13_UNLOCK_CRY_1_0_S0,
+S1 => UN13_UNLOCK_CRY_1_0_S1);
+UN13_UNLOCK_CRY_3_0: CCU2C 
+generic map(
+  INIT0 => X"900a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_3,
+B0 => RDIFF_COMP_LOCK(2),
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_4,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_2,
+COUT => UN13_UNLOCK_CRY_4,
+S0 => UN13_UNLOCK_CRY_3_0_S0,
+S1 => UN13_UNLOCK_CRY_3_0_S1);
+UN13_UNLOCK_CRY_5_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"900a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_5,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_6,
+B1 => RDIFF_COMP_LOCK(2),
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_4,
+COUT => UN13_UNLOCK_CRY_6,
+S0 => UN13_UNLOCK_CRY_5_0_S0,
+S1 => UN13_UNLOCK_CRY_5_0_S1);
+UN13_UNLOCK_CRY_7_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_7,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_8,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_6,
+COUT => UN13_UNLOCK_CRY_8,
+S0 => UN13_UNLOCK_CRY_7_0_S0,
+S1 => UN13_UNLOCK_CRY_7_0_S1);
+UN13_UNLOCK_CRY_9_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_9,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_10,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_8,
+COUT => UN13_UNLOCK_CRY_10,
+S0 => UN13_UNLOCK_CRY_9_0_S0,
+S1 => UN13_UNLOCK_CRY_9_0_S1);
+UN13_UNLOCK_CRY_11_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_11,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_12,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_10,
+COUT => UN13_UNLOCK_CRY_12,
+S0 => UN13_UNLOCK_CRY_11_0_S0,
+S1 => UN13_UNLOCK_CRY_11_0_S1);
+UN13_UNLOCK_CRY_13_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_13,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_14,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_12,
+COUT => UN13_UNLOCK_CRY_14,
+S0 => UN13_UNLOCK_CRY_13_0_S0,
+S1 => UN13_UNLOCK_CRY_13_0_S1);
+UN13_UNLOCK_CRY_15_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_15,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_16,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_14,
+COUT => UN13_UNLOCK_CRY_16,
+S0 => UN13_UNLOCK_CRY_15_0_S0,
+S1 => UN13_UNLOCK_CRY_15_0_S1);
+UN13_UNLOCK_CRY_17_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_17,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_18,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_16,
+COUT => UN13_UNLOCK_CRY_18,
+S0 => UN13_UNLOCK_CRY_17_0_S0,
+S1 => UN13_UNLOCK_CRY_17_0_S1);
+UN13_UNLOCK_CRY_19_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_19,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_20,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_18,
+COUT => UN13_UNLOCK_CRY_20,
+S0 => UN13_UNLOCK_CRY_19_0_S0,
+S1 => UN13_UNLOCK_CRY_19_0_S1);
+UN13_UNLOCK_CRY_21_0: CCU2C 
+generic map(
+  INIT0 => X"500f",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_21,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_20,
+COUT => UN13_UNLOCK_CRY_21_0_COUT,
+S0 => UN13_UNLOCK_CRY_21_0_S0,
+S1 => UN13_UNLOCK_CRY_21);
+PHB_SYNC_INST: sync_0s port map (
+phb => PHB,
+rhb_sync => RHB_SYNC,
+sli_rst => sli_rst,
+pll_refclki => pll_refclki);
+RTC_SYNC_INST: sync_0s_6 port map (
+rtc_pul => RTC_PUL,
+ppul_sync => PPUL_SYNC,
+sli_rst => sli_rst,
+tx_pclk => tx_pclk);
+PDIFF_SYNC_INST: sync_0s_0 port map (
+ppul_sync => PPUL_SYNC,
+pdiff_sync => PDIFF_SYNC,
+sli_rst => sli_rst,
+pll_refclki => pll_refclki);
+VCC_0: VHI port map (
+Z => VCC);
+II_GND: VLO port map (
+Z => GND);
+end beh;
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library synplify;
+use synplify.components.all;
+library pmi;
+use pmi.pmi_components.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity sgmii_ecp5 is
+port(
+hdoutp :  out std_logic;
+hdoutn :  out std_logic;
+hdinp :  in std_logic;
+hdinn :  in std_logic;
+rxrefclk :  in std_logic;
+tx_pclk :  out std_logic;
+txi_clk :  in std_logic;
+txdata : in std_logic_vector(7 downto 0);
+tx_k : in std_logic_vector(0 downto 0);
+xmit : in std_logic_vector(0 downto 0);
+tx_disp_correct : in std_logic_vector(0 downto 0);
+rxdata : out std_logic_vector(7 downto 0);
+rx_k : out std_logic_vector(0 downto 0);
+rx_disp_err : out std_logic_vector(0 downto 0);
+rx_cv_err : out std_logic_vector(0 downto 0);
+signal_detect_c :  in std_logic;
+rx_los_low_s :  out std_logic;
+lsm_status_s :  out std_logic;
+ctc_urun_s :  out std_logic;
+ctc_orun_s :  out std_logic;
+rx_cdr_lol_s :  out std_logic;
+ctc_ins_s :  out std_logic;
+ctc_del_s :  out std_logic;
+sli_rst :  in std_logic;
+tx_pwrup_c :  in std_logic;
+rx_pwrup_c :  in std_logic;
+sci_wrdata : in std_logic_vector(7 downto 0);
+sci_addr : in std_logic_vector(5 downto 0);
+sci_rddata : out std_logic_vector(7 downto 0);
+sci_en_dual :  in std_logic;
+sci_sel_dual :  in std_logic;
+sci_en :  in std_logic;
+sci_sel :  in std_logic;
+sci_rd :  in std_logic;
+sci_wrn :  in std_logic;
+sci_int :  out std_logic;
+cyawstn :  in std_logic;
+serdes_pdb :  in std_logic;
+pll_refclki :  in std_logic;
+rsl_disable :  in std_logic;
+rsl_rst :  in std_logic;
+serdes_rst_dual_c :  in std_logic;
+rst_dual_c :  in std_logic;
+tx_serdes_rst_c :  in std_logic;
+tx_pcs_rst_c :  in std_logic;
+pll_lol :  out std_logic;
+rsl_tx_rdy :  out std_logic;
+rx_serdes_rst_c :  in std_logic;
+rx_pcs_rst_c :  in std_logic;
+rsl_rx_rdy :  out std_logic);
+end sgmii_ecp5;
+
+architecture beh of sgmii_ecp5 is
+signal TX_PCLK_11 : std_logic ;
+signal RX_LOS_LOW_S_12 : std_logic ;
+signal RX_CDR_LOL_S_13 : std_logic ;
+signal RSL_TX_PCS_RST_C : std_logic ;
+signal RSL_RX_PCS_RST_C : std_logic ;
+signal RSL_RX_SERDES_RST_C : std_logic ;
+signal RSL_SERDES_RST_DUAL_C : std_logic ;
+signal RSL_TX_SERDES_RST_C : std_logic ;
+signal N47_1 : std_logic ;
+signal N48_1 : std_logic ;
+signal N1_1 : std_logic ;
+signal N2_1 : std_logic ;
+signal N3_1 : std_logic ;
+signal N4_1 : std_logic ;
+signal N5_1 : std_logic ;
+signal N49_1 : std_logic ;
+signal N6_1 : std_logic ;
+signal N50_1 : std_logic ;
+signal N7_1 : std_logic ;
+signal N51_1 : std_logic ;
+signal N8_1 : std_logic ;
+signal N52_1 : std_logic ;
+signal N9_1 : std_logic ;
+signal N53_1 : std_logic ;
+signal N54_1 : std_logic ;
+signal N55_1 : std_logic ;
+signal N56_1 : std_logic ;
+signal N57_1 : std_logic ;
+signal N58_1 : std_logic ;
+signal N59_1 : std_logic ;
+signal N60_1 : std_logic ;
+signal N61_1 : std_logic ;
+signal N62_1 : std_logic ;
+signal N63_1 : std_logic ;
+signal N64_1 : std_logic ;
+signal N65_1 : std_logic ;
+signal N10_1 : std_logic ;
+signal N66_1 : std_logic ;
+signal N67_1 : std_logic ;
+signal N68_1 : std_logic ;
+signal N69_1 : std_logic ;
+signal N70_1 : std_logic ;
+signal N71_1 : std_logic ;
+signal N72_1 : std_logic ;
+signal N73_1 : std_logic ;
+signal N74_1 : std_logic ;
+signal N75_1 : std_logic ;
+signal N76_1 : std_logic ;
+signal N77_1 : std_logic ;
+signal N78_1 : std_logic ;
+signal N79_1 : std_logic ;
+signal N80_1 : std_logic ;
+signal N81_1 : std_logic ;
+signal N82_1 : std_logic ;
+signal N83_1 : std_logic ;
+signal N84_1 : std_logic ;
+signal N85_1 : std_logic ;
+signal N86_1 : std_logic ;
+signal N87_1 : std_logic ;
+signal N88_1 : std_logic ;
+signal N11_1 : std_logic ;
+signal N89_1 : std_logic ;
+signal N12_1 : std_logic ;
+signal N90_1 : std_logic ;
+signal N13_1 : std_logic ;
+signal N91_1 : std_logic ;
+signal N92_1 : std_logic ;
+signal N93_1 : std_logic ;
+signal N94_1 : std_logic ;
+signal N95_1 : std_logic ;
+signal N14_1 : std_logic ;
+signal N96_1 : std_logic ;
+signal N15_1 : std_logic ;
+signal N97_1 : std_logic ;
+signal N98_1 : std_logic ;
+signal N99_1 : std_logic ;
+signal N100_1 : std_logic ;
+signal N101_1 : std_logic ;
+signal N112_1 : std_logic ;
+signal N16_1 : std_logic ;
+signal N17_1 : std_logic ;
+signal N18_1 : std_logic ;
+signal N19_1 : std_logic ;
+signal N20_1 : std_logic ;
+signal N21_1 : std_logic ;
+signal N22_1 : std_logic ;
+signal N23_1 : std_logic ;
+signal N24_1 : std_logic ;
+signal N25_1 : std_logic ;
+signal N26_1 : std_logic ;
+signal N27_1 : std_logic ;
+signal N28_1 : std_logic ;
+signal N29_1 : std_logic ;
+signal N30_1 : std_logic ;
+signal N31_1 : std_logic ;
+signal N32_1 : std_logic ;
+signal N33_1 : std_logic ;
+signal N34_1 : std_logic ;
+signal N35_1 : std_logic ;
+signal N36_1 : std_logic ;
+signal N37_1 : std_logic ;
+signal N38_1 : std_logic ;
+signal N39_1 : std_logic ;
+signal N40_1 : std_logic ;
+signal N41_1 : std_logic ;
+signal N42_1 : std_logic ;
+signal N43_1 : std_logic ;
+signal N46_1 : std_logic ;
+signal TX_PCLK_I : std_logic ;
+signal GND : std_logic ;
+signal VCC : std_logic ;
+signal \SLL_INST.PLL_LOCK_I_14\ : std_logic ;
+component sgmii_ecp5sll_core_Z1_layer1
+port(
+tx_pclk :  in std_logic;
+sli_rst :  in std_logic;
+pll_refclki :  in std_logic;
+pll_lock_i :  out std_logic  );
+end component;
+component sgmii_ecp5rsl_core_Z2_layer1
+port(
+rx_pcs_rst_c :  in std_logic;
+tx_pcs_rst_c :  in std_logic;
+tx_serdes_rst_c :  in std_logic;
+serdes_rst_dual_c :  in std_logic;
+rsl_tx_pcs_rst_c :  out std_logic;
+rsl_rx_serdes_rst_c :  out std_logic;
+rsl_serdes_rst_dual_c :  out std_logic;
+rsl_tx_serdes_rst_c :  out std_logic;
+rsl_tx_rdy :  out std_logic;
+pll_lock_i :  in std_logic;
+pll_refclki :  in std_logic;
+rsl_rx_rdy :  out std_logic;
+rsl_rst :  in std_logic;
+rxrefclk :  in std_logic;
+rsl_disable :  in std_logic;
+rx_serdes_rst_c :  in std_logic;
+rsl_rx_pcs_rst_c :  out std_logic;
+rst_dual_c :  in std_logic;
+rx_cdr_lol_s :  in std_logic;
+rx_los_low_s :  in std_logic  );
+end component;
+begin
+VCC_0: VHI port map (
+Z => VCC);
+GND_0: VLO port map (
+Z => GND);
+PUR_INST: PUR port map (
+PUR => VCC);
+GSR_INST: GSR port map (
+GSR => VCC);
+TX_PCLK_11 <= TX_PCLK_I;
+DCU0_INST: DCUA 
+generic map( 
+  D_MACROPDB => "0b1", 
+  D_IB_PWDNB => "0b1", 
+  D_XGE_MODE => "0b0", 
+  D_LOW_MARK => "0d4", 
+  D_HIGH_MARK => "0d12", 
+  D_BUS8BIT_SEL => "0b0", 
+  D_CDR_LOL_SET => "0b00", 
+  D_BITCLK_LOCAL_EN => "0b1", 
+  D_BITCLK_ND_EN => "0b0", 
+  D_BITCLK_FROM_ND_EN => "0b0", 
+  D_SYNC_LOCAL_EN => "0b1", 
+  D_SYNC_ND_EN => "0b0", 
+  CH0_UC_MODE => "0b0", 
+  CH0_PCIE_MODE => "0b0", 
+  CH0_RIO_MODE => "0b0", 
+  CH0_WA_MODE => "0b0", 
+  CH0_INVERT_RX => "0b0", 
+  CH0_INVERT_TX => "0b0", 
+  CH0_PRBS_SELECTION => "0b0", 
+  CH0_GE_AN_ENABLE => "0b0", 
+  CH0_PRBS_LOCK => "0b0", 
+  CH0_PRBS_ENABLE => "0b0", 
+  CH0_ENABLE_CG_ALIGN => "0b1", 
+  CH0_TX_GEAR_MODE => "0b0", 
+  CH0_RX_GEAR_MODE => "0b0", 
+  CH0_PCS_DET_TIME_SEL => "0b00", 
+  CH0_PCIE_EI_EN => "0b0", 
+  CH0_TX_GEAR_BYPASS => "0b0", 
+  CH0_ENC_BYPASS => "0b0", 
+  CH0_SB_BYPASS => "0b0", 
+  CH0_RX_SB_BYPASS => "0b0", 
+  CH0_WA_BYPASS => "0b0", 
+  CH0_DEC_BYPASS => "0b0", 
+  CH0_CTC_BYPASS => "0b0", 
+  CH0_RX_GEAR_BYPASS => "0b0", 
+  CH0_LSM_DISABLE => "0b0", 
+  CH0_MATCH_2_ENABLE => "0b1", 
+  CH0_MATCH_4_ENABLE => "0b0", 
+  CH0_MIN_IPG_CNT => "0b11", 
+  CH0_CC_MATCH_1 => "0x000", 
+  CH0_CC_MATCH_2 => "0x000", 
+  CH0_CC_MATCH_3 => "0x1BC", 
+  CH0_CC_MATCH_4 => "0x050", 
+  CH0_UDF_COMMA_MASK => "0x3ff", 
+  CH0_UDF_COMMA_A => "0x283", 
+  CH0_UDF_COMMA_B => "0x17C", 
+  CH0_RX_DCO_CK_DIV => "0b010", 
+  CH0_RCV_DCC_EN => "0b0", 
+  CH0_REQ_LVL_SET => "0b00", 
+  CH0_REQ_EN => "0b1", 
+  CH0_RTERM_RX => "0d22", 
+  CH0_PDEN_SEL => "0b1", 
+  CH0_LDR_RX2CORE_SEL => "0b0", 
+  CH0_LDR_CORE2TX_SEL => "0b0", 
+  CH0_TPWDNB => "0b1", 
+  CH0_RATE_MODE_TX => "0b0", 
+  CH0_RTERM_TX => "0d19", 
+  CH0_TX_CM_SEL => "0b00", 
+  CH0_TDRV_PRE_EN => "0b0", 
+  CH0_TDRV_SLICE0_SEL => "0b01", 
+  CH0_TDRV_SLICE1_SEL => "0b00", 
+  CH0_TDRV_SLICE2_SEL => "0b01", 
+  CH0_TDRV_SLICE3_SEL => "0b01", 
+  CH0_TDRV_SLICE4_SEL => "0b01", 
+  CH0_TDRV_SLICE5_SEL => "0b01", 
+  CH0_TDRV_SLICE0_CUR => "0b101", 
+  CH0_TDRV_SLICE1_CUR => "0b000", 
+  CH0_TDRV_SLICE2_CUR => "0b11", 
+  CH0_TDRV_SLICE3_CUR => "0b11", 
+  CH0_TDRV_SLICE4_CUR => "0b11", 
+  CH0_TDRV_SLICE5_CUR => "0b00", 
+  CH0_TDRV_DAT_SEL => "0b00", 
+  CH0_TX_DIV11_SEL => "0b0", 
+  CH0_RPWDNB => "0b1", 
+  CH0_RATE_MODE_RX => "0b0", 
+  CH0_RLOS_SEL => "0b1", 
+  CH0_RX_LOS_LVL => "0b010", 
+  CH0_RX_LOS_CEQ => "0b11", 
+  CH0_RX_LOS_HYST_EN => "0b0", 
+  CH0_RX_LOS_EN => "0b1", 
+  CH0_RX_DIV11_SEL => "0b0", 
+  CH0_SEL_SD_RX_CLK => "0b0", 
+  CH0_FF_RX_H_CLK_EN => "0b0", 
+  CH0_FF_RX_F_CLK_DIS => "0b0", 
+  CH0_FF_TX_H_CLK_EN => "0b0", 
+  CH0_FF_TX_F_CLK_DIS => "0b0", 
+  CH0_RX_RATE_SEL => "0d8", 
+  CH0_TDRV_POST_EN => "0b0", 
+  CH0_TX_POST_SIGN => "0b0", 
+  CH0_TX_PRE_SIGN => "0b0", 
+  CH0_RXTERM_CM => "0b11", 
+  CH0_RXIN_CM => "0b11", 
+  CH0_LEQ_OFFSET_SEL => "0b0", 
+  CH0_LEQ_OFFSET_TRIM => "0b000", 
+  D_TX_MAX_RATE => "1.25", 
+  CH0_CDR_MAX_RATE => "1.25", 
+  CH0_TXAMPLITUDE => "0d1100", 
+  CH0_TXDEPRE => "DISABLED", 
+  CH0_TXDEPOST => "DISABLED", 
+  CH0_PROTOCOL => "GBE", 
+  D_ISETLOS => "0d0", 
+  D_SETIRPOLY_AUX => "0b00", 
+  D_SETICONST_AUX => "0b00", 
+  D_SETIRPOLY_CH => "0b00", 
+  D_SETICONST_CH => "0b00", 
+  D_REQ_ISET => "0b000", 
+  D_PD_ISET => "0b00", 
+  D_DCO_CALIB_TIME_SEL => "0b00", 
+  CH0_DCOCTLGI => "0b010", 
+  CH0_DCOATDDLY => "0b00", 
+  CH0_DCOATDCFG => "0b00", 
+  CH0_DCOBYPSATD => "0b1", 
+  CH0_DCOSCALEI => "0b00", 
+  CH0_DCOITUNE4LSB => "0b111", 
+  CH0_DCOIOSTUNE => "0b000", 
+  CH0_DCODISBDAVOID => "0b0", 
+  CH0_DCOCALDIV => "0b001", 
+  CH0_DCONUOFLSB => "0b101", 
+  CH0_DCOIUPDNX2 => "0b1", 
+  CH0_DCOSTEP => "0b00", 
+  CH0_DCOSTARTVAL => "0b000", 
+  CH0_DCOFLTDAC => "0b01", 
+  CH0_DCOITUNE => "0b00", 
+  CH0_DCOFTNRG => "0b110", 
+  CH0_CDR_CNT4SEL => "0b00", 
+  CH0_CDR_CNT8SEL => "0b00", 
+  CH0_BAND_THRESHOLD => "0d0", 
+  CH0_AUTO_FACQ_EN => "0b1", 
+  CH0_AUTO_CALIB_EN => "0b1", 
+  CH0_CALIB_CK_MODE => "0b0", 
+  CH0_REG_BAND_OFFSET => "0d0", 
+  CH0_REG_BAND_SEL => "0d0", 
+  CH0_REG_IDAC_SEL => "0d0", 
+  CH0_REG_IDAC_EN => "0b0", 
+  D_TXPLL_PWDNB => "0b1", 
+  D_SETPLLRC => "0d1", 
+  D_REFCK_MODE => "0b001", 
+  D_TX_VCO_CK_DIV => "0b010", 
+  D_PLL_LOL_SET => "0b00", 
+  D_RG_EN => "0b0", 
+  D_RG_SET => "0b00", 
+  D_CMUSETISCL4VCO => "0b000", 
+  D_CMUSETI4VCO => "0b00", 
+  D_CMUSETINITVCT => "0b00", 
+  D_CMUSETZGM => "0b000", 
+  D_CMUSETP2AGM => "0b000", 
+  D_CMUSETP1GM => "0b000", 
+  D_CMUSETI4CPZ => "0d3", 
+  D_CMUSETI4CPP => "0d3", 
+  D_CMUSETICP4Z => "0b101", 
+  D_CMUSETICP4P => "0b01", 
+  D_CMUSETBIASI => "0b00"
+) 
+port map (
+CH0_HDINP => hdinp,
+CH1_HDINP => GND,
+CH0_HDINN => hdinn,
+CH1_HDINN => GND,
+D_TXBIT_CLKP_FROM_ND => GND,
+D_TXBIT_CLKN_FROM_ND => GND,
+D_SYNC_ND => GND,
+D_TXPLL_LOL_FROM_ND => GND,
+CH0_RX_REFCLK => rxrefclk,
+CH1_RX_REFCLK => GND,
+CH0_FF_RXI_CLK => TX_PCLK_11,
+CH1_FF_RXI_CLK => VCC,
+CH0_FF_TXI_CLK => txi_clk,
+CH1_FF_TXI_CLK => VCC,
+CH0_FF_EBRD_CLK => TX_PCLK_11,
+CH1_FF_EBRD_CLK => VCC,
+CH0_FF_TX_D_0 => txdata(0),
+CH1_FF_TX_D_0 => GND,
+CH0_FF_TX_D_1 => txdata(1),
+CH1_FF_TX_D_1 => GND,
+CH0_FF_TX_D_2 => txdata(2),
+CH1_FF_TX_D_2 => GND,
+CH0_FF_TX_D_3 => txdata(3),
+CH1_FF_TX_D_3 => GND,
+CH0_FF_TX_D_4 => txdata(4),
+CH1_FF_TX_D_4 => GND,
+CH0_FF_TX_D_5 => txdata(5),
+CH1_FF_TX_D_5 => GND,
+CH0_FF_TX_D_6 => txdata(6),
+CH1_FF_TX_D_6 => GND,
+CH0_FF_TX_D_7 => txdata(7),
+CH1_FF_TX_D_7 => GND,
+CH0_FF_TX_D_8 => tx_k(0),
+CH1_FF_TX_D_8 => GND,
+CH0_FF_TX_D_9 => GND,
+CH1_FF_TX_D_9 => GND,
+CH0_FF_TX_D_10 => xmit(0),
+CH1_FF_TX_D_10 => GND,
+CH0_FF_TX_D_11 => tx_disp_correct(0),
+CH1_FF_TX_D_11 => GND,
+CH0_FF_TX_D_12 => GND,
+CH1_FF_TX_D_12 => GND,
+CH0_FF_TX_D_13 => GND,
+CH1_FF_TX_D_13 => GND,
+CH0_FF_TX_D_14 => GND,
+CH1_FF_TX_D_14 => GND,
+CH0_FF_TX_D_15 => GND,
+CH1_FF_TX_D_15 => GND,
+CH0_FF_TX_D_16 => GND,
+CH1_FF_TX_D_16 => GND,
+CH0_FF_TX_D_17 => GND,
+CH1_FF_TX_D_17 => GND,
+CH0_FF_TX_D_18 => GND,
+CH1_FF_TX_D_18 => GND,
+CH0_FF_TX_D_19 => GND,
+CH1_FF_TX_D_19 => GND,
+CH0_FF_TX_D_20 => GND,
+CH1_FF_TX_D_20 => GND,
+CH0_FF_TX_D_21 => GND,
+CH1_FF_TX_D_21 => GND,
+CH0_FF_TX_D_22 => GND,
+CH1_FF_TX_D_22 => GND,
+CH0_FF_TX_D_23 => GND,
+CH1_FF_TX_D_23 => GND,
+CH0_FFC_EI_EN => GND,
+CH1_FFC_EI_EN => GND,
+CH0_FFC_PCIE_DET_EN => GND,
+CH1_FFC_PCIE_DET_EN => GND,
+CH0_FFC_PCIE_CT => GND,
+CH1_FFC_PCIE_CT => GND,
+CH0_FFC_SB_INV_RX => GND,
+CH1_FFC_SB_INV_RX => GND,
+CH0_FFC_ENABLE_CGALIGN => GND,
+CH1_FFC_ENABLE_CGALIGN => GND,
+CH0_FFC_SIGNAL_DETECT => signal_detect_c,
+CH1_FFC_SIGNAL_DETECT => GND,
+CH0_FFC_FB_LOOPBACK => GND,
+CH1_FFC_FB_LOOPBACK => GND,
+CH0_FFC_SB_PFIFO_LP => GND,
+CH1_FFC_SB_PFIFO_LP => GND,
+CH0_FFC_PFIFO_CLR => GND,
+CH1_FFC_PFIFO_CLR => GND,
+CH0_FFC_RATE_MODE_RX => GND,
+CH1_FFC_RATE_MODE_RX => GND,
+CH0_FFC_RATE_MODE_TX => GND,
+CH1_FFC_RATE_MODE_TX => GND,
+CH0_FFC_DIV11_MODE_RX => GND,
+CH1_FFC_DIV11_MODE_RX => GND,
+CH0_FFC_RX_GEAR_MODE => GND,
+CH1_FFC_RX_GEAR_MODE => GND,
+CH0_FFC_TX_GEAR_MODE => GND,
+CH1_FFC_TX_GEAR_MODE => GND,
+CH0_FFC_DIV11_MODE_TX => GND,
+CH1_FFC_DIV11_MODE_TX => GND,
+CH0_FFC_LDR_CORE2TX_EN => GND,
+CH1_FFC_LDR_CORE2TX_EN => GND,
+CH0_FFC_LANE_TX_RST => RSL_TX_PCS_RST_C,
+CH1_FFC_LANE_TX_RST => GND,
+CH0_FFC_LANE_RX_RST => RSL_RX_PCS_RST_C,
+CH1_FFC_LANE_RX_RST => GND,
+CH0_FFC_RRST => RSL_RX_SERDES_RST_C,
+CH1_FFC_RRST => GND,
+CH0_FFC_TXPWDNB => tx_pwrup_c,
+CH1_FFC_TXPWDNB => GND,
+CH0_FFC_RXPWDNB => rx_pwrup_c,
+CH1_FFC_RXPWDNB => GND,
+CH0_LDR_CORE2TX => GND,
+CH1_LDR_CORE2TX => GND,
+D_SCIWDATA0 => sci_wrdata(0),
+D_SCIWDATA1 => sci_wrdata(1),
+D_SCIWDATA2 => sci_wrdata(2),
+D_SCIWDATA3 => sci_wrdata(3),
+D_SCIWDATA4 => sci_wrdata(4),
+D_SCIWDATA5 => sci_wrdata(5),
+D_SCIWDATA6 => sci_wrdata(6),
+D_SCIWDATA7 => sci_wrdata(7),
+D_SCIADDR0 => sci_addr(0),
+D_SCIADDR1 => sci_addr(1),
+D_SCIADDR2 => sci_addr(2),
+D_SCIADDR3 => sci_addr(3),
+D_SCIADDR4 => sci_addr(4),
+D_SCIADDR5 => sci_addr(5),
+D_SCIENAUX => sci_en_dual,
+D_SCISELAUX => sci_sel_dual,
+CH0_SCIEN => sci_en,
+CH1_SCIEN => GND,
+CH0_SCISEL => sci_sel,
+CH1_SCISEL => GND,
+D_SCIRD => sci_rd,
+D_SCIWSTN => sci_wrn,
+D_CYAWSTN => cyawstn,
+D_FFC_SYNC_TOGGLE => GND,
+D_FFC_DUAL_RST => rst_dual_c,
+D_FFC_MACRO_RST => RSL_SERDES_RST_DUAL_C,
+D_FFC_MACROPDB => serdes_pdb,
+D_FFC_TRST => RSL_TX_SERDES_RST_C,
+CH0_FFC_CDR_EN_BITSLIP => GND,
+CH1_FFC_CDR_EN_BITSLIP => GND,
+D_SCAN_ENABLE => GND,
+D_SCAN_IN_0 => GND,
+D_SCAN_IN_1 => GND,
+D_SCAN_IN_2 => GND,
+D_SCAN_IN_3 => GND,
+D_SCAN_IN_4 => GND,
+D_SCAN_IN_5 => GND,
+D_SCAN_IN_6 => GND,
+D_SCAN_IN_7 => GND,
+D_SCAN_MODE => GND,
+D_SCAN_RESET => GND,
+D_CIN0 => GND,
+D_CIN1 => GND,
+D_CIN2 => GND,
+D_CIN3 => GND,
+D_CIN4 => GND,
+D_CIN5 => GND,
+D_CIN6 => GND,
+D_CIN7 => GND,
+D_CIN8 => GND,
+D_CIN9 => GND,
+D_CIN10 => GND,
+D_CIN11 => GND,
+CH0_HDOUTP => hdoutp,
+CH1_HDOUTP => N47_1,
+CH0_HDOUTN => hdoutn,
+CH1_HDOUTN => N48_1,
+D_TXBIT_CLKP_TO_ND => N1_1,
+D_TXBIT_CLKN_TO_ND => N2_1,
+D_SYNC_PULSE2ND => N3_1,
+D_TXPLL_LOL_TO_ND => N4_1,
+CH0_FF_RX_F_CLK => N5_1,
+CH1_FF_RX_F_CLK => N49_1,
+CH0_FF_RX_H_CLK => N6_1,
+CH1_FF_RX_H_CLK => N50_1,
+CH0_FF_TX_F_CLK => N7_1,
+CH1_FF_TX_F_CLK => N51_1,
+CH0_FF_TX_H_CLK => N8_1,
+CH1_FF_TX_H_CLK => N52_1,
+CH0_FF_RX_PCLK => N9_1,
+CH1_FF_RX_PCLK => N53_1,
+CH0_FF_TX_PCLK => TX_PCLK_I,
+CH1_FF_TX_PCLK => N54_1,
+CH0_FF_RX_D_0 => rxdata(0),
+CH1_FF_RX_D_0 => N55_1,
+CH0_FF_RX_D_1 => rxdata(1),
+CH1_FF_RX_D_1 => N56_1,
+CH0_FF_RX_D_2 => rxdata(2),
+CH1_FF_RX_D_2 => N57_1,
+CH0_FF_RX_D_3 => rxdata(3),
+CH1_FF_RX_D_3 => N58_1,
+CH0_FF_RX_D_4 => rxdata(4),
+CH1_FF_RX_D_4 => N59_1,
+CH0_FF_RX_D_5 => rxdata(5),
+CH1_FF_RX_D_5 => N60_1,
+CH0_FF_RX_D_6 => rxdata(6),
+CH1_FF_RX_D_6 => N61_1,
+CH0_FF_RX_D_7 => rxdata(7),
+CH1_FF_RX_D_7 => N62_1,
+CH0_FF_RX_D_8 => rx_k(0),
+CH1_FF_RX_D_8 => N63_1,
+CH0_FF_RX_D_9 => rx_disp_err(0),
+CH1_FF_RX_D_9 => N64_1,
+CH0_FF_RX_D_10 => rx_cv_err(0),
+CH1_FF_RX_D_10 => N65_1,
+CH0_FF_RX_D_11 => N10_1,
+CH1_FF_RX_D_11 => N66_1,
+CH0_FF_RX_D_12 => N67_1,
+CH1_FF_RX_D_12 => N68_1,
+CH0_FF_RX_D_13 => N69_1,
+CH1_FF_RX_D_13 => N70_1,
+CH0_FF_RX_D_14 => N71_1,
+CH1_FF_RX_D_14 => N72_1,
+CH0_FF_RX_D_15 => N73_1,
+CH1_FF_RX_D_15 => N74_1,
+CH0_FF_RX_D_16 => N75_1,
+CH1_FF_RX_D_16 => N76_1,
+CH0_FF_RX_D_17 => N77_1,
+CH1_FF_RX_D_17 => N78_1,
+CH0_FF_RX_D_18 => N79_1,
+CH1_FF_RX_D_18 => N80_1,
+CH0_FF_RX_D_19 => N81_1,
+CH1_FF_RX_D_19 => N82_1,
+CH0_FF_RX_D_20 => N83_1,
+CH1_FF_RX_D_20 => N84_1,
+CH0_FF_RX_D_21 => N85_1,
+CH1_FF_RX_D_21 => N86_1,
+CH0_FF_RX_D_22 => N87_1,
+CH1_FF_RX_D_22 => N88_1,
+CH0_FF_RX_D_23 => N11_1,
+CH1_FF_RX_D_23 => N89_1,
+CH0_FFS_PCIE_DONE => N12_1,
+CH1_FFS_PCIE_DONE => N90_1,
+CH0_FFS_PCIE_CON => N13_1,
+CH1_FFS_PCIE_CON => N91_1,
+CH0_FFS_RLOS => RX_LOS_LOW_S_12,
+CH1_FFS_RLOS => N92_1,
+CH0_FFS_LS_SYNC_STATUS => lsm_status_s,
+CH1_FFS_LS_SYNC_STATUS => N93_1,
+CH0_FFS_CC_UNDERRUN => ctc_urun_s,
+CH1_FFS_CC_UNDERRUN => N94_1,
+CH0_FFS_CC_OVERRUN => ctc_orun_s,
+CH1_FFS_CC_OVERRUN => N95_1,
+CH0_FFS_RXFBFIFO_ERROR => N14_1,
+CH1_FFS_RXFBFIFO_ERROR => N96_1,
+CH0_FFS_TXFBFIFO_ERROR => N15_1,
+CH1_FFS_TXFBFIFO_ERROR => N97_1,
+CH0_FFS_RLOL => RX_CDR_LOL_S_13,
+CH1_FFS_RLOL => N98_1,
+CH0_FFS_SKP_ADDED => ctc_ins_s,
+CH1_FFS_SKP_ADDED => N99_1,
+CH0_FFS_SKP_DELETED => ctc_del_s,
+CH1_FFS_SKP_DELETED => N100_1,
+CH0_LDR_RX2CORE => N101_1,
+CH1_LDR_RX2CORE => N112_1,
+D_SCIRDATA0 => sci_rddata(0),
+D_SCIRDATA1 => sci_rddata(1),
+D_SCIRDATA2 => sci_rddata(2),
+D_SCIRDATA3 => sci_rddata(3),
+D_SCIRDATA4 => sci_rddata(4),
+D_SCIRDATA5 => sci_rddata(5),
+D_SCIRDATA6 => sci_rddata(6),
+D_SCIRDATA7 => sci_rddata(7),
+D_SCIINT => sci_int,
+D_SCAN_OUT_0 => N16_1,
+D_SCAN_OUT_1 => N17_1,
+D_SCAN_OUT_2 => N18_1,
+D_SCAN_OUT_3 => N19_1,
+D_SCAN_OUT_4 => N20_1,
+D_SCAN_OUT_5 => N21_1,
+D_SCAN_OUT_6 => N22_1,
+D_SCAN_OUT_7 => N23_1,
+D_COUT0 => N24_1,
+D_COUT1 => N25_1,
+D_COUT2 => N26_1,
+D_COUT3 => N27_1,
+D_COUT4 => N28_1,
+D_COUT5 => N29_1,
+D_COUT6 => N30_1,
+D_COUT7 => N31_1,
+D_COUT8 => N32_1,
+D_COUT9 => N33_1,
+D_COUT10 => N34_1,
+D_COUT11 => N35_1,
+D_COUT12 => N36_1,
+D_COUT13 => N37_1,
+D_COUT14 => N38_1,
+D_COUT15 => N39_1,
+D_COUT16 => N40_1,
+D_COUT17 => N41_1,
+D_COUT18 => N42_1,
+D_COUT19 => N43_1,
+D_REFCLKI => pll_refclki,
+D_FFS_PLOL => N46_1);
+SLL_INST: sgmii_ecp5sll_core_Z1_layer1 port map (
+tx_pclk => TX_PCLK_11,
+sli_rst => sli_rst,
+pll_refclki => pll_refclki,
+pll_lock_i => \SLL_INST.PLL_LOCK_I_14\);
+RSL_INST: sgmii_ecp5rsl_core_Z2_layer1 port map (
+rx_pcs_rst_c => rx_pcs_rst_c,
+tx_pcs_rst_c => tx_pcs_rst_c,
+tx_serdes_rst_c => tx_serdes_rst_c,
+serdes_rst_dual_c => serdes_rst_dual_c,
+rsl_tx_pcs_rst_c => RSL_TX_PCS_RST_C,
+rsl_rx_serdes_rst_c => RSL_RX_SERDES_RST_C,
+rsl_serdes_rst_dual_c => RSL_SERDES_RST_DUAL_C,
+rsl_tx_serdes_rst_c => RSL_TX_SERDES_RST_C,
+rsl_tx_rdy => rsl_tx_rdy,
+pll_lock_i => \SLL_INST.PLL_LOCK_I_14\,
+pll_refclki => pll_refclki,
+rsl_rx_rdy => rsl_rx_rdy,
+rsl_rst => rsl_rst,
+rxrefclk => rxrefclk,
+rsl_disable => rsl_disable,
+rx_serdes_rst_c => rx_serdes_rst_c,
+rsl_rx_pcs_rst_c => RSL_RX_PCS_RST_C,
+rst_dual_c => rst_dual_c,
+rx_cdr_lol_s => RX_CDR_LOL_S_13,
+rx_los_low_s => RX_LOS_LOW_S_12);
+tx_pclk <= TX_PCLK_11;
+rx_los_low_s <= RX_LOS_LOW_S_12;
+rx_cdr_lol_s <= RX_CDR_LOL_S_13;
+pll_lol <= \SLL_INST.PLL_LOCK_I_14\;
+end beh;
+

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.vm b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.vm
new file mode 100644 (file)
index 0000000..ece1a16
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.vm
@@ -0,0 +1,6626 @@
+//
+// Written by Synplify Pro 
+// Product Version "M-2017.03L-SP1-1"
+// Program "Synplify Pro", Mapper "maplat, Build 1796R"
+// Fri May 10 09:02:16 2019
+//
+// Source file index table:
+// Object locations will have the form <file>:<line>
+// file 0 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd "
+// file 1 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd "
+// file 2 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd "
+// file 3 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd "
+// file 4 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd "
+// file 5 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd "
+// file 6 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd "
+// file 7 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd "
+// file 8 "\/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd "
+// file 9 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd "
+// file 10 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v "
+// file 11 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v "
+// file 12 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v "
+// file 13 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v "
+// file 14 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v "
+// file 15 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh "
+// file 16 "\/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v "
+// file 17 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/nlconst.dat "
+// file 18 "\/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.fdc "
+
+`timescale 100 ps/100 ps
+module sync_0s (
+  phb,
+  rhb_sync,
+  sli_rst,
+  pll_refclki
+)
+;
+input phb ;
+output rhb_sync ;
+input sli_rst ;
+input pll_refclki ;
+wire phb ;
+wire rhb_sync ;
+wire sli_rst ;
+wire pll_refclki ;
+wire data_p1 ;
+wire data_p2_QN_0 ;
+wire VCC ;
+wire data_p1_QN_0 ;
+wire GND ;
+// @16:1988
+  FD1S3DX data_p2 (
+       .D(data_p1),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_sync)
+);
+// @16:1988
+  FD1S3DX data_p1_reg (
+       .D(phb),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(data_p1)
+);
+  VHI VCC_0 (
+       .Z(VCC)
+);
+// @16:865
+  VLO GND_cZ (
+       .Z(GND)
+);
+endmodule /* sync_0s */
+
+module sync_0s_6 (
+  rtc_pul,
+  ppul_sync,
+  sli_rst,
+  tx_pclk
+)
+;
+input rtc_pul ;
+output ppul_sync ;
+input sli_rst ;
+input tx_pclk ;
+wire rtc_pul ;
+wire ppul_sync ;
+wire sli_rst ;
+wire tx_pclk ;
+wire data_p1 ;
+wire data_p2_QN ;
+wire VCC ;
+wire data_p1_QN ;
+wire GND ;
+// @16:1988
+  FD1S3DX data_p2 (
+       .D(data_p1),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(ppul_sync)
+);
+// @16:1988
+  FD1S3DX data_p1_reg (
+       .D(rtc_pul),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(data_p1)
+);
+  VHI VCC_0 (
+       .Z(VCC)
+);
+// @16:865
+  VLO GND_cZ (
+       .Z(GND)
+);
+endmodule /* sync_0s_6 */
+
+module sync_0s_0 (
+  ppul_sync,
+  pdiff_sync,
+  sli_rst,
+  pll_refclki
+)
+;
+input ppul_sync ;
+output pdiff_sync ;
+input sli_rst ;
+input pll_refclki ;
+wire ppul_sync ;
+wire pdiff_sync ;
+wire sli_rst ;
+wire pll_refclki ;
+wire data_p1 ;
+wire data_p2_QN_1 ;
+wire VCC ;
+wire data_p1_QN_1 ;
+wire GND ;
+// @16:1988
+  FD1S3DX data_p2 (
+       .D(data_p1),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(pdiff_sync)
+);
+// @16:1988
+  FD1S3DX data_p1_reg (
+       .D(ppul_sync),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(data_p1)
+);
+  VHI VCC_0 (
+       .Z(VCC)
+);
+// @16:865
+  VLO GND_cZ (
+       .Z(GND)
+);
+endmodule /* sync_0s_0 */
+
+module sgmii_ecp5sll_core_Z1_layer1 (
+  tx_pclk,
+  sli_rst,
+  pll_refclki,
+  pll_lock_i
+)
+;
+input tx_pclk ;
+input sli_rst ;
+input pll_refclki ;
+output pll_lock_i ;
+wire tx_pclk ;
+wire sli_rst ;
+wire pll_refclki ;
+wire pll_lock_i ;
+wire [2:0] phb_cnt;
+wire [2:0] phb_cnt_i;
+wire [15:0] rcount;
+wire [21:0] pcount;
+wire [0:0] un1_pcount_diff_i;
+wire [1:0] sll_state;
+wire [1:0] sll_state_QN;
+wire [7:0] rhb_wait_cnt_s;
+wire [7:0] rhb_wait_cnt;
+wire [7:0] rhb_wait_cnt_QN;
+wire [15:0] rcount_s;
+wire [15:0] rcount_QN;
+wire [2:0] phb_cnt_QN;
+wire [2:1] phb_cnt_RNO;
+wire [21:0] pcount_s;
+wire [21:0] pcount_QN;
+wire [21:0] pcount_diff_QN;
+wire [2:2] rdiff_comp_lock;
+wire [2:2] rdiff_comp_lock_QN;
+wire [0:0] un1_pcount_diff;
+wire [20:0] pcount_cry;
+wire [0:0] pcount_cry_0_S0;
+wire [21:21] pcount_s_0_COUT;
+wire [21:21] pcount_s_0_S1;
+wire [14:0] rcount_cry;
+wire [0:0] rcount_cry_0_S0;
+wire [15:15] rcount_s_0_COUT;
+wire [15:15] rcount_s_0_S1;
+wire [6:0] rhb_wait_cnt_cry;
+wire [0:0] rhb_wait_cnt_cry_0_S0;
+wire [7:7] rhb_wait_cnt_s_0_COUT;
+wire [7:7] rhb_wait_cnt_s_0_S1;
+wire pll_lock ;
+wire rtc_ctrl4_0_a3_1 ;
+wire un13_lock_20 ;
+wire ppul_sync_p2 ;
+wire ppul_sync_p1 ;
+wire un1_pcount_diff_1_axb_20 ;
+wire un13_lock_19 ;
+wire un1_pcount_diff_1_axb_19 ;
+wire un13_lock_18 ;
+wire un1_pcount_diff_1_axb_18 ;
+wire un13_lock_17 ;
+wire un1_pcount_diff_1_cry_17_0_RNO ;
+wire un13_lock_16 ;
+wire un1_pcount_diff_1_axb_16 ;
+wire un13_lock_15 ;
+wire un1_pcount_diff_1_axb_15 ;
+wire un13_lock_14 ;
+wire un1_pcount_diff_1_axb_14 ;
+wire un13_lock_13 ;
+wire un1_pcount_diff_1_axb_13 ;
+wire un13_lock_12 ;
+wire un1_pcount_diff_1_axb_12 ;
+wire un13_lock_11 ;
+wire un1_pcount_diff_1_axb_11 ;
+wire un13_lock_10 ;
+wire un1_pcount_diff_1_axb_10 ;
+wire un13_lock_9 ;
+wire un1_pcount_diff_1_axb_9 ;
+wire un13_lock_8 ;
+wire un1_pcount_diff_1_axb_8 ;
+wire un13_lock_7 ;
+wire un1_pcount_diff_1_axb_7 ;
+wire un13_lock_6 ;
+wire un1_pcount_diff_1_axb_6 ;
+wire un13_lock_5 ;
+wire un1_pcount_diff_1_axb_5 ;
+wire un13_lock_4 ;
+wire un1_pcount_diff_1_axb_4 ;
+wire un13_lock_3 ;
+wire un1_pcount_diff_1_axb_3 ;
+wire un13_lock_2 ;
+wire un1_pcount_diff_1_axb_2 ;
+wire un13_lock_1 ;
+wire un1_pcount_diff_1_axb_1 ;
+wire un13_lock_21 ;
+wire ppul_sync_p3 ;
+wire N_7 ;
+wire un13_lock_0 ;
+wire rtc_ctrl4 ;
+wire rtc_ctrl ;
+wire VCC ;
+wire N_2085_0 ;
+wire unlock_5 ;
+wire unlock_1_sqmuxa_i ;
+wire unlock ;
+wire unlock_QN ;
+wire N_95_i ;
+wire N_97_i ;
+wire rtc_pul ;
+wire rtc_pul_p1 ;
+wire rtc_pul_p1_QN ;
+wire rtc_pul5 ;
+wire rtc_pul_QN ;
+wire rtc_ctrl_QN ;
+wire rstat_pclk_2 ;
+wire rstat_pclk ;
+wire rstat_pclk_QN ;
+wire rhb_sync_p1 ;
+wire rhb_sync_p2 ;
+wire rhb_sync_p2_QN ;
+wire rhb_sync ;
+wire rhb_sync_p1_QN ;
+wire ppul_sync_p3_QN ;
+wire ppul_sync_p2_QN ;
+wire ppul_sync ;
+wire ppul_sync_p1_QN ;
+wire N_53_i ;
+wire pll_lock_QN ;
+wire phb ;
+wire phb_QN ;
+wire pdiff_sync ;
+wire pdiff_sync_p1 ;
+wire pdiff_sync_p1_QN ;
+wire un1_pcount_diff_1_cry_1_0_S0 ;
+wire un1_pcount_diff_1_cry_1_0_S1 ;
+wire un1_pcount_diff_1_cry_3_0_S0 ;
+wire un1_pcount_diff_1_cry_3_0_S1 ;
+wire un1_pcount_diff_1_cry_5_0_S0 ;
+wire un1_pcount_diff_1_cry_5_0_S1 ;
+wire un1_pcount_diff_1_cry_7_0_S0 ;
+wire un1_pcount_diff_1_cry_7_0_S1 ;
+wire un1_pcount_diff_1_cry_9_0_S0 ;
+wire un1_pcount_diff_1_cry_9_0_S1 ;
+wire un1_pcount_diff_1_cry_11_0_S0 ;
+wire un1_pcount_diff_1_cry_11_0_S1 ;
+wire un1_pcount_diff_1_cry_13_0_S0 ;
+wire un1_pcount_diff_1_cry_13_0_S1 ;
+wire un1_pcount_diff_1_cry_15_0_S0 ;
+wire un1_pcount_diff_1_cry_15_0_S1 ;
+wire un1_pcount_diff_1_cry_17_0_S0 ;
+wire un1_pcount_diff_1_cry_17_0_S1 ;
+wire un1_pcount_diff_1_cry_19_0_S0 ;
+wire un1_pcount_diff_1_cry_19_0_S1 ;
+wire un1_pcount_diff_1_s_21_0_S0 ;
+wire lock_5 ;
+wire lock_1_sqmuxa_i ;
+wire lock ;
+wire lock_QN ;
+wire N_98 ;
+wire rtc_pul5_0_o3 ;
+wire rtc_pul5_0_a3_6 ;
+wire rtc_pul5_0_a3_7 ;
+wire un1_rcount_1_0_a3 ;
+wire rhb_wait_cnt12 ;
+wire un1_rhb_wait_cnt_4 ;
+wire un1_rhb_wait_cnt_5 ;
+wire N_99 ;
+wire rtc_ctrl4_0_a3_12_4 ;
+wire rtc_ctrl4_0_a3_12_5 ;
+wire rtc_ctrl4_10 ;
+wire un1_rcount_1_0_a3_1 ;
+wire N_6 ;
+wire rtc_pul5_0_a3_5 ;
+wire N_8 ;
+wire un13_unlock_cry_21 ;
+wire un13_lock_cry_21_i ;
+wire rhb_wait_cnt_scalar ;
+wire un1_pcount_diff_1_cry_0 ;
+wire un1_pcount_diff_1_cry_0_0_S0 ;
+wire un1_pcount_diff_1_cry_0_0_S1 ;
+wire un1_pcount_diff_1_cry_2 ;
+wire un1_pcount_diff_1_cry_4 ;
+wire un1_pcount_diff_1_cry_6 ;
+wire un1_pcount_diff_1_cry_8 ;
+wire un1_pcount_diff_1_cry_10 ;
+wire un1_pcount_diff_1_cry_12 ;
+wire un1_pcount_diff_1_cry_14 ;
+wire un1_pcount_diff_1_cry_16 ;
+wire un1_pcount_diff_1_cry_18 ;
+wire un1_pcount_diff_1_cry_20 ;
+wire un1_pcount_diff_1_s_21_0_COUT ;
+wire un1_pcount_diff_1_s_21_0_S1 ;
+wire un13_lock_cry_0 ;
+wire un13_lock_cry_0_0_S0 ;
+wire un13_lock_cry_0_0_S1 ;
+wire un13_lock_cry_2 ;
+wire un13_lock_cry_1_0_S0 ;
+wire un13_lock_cry_1_0_S1 ;
+wire un13_lock_cry_4 ;
+wire un13_lock_cry_3_0_S0 ;
+wire un13_lock_cry_3_0_S1 ;
+wire un13_lock_cry_6 ;
+wire un13_lock_cry_5_0_S0 ;
+wire un13_lock_cry_5_0_S1 ;
+wire un13_lock_cry_8 ;
+wire un13_lock_cry_7_0_S0 ;
+wire un13_lock_cry_7_0_S1 ;
+wire un13_lock_cry_10 ;
+wire un13_lock_cry_9_0_S0 ;
+wire un13_lock_cry_9_0_S1 ;
+wire un13_lock_cry_12 ;
+wire un13_lock_cry_11_0_S0 ;
+wire un13_lock_cry_11_0_S1 ;
+wire un13_lock_cry_14 ;
+wire un13_lock_cry_13_0_S0 ;
+wire un13_lock_cry_13_0_S1 ;
+wire un13_lock_cry_16 ;
+wire un13_lock_cry_15_0_S0 ;
+wire un13_lock_cry_15_0_S1 ;
+wire un13_lock_cry_18 ;
+wire un13_lock_cry_17_0_S0 ;
+wire un13_lock_cry_17_0_S1 ;
+wire un13_lock_cry_20 ;
+wire un13_lock_cry_19_0_S0 ;
+wire un13_lock_cry_19_0_S1 ;
+wire un13_lock_cry_21_0_COUT ;
+wire un13_lock_cry_21_0_S0 ;
+wire un13_unlock_cry_0 ;
+wire un13_unlock_cry_0_0_S0 ;
+wire un13_unlock_cry_0_0_S1 ;
+wire un13_unlock_cry_2 ;
+wire un13_unlock_cry_1_0_S0 ;
+wire un13_unlock_cry_1_0_S1 ;
+wire un13_unlock_cry_4 ;
+wire un13_unlock_cry_3_0_S0 ;
+wire un13_unlock_cry_3_0_S1 ;
+wire un13_unlock_cry_6 ;
+wire un13_unlock_cry_5_0_S0 ;
+wire un13_unlock_cry_5_0_S1 ;
+wire un13_unlock_cry_8 ;
+wire un13_unlock_cry_7_0_S0 ;
+wire un13_unlock_cry_7_0_S1 ;
+wire un13_unlock_cry_10 ;
+wire un13_unlock_cry_9_0_S0 ;
+wire un13_unlock_cry_9_0_S1 ;
+wire un13_unlock_cry_12 ;
+wire un13_unlock_cry_11_0_S0 ;
+wire un13_unlock_cry_11_0_S1 ;
+wire un13_unlock_cry_14 ;
+wire un13_unlock_cry_13_0_S0 ;
+wire un13_unlock_cry_13_0_S1 ;
+wire un13_unlock_cry_16 ;
+wire un13_unlock_cry_15_0_S0 ;
+wire un13_unlock_cry_15_0_S1 ;
+wire un13_unlock_cry_18 ;
+wire un13_unlock_cry_17_0_S0 ;
+wire un13_unlock_cry_17_0_S1 ;
+wire un13_unlock_cry_20 ;
+wire un13_unlock_cry_19_0_S0 ;
+wire un13_unlock_cry_19_0_S1 ;
+wire un13_unlock_cry_21_0_COUT ;
+wire un13_unlock_cry_21_0_S0 ;
+wire N_21 ;
+wire N_20 ;
+wire N_19 ;
+wire N_18 ;
+wire N_14 ;
+wire GND ;
+wire N_1 ;
+wire N_2 ;
+wire N_3 ;
+wire N_4 ;
+wire N_5 ;
+wire N_9 ;
+  INV phb_RNO (
+       .A(phb_cnt[2]),
+       .Z(phb_cnt_i[2])
+);
+  INV \phb_cnt_RNO[0]  (
+       .A(phb_cnt[0]),
+       .Z(phb_cnt_i[0])
+);
+  INV pll_lock_RNI6JK9 (
+       .A(pll_lock),
+       .Z(pll_lock_i)
+);
+  LUT4 rtc_ctrl4_0_a3_RNO (
+       .A(rcount[2]),
+       .B(rcount[0]),
+       .C(rcount[5]),
+       .D(rcount[4]),
+       .Z(rtc_ctrl4_0_a3_1)
+);
+defparam rtc_ctrl4_0_a3_RNO.init=16'h2000;
+  LUT4 un1_pcount_diff_1_cry_19_0_RNO_0 (
+       .A(un13_lock_20),
+       .B(pcount[20]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_20)
+);
+defparam un1_pcount_diff_1_cry_19_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_19_0_RNO (
+       .A(un13_lock_19),
+       .B(pcount[19]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_19)
+);
+defparam un1_pcount_diff_1_cry_19_0_RNO.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_17_0_RNO_0 (
+       .A(un13_lock_18),
+       .B(pcount[18]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_18)
+);
+defparam un1_pcount_diff_1_cry_17_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_17_0_RNO_cZ (
+       .A(un13_lock_17),
+       .B(pcount[17]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_cry_17_0_RNO)
+);
+defparam un1_pcount_diff_1_cry_17_0_RNO_cZ.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_15_0_RNO_0 (
+       .A(un13_lock_16),
+       .B(pcount[16]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_16)
+);
+defparam un1_pcount_diff_1_cry_15_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_15_0_RNO (
+       .A(un13_lock_15),
+       .B(pcount[15]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_15)
+);
+defparam un1_pcount_diff_1_cry_15_0_RNO.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_13_0_RNO_0 (
+       .A(un13_lock_14),
+       .B(pcount[14]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_14)
+);
+defparam un1_pcount_diff_1_cry_13_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_13_0_RNO (
+       .A(un13_lock_13),
+       .B(pcount[13]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_13)
+);
+defparam un1_pcount_diff_1_cry_13_0_RNO.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_11_0_RNO_0 (
+       .A(un13_lock_12),
+       .B(pcount[12]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_12)
+);
+defparam un1_pcount_diff_1_cry_11_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_11_0_RNO (
+       .A(un13_lock_11),
+       .B(pcount[11]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_11)
+);
+defparam un1_pcount_diff_1_cry_11_0_RNO.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_9_0_RNO_0 (
+       .A(un13_lock_10),
+       .B(pcount[10]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_10)
+);
+defparam un1_pcount_diff_1_cry_9_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_9_0_RNO (
+       .A(un13_lock_9),
+       .B(pcount[9]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_9)
+);
+defparam un1_pcount_diff_1_cry_9_0_RNO.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_7_0_RNO_0 (
+       .A(un13_lock_8),
+       .B(pcount[8]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_8)
+);
+defparam un1_pcount_diff_1_cry_7_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_7_0_RNO (
+       .A(un13_lock_7),
+       .B(pcount[7]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_7)
+);
+defparam un1_pcount_diff_1_cry_7_0_RNO.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_5_0_RNO_0 (
+       .A(un13_lock_6),
+       .B(pcount[6]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_6)
+);
+defparam un1_pcount_diff_1_cry_5_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_5_0_RNO (
+       .A(un13_lock_5),
+       .B(pcount[5]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_5)
+);
+defparam un1_pcount_diff_1_cry_5_0_RNO.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_3_0_RNO_0 (
+       .A(un13_lock_4),
+       .B(pcount[4]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_4)
+);
+defparam un1_pcount_diff_1_cry_3_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_3_0_RNO (
+       .A(un13_lock_3),
+       .B(pcount[3]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_3)
+);
+defparam un1_pcount_diff_1_cry_3_0_RNO.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_1_0_RNO_0 (
+       .A(un13_lock_2),
+       .B(pcount[2]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_2)
+);
+defparam un1_pcount_diff_1_cry_1_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_1_0_RNO (
+       .A(un13_lock_1),
+       .B(pcount[1]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_1)
+);
+defparam un1_pcount_diff_1_cry_1_0_RNO.init=16'h5355;
+  LUT4 ppul_sync_p3_RNIU65C (
+       .A(un13_lock_21),
+       .B(ppul_sync_p3),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(N_7)
+);
+defparam ppul_sync_p3_RNIU65C.init=16'h2F20;
+  LUT4 \pcount_diff_RNO[0]  (
+       .A(ppul_sync_p1),
+       .B(ppul_sync_p2),
+       .C(pcount[0]),
+       .D(un13_lock_0),
+       .Z(un1_pcount_diff_i[0])
+);
+defparam \pcount_diff_RNO[0] .init=16'hFD20;
+// @16:1304
+  LUT4 rtc_ctrl_0 (
+       .A(rtc_ctrl4),
+       .B(rtc_ctrl),
+       .C(VCC),
+       .D(VCC),
+       .Z(N_2085_0)
+);
+defparam rtc_ctrl_0.init=16'hEEEE;
+// @16:1278
+  FD1P3DX unlock_reg (
+       .D(unlock_5),
+       .SP(unlock_1_sqmuxa_i),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(unlock)
+);
+// @16:1801
+  FD1S3DX \sll_state_reg[0]  (
+       .D(N_95_i),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(sll_state[0])
+);
+// @16:1801
+  FD1S3DX \sll_state_reg[1]  (
+       .D(N_97_i),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(sll_state[1])
+);
+// @16:1304
+  FD1S3DX rtc_pul_p1_reg (
+       .D(rtc_pul),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rtc_pul_p1)
+);
+// @16:1304
+  FD1P3DX rtc_pul_reg (
+       .D(rtc_pul5),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rtc_pul)
+);
+// @16:1304
+  FD1S3DX rtc_ctrl_reg (
+       .D(N_2085_0),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rtc_ctrl)
+);
+// @16:1350
+  FD1P3DX rstat_pclk_reg (
+       .D(rstat_pclk_2),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rstat_pclk)
+);
+// @16:1350
+  FD1P3DX \rhb_wait_cnt_reg[0]  (
+       .D(rhb_wait_cnt_s[0]),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_wait_cnt[0])
+);
+// @16:1350
+  FD1P3DX \rhb_wait_cnt_reg[1]  (
+       .D(rhb_wait_cnt_s[1]),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_wait_cnt[1])
+);
+// @16:1350
+  FD1P3DX \rhb_wait_cnt_reg[2]  (
+       .D(rhb_wait_cnt_s[2]),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_wait_cnt[2])
+);
+// @16:1350
+  FD1P3DX \rhb_wait_cnt_reg[3]  (
+       .D(rhb_wait_cnt_s[3]),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_wait_cnt[3])
+);
+// @16:1350
+  FD1P3DX \rhb_wait_cnt_reg[4]  (
+       .D(rhb_wait_cnt_s[4]),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_wait_cnt[4])
+);
+// @16:1350
+  FD1P3DX \rhb_wait_cnt_reg[5]  (
+       .D(rhb_wait_cnt_s[5]),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_wait_cnt[5])
+);
+// @16:1350
+  FD1P3DX \rhb_wait_cnt_reg[6]  (
+       .D(rhb_wait_cnt_s[6]),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_wait_cnt[6])
+);
+// @16:1350
+  FD1P3DX \rhb_wait_cnt_reg[7]  (
+       .D(rhb_wait_cnt_s[7]),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_wait_cnt[7])
+);
+// @16:1350
+  FD1S3DX rhb_sync_p2_reg (
+       .D(rhb_sync_p1),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_sync_p2)
+);
+// @16:1350
+  FD1S3DX rhb_sync_p1_reg (
+       .D(rhb_sync),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_sync_p1)
+);
+// @16:1304
+  FD1S3DX \rcount_reg[0]  (
+       .D(rcount_s[0]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[0])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[1]  (
+       .D(rcount_s[1]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[1])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[2]  (
+       .D(rcount_s[2]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[2])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[3]  (
+       .D(rcount_s[3]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[3])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[4]  (
+       .D(rcount_s[4]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[4])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[5]  (
+       .D(rcount_s[5]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[5])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[6]  (
+       .D(rcount_s[6]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[6])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[7]  (
+       .D(rcount_s[7]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[7])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[8]  (
+       .D(rcount_s[8]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[8])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[9]  (
+       .D(rcount_s[9]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[9])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[10]  (
+       .D(rcount_s[10]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[10])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[11]  (
+       .D(rcount_s[11]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[11])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[12]  (
+       .D(rcount_s[12]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[12])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[13]  (
+       .D(rcount_s[13]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[13])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[14]  (
+       .D(rcount_s[14]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[14])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[15]  (
+       .D(rcount_s[15]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[15])
+);
+// @16:1408
+  FD1S3DX ppul_sync_p3_reg (
+       .D(ppul_sync_p2),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(ppul_sync_p3)
+);
+// @16:1408
+  FD1S3DX ppul_sync_p2_reg (
+       .D(ppul_sync_p1),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(ppul_sync_p2)
+);
+// @16:1408
+  FD1S3DX ppul_sync_p1_reg (
+       .D(ppul_sync),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(ppul_sync_p1)
+);
+// @16:1879
+  FD1S3DX pll_lock_reg (
+       .D(N_53_i),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(pll_lock)
+);
+// @16:1759
+  FD1S3DX \phb_cnt_reg[0]  (
+       .D(phb_cnt_i[0]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(phb_cnt[0])
+);
+// @16:1759
+  FD1S3DX \phb_cnt_reg[1]  (
+       .D(phb_cnt_RNO[1]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(phb_cnt[1])
+);
+// @16:1759
+  FD1S3DX \phb_cnt_reg[2]  (
+       .D(phb_cnt_RNO[2]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(phb_cnt[2])
+);
+// @16:1759
+  FD1S3DX phb_reg (
+       .D(phb_cnt_i[2]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(phb)
+);
+// @16:1278
+  FD1S3DX pdiff_sync_p1_reg (
+       .D(pdiff_sync),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(pdiff_sync_p1)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[0]  (
+       .D(pcount_s[0]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[0])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[0]  (
+       .D(un1_pcount_diff_i[0]),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_0)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[1]  (
+       .D(pcount_s[1]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[1])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[1]  (
+       .D(un1_pcount_diff_1_cry_1_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_1)
+);
+// @16:1759
+  FD1P3BX \pcount_diff[2]  (
+       .D(un1_pcount_diff_1_cry_1_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_2)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[2]  (
+       .D(pcount_s[2]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[2])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[3]  (
+       .D(un1_pcount_diff_1_cry_3_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_3)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[3]  (
+       .D(pcount_s[3]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[3])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[4]  (
+       .D(un1_pcount_diff_1_cry_3_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_4)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[4]  (
+       .D(pcount_s[4]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[4])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[5]  (
+       .D(un1_pcount_diff_1_cry_5_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_5)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[5]  (
+       .D(pcount_s[5]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[5])
+);
+// @16:1759
+  FD1S3DX \pcount_reg[6]  (
+       .D(pcount_s[6]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[6])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[6]  (
+       .D(un1_pcount_diff_1_cry_5_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_6)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[7]  (
+       .D(pcount_s[7]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[7])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[7]  (
+       .D(un1_pcount_diff_1_cry_7_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_7)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[8]  (
+       .D(pcount_s[8]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[8])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[8]  (
+       .D(un1_pcount_diff_1_cry_7_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_8)
+);
+// @16:1759
+  FD1P3BX \pcount_diff[9]  (
+       .D(un1_pcount_diff_1_cry_9_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_9)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[9]  (
+       .D(pcount_s[9]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[9])
+);
+// @16:1759
+  FD1S3DX \pcount_reg[10]  (
+       .D(pcount_s[10]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[10])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[10]  (
+       .D(un1_pcount_diff_1_cry_9_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_10)
+);
+// @16:1759
+  FD1P3BX \pcount_diff[11]  (
+       .D(un1_pcount_diff_1_cry_11_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_11)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[11]  (
+       .D(pcount_s[11]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[11])
+);
+// @16:1759
+  FD1S3DX \pcount_reg[12]  (
+       .D(pcount_s[12]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[12])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[12]  (
+       .D(un1_pcount_diff_1_cry_11_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_12)
+);
+// @16:1759
+  FD1P3BX \pcount_diff[13]  (
+       .D(un1_pcount_diff_1_cry_13_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_13)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[13]  (
+       .D(pcount_s[13]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[13])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[14]  (
+       .D(un1_pcount_diff_1_cry_13_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_14)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[14]  (
+       .D(pcount_s[14]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[14])
+);
+// @16:1759
+  FD1S3DX \pcount_reg[15]  (
+       .D(pcount_s[15]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[15])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[15]  (
+       .D(un1_pcount_diff_1_cry_15_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_15)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[16]  (
+       .D(pcount_s[16]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[16])
+);
+// @16:1759
+  FD1P3DX \pcount_diff[16]  (
+       .D(un1_pcount_diff_1_cry_15_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(un13_lock_16)
+);
+// @16:1759
+  FD1P3DX \pcount_diff[17]  (
+       .D(un1_pcount_diff_1_cry_17_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(un13_lock_17)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[17]  (
+       .D(pcount_s[17]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[17])
+);
+// @16:1759
+  FD1P3DX \pcount_diff[18]  (
+       .D(un1_pcount_diff_1_cry_17_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(un13_lock_18)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[18]  (
+       .D(pcount_s[18]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[18])
+);
+// @16:1759
+  FD1S3DX \pcount_reg[19]  (
+       .D(pcount_s[19]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[19])
+);
+// @16:1759
+  FD1P3DX \pcount_diff[19]  (
+       .D(un1_pcount_diff_1_cry_19_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(un13_lock_19)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[20]  (
+       .D(pcount_s[20]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[20])
+);
+// @16:1759
+  FD1P3DX \pcount_diff[20]  (
+       .D(un1_pcount_diff_1_cry_19_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(un13_lock_20)
+);
+// @16:1759
+  FD1P3DX \pcount_diff[21]  (
+       .D(un1_pcount_diff_1_s_21_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(un13_lock_21)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[21]  (
+       .D(pcount_s[21]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[21])
+);
+// @16:1278
+  FD1P3DX lock_reg (
+       .D(lock_5),
+       .SP(lock_1_sqmuxa_i),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(lock)
+);
+// @16:1739
+  FD1S3DX \genblk5.rdiff_comp_lock[2]  (
+       .D(VCC),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rdiff_comp_lock[2])
+);
+// @16:1801
+  LUT4 \sll_state_RNO[0]  (
+       .A(N_98),
+       .B(lock),
+       .C(rstat_pclk),
+       .D(sll_state[0]),
+       .Z(N_95_i)
+);
+defparam \sll_state_RNO[0] .init=16'hE050;
+// @16:1334
+  LUT4 rtc_pul5_0_0 (
+       .A(rtc_pul5_0_o3),
+       .B(rtc_pul5_0_a3_6),
+       .C(rtc_pul5_0_a3_7),
+       .D(un1_rcount_1_0_a3),
+       .Z(rtc_pul5)
+);
+defparam rtc_pul5_0_0.init=16'hFF80;
+// @16:1389
+  LUT4 rstat_pclk_2_iv (
+       .A(rhb_wait_cnt12),
+       .B(rstat_pclk),
+       .C(un1_rhb_wait_cnt_4),
+       .D(un1_rhb_wait_cnt_5),
+       .Z(rstat_pclk_2)
+);
+defparam rstat_pclk_2_iv.init=16'hAEEE;
+// @16:1801
+  LUT4 \sll_state_RNO[1]  (
+       .A(N_99),
+       .B(rstat_pclk),
+       .C(sll_state[1]),
+       .D(unlock),
+       .Z(N_97_i)
+);
+defparam \sll_state_RNO[1] .init=16'h8088;
+// @16:1328
+  LUT4 rtc_ctrl4_0_a3 (
+       .A(rtc_ctrl4_0_a3_1),
+       .B(rtc_ctrl4_0_a3_12_4),
+       .C(rtc_ctrl4_0_a3_12_5),
+       .D(rtc_ctrl4_10),
+       .Z(rtc_ctrl4)
+);
+defparam rtc_ctrl4_0_a3.init=16'h8000;
+// @16:1319
+  LUT4 un1_rcount_1_0_a3_cZ (
+       .A(rtc_ctrl4_0_a3_12_4),
+       .B(rtc_ctrl4_0_a3_12_5),
+       .C(rtc_ctrl4_10),
+       .D(un1_rcount_1_0_a3_1),
+       .Z(un1_rcount_1_0_a3)
+);
+defparam un1_rcount_1_0_a3_cZ.init=16'h8000;
+// @16:1278
+  LUT4 lock_1_sqmuxa_i_cZ (
+       .A(lock),
+       .B(pdiff_sync),
+       .C(pdiff_sync_p1),
+       .D(VCC),
+       .Z(lock_1_sqmuxa_i)
+);
+defparam lock_1_sqmuxa_i_cZ.init=16'h7575;
+// @16:1278
+  LUT4 unlock_1_sqmuxa_i_cZ (
+       .A(pdiff_sync),
+       .B(pdiff_sync_p1),
+       .C(unlock),
+       .D(VCC),
+       .Z(unlock_1_sqmuxa_i)
+);
+defparam unlock_1_sqmuxa_i_cZ.init=16'h4F4F;
+// @16:1334
+  LUT4 rtc_pul5_0_o3_cZ (
+       .A(N_6),
+       .B(rcount[1]),
+       .C(rcount[2]),
+       .D(rcount[3]),
+       .Z(rtc_pul5_0_o3)
+);
+defparam rtc_pul5_0_o3_cZ.init=16'hAAAB;
+// @16:1334
+  LUT4 rtc_pul5_0_a3_7_cZ (
+       .A(rcount[7]),
+       .B(rcount[8]),
+       .C(rtc_pul5_0_a3_5),
+       .D(VCC),
+       .Z(rtc_pul5_0_a3_7)
+);
+defparam rtc_pul5_0_a3_7_cZ.init=16'h1010;
+// @16:1801
+  LUT4 \sll_state_ns_i_m4[1]  (
+       .A(lock),
+       .B(rtc_pul),
+       .C(rtc_pul_p1),
+       .D(sll_state[1]),
+       .Z(N_99)
+);
+defparam \sll_state_ns_i_m4[1] .init=16'hEF20;
+// @16:1879
+  LUT4 pll_lock_RNO (
+       .A(sll_state[0]),
+       .B(sll_state[1]),
+       .C(VCC),
+       .D(VCC),
+       .Z(N_53_i)
+);
+defparam pll_lock_RNO.init=16'h8888;
+// @16:1776
+  LUT4 \phb_cnt_RNO_cZ[2]  (
+       .A(phb_cnt[0]),
+       .B(phb_cnt[1]),
+       .C(phb_cnt[2]),
+       .D(VCC),
+       .Z(phb_cnt_RNO[2])
+);
+defparam \phb_cnt_RNO_cZ[2] .init=16'h7878;
+// @16:1801
+  LUT4 \sll_state_ns_i_o4[0]  (
+       .A(rtc_pul),
+       .B(rtc_pul_p1),
+       .C(sll_state[1]),
+       .D(VCC),
+       .Z(N_98)
+);
+defparam \sll_state_ns_i_o4[0] .init=16'hBFBF;
+// @16:1328
+  LUT4 rtc_ctrl4_0_a3_10 (
+       .A(rcount[1]),
+       .B(rcount[3]),
+       .C(rcount[6]),
+       .D(rcount[15]),
+       .Z(rtc_ctrl4_10)
+);
+defparam rtc_ctrl4_0_a3_10.init=16'h8000;
+// @16:1393
+  LUT4 un1_rhb_wait_cnt_4_cZ (
+       .A(rhb_wait_cnt[4]),
+       .B(rhb_wait_cnt[5]),
+       .C(rhb_wait_cnt[6]),
+       .D(rhb_wait_cnt[7]),
+       .Z(un1_rhb_wait_cnt_4)
+);
+defparam un1_rhb_wait_cnt_4_cZ.init=16'h8000;
+// @16:1393
+  LUT4 un1_rhb_wait_cnt_5_cZ (
+       .A(rhb_wait_cnt[0]),
+       .B(rhb_wait_cnt[1]),
+       .C(rhb_wait_cnt[2]),
+       .D(rhb_wait_cnt[3]),
+       .Z(un1_rhb_wait_cnt_5)
+);
+defparam un1_rhb_wait_cnt_5_cZ.init=16'h8000;
+// @16:1328
+  LUT4 rtc_ctrl4_0_a3_12_4_cZ (
+       .A(rcount[11]),
+       .B(rcount[12]),
+       .C(rcount[13]),
+       .D(rcount[14]),
+       .Z(rtc_ctrl4_0_a3_12_4)
+);
+defparam rtc_ctrl4_0_a3_12_4_cZ.init=16'h8000;
+// @16:1328
+  LUT4 rtc_ctrl4_0_a3_12_5_cZ (
+       .A(rcount[7]),
+       .B(rcount[8]),
+       .C(rcount[9]),
+       .D(rcount[10]),
+       .Z(rtc_ctrl4_0_a3_12_5)
+);
+defparam rtc_ctrl4_0_a3_12_5_cZ.init=16'h8000;
+// @16:1334
+  LUT4 rtc_pul5_0_a3_5_cZ (
+       .A(rcount[6]),
+       .B(rcount[13]),
+       .C(rcount[14]),
+       .D(rcount[15]),
+       .Z(rtc_pul5_0_a3_5)
+);
+defparam rtc_pul5_0_a3_5_cZ.init=16'h0001;
+// @16:1334
+  LUT4 rtc_pul5_0_a3_6_cZ (
+       .A(rcount[9]),
+       .B(rcount[10]),
+       .C(rcount[11]),
+       .D(rcount[12]),
+       .Z(rtc_pul5_0_a3_6)
+);
+defparam rtc_pul5_0_a3_6_cZ.init=16'h0001;
+// @16:1768
+  LUT4 pcount10_0_o3 (
+       .A(ppul_sync_p1),
+       .B(ppul_sync_p2),
+       .C(VCC),
+       .D(VCC),
+       .Z(N_8)
+);
+defparam pcount10_0_o3.init=16'hDDDD;
+// @16:1776
+  LUT4 \phb_cnt_RNO_cZ[1]  (
+       .A(phb_cnt[0]),
+       .B(phb_cnt[1]),
+       .C(VCC),
+       .D(VCC),
+       .Z(phb_cnt_RNO[1])
+);
+defparam \phb_cnt_RNO_cZ[1] .init=16'h6666;
+// @16:1328
+  LUT4 rtc_ctrl4_0_o3 (
+       .A(rcount[4]),
+       .B(rcount[5]),
+       .C(VCC),
+       .D(VCC),
+       .Z(N_6)
+);
+defparam rtc_ctrl4_0_o3.init=16'h7777;
+// @16:1286
+  LUT4 unlock_5_cZ (
+       .A(pdiff_sync),
+       .B(un13_unlock_cry_21),
+       .C(VCC),
+       .D(VCC),
+       .Z(unlock_5)
+);
+defparam unlock_5_cZ.init=16'h8888;
+// @16:1292
+  LUT4 lock_5_cZ (
+       .A(pdiff_sync),
+       .B(un13_lock_cry_21_i),
+       .C(VCC),
+       .D(VCC),
+       .Z(lock_5)
+);
+defparam lock_5_cZ.init=16'h8888;
+// @16:1389
+  LUT4 rhb_wait_cnt12_cZ (
+       .A(rhb_sync_p1),
+       .B(rhb_sync_p2),
+       .C(VCC),
+       .D(VCC),
+       .Z(rhb_wait_cnt12)
+);
+defparam rhb_wait_cnt12_cZ.init=16'h2222;
+// @16:1786
+  LUT4 \un1_pcount_diff_cZ[0]  (
+       .A(un13_lock_0),
+       .B(pcount[0]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff[0])
+);
+defparam \un1_pcount_diff_cZ[0] .init=16'h5355;
+// @16:1319
+  LUT4 un1_rcount_1_0_a3_1_cZ (
+       .A(rcount[2]),
+       .B(rcount[0]),
+       .C(rcount[5]),
+       .D(rcount[4]),
+       .Z(un1_rcount_1_0_a3_1)
+);
+defparam un1_rcount_1_0_a3_1_cZ.init=16'h8000;
+// @16:1350
+  LUT4 rhb_sync_p2_RNIU9TG1 (
+       .A(un1_rhb_wait_cnt_5),
+       .B(un1_rhb_wait_cnt_4),
+       .C(rhb_sync_p2),
+       .D(rhb_sync_p1),
+       .Z(rhb_wait_cnt_scalar)
+);
+defparam rhb_sync_p2_RNIU9TG1.init=16'h7077;
+  CCU2C \pcount_cry_0[0]  (
+       .A0(VCC),
+       .B0(N_8),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_9),
+       .COUT(pcount_cry[0]),
+       .S0(pcount_cry_0_S0[0]),
+       .S1(pcount_s[0])
+);
+defparam \pcount_cry_0[0] .INIT0=16'h500c;
+defparam \pcount_cry_0[0] .INIT1=16'h8000;
+defparam \pcount_cry_0[0] .INJECT1_0="NO";
+defparam \pcount_cry_0[0] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[1]  (
+       .A0(N_8),
+       .B0(pcount[1]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[0]),
+       .COUT(pcount_cry[2]),
+       .S0(pcount_s[1]),
+       .S1(pcount_s[2])
+);
+defparam \pcount_cry_0[1] .INIT0=16'h8000;
+defparam \pcount_cry_0[1] .INIT1=16'h8000;
+defparam \pcount_cry_0[1] .INJECT1_0="NO";
+defparam \pcount_cry_0[1] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[3]  (
+       .A0(N_8),
+       .B0(pcount[3]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[4]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[2]),
+       .COUT(pcount_cry[4]),
+       .S0(pcount_s[3]),
+       .S1(pcount_s[4])
+);
+defparam \pcount_cry_0[3] .INIT0=16'h8000;
+defparam \pcount_cry_0[3] .INIT1=16'h8000;
+defparam \pcount_cry_0[3] .INJECT1_0="NO";
+defparam \pcount_cry_0[3] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[5]  (
+       .A0(N_8),
+       .B0(pcount[5]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[6]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[4]),
+       .COUT(pcount_cry[6]),
+       .S0(pcount_s[5]),
+       .S1(pcount_s[6])
+);
+defparam \pcount_cry_0[5] .INIT0=16'h8000;
+defparam \pcount_cry_0[5] .INIT1=16'h8000;
+defparam \pcount_cry_0[5] .INJECT1_0="NO";
+defparam \pcount_cry_0[5] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[7]  (
+       .A0(N_8),
+       .B0(pcount[7]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[8]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[6]),
+       .COUT(pcount_cry[8]),
+       .S0(pcount_s[7]),
+       .S1(pcount_s[8])
+);
+defparam \pcount_cry_0[7] .INIT0=16'h8000;
+defparam \pcount_cry_0[7] .INIT1=16'h8000;
+defparam \pcount_cry_0[7] .INJECT1_0="NO";
+defparam \pcount_cry_0[7] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[9]  (
+       .A0(N_8),
+       .B0(pcount[9]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[10]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[8]),
+       .COUT(pcount_cry[10]),
+       .S0(pcount_s[9]),
+       .S1(pcount_s[10])
+);
+defparam \pcount_cry_0[9] .INIT0=16'h8000;
+defparam \pcount_cry_0[9] .INIT1=16'h8000;
+defparam \pcount_cry_0[9] .INJECT1_0="NO";
+defparam \pcount_cry_0[9] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[11]  (
+       .A0(N_8),
+       .B0(pcount[11]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[12]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[10]),
+       .COUT(pcount_cry[12]),
+       .S0(pcount_s[11]),
+       .S1(pcount_s[12])
+);
+defparam \pcount_cry_0[11] .INIT0=16'h8000;
+defparam \pcount_cry_0[11] .INIT1=16'h8000;
+defparam \pcount_cry_0[11] .INJECT1_0="NO";
+defparam \pcount_cry_0[11] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[13]  (
+       .A0(N_8),
+       .B0(pcount[13]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[14]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[12]),
+       .COUT(pcount_cry[14]),
+       .S0(pcount_s[13]),
+       .S1(pcount_s[14])
+);
+defparam \pcount_cry_0[13] .INIT0=16'h8000;
+defparam \pcount_cry_0[13] .INIT1=16'h8000;
+defparam \pcount_cry_0[13] .INJECT1_0="NO";
+defparam \pcount_cry_0[13] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[15]  (
+       .A0(N_8),
+       .B0(pcount[15]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[16]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[14]),
+       .COUT(pcount_cry[16]),
+       .S0(pcount_s[15]),
+       .S1(pcount_s[16])
+);
+defparam \pcount_cry_0[15] .INIT0=16'h8000;
+defparam \pcount_cry_0[15] .INIT1=16'h8000;
+defparam \pcount_cry_0[15] .INJECT1_0="NO";
+defparam \pcount_cry_0[15] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[17]  (
+       .A0(N_8),
+       .B0(pcount[17]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[18]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[16]),
+       .COUT(pcount_cry[18]),
+       .S0(pcount_s[17]),
+       .S1(pcount_s[18])
+);
+defparam \pcount_cry_0[17] .INIT0=16'h8000;
+defparam \pcount_cry_0[17] .INIT1=16'h8000;
+defparam \pcount_cry_0[17] .INJECT1_0="NO";
+defparam \pcount_cry_0[17] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[19]  (
+       .A0(N_8),
+       .B0(pcount[19]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[20]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[18]),
+       .COUT(pcount_cry[20]),
+       .S0(pcount_s[19]),
+       .S1(pcount_s[20])
+);
+defparam \pcount_cry_0[19] .INIT0=16'h8000;
+defparam \pcount_cry_0[19] .INIT1=16'h8000;
+defparam \pcount_cry_0[19] .INJECT1_0="NO";
+defparam \pcount_cry_0[19] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_s_0[21]  (
+       .A0(N_8),
+       .B0(pcount[21]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[20]),
+       .COUT(pcount_s_0_COUT[21]),
+       .S0(pcount_s[21]),
+       .S1(pcount_s_0_S1[21])
+);
+defparam \pcount_s_0[21] .INIT0=16'h800a;
+defparam \pcount_s_0[21] .INIT1=16'h5003;
+defparam \pcount_s_0[21] .INJECT1_0="NO";
+defparam \pcount_s_0[21] .INJECT1_1="NO";
+  CCU2C \rcount_cry_0[0]  (
+       .A0(VCC),
+       .B0(un1_rcount_1_0_a3),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_rcount_1_0_a3),
+       .B1(rcount[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_5),
+       .COUT(rcount_cry[0]),
+       .S0(rcount_cry_0_S0[0]),
+       .S1(rcount_s[0])
+);
+defparam \rcount_cry_0[0] .INIT0=16'h5003;
+defparam \rcount_cry_0[0] .INIT1=16'h4000;
+defparam \rcount_cry_0[0] .INJECT1_0="NO";
+defparam \rcount_cry_0[0] .INJECT1_1="NO";
+// @16:1304
+  CCU2C \rcount_cry_0[1]  (
+       .A0(un1_rcount_1_0_a3),
+       .B0(rcount[1]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_rcount_1_0_a3),
+       .B1(rcount[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rcount_cry[0]),
+       .COUT(rcount_cry[2]),
+       .S0(rcount_s[1]),
+       .S1(rcount_s[2])
+);
+defparam \rcount_cry_0[1] .INIT0=16'h4000;
+defparam \rcount_cry_0[1] .INIT1=16'h4000;
+defparam \rcount_cry_0[1] .INJECT1_0="NO";
+defparam \rcount_cry_0[1] .INJECT1_1="NO";
+// @16:1304
+  CCU2C \rcount_cry_0[3]  (
+       .A0(un1_rcount_1_0_a3),
+       .B0(rcount[3]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_rcount_1_0_a3),
+       .B1(rcount[4]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rcount_cry[2]),
+       .COUT(rcount_cry[4]),
+       .S0(rcount_s[3]),
+       .S1(rcount_s[4])
+);
+defparam \rcount_cry_0[3] .INIT0=16'h4000;
+defparam \rcount_cry_0[3] .INIT1=16'h4000;
+defparam \rcount_cry_0[3] .INJECT1_0="NO";
+defparam \rcount_cry_0[3] .INJECT1_1="NO";
+// @16:1304
+  CCU2C \rcount_cry_0[5]  (
+       .A0(un1_rcount_1_0_a3),
+       .B0(rcount[5]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_rcount_1_0_a3),
+       .B1(rcount[6]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rcount_cry[4]),
+       .COUT(rcount_cry[6]),
+       .S0(rcount_s[5]),
+       .S1(rcount_s[6])
+);
+defparam \rcount_cry_0[5] .INIT0=16'h4000;
+defparam \rcount_cry_0[5] .INIT1=16'h4000;
+defparam \rcount_cry_0[5] .INJECT1_0="NO";
+defparam \rcount_cry_0[5] .INJECT1_1="NO";
+// @16:1304
+  CCU2C \rcount_cry_0[7]  (
+       .A0(un1_rcount_1_0_a3),
+       .B0(rcount[7]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_rcount_1_0_a3),
+       .B1(rcount[8]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rcount_cry[6]),
+       .COUT(rcount_cry[8]),
+       .S0(rcount_s[7]),
+       .S1(rcount_s[8])
+);
+defparam \rcount_cry_0[7] .INIT0=16'h4000;
+defparam \rcount_cry_0[7] .INIT1=16'h4000;
+defparam \rcount_cry_0[7] .INJECT1_0="NO";
+defparam \rcount_cry_0[7] .INJECT1_1="NO";
+// @16:1304
+  CCU2C \rcount_cry_0[9]  (
+       .A0(un1_rcount_1_0_a3),
+       .B0(rcount[9]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_rcount_1_0_a3),
+       .B1(rcount[10]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rcount_cry[8]),
+       .COUT(rcount_cry[10]),
+       .S0(rcount_s[9]),
+       .S1(rcount_s[10])
+);
+defparam \rcount_cry_0[9] .INIT0=16'h4000;
+defparam \rcount_cry_0[9] .INIT1=16'h4000;
+defparam \rcount_cry_0[9] .INJECT1_0="NO";
+defparam \rcount_cry_0[9] .INJECT1_1="NO";
+// @16:1304
+  CCU2C \rcount_cry_0[11]  (
+       .A0(un1_rcount_1_0_a3),
+       .B0(rcount[11]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_rcount_1_0_a3),
+       .B1(rcount[12]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rcount_cry[10]),
+       .COUT(rcount_cry[12]),
+       .S0(rcount_s[11]),
+       .S1(rcount_s[12])
+);
+defparam \rcount_cry_0[11] .INIT0=16'h4000;
+defparam \rcount_cry_0[11] .INIT1=16'h4000;
+defparam \rcount_cry_0[11] .INJECT1_0="NO";
+defparam \rcount_cry_0[11] .INJECT1_1="NO";
+// @16:1304
+  CCU2C \rcount_cry_0[13]  (
+       .A0(un1_rcount_1_0_a3),
+       .B0(rcount[13]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_rcount_1_0_a3),
+       .B1(rcount[14]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rcount_cry[12]),
+       .COUT(rcount_cry[14]),
+       .S0(rcount_s[13]),
+       .S1(rcount_s[14])
+);
+defparam \rcount_cry_0[13] .INIT0=16'h4000;
+defparam \rcount_cry_0[13] .INIT1=16'h4000;
+defparam \rcount_cry_0[13] .INJECT1_0="NO";
+defparam \rcount_cry_0[13] .INJECT1_1="NO";
+// @16:1304
+  CCU2C \rcount_s_0[15]  (
+       .A0(un1_rcount_1_0_a3),
+       .B0(rcount[15]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rcount_cry[14]),
+       .COUT(rcount_s_0_COUT[15]),
+       .S0(rcount_s[15]),
+       .S1(rcount_s_0_S1[15])
+);
+defparam \rcount_s_0[15] .INIT0=16'h4005;
+defparam \rcount_s_0[15] .INIT1=16'h5003;
+defparam \rcount_s_0[15] .INJECT1_0="NO";
+defparam \rcount_s_0[15] .INJECT1_1="NO";
+  CCU2C \rhb_wait_cnt_cry_0[0]  (
+       .A0(VCC),
+       .B0(rhb_wait_cnt_scalar),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rhb_wait_cnt_scalar),
+       .B1(rhb_wait_cnt[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_4),
+       .COUT(rhb_wait_cnt_cry[0]),
+       .S0(rhb_wait_cnt_cry_0_S0[0]),
+       .S1(rhb_wait_cnt_s[0])
+);
+defparam \rhb_wait_cnt_cry_0[0] .INIT0=16'h500c;
+defparam \rhb_wait_cnt_cry_0[0] .INIT1=16'h8000;
+defparam \rhb_wait_cnt_cry_0[0] .INJECT1_0="NO";
+defparam \rhb_wait_cnt_cry_0[0] .INJECT1_1="NO";
+// @16:1350
+  CCU2C \rhb_wait_cnt_cry_0[1]  (
+       .A0(rhb_wait_cnt_scalar),
+       .B0(rhb_wait_cnt[1]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rhb_wait_cnt_scalar),
+       .B1(rhb_wait_cnt[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rhb_wait_cnt_cry[0]),
+       .COUT(rhb_wait_cnt_cry[2]),
+       .S0(rhb_wait_cnt_s[1]),
+       .S1(rhb_wait_cnt_s[2])
+);
+defparam \rhb_wait_cnt_cry_0[1] .INIT0=16'h8000;
+defparam \rhb_wait_cnt_cry_0[1] .INIT1=16'h8000;
+defparam \rhb_wait_cnt_cry_0[1] .INJECT1_0="NO";
+defparam \rhb_wait_cnt_cry_0[1] .INJECT1_1="NO";
+// @16:1350
+  CCU2C \rhb_wait_cnt_cry_0[3]  (
+       .A0(rhb_wait_cnt_scalar),
+       .B0(rhb_wait_cnt[3]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rhb_wait_cnt_scalar),
+       .B1(rhb_wait_cnt[4]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rhb_wait_cnt_cry[2]),
+       .COUT(rhb_wait_cnt_cry[4]),
+       .S0(rhb_wait_cnt_s[3]),
+       .S1(rhb_wait_cnt_s[4])
+);
+defparam \rhb_wait_cnt_cry_0[3] .INIT0=16'h8000;
+defparam \rhb_wait_cnt_cry_0[3] .INIT1=16'h8000;
+defparam \rhb_wait_cnt_cry_0[3] .INJECT1_0="NO";
+defparam \rhb_wait_cnt_cry_0[3] .INJECT1_1="NO";
+// @16:1350
+  CCU2C \rhb_wait_cnt_cry_0[5]  (
+       .A0(rhb_wait_cnt_scalar),
+       .B0(rhb_wait_cnt[5]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rhb_wait_cnt_scalar),
+       .B1(rhb_wait_cnt[6]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rhb_wait_cnt_cry[4]),
+       .COUT(rhb_wait_cnt_cry[6]),
+       .S0(rhb_wait_cnt_s[5]),
+       .S1(rhb_wait_cnt_s[6])
+);
+defparam \rhb_wait_cnt_cry_0[5] .INIT0=16'h8000;
+defparam \rhb_wait_cnt_cry_0[5] .INIT1=16'h8000;
+defparam \rhb_wait_cnt_cry_0[5] .INJECT1_0="NO";
+defparam \rhb_wait_cnt_cry_0[5] .INJECT1_1="NO";
+// @16:1350
+  CCU2C \rhb_wait_cnt_s_0[7]  (
+       .A0(rhb_wait_cnt_scalar),
+       .B0(rhb_wait_cnt[7]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rhb_wait_cnt_cry[6]),
+       .COUT(rhb_wait_cnt_s_0_COUT[7]),
+       .S0(rhb_wait_cnt_s[7]),
+       .S1(rhb_wait_cnt_s_0_S1[7])
+);
+defparam \rhb_wait_cnt_s_0[7] .INIT0=16'h800a;
+defparam \rhb_wait_cnt_s_0[7] .INIT1=16'h5003;
+defparam \rhb_wait_cnt_s_0[7] .INJECT1_0="NO";
+defparam \rhb_wait_cnt_s_0[7] .INJECT1_1="NO";
+  CCU2C un1_pcount_diff_1_cry_0_0 (
+       .A0(VCC),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff[0]),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_3),
+       .COUT(un1_pcount_diff_1_cry_0),
+       .S0(un1_pcount_diff_1_cry_0_0_S0),
+       .S1(un1_pcount_diff_1_cry_0_0_S1)
+);
+defparam un1_pcount_diff_1_cry_0_0.INIT0=16'h5003;
+defparam un1_pcount_diff_1_cry_0_0.INIT1=16'h500f;
+defparam un1_pcount_diff_1_cry_0_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_0_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_1_0 (
+       .A0(un1_pcount_diff_1_axb_1),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_2),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_0),
+       .COUT(un1_pcount_diff_1_cry_2),
+       .S0(un1_pcount_diff_1_cry_1_0_S0),
+       .S1(un1_pcount_diff_1_cry_1_0_S1)
+);
+defparam un1_pcount_diff_1_cry_1_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_1_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_1_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_1_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_3_0 (
+       .A0(un1_pcount_diff_1_axb_3),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_4),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_2),
+       .COUT(un1_pcount_diff_1_cry_4),
+       .S0(un1_pcount_diff_1_cry_3_0_S0),
+       .S1(un1_pcount_diff_1_cry_3_0_S1)
+);
+defparam un1_pcount_diff_1_cry_3_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_3_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_3_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_3_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_5_0 (
+       .A0(un1_pcount_diff_1_axb_5),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_6),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_4),
+       .COUT(un1_pcount_diff_1_cry_6),
+       .S0(un1_pcount_diff_1_cry_5_0_S0),
+       .S1(un1_pcount_diff_1_cry_5_0_S1)
+);
+defparam un1_pcount_diff_1_cry_5_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_5_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_5_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_5_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_7_0 (
+       .A0(un1_pcount_diff_1_axb_7),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_8),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_6),
+       .COUT(un1_pcount_diff_1_cry_8),
+       .S0(un1_pcount_diff_1_cry_7_0_S0),
+       .S1(un1_pcount_diff_1_cry_7_0_S1)
+);
+defparam un1_pcount_diff_1_cry_7_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_7_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_7_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_7_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_9_0 (
+       .A0(un1_pcount_diff_1_axb_9),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_10),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_8),
+       .COUT(un1_pcount_diff_1_cry_10),
+       .S0(un1_pcount_diff_1_cry_9_0_S0),
+       .S1(un1_pcount_diff_1_cry_9_0_S1)
+);
+defparam un1_pcount_diff_1_cry_9_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_9_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_9_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_9_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_11_0 (
+       .A0(un1_pcount_diff_1_axb_11),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_12),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_10),
+       .COUT(un1_pcount_diff_1_cry_12),
+       .S0(un1_pcount_diff_1_cry_11_0_S0),
+       .S1(un1_pcount_diff_1_cry_11_0_S1)
+);
+defparam un1_pcount_diff_1_cry_11_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_11_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_11_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_11_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_13_0 (
+       .A0(un1_pcount_diff_1_axb_13),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_14),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_12),
+       .COUT(un1_pcount_diff_1_cry_14),
+       .S0(un1_pcount_diff_1_cry_13_0_S0),
+       .S1(un1_pcount_diff_1_cry_13_0_S1)
+);
+defparam un1_pcount_diff_1_cry_13_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_13_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_13_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_13_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_15_0 (
+       .A0(un1_pcount_diff_1_axb_15),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_16),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_14),
+       .COUT(un1_pcount_diff_1_cry_16),
+       .S0(un1_pcount_diff_1_cry_15_0_S0),
+       .S1(un1_pcount_diff_1_cry_15_0_S1)
+);
+defparam un1_pcount_diff_1_cry_15_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_15_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_15_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_15_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_17_0 (
+       .A0(N_8),
+       .B0(rdiff_comp_lock[2]),
+       .C0(un1_pcount_diff_1_cry_17_0_RNO),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_18),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_16),
+       .COUT(un1_pcount_diff_1_cry_18),
+       .S0(un1_pcount_diff_1_cry_17_0_S0),
+       .S1(un1_pcount_diff_1_cry_17_0_S1)
+);
+defparam un1_pcount_diff_1_cry_17_0.INIT0=16'hb404;
+defparam un1_pcount_diff_1_cry_17_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_17_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_17_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_19_0 (
+       .A0(un1_pcount_diff_1_axb_19),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_20),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_18),
+       .COUT(un1_pcount_diff_1_cry_20),
+       .S0(un1_pcount_diff_1_cry_19_0_S0),
+       .S1(un1_pcount_diff_1_cry_19_0_S1)
+);
+defparam un1_pcount_diff_1_cry_19_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_19_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_19_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_19_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_s_21_0 (
+       .A0(pcount[21]),
+       .B0(un13_lock_21),
+       .C0(N_8),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_20),
+       .COUT(un1_pcount_diff_1_s_21_0_COUT),
+       .S0(un1_pcount_diff_1_s_21_0_S0),
+       .S1(un1_pcount_diff_1_s_21_0_S1)
+);
+defparam un1_pcount_diff_1_s_21_0.INIT0=16'h350a;
+defparam un1_pcount_diff_1_s_21_0.INIT1=16'h5003;
+defparam un1_pcount_diff_1_s_21_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_s_21_0.INJECT1_1="NO";
+  CCU2C un13_lock_cry_0_0 (
+       .A0(VCC),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_0),
+       .B1(rdiff_comp_lock[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_2),
+       .COUT(un13_lock_cry_0),
+       .S0(un13_lock_cry_0_0_S0),
+       .S1(un13_lock_cry_0_0_S1)
+);
+defparam un13_lock_cry_0_0.INIT0=16'h5003;
+defparam un13_lock_cry_0_0.INIT1=16'h900a;
+defparam un13_lock_cry_0_0.INJECT1_0="NO";
+defparam un13_lock_cry_0_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_1_0 (
+       .A0(un13_lock_1),
+       .B0(rdiff_comp_lock[2]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_2),
+       .B1(rdiff_comp_lock[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_0),
+       .COUT(un13_lock_cry_2),
+       .S0(un13_lock_cry_1_0_S0),
+       .S1(un13_lock_cry_1_0_S1)
+);
+defparam un13_lock_cry_1_0.INIT0=16'h900a;
+defparam un13_lock_cry_1_0.INIT1=16'h900a;
+defparam un13_lock_cry_1_0.INJECT1_0="NO";
+defparam un13_lock_cry_1_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_3_0 (
+       .A0(un13_lock_3),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_4),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_2),
+       .COUT(un13_lock_cry_4),
+       .S0(un13_lock_cry_3_0_S0),
+       .S1(un13_lock_cry_3_0_S1)
+);
+defparam un13_lock_cry_3_0.INIT0=16'h500a;
+defparam un13_lock_cry_3_0.INIT1=16'h500a;
+defparam un13_lock_cry_3_0.INJECT1_0="NO";
+defparam un13_lock_cry_3_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_5_0 (
+       .A0(un13_lock_5),
+       .B0(rdiff_comp_lock[2]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_6),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_4),
+       .COUT(un13_lock_cry_6),
+       .S0(un13_lock_cry_5_0_S0),
+       .S1(un13_lock_cry_5_0_S1)
+);
+defparam un13_lock_cry_5_0.INIT0=16'h900a;
+defparam un13_lock_cry_5_0.INIT1=16'h500a;
+defparam un13_lock_cry_5_0.INJECT1_0="NO";
+defparam un13_lock_cry_5_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_7_0 (
+       .A0(un13_lock_7),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_8),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_6),
+       .COUT(un13_lock_cry_8),
+       .S0(un13_lock_cry_7_0_S0),
+       .S1(un13_lock_cry_7_0_S1)
+);
+defparam un13_lock_cry_7_0.INIT0=16'h500a;
+defparam un13_lock_cry_7_0.INIT1=16'h500a;
+defparam un13_lock_cry_7_0.INJECT1_0="NO";
+defparam un13_lock_cry_7_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_9_0 (
+       .A0(un13_lock_9),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_10),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_8),
+       .COUT(un13_lock_cry_10),
+       .S0(un13_lock_cry_9_0_S0),
+       .S1(un13_lock_cry_9_0_S1)
+);
+defparam un13_lock_cry_9_0.INIT0=16'h500a;
+defparam un13_lock_cry_9_0.INIT1=16'h500a;
+defparam un13_lock_cry_9_0.INJECT1_0="NO";
+defparam un13_lock_cry_9_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_11_0 (
+       .A0(un13_lock_11),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_12),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_10),
+       .COUT(un13_lock_cry_12),
+       .S0(un13_lock_cry_11_0_S0),
+       .S1(un13_lock_cry_11_0_S1)
+);
+defparam un13_lock_cry_11_0.INIT0=16'h500a;
+defparam un13_lock_cry_11_0.INIT1=16'h500a;
+defparam un13_lock_cry_11_0.INJECT1_0="NO";
+defparam un13_lock_cry_11_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_13_0 (
+       .A0(un13_lock_13),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_14),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_12),
+       .COUT(un13_lock_cry_14),
+       .S0(un13_lock_cry_13_0_S0),
+       .S1(un13_lock_cry_13_0_S1)
+);
+defparam un13_lock_cry_13_0.INIT0=16'h500a;
+defparam un13_lock_cry_13_0.INIT1=16'h500a;
+defparam un13_lock_cry_13_0.INJECT1_0="NO";
+defparam un13_lock_cry_13_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_15_0 (
+       .A0(un13_lock_15),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_16),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_14),
+       .COUT(un13_lock_cry_16),
+       .S0(un13_lock_cry_15_0_S0),
+       .S1(un13_lock_cry_15_0_S1)
+);
+defparam un13_lock_cry_15_0.INIT0=16'h500a;
+defparam un13_lock_cry_15_0.INIT1=16'h500a;
+defparam un13_lock_cry_15_0.INJECT1_0="NO";
+defparam un13_lock_cry_15_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_17_0 (
+       .A0(un13_lock_17),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_18),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_16),
+       .COUT(un13_lock_cry_18),
+       .S0(un13_lock_cry_17_0_S0),
+       .S1(un13_lock_cry_17_0_S1)
+);
+defparam un13_lock_cry_17_0.INIT0=16'h500a;
+defparam un13_lock_cry_17_0.INIT1=16'h500a;
+defparam un13_lock_cry_17_0.INJECT1_0="NO";
+defparam un13_lock_cry_17_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_19_0 (
+       .A0(un13_lock_19),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_20),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_18),
+       .COUT(un13_lock_cry_20),
+       .S0(un13_lock_cry_19_0_S0),
+       .S1(un13_lock_cry_19_0_S1)
+);
+defparam un13_lock_cry_19_0.INIT0=16'h500a;
+defparam un13_lock_cry_19_0.INIT1=16'h500a;
+defparam un13_lock_cry_19_0.INJECT1_0="NO";
+defparam un13_lock_cry_19_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_21_0 (
+       .A0(un13_lock_21),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_20),
+       .COUT(un13_lock_cry_21_0_COUT),
+       .S0(un13_lock_cry_21_0_S0),
+       .S1(un13_lock_cry_21_i)
+);
+defparam un13_lock_cry_21_0.INIT0=16'h500f;
+defparam un13_lock_cry_21_0.INIT1=16'ha003;
+defparam un13_lock_cry_21_0.INJECT1_0="NO";
+defparam un13_lock_cry_21_0.INJECT1_1="NO";
+  CCU2C un13_unlock_cry_0_0 (
+       .A0(VCC),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_0),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_1),
+       .COUT(un13_unlock_cry_0),
+       .S0(un13_unlock_cry_0_0_S0),
+       .S1(un13_unlock_cry_0_0_S1)
+);
+defparam un13_unlock_cry_0_0.INIT0=16'h5003;
+defparam un13_unlock_cry_0_0.INIT1=16'h500a;
+defparam un13_unlock_cry_0_0.INJECT1_0="NO";
+defparam un13_unlock_cry_0_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_1_0 (
+       .A0(un13_lock_1),
+       .B0(rdiff_comp_lock[2]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_2),
+       .B1(rdiff_comp_lock[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_0),
+       .COUT(un13_unlock_cry_2),
+       .S0(un13_unlock_cry_1_0_S0),
+       .S1(un13_unlock_cry_1_0_S1)
+);
+defparam un13_unlock_cry_1_0.INIT0=16'h900a;
+defparam un13_unlock_cry_1_0.INIT1=16'h900a;
+defparam un13_unlock_cry_1_0.INJECT1_0="NO";
+defparam un13_unlock_cry_1_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_3_0 (
+       .A0(un13_lock_3),
+       .B0(rdiff_comp_lock[2]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_4),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_2),
+       .COUT(un13_unlock_cry_4),
+       .S0(un13_unlock_cry_3_0_S0),
+       .S1(un13_unlock_cry_3_0_S1)
+);
+defparam un13_unlock_cry_3_0.INIT0=16'h900a;
+defparam un13_unlock_cry_3_0.INIT1=16'h500a;
+defparam un13_unlock_cry_3_0.INJECT1_0="NO";
+defparam un13_unlock_cry_3_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_5_0 (
+       .A0(un13_lock_5),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_6),
+       .B1(rdiff_comp_lock[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_4),
+       .COUT(un13_unlock_cry_6),
+       .S0(un13_unlock_cry_5_0_S0),
+       .S1(un13_unlock_cry_5_0_S1)
+);
+defparam un13_unlock_cry_5_0.INIT0=16'h500a;
+defparam un13_unlock_cry_5_0.INIT1=16'h900a;
+defparam un13_unlock_cry_5_0.INJECT1_0="NO";
+defparam un13_unlock_cry_5_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_7_0 (
+       .A0(un13_lock_7),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_8),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_6),
+       .COUT(un13_unlock_cry_8),
+       .S0(un13_unlock_cry_7_0_S0),
+       .S1(un13_unlock_cry_7_0_S1)
+);
+defparam un13_unlock_cry_7_0.INIT0=16'h500a;
+defparam un13_unlock_cry_7_0.INIT1=16'h500a;
+defparam un13_unlock_cry_7_0.INJECT1_0="NO";
+defparam un13_unlock_cry_7_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_9_0 (
+       .A0(un13_lock_9),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_10),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_8),
+       .COUT(un13_unlock_cry_10),
+       .S0(un13_unlock_cry_9_0_S0),
+       .S1(un13_unlock_cry_9_0_S1)
+);
+defparam un13_unlock_cry_9_0.INIT0=16'h500a;
+defparam un13_unlock_cry_9_0.INIT1=16'h500a;
+defparam un13_unlock_cry_9_0.INJECT1_0="NO";
+defparam un13_unlock_cry_9_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_11_0 (
+       .A0(un13_lock_11),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_12),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_10),
+       .COUT(un13_unlock_cry_12),
+       .S0(un13_unlock_cry_11_0_S0),
+       .S1(un13_unlock_cry_11_0_S1)
+);
+defparam un13_unlock_cry_11_0.INIT0=16'h500a;
+defparam un13_unlock_cry_11_0.INIT1=16'h500a;
+defparam un13_unlock_cry_11_0.INJECT1_0="NO";
+defparam un13_unlock_cry_11_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_13_0 (
+       .A0(un13_lock_13),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_14),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_12),
+       .COUT(un13_unlock_cry_14),
+       .S0(un13_unlock_cry_13_0_S0),
+       .S1(un13_unlock_cry_13_0_S1)
+);
+defparam un13_unlock_cry_13_0.INIT0=16'h500a;
+defparam un13_unlock_cry_13_0.INIT1=16'h500a;
+defparam un13_unlock_cry_13_0.INJECT1_0="NO";
+defparam un13_unlock_cry_13_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_15_0 (
+       .A0(un13_lock_15),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_16),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_14),
+       .COUT(un13_unlock_cry_16),
+       .S0(un13_unlock_cry_15_0_S0),
+       .S1(un13_unlock_cry_15_0_S1)
+);
+defparam un13_unlock_cry_15_0.INIT0=16'h500a;
+defparam un13_unlock_cry_15_0.INIT1=16'h500a;
+defparam un13_unlock_cry_15_0.INJECT1_0="NO";
+defparam un13_unlock_cry_15_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_17_0 (
+       .A0(un13_lock_17),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_18),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_16),
+       .COUT(un13_unlock_cry_18),
+       .S0(un13_unlock_cry_17_0_S0),
+       .S1(un13_unlock_cry_17_0_S1)
+);
+defparam un13_unlock_cry_17_0.INIT0=16'h500a;
+defparam un13_unlock_cry_17_0.INIT1=16'h500a;
+defparam un13_unlock_cry_17_0.INJECT1_0="NO";
+defparam un13_unlock_cry_17_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_19_0 (
+       .A0(un13_lock_19),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_20),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_18),
+       .COUT(un13_unlock_cry_20),
+       .S0(un13_unlock_cry_19_0_S0),
+       .S1(un13_unlock_cry_19_0_S1)
+);
+defparam un13_unlock_cry_19_0.INIT0=16'h500a;
+defparam un13_unlock_cry_19_0.INIT1=16'h500a;
+defparam un13_unlock_cry_19_0.INJECT1_0="NO";
+defparam un13_unlock_cry_19_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_21_0 (
+       .A0(un13_lock_21),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_20),
+       .COUT(un13_unlock_cry_21_0_COUT),
+       .S0(un13_unlock_cry_21_0_S0),
+       .S1(un13_unlock_cry_21)
+);
+defparam un13_unlock_cry_21_0.INIT0=16'h500f;
+defparam un13_unlock_cry_21_0.INIT1=16'h5003;
+defparam un13_unlock_cry_21_0.INJECT1_0="NO";
+defparam un13_unlock_cry_21_0.INJECT1_1="NO";
+//@16:1801
+//@8:424
+// @16:1211
+  sync_0s phb_sync_inst (
+       .phb(phb),
+       .rhb_sync(rhb_sync),
+       .sli_rst(sli_rst),
+       .pll_refclki(pll_refclki)
+);
+// @16:1220
+  sync_0s_6 rtc_sync_inst (
+       .rtc_pul(rtc_pul),
+       .ppul_sync(ppul_sync),
+       .sli_rst(sli_rst),
+       .tx_pclk(tx_pclk)
+);
+// @16:1228
+  sync_0s_0 pdiff_sync_inst (
+       .ppul_sync(ppul_sync),
+       .pdiff_sync(pdiff_sync),
+       .sli_rst(sli_rst),
+       .pll_refclki(pll_refclki)
+);
+  VHI VCC_0 (
+       .Z(VCC)
+);
+// @16:865
+  VLO GND_cZ (
+       .Z(GND)
+);
+endmodule /* sgmii_ecp5sll_core_Z1_layer1 */
+
+module sgmii_ecp5rsl_core_Z2_layer1 (
+  rx_pcs_rst_c,
+  tx_pcs_rst_c,
+  tx_serdes_rst_c,
+  serdes_rst_dual_c,
+  rsl_tx_pcs_rst_c,
+  rsl_rx_serdes_rst_c,
+  rsl_serdes_rst_dual_c,
+  rsl_tx_serdes_rst_c,
+  rsl_tx_rdy,
+  pll_lock_i,
+  pll_refclki,
+  rsl_rx_rdy,
+  rsl_rst,
+  rxrefclk,
+  rsl_disable,
+  rx_serdes_rst_c,
+  rsl_rx_pcs_rst_c,
+  rst_dual_c,
+  rx_cdr_lol_s,
+  rx_los_low_s
+)
+;
+input rx_pcs_rst_c ;
+input tx_pcs_rst_c ;
+input tx_serdes_rst_c ;
+input serdes_rst_dual_c ;
+output rsl_tx_pcs_rst_c ;
+output rsl_rx_serdes_rst_c ;
+output rsl_serdes_rst_dual_c ;
+output rsl_tx_serdes_rst_c ;
+output rsl_tx_rdy ;
+input pll_lock_i ;
+input pll_refclki ;
+output rsl_rx_rdy ;
+input rsl_rst ;
+input rxrefclk ;
+input rsl_disable ;
+input rx_serdes_rst_c ;
+output rsl_rx_pcs_rst_c ;
+input rst_dual_c ;
+input rx_cdr_lol_s ;
+input rx_los_low_s ;
+wire rx_pcs_rst_c ;
+wire tx_pcs_rst_c ;
+wire tx_serdes_rst_c ;
+wire serdes_rst_dual_c ;
+wire rsl_tx_pcs_rst_c ;
+wire rsl_rx_serdes_rst_c ;
+wire rsl_serdes_rst_dual_c ;
+wire rsl_tx_serdes_rst_c ;
+wire rsl_tx_rdy ;
+wire pll_lock_i ;
+wire pll_refclki ;
+wire rsl_rx_rdy ;
+wire rsl_rst ;
+wire rxrefclk ;
+wire rsl_disable ;
+wire rx_serdes_rst_c ;
+wire rsl_rx_pcs_rst_c ;
+wire rst_dual_c ;
+wire rx_cdr_lol_s ;
+wire rx_los_low_s ;
+wire [1:0] rxs_cnt;
+wire [1:0] rxs_cnt_3;
+wire [0:0] rxpr_appd_RNO;
+wire [2:0] plol0_cnt;
+wire [2:0] plol0_cnt_3;
+wire [0:0] rxsr_appd;
+wire [1:0] rxs_cnt_QN;
+wire [3:0] rlos_db_cnt;
+wire [3:0] rlos_db_cnt_QN;
+wire [17:0] rlols0_cnt_s;
+wire [17:0] rlols0_cnt;
+wire [17:0] rlols0_cnt_QN;
+wire [3:0] rlol_db_cnt;
+wire [3:0] rlol_db_cnt_QN;
+wire [18:0] rlol1_cnt_s;
+wire [18:0] rlol1_cnt;
+wire [18:0] rlol1_cnt_QN;
+wire [11:0] rxr_wt_cnt_s;
+wire [11:0] rxr_wt_cnt;
+wire [11:0] rxr_wt_cnt_QN;
+wire [0:0] rxsr_appd_QN;
+wire [0:0] rxpr_appd;
+wire [0:0] rxpr_appd_QN;
+wire [1:0] txs_cnt;
+wire [1:0] txs_cnt_QN;
+wire [1:1] txs_cnt_RNO;
+wire [1:0] txp_cnt;
+wire [1:0] txp_cnt_QN;
+wire [1:1] txp_cnt_RNO;
+wire [19:0] plol_cnt_s;
+wire [19:0] plol_cnt;
+wire [19:0] plol_cnt_QN;
+wire [2:0] plol0_cnt_QN;
+wire [11:0] txr_wt_cnt_s;
+wire [11:0] txr_wt_cnt;
+wire [11:0] txr_wt_cnt_QN;
+wire [0:0] txpr_appd;
+wire [0:0] txpr_appd_QN;
+wire [0:0] un1_rlol_db_cnt_zero;
+wire [0:0] un1_rlos_db_cnt_zero;
+wire [0:0] un1_rlol_db_cnt_zero_bm;
+wire [0:0] un1_rlol_db_cnt_zero_am;
+wire [0:0] un1_rlos_db_cnt_zero_bm;
+wire [0:0] un1_rlos_db_cnt_zero_am;
+wire [16:0] rlol1_cnt_cry;
+wire [0:0] rlol1_cnt_cry_0_S0;
+wire [17:17] rlol1_cnt_cry_0_COUT;
+wire [16:0] rlols0_cnt_cry;
+wire [0:0] rlols0_cnt_cry_0_S0;
+wire [17:17] rlols0_cnt_s_0_COUT;
+wire [17:17] rlols0_cnt_s_0_S1;
+wire [10:0] txr_wt_cnt_cry;
+wire [0:0] txr_wt_cnt_cry_0_S0;
+wire [11:11] txr_wt_cnt_s_0_COUT;
+wire [11:11] txr_wt_cnt_s_0_S1;
+wire [10:0] rxr_wt_cnt_cry;
+wire [0:0] rxr_wt_cnt_cry_0_S0;
+wire [11:11] rxr_wt_cnt_s_0_COUT;
+wire [11:11] rxr_wt_cnt_s_0_S1;
+wire [18:0] plol_cnt_cry;
+wire [0:0] plol_cnt_cry_0_S0;
+wire [19:19] plol_cnt_s_0_COUT;
+wire [19:19] plol_cnt_s_0_S1;
+wire rxs_rst ;
+wire VCC ;
+wire dual_or_rserd_rst ;
+wire plol0_cnt9 ;
+wire waita_plol0 ;
+wire rlos_db_p1 ;
+wire rlos_db ;
+wire rxp_rst25 ;
+wire rlol_db ;
+wire un1_rui_rst_dual_c_1_1 ;
+wire rx_all_well ;
+wire un3_rx_all_well_2 ;
+wire un17_rxr_wt_tc ;
+wire un3_rx_all_well_1 ;
+wire rx_any_rst ;
+wire rxr_wt_cnt9 ;
+wire un1_rui_rst_dual_c_1_i ;
+wire rlol1_cnt_tc_1 ;
+wire rlol1_cnt_scalar ;
+wire rxr_wt_en ;
+wire rxr_wt_cnte ;
+wire rlols0_cnt_tc_1 ;
+wire un2_rlos_redge_1_i ;
+wire un18_txr_wt_tc ;
+wire tx_any_rst ;
+wire pll_lol_p2 ;
+wire un2_plol_fedge_5_i ;
+wire N_2124_0 ;
+wire waita_rlols06 ;
+wire un1_rlols0_cnt_tc ;
+wire waita_rlols0 ;
+wire waita_rlols0_QN ;
+wire wait_calib_RNO ;
+wire un1_rlos_fedge_1 ;
+wire wait_calib ;
+wire wait_calib_QN ;
+wire rxs_rst6 ;
+wire un1_rxs_cnt_tc ;
+wire rxs_rst_QN ;
+wire rxp_rst2 ;
+wire rxp_rst2_QN ;
+wire rlos_p1 ;
+wire rlos_p2 ;
+wire rlos_p2_QN ;
+wire rlos_p1_QN ;
+wire rlos_db_p1_QN ;
+wire rlos_db_cnt_axb_0 ;
+wire rlos_db_cnt_cry_1_0_S0 ;
+wire rlos_db_cnt_cry_1_0_S1 ;
+wire rlos_db_cnt_s_3_0_S0 ;
+wire un1_rlos_db_cnt_max ;
+wire rlos_db_QN ;
+wire rlols0_cnte ;
+wire rlol_p1 ;
+wire rlol_p2 ;
+wire rlol_p2_QN ;
+wire rlol_p1_QN ;
+wire rlol_db_p1 ;
+wire rlol_db_p1_QN ;
+wire rlol_db_cnt_axb_0 ;
+wire rlol_db_cnt_cry_1_0_S0 ;
+wire rlol_db_cnt_cry_1_0_S1 ;
+wire rlol_db_cnt_s_3_0_S0 ;
+wire un1_rlol_db_cnt_max ;
+wire rlol_db_QN ;
+wire rlol1_cnte ;
+wire rxsdr_appd_2 ;
+wire rxsdr_appd_4 ;
+wire rxsdr_appd_QN ;
+wire un1_dual_or_rserd_rst_2_i ;
+wire rxr_wt_en_QN ;
+wire rxdpr_appd ;
+wire rxdpr_appd_QN ;
+wire ruo_rx_rdyr_QN ;
+wire un2_rdo_serdes_rst_dual_c_2_i ;
+wire plol_fedge ;
+wire un1_plol0_cnt_tc_1_i ;
+wire waita_plol0_QN ;
+wire un1_plol_cnt_tc ;
+wire un2_plol_cnt_tc ;
+wire txs_rst ;
+wire txs_rst_QN ;
+wire N_10_i ;
+wire un9_plol0_cnt_tc ;
+wire un1_plol0_cnt_tc_1 ;
+wire txp_rst ;
+wire txp_rst_QN ;
+wire N_11_i ;
+wire pll_lol_p3 ;
+wire pll_lol_p3_QN ;
+wire pll_lol_p1 ;
+wire pll_lol_p2_QN ;
+wire pll_lol_p1_QN ;
+wire txsr_appd_2 ;
+wire txsr_appd_4 ;
+wire txsr_appd_QN ;
+wire un1_dual_or_serd_rst_1_1 ;
+wire un1_dual_or_serd_rst_1_i ;
+wire txr_wt_en ;
+wire txr_wt_en_QN ;
+wire txr_wt_cnte ;
+wire un2_plol_fedge_2 ;
+wire un2_plol_fedge_3_i ;
+wire txdpr_appd ;
+wire txdpr_appd_QN ;
+wire un2_plol_fedge_5_1 ;
+wire ruo_tx_rdyr_QN ;
+wire un2_plol_fedge_8_i ;
+wire rlos_redge ;
+wire rlols0_cnt11_0 ;
+wire plol_cnt_scalar ;
+wire rlols0_cnt_scalar ;
+wire un8_rxs_cnt_tc ;
+wire un1_txsr_appd ;
+wire un3_rx_all_well_2_1 ;
+wire un1_rxsdr_or_sr_appd ;
+wire un2_rdo_serdes_rst_dual_c_1_1 ;
+wire rlols0_cnt_tc_1_10 ;
+wire rlols0_cnt_tc_1_11 ;
+wire rlols0_cnt_tc_1_12 ;
+wire rlols0_cnt_tc_1_13 ;
+wire un1_plol_cnt_tc_11 ;
+wire un1_plol_cnt_tc_12 ;
+wire un1_plol_cnt_tc_13 ;
+wire un1_plol_cnt_tc_14 ;
+wire rlol1_cnt_tc_1_11 ;
+wire rlol1_cnt_tc_1_12 ;
+wire rlol1_cnt_tc_1_13 ;
+wire rlol1_cnt_tc_1_14 ;
+wire CO0_2 ;
+wire un18_txr_wt_tc_6 ;
+wire un18_txr_wt_tc_7 ;
+wire un18_txr_wt_tc_8 ;
+wire un17_rxr_wt_tc_6 ;
+wire un17_rxr_wt_tc_7 ;
+wire un17_rxr_wt_tc_8 ;
+wire rlols0_cnt_tc_1_9 ;
+wire un1_plol_cnt_tc_10 ;
+wire rlol1_cnt_tc_1_10 ;
+wire txr_wt_cnt_scalar ;
+wire rlos_db_cnt_cry_0 ;
+wire rlos_db_cnt_cry_0_0_S0 ;
+wire rlos_db_cnt_cry_0_0_S1 ;
+wire rlos_db_cnt_cry_2 ;
+wire rlos_db_cnt_s_3_0_COUT ;
+wire rlos_db_cnt_s_3_0_S1 ;
+wire rlol_db_cnt_cry_0 ;
+wire rlol_db_cnt_cry_0_0_S0 ;
+wire rlol_db_cnt_cry_0_0_S1 ;
+wire rlol_db_cnt_cry_2 ;
+wire rlol_db_cnt_s_3_0_COUT ;
+wire rlol_db_cnt_s_3_0_S1 ;
+wire GND ;
+wire N_1 ;
+wire N_2 ;
+wire N_3 ;
+wire N_4 ;
+wire N_5 ;
+wire N_6 ;
+wire N_7 ;
+  LUT4 \genblk2.rxs_cnt_RNO[0]  (
+       .A(rxs_rst),
+       .B(rxs_cnt[0]),
+       .C(rxs_cnt[1]),
+       .D(VCC),
+       .Z(rxs_cnt_3[0])
+);
+defparam \genblk2.rxs_cnt_RNO[0] .init=16'h2626;
+  LUT4 \genblk2.genblk3.lfor[0].rxpr_appd_RNO[0]  (
+       .A(dual_or_rserd_rst),
+       .B(rx_los_low_s),
+       .C(rx_cdr_lol_s),
+       .D(VCC),
+       .Z(rxpr_appd_RNO[0])
+);
+defparam \genblk2.genblk3.lfor[0].rxpr_appd_RNO[0] .init=16'h0101;
+  LUT4 \genblk1.plol0_cnt_RNO[1]  (
+       .A(plol0_cnt[1]),
+       .B(plol0_cnt9),
+       .C(waita_plol0),
+       .D(plol0_cnt[0]),
+       .Z(plol0_cnt_3[1])
+);
+defparam \genblk1.plol0_cnt_RNO[1] .init=16'h1222;
+  LUT4 \genblk2.rxp_rst2_RNO  (
+       .A(dual_or_rserd_rst),
+       .B(rlos_db_p1),
+       .C(rlos_db),
+       .D(VCC),
+       .Z(rxp_rst25)
+);
+defparam \genblk2.rxp_rst2_RNO .init=16'hBABA;
+  LUT4 \genblk2.genblk3.rxdpr_appd_RNO  (
+       .A(dual_or_rserd_rst),
+       .B(rlos_db),
+       .C(rlol_db),
+       .D(VCC),
+       .Z(un1_rui_rst_dual_c_1_1)
+);
+defparam \genblk2.genblk3.rxdpr_appd_RNO .init=16'h0101;
+  LUT4 \genblk2.genblk3.ruo_rx_rdyr_RNO  (
+       .A(rx_all_well),
+       .B(rst_dual_c),
+       .C(rsl_rx_pcs_rst_c),
+       .D(dual_or_rserd_rst),
+       .Z(un3_rx_all_well_2)
+);
+defparam \genblk2.genblk3.ruo_rx_rdyr_RNO .init=16'h0002;
+  LUT4 \genblk2.genblk3.rxr_wt_en_RNO  (
+       .A(un17_rxr_wt_tc),
+       .B(rx_all_well),
+       .C(dual_or_rserd_rst),
+       .D(VCC),
+       .Z(un3_rx_all_well_1)
+);
+defparam \genblk2.genblk3.rxr_wt_en_RNO .init=16'h0404;
+  LUT4 rx_any_rst_RNIFD021 (
+       .A(rx_any_rst),
+       .B(un17_rxr_wt_tc),
+       .C(rlos_db),
+       .D(rlol_db),
+       .Z(rxr_wt_cnt9)
+);
+defparam rx_any_rst_RNIFD021.init=16'hFFFE;
+  LUT4 \genblk2.genblk3.rxdpr_appd_RNO_0  (
+       .A(rst_dual_c),
+       .B(rx_all_well),
+       .C(dual_or_rserd_rst),
+       .D(VCC),
+       .Z(un1_rui_rst_dual_c_1_i)
+);
+defparam \genblk2.genblk3.rxdpr_appd_RNO_0 .init=16'hFBFB;
+  LUT4 \genblk2.rxs_rst_RNIS0OP  (
+       .A(rlol1_cnt_tc_1),
+       .B(rxs_rst),
+       .C(rlos_db_p1),
+       .D(rlos_db),
+       .Z(rlol1_cnt_scalar)
+);
+defparam \genblk2.rxs_rst_RNIS0OP .init=16'h1011;
+  LUT4 \genblk2.genblk3.rxr_wt_en_RNIQF0H1  (
+       .A(rxr_wt_en),
+       .B(rx_any_rst),
+       .C(rx_all_well),
+       .D(un17_rxr_wt_tc),
+       .Z(rxr_wt_cnte)
+);
+defparam \genblk2.genblk3.rxr_wt_en_RNIQF0H1 .init=16'hFFEF;
+  LUT4 \genblk2.rxp_rst2_RNO_0  (
+       .A(rlols0_cnt_tc_1),
+       .B(dual_or_rserd_rst),
+       .C(rlos_db_p1),
+       .D(rlos_db),
+       .Z(un2_rlos_redge_1_i)
+);
+defparam \genblk2.rxp_rst2_RNO_0 .init=16'hEFEE;
+  LUT4 \genblk1.genblk2.ruo_tx_rdyr_RNO  (
+       .A(un18_txr_wt_tc),
+       .B(tx_any_rst),
+       .C(pll_lol_p2),
+       .D(VCC),
+       .Z(un2_plol_fedge_5_i)
+);
+defparam \genblk1.genblk2.ruo_tx_rdyr_RNO .init=16'hFEFE;
+  LUT4 \genblk2.genblk3.lfor[0].rxsr_appd_RNO[0]  (
+       .A(rxsr_appd[0]),
+       .B(rx_serdes_rst_c),
+       .C(rxs_rst),
+       .D(rsl_disable),
+       .Z(N_2124_0)
+);
+defparam \genblk2.genblk3.lfor[0].rxsr_appd_RNO[0] .init=16'hEEFE;
+// @16:759
+  FD1P3DX \genblk2.waita_rlols0  (
+       .D(waita_rlols06),
+       .SP(un1_rlols0_cnt_tc),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(waita_rlols0)
+);
+// @16:656
+  FD1P3BX \genblk2.wait_calib  (
+       .D(wait_calib_RNO),
+       .SP(un1_rlos_fedge_1),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(wait_calib)
+);
+// @16:694
+  FD1P3DX \genblk2.rxs_rst  (
+       .D(rxs_rst6),
+       .SP(un1_rxs_cnt_tc),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxs_rst)
+);
+// @16:694
+  FD1S3DX \genblk2.rxs_cnt[0]  (
+       .D(rxs_cnt_3[0]),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxs_cnt[0])
+);
+// @16:694
+  FD1S3DX \genblk2.rxs_cnt[1]  (
+       .D(rxs_cnt_3[1]),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxs_cnt[1])
+);
+// @16:806
+  FD1P3BX \genblk2.rxp_rst2  (
+       .D(rxp_rst25),
+       .SP(un2_rlos_redge_1_i),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rxp_rst2)
+);
+// @16:567
+  FD1S3DX \genblk2.rlos_p2  (
+       .D(rlos_p1),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlos_p2)
+);
+// @16:567
+  FD1S3DX \genblk2.rlos_p1  (
+       .D(rx_los_low_s),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlos_p1)
+);
+// @16:567
+  FD1S3BX \genblk2.rlos_db_p1  (
+       .D(rlos_db),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlos_db_p1)
+);
+// @16:640
+  FD1S3BX \genblk2.rlos_db_cnt[0]  (
+       .D(rlos_db_cnt_axb_0),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlos_db_cnt[0])
+);
+// @16:640
+  FD1S3BX \genblk2.rlos_db_cnt[1]  (
+       .D(rlos_db_cnt_cry_1_0_S0),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlos_db_cnt[1])
+);
+// @16:640
+  FD1S3BX \genblk2.rlos_db_cnt[2]  (
+       .D(rlos_db_cnt_cry_1_0_S1),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlos_db_cnt[2])
+);
+// @16:640
+  FD1S3BX \genblk2.rlos_db_cnt[3]  (
+       .D(rlos_db_cnt_s_3_0_S0),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlos_db_cnt[3])
+);
+// @16:649
+  FD1P3BX \genblk2.rlos_db  (
+       .D(rlos_db_cnt[1]),
+       .SP(un1_rlos_db_cnt_max),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlos_db)
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[0]  (
+       .D(rlols0_cnt_s[0]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[0])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[1]  (
+       .D(rlols0_cnt_s[1]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[1])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[2]  (
+       .D(rlols0_cnt_s[2]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[2])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[3]  (
+       .D(rlols0_cnt_s[3]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[3])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[4]  (
+       .D(rlols0_cnt_s[4]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[4])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[5]  (
+       .D(rlols0_cnt_s[5]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[5])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[6]  (
+       .D(rlols0_cnt_s[6]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[6])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[7]  (
+       .D(rlols0_cnt_s[7]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[7])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[8]  (
+       .D(rlols0_cnt_s[8]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[8])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[9]  (
+       .D(rlols0_cnt_s[9]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[9])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[10]  (
+       .D(rlols0_cnt_s[10]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[10])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[11]  (
+       .D(rlols0_cnt_s[11]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[11])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[12]  (
+       .D(rlols0_cnt_s[12]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[12])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[13]  (
+       .D(rlols0_cnt_s[13]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[13])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[14]  (
+       .D(rlols0_cnt_s[14]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[14])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[15]  (
+       .D(rlols0_cnt_s[15]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[15])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[16]  (
+       .D(rlols0_cnt_s[16]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[16])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[17]  (
+       .D(rlols0_cnt_s[17]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[17])
+);
+// @16:567
+  FD1S3DX \genblk2.rlol_p2  (
+       .D(rlol_p1),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol_p2)
+);
+// @16:567
+  FD1S3DX \genblk2.rlol_p1  (
+       .D(rx_cdr_lol_s),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol_p1)
+);
+// @16:567
+  FD1S3BX \genblk2.rlol_db_p1  (
+       .D(rlol_db),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlol_db_p1)
+);
+// @16:624
+  FD1S3BX \genblk2.rlol_db_cnt[0]  (
+       .D(rlol_db_cnt_axb_0),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlol_db_cnt[0])
+);
+// @16:624
+  FD1S3BX \genblk2.rlol_db_cnt[1]  (
+       .D(rlol_db_cnt_cry_1_0_S0),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlol_db_cnt[1])
+);
+// @16:624
+  FD1S3BX \genblk2.rlol_db_cnt[2]  (
+       .D(rlol_db_cnt_cry_1_0_S1),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlol_db_cnt[2])
+);
+// @16:624
+  FD1S3BX \genblk2.rlol_db_cnt[3]  (
+       .D(rlol_db_cnt_s_3_0_S0),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlol_db_cnt[3])
+);
+// @16:633
+  FD1P3BX \genblk2.rlol_db  (
+       .D(rlol_db_cnt[1]),
+       .SP(un1_rlol_db_cnt_max),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlol_db)
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[0]  (
+       .D(rlol1_cnt_s[0]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[0])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[1]  (
+       .D(rlol1_cnt_s[1]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[1])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[2]  (
+       .D(rlol1_cnt_s[2]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[2])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[3]  (
+       .D(rlol1_cnt_s[3]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[3])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[4]  (
+       .D(rlol1_cnt_s[4]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[4])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[5]  (
+       .D(rlol1_cnt_s[5]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[5])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[6]  (
+       .D(rlol1_cnt_s[6]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[6])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[7]  (
+       .D(rlol1_cnt_s[7]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[7])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[8]  (
+       .D(rlol1_cnt_s[8]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[8])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[9]  (
+       .D(rlol1_cnt_s[9]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[9])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[10]  (
+       .D(rlol1_cnt_s[10]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[10])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[11]  (
+       .D(rlol1_cnt_s[11]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[11])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[12]  (
+       .D(rlol1_cnt_s[12]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[12])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[13]  (
+       .D(rlol1_cnt_s[13]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[13])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[14]  (
+       .D(rlol1_cnt_s[14]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[14])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[15]  (
+       .D(rlol1_cnt_s[15]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[15])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[16]  (
+       .D(rlol1_cnt_s[16]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[16])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[17]  (
+       .D(rlol1_cnt_s[17]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[17])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[18]  (
+       .D(rlol1_cnt_s[18]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[18])
+);
+// @16:865
+  FD1S3BX \genblk2.genblk3.rxsdr_appd  (
+       .D(rxsdr_appd_2),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rxsdr_appd_4)
+);
+// @16:900
+  FD1P3DX \genblk2.genblk3.rxr_wt_en  (
+       .D(un3_rx_all_well_1),
+       .SP(un1_dual_or_rserd_rst_2_i),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_en)
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[0]  (
+       .D(rxr_wt_cnt_s[0]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[0])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[1]  (
+       .D(rxr_wt_cnt_s[1]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[1])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[2]  (
+       .D(rxr_wt_cnt_s[2]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[2])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[3]  (
+       .D(rxr_wt_cnt_s[3]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[3])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[4]  (
+       .D(rxr_wt_cnt_s[4]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[4])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[5]  (
+       .D(rxr_wt_cnt_s[5]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[5])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[6]  (
+       .D(rxr_wt_cnt_s[6]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[6])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[7]  (
+       .D(rxr_wt_cnt_s[7]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[7])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[8]  (
+       .D(rxr_wt_cnt_s[8]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[8])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[9]  (
+       .D(rxr_wt_cnt_s[9]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[9])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[10]  (
+       .D(rxr_wt_cnt_s[10]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[10])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[11]  (
+       .D(rxr_wt_cnt_s[11]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[11])
+);
+// @16:871
+  FD1P3DX \genblk2.genblk3.rxdpr_appd  (
+       .D(un1_rui_rst_dual_c_1_1),
+       .SP(un1_rui_rst_dual_c_1_i),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxdpr_appd)
+);
+// @16:920
+  FD1P3DX \genblk2.genblk3.ruo_rx_rdyr  (
+       .D(un3_rx_all_well_2),
+       .SP(rxr_wt_cnt9),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rsl_rx_rdy)
+);
+// @16:882
+  FD1S3DX \genblk2.genblk3.lfor[0].rxsr_appd[0]  (
+       .D(N_2124_0),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxsr_appd[0])
+);
+// @16:888
+  FD1P3DX \genblk2.genblk3.lfor[0].rxpr_appd[0]  (
+       .D(rxpr_appd_RNO[0]),
+       .SP(un2_rdo_serdes_rst_dual_c_2_i),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxpr_appd[0])
+);
+// @16:443
+  FD1P3DX \genblk1.waita_plol0  (
+       .D(plol_fedge),
+       .SP(un1_plol0_cnt_tc_1_i),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(waita_plol0)
+);
+// @16:422
+  FD1P3DX \genblk1.txs_rst  (
+       .D(un1_plol_cnt_tc),
+       .SP(un2_plol_cnt_tc),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txs_rst)
+);
+// @16:422
+  FD1S3DX \genblk1.txs_cnt[0]  (
+       .D(N_10_i),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txs_cnt[0])
+);
+// @16:422
+  FD1S3DX \genblk1.txs_cnt[1]  (
+       .D(txs_cnt_RNO[1]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txs_cnt[1])
+);
+// @16:461
+  FD1P3DX \genblk1.txp_rst  (
+       .D(un9_plol0_cnt_tc),
+       .SP(un1_plol0_cnt_tc_1),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txp_rst)
+);
+// @16:461
+  FD1S3DX \genblk1.txp_cnt[0]  (
+       .D(N_11_i),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txp_cnt[0])
+);
+// @16:461
+  FD1S3DX \genblk1.txp_cnt[1]  (
+       .D(txp_cnt_RNO[1]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txp_cnt[1])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[0]  (
+       .D(plol_cnt_s[0]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[0])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[1]  (
+       .D(plol_cnt_s[1]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[1])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[2]  (
+       .D(plol_cnt_s[2]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[2])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[3]  (
+       .D(plol_cnt_s[3]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[3])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[4]  (
+       .D(plol_cnt_s[4]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[4])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[5]  (
+       .D(plol_cnt_s[5]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[5])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[6]  (
+       .D(plol_cnt_s[6]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[6])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[7]  (
+       .D(plol_cnt_s[7]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[7])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[8]  (
+       .D(plol_cnt_s[8]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[8])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[9]  (
+       .D(plol_cnt_s[9]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[9])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[10]  (
+       .D(plol_cnt_s[10]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[10])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[11]  (
+       .D(plol_cnt_s[11]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[11])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[12]  (
+       .D(plol_cnt_s[12]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[12])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[13]  (
+       .D(plol_cnt_s[13]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[13])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[14]  (
+       .D(plol_cnt_s[14]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[14])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[15]  (
+       .D(plol_cnt_s[15]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[15])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[16]  (
+       .D(plol_cnt_s[16]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[16])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[17]  (
+       .D(plol_cnt_s[17]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[17])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[18]  (
+       .D(plol_cnt_s[18]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[18])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[19]  (
+       .D(plol_cnt_s[19]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[19])
+);
+// @16:451
+  FD1S3DX \genblk1.plol0_cnt[0]  (
+       .D(plol0_cnt_3[0]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol0_cnt[0])
+);
+// @16:451
+  FD1S3DX \genblk1.plol0_cnt[1]  (
+       .D(plol0_cnt_3[1]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol0_cnt[1])
+);
+// @16:451
+  FD1S3DX \genblk1.plol0_cnt[2]  (
+       .D(plol0_cnt_3[2]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol0_cnt[2])
+);
+// @16:398
+  FD1S3DX \genblk1.pll_lol_p3  (
+       .D(pll_lol_p2),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(pll_lol_p3)
+);
+// @16:398
+  FD1S3DX \genblk1.pll_lol_p2  (
+       .D(pll_lol_p1),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(pll_lol_p2)
+);
+// @16:398
+  FD1S3DX \genblk1.pll_lol_p1  (
+       .D(pll_lock_i),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(pll_lol_p1)
+);
+// @16:492
+  FD1S3BX \genblk1.genblk2.txsr_appd  (
+       .D(txsr_appd_2),
+       .CK(pll_refclki),
+       .PD(rsl_rst),
+       .Q(txsr_appd_4)
+);
+// @16:519
+  FD1P3DX \genblk1.genblk2.txr_wt_en  (
+       .D(un1_dual_or_serd_rst_1_1),
+       .SP(un1_dual_or_serd_rst_1_i),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_en)
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[0]  (
+       .D(txr_wt_cnt_s[0]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[0])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[1]  (
+       .D(txr_wt_cnt_s[1]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[1])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[2]  (
+       .D(txr_wt_cnt_s[2]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[2])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[3]  (
+       .D(txr_wt_cnt_s[3]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[3])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[4]  (
+       .D(txr_wt_cnt_s[4]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[4])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[5]  (
+       .D(txr_wt_cnt_s[5]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[5])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[6]  (
+       .D(txr_wt_cnt_s[6]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[6])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[7]  (
+       .D(txr_wt_cnt_s[7]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[7])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[8]  (
+       .D(txr_wt_cnt_s[8]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[8])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[9]  (
+       .D(txr_wt_cnt_s[9]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[9])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[10]  (
+       .D(txr_wt_cnt_s[10]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[10])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[11]  (
+       .D(txr_wt_cnt_s[11]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[11])
+);
+// @16:498
+  FD1P3DX \genblk1.genblk2.txdpr_appd  (
+       .D(un2_plol_fedge_2),
+       .SP(un2_plol_fedge_3_i),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txdpr_appd)
+);
+// @16:537
+  FD1P3DX \genblk1.genblk2.ruo_tx_rdyr  (
+       .D(un2_plol_fedge_5_1),
+       .SP(un2_plol_fedge_5_i),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(rsl_tx_rdy)
+);
+// @16:509
+  FD1P3DX \genblk1.genblk2.mfor[0].txpr_appd[0]  (
+       .D(un2_plol_fedge_2),
+       .SP(un2_plol_fedge_8_i),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txpr_appd[0])
+);
+// @16:422
+  LUT4 \genblk1.txs_cnt_RNO[0]  (
+       .A(txs_cnt[0]),
+       .B(txs_rst),
+       .C(un1_plol_cnt_tc),
+       .D(VCC),
+       .Z(N_10_i)
+);
+defparam \genblk1.txs_cnt_RNO[0] .init=16'hA6A6;
+// @16:434
+  LUT4 \genblk1.txs_cnt_RNO[1]  (
+       .A(txs_cnt[0]),
+       .B(txs_cnt[1]),
+       .C(txs_rst),
+       .D(un1_plol_cnt_tc),
+       .Z(txs_cnt_RNO[1])
+);
+defparam \genblk1.txs_cnt_RNO[1] .init=16'hCC6C;
+// @16:519
+  LUT4 \genblk1.genblk2.txr_wt_en_RNO  (
+       .A(txpr_appd[0]),
+       .B(pll_lol_p2),
+       .C(un1_dual_or_serd_rst_1_1),
+       .D(rsl_tx_rdy),
+       .Z(un1_dual_or_serd_rst_1_i)
+);
+defparam \genblk1.genblk2.txr_wt_en_RNO .init=16'h0F2F;
+// @16:317
+  LUT4 \genblk2.rxs_rst6  (
+       .A(rlol_db),
+       .B(rlos_db),
+       .C(rlol1_cnt_tc_1),
+       .D(VCC),
+       .Z(rxs_rst6)
+);
+defparam \genblk2.rxs_rst6 .init=16'h2020;
+// @8:394
+  LUT4 \genblk2.wait_calib_RNIKRP81  (
+       .A(rxs_rst),
+       .B(wait_calib),
+       .C(rlol1_cnt_tc_1),
+       .D(rlos_redge),
+       .Z(rlol1_cnte)
+);
+defparam \genblk2.wait_calib_RNIKRP81 .init=16'hFFFE;
+// @8:394
+  LUT4 \genblk2.waita_rlols0_RNI266C  (
+       .A(rlols0_cnt11_0),
+       .B(waita_rlols0),
+       .C(rlols0_cnt_tc_1),
+       .D(VCC),
+       .Z(rlols0_cnte)
+);
+defparam \genblk2.waita_rlols0_RNI266C .init=16'hFEFE;
+// @16:412
+  LUT4 \genblk1.plol_cnt11_i  (
+       .A(pll_lol_p2),
+       .B(un1_plol_cnt_tc),
+       .C(rsl_tx_serdes_rst_c),
+       .D(VCC),
+       .Z(plol_cnt_scalar)
+);
+defparam \genblk1.plol_cnt11_i .init=16'h0202;
+// @16:778
+  LUT4 \genblk2.rlols0_cnt11_i  (
+       .A(rlols0_cnt11_0),
+       .B(rlols0_cnt_tc_1),
+       .C(VCC),
+       .D(VCC),
+       .Z(rlols0_cnt_scalar)
+);
+defparam \genblk2.rlols0_cnt11_i .init=16'h1111;
+// @16:317
+  LUT4 \genblk2.un1_rxs_cnt_tc  (
+       .A(rlol_db),
+       .B(rlos_db),
+       .C(un8_rxs_cnt_tc),
+       .D(rlol1_cnt_tc_1),
+       .Z(un1_rxs_cnt_tc)
+);
+defparam \genblk2.un1_rxs_cnt_tc .init=16'hFEFC;
+// @8:394
+  LUT4 \genblk2.wait_calib_RNO  (
+       .A(rlol_db),
+       .B(rlos_db),
+       .C(rlol1_cnt_tc_1),
+       .D(VCC),
+       .Z(wait_calib_RNO)
+);
+defparam \genblk2.wait_calib_RNO .init=16'hA3A3;
+// @16:509
+  LUT4 \genblk1.genblk2.mfor[0].txpr_appd_RNO[0]  (
+       .A(un1_txsr_appd),
+       .B(pll_lol_p2),
+       .C(rsl_serdes_rst_dual_c),
+       .D(rsl_tx_serdes_rst_c),
+       .Z(un2_plol_fedge_8_i)
+);
+defparam \genblk1.genblk2.mfor[0].txpr_appd_RNO[0] .init=16'hFFFE;
+// @16:900
+  LUT4 \genblk2.genblk3.rxr_wt_en_RNO_0  (
+       .A(dual_or_rserd_rst),
+       .B(un3_rx_all_well_2_1),
+       .C(un17_rxr_wt_tc),
+       .D(rx_all_well),
+       .Z(un1_dual_or_rserd_rst_2_i)
+);
+defparam \genblk2.genblk3.rxr_wt_en_RNO_0 .init=16'hFEFF;
+// @16:888
+  LUT4 \genblk2.genblk3.lfor[0].rxpr_appd_RNO_0[0]  (
+       .A(un1_rxsdr_or_sr_appd),
+       .B(un2_rdo_serdes_rst_dual_c_1_1),
+       .C(rsl_rx_serdes_rst_c),
+       .D(rsl_serdes_rst_dual_c),
+       .Z(un2_rdo_serdes_rst_dual_c_2_i)
+);
+defparam \genblk2.genblk3.lfor[0].rxpr_appd_RNO_0[0] .init=16'hFFFB;
+// @16:259
+  LUT4 \genblk1.un2_plol_cnt_tc  (
+       .A(txs_cnt[0]),
+       .B(txs_cnt[1]),
+       .C(un1_plol_cnt_tc),
+       .D(VCC),
+       .Z(un2_plol_cnt_tc)
+);
+defparam \genblk1.un2_plol_cnt_tc .init=16'hF8F8;
+// @8:394
+  LUT4 \genblk1.genblk2.txr_wt_en_RNICEBT  (
+       .A(txr_wt_en),
+       .B(un18_txr_wt_tc),
+       .C(tx_any_rst),
+       .D(VCC),
+       .Z(txr_wt_cnte)
+);
+defparam \genblk1.genblk2.txr_wt_en_RNICEBT .init=16'hFEFE;
+// @16:322
+  LUT4 \genblk2.un1_rlos_fedge_1  (
+       .A(rlos_db),
+       .B(rlos_db_p1),
+       .C(rlol1_cnt_tc_1),
+       .D(VCC),
+       .Z(un1_rlos_fedge_1)
+);
+defparam \genblk2.un1_rlos_fedge_1 .init=16'hF6F6;
+// @16:340
+  LUT4 \genblk2.un1_rlols0_cnt_tc  (
+       .A(rlols0_cnt11_0),
+       .B(waita_rlols06),
+       .C(rlols0_cnt_tc_1),
+       .D(VCC),
+       .Z(un1_rlols0_cnt_tc)
+);
+defparam \genblk2.un1_rlols0_cnt_tc .init=16'hFEFE;
+// @16:498
+  LUT4 \genblk1.genblk2.txdpr_appd_RNO  (
+       .A(pll_lol_p2),
+       .B(rsl_serdes_rst_dual_c),
+       .C(rsl_tx_serdes_rst_c),
+       .D(rst_dual_c),
+       .Z(un2_plol_fedge_3_i)
+);
+defparam \genblk1.genblk2.txdpr_appd_RNO .init=16'hFFFE;
+// @16:461
+  LUT4 \genblk1.txp_cnt_RNO[0]  (
+       .A(txp_cnt[0]),
+       .B(txp_rst),
+       .C(un9_plol0_cnt_tc),
+       .D(VCC),
+       .Z(N_11_i)
+);
+defparam \genblk1.txp_cnt_RNO[0] .init=16'hA6A6;
+// @16:282
+  LUT4 un2_plol_fedge_5_1_cZ (
+       .A(pll_lol_p2),
+       .B(tx_any_rst),
+       .C(VCC),
+       .D(VCC),
+       .Z(un2_plol_fedge_5_1)
+);
+defparam un2_plol_fedge_5_1_cZ.init=16'h1111;
+// @16:522
+  LUT4 un1_dual_or_serd_rst_1_1_cZ (
+       .A(un18_txr_wt_tc),
+       .B(rsl_serdes_rst_dual_c),
+       .C(rsl_tx_serdes_rst_c),
+       .D(VCC),
+       .Z(un1_dual_or_serd_rst_1_1)
+);
+defparam un1_dual_or_serd_rst_1_1_cZ.init=16'h0101;
+// @16:473
+  LUT4 \genblk1.txp_cnt_RNO[1]  (
+       .A(txp_cnt[0]),
+       .B(txp_cnt[1]),
+       .C(txp_rst),
+       .D(un9_plol0_cnt_tc),
+       .Z(txp_cnt_RNO[1])
+);
+defparam \genblk1.txp_cnt_RNO[1] .init=16'hCC6C;
+// @16:388
+  LUT4 rlols0_cnt_tc_1_cZ (
+       .A(rlols0_cnt_tc_1_10),
+       .B(rlols0_cnt_tc_1_11),
+       .C(rlols0_cnt_tc_1_12),
+       .D(rlols0_cnt_tc_1_13),
+       .Z(rlols0_cnt_tc_1)
+);
+defparam rlols0_cnt_tc_1_cZ.init=16'h8000;
+// @16:386
+  LUT4 \genblk1.un1_plol_cnt_tc  (
+       .A(un1_plol_cnt_tc_11),
+       .B(un1_plol_cnt_tc_12),
+       .C(un1_plol_cnt_tc_13),
+       .D(un1_plol_cnt_tc_14),
+       .Z(un1_plol_cnt_tc)
+);
+defparam \genblk1.un1_plol_cnt_tc .init=16'h8000;
+// @16:387
+  LUT4 rlol1_cnt_tc_1_cZ (
+       .A(rlol1_cnt_tc_1_11),
+       .B(rlol1_cnt_tc_1_12),
+       .C(rlol1_cnt_tc_1_13),
+       .D(rlol1_cnt_tc_1_14),
+       .Z(rlol1_cnt_tc_1)
+);
+defparam rlol1_cnt_tc_1_cZ.init=16'h8000;
+// @16:625
+  LUT4 \un1_genblk2.rlol_db_cnt_axb_0  (
+       .A(rlol_db_cnt[0]),
+       .B(un1_rlol_db_cnt_zero[0]),
+       .C(VCC),
+       .D(VCC),
+       .Z(rlol_db_cnt_axb_0)
+);
+defparam \un1_genblk2.rlol_db_cnt_axb_0 .init=16'h9999;
+// @16:641
+  LUT4 \un1_genblk2.rlos_db_cnt_axb_0  (
+       .A(rlos_db_cnt[0]),
+       .B(un1_rlos_db_cnt_zero[0]),
+       .C(VCC),
+       .D(VCC),
+       .Z(rlos_db_cnt_axb_0)
+);
+defparam \un1_genblk2.rlos_db_cnt_axb_0 .init=16'h9999;
+// @16:443
+  LUT4 \genblk1.waita_plol0_RNO  (
+       .A(pll_lol_p2),
+       .B(pll_lol_p3),
+       .C(un9_plol0_cnt_tc),
+       .D(VCC),
+       .Z(un1_plol0_cnt_tc_1_i)
+);
+defparam \genblk1.waita_plol0_RNO .init=16'hF6F6;
+// @16:514
+  LUT4 \genblk1.genblk2.mfor[0].un1_txsr_appd  (
+       .A(txdpr_appd),
+       .B(txsr_appd_4),
+       .C(rsl_tx_pcs_rst_c),
+       .D(VCC),
+       .Z(un1_txsr_appd)
+);
+defparam \genblk1.genblk2.mfor[0].un1_txsr_appd .init=16'hC8C8;
+// @16:493
+  LUT4 \genblk1.genblk2.txsr_appd_2  (
+       .A(txsr_appd_4),
+       .B(rsl_serdes_rst_dual_c),
+       .C(rsl_tx_serdes_rst_c),
+       .D(VCC),
+       .Z(txsr_appd_2)
+);
+defparam \genblk1.genblk2.txsr_appd_2 .init=16'hFEFE;
+// @16:452
+  LUT4 \genblk1.plol0_cnt_3[0]  (
+       .A(plol0_cnt9),
+       .B(plol0_cnt[0]),
+       .C(waita_plol0),
+       .D(VCC),
+       .Z(plol0_cnt_3[0])
+);
+defparam \genblk1.plol0_cnt_3[0] .init=16'h1414;
+// @16:452
+  LUT4 \genblk1.plol0_cnt_3[2]  (
+       .A(CO0_2),
+       .B(plol0_cnt9),
+       .C(plol0_cnt[1]),
+       .D(plol0_cnt[2]),
+       .Z(plol0_cnt_3[2])
+);
+defparam \genblk1.plol0_cnt_3[2] .init=16'h1320;
+// @16:535
+  LUT4 \genblk1.genblk2.un18_txr_wt_tc  (
+       .A(un18_txr_wt_tc_6),
+       .B(un18_txr_wt_tc_7),
+       .C(un18_txr_wt_tc_8),
+       .D(VCC),
+       .Z(un18_txr_wt_tc)
+);
+defparam \genblk1.genblk2.un18_txr_wt_tc .init=16'h8080;
+// @16:211
+  LUT4 un2_plol_fedge_2_cZ (
+       .A(pll_lol_p2),
+       .B(rsl_serdes_rst_dual_c),
+       .C(rsl_tx_serdes_rst_c),
+       .D(VCC),
+       .Z(un2_plol_fedge_2)
+);
+defparam un2_plol_fedge_2_cZ.init=16'h0101;
+// @16:490
+  LUT4 tx_any_rst_cZ (
+       .A(rsl_serdes_rst_dual_c),
+       .B(rsl_tx_pcs_rst_c),
+       .C(rsl_tx_serdes_rst_c),
+       .D(rst_dual_c),
+       .Z(tx_any_rst)
+);
+defparam tx_any_rst_cZ.init=16'hFFFE;
+// @16:863
+  LUT4 rx_any_rst_cZ (
+       .A(dual_or_rserd_rst),
+       .B(rsl_rx_pcs_rst_c),
+       .C(rst_dual_c),
+       .D(VCC),
+       .Z(rx_any_rst)
+);
+defparam rx_any_rst_cZ.init=16'hFEFE;
+// @16:535
+  LUT4 \genblk2.genblk3.un17_rxr_wt_tc  (
+       .A(un17_rxr_wt_tc_6),
+       .B(un17_rxr_wt_tc_7),
+       .C(un17_rxr_wt_tc_8),
+       .D(VCC),
+       .Z(un17_rxr_wt_tc)
+);
+defparam \genblk2.genblk3.un17_rxr_wt_tc .init=16'h8080;
+// @16:219
+  LUT4 \un1_rlol_db_cnt_zero_bm_cZ[0]  (
+       .A(rlol_db_cnt[0]),
+       .B(rlol_db_cnt[1]),
+       .C(rlol_db_cnt[2]),
+       .D(rlol_db_cnt[3]),
+       .Z(un1_rlol_db_cnt_zero_bm[0])
+);
+defparam \un1_rlol_db_cnt_zero_bm_cZ[0] .init=16'h8000;
+// @16:219
+  PFUMX \un1_rlol_db_cnt_zero_cZ[0]  (
+       .ALUT(un1_rlol_db_cnt_zero_bm[0]),
+       .BLUT(un1_rlol_db_cnt_zero_am[0]),
+       .C0(rlol_p2),
+       .Z(un1_rlol_db_cnt_zero[0])
+);
+// @16:219
+  LUT4 \un1_rlos_db_cnt_zero_bm_cZ[0]  (
+       .A(rlos_db_cnt[0]),
+       .B(rlos_db_cnt[1]),
+       .C(rlos_db_cnt[2]),
+       .D(rlos_db_cnt[3]),
+       .Z(un1_rlos_db_cnt_zero_bm[0])
+);
+defparam \un1_rlos_db_cnt_zero_bm_cZ[0] .init=16'h8000;
+// @16:219
+  PFUMX \un1_rlos_db_cnt_zero_cZ[0]  (
+       .ALUT(un1_rlos_db_cnt_zero_bm[0]),
+       .BLUT(un1_rlos_db_cnt_zero_am[0]),
+       .C0(rlos_p2),
+       .Z(un1_rlos_db_cnt_zero[0])
+);
+// @16:309
+  LUT4 \genblk2.un1_rlol_db_cnt_max  (
+       .A(rlol_db_cnt[0]),
+       .B(rlol_db_cnt[1]),
+       .C(rlol_db_cnt[2]),
+       .D(rlol_db_cnt[3]),
+       .Z(un1_rlol_db_cnt_max)
+);
+defparam \genblk2.un1_rlol_db_cnt_max .init=16'h8001;
+// @16:315
+  LUT4 \genblk2.un1_rlos_db_cnt_max  (
+       .A(rlos_db_cnt[0]),
+       .B(rlos_db_cnt[1]),
+       .C(rlos_db_cnt[2]),
+       .D(rlos_db_cnt[3]),
+       .Z(un1_rlos_db_cnt_max)
+);
+defparam \genblk2.un1_rlos_db_cnt_max .init=16'h8001;
+// @16:269
+  LUT4 \genblk1.un1_plol0_cnt_tc_1  (
+       .A(txp_cnt[0]),
+       .B(txp_cnt[1]),
+       .C(un9_plol0_cnt_tc),
+       .D(VCC),
+       .Z(un1_plol0_cnt_tc_1)
+);
+defparam \genblk1.un1_plol0_cnt_tc_1 .init=16'hF8F8;
+// @16:764
+  LUT4 \genblk2.waita_rlols06  (
+       .A(rlol_db),
+       .B(rlol_db_p1),
+       .C(rlos_db),
+       .D(rlos_db_p1),
+       .Z(waita_rlols06)
+);
+defparam \genblk2.waita_rlols06 .init=16'h0504;
+// @16:708
+  LUT4 \rxs_cnt_3_cZ[1]  (
+       .A(rxs_cnt[0]),
+       .B(rxs_cnt[1]),
+       .C(rxs_rst),
+       .D(VCC),
+       .Z(rxs_cnt_3[1])
+);
+defparam \rxs_cnt_3_cZ[1] .init=16'h6464;
+// @16:893
+  LUT4 \genblk2.genblk3.lfor[0].un1_rxsdr_or_sr_appd  (
+       .A(rxsr_appd[0]),
+       .B(rx_all_well),
+       .C(rxsdr_appd_4),
+       .D(rsl_rx_pcs_rst_c),
+       .Z(un1_rxsdr_or_sr_appd)
+);
+defparam \genblk2.genblk3.lfor[0].un1_rxsdr_or_sr_appd .init=16'h3200;
+// @16:388
+  LUT4 rlols0_cnt_tc_1_13_cZ (
+       .A(rlols0_cnt[16]),
+       .B(rlols0_cnt[17]),
+       .C(rlols0_cnt_tc_1_9),
+       .D(VCC),
+       .Z(rlols0_cnt_tc_1_13)
+);
+defparam rlols0_cnt_tc_1_13_cZ.init=16'h1010;
+// @16:386
+  LUT4 \genblk1.un1_plol_cnt_tc_14  (
+       .A(plol_cnt[4]),
+       .B(plol_cnt[5]),
+       .C(plol_cnt[18]),
+       .D(un1_plol_cnt_tc_10),
+       .Z(un1_plol_cnt_tc_14)
+);
+defparam \genblk1.un1_plol_cnt_tc_14 .init=16'h0100;
+// @16:387
+  LUT4 rlol1_cnt_tc_1_14_cZ (
+       .A(rlol1_cnt[11]),
+       .B(rlol1_cnt[12]),
+       .C(rlol1_cnt[18]),
+       .D(rlol1_cnt_tc_1_10),
+       .Z(rlol1_cnt_tc_1_14)
+);
+defparam rlol1_cnt_tc_1_14_cZ.init=16'h0100;
+// @16:906
+  LUT4 \genblk2.genblk3.un3_rx_all_well_2_1  (
+       .A(rxpr_appd[0]),
+       .B(rxdpr_appd),
+       .C(rsl_rx_rdy),
+       .D(VCC),
+       .Z(un3_rx_all_well_2_1)
+);
+defparam \genblk2.genblk3.un3_rx_all_well_2_1 .init=16'h0E0E;
+// @16:375
+  LUT4 rdo_serdes_rst_dual_c (
+       .A(rsl_disable),
+       .B(rsl_rst),
+       .C(serdes_rst_dual_c),
+       .D(VCC),
+       .Z(rsl_serdes_rst_dual_c)
+);
+defparam rdo_serdes_rst_dual_c.init=16'hF4F4;
+// @16:438
+  LUT4 rdo_tx_serdes_rst_c (
+       .A(rsl_disable),
+       .B(txs_rst),
+       .C(tx_serdes_rst_c),
+       .D(VCC),
+       .Z(rsl_tx_serdes_rst_c)
+);
+defparam rdo_tx_serdes_rst_c.init=16'hF4F4;
+// @16:479
+  LUT4 \rdo_tx_pcs_rst_c_1[0]  (
+       .A(rsl_disable),
+       .B(txp_rst),
+       .C(tx_pcs_rst_c),
+       .D(VCC),
+       .Z(rsl_tx_pcs_rst_c)
+);
+defparam \rdo_tx_pcs_rst_c_1[0] .init=16'hF4F4;
+// @16:743
+  LUT4 \rdo_rx_serdes_rst_c_1[0]  (
+       .A(rsl_disable),
+       .B(rxs_rst),
+       .C(rx_serdes_rst_c),
+       .D(VCC),
+       .Z(rsl_rx_serdes_rst_c)
+);
+defparam \rdo_rx_serdes_rst_c_1[0] .init=16'hF4F4;
+// @16:852
+  LUT4 \rdo_rx_pcs_rst_c_1[0]  (
+       .A(rsl_disable),
+       .B(rxp_rst2),
+       .C(rx_pcs_rst_c),
+       .D(VCC),
+       .Z(rsl_rx_pcs_rst_c)
+);
+defparam \rdo_rx_pcs_rst_c_1[0] .init=16'hF4F4;
+// @16:459
+  LUT4 \genblk1.un9_plol0_cnt_tc  (
+       .A(plol0_cnt[0]),
+       .B(plol0_cnt[1]),
+       .C(plol0_cnt[2]),
+       .D(VCC),
+       .Z(un9_plol0_cnt_tc)
+);
+defparam \genblk1.un9_plol0_cnt_tc .init=16'h1010;
+// @16:535
+  LUT4 \genblk2.genblk3.un17_rxr_wt_tc_6  (
+       .A(rxr_wt_cnt[0]),
+       .B(rxr_wt_cnt[8]),
+       .C(rxr_wt_cnt[9]),
+       .D(rxr_wt_cnt[11]),
+       .Z(un17_rxr_wt_tc_6)
+);
+defparam \genblk2.genblk3.un17_rxr_wt_tc_6 .init=16'h4000;
+// @16:535
+  LUT4 \genblk2.genblk3.un17_rxr_wt_tc_7  (
+       .A(rxr_wt_cnt[3]),
+       .B(rxr_wt_cnt[4]),
+       .C(rxr_wt_cnt[5]),
+       .D(rxr_wt_cnt[7]),
+       .Z(un17_rxr_wt_tc_7)
+);
+defparam \genblk2.genblk3.un17_rxr_wt_tc_7 .init=16'h8000;
+// @16:535
+  LUT4 \genblk2.genblk3.un17_rxr_wt_tc_8  (
+       .A(rxr_wt_cnt[1]),
+       .B(rxr_wt_cnt[2]),
+       .C(rxr_wt_cnt[6]),
+       .D(rxr_wt_cnt[10]),
+       .Z(un17_rxr_wt_tc_8)
+);
+defparam \genblk2.genblk3.un17_rxr_wt_tc_8 .init=16'h0001;
+// @16:535
+  LUT4 \genblk1.genblk2.un18_txr_wt_tc_6  (
+       .A(txr_wt_cnt[0]),
+       .B(txr_wt_cnt[8]),
+       .C(txr_wt_cnt[9]),
+       .D(txr_wt_cnt[11]),
+       .Z(un18_txr_wt_tc_6)
+);
+defparam \genblk1.genblk2.un18_txr_wt_tc_6 .init=16'h4000;
+// @16:535
+  LUT4 \genblk1.genblk2.un18_txr_wt_tc_7  (
+       .A(txr_wt_cnt[3]),
+       .B(txr_wt_cnt[4]),
+       .C(txr_wt_cnt[5]),
+       .D(txr_wt_cnt[7]),
+       .Z(un18_txr_wt_tc_7)
+);
+defparam \genblk1.genblk2.un18_txr_wt_tc_7 .init=16'h8000;
+// @16:535
+  LUT4 \genblk1.genblk2.un18_txr_wt_tc_8  (
+       .A(txr_wt_cnt[1]),
+       .B(txr_wt_cnt[2]),
+       .C(txr_wt_cnt[6]),
+       .D(txr_wt_cnt[10]),
+       .Z(un18_txr_wt_tc_8)
+);
+defparam \genblk1.genblk2.un18_txr_wt_tc_8 .init=16'h0001;
+// @16:388
+  LUT4 rlols0_cnt_tc_1_9_cZ (
+       .A(rlols0_cnt[1]),
+       .B(rlols0_cnt[2]),
+       .C(rlols0_cnt[3]),
+       .D(rlols0_cnt[4]),
+       .Z(rlols0_cnt_tc_1_9)
+);
+defparam rlols0_cnt_tc_1_9_cZ.init=16'h0001;
+// @16:388
+  LUT4 rlols0_cnt_tc_1_10_cZ (
+       .A(rlols0_cnt[0]),
+       .B(rlols0_cnt[10]),
+       .C(rlols0_cnt[14]),
+       .D(rlols0_cnt[15]),
+       .Z(rlols0_cnt_tc_1_10)
+);
+defparam rlols0_cnt_tc_1_10_cZ.init=16'h4000;
+// @16:388
+  LUT4 rlols0_cnt_tc_1_11_cZ (
+       .A(rlols0_cnt[9]),
+       .B(rlols0_cnt[11]),
+       .C(rlols0_cnt[12]),
+       .D(rlols0_cnt[13]),
+       .Z(rlols0_cnt_tc_1_11)
+);
+defparam rlols0_cnt_tc_1_11_cZ.init=16'h0001;
+// @16:388
+  LUT4 rlols0_cnt_tc_1_12_cZ (
+       .A(rlols0_cnt[5]),
+       .B(rlols0_cnt[6]),
+       .C(rlols0_cnt[7]),
+       .D(rlols0_cnt[8]),
+       .Z(rlols0_cnt_tc_1_12)
+);
+defparam rlols0_cnt_tc_1_12_cZ.init=16'h0001;
+// @16:386
+  LUT4 \genblk1.un1_plol_cnt_tc_10  (
+       .A(plol_cnt[2]),
+       .B(plol_cnt[3]),
+       .C(plol_cnt[17]),
+       .D(plol_cnt[19]),
+       .Z(un1_plol_cnt_tc_10)
+);
+defparam \genblk1.un1_plol_cnt_tc_10 .init=16'h1000;
+// @16:386
+  LUT4 \genblk1.un1_plol_cnt_tc_11  (
+       .A(plol_cnt[13]),
+       .B(plol_cnt[14]),
+       .C(plol_cnt[15]),
+       .D(plol_cnt[16]),
+       .Z(un1_plol_cnt_tc_11)
+);
+defparam \genblk1.un1_plol_cnt_tc_11 .init=16'h8000;
+// @16:386
+  LUT4 \genblk1.un1_plol_cnt_tc_12  (
+       .A(plol_cnt[7]),
+       .B(plol_cnt[8]),
+       .C(plol_cnt[9]),
+       .D(plol_cnt[11]),
+       .Z(un1_plol_cnt_tc_12)
+);
+defparam \genblk1.un1_plol_cnt_tc_12 .init=16'h8000;
+// @16:386
+  LUT4 \genblk1.un1_plol_cnt_tc_13  (
+       .A(plol_cnt[1]),
+       .B(plol_cnt[6]),
+       .C(plol_cnt[10]),
+       .D(plol_cnt[12]),
+       .Z(un1_plol_cnt_tc_13)
+);
+defparam \genblk1.un1_plol_cnt_tc_13 .init=16'h0008;
+// @16:387
+  LUT4 rlol1_cnt_tc_1_10_cZ (
+       .A(rlol1_cnt[7]),
+       .B(rlol1_cnt[8]),
+       .C(rlol1_cnt[9]),
+       .D(rlol1_cnt[10]),
+       .Z(rlol1_cnt_tc_1_10)
+);
+defparam rlol1_cnt_tc_1_10_cZ.init=16'h0001;
+// @16:387
+  LUT4 rlol1_cnt_tc_1_11_cZ (
+       .A(rlol1_cnt[3]),
+       .B(rlol1_cnt[4]),
+       .C(rlol1_cnt[5]),
+       .D(rlol1_cnt[6]),
+       .Z(rlol1_cnt_tc_1_11)
+);
+defparam rlol1_cnt_tc_1_11_cZ.init=16'h0001;
+// @16:387
+  LUT4 rlol1_cnt_tc_1_12_cZ (
+       .A(rlol1_cnt[0]),
+       .B(rlol1_cnt[1]),
+       .C(rlol1_cnt[2]),
+       .D(rlol1_cnt[17]),
+       .Z(rlol1_cnt_tc_1_12)
+);
+defparam rlol1_cnt_tc_1_12_cZ.init=16'h0100;
+// @16:387
+  LUT4 rlol1_cnt_tc_1_13_cZ (
+       .A(rlol1_cnt[13]),
+       .B(rlol1_cnt[14]),
+       .C(rlol1_cnt[15]),
+       .D(rlol1_cnt[16]),
+       .Z(rlol1_cnt_tc_1_13)
+);
+defparam rlol1_cnt_tc_1_13_cZ.init=16'h0040;
+// @16:866
+  LUT4 \genblk2.genblk3.rxsdr_appd_2  (
+       .A(rxsdr_appd_4),
+       .B(serdes_rst_dual_c),
+       .C(VCC),
+       .D(VCC),
+       .Z(rxsdr_appd_2)
+);
+defparam \genblk2.genblk3.rxsdr_appd_2 .init=16'hEEEE;
+// @16:601
+  LUT4 rx_all_well_cZ (
+       .A(rlol_db),
+       .B(rlos_db),
+       .C(VCC),
+       .D(VCC),
+       .Z(rx_all_well)
+);
+defparam rx_all_well_cZ.init=16'h1111;
+// @16:436
+  LUT4 \genblk2.un8_rxs_cnt_tc  (
+       .A(rxs_cnt[0]),
+       .B(rxs_cnt[1]),
+       .C(VCC),
+       .D(VCC),
+       .Z(un8_rxs_cnt_tc)
+);
+defparam \genblk2.un8_rxs_cnt_tc .init=16'h8888;
+// @16:441
+  LUT4 plol_fedge_cZ (
+       .A(pll_lol_p2),
+       .B(pll_lol_p3),
+       .C(VCC),
+       .D(VCC),
+       .Z(plol_fedge)
+);
+defparam plol_fedge_cZ.init=16'h4444;
+// @16:757
+  LUT4 rlos_redge_cZ (
+       .A(rlos_db),
+       .B(rlos_db_p1),
+       .C(VCC),
+       .D(VCC),
+       .Z(rlos_redge)
+);
+defparam rlos_redge_cZ.init=16'h2222;
+// @16:457
+  LUT4 \genblk1.plol0_cnt_3_RNO[2]  (
+       .A(plol0_cnt[0]),
+       .B(waita_plol0),
+       .C(VCC),
+       .D(VCC),
+       .Z(CO0_2)
+);
+defparam \genblk1.plol0_cnt_3_RNO[2] .init=16'h8888;
+// @16:891
+  LUT4 un2_rdo_serdes_rst_dual_c_1_1_cZ (
+       .A(rx_cdr_lol_s),
+       .B(rx_los_low_s),
+       .C(VCC),
+       .D(VCC),
+       .Z(un2_rdo_serdes_rst_dual_c_1_1)
+);
+defparam un2_rdo_serdes_rst_dual_c_1_1_cZ.init=16'h1111;
+// @16:219
+  LUT4 \un1_rlos_db_cnt_zero_am_cZ[0]  (
+       .A(rlos_db_cnt[0]),
+       .B(rlos_db_cnt[1]),
+       .C(rlos_db_cnt[2]),
+       .D(rlos_db_cnt[3]),
+       .Z(un1_rlos_db_cnt_zero_am[0])
+);
+defparam \un1_rlos_db_cnt_zero_am_cZ[0] .init=16'h0001;
+// @16:219
+  LUT4 \un1_rlol_db_cnt_zero_am_cZ[0]  (
+       .A(rlol_db_cnt[0]),
+       .B(rlol_db_cnt[1]),
+       .C(rlol_db_cnt[2]),
+       .D(rlol_db_cnt[3]),
+       .Z(un1_rlol_db_cnt_zero_am[0])
+);
+defparam \un1_rlol_db_cnt_zero_am_cZ[0] .init=16'h0001;
+// @16:861
+  LUT4 dual_or_rserd_rst_cZ (
+       .A(rsl_rx_serdes_rst_c),
+       .B(serdes_rst_dual_c),
+       .C(rsl_rst),
+       .D(rsl_disable),
+       .Z(dual_or_rserd_rst)
+);
+defparam dual_or_rserd_rst_cZ.init=16'hEEFE;
+// @16:454
+  LUT4 \genblk1.plol0_cnt9  (
+       .A(pll_lol_p2),
+       .B(plol0_cnt[2]),
+       .C(plol0_cnt[1]),
+       .D(plol0_cnt[0]),
+       .Z(plol0_cnt9)
+);
+defparam \genblk1.plol0_cnt9 .init=16'hAAAE;
+// @16:783
+  LUT4 \genblk2.rlols0_cnt11_0  (
+       .A(rlol_db_p1),
+       .B(rlol_db),
+       .C(rlos_db_p1),
+       .D(rlos_db),
+       .Z(rlols0_cnt11_0)
+);
+defparam \genblk2.rlols0_cnt11_0 .init=16'h4F44;
+// @16:527
+  LUT4 \genblk1.genblk2.txr_wt_cnt9_i  (
+       .A(tx_any_rst),
+       .B(un18_txr_wt_tc_8),
+       .C(un18_txr_wt_tc_7),
+       .D(un18_txr_wt_tc_6),
+       .Z(txr_wt_cnt_scalar)
+);
+defparam \genblk1.genblk2.txr_wt_cnt9_i .init=16'h1555;
+  CCU2C \genblk2.rlol1_cnt_cry_0[0]  (
+       .A0(VCC),
+       .B0(rlol1_cnt_scalar),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_7),
+       .COUT(rlol1_cnt_cry[0]),
+       .S0(rlol1_cnt_cry_0_S0[0]),
+       .S1(rlol1_cnt_s[0])
+);
+defparam \genblk2.rlol1_cnt_cry_0[0] .INIT0=16'h500c;
+defparam \genblk2.rlol1_cnt_cry_0[0] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[0] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[0] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[1]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[1]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[0]),
+       .COUT(rlol1_cnt_cry[2]),
+       .S0(rlol1_cnt_s[1]),
+       .S1(rlol1_cnt_s[2])
+);
+defparam \genblk2.rlol1_cnt_cry_0[1] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[1] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[1] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[1] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[3]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[3]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[4]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[2]),
+       .COUT(rlol1_cnt_cry[4]),
+       .S0(rlol1_cnt_s[3]),
+       .S1(rlol1_cnt_s[4])
+);
+defparam \genblk2.rlol1_cnt_cry_0[3] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[3] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[3] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[3] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[5]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[5]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[6]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[4]),
+       .COUT(rlol1_cnt_cry[6]),
+       .S0(rlol1_cnt_s[5]),
+       .S1(rlol1_cnt_s[6])
+);
+defparam \genblk2.rlol1_cnt_cry_0[5] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[5] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[5] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[5] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[7]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[7]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[8]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[6]),
+       .COUT(rlol1_cnt_cry[8]),
+       .S0(rlol1_cnt_s[7]),
+       .S1(rlol1_cnt_s[8])
+);
+defparam \genblk2.rlol1_cnt_cry_0[7] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[7] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[7] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[7] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[9]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[9]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[10]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[8]),
+       .COUT(rlol1_cnt_cry[10]),
+       .S0(rlol1_cnt_s[9]),
+       .S1(rlol1_cnt_s[10])
+);
+defparam \genblk2.rlol1_cnt_cry_0[9] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[9] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[9] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[9] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[11]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[11]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[12]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[10]),
+       .COUT(rlol1_cnt_cry[12]),
+       .S0(rlol1_cnt_s[11]),
+       .S1(rlol1_cnt_s[12])
+);
+defparam \genblk2.rlol1_cnt_cry_0[11] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[11] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[11] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[11] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[13]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[13]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[14]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[12]),
+       .COUT(rlol1_cnt_cry[14]),
+       .S0(rlol1_cnt_s[13]),
+       .S1(rlol1_cnt_s[14])
+);
+defparam \genblk2.rlol1_cnt_cry_0[13] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[13] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[13] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[13] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[15]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[15]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[16]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[14]),
+       .COUT(rlol1_cnt_cry[16]),
+       .S0(rlol1_cnt_s[15]),
+       .S1(rlol1_cnt_s[16])
+);
+defparam \genblk2.rlol1_cnt_cry_0[15] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[15] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[15] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[15] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[17]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[17]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[18]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[16]),
+       .COUT(rlol1_cnt_cry_0_COUT[17]),
+       .S0(rlol1_cnt_s[17]),
+       .S1(rlol1_cnt_s[18])
+);
+defparam \genblk2.rlol1_cnt_cry_0[17] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[17] .INIT1=16'h800a;
+defparam \genblk2.rlol1_cnt_cry_0[17] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[17] .INJECT1_1="NO";
+  CCU2C \genblk2.rlols0_cnt_cry_0[0]  (
+       .A0(VCC),
+       .B0(rlols0_cnt_scalar),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_6),
+       .COUT(rlols0_cnt_cry[0]),
+       .S0(rlols0_cnt_cry_0_S0[0]),
+       .S1(rlols0_cnt_s[0])
+);
+defparam \genblk2.rlols0_cnt_cry_0[0] .INIT0=16'h500c;
+defparam \genblk2.rlols0_cnt_cry_0[0] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[0] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[0] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[1]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[1]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[0]),
+       .COUT(rlols0_cnt_cry[2]),
+       .S0(rlols0_cnt_s[1]),
+       .S1(rlols0_cnt_s[2])
+);
+defparam \genblk2.rlols0_cnt_cry_0[1] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[1] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[1] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[1] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[3]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[3]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[4]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[2]),
+       .COUT(rlols0_cnt_cry[4]),
+       .S0(rlols0_cnt_s[3]),
+       .S1(rlols0_cnt_s[4])
+);
+defparam \genblk2.rlols0_cnt_cry_0[3] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[3] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[3] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[3] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[5]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[5]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[6]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[4]),
+       .COUT(rlols0_cnt_cry[6]),
+       .S0(rlols0_cnt_s[5]),
+       .S1(rlols0_cnt_s[6])
+);
+defparam \genblk2.rlols0_cnt_cry_0[5] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[5] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[5] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[5] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[7]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[7]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[8]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[6]),
+       .COUT(rlols0_cnt_cry[8]),
+       .S0(rlols0_cnt_s[7]),
+       .S1(rlols0_cnt_s[8])
+);
+defparam \genblk2.rlols0_cnt_cry_0[7] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[7] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[7] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[7] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[9]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[9]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[10]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[8]),
+       .COUT(rlols0_cnt_cry[10]),
+       .S0(rlols0_cnt_s[9]),
+       .S1(rlols0_cnt_s[10])
+);
+defparam \genblk2.rlols0_cnt_cry_0[9] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[9] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[9] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[9] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[11]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[11]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[12]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[10]),
+       .COUT(rlols0_cnt_cry[12]),
+       .S0(rlols0_cnt_s[11]),
+       .S1(rlols0_cnt_s[12])
+);
+defparam \genblk2.rlols0_cnt_cry_0[11] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[11] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[11] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[11] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[13]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[13]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[14]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[12]),
+       .COUT(rlols0_cnt_cry[14]),
+       .S0(rlols0_cnt_s[13]),
+       .S1(rlols0_cnt_s[14])
+);
+defparam \genblk2.rlols0_cnt_cry_0[13] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[13] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[13] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[13] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[15]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[15]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[16]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[14]),
+       .COUT(rlols0_cnt_cry[16]),
+       .S0(rlols0_cnt_s[15]),
+       .S1(rlols0_cnt_s[16])
+);
+defparam \genblk2.rlols0_cnt_cry_0[15] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[15] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[15] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[15] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_s_0[17]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[17]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[16]),
+       .COUT(rlols0_cnt_s_0_COUT[17]),
+       .S0(rlols0_cnt_s[17]),
+       .S1(rlols0_cnt_s_0_S1[17])
+);
+defparam \genblk2.rlols0_cnt_s_0[17] .INIT0=16'h800a;
+defparam \genblk2.rlols0_cnt_s_0[17] .INIT1=16'h5003;
+defparam \genblk2.rlols0_cnt_s_0[17] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_s_0[17] .INJECT1_1="NO";
+  CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[0]  (
+       .A0(VCC),
+       .B0(txr_wt_cnt_scalar),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(txr_wt_cnt_scalar),
+       .B1(txr_wt_cnt[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_5),
+       .COUT(txr_wt_cnt_cry[0]),
+       .S0(txr_wt_cnt_cry_0_S0[0]),
+       .S1(txr_wt_cnt_s[0])
+);
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[0] .INIT0=16'h500c;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[0] .INIT1=16'h8000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[0] .INJECT1_0="NO";
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[0] .INJECT1_1="NO";
+// @16:527
+  CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[1]  (
+       .A0(txr_wt_cnt_scalar),
+       .B0(txr_wt_cnt[1]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(txr_wt_cnt_scalar),
+       .B1(txr_wt_cnt[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(txr_wt_cnt_cry[0]),
+       .COUT(txr_wt_cnt_cry[2]),
+       .S0(txr_wt_cnt_s[1]),
+       .S1(txr_wt_cnt_s[2])
+);
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[1] .INIT0=16'h8000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[1] .INIT1=16'h8000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[1] .INJECT1_0="NO";
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[1] .INJECT1_1="NO";
+// @16:527
+  CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[3]  (
+       .A0(txr_wt_cnt_scalar),
+       .B0(txr_wt_cnt[3]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(txr_wt_cnt_scalar),
+       .B1(txr_wt_cnt[4]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(txr_wt_cnt_cry[2]),
+       .COUT(txr_wt_cnt_cry[4]),
+       .S0(txr_wt_cnt_s[3]),
+       .S1(txr_wt_cnt_s[4])
+);
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[3] .INIT0=16'h8000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[3] .INIT1=16'h8000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[3] .INJECT1_0="NO";
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[3] .INJECT1_1="NO";
+// @16:527
+  CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[5]  (
+       .A0(txr_wt_cnt_scalar),
+       .B0(txr_wt_cnt[5]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(txr_wt_cnt_scalar),
+       .B1(txr_wt_cnt[6]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(txr_wt_cnt_cry[4]),
+       .COUT(txr_wt_cnt_cry[6]),
+       .S0(txr_wt_cnt_s[5]),
+       .S1(txr_wt_cnt_s[6])
+);
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[5] .INIT0=16'h8000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[5] .INIT1=16'h8000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[5] .INJECT1_0="NO";
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[5] .INJECT1_1="NO";
+// @16:527
+  CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[7]  (
+       .A0(txr_wt_cnt_scalar),
+       .B0(txr_wt_cnt[7]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(txr_wt_cnt_scalar),
+       .B1(txr_wt_cnt[8]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(txr_wt_cnt_cry[6]),
+       .COUT(txr_wt_cnt_cry[8]),
+       .S0(txr_wt_cnt_s[7]),
+       .S1(txr_wt_cnt_s[8])
+);
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[7] .INIT0=16'h8000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[7] .INIT1=16'h8000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[7] .INJECT1_0="NO";
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[7] .INJECT1_1="NO";
+// @16:527
+  CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[9]  (
+       .A0(txr_wt_cnt_scalar),
+       .B0(txr_wt_cnt[9]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(txr_wt_cnt_scalar),
+       .B1(txr_wt_cnt[10]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(txr_wt_cnt_cry[8]),
+       .COUT(txr_wt_cnt_cry[10]),
+       .S0(txr_wt_cnt_s[9]),
+       .S1(txr_wt_cnt_s[10])
+);
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[9] .INIT0=16'h8000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[9] .INIT1=16'h8000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[9] .INJECT1_0="NO";
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[9] .INJECT1_1="NO";
+// @16:527
+  CCU2C \genblk1.genblk2.txr_wt_cnt_s_0[11]  (
+       .A0(txr_wt_cnt_scalar),
+       .B0(txr_wt_cnt[11]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(txr_wt_cnt_cry[10]),
+       .COUT(txr_wt_cnt_s_0_COUT[11]),
+       .S0(txr_wt_cnt_s[11]),
+       .S1(txr_wt_cnt_s_0_S1[11])
+);
+defparam \genblk1.genblk2.txr_wt_cnt_s_0[11] .INIT0=16'h800a;
+defparam \genblk1.genblk2.txr_wt_cnt_s_0[11] .INIT1=16'h5003;
+defparam \genblk1.genblk2.txr_wt_cnt_s_0[11] .INJECT1_0="NO";
+defparam \genblk1.genblk2.txr_wt_cnt_s_0[11] .INJECT1_1="NO";
+  CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[0]  (
+       .A0(VCC),
+       .B0(rxr_wt_cnt9),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rxr_wt_cnt9),
+       .B1(rxr_wt_cnt[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_4),
+       .COUT(rxr_wt_cnt_cry[0]),
+       .S0(rxr_wt_cnt_cry_0_S0[0]),
+       .S1(rxr_wt_cnt_s[0])
+);
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[0] .INIT0=16'h5003;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[0] .INIT1=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[0] .INJECT1_0="NO";
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[0] .INJECT1_1="NO";
+// @16:909
+  CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[1]  (
+       .A0(rxr_wt_cnt9),
+       .B0(rxr_wt_cnt[1]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rxr_wt_cnt9),
+       .B1(rxr_wt_cnt[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rxr_wt_cnt_cry[0]),
+       .COUT(rxr_wt_cnt_cry[2]),
+       .S0(rxr_wt_cnt_s[1]),
+       .S1(rxr_wt_cnt_s[2])
+);
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[1] .INIT0=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[1] .INIT1=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[1] .INJECT1_0="NO";
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[1] .INJECT1_1="NO";
+// @16:909
+  CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[3]  (
+       .A0(rxr_wt_cnt9),
+       .B0(rxr_wt_cnt[3]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rxr_wt_cnt9),
+       .B1(rxr_wt_cnt[4]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rxr_wt_cnt_cry[2]),
+       .COUT(rxr_wt_cnt_cry[4]),
+       .S0(rxr_wt_cnt_s[3]),
+       .S1(rxr_wt_cnt_s[4])
+);
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[3] .INIT0=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[3] .INIT1=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[3] .INJECT1_0="NO";
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[3] .INJECT1_1="NO";
+// @16:909
+  CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[5]  (
+       .A0(rxr_wt_cnt9),
+       .B0(rxr_wt_cnt[5]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rxr_wt_cnt9),
+       .B1(rxr_wt_cnt[6]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rxr_wt_cnt_cry[4]),
+       .COUT(rxr_wt_cnt_cry[6]),
+       .S0(rxr_wt_cnt_s[5]),
+       .S1(rxr_wt_cnt_s[6])
+);
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[5] .INIT0=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[5] .INIT1=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[5] .INJECT1_0="NO";
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[5] .INJECT1_1="NO";
+// @16:909
+  CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[7]  (
+       .A0(rxr_wt_cnt9),
+       .B0(rxr_wt_cnt[7]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rxr_wt_cnt9),
+       .B1(rxr_wt_cnt[8]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rxr_wt_cnt_cry[6]),
+       .COUT(rxr_wt_cnt_cry[8]),
+       .S0(rxr_wt_cnt_s[7]),
+       .S1(rxr_wt_cnt_s[8])
+);
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[7] .INIT0=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[7] .INIT1=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[7] .INJECT1_0="NO";
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[7] .INJECT1_1="NO";
+// @16:909
+  CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[9]  (
+       .A0(rxr_wt_cnt9),
+       .B0(rxr_wt_cnt[9]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rxr_wt_cnt9),
+       .B1(rxr_wt_cnt[10]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rxr_wt_cnt_cry[8]),
+       .COUT(rxr_wt_cnt_cry[10]),
+       .S0(rxr_wt_cnt_s[9]),
+       .S1(rxr_wt_cnt_s[10])
+);
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[9] .INIT0=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[9] .INIT1=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[9] .INJECT1_0="NO";
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[9] .INJECT1_1="NO";
+// @16:909
+  CCU2C \genblk2.genblk3.rxr_wt_cnt_s_0[11]  (
+       .A0(rxr_wt_cnt9),
+       .B0(rxr_wt_cnt[11]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rxr_wt_cnt_cry[10]),
+       .COUT(rxr_wt_cnt_s_0_COUT[11]),
+       .S0(rxr_wt_cnt_s[11]),
+       .S1(rxr_wt_cnt_s_0_S1[11])
+);
+defparam \genblk2.genblk3.rxr_wt_cnt_s_0[11] .INIT0=16'h4005;
+defparam \genblk2.genblk3.rxr_wt_cnt_s_0[11] .INIT1=16'h5003;
+defparam \genblk2.genblk3.rxr_wt_cnt_s_0[11] .INJECT1_0="NO";
+defparam \genblk2.genblk3.rxr_wt_cnt_s_0[11] .INJECT1_1="NO";
+  CCU2C \genblk1.plol_cnt_cry_0[0]  (
+       .A0(VCC),
+       .B0(plol_cnt_scalar),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_3),
+       .COUT(plol_cnt_cry[0]),
+       .S0(plol_cnt_cry_0_S0[0]),
+       .S1(plol_cnt_s[0])
+);
+defparam \genblk1.plol_cnt_cry_0[0] .INIT0=16'h500c;
+defparam \genblk1.plol_cnt_cry_0[0] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[0] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[0] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[1]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[1]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[0]),
+       .COUT(plol_cnt_cry[2]),
+       .S0(plol_cnt_s[1]),
+       .S1(plol_cnt_s[2])
+);
+defparam \genblk1.plol_cnt_cry_0[1] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[1] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[1] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[1] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[3]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[3]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[4]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[2]),
+       .COUT(plol_cnt_cry[4]),
+       .S0(plol_cnt_s[3]),
+       .S1(plol_cnt_s[4])
+);
+defparam \genblk1.plol_cnt_cry_0[3] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[3] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[3] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[3] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[5]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[5]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[6]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[4]),
+       .COUT(plol_cnt_cry[6]),
+       .S0(plol_cnt_s[5]),
+       .S1(plol_cnt_s[6])
+);
+defparam \genblk1.plol_cnt_cry_0[5] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[5] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[5] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[5] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[7]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[7]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[8]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[6]),
+       .COUT(plol_cnt_cry[8]),
+       .S0(plol_cnt_s[7]),
+       .S1(plol_cnt_s[8])
+);
+defparam \genblk1.plol_cnt_cry_0[7] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[7] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[7] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[7] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[9]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[9]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[10]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[8]),
+       .COUT(plol_cnt_cry[10]),
+       .S0(plol_cnt_s[9]),
+       .S1(plol_cnt_s[10])
+);
+defparam \genblk1.plol_cnt_cry_0[9] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[9] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[9] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[9] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[11]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[11]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[12]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[10]),
+       .COUT(plol_cnt_cry[12]),
+       .S0(plol_cnt_s[11]),
+       .S1(plol_cnt_s[12])
+);
+defparam \genblk1.plol_cnt_cry_0[11] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[11] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[11] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[11] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[13]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[13]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[14]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[12]),
+       .COUT(plol_cnt_cry[14]),
+       .S0(plol_cnt_s[13]),
+       .S1(plol_cnt_s[14])
+);
+defparam \genblk1.plol_cnt_cry_0[13] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[13] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[13] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[13] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[15]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[15]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[16]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[14]),
+       .COUT(plol_cnt_cry[16]),
+       .S0(plol_cnt_s[15]),
+       .S1(plol_cnt_s[16])
+);
+defparam \genblk1.plol_cnt_cry_0[15] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[15] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[15] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[15] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[17]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[17]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[18]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[16]),
+       .COUT(plol_cnt_cry[18]),
+       .S0(plol_cnt_s[17]),
+       .S1(plol_cnt_s[18])
+);
+defparam \genblk1.plol_cnt_cry_0[17] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[17] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[17] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[17] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_s_0[19]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[19]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[18]),
+       .COUT(plol_cnt_s_0_COUT[19]),
+       .S0(plol_cnt_s[19]),
+       .S1(plol_cnt_s_0_S1[19])
+);
+defparam \genblk1.plol_cnt_s_0[19] .INIT0=16'h800a;
+defparam \genblk1.plol_cnt_s_0[19] .INIT1=16'h5003;
+defparam \genblk1.plol_cnt_s_0[19] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_s_0[19] .INJECT1_1="NO";
+  CCU2C \un1_genblk2.rlos_db_cnt_cry_0_0  (
+       .A0(VCC),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlos_db_cnt[0]),
+       .B1(un1_rlos_db_cnt_zero[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_2),
+       .COUT(rlos_db_cnt_cry_0),
+       .S0(rlos_db_cnt_cry_0_0_S0),
+       .S1(rlos_db_cnt_cry_0_0_S1)
+);
+defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INIT0=16'h5003;
+defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INIT1=16'h900a;
+defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INJECT1_0="NO";
+defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INJECT1_1="NO";
+// @16:641
+  CCU2C \un1_genblk2.rlos_db_cnt_cry_1_0  (
+       .A0(un1_rlos_db_cnt_zero[0]),
+       .B0(rlos_p2),
+       .C0(rlos_db_cnt[1]),
+       .D0(VCC),
+       .A1(un1_rlos_db_cnt_zero[0]),
+       .B1(rlos_p2),
+       .C1(rlos_db_cnt[2]),
+       .D1(VCC),
+       .CIN(rlos_db_cnt_cry_0),
+       .COUT(rlos_db_cnt_cry_2),
+       .S0(rlos_db_cnt_cry_1_0_S0),
+       .S1(rlos_db_cnt_cry_1_0_S1)
+);
+defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INIT0=16'he101;
+defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INIT1=16'he101;
+defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INJECT1_0="NO";
+defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INJECT1_1="NO";
+// @16:641
+  CCU2C \un1_genblk2.rlos_db_cnt_s_3_0  (
+       .A0(rlos_db_cnt[3]),
+       .B0(rlos_p2),
+       .C0(un1_rlos_db_cnt_zero[0]),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlos_db_cnt_cry_2),
+       .COUT(rlos_db_cnt_s_3_0_COUT),
+       .S0(rlos_db_cnt_s_3_0_S0),
+       .S1(rlos_db_cnt_s_3_0_S1)
+);
+defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INIT0=16'ha90a;
+defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INIT1=16'h5003;
+defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INJECT1_0="NO";
+defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INJECT1_1="NO";
+  CCU2C \un1_genblk2.rlol_db_cnt_cry_0_0  (
+       .A0(VCC),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol_db_cnt[0]),
+       .B1(un1_rlol_db_cnt_zero[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_1),
+       .COUT(rlol_db_cnt_cry_0),
+       .S0(rlol_db_cnt_cry_0_0_S0),
+       .S1(rlol_db_cnt_cry_0_0_S1)
+);
+defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INIT0=16'h5003;
+defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INIT1=16'h900a;
+defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INJECT1_0="NO";
+defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INJECT1_1="NO";
+// @16:625
+  CCU2C \un1_genblk2.rlol_db_cnt_cry_1_0  (
+       .A0(un1_rlol_db_cnt_zero[0]),
+       .B0(rlol_p2),
+       .C0(rlol_db_cnt[1]),
+       .D0(VCC),
+       .A1(un1_rlol_db_cnt_zero[0]),
+       .B1(rlol_p2),
+       .C1(rlol_db_cnt[2]),
+       .D1(VCC),
+       .CIN(rlol_db_cnt_cry_0),
+       .COUT(rlol_db_cnt_cry_2),
+       .S0(rlol_db_cnt_cry_1_0_S0),
+       .S1(rlol_db_cnt_cry_1_0_S1)
+);
+defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INIT0=16'he101;
+defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INIT1=16'he101;
+defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INJECT1_0="NO";
+defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INJECT1_1="NO";
+// @16:625
+  CCU2C \un1_genblk2.rlol_db_cnt_s_3_0  (
+       .A0(rlol_db_cnt[3]),
+       .B0(rlol_p2),
+       .C0(un1_rlol_db_cnt_zero[0]),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol_db_cnt_cry_2),
+       .COUT(rlol_db_cnt_s_3_0_COUT),
+       .S0(rlol_db_cnt_s_3_0_S0),
+       .S1(rlol_db_cnt_s_3_0_S1)
+);
+defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INIT0=16'ha90a;
+defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INIT1=16'h5003;
+defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INJECT1_0="NO";
+defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INJECT1_1="NO";
+//@16:865
+//@16:492
+  VHI VCC_0 (
+       .Z(VCC)
+);
+// @16:865
+  VLO GND_cZ (
+       .Z(GND)
+);
+endmodule /* sgmii_ecp5rsl_core_Z2_layer1 */
+
+module sgmii_ecp5 (
+  hdoutp,
+  hdoutn,
+  hdinp,
+  hdinn,
+  rxrefclk,
+  tx_pclk,
+  txi_clk,
+  txdata,
+  tx_k,
+  xmit,
+  tx_disp_correct,
+  rxdata,
+  rx_k,
+  rx_disp_err,
+  rx_cv_err,
+  signal_detect_c,
+  rx_los_low_s,
+  lsm_status_s,
+  ctc_urun_s,
+  ctc_orun_s,
+  rx_cdr_lol_s,
+  ctc_ins_s,
+  ctc_del_s,
+  sli_rst,
+  tx_pwrup_c,
+  rx_pwrup_c,
+  sci_wrdata,
+  sci_addr,
+  sci_rddata,
+  sci_en_dual,
+  sci_sel_dual,
+  sci_en,
+  sci_sel,
+  sci_rd,
+  sci_wrn,
+  sci_int,
+  cyawstn,
+  serdes_pdb,
+  pll_refclki,
+  rsl_disable,
+  rsl_rst,
+  serdes_rst_dual_c,
+  rst_dual_c,
+  tx_serdes_rst_c,
+  tx_pcs_rst_c,
+  pll_lol,
+  rsl_tx_rdy,
+  rx_serdes_rst_c,
+  rx_pcs_rst_c,
+  rsl_rx_rdy
+)
+;
+output hdoutp ;
+output hdoutn ;
+input hdinp ;
+input hdinn ;
+input rxrefclk ;
+output tx_pclk ;
+input txi_clk ;
+input [7:0] txdata ;
+input [0:0] tx_k ;
+input [0:0] xmit ;
+input [0:0] tx_disp_correct ;
+output [7:0] rxdata ;
+output [0:0] rx_k ;
+output [0:0] rx_disp_err ;
+output [0:0] rx_cv_err ;
+input signal_detect_c ;
+output rx_los_low_s ;
+output lsm_status_s ;
+output ctc_urun_s ;
+output ctc_orun_s ;
+output rx_cdr_lol_s ;
+output ctc_ins_s ;
+output ctc_del_s ;
+input sli_rst ;
+input tx_pwrup_c ;
+input rx_pwrup_c ;
+input [7:0] sci_wrdata ;
+input [5:0] sci_addr ;
+output [7:0] sci_rddata ;
+input sci_en_dual ;
+input sci_sel_dual ;
+input sci_en ;
+input sci_sel ;
+input sci_rd ;
+input sci_wrn ;
+output sci_int ;
+input cyawstn ;
+input serdes_pdb ;
+input pll_refclki ;
+input rsl_disable ;
+input rsl_rst ;
+input serdes_rst_dual_c ;
+input rst_dual_c ;
+input tx_serdes_rst_c ;
+input tx_pcs_rst_c ;
+output pll_lol ;
+output rsl_tx_rdy ;
+input rx_serdes_rst_c ;
+input rx_pcs_rst_c ;
+output rsl_rx_rdy ;
+wire hdoutp ;
+wire hdoutn ;
+wire hdinp ;
+wire hdinn ;
+wire rxrefclk ;
+wire tx_pclk ;
+wire txi_clk ;
+wire signal_detect_c ;
+wire rx_los_low_s ;
+wire lsm_status_s ;
+wire ctc_urun_s ;
+wire ctc_orun_s ;
+wire rx_cdr_lol_s ;
+wire ctc_ins_s ;
+wire ctc_del_s ;
+wire sli_rst ;
+wire tx_pwrup_c ;
+wire rx_pwrup_c ;
+wire sci_en_dual ;
+wire sci_sel_dual ;
+wire sci_en ;
+wire sci_sel ;
+wire sci_rd ;
+wire sci_wrn ;
+wire sci_int ;
+wire cyawstn ;
+wire serdes_pdb ;
+wire pll_refclki ;
+wire rsl_disable ;
+wire rsl_rst ;
+wire serdes_rst_dual_c ;
+wire rst_dual_c ;
+wire tx_serdes_rst_c ;
+wire tx_pcs_rst_c ;
+wire pll_lol ;
+wire rsl_tx_rdy ;
+wire rx_serdes_rst_c ;
+wire rx_pcs_rst_c ;
+wire rsl_rx_rdy ;
+wire rsl_tx_pcs_rst_c ;
+wire rsl_rx_pcs_rst_c ;
+wire rsl_rx_serdes_rst_c ;
+wire rsl_serdes_rst_dual_c ;
+wire rsl_tx_serdes_rst_c ;
+wire n47_1 ;
+wire n48_1 ;
+wire n1_1 ;
+wire n2_1 ;
+wire n3_1 ;
+wire n4_1 ;
+wire n5_1 ;
+wire n49_1 ;
+wire n6_1 ;
+wire n50_1 ;
+wire n7_1 ;
+wire n51_1 ;
+wire n8_1 ;
+wire n52_1 ;
+wire n9_1 ;
+wire n53_1 ;
+wire n54_1 ;
+wire n55_1 ;
+wire n56_1 ;
+wire n57_1 ;
+wire n58_1 ;
+wire n59_1 ;
+wire n60_1 ;
+wire n61_1 ;
+wire n62_1 ;
+wire n63_1 ;
+wire n64_1 ;
+wire n65_1 ;
+wire n10_1 ;
+wire n66_1 ;
+wire n67_1 ;
+wire n68_1 ;
+wire n69_1 ;
+wire n70_1 ;
+wire n71_1 ;
+wire n72_1 ;
+wire n73_1 ;
+wire n74_1 ;
+wire n75_1 ;
+wire n76_1 ;
+wire n77_1 ;
+wire n78_1 ;
+wire n79_1 ;
+wire n80_1 ;
+wire n81_1 ;
+wire n82_1 ;
+wire n83_1 ;
+wire n84_1 ;
+wire n85_1 ;
+wire n86_1 ;
+wire n87_1 ;
+wire n88_1 ;
+wire n11_1 ;
+wire n89_1 ;
+wire n12_1 ;
+wire n90_1 ;
+wire n13_1 ;
+wire n91_1 ;
+wire n92_1 ;
+wire n93_1 ;
+wire n94_1 ;
+wire n95_1 ;
+wire n14_1 ;
+wire n96_1 ;
+wire n15_1 ;
+wire n97_1 ;
+wire n98_1 ;
+wire n99_1 ;
+wire n100_1 ;
+wire n101_1 ;
+wire n112_1 ;
+wire n16_1 ;
+wire n17_1 ;
+wire n18_1 ;
+wire n19_1 ;
+wire n20_1 ;
+wire n21_1 ;
+wire n22_1 ;
+wire n23_1 ;
+wire n24_1 ;
+wire n25_1 ;
+wire n26_1 ;
+wire n27_1 ;
+wire n28_1 ;
+wire n29_1 ;
+wire n30_1 ;
+wire n31_1 ;
+wire n32_1 ;
+wire n33_1 ;
+wire n34_1 ;
+wire n35_1 ;
+wire n36_1 ;
+wire n37_1 ;
+wire n38_1 ;
+wire n39_1 ;
+wire n40_1 ;
+wire n41_1 ;
+wire n42_1 ;
+wire n43_1 ;
+wire n46_1 ;
+wire GND ;
+wire VCC ;
+  VHI VCC_0 (
+       .Z(VCC)
+);
+  VLO GND_0 (
+       .Z(GND)
+);
+// @16:865
+  PUR PUR_INST (
+       .PUR(VCC)
+);
+// @16:865
+  GSR GSR_INST (
+       .GSR(VCC)
+);
+// @8:162
+(* CHAN="CH0" *)  DCUA DCU0_inst (
+       .CH0_HDINP(hdinp),
+       .CH1_HDINP(GND),
+       .CH0_HDINN(hdinn),
+       .CH1_HDINN(GND),
+       .D_TXBIT_CLKP_FROM_ND(GND),
+       .D_TXBIT_CLKN_FROM_ND(GND),
+       .D_SYNC_ND(GND),
+       .D_TXPLL_LOL_FROM_ND(GND),
+       .CH0_RX_REFCLK(rxrefclk),
+       .CH1_RX_REFCLK(GND),
+       .CH0_FF_RXI_CLK(tx_pclk),
+       .CH1_FF_RXI_CLK(VCC),
+       .CH0_FF_TXI_CLK(txi_clk),
+       .CH1_FF_TXI_CLK(VCC),
+       .CH0_FF_EBRD_CLK(tx_pclk),
+       .CH1_FF_EBRD_CLK(VCC),
+       .CH0_FF_TX_D_0(txdata[0]),
+       .CH1_FF_TX_D_0(GND),
+       .CH0_FF_TX_D_1(txdata[1]),
+       .CH1_FF_TX_D_1(GND),
+       .CH0_FF_TX_D_2(txdata[2]),
+       .CH1_FF_TX_D_2(GND),
+       .CH0_FF_TX_D_3(txdata[3]),
+       .CH1_FF_TX_D_3(GND),
+       .CH0_FF_TX_D_4(txdata[4]),
+       .CH1_FF_TX_D_4(GND),
+       .CH0_FF_TX_D_5(txdata[5]),
+       .CH1_FF_TX_D_5(GND),
+       .CH0_FF_TX_D_6(txdata[6]),
+       .CH1_FF_TX_D_6(GND),
+       .CH0_FF_TX_D_7(txdata[7]),
+       .CH1_FF_TX_D_7(GND),
+       .CH0_FF_TX_D_8(tx_k[0]),
+       .CH1_FF_TX_D_8(GND),
+       .CH0_FF_TX_D_9(GND),
+       .CH1_FF_TX_D_9(GND),
+       .CH0_FF_TX_D_10(xmit[0]),
+       .CH1_FF_TX_D_10(GND),
+       .CH0_FF_TX_D_11(tx_disp_correct[0]),
+       .CH1_FF_TX_D_11(GND),
+       .CH0_FF_TX_D_12(GND),
+       .CH1_FF_TX_D_12(GND),
+       .CH0_FF_TX_D_13(GND),
+       .CH1_FF_TX_D_13(GND),
+       .CH0_FF_TX_D_14(GND),
+       .CH1_FF_TX_D_14(GND),
+       .CH0_FF_TX_D_15(GND),
+       .CH1_FF_TX_D_15(GND),
+       .CH0_FF_TX_D_16(GND),
+       .CH1_FF_TX_D_16(GND),
+       .CH0_FF_TX_D_17(GND),
+       .CH1_FF_TX_D_17(GND),
+       .CH0_FF_TX_D_18(GND),
+       .CH1_FF_TX_D_18(GND),
+       .CH0_FF_TX_D_19(GND),
+       .CH1_FF_TX_D_19(GND),
+       .CH0_FF_TX_D_20(GND),
+       .CH1_FF_TX_D_20(GND),
+       .CH0_FF_TX_D_21(GND),
+       .CH1_FF_TX_D_21(GND),
+       .CH0_FF_TX_D_22(GND),
+       .CH1_FF_TX_D_22(GND),
+       .CH0_FF_TX_D_23(GND),
+       .CH1_FF_TX_D_23(GND),
+       .CH0_FFC_EI_EN(GND),
+       .CH1_FFC_EI_EN(GND),
+       .CH0_FFC_PCIE_DET_EN(GND),
+       .CH1_FFC_PCIE_DET_EN(GND),
+       .CH0_FFC_PCIE_CT(GND),
+       .CH1_FFC_PCIE_CT(GND),
+       .CH0_FFC_SB_INV_RX(GND),
+       .CH1_FFC_SB_INV_RX(GND),
+       .CH0_FFC_ENABLE_CGALIGN(GND),
+       .CH1_FFC_ENABLE_CGALIGN(GND),
+       .CH0_FFC_SIGNAL_DETECT(signal_detect_c),
+       .CH1_FFC_SIGNAL_DETECT(GND),
+       .CH0_FFC_FB_LOOPBACK(GND),
+       .CH1_FFC_FB_LOOPBACK(GND),
+       .CH0_FFC_SB_PFIFO_LP(GND),
+       .CH1_FFC_SB_PFIFO_LP(GND),
+       .CH0_FFC_PFIFO_CLR(GND),
+       .CH1_FFC_PFIFO_CLR(GND),
+       .CH0_FFC_RATE_MODE_RX(GND),
+       .CH1_FFC_RATE_MODE_RX(GND),
+       .CH0_FFC_RATE_MODE_TX(GND),
+       .CH1_FFC_RATE_MODE_TX(GND),
+       .CH0_FFC_DIV11_MODE_RX(GND),
+       .CH1_FFC_DIV11_MODE_RX(GND),
+       .CH0_FFC_RX_GEAR_MODE(GND),
+       .CH1_FFC_RX_GEAR_MODE(GND),
+       .CH0_FFC_TX_GEAR_MODE(GND),
+       .CH1_FFC_TX_GEAR_MODE(GND),
+       .CH0_FFC_DIV11_MODE_TX(GND),
+       .CH1_FFC_DIV11_MODE_TX(GND),
+       .CH0_FFC_LDR_CORE2TX_EN(GND),
+       .CH1_FFC_LDR_CORE2TX_EN(GND),
+       .CH0_FFC_LANE_TX_RST(rsl_tx_pcs_rst_c),
+       .CH1_FFC_LANE_TX_RST(GND),
+       .CH0_FFC_LANE_RX_RST(rsl_rx_pcs_rst_c),
+       .CH1_FFC_LANE_RX_RST(GND),
+       .CH0_FFC_RRST(rsl_rx_serdes_rst_c),
+       .CH1_FFC_RRST(GND),
+       .CH0_FFC_TXPWDNB(tx_pwrup_c),
+       .CH1_FFC_TXPWDNB(GND),
+       .CH0_FFC_RXPWDNB(rx_pwrup_c),
+       .CH1_FFC_RXPWDNB(GND),
+       .CH0_LDR_CORE2TX(GND),
+       .CH1_LDR_CORE2TX(GND),
+       .D_SCIWDATA0(sci_wrdata[0]),
+       .D_SCIWDATA1(sci_wrdata[1]),
+       .D_SCIWDATA2(sci_wrdata[2]),
+       .D_SCIWDATA3(sci_wrdata[3]),
+       .D_SCIWDATA4(sci_wrdata[4]),
+       .D_SCIWDATA5(sci_wrdata[5]),
+       .D_SCIWDATA6(sci_wrdata[6]),
+       .D_SCIWDATA7(sci_wrdata[7]),
+       .D_SCIADDR0(sci_addr[0]),
+       .D_SCIADDR1(sci_addr[1]),
+       .D_SCIADDR2(sci_addr[2]),
+       .D_SCIADDR3(sci_addr[3]),
+       .D_SCIADDR4(sci_addr[4]),
+       .D_SCIADDR5(sci_addr[5]),
+       .D_SCIENAUX(sci_en_dual),
+       .D_SCISELAUX(sci_sel_dual),
+       .CH0_SCIEN(sci_en),
+       .CH1_SCIEN(GND),
+       .CH0_SCISEL(sci_sel),
+       .CH1_SCISEL(GND),
+       .D_SCIRD(sci_rd),
+       .D_SCIWSTN(sci_wrn),
+       .D_CYAWSTN(cyawstn),
+       .D_FFC_SYNC_TOGGLE(GND),
+       .D_FFC_DUAL_RST(rst_dual_c),
+       .D_FFC_MACRO_RST(rsl_serdes_rst_dual_c),
+       .D_FFC_MACROPDB(serdes_pdb),
+       .D_FFC_TRST(rsl_tx_serdes_rst_c),
+       .CH0_FFC_CDR_EN_BITSLIP(GND),
+       .CH1_FFC_CDR_EN_BITSLIP(GND),
+       .D_SCAN_ENABLE(GND),
+       .D_SCAN_IN_0(GND),
+       .D_SCAN_IN_1(GND),
+       .D_SCAN_IN_2(GND),
+       .D_SCAN_IN_3(GND),
+       .D_SCAN_IN_4(GND),
+       .D_SCAN_IN_5(GND),
+       .D_SCAN_IN_6(GND),
+       .D_SCAN_IN_7(GND),
+       .D_SCAN_MODE(GND),
+       .D_SCAN_RESET(GND),
+       .D_CIN0(GND),
+       .D_CIN1(GND),
+       .D_CIN2(GND),
+       .D_CIN3(GND),
+       .D_CIN4(GND),
+       .D_CIN5(GND),
+       .D_CIN6(GND),
+       .D_CIN7(GND),
+       .D_CIN8(GND),
+       .D_CIN9(GND),
+       .D_CIN10(GND),
+       .D_CIN11(GND),
+       .CH0_HDOUTP(hdoutp),
+       .CH1_HDOUTP(n47_1),
+       .CH0_HDOUTN(hdoutn),
+       .CH1_HDOUTN(n48_1),
+       .D_TXBIT_CLKP_TO_ND(n1_1),
+       .D_TXBIT_CLKN_TO_ND(n2_1),
+       .D_SYNC_PULSE2ND(n3_1),
+       .D_TXPLL_LOL_TO_ND(n4_1),
+       .CH0_FF_RX_F_CLK(n5_1),
+       .CH1_FF_RX_F_CLK(n49_1),
+       .CH0_FF_RX_H_CLK(n6_1),
+       .CH1_FF_RX_H_CLK(n50_1),
+       .CH0_FF_TX_F_CLK(n7_1),
+       .CH1_FF_TX_F_CLK(n51_1),
+       .CH0_FF_TX_H_CLK(n8_1),
+       .CH1_FF_TX_H_CLK(n52_1),
+       .CH0_FF_RX_PCLK(n9_1),
+       .CH1_FF_RX_PCLK(n53_1),
+       .CH0_FF_TX_PCLK(tx_pclk),
+       .CH1_FF_TX_PCLK(n54_1),
+       .CH0_FF_RX_D_0(rxdata[0]),
+       .CH1_FF_RX_D_0(n55_1),
+       .CH0_FF_RX_D_1(rxdata[1]),
+       .CH1_FF_RX_D_1(n56_1),
+       .CH0_FF_RX_D_2(rxdata[2]),
+       .CH1_FF_RX_D_2(n57_1),
+       .CH0_FF_RX_D_3(rxdata[3]),
+       .CH1_FF_RX_D_3(n58_1),
+       .CH0_FF_RX_D_4(rxdata[4]),
+       .CH1_FF_RX_D_4(n59_1),
+       .CH0_FF_RX_D_5(rxdata[5]),
+       .CH1_FF_RX_D_5(n60_1),
+       .CH0_FF_RX_D_6(rxdata[6]),
+       .CH1_FF_RX_D_6(n61_1),
+       .CH0_FF_RX_D_7(rxdata[7]),
+       .CH1_FF_RX_D_7(n62_1),
+       .CH0_FF_RX_D_8(rx_k[0]),
+       .CH1_FF_RX_D_8(n63_1),
+       .CH0_FF_RX_D_9(rx_disp_err[0]),
+       .CH1_FF_RX_D_9(n64_1),
+       .CH0_FF_RX_D_10(rx_cv_err[0]),
+       .CH1_FF_RX_D_10(n65_1),
+       .CH0_FF_RX_D_11(n10_1),
+       .CH1_FF_RX_D_11(n66_1),
+       .CH0_FF_RX_D_12(n67_1),
+       .CH1_FF_RX_D_12(n68_1),
+       .CH0_FF_RX_D_13(n69_1),
+       .CH1_FF_RX_D_13(n70_1),
+       .CH0_FF_RX_D_14(n71_1),
+       .CH1_FF_RX_D_14(n72_1),
+       .CH0_FF_RX_D_15(n73_1),
+       .CH1_FF_RX_D_15(n74_1),
+       .CH0_FF_RX_D_16(n75_1),
+       .CH1_FF_RX_D_16(n76_1),
+       .CH0_FF_RX_D_17(n77_1),
+       .CH1_FF_RX_D_17(n78_1),
+       .CH0_FF_RX_D_18(n79_1),
+       .CH1_FF_RX_D_18(n80_1),
+       .CH0_FF_RX_D_19(n81_1),
+       .CH1_FF_RX_D_19(n82_1),
+       .CH0_FF_RX_D_20(n83_1),
+       .CH1_FF_RX_D_20(n84_1),
+       .CH0_FF_RX_D_21(n85_1),
+       .CH1_FF_RX_D_21(n86_1),
+       .CH0_FF_RX_D_22(n87_1),
+       .CH1_FF_RX_D_22(n88_1),
+       .CH0_FF_RX_D_23(n11_1),
+       .CH1_FF_RX_D_23(n89_1),
+       .CH0_FFS_PCIE_DONE(n12_1),
+       .CH1_FFS_PCIE_DONE(n90_1),
+       .CH0_FFS_PCIE_CON(n13_1),
+       .CH1_FFS_PCIE_CON(n91_1),
+       .CH0_FFS_RLOS(rx_los_low_s),
+       .CH1_FFS_RLOS(n92_1),
+       .CH0_FFS_LS_SYNC_STATUS(lsm_status_s),
+       .CH1_FFS_LS_SYNC_STATUS(n93_1),
+       .CH0_FFS_CC_UNDERRUN(ctc_urun_s),
+       .CH1_FFS_CC_UNDERRUN(n94_1),
+       .CH0_FFS_CC_OVERRUN(ctc_orun_s),
+       .CH1_FFS_CC_OVERRUN(n95_1),
+       .CH0_FFS_RXFBFIFO_ERROR(n14_1),
+       .CH1_FFS_RXFBFIFO_ERROR(n96_1),
+       .CH0_FFS_TXFBFIFO_ERROR(n15_1),
+       .CH1_FFS_TXFBFIFO_ERROR(n97_1),
+       .CH0_FFS_RLOL(rx_cdr_lol_s),
+       .CH1_FFS_RLOL(n98_1),
+       .CH0_FFS_SKP_ADDED(ctc_ins_s),
+       .CH1_FFS_SKP_ADDED(n99_1),
+       .CH0_FFS_SKP_DELETED(ctc_del_s),
+       .CH1_FFS_SKP_DELETED(n100_1),
+       .CH0_LDR_RX2CORE(n101_1),
+       .CH1_LDR_RX2CORE(n112_1),
+       .D_SCIRDATA0(sci_rddata[0]),
+       .D_SCIRDATA1(sci_rddata[1]),
+       .D_SCIRDATA2(sci_rddata[2]),
+       .D_SCIRDATA3(sci_rddata[3]),
+       .D_SCIRDATA4(sci_rddata[4]),
+       .D_SCIRDATA5(sci_rddata[5]),
+       .D_SCIRDATA6(sci_rddata[6]),
+       .D_SCIRDATA7(sci_rddata[7]),
+       .D_SCIINT(sci_int),
+       .D_SCAN_OUT_0(n16_1),
+       .D_SCAN_OUT_1(n17_1),
+       .D_SCAN_OUT_2(n18_1),
+       .D_SCAN_OUT_3(n19_1),
+       .D_SCAN_OUT_4(n20_1),
+       .D_SCAN_OUT_5(n21_1),
+       .D_SCAN_OUT_6(n22_1),
+       .D_SCAN_OUT_7(n23_1),
+       .D_COUT0(n24_1),
+       .D_COUT1(n25_1),
+       .D_COUT2(n26_1),
+       .D_COUT3(n27_1),
+       .D_COUT4(n28_1),
+       .D_COUT5(n29_1),
+       .D_COUT6(n30_1),
+       .D_COUT7(n31_1),
+       .D_COUT8(n32_1),
+       .D_COUT9(n33_1),
+       .D_COUT10(n34_1),
+       .D_COUT11(n35_1),
+       .D_COUT12(n36_1),
+       .D_COUT13(n37_1),
+       .D_COUT14(n38_1),
+       .D_COUT15(n39_1),
+       .D_COUT16(n40_1),
+       .D_COUT17(n41_1),
+       .D_COUT18(n42_1),
+       .D_COUT19(n43_1),
+       .D_REFCLKI(pll_refclki),
+       .D_FFS_PLOL(n46_1)
+);
+defparam DCU0_inst.D_MACROPDB = "0b1";
+defparam DCU0_inst.D_IB_PWDNB = "0b1";
+defparam DCU0_inst.D_XGE_MODE = "0b0";
+defparam DCU0_inst.D_LOW_MARK = "0d4";
+defparam DCU0_inst.D_HIGH_MARK = "0d12";
+defparam DCU0_inst.D_BUS8BIT_SEL = "0b0";
+defparam DCU0_inst.D_CDR_LOL_SET = "0b00";
+defparam DCU0_inst.D_BITCLK_LOCAL_EN = "0b1";
+defparam DCU0_inst.D_BITCLK_ND_EN = "0b0";
+defparam DCU0_inst.D_BITCLK_FROM_ND_EN = "0b0";
+defparam DCU0_inst.D_SYNC_LOCAL_EN = "0b1";
+defparam DCU0_inst.D_SYNC_ND_EN = "0b0";
+defparam DCU0_inst.CH0_UC_MODE = "0b0";
+defparam DCU0_inst.CH0_PCIE_MODE = "0b0";
+defparam DCU0_inst.CH0_RIO_MODE = "0b0";
+defparam DCU0_inst.CH0_WA_MODE = "0b0";
+defparam DCU0_inst.CH0_INVERT_RX = "0b0";
+defparam DCU0_inst.CH0_INVERT_TX = "0b0";
+defparam DCU0_inst.CH0_PRBS_SELECTION = "0b0";
+defparam DCU0_inst.CH0_GE_AN_ENABLE = "0b0";
+defparam DCU0_inst.CH0_PRBS_LOCK = "0b0";
+defparam DCU0_inst.CH0_PRBS_ENABLE = "0b0";
+defparam DCU0_inst.CH0_ENABLE_CG_ALIGN = "0b1";
+defparam DCU0_inst.CH0_TX_GEAR_MODE = "0b0";
+defparam DCU0_inst.CH0_RX_GEAR_MODE = "0b0";
+defparam DCU0_inst.CH0_PCS_DET_TIME_SEL = "0b00";
+defparam DCU0_inst.CH0_PCIE_EI_EN = "0b0";
+defparam DCU0_inst.CH0_TX_GEAR_BYPASS = "0b0";
+defparam DCU0_inst.CH0_ENC_BYPASS = "0b0";
+defparam DCU0_inst.CH0_SB_BYPASS = "0b0";
+defparam DCU0_inst.CH0_RX_SB_BYPASS = "0b0";
+defparam DCU0_inst.CH0_WA_BYPASS = "0b0";
+defparam DCU0_inst.CH0_DEC_BYPASS = "0b0";
+defparam DCU0_inst.CH0_CTC_BYPASS = "0b0";
+defparam DCU0_inst.CH0_RX_GEAR_BYPASS = "0b0";
+defparam DCU0_inst.CH0_LSM_DISABLE = "0b0";
+defparam DCU0_inst.CH0_MATCH_2_ENABLE = "0b1";
+defparam DCU0_inst.CH0_MATCH_4_ENABLE = "0b0";
+defparam DCU0_inst.CH0_MIN_IPG_CNT = "0b11";
+defparam DCU0_inst.CH0_CC_MATCH_1 = "0x000";
+defparam DCU0_inst.CH0_CC_MATCH_2 = "0x000";
+defparam DCU0_inst.CH0_CC_MATCH_3 = "0x1BC";
+defparam DCU0_inst.CH0_CC_MATCH_4 = "0x050";
+defparam DCU0_inst.CH0_UDF_COMMA_MASK = "0x3ff";
+defparam DCU0_inst.CH0_UDF_COMMA_A = "0x283";
+defparam DCU0_inst.CH0_UDF_COMMA_B = "0x17C";
+defparam DCU0_inst.CH0_RX_DCO_CK_DIV = "0b010";
+defparam DCU0_inst.CH0_RCV_DCC_EN = "0b0";
+defparam DCU0_inst.CH0_REQ_LVL_SET = "0b00";
+defparam DCU0_inst.CH0_REQ_EN = "0b1";
+defparam DCU0_inst.CH0_RTERM_RX = "0d22";
+defparam DCU0_inst.CH0_PDEN_SEL = "0b1";
+defparam DCU0_inst.CH0_LDR_RX2CORE_SEL = "0b0";
+defparam DCU0_inst.CH0_LDR_CORE2TX_SEL = "0b0";
+defparam DCU0_inst.CH0_TPWDNB = "0b1";
+defparam DCU0_inst.CH0_RATE_MODE_TX = "0b0";
+defparam DCU0_inst.CH0_RTERM_TX = "0d19";
+defparam DCU0_inst.CH0_TX_CM_SEL = "0b00";
+defparam DCU0_inst.CH0_TDRV_PRE_EN = "0b0";
+defparam DCU0_inst.CH0_TDRV_SLICE0_SEL = "0b01";
+defparam DCU0_inst.CH0_TDRV_SLICE1_SEL = "0b00";
+defparam DCU0_inst.CH0_TDRV_SLICE2_SEL = "0b01";
+defparam DCU0_inst.CH0_TDRV_SLICE3_SEL = "0b01";
+defparam DCU0_inst.CH0_TDRV_SLICE4_SEL = "0b01";
+defparam DCU0_inst.CH0_TDRV_SLICE5_SEL = "0b01";
+defparam DCU0_inst.CH0_TDRV_SLICE0_CUR = "0b101";
+defparam DCU0_inst.CH0_TDRV_SLICE1_CUR = "0b000";
+defparam DCU0_inst.CH0_TDRV_SLICE2_CUR = "0b11";
+defparam DCU0_inst.CH0_TDRV_SLICE3_CUR = "0b11";
+defparam DCU0_inst.CH0_TDRV_SLICE4_CUR = "0b11";
+defparam DCU0_inst.CH0_TDRV_SLICE5_CUR = "0b00";
+defparam DCU0_inst.CH0_TDRV_DAT_SEL = "0b00";
+defparam DCU0_inst.CH0_TX_DIV11_SEL = "0b0";
+defparam DCU0_inst.CH0_RPWDNB = "0b1";
+defparam DCU0_inst.CH0_RATE_MODE_RX = "0b0";
+defparam DCU0_inst.CH0_RLOS_SEL = "0b1";
+defparam DCU0_inst.CH0_RX_LOS_LVL = "0b010";
+defparam DCU0_inst.CH0_RX_LOS_CEQ = "0b11";
+defparam DCU0_inst.CH0_RX_LOS_HYST_EN = "0b0";
+defparam DCU0_inst.CH0_RX_LOS_EN = "0b1";
+defparam DCU0_inst.CH0_RX_DIV11_SEL = "0b0";
+defparam DCU0_inst.CH0_SEL_SD_RX_CLK = "0b0";
+defparam DCU0_inst.CH0_FF_RX_H_CLK_EN = "0b0";
+defparam DCU0_inst.CH0_FF_RX_F_CLK_DIS = "0b0";
+defparam DCU0_inst.CH0_FF_TX_H_CLK_EN = "0b0";
+defparam DCU0_inst.CH0_FF_TX_F_CLK_DIS = "0b0";
+defparam DCU0_inst.CH0_RX_RATE_SEL = "0d8";
+defparam DCU0_inst.CH0_TDRV_POST_EN = "0b0";
+defparam DCU0_inst.CH0_TX_POST_SIGN = "0b0";
+defparam DCU0_inst.CH0_TX_PRE_SIGN = "0b0";
+defparam DCU0_inst.CH0_RXTERM_CM = "0b11";
+defparam DCU0_inst.CH0_RXIN_CM = "0b11";
+defparam DCU0_inst.CH0_LEQ_OFFSET_SEL = "0b0";
+defparam DCU0_inst.CH0_LEQ_OFFSET_TRIM = "0b000";
+defparam DCU0_inst.D_TX_MAX_RATE = "1.25";
+defparam DCU0_inst.CH0_CDR_MAX_RATE = "1.25";
+defparam DCU0_inst.CH0_TXAMPLITUDE = "0d1100";
+defparam DCU0_inst.CH0_TXDEPRE = "DISABLED";
+defparam DCU0_inst.CH0_TXDEPOST = "DISABLED";
+defparam DCU0_inst.CH0_PROTOCOL = "GBE";
+defparam DCU0_inst.D_ISETLOS = "0d0";
+defparam DCU0_inst.D_SETIRPOLY_AUX = "0b00";
+defparam DCU0_inst.D_SETICONST_AUX = "0b00";
+defparam DCU0_inst.D_SETIRPOLY_CH = "0b00";
+defparam DCU0_inst.D_SETICONST_CH = "0b00";
+defparam DCU0_inst.D_REQ_ISET = "0b000";
+defparam DCU0_inst.D_PD_ISET = "0b00";
+defparam DCU0_inst.D_DCO_CALIB_TIME_SEL = "0b00";
+defparam DCU0_inst.CH0_DCOCTLGI = "0b010";
+defparam DCU0_inst.CH0_DCOATDDLY = "0b00";
+defparam DCU0_inst.CH0_DCOATDCFG = "0b00";
+defparam DCU0_inst.CH0_DCOBYPSATD = "0b1";
+defparam DCU0_inst.CH0_DCOSCALEI = "0b00";
+defparam DCU0_inst.CH0_DCOITUNE4LSB = "0b111";
+defparam DCU0_inst.CH0_DCOIOSTUNE = "0b000";
+defparam DCU0_inst.CH0_DCODISBDAVOID = "0b0";
+defparam DCU0_inst.CH0_DCOCALDIV = "0b001";
+defparam DCU0_inst.CH0_DCONUOFLSB = "0b101";
+defparam DCU0_inst.CH0_DCOIUPDNX2 = "0b1";
+defparam DCU0_inst.CH0_DCOSTEP = "0b00";
+defparam DCU0_inst.CH0_DCOSTARTVAL = "0b000";
+defparam DCU0_inst.CH0_DCOFLTDAC = "0b01";
+defparam DCU0_inst.CH0_DCOITUNE = "0b00";
+defparam DCU0_inst.CH0_DCOFTNRG = "0b110";
+defparam DCU0_inst.CH0_CDR_CNT4SEL = "0b00";
+defparam DCU0_inst.CH0_CDR_CNT8SEL = "0b00";
+defparam DCU0_inst.CH0_BAND_THRESHOLD = "0d0";
+defparam DCU0_inst.CH0_AUTO_FACQ_EN = "0b1";
+defparam DCU0_inst.CH0_AUTO_CALIB_EN = "0b1";
+defparam DCU0_inst.CH0_CALIB_CK_MODE = "0b0";
+defparam DCU0_inst.CH0_REG_BAND_OFFSET = "0d0";
+defparam DCU0_inst.CH0_REG_BAND_SEL = "0d0";
+defparam DCU0_inst.CH0_REG_IDAC_SEL = "0d0";
+defparam DCU0_inst.CH0_REG_IDAC_EN = "0b0";
+defparam DCU0_inst.D_TXPLL_PWDNB = "0b1";
+defparam DCU0_inst.D_SETPLLRC = "0d1";
+defparam DCU0_inst.D_REFCK_MODE = "0b001";
+defparam DCU0_inst.D_TX_VCO_CK_DIV = "0b010";
+defparam DCU0_inst.D_PLL_LOL_SET = "0b00";
+defparam DCU0_inst.D_RG_EN = "0b0";
+defparam DCU0_inst.D_RG_SET = "0b00";
+defparam DCU0_inst.D_CMUSETISCL4VCO = "0b000";
+defparam DCU0_inst.D_CMUSETI4VCO = "0b00";
+defparam DCU0_inst.D_CMUSETINITVCT = "0b00";
+defparam DCU0_inst.D_CMUSETZGM = "0b000";
+defparam DCU0_inst.D_CMUSETP2AGM = "0b000";
+defparam DCU0_inst.D_CMUSETP1GM = "0b000";
+defparam DCU0_inst.D_CMUSETI4CPZ = "0d3";
+defparam DCU0_inst.D_CMUSETI4CPP = "0d3";
+defparam DCU0_inst.D_CMUSETICP4Z = "0b101";
+defparam DCU0_inst.D_CMUSETICP4P = "0b01";
+defparam DCU0_inst.D_CMUSETBIASI = "0b00";
+// @8:424
+  sgmii_ecp5sll_core_Z1_layer1 sll_inst (
+       .tx_pclk(tx_pclk),
+       .sli_rst(sli_rst),
+       .pll_refclki(pll_refclki),
+       .pll_lock_i(pll_lol)
+);
+// @8:394
+  sgmii_ecp5rsl_core_Z2_layer1 rsl_inst (
+       .rx_pcs_rst_c(rx_pcs_rst_c),
+       .tx_pcs_rst_c(tx_pcs_rst_c),
+       .tx_serdes_rst_c(tx_serdes_rst_c),
+       .serdes_rst_dual_c(serdes_rst_dual_c),
+       .rsl_tx_pcs_rst_c(rsl_tx_pcs_rst_c),
+       .rsl_rx_serdes_rst_c(rsl_rx_serdes_rst_c),
+       .rsl_serdes_rst_dual_c(rsl_serdes_rst_dual_c),
+       .rsl_tx_serdes_rst_c(rsl_tx_serdes_rst_c),
+       .rsl_tx_rdy(rsl_tx_rdy),
+       .pll_lock_i(pll_lol),
+       .pll_refclki(pll_refclki),
+       .rsl_rx_rdy(rsl_rx_rdy),
+       .rsl_rst(rsl_rst),
+       .rxrefclk(rxrefclk),
+       .rsl_disable(rsl_disable),
+       .rx_serdes_rst_c(rx_serdes_rst_c),
+       .rsl_rx_pcs_rst_c(rsl_rx_pcs_rst_c),
+       .rst_dual_c(rst_dual_c),
+       .rx_cdr_lol_s(rx_cdr_lol_s),
+       .rx_los_low_s(rx_los_low_s)
+);
+endmodule /* sgmii_ecp5 */
+

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_cck.rpt.db b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_cck.rpt.db
new file mode 100644 (file)
index 0000000..029fa7a
Binary files /dev/null and b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_cck.rpt.db differ

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt.db b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt.db
new file mode 100644 (file)
index 0000000..029fa7a
Binary files /dev/null and b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt.db differ

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_synplify.lpf b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_synplify.lpf
new file mode 100644 (file)
index 0000000..9cbac38
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_synplify.lpf
@@ -0,0 +1,29 @@
+#
+# Logical Preferences generated for Lattice by Synplify maplat, Build 1796R.
+#
+
+# Period Constraints 
+#FREQUENCY PORT "pll_refclki" 100.0 MHz;
+#FREQUENCY PORT "rxrefclk" 100.0 MHz;
+#FREQUENCY NET "tx_pclk" 100.0 MHz;
+
+
+# Output Constraints 
+
+# Input Constraints 
+
+# Point-to-point Delay Constraints 
+
+
+
+# Block Path Constraints 
+#BLOCK PATH FROM CLKNET "tx_pclk" TO CLKNET "rxrefclk";
+#BLOCK PATH FROM CLKNET "tx_pclk" TO CLKNET "pll_refclki";
+#BLOCK PATH FROM CLKNET "rxrefclk" TO CLKNET "tx_pclk";
+#BLOCK PATH FROM CLKNET "rxrefclk" TO CLKNET "pll_refclki";
+#BLOCK PATH FROM CLKNET "pll_refclki" TO CLKNET "tx_pclk";
+#BLOCK PATH FROM CLKNET "pll_refclki" TO CLKNET "rxrefclk";
+
+BLOCK ASYNCPATHS;
+
+# End of generated Logical Preferences.

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_synplify_tmp2.lpf b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_synplify_tmp2.lpf
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_synplify_tmp4.lpf b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_synplify_tmp4.lpf
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_synplify_tmp8.lpf b/gbe/cores/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_synplify_tmp8.lpf
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/layer0.tlg.rptmap b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/layer0.tlg.rptmap
new file mode 100644 (file)
index 0000000..3910cac
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/layer0.tlg.rptmap
@@ -0,0 +1 @@
+./synwork/layer0.tlg,layer0.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages.

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/layer1.tlg.rptmap b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/layer1.tlg.rptmap
new file mode 100644 (file)
index 0000000..af92e0b
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/layer1.tlg.rptmap
@@ -0,0 +1 @@
+./synwork/layer1.tlg,layer1.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages.

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/linker.rpt.rptmap b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/linker.rpt.rptmap
new file mode 100644 (file)
index 0000000..3793ead
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/linker.rpt.rptmap
@@ -0,0 +1 @@
+./synwork/sgmii_ecp5_comp.linkerlog,linker.rpt,Summary of linker messages for components that did not bind

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/metrics.db b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/metrics.db
new file mode 100644 (file)
index 0000000..f26fd6a
Binary files /dev/null and b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/metrics.db differ

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_notes.txt b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_notes.txt
new file mode 100644 (file)
index 0000000..cf05fac
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_notes.txt
@@ -0,0 +1,16 @@
+@N|Running in 64-bit mode
+@N|Running in 64-bit mode
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
+@N|Running in 64-bit mode
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1.
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work.
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work.
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment.
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment.
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work.
+@N: CL201 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state.
+@N|Running in 64-bit mode
+

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_runstatus.xml b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_runstatus.xml
new file mode 100644 (file)
index 0000000..797309b
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_runstatus.xml
@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the job information from compiler to be displayed as part of the summary report.
+*******************************************************************************************-->
+
+<job_run_status name="compiler"> 
+  <report_link name="Detailed report">
+    <data>/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr</data>
+    <title>Synopsys HDL Compiler</title>
+  </report_link> 
+  <job_status>
+    <data>Completed    </data>
+  </job_status>
+<job_info> 
+                       <info name="Notes">
+  <data>15</data>
+  <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_notes.txt</data></report_link>
+  </info>
+                       <info name="Warnings">
+  <data>76</data>
+  <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt</data></report_link>
+  </info>
+                       <info name="Errors">
+  <data>0</data>
+  <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_errors.txt</data></report_link>
+  </info>
+                       <info name="CPU Time">
+  <data>-</data>
+  </info>
+                       <info name="Real Time">
+  <data>00h:00m:02s</data>
+  </info>
+                       <info name="Peak Memory">
+  <data>-</data>
+  </info>
+                       <info name="Date &amp;Time">
+  <data type="timestamp">1557471731</data>
+  </info>
+                       </job_info>
+</job_run_status>
\ No newline at end of file

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt
new file mode 100644 (file)
index 0000000..d386b26
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt
@@ -0,0 +1,77 @@
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers.
+

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_area_report.xml b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_area_report.xml
new file mode 100644 (file)
index 0000000..8733c9b
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_area_report.xml
@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the area information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<report_table display_priority="1" name="Area Summary">
+<report_link name="Detailed report">
+<data>/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_resourceusage.rpt</data>
+<title>Resource Usage</title>
+</report_link>
+<parameter tooltip="Total Register bits used" name="Register bits">
+<data>221</data>
+</parameter>
+<parameter tooltip="Total I/O cells used" name="I/O cells">
+<data>0</data>
+</parameter>
+<parameter tcl_name="v_ram" tooltip="Total Block RAMs used" name="Block RAMs">
+<data>0</data>
+</parameter>
+<parameter tcl_name="dsp_used" tooltip="Total DSPs used" name="DSPs">
+<data>0</data>
+</parameter>
+<parameter tcl_name="total_luts" tooltip="Total ORCA LUTs used" name="ORCA LUTs">
+<data>154</data>
+</parameter>
+</report_table>

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_errors.txt b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_errors.txt
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt
new file mode 100644 (file)
index 0000000..d8e3e2c
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt
@@ -0,0 +1,22 @@
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+@N: MO225 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":909:3:909:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":527:3:527:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] 
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.edn
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_opt_report.xml b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_opt_report.xml
new file mode 100644 (file)
index 0000000..c6da126
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_opt_report.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the optimization information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<report_table display_priority="3" name="Optimizations Summary">
+<parameter tooltip="Non-gated/non-generated clock trees / Gated/generated clock trees" name="Combined Clock Conversion">
+<data>3 / 0</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_combined_clk.rpt</data>
+<title>START OF CLOCK OPTIMIZATION REPORT</title>
+</report_link>
+</parameter>
+</report_table>

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_runstatus.xml b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_runstatus.xml
new file mode 100644 (file)
index 0000000..05527dc
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_runstatus.xml
@@ -0,0 +1,46 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the job information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<job_run_status name="Mapper">
+<report_link name="Detailed report">
+<data>/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr</data>
+<title>Synopsys Lattice Technology Mapper</title>
+</report_link>
+<job_status>
+<data>Completed</data>
+</job_status>
+<job_info>
+<info name="Notes">
+<data>22</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt</data>
+</report_link>
+</info>
+<info name="Warnings">
+<data>4</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt</data>
+</report_link>
+</info>
+<info name="Errors">
+<data>0</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_errors.txt</data>
+</report_link>
+</info>
+<info name="CPU Time">
+<data>0h:00m:03s</data>
+</info>
+<info name="Real Time">
+<data>0h:00m:03s</data>
+</info>
+<info name="Peak Memory">
+<data>153MB</data>
+</info>
+<info name="Date &amp; Time">
+<data type="timestamp">1557471736</data>
+</info>
+</job_info>
+</job_run_status>

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_timing_report.xml b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_timing_report.xml
new file mode 100644 (file)
index 0000000..8f866cb
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_timing_report.xml
@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+Max Top 5 critical clocks will be reported. For rest user needs to refer to Detailed report
+*******************************************************************************************-->
+<report_table display_priority="2" name="Timing Summary">
+<report_link name="Detailed report">
+<data>/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr</data>
+<title>START OF TIMING REPORT</title>
+</report_link>
+<row>
+<data tcl_name="clock_name">Clock Name</data>
+<data tcl_name="req_freq">Req Freq</data>
+<data tcl_name="est_freq">Est Freq</data>
+<data tcl_name="slack">Slack</data>
+</row>
+<row>
+<data>sgmii_ecp5|pll_refclki</data>
+<data>100.0 MHz</data>
+<data>168.9 MHz</data>
+<data>4.079</data>
+</row>
+<row>
+<data>sgmii_ecp5|rxrefclk</data>
+<data>100.0 MHz</data>
+<data>167.9 MHz</data>
+<data>4.043</data>
+</row>
+<row>
+<data>sgmii_ecp5|tx_pclk_inferred_clock</data>
+<data>100.0 MHz</data>
+<data>237.5 MHz</data>
+<data>5.789</data>
+</row>
+<row>
+<data>System</data>
+<data>100.0 MHz</data>
+<data>840.7 MHz</data>
+<data>8.810</data>
+</row>
+</report_table>

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt
new file mode 100644 (file)
index 0000000..6170ebf
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt
@@ -0,0 +1,4 @@
+@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":162:4:162:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"
+@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"
+@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk"

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_errors.txt b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_errors.txt
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt
new file mode 100644 (file)
index 0000000..bd89dbb
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt
@@ -0,0 +1,9 @@
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+@N: BN362 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances.
+@N: MO225 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_runstatus.xml b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_runstatus.xml
new file mode 100644 (file)
index 0000000..3878c1e
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_runstatus.xml
@@ -0,0 +1,46 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the job information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<job_run_status name="Mapper">
+<report_link name="Detailed report">
+<data>/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr</data>
+<title>Synopsys Lattice Technology Pre-mapping</title>
+</report_link>
+<job_status>
+<data>Completed</data>
+</job_status>
+<job_info>
+<info name="Notes">
+<data>9</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt</data>
+</report_link>
+</info>
+<info name="Warnings">
+<data>3</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt</data>
+</report_link>
+</info>
+<info name="Errors">
+<data>0</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_errors.txt</data>
+</report_link>
+</info>
+<info name="CPU Time">
+<data>0h:00m:00s</data>
+</info>
+<info name="Real Time">
+<data>0h:00m:00s</data>
+</info>
+<info name="Peak Memory">
+<data>144MB</data>
+</info>
+<info name="Date &amp; Time">
+<data type="timestamp">1557471733</data>
+</info>
+</job_info>
+</job_run_status>

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt
new file mode 100644 (file)
index 0000000..3044eef
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt
@@ -0,0 +1,3 @@
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr
new file mode 100644 (file)
index 0000000..5d31417
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr
@@ -0,0 +1,357 @@
+Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
+VHDL syntax check successful!
+File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd changed - recompiling
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Fri May 10 09:02:09 2019
+
+###########################################################]
+Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
+Verilog syntax check successful!
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Fri May 10 09:02:10 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
+File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd changed - recompiling
+File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling
+VHDL syntax check successful!
+File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd changed - recompiling
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1.
+Post processing for work.sgmii_ecp5.v1
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB)
+
+
+Process completed successfully.
+# Fri May 10 09:02:10 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
+Verilog syntax check successful!
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work.
+
+       PDATA_RST_VAL=32'b00000000000000000000000000000000
+   Generated name = sync_0s
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work.
+
+       PPROTOCOL=24'b010001110100001001000101
+       PLOL_SETTING=32'b00000000000000000000000000000000
+       PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100
+       PPCIE_MAX_RATE=24'b001100100010111000110101
+       PDIFF_VAL_LOCK=32'b00000000000000000000000000100111
+       PDIFF_VAL_UNLOCK=32'b00000000000000000000000001001110
+       PPCLK_TC=32'b00000000000000100000000000000000
+       PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000
+       PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000
+       PPCLK_DIV11_TC=32'b00000000000000000000000000000000
+       LPLL_LOSS_ST=2'b00
+       LPLL_PRELOSS_ST=2'b01
+       LPLL_PRELOCK_ST=2'b10
+       LPLL_LOCK_ST=2'b11
+       LRCLK_TC=16'b1111111111111111
+       LRCLK_TC_PUL_WIDTH=16'b0000000000110010
+       LHB_WAIT_CNT=8'b11111111
+       LPCLK_TC_0=32'b00000000000000001000000000000000
+       LPCLK_TC_1=32'b00000000000000010000000000000000
+       LPCLK_TC_2=32'b00000000000000100000000000000000
+       LPCLK_TC_3=32'b00000000000000101000000000000000
+       LPCLK_TC_4=32'b00000000000000010000000000000000
+       LPDIFF_LOCK_00=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_10=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_20=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_30=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_40=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_01=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_11=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_21=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_31=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_41=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_02=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_12=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_22=32'b00000000000000000000000011000100
+       LPDIFF_LOCK_32=32'b00000000000000000000000011110101
+       LPDIFF_LOCK_42=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_03=32'b00000000000000000000000010000011
+       LPDIFF_LOCK_13=32'b00000000000000000000000100000110
+       LPDIFF_LOCK_23=32'b00000000000000000000001000001100
+       LPDIFF_LOCK_33=32'b00000000000000000000001010001111
+       LPDIFF_LOCK_43=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011
+       LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110
+       LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010
+       LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001
+       LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111
+       LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000
+       LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000
+       LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000
+       LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100
+       LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001
+       LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010
+       LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111
+       LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001
+   Generated name = sgmii_ecp5sll_core_Z1_layer1
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment.
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work.
+
+       pnum_channels=32'b00000000000000000000000000000001
+       pprotocol=24'b010001110100001001000101
+       pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
+       pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_tx_rdy=32'b00000000000000000000101110111000
+       pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_rx_rdy=32'b00000000000000000000101110111000
+       wa_num_cycles=32'b00000000000000000000010000000000
+       dac_num_cycles=32'b00000000000000000000000000000011
+       lreset_pwidth=32'b00000000000000000000000000000011
+       lwait_b4_trst=32'b00000000000010111110101111000010
+       lwait_b4_trst_s=32'b00000000000000000000001100001101
+       lplol_cnt_width=32'b00000000000000000000000000010100
+       lwait_after_plol0=32'b00000000000000000000000000000100
+       lwait_b4_rrst=32'b00000000000000101100000000000000
+       lrrst_wait_width=32'b00000000000000000000000000010100
+       lwait_after_rrst=32'b00000000000011000011010100000000
+       lwait_b4_rrst_s=32'b00000000000000000000000111001100
+       lrlol_cnt_width=32'b00000000000000000000000000010011
+       lwait_after_lols=32'b00000000000000001100010000000000
+       lwait_after_lols_s=32'b00000000000000000000000010010110
+       llols_cnt_width=32'b00000000000000000000000000010010
+       lrdb_max=32'b00000000000000000000000000001111
+       ltxr_wait_width=32'b00000000000000000000000000001100
+       lrxr_wait_width=32'b00000000000000000000000000001100
+   Generated name = sgmii_ecp5rsl_core_Z2_layer1
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers.
+@N: CL201 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state.
+Extracted state machine for register sll_state
+State machine has 4 reachable states with original encodings of:
+   00
+   01
+   10
+   11
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB)
+
+
+Process completed successfully.
+# Fri May 10 09:02:10 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/layer0.srs changed - recompiling
+File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/layer1.srs changed - recompiling
+
+=======================================================================================
+For a summary of linker messages for components that did not bind, please see log file:
+@L: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.linkerlog
+=======================================================================================
+
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 09:02:11 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 09:02:11 2019
+
+###########################################################]

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr.db b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr.db
new file mode 100644 (file)
index 0000000..a986936
Binary files /dev/null and b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr.db differ

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr.rptmap b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr.rptmap
new file mode 100644 (file)
index 0000000..14937c8
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr.rptmap
@@ -0,0 +1 @@
+./synlog/sgmii_ecp5_compiler.srr,sgmii_ecp5_compiler.srr,Compile Log

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr
new file mode 100644 (file)
index 0000000..41be052
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr
@@ -0,0 +1,673 @@
+# Fri May 10 09:02:13 2019
+
+Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   10 -> 10
+   11 -> 11
+@N: MO225 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":909:3:909:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":527:3:527:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] 
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 145MB)
+
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+   1           0h:00m:01s                   4.90ns              155 /       221
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+3 non-gated/non-generated clock tree(s) driving 221 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+============================================= Non-Gated/Non-Generated Clocks =============================================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                                   
+--------------------------------------------------------------------------------------------------------------------------
+@K:CKID0001       pll_refclki         port                   91         rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]
+@K:CKID0002       rxrefclk            port                   77         rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]
+@K:CKID0003       DCU0_inst           DCUA                   53         sll_inst.pcount[21]                               
+==========================================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 149MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 149MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.edn
+M-2017.03L-SP1-1
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 152MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 152MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+@W: MT246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":162:4:162:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"
+@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"
+@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk"
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Fri May 10 09:02:16 2019
+#
+
+
+Top view:               sgmii_ecp5
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.fdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 4.043
+
+                                      Requested     Estimated     Requested     Estimated               Clock        Clock              
+Starting Clock                        Frequency     Frequency     Period        Period        Slack     Type         Group              
+----------------------------------------------------------------------------------------------------------------------------------------
+sgmii_ecp5|pll_refclki                100.0 MHz     168.9 MHz     10.000        5.921         4.079     inferred     Inferred_clkgroup_0
+sgmii_ecp5|rxrefclk                   100.0 MHz     167.9 MHz     10.000        5.957         4.043     inferred     Inferred_clkgroup_1
+sgmii_ecp5|tx_pclk_inferred_clock     100.0 MHz     237.5 MHz     10.000        4.211         5.789     inferred     Inferred_clkgroup_2
+System                                100.0 MHz     840.7 MHz     10.000        1.190         8.810     system       system_clkgroup    
+========================================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                                                                |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+Starting                           Ending                             |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+System                             sgmii_ecp5|rxrefclk                |  10.000      8.811  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             System                             |  10.000      8.253  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             sgmii_ecp5|pll_refclki             |  10.000      4.079  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             sgmii_ecp5|tx_pclk_inferred_clock  |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|rxrefclk                System                             |  10.000      8.277  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|rxrefclk                sgmii_ecp5|rxrefclk                |  10.000      4.043  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|tx_pclk_inferred_clock  sgmii_ecp5|pll_refclki             |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|tx_pclk_inferred_clock  sgmii_ecp5|tx_pclk_inferred_clock  |  10.000      5.789  |  No paths    -      |  No paths    -      |  No paths    -    
+============================================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|pll_refclki
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                   Starting                                                        Arrival          
+Instance                           Reference                  Type        Pin     Net              Time        Slack
+                                   Clock                                                                            
+--------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[2]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[2]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[3]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[3]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[17]     sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[17]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[19]     sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[19]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[1]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[1]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[4]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[4]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[5]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[5]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[6]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[6]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[7]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[7]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[8]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[8]      0.907       4.684
+====================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                   Starting                                                          Required          
+Instance                           Reference                  Type        Pin     Net                Time         Slack
+                                   Clock                                                                               
+-----------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[19]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[19]     9.946        4.079
+rsl_inst.genblk1\.plol_cnt[17]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[17]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[18]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[18]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[15]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[15]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[16]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[16]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[13]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[13]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[14]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[14]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[11]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[11]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[12]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[12]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[9]      sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[9]      9.946        4.383
+=======================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.867
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.079
+
+    Number of logic level(s):                15
+    Starting point:                          rsl_inst.genblk1\.plol_cnt[2] / Q
+    Ending point:                            rsl_inst.genblk1\.plol_cnt[19] / D
+    The start point is clocked by            sgmii_ecp5|pll_refclki [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|pll_refclki [rising] on pin CK
+
+Instance / Net                                        Pin      Pin               Arrival     No. of    
+Name                                     Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[2]            FD1S3DX      Q        Out     0.907     0.907       -         
+plol_cnt[2]                              Net          -        -       -         -           2         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     Z        Out     0.606     1.513       -         
+un1_plol_cnt_tc_10                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     Z        Out     0.606     2.119       -         
+un1_plol_cnt_tc_14                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     Z        Out     0.762     2.881       -         
+un1_plol_cnt_tc                          Net          -        -       -         -           5         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     B        In      0.000     2.881       -         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     Z        Out     0.840     3.721       -         
+plol_cnt                                 Net          -        -       -         -           21        
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.721       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.621       -         
+plol_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.621       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.682       -         
+plol_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.682       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.743       -         
+plol_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.743       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.804       -         
+plol_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.804       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.865       -         
+plol_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.865       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.926       -         
+plol_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.926       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.987       -         
+plol_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.987       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.048       -         
+plol_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.048       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.109       -         
+plol_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.109       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        COUT     Out     0.061     5.170       -         
+plol_cnt_cry[18]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        CIN      In      0.000     5.170       -         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        S0       Out     0.698     5.867       -         
+plol_cnt_s[19]                           Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt[19]           FD1S3DX      D        In      0.000     5.867       -         
+=======================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|rxrefclk
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                    Starting                                                      Arrival          
+Instance                            Reference               Type        Pin     Net               Time        Slack
+                                    Clock                                                                          
+-------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rxs_rst           sgmii_ecp5|rxrefclk     FD1P3DX     Q       rxs_rst           1.015       4.043
+rsl_inst.genblk2\.rlol1_cnt[7]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[7]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[8]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[8]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[9]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[9]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[10]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[10]     0.907       4.136
+rsl_inst.genblk2\.rlols0_cnt[1]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[1]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[2]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[2]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[3]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[3]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[4]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[4]     0.907       4.170
+rsl_inst.genblk2\.rlol1_cnt[0]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[0]      0.907       4.742
+===================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                              Starting                                                         Required          
+Instance                                      Reference               Type        Pin     Net                  Time         Slack
+                                              Clock                                                                              
+---------------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[11]     9.946        4.043
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[9]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[9]      9.946        4.104
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[10]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[10]     9.946        4.104
+rsl_inst.genblk2\.rlol1_cnt[17]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[17]      9.946        4.136
+rsl_inst.genblk2\.rlol1_cnt[18]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[18]      9.946        4.136
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[7]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[7]      9.946        4.165
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[8]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[8]      9.946        4.165
+rsl_inst.genblk2\.rlols0_cnt[17]              sgmii_ecp5|rxrefclk     FD1P3DX     D       rlols0_cnt_s[17]     9.946        4.170
+rsl_inst.genblk2\.rlol1_cnt[15]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[15]      9.946        4.197
+rsl_inst.genblk2\.rlol1_cnt[16]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[16]      9.946        4.197
+=================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.902
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     4.043
+
+    Number of logic level(s):                11
+    Starting point:                          rsl_inst.genblk2\.rxs_rst / Q
+    Ending point:                            rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] / D
+    The start point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+
+Instance / Net                                                  Pin      Pin               Arrival     No. of    
+Name                                               Type         Name     Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rxs_rst                          FD1P3DX      Q        Out     1.015     1.015       -         
+rxs_rst                                            Net          -        -       -         -           6         
+rsl_inst.rdo_rx_serdes_rst_c_1[0]                  ORCALUT4     B        In      0.000     1.015       -         
+rsl_inst.rdo_rx_serdes_rst_c_1[0]                  ORCALUT4     Z        Out     0.708     1.723       -         
+rsl_rx_serdes_rst_c                                Net          -        -       -         -           3         
+rsl_inst.dual_or_rserd_rst                         ORCALUT4     A        In      0.000     1.723       -         
+rsl_inst.dual_or_rserd_rst                         ORCALUT4     Z        Out     0.798     2.521       -         
+dual_or_rserd_rst                                  Net          -        -       -         -           9         
+rsl_inst.rx_any_rst                                ORCALUT4     A        In      0.000     2.521       -         
+rsl_inst.rx_any_rst                                ORCALUT4     Z        Out     0.660     3.181       -         
+rx_any_rst                                         Net          -        -       -         -           2         
+rsl_inst.rx_any_rst_RNIFD021                       ORCALUT4     A        In      0.000     3.181       -         
+rsl_inst.rx_any_rst_RNIFD021                       ORCALUT4     Z        Out     0.819     4.000       -         
+rxr_wt_cnt9                                        Net          -        -       -         -           14        
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0]     CCU2C        A1       In      0.000     4.000       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0]     CCU2C        COUT     Out     0.900     4.900       -         
+rxr_wt_cnt_cry[0]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1]     CCU2C        CIN      In      0.000     4.900       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1]     CCU2C        COUT     Out     0.061     4.961       -         
+rxr_wt_cnt_cry[2]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3]     CCU2C        CIN      In      0.000     4.961       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3]     CCU2C        COUT     Out     0.061     5.022       -         
+rxr_wt_cnt_cry[4]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5]     CCU2C        CIN      In      0.000     5.022       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5]     CCU2C        COUT     Out     0.061     5.083       -         
+rxr_wt_cnt_cry[6]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7]     CCU2C        CIN      In      0.000     5.083       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7]     CCU2C        COUT     Out     0.061     5.144       -         
+rxr_wt_cnt_cry[8]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9]     CCU2C        CIN      In      0.000     5.144       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9]     CCU2C        COUT     Out     0.061     5.205       -         
+rxr_wt_cnt_cry[10]                                 Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11]      CCU2C        CIN      In      0.000     5.205       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11]      CCU2C        S0       Out     0.698     5.902       -         
+rxr_wt_cnt_s[11]                                   Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11]          FD1P3DX      D        In      0.000     5.902       -         
+=================================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|tx_pclk_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                            Starting                                                                   Arrival          
+Instance                    Reference                             Type        Pin     Net              Time        Slack
+                            Clock                                                                                       
+------------------------------------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1       sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p1     1.098       5.789
+sll_inst.ppul_sync_p2       sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p2     1.098       5.789
+sll_inst.pcount_diff[0]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_0      0.985       6.147
+sll_inst.pcount[0]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[0]        0.955       6.178
+sll_inst.pcount_diff[1]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_1      0.955       6.239
+sll_inst.pcount_diff[2]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_2      0.955       6.239
+sll_inst.pcount[1]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[1]        0.907       6.287
+sll_inst.pcount[2]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[2]        0.907       6.287
+sll_inst.pcount_diff[3]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_3      0.955       6.300
+sll_inst.pcount_diff[4]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_4      0.955       6.300
+========================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                             Starting                                                                                  Required          
+Instance                     Reference                             Type        Pin     Net                             Time         Slack
+                             Clock                                                                                                       
+-----------------------------------------------------------------------------------------------------------------------------------------
+sll_inst.pcount[21]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[21]                    9.946        5.789
+sll_inst.pcount[19]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[19]                    9.946        5.850
+sll_inst.pcount[20]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[20]                    9.946        5.850
+sll_inst.pcount[17]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[17]                    9.946        5.911
+sll_inst.pcount[18]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[18]                    9.946        5.911
+sll_inst.pcount[15]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[15]                    9.946        5.972
+sll_inst.pcount[16]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[16]                    9.946        5.972
+sll_inst.pcount[13]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[13]                    9.946        6.033
+sll_inst.pcount[14]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[14]                    9.946        6.033
+sll_inst.pcount_diff[21]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3DX     D       un1_pcount_diff_1_s_21_0_S0     9.946        6.034
+=========================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      4.157
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 5.789
+
+    Number of logic level(s):                13
+    Starting point:                          sll_inst.ppul_sync_p1 / Q
+    Ending point:                            sll_inst.pcount[21] / D
+    The start point is clocked by            sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
+
+Instance / Net                             Pin      Pin               Arrival     No. of    
+Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1         FD1S3DX      Q        Out     1.098     1.098       -         
+ppul_sync_p1                  Net          -        -       -         -           25        
+sll_inst.pcount10_0_o3        ORCALUT4     A        In      0.000     1.098       -         
+sll_inst.pcount10_0_o3        ORCALUT4     Z        Out     0.851     1.950       -         
+N_8                           Net          -        -       -         -           25        
+sll_inst.pcount_cry_0[0]      CCU2C        A1       In      0.000     1.950       -         
+sll_inst.pcount_cry_0[0]      CCU2C        COUT     Out     0.900     2.850       -         
+pcount_cry[0]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[1]      CCU2C        CIN      In      0.000     2.850       -         
+sll_inst.pcount_cry_0[1]      CCU2C        COUT     Out     0.061     2.911       -         
+pcount_cry[2]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[3]      CCU2C        CIN      In      0.000     2.911       -         
+sll_inst.pcount_cry_0[3]      CCU2C        COUT     Out     0.061     2.972       -         
+pcount_cry[4]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[5]      CCU2C        CIN      In      0.000     2.972       -         
+sll_inst.pcount_cry_0[5]      CCU2C        COUT     Out     0.061     3.033       -         
+pcount_cry[6]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[7]      CCU2C        CIN      In      0.000     3.033       -         
+sll_inst.pcount_cry_0[7]      CCU2C        COUT     Out     0.061     3.094       -         
+pcount_cry[8]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[9]      CCU2C        CIN      In      0.000     3.094       -         
+sll_inst.pcount_cry_0[9]      CCU2C        COUT     Out     0.061     3.155       -         
+pcount_cry[10]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[11]     CCU2C        CIN      In      0.000     3.155       -         
+sll_inst.pcount_cry_0[11]     CCU2C        COUT     Out     0.061     3.216       -         
+pcount_cry[12]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[13]     CCU2C        CIN      In      0.000     3.216       -         
+sll_inst.pcount_cry_0[13]     CCU2C        COUT     Out     0.061     3.277       -         
+pcount_cry[14]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[15]     CCU2C        CIN      In      0.000     3.277       -         
+sll_inst.pcount_cry_0[15]     CCU2C        COUT     Out     0.061     3.338       -         
+pcount_cry[16]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[17]     CCU2C        CIN      In      0.000     3.338       -         
+sll_inst.pcount_cry_0[17]     CCU2C        COUT     Out     0.061     3.399       -         
+pcount_cry[18]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[19]     CCU2C        CIN      In      0.000     3.399       -         
+sll_inst.pcount_cry_0[19]     CCU2C        COUT     Out     0.061     3.460       -         
+pcount_cry[20]                Net          -        -       -         -           1         
+sll_inst.pcount_s_0[21]       CCU2C        CIN      In      0.000     3.460       -         
+sll_inst.pcount_s_0[21]       CCU2C        S0       Out     0.698     4.157       -         
+pcount_s[21]                  Net          -        -       -         -           1         
+sll_inst.pcount[21]           FD1S3DX      D        In      0.000     4.157       -         
+============================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                                 Arrival          
+Instance      Reference     Type     Pin              Net              Time        Slack
+              Clock                                                                     
+----------------------------------------------------------------------------------------
+DCU0_inst     System        DCUA     CH0_FFS_RLOL     rx_cdr_lol_s     0.000       8.810
+DCU0_inst     System        DCUA     CH0_FFS_RLOS     rx_los_low_s     0.000       8.810
+========================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                       Starting                                                            Required          
+Instance                                               Reference     Type        Pin     Net                               Time         Slack
+                                                       Clock                                                                                 
+---------------------------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     SP      un2_rdo_serdes_rst_dual_c_2_i     9.806        8.810
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     D       rxpr_appd_RNO[0]                  9.946        9.556
+rsl_inst.genblk2\.rlol_p1                              System        FD1S3DX     D       rx_cdr_lol_s                      9.946        9.946
+rsl_inst.genblk2\.rlos_p1                              System        FD1S3DX     D       rx_los_low_s                      9.946        9.946
+=============================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.194
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.806
+
+    - Propagation time:                      0.996
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 8.810
+
+    Number of logic level(s):                2
+    Starting point:                          DCU0_inst / CH0_FFS_RLOL
+    Ending point:                            rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+
+Instance / Net                                                            Pin              Pin               Arrival     No. of    
+Name                                                         Type         Name             Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------------------------------------------------------
+DCU0_inst                                                    DCUA         CH0_FFS_RLOL     Out     0.000     0.000       -         
+rx_cdr_lol_s                                                 Net          -                -       -         -           4         
+rsl_inst.un2_rdo_serdes_rst_dual_c_1_1                       ORCALUT4     A                In      0.000     0.000       -         
+rsl_inst.un2_rdo_serdes_rst_dual_c_1_1                       ORCALUT4     Z                Out     0.606     0.606       -         
+un2_rdo_serdes_rst_dual_c_1_1                                Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0]     ORCALUT4     B                In      0.000     0.606       -         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0]     ORCALUT4     Z                Out     0.390     0.996       -         
+un2_rdo_serdes_rst_dual_c_2_i                                Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]           FD1P3DX      SP               In      0.000     0.996       -         
+===================================================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 221 of 24288 (1%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+CCU2C:          113
+DCUA:           1
+FD1P3BX:        20
+FD1P3DX:        92
+FD1S3BX:        12
+FD1S3DX:        97
+GSR:            1
+INV:            3
+ORCALUT4:       154
+PFUMX:          2
+PUR:            1
+VHI:            6
+VLO:            6
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 153MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Fri May 10 09:02:16 2019
+
+###########################################################]

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr.db b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr.db
new file mode 100644 (file)
index 0000000..35caf2e
Binary files /dev/null and b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr.db differ

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.szr b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.szr
new file mode 100644 (file)
index 0000000..10f80e0
Binary files /dev/null and b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.szr differ

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.xck b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.xck
new file mode 100644 (file)
index 0000000..eb3488c
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.xck
@@ -0,0 +1,3 @@
+CKID0001:@|S:pll_refclki@|E:rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001 
+CKID0002:@|S:rxrefclk@|E:rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]@|F:@syn_sample_clock_path==CKID0002@|M:ClockId0002 
+CKID0003:@|S:DCU0_inst@|E:sll_inst.pcount[21]@|F:@syn_sample_clock_path==CKID0003@|M:ClockId0003 

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_multi_srs_gen.srr b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_multi_srs_gen.srr
new file mode 100644 (file)
index 0000000..8337c2b
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_multi_srs_gen.srr
@@ -0,0 +1,12 @@
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 09:02:12 2019
+
+###########################################################]

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_multi_srs_gen.srr.db b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_multi_srs_gen.srr.db
new file mode 100644 (file)
index 0000000..029fa7a
Binary files /dev/null and b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_multi_srs_gen.srr.db differ

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr
new file mode 100644 (file)
index 0000000..0a65ebd
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr
@@ -0,0 +1,86 @@
+# Fri May 10 09:02:12 2019
+
+Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.fdc
+@L: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt 
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt" file 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)
+
+@N: BN362 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances.
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist sgmii_ecp5
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+
+Clock Summary
+******************
+
+          Start                                 Requested     Requested     Clock        Clock                   Clock
+Level     Clock                                 Frequency     Period        Type         Group                   Load 
+----------------------------------------------------------------------------------------------------------------------
+0 -       System                                100.0 MHz     10.000        system       system_clkgroup         0    
+                                                                                                                      
+0 -       sgmii_ecp5|pll_refclki                100.0 MHz     10.000        inferred     Inferred_clkgroup_0     93   
+                                                                                                                      
+0 -       sgmii_ecp5|rxrefclk                   100.0 MHz     10.000        inferred     Inferred_clkgroup_1     77   
+                                                                                                                      
+0 -       sgmii_ecp5|tx_pclk_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_2     53   
+======================================================================================================================
+
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   10 -> 10
+   11 -> 11
+@N: MO225 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 144MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Fri May 10 09:02:13 2019
+
+###########################################################]

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr.db b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr.db
new file mode 100644 (file)
index 0000000..283b4fd
Binary files /dev/null and b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr.db differ

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.szr b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.szr
new file mode 100644 (file)
index 0000000..81e5490
Binary files /dev/null and b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.szr differ

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/syntax_constraint_check.rpt.rptmap b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/syntax_constraint_check.rpt.rptmap
new file mode 100644 (file)
index 0000000..fe7eb22
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synlog/syntax_constraint_check.rpt.rptmap
@@ -0,0 +1 @@
+./sgmii_ecp5_scck.rpt,syntax_constraint_check.rpt,Syntax Constraint Check Report

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/syntmp/closed.png b/gbe/cores/sgmii/sgmii_ecp5/syn_results/syntmp/closed.png
new file mode 100644 (file)
index 0000000..0d78634
Binary files /dev/null and b/gbe/cores/sgmii/sgmii_ecp5/syn_results/syntmp/closed.png differ

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/syntmp/open.png b/gbe/cores/sgmii/sgmii_ecp5/syn_results/syntmp/open.png
new file mode 100644 (file)
index 0000000..a227005
Binary files /dev/null and b/gbe/cores/sgmii/sgmii_ecp5/syn_results/syntmp/open.png differ

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/syntmp/run_option.xml b/gbe/cores/sgmii/sgmii_ecp5/syn_results/syntmp/run_option.xml
new file mode 100644 (file)
index 0000000..a1f64ec
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/syntmp/run_option.xml
@@ -0,0 +1,24 @@
+<?xml version="1.0" encoding="utf-8"?> 
+<!-- 
+  Synopsys, Inc.
+  Version M-2017.03L-SP1-1
+  Project file /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/syntmp/run_option.xml
+  Written on Fri May 10 09:02:09 2019
+
+
+--> 
+<project_attribute_list name="Project Settings"> 
+     <option name="project_name" display_name="Project Name">sgmii_ecp5</option>
+     <option name="device_name" display_name="Device Name">syn_results: Lattice ECP5UM : LFE5UM_25F</option>
+     <option name="impl_name" display_name="Implementation Name">syn_results</option>
+     <option name="top_module" display_name="Top Module">sgmii_ecp5</option>
+     <option name="pipe" display_name="Pipelining">0</option>
+     <option name="retiming" display_name="Retiming">0</option>
+     <option name="resource_sharing" display_name="Resource Sharing">1</option>
+     <option name="maxfan" display_name="Fanout Guide">50</option>
+     <option name="disable_io_insertion" display_name="Disable I/O Insertion">1</option>
+     <option name="no_sequential_opt" display_name="Disable Sequential Optimizations">0</option>
+     <option name="fix_gated_and_generated_clocks" display_name="Clock Conversion">1</option>
+     <option name="symbolic_fsm_compiler" display_name="FSM Compiler">1</option>
+</project_attribute_list>
+

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5.plg b/gbe/cores/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5.plg
new file mode 100644 (file)
index 0000000..bab41a3
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5.plg
@@ -0,0 +1,28 @@
+@P:  Worst Slack : 4.043
+@P:  sgmii_ecp5|pll_refclki - Estimated Frequency : 168.9 MHz
+@P:  sgmii_ecp5|pll_refclki - Requested Frequency : 100.0 MHz
+@P:  sgmii_ecp5|pll_refclki - Estimated Period : 5.921
+@P:  sgmii_ecp5|pll_refclki - Requested Period : 10.000
+@P:  sgmii_ecp5|pll_refclki - Slack : 4.079
+@P:  sgmii_ecp5|rxrefclk - Estimated Frequency : 167.9 MHz
+@P:  sgmii_ecp5|rxrefclk - Requested Frequency : 100.0 MHz
+@P:  sgmii_ecp5|rxrefclk - Estimated Period : 5.957
+@P:  sgmii_ecp5|rxrefclk - Requested Period : 10.000
+@P:  sgmii_ecp5|rxrefclk - Slack : 4.043
+@P:  sgmii_ecp5|tx_pclk_inferred_clock - Estimated Frequency : 237.5 MHz
+@P:  sgmii_ecp5|tx_pclk_inferred_clock - Requested Frequency : 100.0 MHz
+@P:  sgmii_ecp5|tx_pclk_inferred_clock - Estimated Period : 4.211
+@P:  sgmii_ecp5|tx_pclk_inferred_clock - Requested Period : 10.000
+@P:  sgmii_ecp5|tx_pclk_inferred_clock - Slack : 5.789
+@P:  System - Estimated Frequency : 840.7 MHz
+@P:  System - Requested Frequency : 100.0 MHz
+@P:  System - Estimated Period : 1.190
+@P:  System - Requested Period : 10.000
+@P:  System - Slack : 8.810
+@P:  Total Area : 157.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  CPU Time : 0h:00m:03s

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm b/gbe/cores/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm
new file mode 100644 (file)
index 0000000..a9d2ee2
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm
@@ -0,0 +1,1157 @@
+<html><body><samp><pre>
+<!@TC:1557471729>
+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
+#install: /home/soft/lattice/diamond/3.10_x64/synpbase
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Fri May 10 09:02:09 2019
+
+#Implementation: syn_results
+
+<a name=compilerReport1></a>Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1557471731> | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+<a name=compilerReport2></a>Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1557471731> | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1557471731> | Setting time resolution to ps
+@N: : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd:30:7:30:17:@N::@XP_MSG">sgmii_ecp5.vhd(30)</a><!@TM:1557471731> | Top entity is set to sgmii_ecp5.
+VHDL syntax check successful!
+File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd changed - recompiling
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Fri May 10 09:02:09 2019
+
+###########################################################]
+<a name=compilerReport3></a>Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1557471731> | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
+Verilog syntax check successful!
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Fri May 10 09:02:10 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1557471731> | Setting time resolution to ps
+@N: : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd:30:7:30:17:@N::@XP_MSG">sgmii_ecp5.vhd(30)</a><!@TM:1557471731> | Top entity is set to sgmii_ecp5.
+File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd changed - recompiling
+File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling
+VHDL syntax check successful!
+File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd changed - recompiling
+@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd:30:7:30:17:@N:CD630:@XP_MSG">sgmii_ecp5.vhd(30)</a><!@TM:1557471731> | Synthesizing work.sgmii_ecp5.v1.
+Post processing for work.sgmii_ecp5.v1
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB)
+
+
+Process completed successfully.
+# Fri May 10 09:02:10 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
+Verilog syntax check successful!
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1968:7:1968:11:@N:CG364:@XP_MSG">sgmii_ecp5_softlogic.v(1968)</a><!@TM:1557471731> | Synthesizing module sync in library work.
+
+       PDATA_RST_VAL=32'b00000000000000000000000000000000
+   Generated name = sync_0s
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1051:7:1051:25:@N:CG364:@XP_MSG">sgmii_ecp5_softlogic.v(1051)</a><!@TM:1557471731> | Synthesizing module sgmii_ecp5sll_core in library work.
+
+       PPROTOCOL=24'b010001110100001001000101
+       PLOL_SETTING=32'b00000000000000000000000000000000
+       PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100
+       PPCIE_MAX_RATE=24'b001100100010111000110101
+       PDIFF_VAL_LOCK=32'b00000000000000000000000000100111
+       PDIFF_VAL_UNLOCK=32'b00000000000000000000000001001110
+       PPCLK_TC=32'b00000000000000100000000000000000
+       PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000
+       PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000
+       PPCLK_DIV11_TC=32'b00000000000000000000000000000000
+       LPLL_LOSS_ST=2'b00
+       LPLL_PRELOSS_ST=2'b01
+       LPLL_PRELOCK_ST=2'b10
+       LPLL_LOCK_ST=2'b11
+       LRCLK_TC=16'b1111111111111111
+       LRCLK_TC_PUL_WIDTH=16'b0000000000110010
+       LHB_WAIT_CNT=8'b11111111
+       LPCLK_TC_0=32'b00000000000000001000000000000000
+       LPCLK_TC_1=32'b00000000000000010000000000000000
+       LPCLK_TC_2=32'b00000000000000100000000000000000
+       LPCLK_TC_3=32'b00000000000000101000000000000000
+       LPCLK_TC_4=32'b00000000000000010000000000000000
+       LPDIFF_LOCK_00=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_10=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_20=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_30=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_40=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_01=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_11=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_21=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_31=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_41=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_02=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_12=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_22=32'b00000000000000000000000011000100
+       LPDIFF_LOCK_32=32'b00000000000000000000000011110101
+       LPDIFF_LOCK_42=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_03=32'b00000000000000000000000010000011
+       LPDIFF_LOCK_13=32'b00000000000000000000000100000110
+       LPDIFF_LOCK_23=32'b00000000000000000000001000001100
+       LPDIFF_LOCK_33=32'b00000000000000000000001010001111
+       LPDIFF_LOCK_43=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011
+       LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110
+       LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010
+       LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001
+       LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111
+       LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000
+       LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000
+       LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000
+       LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100
+       LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001
+       LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010
+       LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111
+       LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001
+   Generated name = sgmii_ecp5sll_core_Z1_layer1
+@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1287:54:1287:60:@N:CG179:@XP_MSG">sgmii_ecp5_softlogic.v(1287)</a><!@TM:1557471731> | Removing redundant assignment.
+@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1293:52:1293:56:@N:CG179:@XP_MSG">sgmii_ecp5_softlogic.v(1293)</a><!@TM:1557471731> | Removing redundant assignment.
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1350:0:1350:6:@W:CL169:@XP_MSG">sgmii_ecp5_softlogic.v(1350)</a><!@TM:1557471731> | Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:92:7:92:25:@N:CG364:@XP_MSG">sgmii_ecp5_softlogic.v(92)</a><!@TM:1557471731> | Synthesizing module sgmii_ecp5rsl_core in library work.
+
+       pnum_channels=32'b00000000000000000000000000000001
+       pprotocol=24'b010001110100001001000101
+       pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
+       pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_tx_rdy=32'b00000000000000000000101110111000
+       pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_rx_rdy=32'b00000000000000000000101110111000
+       wa_num_cycles=32'b00000000000000000000010000000000
+       dac_num_cycles=32'b00000000000000000000000000000011
+       lreset_pwidth=32'b00000000000000000000000000000011
+       lwait_b4_trst=32'b00000000000010111110101111000010
+       lwait_b4_trst_s=32'b00000000000000000000001100001101
+       lplol_cnt_width=32'b00000000000000000000000000010100
+       lwait_after_plol0=32'b00000000000000000000000000000100
+       lwait_b4_rrst=32'b00000000000000101100000000000000
+       lrrst_wait_width=32'b00000000000000000000000000010100
+       lwait_after_rrst=32'b00000000000011000011010100000000
+       lwait_b4_rrst_s=32'b00000000000000000000000111001100
+       lrlol_cnt_width=32'b00000000000000000000000000010011
+       lwait_after_lols=32'b00000000000000001100010000000000
+       lwait_after_lols_s=32'b00000000000000000000000010010110
+       llols_cnt_width=32'b00000000000000000000000000010010
+       lrdb_max=32'b00000000000000000000000000001111
+       ltxr_wait_width=32'b00000000000000000000000000001100
+       lrxr_wait_width=32'b00000000000000000000000000001100
+   Generated name = sgmii_ecp5rsl_core_Z2_layer1
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:326:33:326:41:@W:CG133:@XP_MSG">sgmii_ecp5_softlogic.v(326)</a><!@TM:1557471731> | Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:327:33:327:44:@W:CG360:@XP_MSG">sgmii_ecp5_softlogic.v(327)</a><!@TM:1557471731> | Removing wire rrst_cnt_tc, as there is no assignment to it.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:328:33:328:42:@W:CG133:@XP_MSG">sgmii_ecp5_softlogic.v(328)</a><!@TM:1557471731> | Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:341:33:341:40:@W:CG133:@XP_MSG">sgmii_ecp5_softlogic.v(341)</a><!@TM:1557471731> | Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:342:33:342:40:@W:CG133:@XP_MSG">sgmii_ecp5_softlogic.v(342)</a><!@TM:1557471731> | Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:343:33:343:43:@W:CG360:@XP_MSG">sgmii_ecp5_softlogic.v(343)</a><!@TM:1557471731> | Removing wire rxp_cnt_tc, as there is no assignment to it.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:346:33:346:43:@W:CG133:@XP_MSG">sgmii_ecp5_softlogic.v(346)</a><!@TM:1557471731> | Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:347:33:347:46:@W:CG360:@XP_MSG">sgmii_ecp5_softlogic.v(347)</a><!@TM:1557471731> | Removing wire rlolsz_cnt_tc, as there is no assignment to it.</font>
+<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:350:33:350:44:@W:CG360:@XP_MSG">sgmii_ecp5_softlogic.v(350)</a><!@TM:1557471731> | Removing wire rxp_cnt2_tc, as there is no assignment to it.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:351:33:351:48:@W:CG133:@XP_MSG">sgmii_ecp5_softlogic.v(351)</a><!@TM:1557471731> | Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:352:33:352:44:@W:CG133:@XP_MSG">sgmii_ecp5_softlogic.v(352)</a><!@TM:1557471731> | Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:353:33:353:47:@W:CG360:@XP_MSG">sgmii_ecp5_softlogic.v(353)</a><!@TM:1557471731> | Removing wire data_loop_b_tc, as there is no assignment to it.</font>
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:806:3:806:9:@W:CL169:@XP_MSG">sgmii_ecp5_softlogic.v(806)</a><!@TM:1557471731> | Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.</font>
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:567:3:567:9:@W:CL169:@XP_MSG">sgmii_ecp5_softlogic.v(567)</a><!@TM:1557471731> | Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.</font>
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:567:3:567:9:@W:CL169:@XP_MSG">sgmii_ecp5_softlogic.v(567)</a><!@TM:1557471731> | Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.</font>
+<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:694:3:694:9:@W:CL190:@XP_MSG">sgmii_ecp5_softlogic.v(694)</a><!@TM:1557471731> | Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
+<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:461:3:461:9:@W:CL190:@XP_MSG">sgmii_ecp5_softlogic.v(461)</a><!@TM:1557471731> | Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
+<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:422:3:422:9:@W:CL190:@XP_MSG">sgmii_ecp5_softlogic.v(422)</a><!@TM:1557471731> | Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
+<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:422:3:422:9:@W:CL260:@XP_MSG">sgmii_ecp5_softlogic.v(422)</a><!@TM:1557471731> | Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
+<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:461:3:461:9:@W:CL260:@XP_MSG">sgmii_ecp5_softlogic.v(461)</a><!@TM:1557471731> | Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
+<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:694:3:694:9:@W:CL260:@XP_MSG">sgmii_ecp5_softlogic.v(694)</a><!@TM:1557471731> | Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
+<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:200:33:200:49:@W:CL246:@XP_MSG">sgmii_ecp5_softlogic.v(200)</a><!@TM:1557471731> | Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.</font>
+<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:204:33:204:52:@W:CL246:@XP_MSG">sgmii_ecp5_softlogic.v(204)</a><!@TM:1557471731> | Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.</font>
+<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:205:33:205:49:@W:CL246:@XP_MSG">sgmii_ecp5_softlogic.v(205)</a><!@TM:1557471731> | Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.</font>
+<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:206:33:206:49:@W:CL246:@XP_MSG">sgmii_ecp5_softlogic.v(206)</a><!@TM:1557471731> | Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.</font>
+<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:207:33:207:49:@W:CL246:@XP_MSG">sgmii_ecp5_softlogic.v(207)</a><!@TM:1557471731> | Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.</font>
+<font color=#A52A2A>@W:<a href="@W:CL279:@XP_HELP">CL279</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL279:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.</font>
+<font color=#A52A2A>@W:<a href="@W:CL279:@XP_HELP">CL279</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL279:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.</font>
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL169:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers.</font>
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL169:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557471731> | Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers.</font>
+@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1801:0:1801:6:@N:CL201:@XP_MSG">sgmii_ecp5_softlogic.v(1801)</a><!@TM:1557471731> | Trying to extract state machine for register sll_state.
+Extracted state machine for register sll_state
+State machine has 4 reachable states with original encodings of:
+   00
+   01
+   10
+   11
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB)
+
+
+Process completed successfully.
+# Fri May 10 09:02:10 2019
+
+###########################################################]
+<a name=compilerReport4></a>Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1557471731> | Running in 64-bit mode 
+File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/layer0.srs changed - recompiling
+File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/layer1.srs changed - recompiling
+
+=======================================================================================
+For a summary of linker messages for components that did not bind, please see log file:
+Linked File: <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.linkerlog:@XP_FILE">sgmii_ecp5_comp.linkerlog</a>
+=======================================================================================
+
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 09:02:11 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 09:02:11 2019
+
+###########################################################]
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1557471729>
+<a name=compilerReport5></a>Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1557471732> | Running in 64-bit mode 
+File /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 09:02:12 2019
+
+###########################################################]
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1557471729>
+# Fri May 10 09:02:12 2019
+
+<a name=mapperReport6></a>Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35</a>
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.fdc
+Linked File: <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt:@XP_FILE">sgmii_ecp5_scck.rpt</a>
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt" file 
+@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1557471733> | Running in 64-bit mode. 
+@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1557471733> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)
+
+@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1408:0:1408:6:@N:BN362:@XP_MSG">sgmii_ecp5_softlogic.v(1408)</a><!@TM:1557471733> | Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
+@N:<a href="@N:BN115:@XP_HELP">BN115</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1244:27:1244:41:@N:BN115:@XP_MSG">sgmii_ecp5_softlogic.v(1244)</a><!@TM:1557471733> | Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances.
+@N:<a href="@N:BN115:@XP_HELP">BN115</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1252:27:1252:42:@N:BN115:@XP_MSG">sgmii_ecp5_softlogic.v(1252)</a><!@TM:1557471733> | Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances.
+@N:<a href="@N:BN115:@XP_HELP">BN115</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1236:27:1236:41:@N:BN115:@XP_MSG">sgmii_ecp5_softlogic.v(1236)</a><!@TM:1557471733> | Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances.
+@N:<a href="@N:BN115:@XP_HELP">BN115</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1268:27:1268:45:@N:BN115:@XP_MSG">sgmii_ecp5_softlogic.v(1268)</a><!@TM:1557471733> | Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances.
+@N:<a href="@N:BN115:@XP_HELP">BN115</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1260:27:1260:45:@N:BN115:@XP_MSG">sgmii_ecp5_softlogic.v(1260)</a><!@TM:1557471733> | Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances.
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist sgmii_ecp5
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+
+<a name=mapperReport7></a>Clock Summary</a>
+******************
+
+          Start                                 Requested     Requested     Clock        Clock                   Clock
+Level     Clock                                 Frequency     Period        Type         Group                   Load 
+----------------------------------------------------------------------------------------------------------------------
+0 -       System                                100.0 MHz     10.000        system       system_clkgroup         0    
+                                                                                                                      
+0 -       sgmii_ecp5|pll_refclki                100.0 MHz     10.000        inferred     Inferred_clkgroup_0     93   
+                                                                                                                      
+0 -       sgmii_ecp5|rxrefclk                   100.0 MHz     10.000        inferred     Inferred_clkgroup_1     77   
+                                                                                                                      
+0 -       sgmii_ecp5|tx_pclk_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_2     53   
+======================================================================================================================
+
+<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1988:0:1988:6:@W:MT529:@XP_MSG">sgmii_ecp5_softlogic.v(1988)</a><!@TM:1557471733> | Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
+<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:567:3:567:9:@W:MT529:@XP_MSG">sgmii_ecp5_softlogic.v(567)</a><!@TM:1557471733> | Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
+<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1988:0:1988:6:@W:MT529:@XP_MSG">sgmii_ecp5_softlogic.v(1988)</a><!@TM:1557471733> | Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   10 -> 10
+   11 -> 11
+@N:<a href="@N:MO225:@XP_HELP">MO225</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1801:0:1801:6:@N:MO225:@XP_MSG">sgmii_ecp5_softlogic.v(1801)</a><!@TM:1557471733> | There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 144MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Fri May 10 09:02:13 2019
+
+###########################################################]
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1557471729>
+# Fri May 10 09:02:13 2019
+
+<a name=mapperReport8></a>Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35</a>
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1557471737> | Running in 64-bit mode. 
+@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1557471737> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   10 -> 10
+   11 -> 11
+@N:<a href="@N:MO225:@XP_HELP">MO225</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1801:0:1801:6:@N:MO225:@XP_MSG">sgmii_ecp5_softlogic.v(1801)</a><!@TM:1557471737> | There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1350:0:1350:6:@N:MO231:@XP_MSG">sgmii_ecp5_softlogic.v(1350)</a><!@TM:1557471737> | Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] 
+@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1304:0:1304:6:@N:MO231:@XP_MSG">sgmii_ecp5_softlogic.v(1304)</a><!@TM:1557471737> | Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] 
+@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1759:0:1759:6:@N:MO231:@XP_MSG">sgmii_ecp5_softlogic.v(1759)</a><!@TM:1557471737> | Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] 
+@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:412:3:412:9:@N:MO231:@XP_MSG">sgmii_ecp5_softlogic.v(412)</a><!@TM:1557471737> | Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] 
+@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:909:3:909:9:@N:MO231:@XP_MSG">sgmii_ecp5_softlogic.v(909)</a><!@TM:1557471737> | Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] 
+@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:527:3:527:9:@N:MO231:@XP_MSG">sgmii_ecp5_softlogic.v(527)</a><!@TM:1557471737> | Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] 
+@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:778:3:778:9:@N:MO231:@XP_MSG">sgmii_ecp5_softlogic.v(778)</a><!@TM:1557471737> | Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] 
+@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:680:3:680:9:@N:MO231:@XP_MSG">sgmii_ecp5_softlogic.v(680)</a><!@TM:1557471737> | Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] 
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 145MB)
+
+@N:<a href="@N:FX1019:@XP_HELP">FX1019</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1988:0:1988:6:@N:FX1019:@XP_MSG">sgmii_ecp5_softlogic.v(1988)</a><!@TM:1557471737> | Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N:<a href="@N:FX1019:@XP_HELP">FX1019</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1988:0:1988:6:@N:FX1019:@XP_MSG">sgmii_ecp5_softlogic.v(1988)</a><!@TM:1557471737> | Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N:<a href="@N:FX1019:@XP_HELP">FX1019</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1988:0:1988:6:@N:FX1019:@XP_MSG">sgmii_ecp5_softlogic.v(1988)</a><!@TM:1557471737> | Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+   1           0h:00m:01s                   4.90ns              155 /       221
+@N:<a href="@N:FX1019:@XP_HELP">FX1019</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1988:0:1988:6:@N:FX1019:@XP_MSG">sgmii_ecp5_softlogic.v(1988)</a><!@TM:1557471737> | Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N:<a href="@N:FX1019:@XP_HELP">FX1019</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1988:0:1988:6:@N:FX1019:@XP_MSG">sgmii_ecp5_softlogic.v(1988)</a><!@TM:1557471737> | Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N:<a href="@N:FX1019:@XP_HELP">FX1019</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v:1988:0:1988:6:@N:FX1019:@XP_MSG">sgmii_ecp5_softlogic.v(1988)</a><!@TM:1557471737> | Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB)
+
+@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1557471737> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 149MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+<a name=clockReport9></a>#### START OF CLOCK OPTIMIZATION REPORT #####[</a>
+
+3 non-gated/non-generated clock tree(s) driving 221 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+============================================= Non-Gated/Non-Generated Clocks =============================================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                                   
+--------------------------------------------------------------------------------------------------------------------------
+<a href="@|S:pll_refclki@|E:rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001  @XP_NAMES_BY_PROP">ClockId0001 </a>       pll_refclki         port                   91         rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]
+<a href="@|S:rxrefclk@|E:rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]@|F:@syn_sample_clock_path==CKID0002@|M:ClockId0002  @XP_NAMES_BY_PROP">ClockId0002 </a>       rxrefclk            port                   77         rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]
+<a href="@|S:DCU0_inst@|E:sll_inst.pcount[21]@|F:@syn_sample_clock_path==CKID0003@|M:ClockId0003  @XP_NAMES_BY_PROP">ClockId0003 </a>       DCU0_inst           DCUA                   53         sll_inst.pcount[21]                               
+==========================================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 149MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 149MB)
+
+Writing EDIF Netlist and constraint files
+@N:<a href="@N:FX1056:@XP_HELP">FX1056</a> : <!@TM:1557471737> | Writing EDF file: /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.edn 
+M-2017.03L-SP1-1
+@N:<a href="@N:BW106:@XP_HELP">BW106</a> : <!@TM:1557471737> | Synplicity Constraint File capacitance units using default value of 1pF  
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 152MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 152MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+<font color=#A52A2A>@W:<a href="@W:MT246:@XP_HELP">MT246</a> : <a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd:162:4:162:13:@W:MT246:@XP_MSG">sgmii_ecp5.vhd(162)</a><!@TM:1557471737> | Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) </font>
+<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1557471737> | Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"</font> 
+<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1557471737> | Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"</font> 
+<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1557471737> | Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk"</font> 
+
+
+<a name=timingReport10></a>##### START OF TIMING REPORT #####[</a>
+# Timing Report written on Fri May 10 09:02:16 2019
+#
+
+
+Top view:               sgmii_ecp5
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.fdc
+                       
+@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1557471737> | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 
+
+@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1557471737> | Clock constraints include only register-to-register paths associated with each individual clock. 
+
+
+
+<a name=performanceSummary11></a>Performance Summary</a>
+*******************
+
+
+Worst slack in design: 4.043
+
+                                      Requested     Estimated     Requested     Estimated               Clock        Clock              
+Starting Clock                        Frequency     Frequency     Period        Period        Slack     Type         Group              
+----------------------------------------------------------------------------------------------------------------------------------------
+sgmii_ecp5|pll_refclki                100.0 MHz     168.9 MHz     10.000        5.921         4.079     inferred     Inferred_clkgroup_0
+sgmii_ecp5|rxrefclk                   100.0 MHz     167.9 MHz     10.000        5.957         4.043     inferred     Inferred_clkgroup_1
+sgmii_ecp5|tx_pclk_inferred_clock     100.0 MHz     237.5 MHz     10.000        4.211         5.789     inferred     Inferred_clkgroup_2
+System                                100.0 MHz     840.7 MHz     10.000        1.190         8.810     system       system_clkgroup    
+========================================================================================================================================
+
+
+
+
+
+<a name=clockRelationships12></a>Clock Relationships</a>
+*******************
+
+Clocks                                                                |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+Starting                           Ending                             |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+System                             sgmii_ecp5|rxrefclk                |  10.000      8.811  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             System                             |  10.000      8.253  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             sgmii_ecp5|pll_refclki             |  10.000      4.079  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             sgmii_ecp5|tx_pclk_inferred_clock  |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|rxrefclk                System                             |  10.000      8.277  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|rxrefclk                sgmii_ecp5|rxrefclk                |  10.000      4.043  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|tx_pclk_inferred_clock  sgmii_ecp5|pll_refclki             |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|tx_pclk_inferred_clock  sgmii_ecp5|tx_pclk_inferred_clock  |  10.000      5.789  |  No paths    -      |  No paths    -      |  No paths    -    
+============================================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+<a name=interfaceInfo13></a>Interface Information </a>
+*********************
+
+No IO constraint found
+
+
+
+====================================
+<a name=clockReport14></a>Detailed Report for Clock: sgmii_ecp5|pll_refclki</a>
+====================================
+
+
+
+<a name=startingSlack15></a>Starting Points with Worst Slack</a>
+********************************
+
+                                   Starting                                                        Arrival          
+Instance                           Reference                  Type        Pin     Net              Time        Slack
+                                   Clock                                                                            
+--------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[2]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[2]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[3]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[3]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[17]     sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[17]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[19]     sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[19]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[1]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[1]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[4]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[4]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[5]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[5]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[6]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[6]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[7]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[7]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[8]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[8]      0.907       4.684
+====================================================================================================================
+
+
+<a name=endingSlack16></a>Ending Points with Worst Slack</a>
+******************************
+
+                                   Starting                                                          Required          
+Instance                           Reference                  Type        Pin     Net                Time         Slack
+                                   Clock                                                                               
+-----------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[19]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[19]     9.946        4.079
+rsl_inst.genblk1\.plol_cnt[17]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[17]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[18]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[18]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[15]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[15]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[16]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[16]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[13]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[13]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[14]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[14]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[11]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[11]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[12]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[12]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[9]      sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[9]      9.946        4.383
+=======================================================================================================================
+
+
+
+<a name=worstPaths17></a>Worst Path Information</a>
+<a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr:srsf/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srs:fp:60928:65920:@XP_NAMES_GATE">View Worst Path in Analyst</a>
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.867
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.079
+
+    Number of logic level(s):                15
+    Starting point:                          rsl_inst.genblk1\.plol_cnt[2] / Q
+    Ending point:                            rsl_inst.genblk1\.plol_cnt[19] / D
+    The start point is clocked by            sgmii_ecp5|pll_refclki [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|pll_refclki [rising] on pin CK
+
+Instance / Net                                        Pin      Pin               Arrival     No. of    
+Name                                     Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[2]            FD1S3DX      Q        Out     0.907     0.907       -         
+plol_cnt[2]                              Net          -        -       -         -           2         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     Z        Out     0.606     1.513       -         
+un1_plol_cnt_tc_10                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     Z        Out     0.606     2.119       -         
+un1_plol_cnt_tc_14                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     Z        Out     0.762     2.881       -         
+un1_plol_cnt_tc                          Net          -        -       -         -           5         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     B        In      0.000     2.881       -         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     Z        Out     0.840     3.721       -         
+plol_cnt                                 Net          -        -       -         -           21        
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.721       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.621       -         
+plol_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.621       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.682       -         
+plol_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.682       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.743       -         
+plol_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.743       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.804       -         
+plol_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.804       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.865       -         
+plol_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.865       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.926       -         
+plol_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.926       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.987       -         
+plol_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.987       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.048       -         
+plol_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.048       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.109       -         
+plol_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.109       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        COUT     Out     0.061     5.170       -         
+plol_cnt_cry[18]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        CIN      In      0.000     5.170       -         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        S0       Out     0.698     5.867       -         
+plol_cnt_s[19]                           Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt[19]           FD1S3DX      D        In      0.000     5.867       -         
+=======================================================================================================
+
+
+
+
+====================================
+<a name=clockReport18></a>Detailed Report for Clock: sgmii_ecp5|rxrefclk</a>
+====================================
+
+
+
+<a name=startingSlack19></a>Starting Points with Worst Slack</a>
+********************************
+
+                                    Starting                                                      Arrival          
+Instance                            Reference               Type        Pin     Net               Time        Slack
+                                    Clock                                                                          
+-------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rxs_rst           sgmii_ecp5|rxrefclk     FD1P3DX     Q       rxs_rst           1.015       4.043
+rsl_inst.genblk2\.rlol1_cnt[7]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[7]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[8]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[8]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[9]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[9]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[10]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[10]     0.907       4.136
+rsl_inst.genblk2\.rlols0_cnt[1]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[1]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[2]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[2]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[3]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[3]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[4]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[4]     0.907       4.170
+rsl_inst.genblk2\.rlol1_cnt[0]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[0]      0.907       4.742
+===================================================================================================================
+
+
+<a name=endingSlack20></a>Ending Points with Worst Slack</a>
+******************************
+
+                                              Starting                                                         Required          
+Instance                                      Reference               Type        Pin     Net                  Time         Slack
+                                              Clock                                                                              
+---------------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[11]     9.946        4.043
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[9]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[9]      9.946        4.104
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[10]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[10]     9.946        4.104
+rsl_inst.genblk2\.rlol1_cnt[17]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[17]      9.946        4.136
+rsl_inst.genblk2\.rlol1_cnt[18]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[18]      9.946        4.136
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[7]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[7]      9.946        4.165
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[8]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rxr_wt_cnt_s[8]      9.946        4.165
+rsl_inst.genblk2\.rlols0_cnt[17]              sgmii_ecp5|rxrefclk     FD1P3DX     D       rlols0_cnt_s[17]     9.946        4.170
+rsl_inst.genblk2\.rlol1_cnt[15]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[15]      9.946        4.197
+rsl_inst.genblk2\.rlol1_cnt[16]               sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[16]      9.946        4.197
+=================================================================================================================================
+
+
+
+<a name=worstPaths21></a>Worst Path Information</a>
+<a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr:srsf/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srs:fp:71164:75268:@XP_NAMES_GATE">View Worst Path in Analyst</a>
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.902
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     4.043
+
+    Number of logic level(s):                11
+    Starting point:                          rsl_inst.genblk2\.rxs_rst / Q
+    Ending point:                            rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11] / D
+    The start point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+
+Instance / Net                                                  Pin      Pin               Arrival     No. of    
+Name                                               Type         Name     Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rxs_rst                          FD1P3DX      Q        Out     1.015     1.015       -         
+rxs_rst                                            Net          -        -       -         -           6         
+rsl_inst.rdo_rx_serdes_rst_c_1[0]                  ORCALUT4     B        In      0.000     1.015       -         
+rsl_inst.rdo_rx_serdes_rst_c_1[0]                  ORCALUT4     Z        Out     0.708     1.723       -         
+rsl_rx_serdes_rst_c                                Net          -        -       -         -           3         
+rsl_inst.dual_or_rserd_rst                         ORCALUT4     A        In      0.000     1.723       -         
+rsl_inst.dual_or_rserd_rst                         ORCALUT4     Z        Out     0.798     2.521       -         
+dual_or_rserd_rst                                  Net          -        -       -         -           9         
+rsl_inst.rx_any_rst                                ORCALUT4     A        In      0.000     2.521       -         
+rsl_inst.rx_any_rst                                ORCALUT4     Z        Out     0.660     3.181       -         
+rx_any_rst                                         Net          -        -       -         -           2         
+rsl_inst.rx_any_rst_RNIFD021                       ORCALUT4     A        In      0.000     3.181       -         
+rsl_inst.rx_any_rst_RNIFD021                       ORCALUT4     Z        Out     0.819     4.000       -         
+rxr_wt_cnt9                                        Net          -        -       -         -           14        
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0]     CCU2C        A1       In      0.000     4.000       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[0]     CCU2C        COUT     Out     0.900     4.900       -         
+rxr_wt_cnt_cry[0]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1]     CCU2C        CIN      In      0.000     4.900       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[1]     CCU2C        COUT     Out     0.061     4.961       -         
+rxr_wt_cnt_cry[2]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3]     CCU2C        CIN      In      0.000     4.961       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[3]     CCU2C        COUT     Out     0.061     5.022       -         
+rxr_wt_cnt_cry[4]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5]     CCU2C        CIN      In      0.000     5.022       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[5]     CCU2C        COUT     Out     0.061     5.083       -         
+rxr_wt_cnt_cry[6]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7]     CCU2C        CIN      In      0.000     5.083       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[7]     CCU2C        COUT     Out     0.061     5.144       -         
+rxr_wt_cnt_cry[8]                                  Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9]     CCU2C        CIN      In      0.000     5.144       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_cry_0[9]     CCU2C        COUT     Out     0.061     5.205       -         
+rxr_wt_cnt_cry[10]                                 Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11]      CCU2C        CIN      In      0.000     5.205       -         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt_s_0[11]      CCU2C        S0       Out     0.698     5.902       -         
+rxr_wt_cnt_s[11]                                   Net          -        -       -         -           1         
+rsl_inst.genblk2\.genblk3\.rxr_wt_cnt[11]          FD1P3DX      D        In      0.000     5.902       -         
+=================================================================================================================
+
+
+
+
+====================================
+<a name=clockReport22></a>Detailed Report for Clock: sgmii_ecp5|tx_pclk_inferred_clock</a>
+====================================
+
+
+
+<a name=startingSlack23></a>Starting Points with Worst Slack</a>
+********************************
+
+                            Starting                                                                   Arrival          
+Instance                    Reference                             Type        Pin     Net              Time        Slack
+                            Clock                                                                                       
+------------------------------------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1       sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p1     1.098       5.789
+sll_inst.ppul_sync_p2       sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p2     1.098       5.789
+sll_inst.pcount_diff[0]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_0      0.985       6.147
+sll_inst.pcount[0]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[0]        0.955       6.178
+sll_inst.pcount_diff[1]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_1      0.955       6.239
+sll_inst.pcount_diff[2]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_2      0.955       6.239
+sll_inst.pcount[1]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[1]        0.907       6.287
+sll_inst.pcount[2]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[2]        0.907       6.287
+sll_inst.pcount_diff[3]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_3      0.955       6.300
+sll_inst.pcount_diff[4]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_4      0.955       6.300
+========================================================================================================================
+
+
+<a name=endingSlack24></a>Ending Points with Worst Slack</a>
+******************************
+
+                             Starting                                                                                  Required          
+Instance                     Reference                             Type        Pin     Net                             Time         Slack
+                             Clock                                                                                                       
+-----------------------------------------------------------------------------------------------------------------------------------------
+sll_inst.pcount[21]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[21]                    9.946        5.789
+sll_inst.pcount[19]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[19]                    9.946        5.850
+sll_inst.pcount[20]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[20]                    9.946        5.850
+sll_inst.pcount[17]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[17]                    9.946        5.911
+sll_inst.pcount[18]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[18]                    9.946        5.911
+sll_inst.pcount[15]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[15]                    9.946        5.972
+sll_inst.pcount[16]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[16]                    9.946        5.972
+sll_inst.pcount[13]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[13]                    9.946        6.033
+sll_inst.pcount[14]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[14]                    9.946        6.033
+sll_inst.pcount_diff[21]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3DX     D       un1_pcount_diff_1_s_21_0_S0     9.946        6.034
+=========================================================================================================================================
+
+
+
+<a name=worstPaths25></a>Worst Path Information</a>
+<a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr:srsf/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srs:fp:80670:84576:@XP_NAMES_GATE">View Worst Path in Analyst</a>
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      4.157
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 5.789
+
+    Number of logic level(s):                13
+    Starting point:                          sll_inst.ppul_sync_p1 / Q
+    Ending point:                            sll_inst.pcount[21] / D
+    The start point is clocked by            sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
+
+Instance / Net                             Pin      Pin               Arrival     No. of    
+Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1         FD1S3DX      Q        Out     1.098     1.098       -         
+ppul_sync_p1                  Net          -        -       -         -           25        
+sll_inst.pcount10_0_o3        ORCALUT4     A        In      0.000     1.098       -         
+sll_inst.pcount10_0_o3        ORCALUT4     Z        Out     0.851     1.950       -         
+N_8                           Net          -        -       -         -           25        
+sll_inst.pcount_cry_0[0]      CCU2C        A1       In      0.000     1.950       -         
+sll_inst.pcount_cry_0[0]      CCU2C        COUT     Out     0.900     2.850       -         
+pcount_cry[0]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[1]      CCU2C        CIN      In      0.000     2.850       -         
+sll_inst.pcount_cry_0[1]      CCU2C        COUT     Out     0.061     2.911       -         
+pcount_cry[2]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[3]      CCU2C        CIN      In      0.000     2.911       -         
+sll_inst.pcount_cry_0[3]      CCU2C        COUT     Out     0.061     2.972       -         
+pcount_cry[4]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[5]      CCU2C        CIN      In      0.000     2.972       -         
+sll_inst.pcount_cry_0[5]      CCU2C        COUT     Out     0.061     3.033       -         
+pcount_cry[6]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[7]      CCU2C        CIN      In      0.000     3.033       -         
+sll_inst.pcount_cry_0[7]      CCU2C        COUT     Out     0.061     3.094       -         
+pcount_cry[8]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[9]      CCU2C        CIN      In      0.000     3.094       -         
+sll_inst.pcount_cry_0[9]      CCU2C        COUT     Out     0.061     3.155       -         
+pcount_cry[10]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[11]     CCU2C        CIN      In      0.000     3.155       -         
+sll_inst.pcount_cry_0[11]     CCU2C        COUT     Out     0.061     3.216       -         
+pcount_cry[12]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[13]     CCU2C        CIN      In      0.000     3.216       -         
+sll_inst.pcount_cry_0[13]     CCU2C        COUT     Out     0.061     3.277       -         
+pcount_cry[14]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[15]     CCU2C        CIN      In      0.000     3.277       -         
+sll_inst.pcount_cry_0[15]     CCU2C        COUT     Out     0.061     3.338       -         
+pcount_cry[16]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[17]     CCU2C        CIN      In      0.000     3.338       -         
+sll_inst.pcount_cry_0[17]     CCU2C        COUT     Out     0.061     3.399       -         
+pcount_cry[18]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[19]     CCU2C        CIN      In      0.000     3.399       -         
+sll_inst.pcount_cry_0[19]     CCU2C        COUT     Out     0.061     3.460       -         
+pcount_cry[20]                Net          -        -       -         -           1         
+sll_inst.pcount_s_0[21]       CCU2C        CIN      In      0.000     3.460       -         
+sll_inst.pcount_s_0[21]       CCU2C        S0       Out     0.698     4.157       -         
+pcount_s[21]                  Net          -        -       -         -           1         
+sll_inst.pcount[21]           FD1S3DX      D        In      0.000     4.157       -         
+============================================================================================
+
+
+
+
+====================================
+<a name=clockReport26></a>Detailed Report for Clock: System</a>
+====================================
+
+
+
+<a name=startingSlack27></a>Starting Points with Worst Slack</a>
+********************************
+
+              Starting                                                 Arrival          
+Instance      Reference     Type     Pin              Net              Time        Slack
+              Clock                                                                     
+----------------------------------------------------------------------------------------
+DCU0_inst     System        DCUA     CH0_FFS_RLOL     rx_cdr_lol_s     0.000       8.810
+DCU0_inst     System        DCUA     CH0_FFS_RLOS     rx_los_low_s     0.000       8.810
+========================================================================================
+
+
+<a name=endingSlack28></a>Ending Points with Worst Slack</a>
+******************************
+
+                                                       Starting                                                            Required          
+Instance                                               Reference     Type        Pin     Net                               Time         Slack
+                                                       Clock                                                                                 
+---------------------------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     SP      un2_rdo_serdes_rst_dual_c_2_i     9.806        8.810
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     D       rxpr_appd_RNO[0]                  9.946        9.556
+rsl_inst.genblk2\.rlol_p1                              System        FD1S3DX     D       rx_cdr_lol_s                      9.946        9.946
+rsl_inst.genblk2\.rlos_p1                              System        FD1S3DX     D       rx_los_low_s                      9.946        9.946
+=============================================================================================================================================
+
+
+
+<a name=worstPaths29></a>Worst Path Information</a>
+<a href="/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srr:srsf/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5.srs:fp:88094:89282:@XP_NAMES_GATE">View Worst Path in Analyst</a>
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.194
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.806
+
+    - Propagation time:                      0.996
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 8.810
+
+    Number of logic level(s):                2
+    Starting point:                          DCU0_inst / CH0_FFS_RLOL
+    Ending point:                            rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+
+Instance / Net                                                            Pin              Pin               Arrival     No. of    
+Name                                                         Type         Name             Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------------------------------------------------------
+DCU0_inst                                                    DCUA         CH0_FFS_RLOL     Out     0.000     0.000       -         
+rx_cdr_lol_s                                                 Net          -                -       -         -           4         
+rsl_inst.un2_rdo_serdes_rst_dual_c_1_1                       ORCALUT4     A                In      0.000     0.000       -         
+rsl_inst.un2_rdo_serdes_rst_dual_c_1_1                       ORCALUT4     Z                Out     0.606     0.606       -         
+un2_rdo_serdes_rst_dual_c_1_1                                Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0]     ORCALUT4     B                In      0.000     0.606       -         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0]     ORCALUT4     Z                Out     0.390     0.996       -         
+un2_rdo_serdes_rst_dual_c_2_i                                Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]           FD1P3DX      SP               In      0.000     0.996       -         
+===================================================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+---------------------------------------
+<a name=resourceUsage30></a>Resource Usage Report</a>
+Part: lfe5um_25f-6
+
+Register bits: 221 of 24288 (1%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+CCU2C:          113
+DCUA:           1
+FD1P3BX:        20
+FD1P3DX:        92
+FD1S3BX:        12
+FD1S3DX:        97
+GSR:            1
+INV:            3
+ORCALUT4:       154
+PFUMX:          2
+PUR:            1
+VHI:            6
+VLO:            6
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 153MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Fri May 10 09:02:16 2019
+
+###########################################################]
+
+</pre></samp></body></html>

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_toc.htm b/gbe/cores/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_toc.htm
new file mode 100644 (file)
index 0000000..7eb2da0
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_toc.htm
@@ -0,0 +1,60 @@
+ <html> 
+  <head>
+    <script type="text/javascript" src="file:///home/soft/lattice/diamond/3.10_x64/synpbase/lib/report/reportlog_tree.js"></script>
+    <link rel="stylesheet" type="text/css" href="file:///home/soft/lattice/diamond/3.10_x64/synpbase/lib/report/reportlog_tree.css" />  
+  </head> 
+
+  <body style="background-color:#e0e0ff;">
+   <script type="text/javascript"> reportLogObj.loadImage("closed.png", "open.png")</script>
+    <ul id="syn_results-menu" class="treeview" style="padding-left:12;">
+        <li style="font-size:12; font-style:normal"> <b style="background-color:#a2bff0; font-weight:bold">sgmii_ecp5 (syn_results)</b> 
+         <ul rel="open" style="font-size:small;">
+
+<li style="font-size:12; font-style:normal"><b style="background-color:#a2bff0; font-weight:bold">Synthesis -  </b> 
+<ul rel="open">
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#compilerReport1" target="srrFrame" title="">Compiler Report</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#compilerReport4" target="srrFrame" title="">Compiler Constraint Applicator</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#mapperReport6" target="srrFrame" title="">Pre-mapping Report</a>  
+<ul rel="open" >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#mapperReport7" target="srrFrame" title="">Clock Summary</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#mapperReport8" target="srrFrame" title="">Mapper Report</a>  
+<ul rel="open" >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#clockReport9" target="srrFrame" title="">Clock Conversion</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#timingReport10" target="srrFrame" title="">Timing Report</a>  
+<ul rel="open" >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#performanceSummary11" target="srrFrame" title="">Performance Summary</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#clockRelationships12" target="srrFrame" title="">Clock Relationships</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#interfaceInfo13" target="srrFrame" title="">Interface Information</a>  </li>
+<li><a href="file://#" target="srrFrame" title="">Detailed Report for Clocks</a>  
+<ul  >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#clockReport14" target="srrFrame" title="">Clock: sgmii_ecp5|pll_refclki</a>  
+<ul  >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#startingSlack15" target="srrFrame" title="">Starting Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#endingSlack16" target="srrFrame" title="">Ending Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#worstPaths17" target="srrFrame" title="">Worst Path Information</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#clockReport18" target="srrFrame" title="">Clock: sgmii_ecp5|rxrefclk</a>  
+<ul  >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#startingSlack19" target="srrFrame" title="">Starting Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#endingSlack20" target="srrFrame" title="">Ending Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#worstPaths21" target="srrFrame" title="">Worst Path Information</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#clockReport22" target="srrFrame" title="">Clock: sgmii_ecp5|tx_pclk_inferred_clock</a>  
+<ul  >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#startingSlack23" target="srrFrame" title="">Starting Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#endingSlack24" target="srrFrame" title="">Ending Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#worstPaths25" target="srrFrame" title="">Worst Path Information</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#clockReport26" target="srrFrame" title="">Clock: System</a>  
+<ul  >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#startingSlack27" target="srrFrame" title="">Starting Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#endingSlack28" target="srrFrame" title="">Ending Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#worstPaths29" target="srrFrame" title="">Worst Path Information</a>  </li></ul></li></ul></li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#resourceUsage30" target="srrFrame" title="">Resource Utilization</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/sgmii_ecp5_cck.rpt" target="srrFrame" title="">Constraint Checker Report (09:02 10-May)</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/stdout.log" target="srrFrame" title="">Session Log (09:02 10-May)</a>  
+<ul  ></ul></li>         </ul>
+        </li>
+   </ul>
+
+   <script type="text/javascript"> reportLogObj.generateLog("syn_results-menu")</script>
+
+  </body>
+ </html>
\ No newline at end of file

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/syntmp/statusReport.html b/gbe/cores/sgmii/sgmii_ecp5/syn_results/syntmp/statusReport.html
new file mode 100644 (file)
index 0000000..3cf8cd2
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/syntmp/statusReport.html
@@ -0,0 +1,115 @@
+<html> 
+                       <head>                  <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1" />
+                       <title>Project Status Summary Page</title>
+                       <link rel="stylesheet" type="text/css" href="projectstatuspage.css" />
+                       <script type = "text/javascript" src="projectstatuspage.js"></script>
+                       </head>
+
+                       <body style="background-color:#f0f0ff;">
+                       
+<table style="border:none;" width="100%" ><tr> <td class="outline">
+<table width="100%" border="0" cellspacing="0" cellpadding="0">             <thead class="tablehead"><tr><th colspan="4">Project Settings</th><tr> 
+ <tr> <td class="optionTitle" align="left"> Project Name</td> <td> sgmii_ecp5</td> <td class="optionTitle" align="left"> Device Name</td> <td> syn_results: Lattice ECP5UM : LFE5UM_25F</td> </tr>
+<tr> <td class="optionTitle" align="left"> Implementation Name</td> <td> syn_results</td> <td class="optionTitle" align="left"> Top Module</td> <td> sgmii_ecp5</td> </tr>
+                </thead> 
+                <tbody> <tr> <td class="optionTitle" align="left"> Pipelining</td> <td> 0</td> <td class="optionTitle" align="left"> Retiming</td> <td> 0</td> </tr>
+<tr> <td class="optionTitle" align="left"> Resource Sharing</td> <td> 1</td> <td class="optionTitle" align="left"> Fanout Guide</td> <td> 50</td> </tr>
+<tr> <td class="optionTitle" align="left"> Disable I/O Insertion</td> <td> 1</td> <td class="optionTitle" align="left"> Disable Sequential Optimizations</td> <td> 0</td> </tr>
+<tr> <td class="optionTitle" align="left"> Clock Conversion</td> <td> 1</td> <td class="optionTitle" align="left"> FSM Compiler</td> <td> 1</td> </tr>
+ 
+</tbody> 
+  </table><br>  <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
+                                  <thead class="tablehead"><tr><th   colspan="9">Run Status</th></tr></thead>
+         <tbody>
+               <tr>
+                       <th align="left" width="17%">Job Name</th>
+                       <th align="left">Status</th>
+                       <td class="lnote" align="center" title="Notes"></td>
+                       <td class="lwarn" align="center" title="Warnings"></td>
+                       <td class="lerror" align="center" title="Errors"></td>
+                       <th align="left">CPU Time</th>
+                       <th align="left">Real Time</th>
+                       <th align="left">Memory</th>
+                       <th align="left">Date/Time</th>
+         </tr>
+  <tr>
+  <td class="optionTitle"> (compiler)</td><td>Complete</td>
+ <td>15</td>
+ <td>76</td>
+<td>0</td>
+<td>-</td>
+<td>00m:02s</td>
+<td>-</td>
+<td><font size="-1">5/10/19</font><br/><font size="-2">9:02 AM</font></td>
+</tr> 
+
+ <tr>
+  <td class="optionTitle"> (premap)</td><td>Complete</td>
+ <td>9</td>
+ <td>3</td>
+<td>0</td>
+<td>0m:00s</td>
+<td>0m:00s</td>
+<td>144MB</td>
+<td><font size="-1">5/10/19</font><br/><font size="-2">9:02 AM</font></td>
+</tr> 
+
+ <tr>
+  <td class="optionTitle"> (fpga_mapper)</td><td>Complete</td>
+ <td>22</td>
+ <td>4</td>
+<td>0</td>
+<td>0m:03s</td>
+<td>0m:03s</td>
+<td>153MB</td>
+<td><font size="-1">5/10/19</font><br/><font size="-2">9:02 AM</font></td>
+</tr> 
+
+<tr>
+  <td class="optionTitle">Multi-srs Generator</td>
+  <td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td></td><td class="empty"></td><td class="empty"></td><td><font size="-1">5/10/19</font><br/><font size="-2">9:02 AM</font></td>              </tbody>
+     </table>
+ <br> 
+ <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
+                                  <thead class="tablehead"><tr><th   colspan="4">Area Summary</th></tr></thead>
+<tfoot> <tr> <td class="optionTitle" colspan="4"></td></tr> 
+ </tfoot> 
+ <tbody> <tr> 
+<td title ="Total Register bits used" class="optionTitle" align="left">Register bits</td> <td>221</td>
+<td title ="Total I/O cells used" class="optionTitle" align="left">I/O cells</td> <td>0</td>
+</tr>
+<tr> 
+<td title ="Total Block RAMs used" class="optionTitle" align="left">Block RAMs
+(v_ram)</td> <td>0</td>
+<td title ="Total DSPs used" class="optionTitle" align="left">DSPs
+(dsp_used)</td> <td>0</td>
+</tr>
+<tr> 
+<td title ="Total ORCA LUTs used" class="optionTitle" align="left">ORCA LUTs
+(total_luts)</td> <td>154</td>
+<td class="optionTitle"></td><td></td></tr> 
+</tbody>
+    </table><br>
+ <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
+                                  <thead class="tablehead"><tr><th   colspan="4">Timing Summary</th></tr></thead>
+<tfoot> <tr> <td class="optionTitle" colspan="2"></td></tr> 
+ </tfoot> 
+<tbody> 
+   <tr><th class="optionTitle" align= "left ">Clock Name</th><th class="optionTitle" align= "left ">Req Freq</th><th class="optionTitle" align= "left ">Est Freq</th><th class="optionTitle" align= "left ">Slack</th></tr> 
+<tr> <td  align="left">sgmii_ecp5|pll_refclki</td><td  align="left">100.0 MHz</td><td  align="left">168.9 MHz</td><td  align="left">4.079</td></tr> 
+<tr> <td  align="left">sgmii_ecp5|rxrefclk</td><td  align="left">100.0 MHz</td><td  align="left">167.9 MHz</td><td  align="left">4.043</td></tr> 
+<tr> <td  align="left">sgmii_ecp5|tx_pclk_inferred_clock</td><td  align="left">100.0 MHz</td><td  align="left">237.5 MHz</td><td  align="left">5.789</td></tr> 
+<tr> <td  align="left">System</td><td  align="left">100.0 MHz</td><td  align="left">840.7 MHz</td><td  align="left">8.810</td></tr> 
+</tbody> 
+ </table>
+<br>
+ <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
+                                  <thead class="tablehead"><tr><th   colspan="4">Optimizations Summary</th></tr></thead>
+ <tbody> <tr> 
+<td title ="Non-gated/non-generated clock trees / Gated/generated clock trees" class="optionTitle" align="left">Combined Clock Conversion</td> <td>3 / 0</td>
+<td class="optionTitle"></td><td></td></tr> 
+</tbody>
+    </table><br>
+<br> 
+</td></tr></table></body> 
+ </html>
\ No newline at end of file

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/.cckTransfer b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/.cckTransfer
new file mode 100644 (file)
index 0000000..b4c45f7
Binary files /dev/null and b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/.cckTransfer differ

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/_mh_info b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/_mh_info
new file mode 100644 (file)
index 0000000..1a725a4
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/_mh_info
@@ -0,0 +1,2 @@
+|/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/layer1.info|
+|2|

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/_verilog_hintfile b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/_verilog_hintfile
new file mode 100644 (file)
index 0000000..d5a098c
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/_verilog_hintfile
@@ -0,0 +1,69 @@
+%%% protect protected_file
+#OPTIONS:"|-bldtbl|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
+#CUR:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":1557471728
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599
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+M0bkR_0G#8CsCs#_#O0_RH4
+M0bkR_0Gb_O#s_#0O
+R4Fbk0kb0RDDD_F4DR
+0FkbRk0s_#D0sG_84$R
+bHMks0RGC_#s#8C_0s#_4OR
+bHMks0RGO_b##_s0R_O4k
+F00bkRDs#__sGsR8$4M
+C88lFk
+DC
+
+@ 

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer0.fdep b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer0.fdep
new file mode 100644 (file)
index 0000000..23da417
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer0.fdep
@@ -0,0 +1,33 @@
+#defaultlanguage:vhdl
+#OPTIONS:"|-mixedhdl|-top|sgmii_ecp5|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610
+#CUR:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":1557471728
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599
+0 "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd" vhdl
+
+# Dependency Lists (Uses list)
+0 -1
+
+# Dependency Lists (Users Of)
+0 -1
+
+# Design Unit to File Association
+arch work sgmii_ecp5 v1 0
+module work sgmii_ecp5 0
+
+# Unbound Instances to File Association
+inst work sgmii_ecp5 sgmii_ecp5sll_core 0
+inst work sgmii_ecp5 sgmii_ecp5rsl_core 0
+inst work sgmii_ecp5 dcua 0
+
+
+# Configuration files used

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer0.fdeporig b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer0.fdeporig
new file mode 100644 (file)
index 0000000..7f50852
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer0.fdeporig
@@ -0,0 +1,29 @@
+#defaultlanguage:vhdl
+#OPTIONS:"|-mixedhdl|-top|sgmii_ecp5|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610
+#CUR:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":1557471728
+0 "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd" vhdl
+
+# Dependency Lists (Uses list)
+0 -1
+
+# Dependency Lists (Users Of)
+0 -1
+
+# Design Unit to File Association
+arch work sgmii_ecp5 v1 0
+module work sgmii_ecp5 0
+
+# Unbound Instances to File Association
+inst work sgmii_ecp5 sgmii_ecp5sll_core 0
+inst work sgmii_ecp5 sgmii_ecp5rsl_core 0
+inst work sgmii_ecp5 dcua 0

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer0.srs b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer0.srs
new file mode 100644 (file)
index 0000000..20f66e0
Binary files /dev/null and b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer0.srs differ

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer0.tlg b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer0.tlg
new file mode 100644 (file)
index 0000000..79092c2
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer0.tlg
@@ -0,0 +1,2 @@
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1.
+Post processing for work.sgmii_ecp5.v1

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer0.tlg.db b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer0.tlg.db
new file mode 100644 (file)
index 0000000..28759a6
Binary files /dev/null and b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer0.tlg.db differ

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer1.fdep b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer1.fdep
new file mode 100644 (file)
index 0000000..ede843b
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer1.fdep
@@ -0,0 +1,22 @@
+#OPTIONS:"|-mixedhdl|-modhint|/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/_verilog_hintfile|-top|work.sgmii_ecp5sll_core|-top|work.sgmii_ecp5rsl_core|-mpparams|/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/_mh_params|-layerid|1|-orig_srs|/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/|-I|/home/soft/lattice/diamond/3.10_x64/synpbase/lib|-v2001|-devicelib|/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v|-devicelib|/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_ver":1542167761
+#CUR:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/_verilog_hintfile":1557471729
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v":1542167595
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v":1542167597
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v":1542167630
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v":1542167630
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v":1542167630
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh":1542167630
+#CUR:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1557471728
+#numinternalfiles:6
+#defaultlanguage:verilog
+0                      "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v" verilog
+#Dependency Lists(Uses List)
+0 -1
+#Dependency Lists(Users Of)
+0 -1
+#Design Unit to File Association
+module work sgmii_ecp5rsl_core 0
+module work sync 0
+module work sgmii_ecp5sll_core 0
+#Unbound instances to file Association.

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer1.fdepxmr b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer1.fdepxmr
new file mode 100644 (file)
index 0000000..37d628b
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer1.fdepxmr
@@ -0,0 +1 @@
+#XMR Information

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer1.info b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer1.info
new file mode 100644 (file)
index 0000000..ddcec68
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer1.info
@@ -0,0 +1,2 @@
+|work.sgmii_ecp5rsl_core|parameter pnum_channels 1;,parameter pprotocol "GBE";,parameter pserdes_mode "RX AND TX";,parameter pport_tx_rdy "ENABLED";,parameter pwait_tx_rdy 3000;,parameter pport_rx_rdy "ENABLED";,parameter pwait_rx_rdy 3000;|
+|work.sgmii_ecp5sll_core|parameter PPROTOCOL "GBE";,parameter PLOL_SETTING 0;,parameter PDYN_RATE_CTRL "DISABLED";,parameter PPCIE_MAX_RATE "2.5";,parameter PDIFF_VAL_LOCK 39;,parameter PDIFF_VAL_UNLOCK 78;,parameter PPCLK_TC 131072;,parameter PDIFF_DIV11_VAL_LOCK 0;,parameter PDIFF_DIV11_VAL_UNLOCK 0;,parameter PPCLK_DIV11_TC 0;|

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer1.srs b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer1.srs
new file mode 100644 (file)
index 0000000..5f52009
Binary files /dev/null and b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer1.srs differ

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer1.tlg b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer1.tlg
new file mode 100644 (file)
index 0000000..52a25c2
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer1.tlg
@@ -0,0 +1,252 @@
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work.
+
+       PDATA_RST_VAL=32'b00000000000000000000000000000000
+   Generated name = sync_0s
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work.
+
+       PPROTOCOL=24'b010001110100001001000101
+       PLOL_SETTING=32'b00000000000000000000000000000000
+       PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100
+       PPCIE_MAX_RATE=24'b001100100010111000110101
+       PDIFF_VAL_LOCK=32'b00000000000000000000000000100111
+       PDIFF_VAL_UNLOCK=32'b00000000000000000000000001001110
+       PPCLK_TC=32'b00000000000000100000000000000000
+       PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000
+       PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000
+       PPCLK_DIV11_TC=32'b00000000000000000000000000000000
+       LPLL_LOSS_ST=2'b00
+       LPLL_PRELOSS_ST=2'b01
+       LPLL_PRELOCK_ST=2'b10
+       LPLL_LOCK_ST=2'b11
+       LRCLK_TC=16'b1111111111111111
+       LRCLK_TC_PUL_WIDTH=16'b0000000000110010
+       LHB_WAIT_CNT=8'b11111111
+       LPCLK_TC_0=32'b00000000000000001000000000000000
+       LPCLK_TC_1=32'b00000000000000010000000000000000
+       LPCLK_TC_2=32'b00000000000000100000000000000000
+       LPCLK_TC_3=32'b00000000000000101000000000000000
+       LPCLK_TC_4=32'b00000000000000010000000000000000
+       LPDIFF_LOCK_00=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_10=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_20=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_30=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_40=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_01=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_11=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_21=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_31=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_41=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_02=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_12=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_22=32'b00000000000000000000000011000100
+       LPDIFF_LOCK_32=32'b00000000000000000000000011110101
+       LPDIFF_LOCK_42=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_03=32'b00000000000000000000000010000011
+       LPDIFF_LOCK_13=32'b00000000000000000000000100000110
+       LPDIFF_LOCK_23=32'b00000000000000000000001000001100
+       LPDIFF_LOCK_33=32'b00000000000000000000001010001111
+       LPDIFF_LOCK_43=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011
+       LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110
+       LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010
+       LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001
+       LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111
+       LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000
+       LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000
+       LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000
+       LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100
+       LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001
+       LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010
+       LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111
+       LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001
+   Generated name = sgmii_ecp5sll_core_Z1_layer1
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment.
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work.
+
+       pnum_channels=32'b00000000000000000000000000000001
+       pprotocol=24'b010001110100001001000101
+       pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
+       pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_tx_rdy=32'b00000000000000000000101110111000
+       pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_rx_rdy=32'b00000000000000000000101110111000
+       wa_num_cycles=32'b00000000000000000000010000000000
+       dac_num_cycles=32'b00000000000000000000000000000011
+       lreset_pwidth=32'b00000000000000000000000000000011
+       lwait_b4_trst=32'b00000000000010111110101111000010
+       lwait_b4_trst_s=32'b00000000000000000000001100001101
+       lplol_cnt_width=32'b00000000000000000000000000010100
+       lwait_after_plol0=32'b00000000000000000000000000000100
+       lwait_b4_rrst=32'b00000000000000101100000000000000
+       lrrst_wait_width=32'b00000000000000000000000000010100
+       lwait_after_rrst=32'b00000000000011000011010100000000
+       lwait_b4_rrst_s=32'b00000000000000000000000111001100
+       lrlol_cnt_width=32'b00000000000000000000000000010011
+       lwait_after_lols=32'b00000000000000001100010000000000
+       lwait_after_lols_s=32'b00000000000000000000000010010110
+       llols_cnt_width=32'b00000000000000000000000000010010
+       lrdb_max=32'b00000000000000000000000000001111
+       ltxr_wait_width=32'b00000000000000000000000000001100
+       lrxr_wait_width=32'b00000000000000000000000000001100
+   Generated name = sgmii_ecp5rsl_core_Z2_layer1
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 6 to 4 of genblk5.rdiff_comp_unlock[6:3]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[3]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers.
+@N: CL201 :"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state.
+Extracted state machine for register sll_state
+State machine has 4 reachable states with original encodings of:
+   00
+   01
+   10
+   11

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer1.tlg.db b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/layer1.tlg.db
new file mode 100644 (file)
index 0000000..d0d562d
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diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/modulechange.db b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/modulechange.db
new file mode 100644 (file)
index 0000000..371c38b
Binary files /dev/null and b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/modulechange.db differ

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/modulechange_mixhdl/layer0/modulechange.db b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/modulechange_mixhdl/layer0/modulechange.db
new file mode 100644 (file)
index 0000000..aa7cae8
Binary files /dev/null and b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/modulechange_mixhdl/layer0/modulechange.db differ

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/modulechange_mixhdl/layer1/modulechange.db b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/modulechange_mixhdl/layer1/modulechange.db
new file mode 100644 (file)
index 0000000..9ca4962
Binary files /dev/null and b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/modulechange_mixhdl/layer1/modulechange.db differ

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.fdep b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.fdep
new file mode 100644 (file)
index 0000000..59a2556
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.fdep
@@ -0,0 +1,37 @@
+#OPTIONS:"|-mixedhdl|-top|sgmii_ecp5|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610
+#CUR:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd":1557471728
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599
+#OPTIONS:"|-mixedhdl|-modhint|/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/_verilog_hintfile|-top|work.sgmii_ecp5sll_core|-top|work.sgmii_ecp5rsl_core|-mpparams|/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/_mh_params|-layerid|1|-orig_srs|/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/|-I|/home/soft/lattice/diamond/3.10_x64/synpbase/lib|-v2001|-devicelib|/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v|-devicelib|/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_ver":1542167761
+#CUR:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/syn_results/synwork/_verilog_hintfile":1557471729
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v":1542167595
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v":1542167597
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v":1542167630
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v":1542167630
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v":1542167630
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh":1542167630
+#CUR:"/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v":1557471728
+0                      "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5.vhd" vhdl
+1                      "/home/adrian/git/trb5sc/template/project/sgmii/sgmii_ecp5/sgmii_ecp5_softlogic.v" verilog
+#Dependency Lists(Uses List)
+0 1
+1 -1
+#Dependency Lists(Users Of)
+0 -1
+1 0
+#Design Unit to File Association
+module work sgmii_ecp5sll_core 1
+module work sync 1
+module work sgmii_ecp5rsl_core 1
+module work sgmii_ecp5 0
+arch work sgmii_ecp5 v1 0

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.linkerlog b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.linkerlog
new file mode 100644 (file)
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diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs
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diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm
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diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult.srs b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult.srs
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diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult_srs/1.srs b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult_srs/1.srs
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diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult_srs/fileinfo.srs b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult_srs/fileinfo.srs
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diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult_srs/skeleton.srs b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult_srs/skeleton.srs
new file mode 100644 (file)
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diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_prem.fse b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_prem.fse
new file mode 100644 (file)
index 0000000..cc147f0
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_prem.fse
@@ -0,0 +1,12 @@
+
+fsm_encoding {61801018011} sequential
+
+fsm_state_encoding {61801018011} LPLL_LOSS_ST {00}
+
+fsm_state_encoding {61801018011} LPLL_PRELOSS_ST {01}
+
+fsm_state_encoding {61801018011} LPLL_PRELOCK_ST {10}
+
+fsm_state_encoding {61801018011} LPLL_LOCK_ST {11}
+
+fsm_registers {61801018011} {sll_state[1]}  {sll_state[0]} 

diff --git a/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_prem.srd b/gbe/cores/sgmii/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_prem.srd
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index 0000000..d37603c
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diff --git a/gbe/cores/sgmii/sgmii_tmpl.v b/gbe/cores/sgmii/sgmii_tmpl.v
new file mode 100644 (file)
index 0000000..f02caf0
--- /dev/null
+++ b/gbe/cores/sgmii/sgmii_tmpl.v
@@ -0,0 +1,6 @@
+//Verilog instantiation template
+
+sgmii _inst (.PCSD_hdinn(), .PCSD_hdinp(), .PCSD_hdoutn(), .PCSD_hdoutp(), 
+      .sgmii_ecp5_hdinn(), .sgmii_ecp5_hdinp(), .sgmii_ecp5_hdoutn(), 
+      .sgmii_ecp5_hdoutp(), .pll_in125_out125_out33_CLKI(), .pll_in125_out125_out33_CLKOP(), 
+      .pll_in125_out125_out33_CLKOS(), .pll_in125_out125_out33_LOCK());
\ No newline at end of file

diff --git a/gbe/cores/sgmii/tsmac/pmi_ram_dpEbnonessdn208256208256p138702ef.ngo b/gbe/cores/sgmii/tsmac/pmi_ram_dpEbnonessdn208256208256p138702ef.ngo
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diff --git a/gbe/cores/sgmii/tsmac/pmi_ram_dpEbnonessdn96649664p13506f63.ngo b/gbe/cores/sgmii/tsmac/pmi_ram_dpEbnonessdn96649664p13506f63.ngo
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diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/models/ecp5um/JTAGG.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/models/ecp5um/JTAGG.v
new file mode 100644 (file)
index 0000000..100dd98
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/models/ecp5um/JTAGG.v
@@ -0,0 +1,8 @@
+module JTAGG (\r
+input TCK, TMS, TDI, JTDO2, JTDO1,\r
+output TDO, JTDI, JTCK, JRTI2, JRTI1,\r
+output JSHIFT, JUPDATE, JRSTN, JCE2, JCE1 )\r
+/* synthesis syn_black_box syn_noprune=1 */;  //synthesis syn_black_box\r
+parameter ER1 = "ENABLED";\r
+parameter ER2 = "ENABLED";\r
+endmodule\r

diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/models/ecp5um/JTAG_ECP5UM.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/models/ecp5um/JTAG_ECP5UM.v
new file mode 100644 (file)
index 0000000..ac5e46d
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/models/ecp5um/JTAG_ECP5UM.v
@@ -0,0 +1,219 @@
+module JTAG_ECP5UM(\r
+       grst_ni,\r
+       tck,\r
+       tms,\r
+       tdi,\r
+       tdo,\r
+       PC_Clk,\r
+       PC_Data_In,\r
+       PC_Ready,\r
+       PC_Reset,\r
+       Cnt,\r
+       PC_Data_Out,\r
+       PC_Ack,\r
+       PC_Error);\r
+\r
+  input            grst_ni;\r
+  input            tck;\r
+  input            tms;\r
+  input            tdi;\r
+  output    tdo;\r
+  input     PC_Data_Out;\r
+  input     PC_Ack;\r
+  input     PC_Error;\r
+  output    PC_Clk;\r
+  output    PC_Data_In;\r
+  output    PC_Ready;\r
+  output    PC_Reset;\r
+  output    Cnt;\r
+  wire      JTCK;\r
+  wire      JTDI;\r
+  wire      JSHIFT;\r
+  wire      JRSTN;\r
+  wire      JCE1;\r
+  reg       JTDI_x;\r
+  reg       JSHIFT_x;\r
+  reg       JRSTN_x;\r
+  reg       JCE1_x;\r
+  reg       JTDO1;\r
+  reg[5:0]  Count;\r
+  reg[2:0]  State;\r
+  reg       JTD01_a;\r
+  reg       JTD01_b;\r
+  reg       PC_Ready_i;\r
+  reg       PC_Clk_a;\r
+  reg       PC_Clk_b;\r
+  reg       PC_Reset;\r
+  reg       PC_Data_In;\r
+\r
+JTAGG JTAGG(\r
+\r
+         // External Pad Interface\r
+       .TCK            (tck), \r
+       .TMS            (tms), \r
+       .TDI            (tdi),\r
+       .TDO            (tdo),\r
+\r
+\r
+       .JTDO1          (JTDO1),\r
+       .JTDO2          (1'b0),\r
+       .JTDI           (JTDI),\r
+       .JTCK           (JTCK),\r
+       .JRTI1          (),\r
+       .JRTI2          (),\r
+       .JSHIFT         (JSHIFT),\r
+       .JUPDATE        (),\r
+       .JRSTN          (JRSTN),\r
+       .JCE1           (JCE1),\r
+       .JCE2           ()\r
+\r
+// Oringal XP I/O List\r
+        // .JTDO1  (JTDO1),\r
+       // .JTDO2  (0),\r
+       // .JTCK   (JTCK),\r
+       // .JRTI1  (),\r
+       // .JRTI2  (),\r
+       // .JTDI   (JTDI),\r
+       // .JSHIFT (JSHIFT),\r
+       // .JUPDATE(),\r
+       // .JRSTN  (JRSTN),\r
+       // .JCE1   (JCE1),\r
+       // .JCE2   ()\r
+\r
+\r
+);\r
+\r
+\r
+initial\r
+begin\r
+//   PC_Clk_a  = 1'b0;\r
+//   State = 3'd0;\r
+//   Count = 6'd0;\r
+end\r
+\r
+  always @(negedge JTCK or negedge grst_ni)        // Delayed Data\r
+  begin\r
+    if (~grst_ni) begin\r
+      JTDI_x    <= 1'b0;\r
+      JSHIFT_x  <= 1'b0;\r
+      JRSTN_x   <= 1'b0;\r
+      JCE1_x    <= 1'b0;\r
+    end else begin\r
+      JTDI_x    <= JTDI;\r
+      JSHIFT_x  <= JSHIFT;\r
+      JRSTN_x   <= JRSTN;\r
+      JCE1_x    <= JCE1;\r
+    end\r
+  end\r
+\r
+  always @(posedge JTCK or negedge grst_ni) begin        // Count\r
+    if (~grst_ni) begin\r
+      Count    <= 6'b0;\r
+    end else begin    \r
+           if (JCE1_x == 1) begin\r
+               if (JSHIFT_x == 0) begin\r
+                 Count <= 0;\r
+         end else begin\r
+                 Count <= Count + 1;\r
+               end\r
+         end\r
+    end\r
+  end\r
+\r
+//* kes (011006): Only states 6, 5, and 1 are actualy used. First\r
+//* three bits of tdi provide opcode and determine selective clock\r
+//* assertion to target below. These are always required.\r
+always @(posedge JTCK or negedge grst_ni) begin                                    \r
+    if (~grst_ni) begin\r
+       State <= 3'b0;\r
+    end else begin\r
+       if ((Count == 1) | (Count == 2) | (Count == 3)) begin       // 0 1 0 Ph2 of Write\r
+        State <= {State[1:0], JTDI_x};                       // 0 1 1 (Don't Care)\r
+      end                                                      // 1 0 0 (Don't Care)\r
+    end\r
+  end\r
+                                                             // 1 0 1 Ph1 of Read\r
+                                                             // 1 1 0 Ph1 of Write\r
+                                                             // 1 1 1 (Don't Care)\r
+\r
+  always @(posedge JTCK or negedge grst_ni) begin\r
+    if (~grst_ni) begin\r
+       JTDO1 <= 1'b0;\r
+       JTD01_b <= 1'b0;\r
+       JTD01_a <= 1'b0;\r
+    end else begin\r
+      if (Count == 4) begin\r
+          JTDO1   <= PC_Ack;\r
+          JTD01_b <= PC_Error;\r
+      end else begin\r
+          JTDO1   <= JTD01_b;\r
+          JTD01_b <= JTD01_a;\r
+      end\r
+      JTD01_a     <= PC_Data_Out;\r
+    end\r
+  end\r
+\r
+  always @(posedge JTCK or negedge grst_ni) begin\r
+    if (~grst_ni) begin\r
+      PC_Data_In    <= 1'b0;\r
+      PC_Reset    <= 1'b0;\r
+    end else begin\r
+           if (Count >  3) begin\r
+               PC_Data_In    <= JTDI_x;              // PC_Data_In\r
+           end\r
+      PC_Reset <= JRSTN_x;             // PC_Reset\r
+    end\r
+  end\r
+\r
+//* kes (011006): Writes and Phase 1 read operations require the full 55+\r
+//* (actually ~58) cycles of tdi even though many tdi bits/fields are \r
+//* unused & not passed on to the target. Done to simplify I guess.\r
+//* tdi bits are selectively passed by turning on and off the clock \r
+//* used by  the target. Phase 2 reads are shorter - see below.\r
+  always @(posedge JTCK or negedge grst_ni) begin\r
+    if (~grst_ni) begin\r
+      PC_Clk_a    <= 1'b0;\r
+    end else begin\r
+      if (((State    == 'b001) & (Count >   3) & (Count <= 12)) |      // Read Data (+ extra clock at 12)\r
+          ((State    == 'b110) & (Count >  16) & (Count <= 24)) |      // Write Data\r
+          ((State[2] ==    1 ) & (Count >  30) & (Count <= 48)) |      // Address\r
+         ((State    == 'b010) & (Count == 12)                  )) begin    // (extra clock at 12 for writes)\r
+         if (PC_Clk_a == 1) begin\r
+            PC_Clk_a    <= 0;\r
+          end else begin\r
+            PC_Clk_a    <= 1;\r
+         end\r
+      end\r
+    end\r
+  end\r
+\r
+  always @(negedge JTCK or negedge grst_ni)\r
+    if (~grst_ni) begin\r
+      PC_Clk_b    <= 1'b0;\r
+    end else begin\r
+      PC_Clk_b <= PC_Clk_a;\r
+    end\r
+\r
+//* kes (011006): Ready only generted for writes and phase 1 reads. Phase2\r
+//* reads do not require additional work inside orcastra.v other than to\r
+//* shift data back when this models selectively provides clocks as part\r
+//* of the phase 2 operation. It can be shorter then than write & ph1 write \r
+  always @(posedge JTCK or negedge grst_ni) begin\r
+   if (~grst_ni) begin\r
+      PC_Ready_i    <= 1'b0;\r
+   end else begin\r
+       if ((Count == 55) & (State[2] == 1)) begin\r
+            PC_Ready_i    <= 1;\r
+        end else begin\r
+           if (Count == 3) begin\r
+                PC_Ready_i    <= 0;\r
+           end\r
+       end\r
+   end\r
+ end\r
+\r
+  assign PC_Ready = PC_Ready_i;\r
+  assign PC_Clk   = PC_Clk_a ^ PC_Clk_b;\r
+  assign Cnt      = Count;\r
+\r
+endmodule\r

diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/models/ecp5um/rxmac_clk_pll.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/models/ecp5um/rxmac_clk_pll.v
new file mode 100644 (file)
index 0000000..7d2dfbe
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/models/ecp5um/rxmac_clk_pll.v
@@ -0,0 +1,87 @@
+/* Verilog netlist generated by SCUBA Diamond_2.2_Beta (60) */
+/* Module Version: 5.3 */
+/* D:\lscc\diamond\2.2\ispfpga\bin\nt\scuba.exe -w -n rxmac_clk_pll -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 125 -fclkop 125 -fclkop_tol 0.0 -phasep 0 -fclkos 125 -fclkos_tol 0.0 -phases 0 -fclkos2 62.5 -fclkos2_tol 0.0 -phases2 0 -phase_cntl STATIC -rst -lock -fb_mode 9 -e  */
+/* Tue Mar 12 11:17:39 2013 */
+
+
+`timescale 1 ns / 1 ps
+module rxmac_clk_pll (CLK, RESET, CLKFB, CLKOP, CLKOS, CLKOK, LOCK)/* synthesis syn_noprune=1 *//* synthesis NGD_DRC_MASK=1 */;// exemplar attribute rxmac_clk_pll dont_touch true 
+    input wire CLK;
+    input wire CLKFB;
+    input wire RESET;
+    output wire CLKOP;
+    output wire CLKOS;
+    output wire CLKOK;
+    output wire LOCK;
+
+    wire REFCLK;
+    wire CLKOS2_t;
+    wire CLKOS_t;
+    wire CLKOP_t;
+    wire scuba_vhi;
+    wire scuba_vlo;
+
+    VHI scuba_vhi_inst (.Z(scuba_vhi));
+
+    VLO scuba_vlo_inst (.Z(scuba_vlo));
+
+    defparam PLLInst_0.PLLRST_ENA = "ENABLED" ;
+    defparam PLLInst_0.INTFB_WAKE = "DISABLED" ;
+    defparam PLLInst_0.STDBY_ENABLE = "DISABLED" ;
+    defparam PLLInst_0.DPHASE_SOURCE = "DISABLED" ;
+    defparam PLLInst_0.CLKOS3_FPHASE = 0 ;
+    defparam PLLInst_0.CLKOS3_CPHASE = 0 ;
+    defparam PLLInst_0.CLKOS2_FPHASE = 0 ;
+    defparam PLLInst_0.CLKOS2_CPHASE = 9 ;
+    defparam PLLInst_0.CLKOS_FPHASE = 0 ;
+    defparam PLLInst_0.CLKOS_CPHASE = 4 ;
+    defparam PLLInst_0.CLKOP_FPHASE = 0 ;
+    defparam PLLInst_0.CLKOP_CPHASE = 4 ;
+    defparam PLLInst_0.PLL_LOCK_MODE = 0 ;
+    defparam PLLInst_0.CLKOS_TRIM_DELAY = 0 ;
+    defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING" ;
+    defparam PLLInst_0.CLKOP_TRIM_DELAY = 0 ;
+    defparam PLLInst_0.CLKOP_TRIM_POL = "FALLING" ;
+    defparam PLLInst_0.OUTDIVIDER_MUXD = "DIVD" ;
+    defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED" ;
+    defparam PLLInst_0.OUTDIVIDER_MUXC = "DIVC" ;
+    defparam PLLInst_0.CLKOS2_ENABLE = "ENABLED" ;
+    defparam PLLInst_0.OUTDIVIDER_MUXB = "DIVB" ;
+    defparam PLLInst_0.CLKOS_ENABLE = "ENABLED" ;
+    defparam PLLInst_0.OUTDIVIDER_MUXA = "DIVA" ;
+    defparam PLLInst_0.CLKOP_ENABLE = "ENABLED" ;
+    defparam PLLInst_0.CLKOS3_DIV = 1 ;
+    defparam PLLInst_0.CLKOS2_DIV = 10 ;
+    defparam PLLInst_0.CLKOS_DIV = 5 ;
+    defparam PLLInst_0.CLKOP_DIV = 5 ;
+    defparam PLLInst_0.CLKFB_DIV = 1 ;
+    defparam PLLInst_0.CLKI_DIV = 1 ;
+    defparam PLLInst_0.FEEDBK_PATH = "USERCLOCK" ;
+    EHXPLLL PLLInst_0 (.CLKI(CLK), .CLKFB(CLKFB), .PHASESEL1(scuba_vlo), 
+        .PHASESEL0(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo), 
+        .PHASELOADREG(scuba_vlo), .STDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo), 
+        .RST(RESET), .ENCLKOP(scuba_vlo), .ENCLKOS(scuba_vlo), .ENCLKOS2(scuba_vlo), 
+        .ENCLKOS3(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(CLKOS_t), .CLKOS2(CLKOS2_t), 
+        .CLKOS3(), .LOCK(LOCK), .INTLOCK(), .REFCLK(REFCLK), .CLKINTFB())
+             /* synthesis FREQUENCY_PIN_CLKOS2="62.500000" */
+             /* synthesis FREQUENCY_PIN_CLKOS="125.000000" */
+             /* synthesis FREQUENCY_PIN_CLKOP="125.000000" */
+             /* synthesis FREQUENCY_PIN_CLKI="125.000000" */
+             /* synthesis ICP_CURRENT="13" */
+             /* synthesis LPF_RESISTOR="24" */;
+
+    assign CLKOK = CLKOS2_t;
+    assign CLKOS = CLKOS_t;
+    assign CLKOP = CLKOP_t;
+
+
+    // exemplar begin
+    // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOS2 62.500000
+    // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOS 125.000000
+    // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOP 125.000000
+    // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKI 125.000000
+    // exemplar attribute PLLInst_0 ICP_CURRENT 13
+    // exemplar attribute PLLInst_0 LPF_RESISTOR 24
+    // exemplar end
+
+endmodule

diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/models/ecp5um/txmac_clk_pll.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/models/ecp5um/txmac_clk_pll.v
new file mode 100644 (file)
index 0000000..845300d
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/models/ecp5um/txmac_clk_pll.v
@@ -0,0 +1,87 @@
+/* Verilog netlist generated by SCUBA Diamond_2.2_Beta (60) */
+/* Module Version: 5.3 */
+/* D:\lscc\diamond\2.2\ispfpga\bin\nt\scuba.exe -w -n txmac_clk_pll -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 125 -fclkop 125 -fclkop_tol 0.0 -phasep 0 -fclkos 125 -fclkos_tol 0.0 -phases 0 -fclkos2 62.5 -fclkos2_tol 0.0 -phases2 0 -phase_cntl STATIC -rst -lock -fb_mode 9 -e  */
+/* Tue Mar 12 11:17:39 2013 */
+
+
+`timescale 1 ns / 1 ps
+module txmac_clk_pll (CLK, RESET, CLKFB, CLKOP, CLKOS, LOCK)/* synthesis syn_noprune=1 *//* synthesis NGD_DRC_MASK=1 */;// exemplar attribute txmac_clk_pll dont_touch true 
+    input wire CLK;
+    input wire CLKFB;
+    input wire RESET;
+    output wire CLKOP;
+    output wire CLKOS;
+    output wire LOCK;
+
+    wire REFCLK;
+    wire CLKOS2_t;
+    wire CLKOS_t;
+    wire CLKOP_t;
+    wire CLKOK;
+    wire scuba_vhi;
+    wire scuba_vlo;
+
+    VHI scuba_vhi_inst (.Z(scuba_vhi));
+
+    VLO scuba_vlo_inst (.Z(scuba_vlo));
+
+    defparam PLLInst_0.PLLRST_ENA = "ENABLED" ;
+    defparam PLLInst_0.INTFB_WAKE = "DISABLED" ;
+    defparam PLLInst_0.STDBY_ENABLE = "DISABLED" ;
+    defparam PLLInst_0.DPHASE_SOURCE = "DISABLED" ;
+    defparam PLLInst_0.CLKOS3_FPHASE = 0 ;
+    defparam PLLInst_0.CLKOS3_CPHASE = 0 ;
+    defparam PLLInst_0.CLKOS2_FPHASE = 0 ;
+    defparam PLLInst_0.CLKOS2_CPHASE = 9 ;
+    defparam PLLInst_0.CLKOS_FPHASE = 4 ;
+    defparam PLLInst_0.CLKOS_CPHASE = 6 ;
+    defparam PLLInst_0.CLKOP_FPHASE = 0 ;
+    defparam PLLInst_0.CLKOP_CPHASE = 4 ;
+    defparam PLLInst_0.PLL_LOCK_MODE = 0 ;
+    defparam PLLInst_0.CLKOS_TRIM_DELAY = 0 ;
+    defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING" ;
+    defparam PLLInst_0.CLKOP_TRIM_DELAY = 0 ;
+    defparam PLLInst_0.CLKOP_TRIM_POL = "FALLING" ;
+    defparam PLLInst_0.OUTDIVIDER_MUXD = "DIVD" ;
+    defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED" ;
+    defparam PLLInst_0.OUTDIVIDER_MUXC = "DIVC" ;
+    defparam PLLInst_0.CLKOS2_ENABLE = "ENABLED" ;
+    defparam PLLInst_0.OUTDIVIDER_MUXB = "DIVB" ;
+    defparam PLLInst_0.CLKOS_ENABLE = "ENABLED" ;
+    defparam PLLInst_0.OUTDIVIDER_MUXA = "DIVA" ;
+    defparam PLLInst_0.CLKOP_ENABLE = "ENABLED" ;
+    defparam PLLInst_0.CLKOS3_DIV = 1 ;
+    defparam PLLInst_0.CLKOS2_DIV = 10 ;
+    defparam PLLInst_0.CLKOS_DIV = 5 ;
+    defparam PLLInst_0.CLKOP_DIV = 5 ;
+    defparam PLLInst_0.CLKFB_DIV = 1 ;
+    defparam PLLInst_0.CLKI_DIV = 1 ;
+    defparam PLLInst_0.FEEDBK_PATH = "USERCLOCK" ;
+    EHXPLLL PLLInst_0 (.CLKI(CLK), .CLKFB(CLKFB), .PHASESEL1(scuba_vlo), 
+        .PHASESEL0(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo), 
+        .PHASELOADREG(scuba_vlo), .STDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo), 
+        .RST(RESET), .ENCLKOP(scuba_vlo), .ENCLKOS(scuba_vlo), .ENCLKOS2(scuba_vlo), 
+        .ENCLKOS3(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(CLKOS_t), .CLKOS2(CLKOS2_t), 
+        .CLKOS3(), .LOCK(LOCK), .INTLOCK(), .REFCLK(REFCLK), .CLKINTFB())
+             /* synthesis FREQUENCY_PIN_CLKOS2="62.500000" */
+             /* synthesis FREQUENCY_PIN_CLKOS="125.000000" */
+             /* synthesis FREQUENCY_PIN_CLKOP="125.000000" */
+             /* synthesis FREQUENCY_PIN_CLKI="125.000000" */
+             /* synthesis ICP_CURRENT="13" */
+             /* synthesis LPF_RESISTOR="24" */;
+
+    assign CLKOK = CLKOS2_t;
+    assign CLKOS = CLKOS_t;
+    assign CLKOP = CLKOP_t;
+
+
+    // exemplar begin
+    // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOS2 62.500000
+    // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOS 125.000000
+    // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOP 125.000000
+    // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKI 125.000000
+    // exemplar attribute PLLInst_0 ICP_CURRENT 13
+    // exemplar attribute PLLInst_0 LPF_RESISTOR 24
+    // exemplar end
+
+endmodule

diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/readme.htm b/gbe/cores/sgmii/tsmac/ts_mac_eval/readme.htm
new file mode 100644 (file)
index 0000000..b878a81
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/readme.htm
@@ -0,0 +1,1355 @@
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+<p class=MsoNormal style='margin-bottom:12.0pt;border:none;mso-border-bottom-alt:\r
+solid windowtext .75pt;padding:0cm;mso-padding-alt:0cm 0cm 0cm 0cm'><span\r
+style='color:navy'><o:p>&nbsp;</o:p></span></p>\r
+\r
+<p class=MsoNormal style='margin-bottom:12.0pt;border:none;mso-border-bottom-alt:\r
+solid windowtext .75pt;padding:0cm;mso-padding-alt:0cm 0cm 0cm 0cm'><b><span\r
+style='font-size:18.0pt;font-family:"Arial","sans-serif"'>General Information</span></b></p>\r
+\r
+</div>\r
+\r
+<p class=MsoNormal style='margin-bottom:12.0pt'><br>\r
+<b><span style='font-family:"Arial","sans-serif"'>Copyright Notice</span></b></p>\r
+\r
+<table class=MsoNormalTable border=0 cellpadding=0 width="80%"\r
+ style='width:80.0%;mso-cellspacing:1.5pt;mso-yfti-tbllook:1184;mso-padding-alt:\r
+ 0cm 0cm 0cm 0cm'>\r
+ <tr style='mso-yfti-irow:0;mso-yfti-firstrow:yes;mso-yfti-lastrow:yes'>\r
+  <td style='padding:.75pt .75pt .75pt .75pt'>\r
+  <p><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Copyright 2000-2016©\r
+      Lattice Semiconductor Corporation. ALL RIGHTS RESERVED. This\r
+  confidential and proprietary software may be used only as authorized by a licensing\r
+  agreement from Lattice Semiconductor Corporation. The entire notice above\r
+  must be reproduced on all authorized copies and copies may only be made to\r
+  the extent permitted by a licensing agreement from Lattice Semiconductor\r
+  Corporation.<o:p></o:p></span></p>\r
+  </td>\r
+ </tr>\r
+</table>\r
+\r
+<div style='mso-element:para-border-div;border:none;border-bottom:solid windowtext 1.0pt;\r
+mso-border-bottom-alt:solid windowtext .75pt;padding:0cm 0cm 0cm 0cm'>\r
+\r
+<p class=MsoNormal style='margin-bottom:12.0pt;border:none;mso-border-bottom-alt:\r
+solid windowtext .75pt;padding:0cm;mso-padding-alt:0cm 0cm 0cm 0cm'><br>\r
+<b><span style='font-size:18.0pt;font-family:"Arial","sans-serif"'>Contacting\r
+Lattice</span></b></p>\r
+\r
+</div>\r
+\r
+<p class=MsoNormal><o:p>&nbsp;</o:p></p>\r
+\r
+<table class=MsoNormalTable border=1 cellspacing=0 cellpadding=0 width=450\r
+ style='width:337.5pt;mso-cellspacing:0cm;margin-left:9.0pt;border:solid silver 1.0pt;\r
+ mso-border-alt:solid silver .75pt;mso-yfti-tbllook:1184;mso-padding-alt:0cm 0cm 0cm 0cm;\r
+ border-spacing: 0px;border-spacing: 0px' x-use-null-cells>\r
+ <col class=whs6><col class=whs7>\r
+ <tr style='mso-yfti-irow:0;mso-yfti-firstrow:yes;x-cell-content-align: top'>\r
+  <td width=100 valign=top style='width:75.0pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><!--(Table)=========================================================--><span\r
+  style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Mail:<o:p></o:p></span></p>\r
+  </td>\r
+  <td width=300 valign=top style='width:225.0pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Lattice\r
+  Semiconductor Corporation<br>\r
+<st1:address w:st="on"><st1:Street w:st="on">5555 NE Moore \r
+      Court</st1:Street><br><st1:City w:st="on">Hillsboro</st1:City>, \r
+      <st1:State w:st="on">OR</st1:State> \r
+      &nbsp;<st1:PostalCode w:st="on">97124</st1:PostalCode><br><st1:country-region w:st="on">U.S.A.<u1:p></u1:p></st1:country-region></st1:address><o:p></o:p></span></p>\r
+  </td>\r
+ </tr>\r
+ <tr style='mso-yfti-irow:1;x-cell-content-align: top'>\r
+  <td width=100 valign=top style='width:75.0pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Telephone:<o:p></o:p></span></p>\r
+  </td>\r
+  <td width=300 valign=top style='width:225.0pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>1-800-Lattice\r
+  (<st1:country-region w:st="on">USA</st1:country-region> and <st1:country-region\r
+  w:st="on"><st1:place w:st="on">Canada</st1:place></st1:country-region>)<u1:p></u1:p><o:p></o:p></span></p>\r
+  </td>\r
+ </tr>\r
+ <tr style='mso-yfti-irow:2;x-cell-content-align: top'>\r
+  <td width=100 valign=top style='width:75.0pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table>&nbsp;</p>\r
+  </td>\r
+  <td width=300 valign=top style='width:225.0pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>1-503-268-8001\r
+  (other locations)<u1:p></u1:p><o:p></o:p></span></p>\r
+  </td>\r
+ </tr>\r
+ <tr style='mso-yfti-irow:3;x-cell-content-align: top'>\r
+  <td width=100 valign=top style='width:75.0pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Website:<o:p></o:p></span></p>\r
+  </td>\r
+  <td width=300 valign=top style='width:225.0pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span style='font-size:10.0pt;font-family:"Verdana","sans-serif";\r
+  color:#013C9A'><a href="http://www.latticesemi.com" target="_blank"><span\r
+  style='color:#013C9A'>http://www.latticesemi.com</span></a><u1:p></u1:p><o:p></o:p></span></p>\r
+  </td>\r
+ </tr>\r
+ <tr style='mso-yfti-irow:4;mso-yfti-lastrow:yes;x-cell-content-align: top'>\r
+  <td width=100 valign=top style='width:75.0pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>E-mail:<o:p></o:p></span></p>\r
+  </td>\r
+  <td width=300 valign=top style='width:225.0pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span style='font-size:10.0pt;font-family:"Verdana","sans-serif";\r
+  color:#013C9A'><a href="mailto:techsupport@latticesemi.com"><span\r
+  style='color:#013C9A'>techsupport@latticesemi.com</span></a><u1:p></u1:p><o:p></o:p></span></p>\r
+  </td>\r
+ </tr>\r
+</table>\r
+\r
+<p class=MsoNormal style='margin-bottom:12.0pt'><o:p>&nbsp;</o:p></p>\r
+\r
+<div style='mso-element:para-border-div;border:none;border-bottom:solid windowtext 1.0pt;\r
+mso-border-bottom-alt:solid windowtext .75pt;padding:0cm 0cm 0cm 0cm'>\r
+\r
+<p class=MsoNormal style='margin-bottom:12.0pt;border:none;mso-border-bottom-alt:\r
+solid windowtext .75pt;padding:0cm;mso-padding-alt:0cm 0cm 0cm 0cm'><b><span\r
+style='font-size:18.0pt;font-family:"Arial","sans-serif"'>IP Module Information</span></b></p>\r
+\r
+</div>\r
+\r
+<p class=MsoNormal style='margin-bottom:12.0pt'><br>\r
+<b><span style='font-family:"Arial","sans-serif"'>About this Module</span></b> <o:p></o:p></p>\r
+\r
+<table class=MsoNormalTable border=1 cellspacing=0 cellpadding=0 width=450\r
+ style='width:337.5pt;mso-cellspacing:0cm;margin-left:9.0pt;border:solid silver 1.0pt;\r
+ mso-border-alt:solid silver .75pt;mso-yfti-tbllook:1184;mso-padding-alt:0cm 0cm 0cm 0cm;\r
+ border-spacing: 0px;border-spacing: 0px' x-use-null-cells>\r
+ <col><col>\r
+ <tr style='mso-yfti-irow:0;mso-yfti-firstrow:yes;x-cell-content-align: top'>\r
+  <td width=300 valign=top style='width:225.0pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><!--(Table)=========================================================--><span\r
+  style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>IP Name:<o:p></o:p></span></p>\r
+  </td>\r
+  <td width=300 valign=top style='width:225.0pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=MsoNormal><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Tri-Speed\r
+  Ethernet Media Access Controller</span> </p>\r
+  </td>\r
+ </tr>\r
+ <tr style='mso-yfti-irow:1;x-cell-content-align: top'>\r
+  <td width=300 valign=top style='width:225.0pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>IP\r
+  Version:<o:p></o:p></span></p>\r
+  </td>\r
+  <td width=300 valign=top style='width:225.0pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span style='font-size:10.0pt;\r
+  font-family:"Verdana","sans-serif"'>4.1</span></p>\r
+  </td>\r
+ </tr>\r
+ <tr style='mso-yfti-irow:2;x-cell-content-align: top'>\r
+  <td width=300 valign=top style='width:225.0pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>IP\r
+  Release Date:<o:p></o:p></span></p>\r
+  </td>\r
+  <td width=300 valign=top style='width:225.0pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span style='font-size:10.0pt;font-family:"Verdana","sans-serif";\r
+  mso-fareast-font-family:SimSun'>Aug 2016</span></p>\r
+  </td>\r
+ </tr>\r
+ <tr style='mso-yfti-irow:3;mso-yfti-lastrow:yes;x-cell-content-align: top'>\r
+  <td width=300 valign=top style='width:225.0pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Target\r
+  Technology:<o:p></o:p></span></p>\r
+  </td>\r
+  <td width=300 valign=top style='width:225.0pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span class=SpellE><span style='font-size:10.0pt;font-family:\r
+  "Verdana","sans-serif"'>LatticeXP2</span></span><span style='font-size:10.0pt;\r
+  font-family:"Verdana","sans-serif"'>, LatticeECP3, <span class=SpellE>ECP5U</span>,\r
+      <span style='font-size:10.0pt;\r
+  font-family:"Verdana","sans-serif"'><span class=SpellE>ECP5UM, ECP5UM5G</span></span></span></p>\r
+  </td>\r
+ </tr>\r
+</table>\r
+\r
+<p class=MsoNormal style='margin-bottom:12.0pt'><br>\r
+<b><span style='font-family:"Arial","sans-serif"'>Software Requirements</span></b><o:p></o:p></p>\r
+\r
+<table class=MsoNormalTable border=1 cellspacing=0 cellpadding=0 width=631\r
+ style='width:472.95pt;mso-cellspacing:0cm;margin-left:9.0pt;border:solid silver 1.0pt;\r
+ mso-border-alt:solid silver .75pt;mso-yfti-tbllook:1184;mso-padding-alt:0cm 0cm 0cm 0cm;\r
+ border-spacing: 0px;border-spacing: 0px' x-use-null-cells>\r
+ <col><col>\r
+ <tr style='mso-yfti-irow:0;mso-yfti-firstrow:yes;x-cell-content-align: top'>\r
+  <td width=207 valign=top style='width:155.45pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><!--(Table)=========================================================--><span\r
+  style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Synthesis Tools\r
+  Supported:<o:p></o:p></span></p>\r
+  </td>\r
+  <td width=423 valign=top style='width:317.5pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span class=SpellE><span style='font-size:10.0pt;font-family:\r
+  "Verdana","sans-serif"'>Synplify</span></span><span style='font-size:10.0pt;\r
+  font-family:"Verdana","sans-serif"'> Pro for Lattice K-2015.09L-2<br>\r
+  Lattice LSE Synthesis tool<o:p></o:p></span></p>\r
+  </td>\r
+ </tr>\r
+ <tr style='mso-yfti-irow:1;x-cell-content-align: top'>\r
+  <td width=207 valign=top style='width:155.45pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Simulation\r
+  Tools Supported:<o:p></o:p></span></p>\r
+  </td>\r
+  <td width=423 valign=top style='width:317.5pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Active-HD 10.2(Windows\r
+      only)<br>\r
+  ModelSim SE 10<o:p></o:p></span></p>\r
+  </td>\r
+ </tr>\r
+ <tr style='mso-yfti-irow:2;mso-yfti-lastrow:yes;x-cell-content-align: top'>\r
+  <td width=207 valign=top style='width:155.45pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Lattice\r
+  Tool Supported:<o:p></o:p></span></p>\r
+  </td>\r
+  <td width=423 valign=top style='width:317.5pt;border:none;padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=table><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Diamond 3.7 or later</span></p>\r
+  </td>\r
+ </tr>\r
+</table>\r
+\r
+<p>&nbsp;</p>\r
+\r
+<div style='mso-element:para-border-div;border:none;border-bottom:solid windowtext 1.0pt;\r
+mso-border-bottom-alt:solid windowtext .75pt;padding:0cm 0cm 0cm 0cm'>\r
+\r
+<p class=MsoNormal style='margin-bottom:12.0pt;border:none;mso-border-bottom-alt:\r
+solid windowtext .75pt;padding:0cm;mso-padding-alt:0cm 0cm 0cm 0cm'><b><span\r
+style='font-size:18.0pt;font-family:"Arial","sans-serif"'>Implementing the IP Module\r
+Using Lattice Diamond SW</span></b></p>\r
+\r
+</div>\r
+\r
+<p class=MsoNormal style='margin-bottom:12.0pt'><br>\r
+<b><span style='font-family:"Arial","sans-serif"'>Instantiating the Core</span></b></p>\r
+\r
+<table class=MsoNormalTable border=0 cellpadding=0 width="80%"\r
+ style='width:80.0%;mso-cellspacing:1.5pt;mso-yfti-tbllook:1184;mso-padding-alt:\r
+ 0cm 0cm 0cm 0cm'>\r
+ <tr style='mso-yfti-irow:0;mso-yfti-firstrow:yes;mso-yfti-lastrow:yes'>\r
+  <td style='padding:.75pt .75pt .75pt .75pt'>\r
+  <p><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>The\r
+  generated Tri-<span class=SpellE>Speed_MAC</span> core package includes\r
+  black-box (&lt;user_name&gt;_bb.v) and instance (&lt;username&gt;_inst.v)\r
+  templates that can be used to instantiate the core in a top-level design. <o:p></o:p></span></p>\r
+  <p><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>An\r
+  example RTL top-level reference source file(ts_mac_top.v) that can be used as\r
+  an instantiation template for the IP core is provided in <i>&lt;project_dir&gt;\ts_mac_eval\&lt;username&gt;\src\rtl\top</i>.\r
+  Users may also use this top-level reference as the starting template for the\r
+  top-level for their complete design.<o:p></o:p></span></p>\r
+  </td>\r
+ </tr>\r
+</table>\r
+\r
+<p class=MsoNormal style='margin-bottom:12.0pt'><br>\r
+<b><span style='font-family:"Arial","sans-serif"'>Hardware Evaluation</span></b></p>\r
+\r
+<table class=MsoNormalTable border=0 cellpadding=0 width="80%"\r
+ style='width:80.0%;mso-cellspacing:1.5pt;mso-yfti-tbllook:1184;mso-padding-alt:\r
+ 0cm 0cm 0cm 0cm'>\r
+ <tr style='mso-yfti-irow:0;mso-yfti-firstrow:yes;mso-yfti-lastrow:yes'>\r
+  <td style='padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=MsoBodyText>Lattice's IP hardware evaluation capability makes it\r
+  possible to create IP cores that operate in hardware for a limited period of\r
+  time (approximately four hours) without requiring the purchase on an IP\r
+  license. The hardware evaluation capability is enabled by default. It can be\r
+  disabled by Project-&gt;Active Strategy-&gt;Translate\r
+      Design Settings. The setting is\r
+  called &quot;Hardware Evaluation&quot; and the options are &quot;Enable&quot;\r
+  or &quot;Disable&quot;.<br />\r
+  <span style='mso-spacerun:yes'> &nbsp;&nbsp;&nbsp;&nbsp;</span><br>\r
+  When the Hardware Evaluation feature is enabled in the design, it will\r
+  generate a programming file that may be downloaded into the device. After initialization,\r
+  the IP core will be operational for approximately four hours. After four\r
+  hours, the device will stop working and it will be necessary to reprogram the\r
+  device to re-enable operation. This hardware evaluation capability is only\r
+  enabled if the core has not been licensed. During implementation, a license\r
+  check is performed. If the hardware evaluation feature is disabled, a pop-up\r
+  window will be displayed indicating a license failure. <span class=SpellE>Click&quot;OK</span>&quot;\r
+  in the window and the bitstream will not be generated. If a license is\r
+  detected, no pop-up window is displayed and core generation is completed with\r
+  no restrictions.<span style='font-family:"Verdana","sans-serif"'><o:p></o:p></span></p>\r
+  </td>\r
+ </tr>\r
+</table>\r
+\r
+<p class=MsoNormal><br>\r
+<b><span style='font-family:"Arial","sans-serif"'>Implementing the core only\r
+design in a Top-Level Design</span></b></p>\r
+\r
+<table class=MsoNormalTable border=0 cellpadding=0 width="80%"\r
+ style='width:80.0%;mso-cellspacing:1.5pt;mso-yfti-tbllook:1184;mso-padding-alt:\r
+ 0cm 0cm 0cm 0cm'>\r
+ <tr style='mso-yfti-irow:0;mso-yfti-firstrow:yes'>\r
+  <td style='padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=MsoNormal><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>As\r
+  described previously, the top-level file <span class=SpellE>ts_mac_core_only_top.v</span>\r
+  and <span class=SpellE>ts_mac_core_only_top.vhd</span> files provided in <i>&lt;project_dir&gt;\ts_mac_eval\&lt;username&gt;\src\rtl\top</i>\r
+  support the ability to implement just the Tri-<span class=SpellE>Speed_MAC</span>\r
+  IP core. <o:p></o:p></span></p>\r
+  <p><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Push-button\r
+  top-level implementation of this top-level is supported via the Diamond project file &lt;username&gt;_<span\r
+  class=SpellE>core_only_eval.</span><span class=SpellE>ldf</span> located in &lt;<span class=SpellE>project_dir</span>&gt;\<span\r
+  class=SpellE>ts_mac_eval</span>\&lt;username&gt;\<span class=SpellE>impl</span>\&lt;synthesis&gt;.\r
+  <o:p></o:p></span></p>\r
+  <p><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>This\r
+  design is intended only to provide an accurate indication of the device\r
+  utilization associated with the core itself and should not be used as an\r
+  actual implementation example.<o:p></o:p></span></p>\r
+      <![if !supportLists]><![endif]><![if !supportLists]><![endif]><![if !supportLists]><![endif]><![if\r
+      !supportLists]><![endif]><![if !supportLists]><![endif]><![if !supportLists]><![endif]></td>\r
+ </tr>\r
+ <tr style='mso-yfti-irow:1;mso-yfti-lastrow:yes'>\r
+  <td style='padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=MsoNormal><br>\r
+  <span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>To use the\r
+  project file:<o:p></o:p></span></p>\r
+  <ul type=disc>\r
+   <li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l1 level1 lfo1;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Select File-&gt;Open-&gt;Project\r
+           in Lattice Diamond.<o:p></o:p></span></li>\r
+   <li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l1 level1 lfo1;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Browse to <i>\&lt;<span\r
+       class=SpellE>project_dir</span>&gt;\<span class=SpellE>ts_mac_eval</span>\&lt;username&gt;\<span\r
+       class=SpellE>impl</span>\&lt;synthesis&gt;</i> in the Open Project\r
+       dialog box.<o:p></o:p></span></li>\r
+   <li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l1 level1 lfo1;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Select and\r
+       open &lt;username&gt;_<span class=SpellE>core_only_eval.ldf</span>.At this point, all\r
+       of the files needed to support top-level synthesis and implementation\r
+       will be imported to the project.<o:p></o:p></span></li>\r
+   <li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l1 level1 lfo1;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Implement\r
+       the complete design via the standard Lattice Diamond GUI flow.<o:p></o:p></span></li>\r
+  </ul>\r
+  <p class=MsoNormal style='margin-left:36.0pt'><span style='font-size:10.0pt;\r
+  font-family:"Verdana","sans-serif"'><o:p>&nbsp;</o:p></span></p>\r
+  </td>\r
+ </tr>\r
+</table>\r
+\r
+<p class=MsoNormal><b><span style='font-family:"Arial","sans-serif"'><o:p>&nbsp;</o:p></span></b></p>\r
+\r
+<p class=MsoNormal><b><span style='font-family:"Arial","sans-serif"'>Implementing\r
+the reference design in a Top-Level Design</span></b></p>\r
+\r
+<table class=MsoNormalTable border=0 cellpadding=0 width="80%"\r
+ style='width:80.0%;mso-cellspacing:1.5pt;mso-yfti-tbllook:1184;mso-padding-alt:\r
+ 0cm 0cm 0cm 0cm'>\r
+ <tr style='mso-yfti-irow:0;mso-yfti-firstrow:yes'>\r
+  <td style='padding:.75pt .75pt .75pt .75pt'>\r
+  <p><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Push-button\r
+  top-level implementation of a sample reference design is also supported via\r
+  the <span class=SpellE>\r
+          Diamond</span> project file &lt;username&gt;_<span\r
+  class=SpellE>reference_eval.</span><span class=SpellE>ldf</span> located in &lt;<span class=SpellE>project_dir</span>&gt;\<span\r
+  class=SpellE>ts_mac_eval</span>\&lt;username&gt;\<span class=SpellE>impl</span>\&lt;synthesis&gt;.\r
+  <o:p></o:p></span></p>\r
+  <p><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Implementation\r
+  of the reference evaluation configuration is targeted to a specific device\r
+  and package type for each device family. Specifically:<o:p></o:p></span></p>\r
+  <p class=MsoBodyText style='margin-top:0cm;margin-right:0cm;margin-bottom:\r
+  0cm;margin-left:36.0pt;margin-bottom:.0001pt;tab-stops:36.0pt 90.0pt'>XP2:<span\r
+  style='mso-tab-count:1'> &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;&nbsp; </span>LFXP2-17E-6F484C</p>\r
+  <p class=MsoBodyText style='margin-top:0cm;margin-right:0cm;margin-bottom:\r
+  0cm;margin-left:36.0pt;margin-bottom:.0001pt;tab-stops:36.0pt 90.0pt'>ECP3:<span\r
+  style='mso-tab-count:1'> &nbsp; &nbsp; &nbsp; &nbsp;  </span>LFE3-95EA-8FN484C</p>\r
+  <p class=MsoBodyText style='margin-top:0cm;margin-right:0cm;margin-bottom:\r
+  0cm;margin-left:36.0pt;margin-bottom:.0001pt;tab-stops:36.0pt 90.0pt'>ECP5U:<span\r
+  style='mso-tab-count:1'> &nbsp; &nbsp; &nbsp; </span>LFE5U-85F-8BG756C</p>\r
+  <p class=MsoBodyText style='margin-top:0cm;margin-right:0cm;margin-bottom:\r
+  0cm;margin-left:36.0pt;margin-bottom:.0001pt;tab-stops:36.0pt 90.0pt'>ECP5UM:<span\r
+  style='mso-tab-count:1'> &nbsp; &nbsp; </span>LFE5UM-85F-8BG756C</p>\r
+  <p class=MsoBodyText style='margin-top:0cm;margin-right:0cm;margin-bottom:\r
+  0cm;margin-left:36.0pt;margin-bottom:.0001pt;tab-stops:36.0pt 90.0pt'>ECP5UM5G:<span\r
+  style='mso-tab-count:1'> &nbsp; &nbsp; </span>LFE5UM5G-85F-8BG756C</p>\r
+      <![if !supportLists]><![endif]><![if !supportLists]><![endif]><![if !supportLists]><![endif]><![if\r
+      !supportLists]><![endif]><![if !supportLists]><![endif]><![if !supportLists]><![endif]></td>\r
+ </tr>\r
+ <tr style='mso-yfti-irow:1;mso-yfti-lastrow:yes'>\r
+  <td style='padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=MsoNormal><br>\r
+  <span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>To use the\r
+  project file:<o:p></o:p></span></p>\r
+  <ul type=disc>\r
+   <li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l1 level1 lfo1;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Select File-&gt;Open-&gt;Project\r
+           in Lattice Diamond.</span></li><li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l1 level1 lfo1;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Browse to <i>\&lt;<span\r
+       class=SpellE>project_dir</span>&gt;\<span class=SpellE>ts_mac_eval</span>\&lt;username&gt;\<span\r
+       class=SpellE>impl</span>\&lt;synthesis&gt;</i> in the Open Project\r
+       dialog box.<o:p></o:p></span></li>\r
+   <li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l1 level1 lfo1;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Select and\r
+       open &lt;username&gt;_<span class=SpellE>reference_eval.</span><span\r
+       class=SpellE>ldf</span>. At this point, all\r
+       of the files needed to support top-level synthesis and implementation\r
+       will be imported to the project.<o:p></o:p></span></li>\r
+   <li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l1 level1 lfo1;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Implement\r
+       the complete design via the standard Diamond GUI flow.<o:p></o:p></span></li>\r
+  </ul>\r
+  </td>\r
+ </tr>\r
+</table>\r
+\r
+<p style='margin-bottom:12.0pt'><br>\r
+<b><span style='font-family:"Arial","sans-serif"'>Running Functional and <st1:Street\r
+w:st="on"><st1:address w:st="on">Post \r
+Route</st1:address></st1:Street> Timing\r
+Simulation</span></b></p>\r
+\r
+<table class=MsoNormalTable border=0 cellpadding=0 width="80%"\r
+ style='width:80.0%;mso-cellspacing:1.5pt;mso-yfti-tbllook:1184;mso-padding-alt:\r
+ 0cm 0cm 0cm 0cm'>\r
+ <tr style='mso-yfti-irow:0;mso-yfti-firstrow:yes'>\r
+  <td style='padding:.75pt .75pt .75pt .75pt'>\r
+  <p><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>The\r
+  functional simulation includes a configuration-specific behavioral model of\r
+  the <span class=SpellE><i>Tri_Speed</i></span><i> MAC</i>, which is\r
+  instantiated in an FPGA top level along with some test logic (PLLs, and registers\r
+  with Read/Write Interface). This FPGA top is instantiated in an eval\r
+  testbench that configures FPGA test logic registers and <span class=SpellE><i>Tri_Speed</i></span><i>\r
+  MAC</i> IP core registers. The testbench files can be found in <i>\&lt;<span\r
+  class=SpellE>project_dir</span>&gt;\<span class=SpellE>ts_mac_eval</span>\<span\r
+  class=SpellE>testbench</span></i>. <br>\r
+  <br>\r
+  Both Active-HDL and ModelSim are supported for simulation.<o:p></o:p></span></p>\r
+  </td>\r
+ </tr>\r
+ <tr style='mso-yfti-irow:1;mso-yfti-lastrow:yes'>\r
+  <td style='padding:.75pt .75pt .75pt .75pt'>\r
+  <p class=MsoNormal><span class=style31><span style='font-size:10.0pt'>Functional\r
+  Simulation</span></span><br>\r
+  <span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>The\r
+  generated IP core package includes the configuration-specific behavior model\r
+  (&lt;username&gt;_beh.v) for functional simulation. ModelSim simulation is\r
+  supported via testbench files provided in <i>\&lt;<span class=SpellE>project_dir</span>&gt;\<span\r
+  class=SpellE>ts_mac_eval</span>\&lt;username&gt;\<span class=SpellE>src</span>\<span\r
+  class=SpellE>rtl</span>\top\</i>. Models required for simulation are provided\r
+  in the <i>\&lt;<span class=SpellE>project_dir</span>&gt;\<span class=SpellE>ts_mac_eval</span>\models</i>\r
+  directory.<o:p></o:p></span></p>\r
+  <p class=MsoNormal><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'><o:p>&nbsp;</o:p></span></p>\r
+  <p class=MsoNormal><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Users\r
+  may run the eval simulation by doing the following with <strong><span\r
+  style='font-family:"Verdana","sans-serif"'>ModelSim SE</span></strong>:<span\r
+  class=style31><o:p></o:p></span></span></p>\r
+  <ul type=disc>\r
+   <li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l4 level1 lfo2;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Open\r
+       ModelSim.</span> </li>\r
+   <li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l4 level1 lfo2;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Under the <i>File</i>\r
+       tab, select <i>Change Directory</i></span> <span style='font-size:10.0pt;\r
+       font-family:"Verdana","sans-serif"'><o:p></o:p></span></li><li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l4 level1 lfo2;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Set the\r
+       directory to \&lt;<span class=SpellE>project_dir</span>&gt;\<span\r
+       class=SpellE><i>ts_mac_eval</i></span>\&lt;username&gt;\<span\r
+       class=SpellE>sim</span>\<span class=SpellE>modelsim</span>.</span> <span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'><o:p></o:p></span></li><li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l4 level1 lfo2;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Select OK.</span>\r
+       <span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'><o:p></o:p></span></li><li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l4 level1 lfo2;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Under the\r
+       Tools tab, select TCL, then select Execute Macro.</span> <span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'><o:p></o:p></span></li><li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l4 level1 lfo2;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Select file\r
+       &lt;username&gt;_eval_se.do for ModelSim SE.</span> <span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'><o:p></o:p></span></li></ul>\r
+  <p class=MsoNormal><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'><br>\r
+  <u>NOTE1:</u> When the simulation completes, a pop-up window will appear\r
+  asking &quot;are you sure you want to finish?&quot; Answer &quot;no&quot; to\r
+  analyze the results (answering &quot;yes&quot; closes ModelSim). <o:p></o:p></span></p>\r
+  <p><span class=msonormal00><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Users\r
+  may run the eval simulation by doing the following with</span></span><strong><span\r
+  style='font-size:10.0pt;font-family:"Verdana","sans-serif"'> Active-HDL</span></strong><span\r
+  style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>(Windows Only):<o:p></o:p></span></p>\r
+  <ul type=disc>\r
+   <li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l0 level1 lfo3;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Open Active-HDL.<o:p></o:p></span></li>\r
+   <li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l0 level1 lfo3;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Under the <i>tools</i>\r
+       tab, select <i>Execute Macro...</i><o:p></o:p></span></li>\r
+   <li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l0 level1 lfo3;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Select file\r
+       \&lt;project_dir&gt;\<i>ts_mac_eval</i>\&lt;username&gt;\sim\aldec\&lt;username&gt;_eval.do</span></li>\r
+   <li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l0 level1 lfo3;tab-stops:list 36.0pt'><span\r
+       class=msonormal00><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Select\r
+       OK.</span><o:p></o:p></span></li>\r
+  </ul>\r
+  <p class=MsoNormal><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'><o:p>&nbsp;</o:p></span></p>\r
+  <p><b><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;font-family:\r
+  "Verdana","sans-serif"'>Post Route Timing Simulation<o:p></o:p></span></b></p>\r
+  <p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span\r
+  style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>In order to run\r
+  the <st1:Street w:st="on"><st1:address w:st="on">Post \r
+      Route</st1:address></st1:Street>\r
+  timing simulation, an IP license is required. For post route simulation, you\r
+  need to generate the timing simulation file by Selecting "Export Files-&gt;Verilog Simulation\r
+      File" in Process Window; This IP only supports Verilog TOP timing simulation).</span><span\r
+  style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Users may run the\r
+  timing simulation by doing the following with <strong><span style='font-family:\r
+  "Verdana","sans-serif"'>ModelSim SE:</span></strong></span> </p>\r
+  <ul type=disc>\r
+   <li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l2 level1 lfo4;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Open\r
+       ModelSim.</span> <span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'><o:p></o:p></span></li><li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l2 level1 lfo4;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Under the <i>File</i>\r
+       tab, select <i>Change Directory</i></span> <span style='font-size:10.0pt;\r
+       font-family:"Verdana","sans-serif"'><o:p></o:p></span></li><li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l2 level1 lfo4;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Set the\r
+       directory to \&lt;<span class=SpellE>project_dir</span>&gt;\<span\r
+       class=SpellE><i>ts_mac_eval</i></span>\&lt;username&gt;\<span\r
+       class=SpellE>sim</span>\<span class=SpellE>modelsim</span>.</span> <span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'><o:p></o:p></span></li><li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l2 level1 lfo4;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Select OK.</span>\r
+       <span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'><o:p></o:p></span></li><li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l2 level1 lfo4;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Under the\r
+       Tools tab, select TCL, then select Execute Macro.</span> <span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'><o:p></o:p></span></li><li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l2 level1 lfo4;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Select file\r
+       &lt;username&gt;_<span class=SpellE>eval_timing</span>_&lt;<span\r
+       class=SpellE>lse|synp</span>&gt;_se.do for <span class=SpellE>ModelSim</span>\r
+       SE.</span> <span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'><o:p></o:p></span></li></ul>\r
+  <p class=MsoNormal><u><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>NOTE:</span></u><span\r
+  style='font-size:10.0pt;font-family:"Verdana","sans-serif"'> When the\r
+  simulation completes, a pop-up window may appear asking, &quot;are you sure\r
+  you want to finish?&quot; Answer &quot;No&quot; to analyze the results\r
+  (answering &quot;Yes&quot; closes ModelSim). <o:p></o:p></span></p>\r
+  <p class=MsoNormal><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'><o:p>&nbsp;</o:p></span></p>\r
+  <p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span\r
+  style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Users may run the\r
+  timing simulation by doing the following with <strong><span style='font-family:\r
+  "Verdana","sans-serif"'>Active-HDL</span></strong>(Windows only):</span> </p>\r
+  <ul type=disc>\r
+   <li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l0 level1 lfo3;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Open\r
+       Active-HDL.<o:p></o:p></span></li>\r
+   <li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l0 level1 lfo3;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Under the <i>tools</i>\r
+       tab, select <i>Execute Macro...</i><o:p></o:p></span></li>\r
+   <li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l0 level1 lfo3;tab-stops:list 36.0pt'><span\r
+       style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Select file\r
+       \&lt;project_dir&gt;\<i>ts_mac_eval</i>\&lt;username&gt;\sim\aldec\&lt;username&gt;_eval_timing_&lt;lse|synp&gt;.do<o:p></o:p></span></li>\r
+   <li class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+       auto;mso-list:l0 level1 lfo3;tab-stops:list 36.0pt'><span\r
+       class=msonormal00><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'>Select\r
+       OK.</span><o:p></o:p></span></li>\r
+  </ul>\r
+  <p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;\r
+  margin-left:18.0pt'><o:p>&nbsp;</o:p></p>\r
+  </td>\r
+ </tr>\r
+</table>\r
+\r
+<p class=MsoNormal><br>\r
+<b><span style='font-family:"Arial","sans-serif"'>Reference Information</span></b><br>\r
+<span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'><br>\r
+The following documents provide more information on implementing this core:<o:p></o:p></span></p>\r
+\r
+<ul type=disc>\r
+ <li class=MsoNormal style='color:#013C9A;mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+     auto;mso-list:l3 level1 lfo5;tab-stops:list 36.0pt'><span\r
+     style='font-size:10.0pt;font-family:"Verdana","sans-serif"'><a\r
+     href="http://www.latticesemi.com/dynamic/view_document.cfm?document_id=19224" target="_blank"><span\r
+     style='color:#013C9A'>User\92s Guide</span></a><o:p></o:p></span></li>\r
+ <li class=MsoNormal style='color:#013C9A;mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+     auto;mso-list:l3 level1 lfo5;tab-stops:list 36.0pt'><span\r
+     style='font-size:10.0pt;font-family:"Verdana","sans-serif"'><a\r
+     href="http://www.latticesemi.com/dynamic/view_document.cfm?document_id=18503" target="_blank"><span\r
+     style='color:#013C9A'>IPexpress Quick Start Guide</span></a> <o:p></o:p></span></li>\r
+ <li class=MsoNormal style='color:#013C9A;mso-margin-top-alt:auto;mso-margin-bottom-alt:\r
+     auto;mso-list:l3 level1 lfo5;tab-stops:list 36.0pt'><span\r
+     style='font-size:10.0pt;font-family:"Verdana","sans-serif"'><a\r
+     href="http://www.latticesemi.com/view_document?document_id=51418" target="_blank"><span\r
+     style='color:#013C9A'>Clarity Designer User Manual</span></a> <o:p></o:p></span></li></ul>\r
+</div>\r
+\r
+</body>\r
+\r
+</html>\r

diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/tests/testcase.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/tests/testcase.v
new file mode 100644 (file)
index 0000000..529fe15
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/tests/testcase.v
@@ -0,0 +1,121 @@
+// ===========================================================================\r
+// Verilog module generated by IPexpress\r
+// Filename: test_1.v  \r
+// Copyright 2005 (c) Lattice Semiconductor Corporation. All rights reserved.\r
+// ===========================================================================\r
+\r
+reg   [7:0]  dummy_data;\r
+\r
+\r
+initial begin\r
+   $display(" .") ;\r
+   $display(" ==============================================================") ;\r
+   $display(" INFO : EVAL SIMULATION") ;\r
+   $display(" ==============================================================") ;\r
+   $display(" INFO : NOTE: This simulation includes the TSMAC IP Core,") ;\r
+   $display(" INFO : instantiated in an FPGA top level that consists of ") ;\r
+   $display(" INFO : test logic (MAC client side loop back logic, PLLs, ") ;\r
+   $display(" INFO : and registers with Read/Write Intf). This FPGA top ") ;\r
+   $display(" INFO : is instantiated in an eval testbench that configures ") ;\r
+   $display(" INFO : FPGA test logic and TSMAC IP core registers and sources") ;\r
+   $display(" INFO : ethernet packets (testcase.v)") ;\r
+   $display(" ==============================================================") ;\r
+   $display(" .") ;\r
+   $display(" .") ;\r
+   $display(" INFO : testcase STARTING") ;\r
+   repeat (10) @(posedge clk_125) ;\r
+   reset_n   <= 1'b0 ;\r
+   repeat (10) @(posedge clk_125) ;\r
+   reset_n   <= 1'b1 ;\r
+\r
+// delay to wait for initialization\r
+   repeat (10) @(posedge clk_125 );\r
+\r
+       // Test logic registers\r
+        orc_write(18'h08006, 8'hC1); // fifo AFL \r
+        orc_write(18'h08007, 8'h01); //  fifo AFH\r
+        orc_write(18'h08008, 8'h05); //  fifo AEL\r
+        orc_write(18'h08001, 8'h07); // tstcntl\r
+        orc_read(18'h08000, dummy_data); // verid\r
+        orc_read(18'h08006, dummy_data); // fifo AFL\r
+        orc_read(18'h08007, dummy_data); // fifo AFH\r
+        orc_read(18'h08008, dummy_data); // fifo AEL\r
+\r
+       // MDIO registers\r
+       `ifdef MIIM_MODULE\r
+        orc_write(18'h00016, 8'h00); // to  - MDIO DATA reg \r
+        orc_write(18'h00017, 8'h80); // to  - MDIO DATA reg \r
+        orc_write(18'h00014, 8'h00); // to  - MDIO ACCESS CTL reg \r
+        orc_write(18'h00015, 8'h21); // to  - MDIO ACCESS CTL reg\r
+       #20000 \r
+        orc_read(18'h00014, dummy_data); // to  - MDIO ACCESS CTL reg \r
+        orc_read(18'h00015, dummy_data); // to  - MDIO ACCESS CTL reg \r
+       `endif\r
+\r
+       // MAC registers\r
+        orc_write(18'h0000a, 8'hcd);           // MAC Addr reg 0\r
+        orc_write(18'h0000b, 8'haa);           // MAC Addr reg 0\r
+        orc_write(18'h0000c, 8'h12);           // MAC Addr reg 1\r
+        orc_write(18'h0000d, 8'hef);           // MAC Addr reg 1\r
+        orc_write(18'h0000e, 8'h56);           // MAC Addr reg 2\r
+        orc_write(18'h0000f, 8'h34);           // MAC Addr reg 2\r
+\r
+        orc_write(18'h00002, 8'h9a); // to host bus - TX_RX_CTL reg \r
+        orc_read(18'h00002, dummy_data); // to host bus  - TX_RX_CTL reg\r
+\r
+        orc_write(18'h00008, 8'h48); // to host bus - IPG reg \r
+        orc_read(18'h00008, dummy_data); // to host bus  - IPG reg\r
+        orc_read(18'h00009, dummy_data); // to host bus  - IPG reg\r
+\r
+    // Default to simulate with 1000M mode\r
+        orc_write(18'h00000, 8'h0f); // to host bus - mode reg \r
+    // To simulate the 100M mode, use the following mode reg\r
+    //  orc_write(18'h00000, 8'h0e); // to host bus - mode reg \r
+        orc_read(18'h00000, dummy_data); // to host bus  - mode reg\r
+\r
+\r
+    // FRAME TEMPLATE\r
+    // rx_frmgen (gben(1), des_addr(48), frm_len(14), num_premb(4), num_ipg(5), badcrc(1), norm_vlan_paus(2),\r
+    // pause_timer(16), bad_pcode(1), len_type(1), len_chkerr(1), badsfd(1), runt_frmid(3), frm_patn(4));\r
+\r
+    rx_frmgen(1'b1, 48'haacdef123456, 14'd75, 4'd7, 5'd26, `RX_GOOD_CRC, `RX_NORM_FRM, 16'h0, `RX_GOOD_OPCODE,\r
+             `RX_LEN_FIELD, `RX_LENCHK_NOER, `RX_GOOD_SFD, `RX_RUNT_NOT, `RX_FRMPTN_NOER); \r
+\r
+    rx_frmgen(1'b1, 48'haacdef123456, 14'd70, 4'd7, 5'd26, `RX_GOOD_CRC, `RX_NORM_FRM, 16'h0, `RX_GOOD_OPCODE,\r
+             `RX_LEN_FIELD, `RX_LENCHK_NOER, `RX_GOOD_SFD, `RX_RUNT_NOT, `RX_FRMPTN_NOER); \r
+\r
+    rx_frmgen(1'b1, 48'haacdef123456, 14'd66, 4'd7, 5'd26, `RX_GOOD_CRC, `RX_NORM_FRM, 16'h0, `RX_GOOD_OPCODE,\r
+             `RX_LEN_FIELD, `RX_LENCHK_NOER, `RX_GOOD_SFD, `RX_RUNT_NOT, `RX_FRMPTN_NOER); \r
+\r
+    rx_frmgen(1'b1, 48'haacdef123456, 14'd64, 4'd7, 5'd26, `RX_GOOD_CRC, `RX_NORM_FRM, 16'h0, `RX_GOOD_OPCODE,\r
+             `RX_LEN_FIELD, `RX_LENCHK_NOER, `RX_GOOD_SFD, `RX_RUNT_NOT, `RX_FRMPTN_NOER); \r
+\r
+    rx_frmgen(1'b1, 48'haacdef123456, 14'd32, 4'd7, 5'd26, `RX_GOOD_CRC, `RX_NORM_FRM, 16'h0, `RX_GOOD_OPCODE,\r
+             `RX_LEN_FIELD, `RX_LENCHK_NOER, `RX_GOOD_SFD, `RX_RUNT_NOT, `RX_FRMPTN_NOER); \r
+\r
+    /* For 100M Classic mode, use following rx_frmgen\r
+    rx_frmgen(1'b0, 48'haacdef123456, 14'd75, 4'd7, 5'd26, `RX_GOOD_CRC, `RX_NORM_FRM, 16'h0, `RX_GOOD_OPCODE,\r
+             `RX_LEN_FIELD, `RX_LENCHK_NOER, `RX_GOOD_SFD, `RX_RUNT_NOT, `RX_FRMPTN_NOER); \r
+\r
+    rx_frmgen(1'b0, 48'haacdef123456, 14'd70, 4'd7, 5'd26, `RX_GOOD_CRC, `RX_NORM_FRM, 16'h0, `RX_GOOD_OPCODE,\r
+             `RX_LEN_FIELD, `RX_LENCHK_NOER, `RX_GOOD_SFD, `RX_RUNT_NOT, `RX_FRMPTN_NOER); \r
+\r
+    rx_frmgen(1'b0, 48'haacdef123456, 14'd66, 4'd7, 5'd26, `RX_GOOD_CRC, `RX_NORM_FRM, 16'h0, `RX_GOOD_OPCODE,\r
+             `RX_LEN_FIELD, `RX_LENCHK_NOER, `RX_GOOD_SFD, `RX_RUNT_NOT, `RX_FRMPTN_NOER); \r
+\r
+    rx_frmgen(1'b0, 48'haacdef123456, 14'd64, 4'd7, 5'd26, `RX_GOOD_CRC, `RX_NORM_FRM, 16'h0, `RX_GOOD_OPCODE,\r
+             `RX_LEN_FIELD, `RX_LENCHK_NOER, `RX_GOOD_SFD, `RX_RUNT_NOT, `RX_FRMPTN_NOER); \r
+\r
+    rx_frmgen(1'b0, 48'haacdef123456, 14'd32, 4'd7, 5'd26, `RX_GOOD_CRC, `RX_NORM_FRM, 16'h0, `RX_GOOD_OPCODE,\r
+             `RX_LEN_FIELD, `RX_LENCHK_NOER, `RX_GOOD_SFD, `RX_RUNT_NOT, `RX_FRMPTN_NOER); \r
+   */\r
+\r
+   repeat (500) @(posedge clk_125 );\r
+   // To simulate the 100M mode, will need long simulation time and should use following one:\r
+   //repeat (2000) @(posedge clk_125 );\r
+\r
+   $stop ;\r
+end\r
+\r
+// =============================================================================\r
+\r

diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/env_params.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/env_params.v
new file mode 100644 (file)
index 0000000..494f6e0
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/env_params.v
@@ -0,0 +1,34 @@
+// ===========================================================================\r
+// Verilog module generated by IPexpress\r
+// Filename: env_params.v  \r
+// Copyright 2005 (c) Lattice Semiconductor Corporation. All rights reserved.\r
+// ===========================================================================\r
+\r
+parameter  K28_5 = 8'hBC , \r
+           K28_1 = 8'h3C , \r
+           K28_7 = 8'hFC , \r
+           D5_6  = 8'hC5 ,  \r
+           D16_2 = 8'h50 ,   \r
+           D21_5 = 8'hB5 ,  \r
+           D2_2  = 8'h42 ,   \r
+           D0_0  = 8'h00 ,    \r
+           K23_7 = 8'hF7 , \r
+           K27_7 = 8'hFB , \r
+           K29_7 = 8'hFD ,\r
+           K30_7 = 8'hFE ; \r
+\r
+parameter ZEROS = 0 ;\r
+parameter ONES  = 1 ;\r
+parameter INC   = 2 ;\r
+parameter DEC   = 3 ;\r
+parameter RAND  = 4 ;\r
+\r
+parameter NPTI   = 3'd0;\r
+parameter NPTR   = 3'd1;\r
+parameter PTER   = 3'd2;\r
+parameter PTES   = 3'd3;\r
+parameter PTEI   = 3'd4;\r
+parameter PTEC   = 3'd5;\r
+\r
+//==============================================================================\r
+\r

diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/orcastra_drv.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/orcastra_drv.v
new file mode 100644 (file)
index 0000000..e30f810
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/orcastra_drv.v
@@ -0,0 +1,210 @@
+// ===========================================================================\r
+// Verilog module generated by IPexpress\r
+// Filename: orcastra_drv.v  \r
+// Copyright 2005 (c) Lattice Semiconductor Corporation. All rights reserved.\r
+// ===========================================================================\r
+//\r
+`timescale 1 ns/100 ps\r
+\r
+`define FAIL  1'b1\r
+`define PASS  1'b0\r
+`define SYS_DATA       8  // system bus data bus size\r
+`define SYS_ADDR       18  // system bus address bus size\r
+`define SYS_SIZE       2  // system bus transfer size\r
+`define half_period    10  // pc_clk half period = 200 ns  \r
+\r
+module orcastra_drv(\r
+   pc_clk,\r
+   pc_datain,\r
+   pc_dataout,\r
+   pc_retry,\r
+   pc_error,\r
+   pc_ready,\r
+   pc_ack\r
+);\r
+\r
+output             pc_clk;\r
+output             pc_datain;\r
+output             pc_ready;\r
+input              pc_ack;\r
+input              pc_dataout;\r
+input              pc_retry;\r
+input              pc_error;\r
+\r
+reg             pc_clk;\r
+reg             pc_ready;\r
+reg             wr;\r
+reg             da;\r
+reg             a;\r
+\r
+initial begin\r
+   pc_clk = 1'b0;\r
+   pc_ready = 1'b0;\r
+   wr = 1'b0;\r
+end\r
+\r
+assign pc_datain = (wr) ? da:a; \r
+\r
+task single_write;\r
+\r
+input [`SYS_ADDR-1:0] address;\r
+input [`SYS_DATA-1:0] data;\r
+inout ret_status;\r
+\r
+integer i;\r
+\r
+reg status;\r
+reg ret_status;\r
+\r
+begin\r
+   \r
+   status = `PASS;\r
+   \r
+   if (!status) begin\r
+    \r
+      wr = 1'b1;\r
+\r
+      da = 0;\r
+      #`half_period\r
+\r
+      // serial data phase\r
+      for (i=0;i<8;i=i+1) begin\r
+\r
+        pc_clk = 1;\r
+        da = data[i];\r
+        #`half_period;\r
+        pc_clk = 0;\r
+        #`half_period;\r
+\r
+      end\r
+\r
+      #`half_period;\r
+      #`half_period;\r
+      #`half_period;\r
+      #`half_period;\r
+      #`half_period;\r
+\r
+\r
+      // serial address phase \r
+      for (i=17;i>=0;i=i-1) begin\r
+\r
+        pc_clk = 1;\r
+        da = address[i];\r
+        #`half_period;\r
+        pc_clk = 0;\r
+        #`half_period;\r
+\r
+      end\r
+\r
+      da = 0;        // WRITE\r
+\r
+      pc_ready = 1;      \r
+      //#`half_period;\r
+      //#`half_period;\r
+      //#`half_period;\r
+      //#`half_period;\r
+      //pc_ready = 0;      \r
+\r
+      // wait for an acknowledge and then wait ten clocks (simulate PC)\r
+      @(posedge pc_ack);\r
+\r
+      for (i=10;i>=0;i=i-1) begin\r
+        #`half_period;\r
+        #`half_period;\r
+      end\r
+      \r
+      pc_ready = 0;  // bring pc_ready low\r
+      \r
+      wr = 1'b0;\r
+      status =         `PASS;\r
+                  \r
+   end\r
+   \r
+   ret_status = ret_status | status;\r
+   \r
+end\r
+\r
+endtask\r
+\r
+task single_read;\r
+\r
+input [`SYS_ADDR-1:0] address;\r
+output [`SYS_DATA-1:0] data;\r
+inout ret_status;\r
+\r
+reg status;\r
+reg ret_status;\r
+reg [7:0] data;\r
+\r
+integer i;\r
+\r
+begin\r
+   \r
+   status = `PASS;\r
+   \r
+   if (!status) begin\r
+\r
+      a = 0;\r
+      #`half_period\r
+   \r
+      // serial address phase \r
+      for (i=17;i>=0;i=i-1) begin\r
+\r
+        pc_clk = 1;\r
+        a = address[i];\r
+        #`half_period;\r
+        pc_clk = 0;\r
+        #`half_period;\r
+\r
+      end\r
+      \r
+      a = 1;        // READ\r
+\r
+      pc_ready = 1;      \r
+      //#`half_period;\r
+      //#`half_period;\r
+      //#`half_period;\r
+      //#`half_period;\r
+      //pc_ready = 0;      \r
+\r
+      // wait for an acknowledge and then wait ten clocks (simulate PC)\r
+      @(posedge pc_ack);\r
+      \r
+      for (i=10;i>=0;i=i-1) begin\r
+        #`half_period;\r
+        #`half_period;\r
+      end\r
+      \r
+      pc_ready = 0;  // bring pc_ready low\r
+\r
+      // extra clock ???????\r
+      pc_clk = 1;\r
+      #`half_period;\r
+      pc_clk = 0;\r
+      #`half_period;\r
+\r
+      // serial data phase - read data\r
+      for (i=0;i<8;i=i+1) begin\r
+\r
+        pc_clk = 1;\r
+        #`half_period;\r
+        pc_clk = 0;\r
+       data[i] = pc_dataout;\r
+        #`half_period;\r
+\r
+      end\r
+\r
+      #`half_period;\r
+      #`half_period;\r
+      \r
+      status = `PASS;\r
+            \r
+   end\r
+   \r
+   ret_status = ret_status | status;\r
+   \r
+end\r
+\r
+endtask\r
+\r
+endmodule\r

diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/pkt_mon.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/pkt_mon.v
new file mode 100644 (file)
index 0000000..d42b3ed
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/pkt_mon.v
@@ -0,0 +1,624 @@
+/*================================================================\r
+-- Copyright (c) 2004 - Lattice Semiconductor Corporation\r
+--                    - NetCom IP\r
+--\r
+-- This program is controlled by a written license agreement.\r
+-- Unauthorized Reproduction or Use is Expressly Prohibited.\r
+-- ================================================================*/\r
+\r
+// file name:  pkt_mon.v\r
+// version:    1.0\r
+// date:       may 13, 2008 \r
+// \r
+// code type:  Behavioral Level\r
+//\r
+// Overview:    This module monitors ethernet packets, and checks\r
+//              their crc and then prints them to a file.      \r
+//\r
+// Rev:                0.0 - Initial Ver N.G\r
+/*=================================================================*/\r
+\r
+`timescale 1ns/100ps\r
+\r
+\r
+// DEFINES\r
+\r
+\r
+module pkt_mon(\r
+               reset_n,\r
+               gbit_en,\r
+               tx_clk,\r
+               `ifdef SGMII_TSMAC\r
+                 tx_clk_en,\r
+               `endif\r
+               tx_en,\r
+               tx_er,\r
+               txd\r
+               );\r
+\r
+\r
+\r
+        // ethernet ports\r
+       input [7:0] txd;\r
+       input tx_er;\r
+       input tx_en;\r
+\r
+        // general ports\r
+        input reset_n;                      // active low global reset\r
+        input gbit_en;                      // GbE mode enable \r
+        input tx_clk;                       // tx clock\r
+\r
+       `ifdef SGMII_TSMAC\r
+         input tx_clk_en;\r
+       `endif\r
+\r
+        integer out_file;                   // pointer to output file - ethernet_pkts_sink \r
+\r
+        wire nib_enb;                        //\r
+        wire nib_enb_0;                      // nib_0 enable select (3:0) \r
+        wire nib_enb_1;                      // nib_0 enable select (7:4) \r
+       \r
+       // ------------------------------\r
+       // signals related to monitor FSM\r
+       // ------------------------------\r
+        reg [1:0] m_st;\r
+       reg [11:0] byt_cnt;\r
+       reg [15:0] pkt_cnt;\r
+       reg [7:0] txd_fe ;\r
+       reg [7:0] txd_fe_B ;\r
+       reg byte_valid_fe ;\r
+       reg tx_en_1d ;\r
+       reg tx_er_1d ;\r
+       reg tx_en_2d ;\r
+       reg tx_er_2d ;\r
+       reg [7:0] txd_1d ;\r
+        reg nib_cnt;                          // nibble counter - toggles \r
+\r
+       reg [7:0] len_B0 ;\r
+       reg [15:0] len_B0B1 ;\r
+        reg [31:0] crc_reg;\r
+        reg [31:0] crc_reg_latched;\r
+       reg [7:0] Rx_CRC_B0 ;\r
+       reg [7:0] Rx_CRC_B1 ;\r
+       reg [7:0] Rx_CRC_B2 ;\r
+       reg [31:0] Rx_CRC ;\r
+       reg tx_error_latched ;\r
+       reg control_pkt ;\r
+       reg pause_pkt ;\r
+       reg vlan_pkt ;\r
+       reg [7:0] op_code_B0 ;\r
+       reg [7:0] vlan_len_B0 ;\r
+\r
+       \r
+        parameter[1:0] \r
+                  IDLE = 0,\r
+                  PREMB = 1,\r
+                  PKT_BODY = 2;\r
+         \r
+        parameter CRC_INIT_VALUE = 32'hffff_ffff;\r
+\r
+       // ------------------------------\r
+\r
+\r
+\r
+// Initializations\r
+initial\r
+begin\r
+       out_file = $fopen("ethernet_pkts_sink");\r
+       m_st = 0;\r
+       byt_cnt = 0;\r
+       pkt_cnt = 0;\r
+       len_B0 = 0;\r
+       len_B0B1 = 0;\r
+       Rx_CRC_B0 = 0;\r
+       Rx_CRC_B1 = 0;\r
+       Rx_CRC_B2 = 0;\r
+       Rx_CRC = 0;\r
+end\r
+\r
+\r
+  // wire assignments\r
+   assign nib_enb = nib_cnt;\r
+   assign nib_enb_0 = ( (nib_enb == 1'd0) && (tx_en == 1'b1) ) ? 1:0;\r
+   assign nib_enb_1 = ( (nib_enb == 1'd1) && (tx_en == 1'b1) ) ? 1:0;\r
+\r
+   \r
+  // ---------------------------------------------------------------------------------\r
+  // 10/100 nib to bytes \r
+  // ---------------------------------------------------------------------------------\r
+   always @(posedge tx_clk or negedge reset_n) begin\r
+        if (~reset_n) begin\r
+           nib_cnt <= 1'b0;\r
+           txd_fe[7:0]  <= 8'b0;\r
+           byte_valid_fe  <= 1'b0;\r
+           tx_en_1d  <= 1'b0;\r
+           tx_en_2d  <= 1'b0;\r
+           tx_er_1d  <= 1'b0;\r
+           tx_er_2d  <= 1'b0;\r
+           txd_1d  <= 8'b0;\r
+           txd_fe_B  <= 8'b0;\r
+       end\r
+       else begin\r
+\r
+           txd_1d  <= txd;\r
+           tx_en_1d  <= tx_en;\r
+           tx_en_2d  <= tx_en_1d;\r
+           tx_er_1d  <= tx_er;\r
+           tx_er_2d  <= tx_er_1d;\r
+          \r
+           byte_valid_fe  <= nib_enb_1 & tx_en_1d;\r
+          \r
+          if (tx_en && nib_cnt == 1'b0) begin\r
+             nib_cnt <= 1'b1;\r
+           end\r
+          else begin\r
+             nib_cnt <= 1'b0;\r
+           end\r
+\r
+          if (nib_enb_0) begin\r
+              txd_fe[3:0] <= txd[3:0];\r
+          end\r
+          if (nib_enb_1) begin\r
+              txd_fe_B[7:0] <= {txd[3:0],txd_fe[3:0]};\r
+          end\r
+       end\r
+   end // always \r
+\r
+  \r
+   \r
+// -------------------------------------------------------------------------------------------------------\r
+// Ethernet PACKETS SINK MONITOR  \r
+// -------------------------------------------------------------------------------------------------------\r
+always@(posedge tx_clk) begin\r
+        case (m_st)\r
+\r
+             IDLE:\r
+                begin\r
+                 byt_cnt = 0;\r
+                  crc_reg = 32'hffff_ffff;\r
+                  crc_reg_latched = 32'hffff_ffff;\r
+                  tx_error_latched = 1'b0;\r
+                  control_pkt <= 1'b0;\r
+                  pause_pkt <= 1'b0;\r
+                  vlan_pkt <= 1'b0;\r
+                  op_code_B0 <= 8'd0;\r
+                  vlan_len_B0 <= 8'd0;\r
+\r
+                   if (gbit_en) begin\r
+                     `ifdef SGMII_TSMAC\r
+                       if (tx_en == 1 && byt_cnt == 0) begin\r
+                          byt_cnt <= byt_cnt + 1;\r
+                          pkt_cnt <= pkt_cnt + 1;\r
+                           $fdisplay(out_file, "-----------------------------------------------");\r
+                           $fdisplay(out_file, "PKT %d \t BYTE \t DATA \t TX_EN \t TX_ER", pkt_cnt);\r
+                           $fdisplay(out_file, "-----------------------------------------------");\r
+                           m_st = PREMB;\r
+                      end\r
+                    `else // CLASSIC_TSMAC OR GBE_MAC\r
+                       if (tx_en == 1 && byt_cnt == 0) begin\r
+                          byt_cnt <= byt_cnt + 1;\r
+                          pkt_cnt <= pkt_cnt + 1;\r
+                           $fdisplay(out_file, "-----------------------------------------------");\r
+                           $fdisplay(out_file, "PKT %d \t BYTE \t DATA \t TX_EN \t TX_ER", pkt_cnt);\r
+                           $fdisplay(out_file, "-----------------------------------------------");\r
+                           m_st = PREMB;\r
+                      end\r
+                    `endif\r
+\r
+                    end\r
+                   else begin\r
+                 \r
+                       if (tx_en_1d == 1 && byt_cnt == 0) begin\r
+                         byt_cnt <= byt_cnt + 1;\r
+                         pkt_cnt <= pkt_cnt + 1;\r
+                          $fdisplay(out_file, "-----------------------------------------------");\r
+                          $fdisplay(out_file, "PKT %d \t BYTE \t DATA \t TX_EN \t TX_ER", pkt_cnt);\r
+                          $fdisplay(out_file, "-----------------------------------------------");\r
+                          m_st = PREMB;\r
+                      end\r
+\r
+                    end\r
+                end\r
+             PREMB:\r
+                begin\r
+\r
+                   if (gbit_en) begin\r
+\r
+                     `ifdef SGMII_TSMAC\r
+                       if (tx_en_1d && txd_1d[7:0] != 8'hd5 && tx_clk_en == 1) begin\r
+                          byt_cnt <= byt_cnt + 1;\r
+                           $fdisplay(out_file, "preamble \t %d \t %h \t %b \t %b",byt_cnt,txd_1d,tx_en_1d,tx_er_1d);\r
+                           m_st = PREMB;\r
+                       end\r
+                      else if (tx_en_1d && txd_1d[7:0] == 8'hd5 && tx_clk_en == 1) begin\r
+                          byt_cnt <= 1;\r
+                           $fdisplay(out_file, "SFD \t \t \t %h \t %b \t %b",txd_1d,tx_en_1d,tx_er_1d);\r
+                           m_st = PKT_BODY;\r
+                       end\r
+                    `else // CLASSIC_TSMAC OR GBE_MAC\r
+                       if (tx_en_1d && txd_1d[7:0] != 8'hd5) begin\r
+                          byt_cnt <= byt_cnt + 1;\r
+                           $fdisplay(out_file, "preamble \t %d \t %h \t %b \t %b",byt_cnt,txd_1d,tx_en_1d,tx_er_1d);\r
+                           m_st = PREMB;\r
+                       end\r
+                      else if (tx_en_1d && txd_1d[7:0] == 8'hd5) begin\r
+                          byt_cnt <= 1;\r
+                           $fdisplay(out_file, "SFD \t \t \t %h \t %b \t %b",txd_1d,tx_en_1d,tx_er_1d);\r
+                           m_st = PKT_BODY;\r
+                       end\r
+                    `endif\r
+\r
+                    end\r
+                   else begin\r
+                           \r
+                      if (tx_en_2d && txd_fe_B[7:0] != 8'hd5) begin\r
+                        if (byte_valid_fe) begin\r
+                         byt_cnt <= byt_cnt + 1;\r
+                          $fdisplay(out_file, "preamble \t %d \t %h \t %b \t %b",byt_cnt,txd_fe_B,tx_en_2d,tx_er_2d);\r
+                          m_st = PREMB;\r
+                        end\r
+                      end\r
+                     else if (tx_en_2d && txd_fe_B[7:0] == 8'hd5) begin\r
+                        if (byte_valid_fe) begin\r
+                         byt_cnt <= 1;\r
+                          $fdisplay(out_file, "SFD \t \t \t %h \t %b \t %b",txd_fe_B,tx_en_2d,tx_er_2d);\r
+                          m_st = PKT_BODY;\r
+                        end\r
+                      end\r
+\r
+                    end\r
+\r
+                end\r
+             PKT_BODY:\r
+                begin\r
+\r
+                   if (gbit_en) begin\r
+\r
+                     `ifdef SGMII_TSMAC\r
+                      if (tx_en_1d && tx_clk_en == 1) begin    \r
+                    `else // CLASSIC_TSMAC OR GBE_MAC\r
+                       if (tx_en_1d) begin\r
+                    `endif\r
+                          byt_cnt <= byt_cnt + 1;\r
+                           m_st = PKT_BODY;\r
+                          \r
+                          if (byt_cnt == 12'd1) begin\r
+                             crc_reg = nextCRC32_D8(txd_1d, CRC_INIT_VALUE);\r
+                           end\r
+                          else if (byt_cnt == (len_B0B1 + 12'd15)) begin\r
+                              crc_reg_latched = crc_rev(crc_reg);\r
+                           end\r
+                          else begin\r
+                             crc_reg = nextCRC32_D8(txd_1d, crc_reg);\r
+                           end\r
+                          \r
+                          if (byt_cnt == 12'd13) begin\r
+                                 len_B0 <= txd_1d;\r
+                          end \r
+                          if (byt_cnt == 12'd15 && control_pkt) begin\r
+                                 op_code_B0 <= txd_1d;\r
+                          end \r
+                          if (byt_cnt == 12'd17 && vlan_pkt) begin\r
+                                 vlan_len_B0 <= txd_1d;\r
+                          end \r
+                          if (byt_cnt == 12'd14) begin\r
+                                  if ({len_B0,txd_1d} < 16'd46) begin // short pkt \r
+                                    len_B0B1 <= 16'd46;\r
+                                  end\r
+                                  else if ({len_B0,txd_1d} == 16'h8808) begin // control pkt \r
+                                    control_pkt <= 1'b1;\r
+                                  end\r
+                                  else if ({len_B0,txd_1d} == 16'h8100) begin // vlan tagged pkt \r
+                                    vlan_pkt <= 1'b1;\r
+                                  end\r
+                                  else begin\r
+                                    len_B0B1 <= {len_B0,txd_1d};\r
+                                  end\r
+                          end\r
+                          else if (byt_cnt == 12'd16 && control_pkt) begin\r
+                                  if ({op_code_B0,txd_1d} == 16'h0001) begin // pause pkt\r
+                                    pause_pkt <= 1'b1; \r
+                                    len_B0B1 <= 16'd46;\r
+                                  end\r
+                          end\r
+                          else if (byt_cnt == 12'd18 && vlan_pkt) begin\r
+                                  len_B0B1 <= {vlan_len_B0,txd_1d} + 16'd4;\r
+                          end\r
+                          \r
+                          if (byt_cnt == (len_B0B1 + 12'd15)) begin\r
+                                 Rx_CRC_B0 <= txd_1d;\r
+                          end \r
+                          if (byt_cnt == (len_B0B1 + 12'd16)) begin\r
+                                 Rx_CRC_B1 <= txd_1d;\r
+                          end\r
+                          if (byt_cnt == (len_B0B1 + 12'd17)) begin\r
+                                 Rx_CRC_B2 <= txd_1d;\r
+                          end\r
+                          if (byt_cnt == (len_B0B1 + 12'd18)) begin\r
+                                 Rx_CRC <= {txd_1d,Rx_CRC_B2,Rx_CRC_B1,Rx_CRC_B0};\r
+                          end\r
+                          \r
+                          if (byt_cnt >= 12'd1 && byt_cnt <= 12'd6 ) begin\r
+                              $fdisplay(out_file, "DA \t \t %d \t %h \t %b \t %b",byt_cnt,txd_1d,tx_en_1d,tx_er_1d);\r
+                          end\r
+                          else if (byt_cnt >= 12'd7 && byt_cnt <= 12'd12 ) begin\r
+                              $fdisplay(out_file, "SA \t \t %d \t %h \t %b \t %b",byt_cnt,txd_1d,tx_en_1d,tx_er_1d);\r
+                          end\r
+                          else if (byt_cnt >= 12'd13 && byt_cnt <= 12'd14 ) begin\r
+                             if ((byt_cnt == 12'd13 && txd_1d == 8'h81) \r
+                                  || (byt_cnt == 12'd14 && {len_B0,txd_1d} == 16'h8100)) begin\r
+                                $fdisplay(out_file, "TAG \t \t %d \t %h \t %b \t %b",byt_cnt,txd_1d,tx_en_1d,tx_er_1d);\r
+                             end\r
+                             else begin\r
+                                $fdisplay(out_file, "LT \t \t %d \t %h \t %b \t %b",byt_cnt,txd_1d,tx_en_1d,tx_er_1d);\r
+                             end\r
+                          end\r
+                          else if ((byt_cnt >= 12'd15 && byt_cnt <= 12'd16) && vlan_pkt ) begin\r
+                              $fdisplay(out_file, "TAGC \t \t %d \t %h \t %b \t %b",byt_cnt,txd_1d,tx_en_1d,tx_er_1d);\r
+                          end\r
+                          else if ((byt_cnt >= 12'd17 && byt_cnt <= 12'd18) && vlan_pkt ) begin\r
+                              $fdisplay(out_file, "LT \t \t %d \t %h \t %b \t %b",byt_cnt,txd_1d,tx_en_1d,tx_er_1d);\r
+                          end\r
+                          else if (byt_cnt >= (len_B0B1 + 12'd15) && byt_cnt <= (len_B0B1 + 12'd18) ) begin\r
+                              $fdisplay(out_file, "CRC \t \t %d \t %h \t %b \t %b",byt_cnt,txd_1d,tx_en_1d,tx_er_1d);\r
+                          end\r
+                          else begin\r
+                              $fdisplay(out_file, "Data \t \t %d \t %h \t %b \t %b",byt_cnt,txd_1d,tx_en_1d,tx_er_1d);\r
+                          end\r
+                     \r
+                          if (tx_er_1d == 1'b1) begin\r
+                                 tx_error_latched <= 1'b1;\r
+                          end\r
+                          \r
+                       end\r
+                     `ifdef SGMII_TSMAC\r
+                      else if (tx_en_1d == 0 && tx_clk_en == 1) begin  \r
+                    `else // CLASSIC_TSMAC OR GBE_MAC\r
+                      else if (tx_en_1d == 0) begin\r
+                    `endif\r
+                          byt_cnt <= 0;\r
+                           $fdisplay(out_file, "-----------------------------------------------");\r
+                           $fdisplay(out_file, "RECEIVED CRC \t \t %h ",Rx_CRC);\r
+                           $fdisplay(out_file, "EXPECTED CRC \t \t %h ",crc_reg_latched);\r
+                          if ( Rx_CRC == crc_reg_latched && !tx_error_latched) begin\r
+                                  $fdisplay(out_file, "GOOD PKT");\r
+                          end\r
+                          else begin\r
+                                  $fdisplay(out_file, "BAD PKT");\r
+                          end\r
+                          if (pause_pkt) begin\r
+                                  $fdisplay(out_file, "THIS IS A PAUSE PACKET");\r
+                          end\r
+                          else if (vlan_pkt) begin\r
+                                  $fdisplay(out_file, "THIS IS A VLAN TAGGED PACKET");\r
+                          end\r
+                           $fdisplay(out_file, " ");\r
+                           $fdisplay(out_file, " ");\r
+                           $fdisplay(out_file, " ");\r
+                           m_st = IDLE;\r
+                       end\r
+                       \r
+                    end // (gbit_en)\r
+                   else begin  // gbit_en == 0 (10/100 mode)\r
+                      \r
+                       if (tx_en_2d) begin\r
+                             \r
+                          if (byte_valid_fe) begin\r
+                                  \r
+                             byt_cnt <= byt_cnt + 1;\r
+                              m_st = PKT_BODY;\r
+                          \r
+                             if (byt_cnt == 12'd1) begin\r
+                                crc_reg = nextCRC32_D8(txd_fe_B, CRC_INIT_VALUE);\r
+                              end\r
+                             else if (byt_cnt == (len_B0B1 + 12'd15)) begin\r
+                                crc_reg_latched = crc_rev(crc_reg);\r
+                              end\r
+                             else begin\r
+                                crc_reg = nextCRC32_D8(txd_fe_B, crc_reg);\r
+                              end\r
+                          \r
+\r
+                             if (byt_cnt == 12'd13) begin\r
+                                 len_B0 <= txd_fe_B;\r
+                            end \r
+                            if (byt_cnt == 12'd15 && control_pkt) begin\r
+                                   op_code_B0 <= txd_1d;\r
+                            end \r
+                             if (byt_cnt == 12'd17 && vlan_pkt) begin\r
+                                 vlan_len_B0 <= txd_fe_B;\r
+                            end \r
+                            if (byt_cnt == 12'd14) begin\r
+                                    if ({len_B0,txd_fe_B} < 16'd46) begin // short pkt \r
+                                      len_B0B1 <= 16'd46;\r
+                                    end\r
+                                    else if ({len_B0,txd_fe_B} == 16'h8808) begin // control pkt \r
+                                      control_pkt <= 1'b1;\r
+                                    end\r
+                                    else if ({len_B0,txd_fe_B} == 16'h8100) begin // vlan tagged pkt \r
+                                      vlan_pkt <= 1'b1;\r
+                                    end\r
+                                    else begin\r
+                                      len_B0B1 <= {len_B0,txd_fe_B};\r
+                                    end\r
+                            end\r
+                            else if (byt_cnt == 12'd16 && control_pkt) begin\r
+                                    if ({op_code_B0,txd_fe_B} == 16'h0001) begin // pause pkt\r
+                                      pause_pkt <= 1'b1; \r
+                                      len_B0B1 <= 16'd46;\r
+                                    end\r
+                            end\r
+                             else if (byt_cnt == 12'd18 && vlan_pkt) begin\r
+                                  len_B0B1 <= {vlan_len_B0,txd_fe_B} + 16'd4;\r
+                            end\r
+\r
+                             \r
+                             if (byt_cnt == (len_B0B1 + 12'd15)) begin\r
+                                 Rx_CRC_B0 <= txd_fe_B;\r
+                             end \r
+                             if (byt_cnt == (len_B0B1 + 12'd16)) begin\r
+                                 Rx_CRC_B1 <= txd_fe_B;\r
+                             end\r
+                             if (byt_cnt == (len_B0B1 + 12'd17)) begin\r
+                                 Rx_CRC_B2 <= txd_fe_B;\r
+                             end\r
+                             if (byt_cnt == (len_B0B1 + 12'd18)) begin\r
+                                 Rx_CRC <= {txd_fe_B,Rx_CRC_B2,Rx_CRC_B1,Rx_CRC_B0};\r
+                             end\r
+                          \r
+                             if (byt_cnt >= 12'd1 && byt_cnt <= 12'd6 ) begin\r
+                                 $fdisplay(out_file, "DA \t \t %d \t %h \t %b \t %b",byt_cnt,txd_fe_B,tx_en_2d,tx_er_2d);\r
+                             end\r
+                             else if (byt_cnt >= 12'd7 && byt_cnt <= 12'd12 ) begin\r
+                                 $fdisplay(out_file, "SA \t \t %d \t %h \t %b \t %b",byt_cnt,txd_fe_B,tx_en_2d,tx_er_2d);\r
+                             end\r
+                             else if (byt_cnt >= 12'd13 && byt_cnt <= 12'd14 ) begin\r
+                                if ((byt_cnt == 12'd13 && txd_fe_B == 8'h81) \r
+                                  || (byt_cnt == 12'd14 && {len_B0,txd_fe_B} == 16'h8100)) begin\r
+                                   $fdisplay(out_file, "TAG \t \t %d \t %h \t %b \t %b",byt_cnt,txd_fe_B,tx_en_2d,tx_er_2d);\r
+                                end\r
+                                else begin\r
+                                   $fdisplay(out_file, "LT \t \t %d \t %h \t %b \t %b",byt_cnt,txd_fe_B,tx_en_2d,tx_er_2d);\r
+                                end\r
+                             end\r
+                             else if ((byt_cnt >= 12'd15 && byt_cnt <= 12'd16) && vlan_pkt ) begin\r
+                                 $fdisplay(out_file, "TAGC \t \t %d \t %h \t %b \t %b",byt_cnt,txd_fe_B,tx_en_2d,tx_er_2d);\r
+                             end\r
+                             else if ((byt_cnt >= 12'd17 && byt_cnt <= 12'd18) && vlan_pkt ) begin\r
+                                 $fdisplay(out_file, "LT \t \t %d \t %h \t %b \t %b",byt_cnt,txd_fe_B,tx_en_2d,tx_er_2d);\r
+                             end\r
+                             else if (byt_cnt >= (len_B0B1 + 12'd15) && byt_cnt <= (len_B0B1 + 12'd18) ) begin\r
+                                 $fdisplay(out_file, "CRC \t \t %d \t %h \t %b \t %b",byt_cnt,txd_fe_B,tx_en_2d,tx_er_2d);\r
+                             end\r
+                             else begin\r
+                                 $fdisplay(out_file, "Data \t \t %d \t %h \t %b \t %b",byt_cnt,txd_fe_B,tx_en_2d,tx_er_2d);\r
+                             end\r
+                    \r
+                             if (tx_er_2d == 1'b1) begin\r
+                                 tx_error_latched <= 1'b1;\r
+                             end\r
+                             \r
+                          end // if (byte_valid_fe)\r
+                          \r
+                       end //  if (tx_en_2d)\r
+                       else if (tx_en_2d == 0) begin\r
+                           byt_cnt <= 0;\r
+                           $fdisplay(out_file, "-----------------------------------------------");\r
+                           $fdisplay(out_file, "RECEIVED CRC \t \t %h ",Rx_CRC);\r
+                           $fdisplay(out_file, "EXPECTED CRC \t \t %h ",crc_reg_latched);\r
+                          if ( Rx_CRC == crc_reg_latched && !tx_error_latched) begin\r
+                                  $fdisplay(out_file, "GOOD PKT");\r
+                          end\r
+                          else begin\r
+                                  $fdisplay(out_file, "BAD PKT");\r
+                          end\r
+                          if (pause_pkt) begin\r
+                                  $fdisplay(out_file, "THIS IS A PAUSE PACKET");\r
+                          end\r
+                          else if (vlan_pkt) begin\r
+                                  $fdisplay(out_file, "THIS IS A VLAN TAGGED PACKET");\r
+                          end\r
+                           $fdisplay(out_file, " ");\r
+                           $fdisplay(out_file, " ");\r
+                           $fdisplay(out_file, " ");\r
+                           m_st = IDLE;\r
+                       end //  if (tx_en_2d == 0)\r
+                       \r
+                    end // gbit_en == 0 (10/100 mode)\r
+                  \r
+                end // PKT_BODY\r
+        endcase //case (m_st)\r
+\r
+end //always@( posedge tx_clk) begin\r
+\r
+\r
+function [31:0] nextCRC32_D8;\r
+\r
+      input [7:0] Data;\r
+      input [31:0] CRC;\r
+      \r
+      reg [7:0] D;\r
+      reg [31:0] C;\r
+      reg [31:0] NewCRC;\r
+\r
+  begin\r
+     D[0] = Data[7];\r
+     D[1] = Data[6];\r
+     D[2] = Data[5];\r
+     D[3] = Data[4];\r
+     D[4] = Data[3];\r
+     D[5] = Data[2];\r
+     D[6] = Data[1];\r
+     D[7] = Data[0];\r
+     C = CRC;\r
+     \r
+     NewCRC[0] = D[6] ^ D[0] ^ C[24] ^ C[30];\r
+     NewCRC[1] = D[7] ^ D[6] ^ D[1] ^ D[0] ^ C[24] ^ C[25] ^ C[30] ^ \r
+                 C[31];\r
+     NewCRC[2] = D[7] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^ C[24] ^ C[25] ^ \r
+                 C[26] ^ C[30] ^ C[31];\r
+     NewCRC[3] = D[7] ^ D[3] ^ D[2] ^ D[1] ^ C[25] ^ C[26] ^ C[27] ^ \r
+                 C[31];\r
+     NewCRC[4] = D[6] ^ D[4] ^ D[3] ^ D[2] ^ D[0] ^ C[24] ^ C[26] ^ \r
+                 C[27] ^ C[28] ^ C[30];\r
+     NewCRC[5] = D[7] ^ D[6] ^ D[5] ^ D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[24] ^ \r
+                C[25] ^ C[27] ^ C[28] ^ C[29] ^ C[30] ^ C[31];\r
+     NewCRC[6] = D[7] ^ D[6] ^ D[5] ^ D[4] ^ D[2] ^ D[1] ^ C[25] ^ C[26] ^ \r
+                C[28] ^ C[29] ^ C[30] ^ C[31];\r
+     NewCRC[7] = D[7] ^ D[5] ^ D[3] ^ D[2] ^ D[0] ^ C[24] ^ C[26] ^ \r
+                 C[27] ^ C[29] ^ C[31];\r
+     NewCRC[8] = D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[0] ^ C[24] ^ C[25] ^ \r
+                 C[27] ^ C[28];\r
+     NewCRC[9] = D[5] ^ D[4] ^ D[2] ^ D[1] ^ C[1] ^ C[25] ^ C[26] ^ \r
+                 C[28] ^ C[29];\r
+     NewCRC[10] = D[5] ^ D[3] ^ D[2] ^ D[0] ^ C[2] ^ C[24] ^ C[26] ^ \r
+                  C[27] ^ C[29];\r
+     NewCRC[11] = D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[3] ^ C[24] ^ C[25] ^ \r
+                 C[27] ^ C[28];\r
+     NewCRC[12] = D[6] ^ D[5] ^ D[4] ^ D[2] ^ D[1] ^ D[0] ^ C[4] ^ C[24] ^ \r
+                  C[25] ^ C[26] ^ C[28] ^ C[29] ^ C[30];\r
+     NewCRC[13] = D[7] ^ D[6] ^ D[5] ^ D[3] ^ D[2] ^ D[1] ^ C[5] ^ C[25] ^ \r
+                  C[26] ^ C[27] ^ C[29] ^ C[30] ^ C[31];\r
+     NewCRC[14] = D[7] ^ D[6] ^ D[4] ^ D[3] ^ D[2] ^ C[6] ^ C[26] ^ C[27] ^ \r
+                  C[28] ^ C[30] ^ C[31];\r
+     NewCRC[15] = D[7] ^ D[5] ^ D[4] ^ D[3] ^ C[7] ^ C[27] ^ C[28] ^ \r
+                  C[29] ^ C[31];\r
+     NewCRC[16] = D[5] ^ D[4] ^ D[0] ^ C[8] ^ C[24] ^ C[28] ^ C[29];\r
+     NewCRC[17] = D[6] ^ D[5] ^ D[1] ^ C[9] ^ C[25] ^ C[29] ^ C[30];\r
+     NewCRC[18] = D[7] ^ D[6] ^ D[2] ^ C[10] ^ C[26] ^ C[30] ^ C[31];\r
+     NewCRC[19] = D[7] ^ D[3] ^ C[11] ^ C[27] ^ C[31];\r
+     NewCRC[20] = D[4] ^ C[12] ^ C[28];\r
+     NewCRC[21] = D[5] ^ C[13] ^ C[29];\r
+     NewCRC[22] = D[0] ^ C[14] ^ C[24];\r
+     NewCRC[23] = D[6] ^ D[1] ^ D[0] ^ C[15] ^ C[24] ^ C[25] ^ C[30];\r
+     NewCRC[24] = D[7] ^ D[2] ^ D[1] ^ C[16] ^ C[25] ^ C[26] ^ C[31];\r
+     NewCRC[25] = D[3] ^ D[2] ^ C[17] ^ C[26] ^ C[27];\r
+     NewCRC[26] = D[6] ^ D[4] ^ D[3] ^ D[0] ^ C[18] ^ C[24] ^ C[27] ^ \r
+                  C[28] ^ C[30];\r
+     NewCRC[27] = D[7] ^ D[5] ^ D[4] ^ D[1] ^ C[19] ^ C[25] ^ C[28] ^ \r
+                  C[29] ^ C[31];\r
+     NewCRC[28] = D[6] ^ D[5] ^ D[2] ^ C[20] ^ C[26] ^ C[29] ^ C[30];\r
+     NewCRC[29] = D[7] ^ D[6] ^ D[3] ^ C[21] ^ C[27] ^ C[30] ^ C[31];\r
+     NewCRC[30] = D[7] ^ D[4] ^ C[22] ^ C[28] ^ C[31];\r
+     NewCRC[31] = D[5] ^ C[23] ^ C[29];\r
+     \r
+     nextCRC32_D8 = NewCRC;\r
+\r
+  end\r
+\r
+endfunction\r
+\r
+\r
+function [31:0] crc_rev;\r
+      \r
+      input [31:0] data_in;\r
+      integer crc_i;\r
+   begin    \r
+      for (crc_i = 0; crc_i < 32; crc_i = crc_i+1) begin\r
+         crc_rev[crc_i] = ~data_in[31 - crc_i]; \r
+      end\r
+   end\r
+endfunction\r
+       \r
+endmodule\r
+\r

diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/rdwr_task.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/rdwr_task.v
new file mode 100644 (file)
index 0000000..f88f46a
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/rdwr_task.v
@@ -0,0 +1,50 @@
+// ===========================================================================\r
+// Verilog module generated by IPexpress\r
+// Filename: rdwr_task.v  \r
+// Copyright 2005 (c) Lattice Semiconductor Corporation. All rights reserved.\r
+// ===========================================================================\r
+\r
+// MPI Write\r
+task orc_write;\r
+input [17:0]   address;\r
+input  [7:0]   data;\r
+reg            ret_status;\r
+begin\r
+orcastra_drv.single_write(address,data,ret_status);\r
+end\r
+endtask\r
+\r
+// MPI Read\r
+task orc_read;\r
+input  [17:0]  address;\r
+output  [7:0]  data;\r
+reg            ret_status;\r
+reg    [7:0]   read_data;\r
+begin\r
+orcastra_drv.single_read(address,read_data,ret_status);\r
+data = read_data[7:0];\r
+$display(" READ at address: %h at time: %t data is : %h", address, $time, data ) ;\r
+end\r
+endtask\r
+\r
+// Register Write\r
+task reg_wr;\r
+input [17:0]   waddr;\r
+input  [7:0]   wdata;\r
+begin\r
+   orc_write(waddr,wdata);\r
+end\r
+endtask\r
+\r
+// Register Read\r
+task reg_rd;\r
+input [17:0]   raddr;\r
+output [7:0]   rdata;\r
+reg    [7:0]   read_data;\r
+begin\r
+   orc_read(raddr,read_data);\r
+   rdata = read_data;\r
+end\r
+endtask\r
+\r
+\r

diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/rx_gen_tasks.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/rx_gen_tasks.v
new file mode 100644 (file)
index 0000000..de3b30a
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/rx_gen_tasks.v
@@ -0,0 +1,853 @@
+// ===========================================================================
+// Verilog module generated by IPexpress
+// Filename: rx_gen_tasks.v  
+// Copyright 2005 (c) Lattice Semiconductor Corporation. All rights reserved.
+// ===========================================================================
+
+   task rx_frmgen;
+ /*( gben,
+                 des_addr,
+                 frm_len,
+                 num_premb,
+                 num_ipg,
+                 badcrc,         //1'b0 is for good crc, 1'b1 is for bad crc 
+                 norm_vlan_paus, //2'b00 is for normal frame, 2'b01 is for VLAN tagged frame,
+                                 //2'b10 is for pause frame, 
+                                 //2'b11 is for pause frame with customized des_addr
+                 pause_timer,    //valid only when norm_vlan_paus is set to 2'b10
+                 bad_pcode,      //1'b0 is for good pause op-code, 1'b1 is for bad pause op-code
+                 len_type,       //1'b0 is for length field, 1'b1 is for type field
+                 len_chkerr,     //1'b0 is for no length check error, 
+                                 //1'b1 is for generating length check error
+                 badsfd,         //1'b0 is for good sfd, 1'b1 is for bad sfd
+                 runt_frmid,
+                 frm_patn       //4'd0 is a normal frame without any following condition
+                                 //4'd1 is for assert one clock long rx_er during frame     
+                                 //4'd2 is for non-padded frame which is less than 64 bytes
+                                 //4'd14 is for non-padded frame which is less than 64 with dribble nibble
+                                 //4'd15 is for dribble nibble frame
+                 );*/
+      input        gben;              //bit 0 in frm_info
+      input [47:0] des_addr;          //bit 48:1 in frm_info
+      input [13:0] frm_len;           //bit 62:49 in frm_info
+      input [3:0]  num_premb;         //bit 66:63 in frm_info
+      input [4:0]  num_ipg;           //bit 71:67 in frm_info
+      input        badcrc;            //bit 72 in frm_info
+      input [1:0]  norm_vlan_paus;    //bit 74:73 in frm_info
+      input [15:0] pause_timer;       //bit 90:75 in frm_info
+      input        bad_pcode;         //bit 91 in frm_info
+      input        len_type;          //bit 92 in frm_info  
+      input        len_chkerr;        //bit 93 in frm_info 
+      input        badsfd;            //bit 94 in frm_info
+      input [2:0]  runt_frmid;        //bit 97:95 in frm_info
+      input [3:0]  frm_patn;          //bit 101:98 in frm_info
+
+      integer i;
+      reg [13:0] reg_i;
+      reg [13:0] data_len;
+      
+      reg [7:0] strt_rxd;
+      reg [31:0] crc_reg;
+      reg [101:0] frm_info;
+
+      reg [7:0] rxd_reg;
+      //reg       rxdv;
+      //reg       rxer;
+      //reg [7:0] rxd;
+      event frm_data;
+      
+      
+      parameter PREAMBLE_NIB = 4'h5;
+      parameter SFD_NIB1 = 4'hd;
+      parameter GOODSFD_NIB2 = 4'h5;
+      parameter BADSFD_NIB2 = 4'h3;
+      parameter RNDM_FRM_TYPE1 = 4'h5;
+      parameter RNDM_FRM_TYPE2 = 4'hd;
+      parameter CRC_INIT_VALUE = 32'hffff_ffff;
+      parameter TAG_CTRL_NIB1 = 4'd1;
+      parameter TAG_CTRL_NIB2 = 4'd2;
+      parameter TAG_CTRL_NIB3 = 4'd3;
+      parameter TAG_CTRL_NIB4 = 4'd4;
+      parameter PAUSE_LENTYPE1 = 4'h8; //length/type field for pause frame is 16'h8808
+      parameter PAUSE_LENTYPE2 = 4'h0; //reversed version of it is 16'h1110 
+      parameter PAUSE_LENTYPE3 = 4'h8;
+      parameter PAUSE_LENTYPE4 = 4'h8;
+      
+      parameter PAUSE_DES_NIB0 = 4'h1; //destination address for pause frame is 48'h0180_c200_0001
+      parameter PAUSE_DES_NIB1 = 4'h0;
+      parameter PAUSE_DES_NIB2 = 4'h0;
+      parameter PAUSE_DES_NIB3 = 4'h0;
+      parameter PAUSE_DES_NIB4 = 4'h0;
+      parameter PAUSE_DES_NIB5 = 4'h0;
+      parameter PAUSE_DES_NIB6 = 4'h2;
+      parameter PAUSE_DES_NIB7 = 4'hc;
+      parameter PAUSE_DES_NIB8 = 4'h0;
+      parameter PAUSE_DES_NIB9 = 4'h8;
+      parameter PAUSE_DES_NIB10 = 4'h1;
+      parameter PAUSE_DES_NIB11 = 4'h0;
+
+//      parameter PAUSE_OP_NIB1 = 4'h0;
+//      parameter PAUSE_OP_NIB2 = 4'h0;
+//      parameter PAUSE_OP_NIB3 = 4'h8;
+//      parameter PAUSE_OP_NIB4 = 4'h0;
+
+      parameter PAUSE_D_NIB1 = 4'h0;
+      parameter PAUSE_D_NIB2 = 4'h0;
+  
+      //runt frame ID
+      //8'd0 do not generate runt frame
+      //8'd1 runt frame with preamble only
+      //8'd2 runt frame with preamble and sfd
+      //8'd3 runt frame with preamble, sfd and destination address 
+      //8'd4 runt frame with preamble, sfd, destination address and source address 
+`define PAUSE_OP_NIB4  4'h0
+`define PAUSE_OP_NIB3  4'h0
+`define PAUSE_OP_NIB2  4'h0
+`define PAUSE_OP_NIB1  4'h1
+//`define PAUSE_OP_NIB4 test_ts_mac.U1_ts_mac_top.U1_ts_mac_core.U1_cpu_if.pause_opcode[15:12]   
+//`define PAUSE_OP_NIB3 test_ts_mac.U1_ts_mac_top.U1_ts_mac_core.U1_cpu_if.pause_opcode[11:8]   
+//`define PAUSE_OP_NIB2 test_ts_mac.U1_ts_mac_top.U1_ts_mac_core.U1_cpu_if.pause_opcode[7:4]   
+//`define PAUSE_OP_NIB1 test_ts_mac.U1_ts_mac_top.U1_ts_mac_core.U1_cpu_if.pause_opcode[3:0]   
+
+//`include "rx_gen_tasks.inc.v"
+      
+   begin
+      frm_info = {frm_patn, runt_frmid, badsfd, len_chkerr, len_type, bad_pcode, pause_timer,
+                  norm_vlan_paus, badcrc, num_ipg, num_premb, frm_len, des_addr, gben};
+
+      if (num_ipg == 0) begin  
+        rxdv = 1'b0;
+        rxer = 1'b1;
+        rxd  = 8'h0f; // carrier extend
+      end 
+      else begin
+        rxdv = 1'b0;
+        rxer = 1'b0;
+        rxd  = 8'b0;
+      end 
+
+      $display("INFO:%t New Frame is generated:", $time);
+      if(!norm_vlan_paus[0] && !norm_vlan_paus[1]) 
+        $display("\t\tIt is a normal frame;");
+      else if(norm_vlan_paus[0] && !norm_vlan_paus[1])
+        $display("\t\tIt is a VLAN tagged frame;");
+      else if(norm_vlan_paus[1])
+        $display("\t\tIt is a Pause frame;");
+      $display("\t\tData length is %d(DEC);", frm_len);
+      $display("\t\tDestination address is %h(HEX);", des_addr);
+      $display("\t\t%d bytes of preamble;", num_premb);
+      if(badsfd)
+        $display("\t\tBad SFD will be appended;");
+      $display("\t\tIPG number is %d(DEC);", num_ipg);
+      if(len_chkerr)
+        $display("\t\tLength check err will be generated;");
+      if(badcrc)
+        $display("\t\tBad CRC will be generated.\n");
+      else
+        $display("\t\tGood CRC will be generated.\n");
+        
+      if(num_ipg == 0)
+        $display("\t\t6 clocks of carrier extension will be generated.\n");
+
+      //wait for proper IPG or 6 clks of Carrier Extend
+      if (num_ipg == 0) begin  
+         repeat (6) begin
+            @(negedge rxmac_clk);
+         end
+      end 
+      else begin
+         repeat (num_ipg-1) begin
+            @(negedge rxmac_clk);
+         end
+      end 
+
+      crc_reg = 32'hffff_ffff;
+      
+      //Preamble generation
+      if(num_premb > 4'd0) begin
+         repeat (num_premb) begin
+           @(negedge rxmac_clk)
+            rxdv = 1'b1;
+           
+            if (num_ipg == 0) begin  // carrier extend
+              rxer = 1'b0;
+            end
+           
+            rxd_reg = {PREAMBLE_NIB, PREAMBLE_NIB};
+            if (gben == 1) begin
+              rxd[7:0] = rxd_reg[7:0];
+            end else begin
+              rxd[3:0] = rxd_reg[3:0];
+               @(posedge rxmac_clk)
+              rxd[3:0] = rxd_reg[7:4];
+            end
+           //$display ("%t rxd_reg is %h\n", $time, rxd_reg);
+         end // repeat (num_premb)
+      end // if (num_premb > 4'd0)
+
+
+      //SFD generation
+      if(runt_frmid !== 8'd1) begin
+         if(!badsfd) begin
+           @(negedge rxmac_clk)
+            rxdv = 1'b1;
+            rxd_reg = {SFD_NIB1, GOODSFD_NIB2};
+         end // if (!badsfd)
+         else begin
+            @(negedge rxmac_clk)
+            rxdv = 1'b1;
+            rxd_reg = {SFD_NIB1, BADSFD_NIB2};
+         end
+      end
+      if (gben == 1) begin
+        rxd[7:0] = rxd_reg[7:0];
+      end else begin
+        rxd[3:0] = rxd_reg[3:0];
+         @(posedge rxmac_clk)
+        rxd[3:0] = rxd_reg[7:4];
+      end
+      
+      //destination address generation
+      if (norm_vlan_paus == 2'b10) begin //pause frame
+         @(negedge rxmac_clk)
+         rxd_reg = {PAUSE_DES_NIB11, PAUSE_DES_NIB10};
+         crc_reg = nextCRC32_D8(rxd_reg, CRC_INIT_VALUE);
+         if (gben == 1) begin
+           rxd[7:0] = rxd_reg[7:0];
+         end else begin
+           rxd[3:0] = rxd_reg[3:0];
+            @(posedge rxmac_clk)
+           rxd[3:0] = rxd_reg[7:4];
+         end
+         @(negedge rxmac_clk)
+         rxd_reg = {PAUSE_DES_NIB9, PAUSE_DES_NIB8};
+         crc_reg = nextCRC32_D8(rxd_reg, crc_reg);
+         if (gben == 1) begin
+           rxd[7:0] = rxd_reg[7:0];
+         end else begin
+           rxd[3:0] = rxd_reg[3:0];
+            @(posedge rxmac_clk)
+           rxd[3:0] = rxd_reg[7:4];
+         end
+         @(negedge rxmac_clk)
+         rxd_reg = {PAUSE_DES_NIB7, PAUSE_DES_NIB6};
+         crc_reg = nextCRC32_D8(rxd_reg, crc_reg);
+         if (gben == 1) begin
+           rxd[7:0] = rxd_reg[7:0];
+         end else begin
+           rxd[3:0] = rxd_reg[3:0];
+            @(posedge rxmac_clk)
+           rxd[3:0] = rxd_reg[7:4];
+         end
+         @(negedge rxmac_clk)
+         rxd_reg = {PAUSE_DES_NIB5, PAUSE_DES_NIB4};
+         crc_reg = nextCRC32_D8(rxd_reg, crc_reg);
+         if (gben == 1) begin
+           rxd[7:0] = rxd_reg[7:0];
+         end else begin
+           rxd[3:0] = rxd_reg[3:0];
+            @(posedge rxmac_clk)
+           rxd[3:0] = rxd_reg[7:4];
+         end
+         @(negedge rxmac_clk)
+         rxd_reg = {PAUSE_DES_NIB3, PAUSE_DES_NIB2};
+         crc_reg = nextCRC32_D8(rxd_reg, crc_reg);
+         if (gben == 1) begin
+           rxd[7:0] = rxd_reg[7:0];
+         end else begin
+           rxd[3:0] = rxd_reg[3:0];
+            @(posedge rxmac_clk)
+           rxd[3:0] = rxd_reg[7:4];
+         end
+         @(negedge rxmac_clk)
+         rxd_reg = {PAUSE_DES_NIB1, PAUSE_DES_NIB0};
+         crc_reg = nextCRC32_D8(rxd_reg, crc_reg);
+         if (gben == 1) begin
+           rxd[7:0] = rxd_reg[7:0];
+         end else begin
+           rxd[3:0] = rxd_reg[3:0];
+            @(posedge rxmac_clk)
+           rxd[3:0] = rxd_reg[7:4];
+         end
+      end // if (norm_vlan_paus == 2'b10)
+      else begin
+         if( (runt_frmid !== 8'd1) && (runt_frmid !== 8'd2) ) begin
+            @(negedge rxmac_clk)
+            rxd_reg = des_addr[47:40];
+            crc_reg = nextCRC32_D8(rxd_reg, CRC_INIT_VALUE);
+            if (gben == 1) begin
+              rxd[7:0] = rxd_reg[7:0];
+            end else begin
+              rxd[3:0] = rxd_reg[3:0];
+               @(posedge rxmac_clk)
+              rxd[3:0] = rxd_reg[7:4];
+            end
+            @(negedge rxmac_clk)
+            rxd_reg = des_addr[39:32];
+            crc_reg = nextCRC32_D8(rxd_reg, crc_reg);
+            if (gben == 1) begin
+              rxd[7:0] = rxd_reg[7:0];
+            end else begin
+              rxd[3:0] = rxd_reg[3:0];
+               @(posedge rxmac_clk)
+              rxd[3:0] = rxd_reg[7:4];
+            end
+            @(negedge rxmac_clk)
+            rxd_reg = des_addr[31:24];
+            crc_reg = nextCRC32_D8(rxd_reg, crc_reg);
+            if (gben == 1) begin
+              rxd[7:0] = rxd_reg[7:0];
+            end else begin
+              rxd[3:0] = rxd_reg[3:0];
+               @(posedge rxmac_clk)
+              rxd[3:0] = rxd_reg[7:4];
+            end
+            @(negedge rxmac_clk)
+            rxd_reg = des_addr[23:16];
+            crc_reg = nextCRC32_D8(rxd_reg, crc_reg);
+            if (gben == 1) begin
+              rxd[7:0] = rxd_reg[7:0];
+            end else begin
+              rxd[3:0] = rxd_reg[3:0];
+               @(posedge rxmac_clk)
+              rxd[3:0] = rxd_reg[7:4];
+            end
+            @(negedge rxmac_clk)
+            rxd_reg = des_addr[15:8];
+            crc_reg = nextCRC32_D8(rxd_reg, crc_reg);
+            if (gben == 1) begin
+              rxd[7:0] = rxd_reg[7:0];
+            end else begin
+              rxd[3:0] = rxd_reg[3:0];
+               @(posedge rxmac_clk)
+              rxd[3:0] = rxd_reg[7:4];
+            end
+            @(negedge rxmac_clk)
+            rxd_reg = des_addr[7:0];
+            crc_reg = nextCRC32_D8(rxd_reg, crc_reg);
+            if (gben == 1) begin
+              rxd[7:0] = rxd_reg[7:0];
+            end else begin
+              rxd[3:0] = rxd_reg[3:0];
+               @(posedge rxmac_clk)
+              rxd[3:0] = rxd_reg[7:4];
+            end
+         end // if ( (runt_frmid !== 8'd1) && (runt_frmid !== 8'd2) )
+      end // else: !if(norm_vlan_paus == 2'b10)
+         
+      //source address generation
+      if( (runt_frmid !== 8'd1) && (runt_frmid !== 8'd2) && (runt_frmid !== 8'd3) ) begin
+         @(negedge rxmac_clk)
+         rxd_reg = {`SRC_NIB11, `SRC_NIB10};
+         crc_reg = nextCRC32_D8(rxd_reg, crc_reg);
+         if (gben == 1) begin
+           rxd[7:0] = rxd_reg[7:0];
+         end else begin
+           rxd[3:0] = rxd_reg[3:0];
+            @(posedge rxmac_clk)
+           rxd[3:0] = rxd_reg[7:4];
+         end
+         @(negedge rxmac_clk)
+         rxd_reg = {`SRC_NIB9, `SRC_NIB8};
+         crc_reg = nextCRC32_D8(rxd_reg, crc_reg);
+         if (gben == 1) begin
+           rxd[7:0] = rxd_reg[7:0];
+         end else begin
+           rxd[3:0] = rxd_reg[3:0];
+            @(posedge rxmac_clk)
+           rxd[3:0] = rxd_reg[7:4];
+         end
+         @(negedge rxmac_clk)
+         rxd_reg = {`SRC_NIB7, `SRC_NIB6};
+         crc_reg = nextCRC32_D8(rxd_reg, crc_reg);
+         if (gben == 1) begin
+           rxd[7:0] = rxd_reg[7:0];
+         end else begin
+           rxd[3:0] = rxd_reg[3:0];
+            @(posedge rxmac_clk)
+           rxd[3:0] = rxd_reg[7:4];
+         end
+         @(negedge rxmac_clk)             
+         rxd_reg = {`SRC_NIB5, `SRC_NIB4};
+         crc_reg = nextCRC32_D8(rxd_reg, crc_reg);
+         if (gben == 1) begin
+           rxd[7:0] = rxd_reg[7:0];
+         end else begin
+           rxd[3:0] = rxd_reg[3:0];
+            @(posedge rxmac_clk)
+           rxd[3:0] = rxd_reg[7:4];
+         end
+         @(negedge rxmac_clk)
+         rxd_reg = {`SRC_NIB3, `SRC_NIB2};
+         crc_reg = nextCRC32_D8(rxd_reg, crc_reg);
+         if (gben == 1) begin
+           rxd[7:0] = rxd_reg[7:0];
+         end else begin
+           rxd[3:0] = rxd_reg[3:0];
+            @(posedge rxmac_clk)
+           rxd[3:0] = rxd_reg[7:4];
+         end
+         @(negedge rxmac_clk)
+         rxd_reg = {`SRC_NIB1, `SRC_NIB0};
+         crc_reg = nextCRC32_D8(rxd_reg, crc_reg);
+         if (gben == 1) begin
+           rxd[7:0] = rxd_reg[7:0];
+         end else begin
+           rxd[3:0] = rxd_reg[3:0];
+            @(posedge rxmac_clk)
+           rxd[3:0] = rxd_reg[7:4];
+         end
+      end // if ( (runt_frmid !== 8'd1) && (runt_frmid !== 8'd2) )
+
+         //VLAN tagged field
+      if(norm_vlan_paus == 2'b01) begin
+         @(negedge rxmac_clk)
+         rxd_reg = 8'b1000_0001;
+         crc_reg = nextCRC32_D8(rxd_reg, crc_reg);
+         if (gben == 1) begin
+           rxd[7:0] = rxd_reg[7:0];
+         end else begin
+           rxd[3:0] = rxd_reg[3:0];
+            @(posedge rxmac_clk)
+           rxd[3:0] = rxd_reg[7:4];
+         end
+         @(negedge rxmac_clk)
+         rxd_reg = 8'b0000_0000;
+         crc_reg = nextCRC32_D8(rxd_reg, crc_reg);
+         if (gben == 1) begin
+           rxd[7:0] = rxd_reg[7:0];
+         end else begin
+           rxd[3:0] = rxd_reg[3:0];
+            @(posedge rxmac_clk)
+           rxd[3:0] = rxd_reg[7:4];
+         end
+         @(negedge rxmac_clk)
+         rxd_reg = {TAG_CTRL_NIB4, TAG_CTRL_NIB3};
+         crc_reg = nextCRC32_D8(rxd_reg, crc_reg);
+         if (gben == 1) begin
+           rxd[7:0] = rxd_reg[7:0];
+         end else begin
+           rxd[3:0] = rxd_reg[3:0];
+            @(posedge rxmac_clk)
+           rxd[3:0] = rxd_reg[7:4];
+         end
+         @(negedge rxmac_clk)
+         rxd_reg = {TAG_CTRL_NIB2, TAG_CTRL_NIB1};
+         crc_reg = nextCRC32_D8(rxd_reg, crc_reg);
+         if (gben == 1) begin
+           rxd[7:0] = rxd_reg[7:0];
+         end else begin
+           rxd[3:0] = rxd_reg[3:0];
+            @(posedge rxmac_clk)
+           rxd[3:0] = rxd_reg[7:4];
+         end
+      end // if (norm_vlan_paus == 2'b01)
+
+         //length/type field generation
+      if((norm_vlan_paus == 2'b10) || (norm_vlan_paus == 2'b11)) begin //pause frame
+         @(negedge rxmac_clk)
+         rxd_reg = {PAUSE_LENTYPE4, PAUSE_LENTYPE3};
+         crc_reg = nextCRC32_D8(rxd_reg, crc_reg);
+         if (gben == 1) begin
+           rxd[7:0] = rxd_reg[7:0];
+         end else begin
+           rxd[3:0] = rxd_reg[3:0];
+            @(posedge rxmac_clk)
+           rxd[3:0] = rxd_reg[7:4];
+         end
+         @(negedge rxmac_clk)
+         rxd_reg = {PAUSE_LENTYPE2, PAUSE_LENTYPE1};
+         crc_reg = nextCRC32_D8(rxd_reg, crc_reg);
+         if (gben == 1) begin
+           rxd[7:0] = rxd_reg[7:0];
+         end else begin
+           rxd[3:0] = rxd_reg[3:0];
+            @(posedge rxmac_clk)
+           rxd[3:0] = rxd_reg[7:4];
+         end
+      end // if (norm_vlan_paus[1] == 1'b1)
+      else begin
+         if( (runt_frmid != 8'd1) && (runt_frmid != 8'd2) && (runt_frmid != 8'd3)
+             && (runt_frmid != 8'd4) ) begin     
+           if(!len_type) begin
+              if(!len_chkerr) begin
+                 @(negedge rxmac_clk)
+                 rxd_reg = {5'b00000,frm_len[10:8]};
+                 crc_reg = nextCRC32_D8(rxd_reg, crc_reg);
+                 if (gben == 1) begin
+                   rxd[7:0] = rxd_reg[7:0];
+                 end else begin
+                   rxd[3:0] = rxd_reg[3:0];
+                    @(posedge rxmac_clk)
+                   rxd[3:0] = rxd_reg[7:4];
+                 end
+                 @(negedge rxmac_clk)
+                 rxd_reg = frm_len[7:0];
+                 crc_reg = nextCRC32_D8(rxd_reg, crc_reg);
+                 if (gben == 1) begin
+                   rxd[7:0] = rxd_reg[7:0];
+                 end else begin
+                   rxd[3:0] = rxd_reg[3:0];
+                    @(posedge rxmac_clk)
+                   rxd[3:0] = rxd_reg[7:4];
+                 end
+              end // if (!len_chkerr)
+              else begin
+                 @(negedge rxmac_clk)
+                 rxd_reg = {5'b00000, frm_len[10:8]};
+                 crc_reg = nextCRC32_D8(rxd_reg, crc_reg);
+                 if (gben == 1) begin
+                   rxd[7:0] = rxd_reg[7:0];
+                 end else begin
+                   rxd[3:0] = rxd_reg[3:0];
+                    @(posedge rxmac_clk)
+                   rxd[3:0] = rxd_reg[7:4];
+                 end
+                 @(negedge rxmac_clk)
+                 rxd_reg = frm_len[7:0] + 8'h01;
+                 crc_reg = nextCRC32_D8(rxd_reg, crc_reg);
+                 if (gben == 1) begin
+                   rxd[7:0] = rxd_reg[7:0];
+                 end else begin
+                   rxd[3:0] = rxd_reg[3:0];
+                    @(posedge rxmac_clk)
+                   rxd[3:0] = rxd_reg[7:4];
+                 end
+              end // else: !if(!len_chkerr)
+           end // if (!len_type)
+           else begin
+              @(negedge rxmac_clk)
+              rxd_reg = {RNDM_FRM_TYPE2, RNDM_FRM_TYPE1};
+              crc_reg = nextCRC32_D8(rxd_reg, crc_reg);
+              if (gben == 1) begin
+                rxd[7:0] = rxd_reg[7:0];
+              end else begin
+                rxd[3:0] = rxd_reg[3:0];
+                 @(posedge rxmac_clk)
+                rxd[3:0] = rxd_reg[7:4];
+              end
+              @(negedge rxmac_clk)
+              rxd_reg = 8'h00;
+              crc_reg = nextCRC32_D8(rxd_reg, crc_reg);
+              if (gben == 1) begin
+                rxd[7:0] = rxd_reg[7:0];
+              end else begin
+                rxd[3:0] = rxd_reg[3:0];
+                 @(posedge rxmac_clk)
+                rxd[3:0] = rxd_reg[7:4];
+              end
+           end // else: !if(!len_type)
+         end // if ( (runt_frmid != 8'd1) && (runt_frmid != 8'd2) && (runt_frmid != 8'd3)...
+      end // else: !if(norm_vlan_paus == 2'b10)
+      
+         //MAC control op-code and parameter, frame data for pause frame
+      if((norm_vlan_paus == 2'b11) || (norm_vlan_paus == 2'b10)) begin //pause frame
+         @(negedge rxmac_clk)
+         if(bad_pcode)
+            rxd_reg = ~{`PAUSE_OP_NIB4, `PAUSE_OP_NIB3};
+         else
+            rxd_reg = {`PAUSE_OP_NIB4, `PAUSE_OP_NIB3};
+         crc_reg = nextCRC32_D8(rxd_reg, crc_reg);
+         if (gben == 1) begin
+           rxd[7:0] = rxd_reg[7:0];
+         end else begin
+           rxd[3:0] = rxd_reg[3:0];
+            @(posedge rxmac_clk)
+           rxd[3:0] = rxd_reg[7:4];
+         end
+         @(negedge rxmac_clk)
+         rxer = (frm_patn === 4'd1); //generating rx_er during pause frame
+         rxd_reg = {`PAUSE_OP_NIB2, `PAUSE_OP_NIB1};
+         crc_reg = nextCRC32_D8(rxd_reg, crc_reg);
+         if (gben == 1) begin
+           rxd[7:0] = rxd_reg[7:0];
+         end else begin
+           rxd[3:0] = rxd_reg[3:0];
+            @(posedge rxmac_clk)
+           rxd[3:0] = rxd_reg[7:4];
+         end
+         @(negedge rxmac_clk)
+         rxer = 1'b0;                //de-assert rx_er
+         rxd_reg = pause_timer[15:8];
+         crc_reg = nextCRC32_D8(rxd_reg, crc_reg);
+         if (gben == 1) begin
+           rxd[7:0] = rxd_reg[7:0];
+         end else begin
+           rxd[3:0] = rxd_reg[3:0];
+            @(posedge rxmac_clk)
+           rxd[3:0] = rxd_reg[7:4];
+         end
+         @(negedge rxmac_clk)
+         rxd_reg = pause_timer[7:0];
+         crc_reg = nextCRC32_D8(rxd_reg, crc_reg);
+         if (gben == 1) begin
+           rxd[7:0] = rxd_reg[7:0];
+         end else begin
+           rxd[3:0] = rxd_reg[3:0];
+            @(posedge rxmac_clk)
+           rxd[3:0] = rxd_reg[7:4];
+         end
+         for (i=0; i<42; i=i+1) begin
+            @(negedge rxmac_clk)
+            rxd_reg = {PAUSE_D_NIB2, PAUSE_D_NIB1};
+            crc_reg = nextCRC32_D8(rxd_reg, crc_reg);
+            if (gben == 1) begin
+              rxd[7:0] = rxd_reg[7:0];
+            end else begin
+              rxd[3:0] = rxd_reg[3:0];
+               @(posedge rxmac_clk)
+              rxd[3:0] = rxd_reg[7:4];
+            end
+         end
+      end // if (norm_vlan_paus[1] == 1'b1)
+      //else if(runt_frmid == 4'd0) begin
+      else if(runt_frmid == 4'd0 || (runt_frmid == 4'd2 && frm_patn == 4'd3) ) begin  // N.G change
+         
+         //frame data generation
+         strt_rxd = $random;
+         rxer = (frm_patn === 4'd1);
+         @(negedge rxmac_clk)    
+         rxd_reg = strt_rxd[7:0];
+         crc_reg = nextCRC32_D8(rxd_reg, crc_reg);
+         if (gben == 1) begin
+           rxd[7:0] = rxd_reg[7:0];
+         end else begin
+           rxd[3:0] = rxd_reg[3:0];
+            @(posedge rxmac_clk)
+           rxd[3:0] = rxd_reg[7:4];
+         end
+         rxer = 1'b0;
+         //for (i=(frm_len-18-1);i>=1;i=i-1) begin
+         if( !norm_vlan_paus[0] && !norm_vlan_paus[1] ) begin
+            //if ( (frm_len < 14'd46) && ((frm_patn != 4'd2) && (frm_patn != 4'd14)) ) begin
+            if ( (frm_len < 14'd46) && ((frm_patn != 4'd2) && (frm_patn != 4'd14) && (frm_patn != 4'd3)) ) begin
+              data_len = 14'd46;
+            end
+            else begin
+               data_len = frm_len;
+            end
+         end
+         else if( norm_vlan_paus[0] && !norm_vlan_paus[1] ) begin
+            if( (frm_len < 14'd42) && (frm_patn != 4'd2) ) begin
+              data_len = 14'd42;
+            end
+            else begin
+               //data_len = frm_len - 4;
+               data_len = frm_len;
+            end
+         end
+         else 
+           data_len = frm_len;
+         //for (i=(frm_len-1);i>=1;i=i-1) begin
+         for (i=(data_len-1);i>=1;i=i-1) begin
+            @(negedge rxmac_clk)
+
+             rxd_reg = rxd_reg+8'd1;
+
+            /*
+           if (i == 0) begin
+               rxd_reg = 8'h24;
+           end else begin
+               rxd_reg = 8'h55;
+            end
+           */
+
+            crc_reg = nextCRC32_D8(rxd_reg, crc_reg);                
+            if (gben == 1) begin
+              rxd[7:0] = rxd_reg[7:0];
+            end else begin
+              rxd[3:0] = rxd_reg[3:0];
+               @(posedge rxmac_clk)
+              rxd[3:0] = rxd_reg[7:4];
+            end
+         end // for (i=frm_len-1;i<1;i=i-1)
+      end // else: !if(norm_vlan_paus[1] == 1'b1)
+        
+      //FCS generation
+      if(runt_frmid === 3'd0) begin        
+         if(!badcrc) begin
+            crc_reg = crc_rev(crc_reg);
+           @(negedge rxmac_clk)
+            rxd_reg = crc_reg[7:0];
+            if (gben == 1) begin
+              rxd[7:0] = rxd_reg[7:0];
+            end else begin
+              rxd[3:0] = rxd_reg[3:0];
+               @(posedge rxmac_clk)
+              rxd[3:0] = rxd_reg[7:4];
+            end
+            @(negedge rxmac_clk)
+            rxd_reg = crc_reg[15:8];
+            if (gben == 1) begin
+              rxd[7:0] = rxd_reg[7:0];
+            end else begin
+              rxd[3:0] = rxd_reg[3:0];
+               @(posedge rxmac_clk)
+              rxd[3:0] = rxd_reg[7:4];
+            end
+            @(negedge rxmac_clk)
+            rxd_reg = crc_reg[23:16];
+            if (gben == 1) begin
+              rxd[7:0] = rxd_reg[7:0];
+            end else begin
+              rxd[3:0] = rxd_reg[3:0];
+               @(posedge rxmac_clk)
+              rxd[3:0] = rxd_reg[7:4];
+            end
+            @(negedge rxmac_clk)
+            rxd_reg = crc_reg[31:24];
+            if (gben == 1) begin
+              rxd[7:0] = rxd_reg[7:0];
+            end else begin
+              rxd[3:0] = rxd_reg[3:0];
+               @(posedge rxmac_clk)
+              rxd[3:0] = rxd_reg[7:4];
+            end
+         end // if (badfcs)
+         else begin
+            @(negedge rxmac_clk)
+            rxd_reg = crc_reg[7:0];
+            if (gben == 1) begin
+              rxd[7:0] = rxd_reg[7:0];
+            end else begin
+              rxd[3:0] = rxd_reg[3:0];
+               @(posedge rxmac_clk)
+              rxd[3:0] = rxd_reg[7:4];
+            end
+            @(negedge rxmac_clk)
+            rxd_reg = crc_reg[15:8];
+            if (gben == 1) begin
+              rxd[7:0] = rxd_reg[7:0];
+            end else begin
+              rxd[3:0] = rxd_reg[3:0];
+               @(posedge rxmac_clk)
+              rxd[3:0] = rxd_reg[7:4];
+            end
+            @(negedge rxmac_clk)
+            rxd_reg = crc_reg[23:16];
+            if (gben == 1) begin
+              rxd[7:0] = rxd_reg[7:0];
+            end else begin
+              rxd[3:0] = rxd_reg[3:0];
+               @(posedge rxmac_clk)
+              rxd[3:0] = rxd_reg[7:4];
+            end
+            @(negedge rxmac_clk)
+            rxd_reg = crc_reg[31:24];
+            if (gben == 1) begin
+              rxd[7:0] = rxd_reg[7:0];
+            end else begin
+              rxd[3:0] = rxd_reg[3:0];
+               @(posedge rxmac_clk)
+              rxd[3:0] = rxd_reg[7:4];
+            end
+         end // else: !if(badfcs)
+      end // if (runt_frmid === 8'd0)
+
+      if (gben == 1) begin
+         @(negedge rxmac_clk)
+         rxdv = 1'b0;
+      end else begin
+        if ((frm_patn == 4'd15) || (frm_patn == 4'd14)) begin
+            @(negedge rxmac_clk)
+              rxd_reg = $random;
+             rxd[3:0] = rxd_reg[3:0];
+              @(posedge rxmac_clk)
+              rxdv = 1'b0;
+         end else begin
+           @(negedge rxmac_clk)
+            rxdv = 1'b0;
+        end
+      end
+   end
+endtask     
+
+function [31:0] nextCRC32_D8;
+
+      input [7:0] Data;
+      input [31:0] CRC;
+      
+      reg [7:0] D;
+      reg [31:0] C;
+      reg [31:0] NewCRC;
+
+  begin
+     D[0] = Data[7];
+     D[1] = Data[6];
+     D[2] = Data[5];
+     D[3] = Data[4];
+     D[4] = Data[3];
+     D[5] = Data[2];
+     D[6] = Data[1];
+     D[7] = Data[0];
+     C = CRC;
+     
+     NewCRC[0] = D[6] ^ D[0] ^ C[24] ^ C[30];
+     NewCRC[1] = D[7] ^ D[6] ^ D[1] ^ D[0] ^ C[24] ^ C[25] ^ C[30] ^ 
+                 C[31];
+     NewCRC[2] = D[7] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^ C[24] ^ C[25] ^ 
+                 C[26] ^ C[30] ^ C[31];
+     NewCRC[3] = D[7] ^ D[3] ^ D[2] ^ D[1] ^ C[25] ^ C[26] ^ C[27] ^ 
+                 C[31];
+     NewCRC[4] = D[6] ^ D[4] ^ D[3] ^ D[2] ^ D[0] ^ C[24] ^ C[26] ^ 
+                 C[27] ^ C[28] ^ C[30];
+     NewCRC[5] = D[7] ^ D[6] ^ D[5] ^ D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[24] ^ 
+                C[25] ^ C[27] ^ C[28] ^ C[29] ^ C[30] ^ C[31];
+     NewCRC[6] = D[7] ^ D[6] ^ D[5] ^ D[4] ^ D[2] ^ D[1] ^ C[25] ^ C[26] ^ 
+                C[28] ^ C[29] ^ C[30] ^ C[31];
+     NewCRC[7] = D[7] ^ D[5] ^ D[3] ^ D[2] ^ D[0] ^ C[24] ^ C[26] ^ 
+                 C[27] ^ C[29] ^ C[31];
+     NewCRC[8] = D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[0] ^ C[24] ^ C[25] ^ 
+                 C[27] ^ C[28];
+     NewCRC[9] = D[5] ^ D[4] ^ D[2] ^ D[1] ^ C[1] ^ C[25] ^ C[26] ^ 
+                 C[28] ^ C[29];
+     NewCRC[10] = D[5] ^ D[3] ^ D[2] ^ D[0] ^ C[2] ^ C[24] ^ C[26] ^ 
+                  C[27] ^ C[29];
+     NewCRC[11] = D[4] ^ D[3] ^ D[1] ^ D[0] ^ C[3] ^ C[24] ^ C[25] ^ 
+                 C[27] ^ C[28];
+     NewCRC[12] = D[6] ^ D[5] ^ D[4] ^ D[2] ^ D[1] ^ D[0] ^ C[4] ^ C[24] ^ 
+                  C[25] ^ C[26] ^ C[28] ^ C[29] ^ C[30];
+     NewCRC[13] = D[7] ^ D[6] ^ D[5] ^ D[3] ^ D[2] ^ D[1] ^ C[5] ^ C[25] ^ 
+                  C[26] ^ C[27] ^ C[29] ^ C[30] ^ C[31];
+     NewCRC[14] = D[7] ^ D[6] ^ D[4] ^ D[3] ^ D[2] ^ C[6] ^ C[26] ^ C[27] ^ 
+                  C[28] ^ C[30] ^ C[31];
+     NewCRC[15] = D[7] ^ D[5] ^ D[4] ^ D[3] ^ C[7] ^ C[27] ^ C[28] ^ 
+                  C[29] ^ C[31];
+     NewCRC[16] = D[5] ^ D[4] ^ D[0] ^ C[8] ^ C[24] ^ C[28] ^ C[29];
+     NewCRC[17] = D[6] ^ D[5] ^ D[1] ^ C[9] ^ C[25] ^ C[29] ^ C[30];
+     NewCRC[18] = D[7] ^ D[6] ^ D[2] ^ C[10] ^ C[26] ^ C[30] ^ C[31];
+     NewCRC[19] = D[7] ^ D[3] ^ C[11] ^ C[27] ^ C[31];
+     NewCRC[20] = D[4] ^ C[12] ^ C[28];
+     NewCRC[21] = D[5] ^ C[13] ^ C[29];
+     NewCRC[22] = D[0] ^ C[14] ^ C[24];
+     NewCRC[23] = D[6] ^ D[1] ^ D[0] ^ C[15] ^ C[24] ^ C[25] ^ C[30];
+     NewCRC[24] = D[7] ^ D[2] ^ D[1] ^ C[16] ^ C[25] ^ C[26] ^ C[31];
+     NewCRC[25] = D[3] ^ D[2] ^ C[17] ^ C[26] ^ C[27];
+     NewCRC[26] = D[6] ^ D[4] ^ D[3] ^ D[0] ^ C[18] ^ C[24] ^ C[27] ^ 
+                  C[28] ^ C[30];
+     NewCRC[27] = D[7] ^ D[5] ^ D[4] ^ D[1] ^ C[19] ^ C[25] ^ C[28] ^ 
+                  C[29] ^ C[31];
+     NewCRC[28] = D[6] ^ D[5] ^ D[2] ^ C[20] ^ C[26] ^ C[29] ^ C[30];
+     NewCRC[29] = D[7] ^ D[6] ^ D[3] ^ C[21] ^ C[27] ^ C[30] ^ C[31];
+     NewCRC[30] = D[7] ^ D[4] ^ C[22] ^ C[28] ^ C[31];
+     NewCRC[31] = D[5] ^ C[23] ^ C[29];
+     
+     nextCRC32_D8 = NewCRC;
+
+  end
+
+endfunction
+
+
+function [31:0] crc_rev;
+      
+      input [31:0] data_in;
+      integer crc_i;
+   begin    
+      for (crc_i = 0; crc_i < 32; crc_i = crc_i+1) begin
+         crc_rev[crc_i] = ~data_in[31 - crc_i]; 
+      end
+   end
+endfunction
+
+      

diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/test_ts_mac.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/test_ts_mac.v
new file mode 100644 (file)
index 0000000..fc85e57
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/test_ts_mac.v
@@ -0,0 +1,328 @@
+// ===========================================================================\r
+// Verilog module generated by IPexpress\r
+// Filename: test_ts_mac.v  \r
+// Copyright 2005 (c) Lattice Semiconductor Corporation. All rights reserved.\r
+// ===========================================================================\r
+\r
+`timescale 1 ns/100 ps\r
+\r
+module  test_ts_mac ;\r
+\r
+`include "env_params.v"\r
+`include "test_tsmac_params.v"\r
+\r
+\r
+reg         reset_n ;\r
+reg         tx_clk_125 ;\r
+reg         rx_clk_125 ;\r
+reg         tx_clk_25 ;\r
+reg         rx_clk_25 ;\r
+reg         clk_125 ;\r
+reg         clk_12_5 ;\r
+reg         sys_clk ;\r
+reg         hclk ;\r
+\r
+wire gtx_clk;\r
+wire tx_en;\r
+wire tx_er;\r
+wire [7:0] txd;\r
+\r
+wire tx_clk;\r
+wire rx_clk;\r
+\r
+`ifdef MIIM_MODULE\r
+   tri mdio;\r
+`endif\r
+\r
+reg [7:0] rxd;\r
+reg rxer;\r
+reg rxdv;\r
+reg col;\r
+reg crs;\r
+\r
+reg tdi;\r
+reg tms;\r
+reg tck;\r
+\r
+wire rxmac_clk_wire;\r
+wire txmac_clk_wire;\r
+wire rxmac_clk;\r
+wire txmac_clk;\r
+\r
+// test points\r
+wire [7:0] tx_fifodata;  \r
+wire tx_fifoavail;   \r
+wire tx_fifoeof;     \r
+wire tx_fifoempty;   \r
+wire tx_sndpausreq;  \r
+wire tx_fifoctrl;    \r
+wire tx_fifo_full_ri;\r
+wire tx_macread;     \r
+wire tx_discfrm;     \r
+wire tx_staten;      \r
+wire tx_done; \r
+wire gbit_en; // gbit_en signal\r
+\r
+`ifdef SGMII_TSMAC\r
+   wire txmac_clk_en;\r
+   wire rxmac_clk_en;\r
+   wire clk_en_1000;\r
+   reg  clk_en_100_tx;\r
+   reg  clk_en_100_rx;\r
+`endif\r
+       \r
+initial begin\r
+   reset_n = 1;\r
+   #50;\r
+   reset_n = 0;\r
+   #100;\r
+   reset_n = 1;\r
+end\r
+\r
+initial begin\r
+   col = 0;\r
+   tx_clk_125 = 0;\r
+   rx_clk_125 = 0;\r
+   tx_clk_25 = 0;\r
+   rx_clk_25 = 0;\r
+   clk_125 = 0;\r
+   clk_12_5 = 0;\r
+   hclk = 0;\r
+   sys_clk = 0;\r
+   rxd = 8'h00;\r
+   rxdv = 0;\r
+   rxer = 0;\r
+   crs = 0;\r
+   `ifdef SGMII_TSMAC\r
+         clk_en_100_tx = 0;\r
+         clk_en_100_rx = 0;\r
+   `endif\r
+   tdi = 0;\r
+   tms = 0;\r
+   tck = 0;\r
+   \r
+   `ifdef GBE_MAC\r
+   `else\r
+`ifdef GATE_SIM_VHD\r
+   force U1_ts_mac_top.gbit_en_c = 1;\r
+   #40;\r
+   release U1_ts_mac_top.gbit_en_c;\r
+`else\r
+   force U1_ts_mac_top.gbit_en_wire = 1;\r
+   #40;\r
+   release U1_ts_mac_top.gbit_en_wire;\r
+`endif\r
+   `endif\r
+   \r
+   //force U1_ts_mac_top.U1_ts_mac_core.U1_tx_mac.U1_tx_readfifo.tx_fifodata = 0;\r
+   //#300;\r
+   //release U1_ts_mac_top.U1_ts_mac_core.U1_tx_mac.U1_tx_readfifo.tx_fifodata;\r
+   \r
+   //#85000\r
+   //#103000\r
+   //force U1_ts_mac_top.u1_tst_logic.tx_fifo_empty_ri = 1;\r
+   //#1000;\r
+   //release U1_ts_mac_top.u1_tst_logic.tx_fifo_empty_ri;\r
+end\r
+\r
+GSR GSR_INST   (.GSR(reset_n)) /* synthesis syn_noprune = 1 */ ;\r
+PUR PUR_INST   (.PUR(1'b1)) /* synthesis syn_noprune = 1 */ ;\r
+//TSALL TSALL_INST (1'b1) /* synthesis syn_noprune = 1 */ ;\r
+\r
+`ifdef CLASSIC_TSMAC\r
+    assign tx_clk = (gbit_en) ? tx_clk_125:tx_clk_25;\r
+    assign rx_clk = (gbit_en) ? rx_clk_125:rx_clk_25;\r
+`else // SGMII_TSMAC OR GBE_MAC\r
+    assign tx_clk = tx_clk_125;\r
+    assign rx_clk = rx_clk_125;\r
+`endif\r
+\r
+// rxmac_clk goes to rx_gen_task to drive pkts\r
+`ifdef SGMII_TSMAC\r
+    assign rxmac_clk = (gbit_en) ? clk_125:clk_12_5; //\r
+`else // CLASSIC_TSMAC OR GBE_MAC\r
+    assign rxmac_clk = rxmac_clk_wire;\r
+`endif\r
+\r
+\r
+       ts_mac_top U1_ts_mac_top (\r
+\r
+               // clock and reset\r
+\r
+               .gtx_clk (gtx_clk),\r
+               .tx_clk (tx_clk),\r
+\r
+                `ifdef SGMII_TSMAC\r
+                  .txmac_clk_en (txmac_clk_en),\r
+                  .rxmac_clk_en (rxmac_clk_en),\r
+                `endif\r
+               \r
+                `ifdef MIIM_MODULE\r
+                  .mdc (mdc),\r
+                `endif\r
+\r
+               .sys_clk (sys_clk),\r
+               .hclk (hclk),\r
+               .rx_clk (rx_clk),\r
+               .rxmac_clk (rxmac_clk_wire),\r
+               .txmac_clk (txmac_clk_wire),\r
+               .reset_n (reset_n),\r
+               \r
+               // Input signals to the GMII\r
+               .rx_dv (rxdv),\r
+               .rx_er (rxer),\r
+               .rxd (rxd),\r
+               \r
+                `ifndef GBE_MAC\r
+                 .col (col),\r
+                 .crs (crs),\r
+                `endif\r
+               \r
+                // orcastra interface\r
+               .pc_clk (pc_clk),\r
+               .pc_datain (pc_datain),\r
+               .pc_dataout (pc_dataout),\r
+               .pc_retry (pc_retry),\r
+               .pc_error (pc_error),\r
+               .pc_ready (pc_ready),\r
+               .pc_ack (pc_ack),\r
+               .jtag_present (),\r
+               .jtag_parallel (1'b0),\r
+\r
+               // JTAG Signals \r
+               .tdi (tdi),\r
+               .tms (tms),\r
+               .tck (tck),\r
+               .tdo (),\r
+\r
+               // Input/Output signal from the MII Management Interface\r
+                `ifdef MIIM_MODULE\r
+                  .mdio (mdio),\r
+                `endif\r
+\r
+               // Output signals from the GMII\r
+               .tx_en (tx_en),\r
+               .tx_er (tx_er),\r
+               .txd (txd),\r
+               \r
+               // These are test points on the evaluation board\r
+               .tx_fifodata (tx_fifodata),\r
+               .tx_fifoavail (tx_fifoavail),\r
+               .tx_fifoeof (tx_fifoeof),\r
+               .tx_fifoempty (tx_fifoempty),\r
+               .tx_sndpausreq (tx_sndpausreq),\r
+               .tx_fifoctrl (tx_fifoctrl),\r
+               .tx_fifo_full_ri (tx_fifo_full_ri),\r
+               .tx_macread (tx_macread),\r
+               .tx_discfrm (tx_discfrm),\r
+               .tx_staten (tx_staten),\r
+               .tx_done (tx_done),\r
+               .gbit_en (gbit_en),\r
+                .phy_reset_n(phy_reset_n)\r
+               );\r
+\r
+\r
+\r
+       orcastra_drv orcastra_drv(\r
+               .pc_clk (pc_clk),\r
+               .pc_datain (pc_datain),\r
+               .pc_dataout (pc_dataout),\r
+               .pc_retry (pc_retry),\r
+               .pc_error (pc_error),\r
+               .pc_ready (pc_ready),\r
+               .pc_ack (pc_ack)\r
+               );\r
+\r
+               \r
+       pkt_mon pkt_mon(\r
+               .reset_n (reset_n),\r
+               \r
+               `ifdef SGMII_TSMAC\r
+                 .gbit_en (1'b1),\r
+                 .tx_clk_en (txmac_clk_en),\r
+               `else\r
+                 .gbit_en (gbit_en),\r
+               `endif\r
+               \r
+               .tx_clk (tx_clk),\r
+               .tx_en (tx_en),\r
+               .tx_er (tx_er),\r
+               .txd (txd)\r
+               );\r
+\r
+               \r
+       //jtag_drv jtag_drv (\r
+       //   .PTDO ( tdo ), \r
+       //   .PTCK ( tck ), \r
+       //   .PTDI ( tdi ), \r
+       //   .PTMS ( tms )\r
+       //   );\r
+\r
+`define SRC_NIB11 4'hd\r
+`define SRC_NIB10 4'he\r
+`define SRC_NIB9 4'ha\r
+`define SRC_NIB8 4'hd\r
+`define SRC_NIB7 4'hd\r
+`define SRC_NIB6 4'he\r
+`define SRC_NIB5 4'ha\r
+`define SRC_NIB4 4'hd\r
+`define SRC_NIB3 4'hb\r
+`define SRC_NIB2 4'he\r
+`define SRC_NIB1 4'he\r
+`define SRC_NIB0 4'hf\r
+// =============================================================================\r
+`include "rx_gen_tasks.v"\r
+`include "testcase.v"\r
+`include "rdwr_task.v"\r
+// =============================================================================\r
+\r
+\r
+// Clocks generation\r
+// 125 Mhz clock\r
+always #4 clk_125 = ~clk_125 ;\r
+always #4 tx_clk_125 = ~tx_clk_125 ;\r
+always #4 rx_clk_125 = ~rx_clk_125 ;\r
+always #20 tx_clk_25 = ~tx_clk_25 ;\r
+always #20 rx_clk_25 = ~rx_clk_25 ;\r
+always #40 clk_12_5 = ~clk_12_5 ;\r
+// 125 Mhz clock\r
+always #4 sys_clk = ~sys_clk ;\r
+// 50 Mhz clock\r
+always #10 hclk = ~hclk;\r
+\r
+// Clock enable generation\r
+`ifdef SGMII_TSMAC\r
+\r
+        assign clk_en_1000 = 1'b1;\r
+       \r
+       always @(posedge clk_125) begin\r
+               #72 clk_en_100_tx = 1'b1;\r
+               #8  clk_en_100_tx = 1'b0;\r
+       end     \r
+        \r
+       always @(posedge clk_125) begin\r
+               #72 clk_en_100_rx = 1'b1;\r
+               #8  clk_en_100_rx = 1'b0;\r
+       end\r
+       \r
+       assign txmac_clk_en = (gbit_en) ? clk_en_1000:clk_en_100_tx;\r
+        assign rxmac_clk_en = (gbit_en) ? clk_en_1000:clk_en_100_rx;\r
+               \r
+`endif\r
+\r
+initial begin\r
+     $timeformat (-9 ,1 , "ns", 10);\r
+end\r
+\r
+// Timeout generation to finish hung test cases.\r
+initial begin\r
+   repeat (10000000) @(posedge clk_125 );\r
+   $display(" INFO : Simulation Time Out, Test case Terminated") ;\r
+   $finish ;\r
+end\r
+\r
+endmodule\r
+// =============================================================================\r
+\r
+\r
+\r

diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/test_tsmac_params.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/test_tsmac_params.v
new file mode 100644 (file)
index 0000000..7e61bcb
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/testbench/top/test_tsmac_params.v
@@ -0,0 +1,118 @@
+// ===========================================================================\r
+// Verilog module generated by IPexpress\r
+// Filename: test_tsmac_params.v  \r
+// Copyright 2005 (c) Lattice Semiconductor Corporation. All rights reserved.\r
+// ===========================================================================\r
+\r
+parameter GETH_GMII_DATA       = 8;   // GMII data width in 1000 Mbps mode\r
+parameter FETH_GMII_DATA       = 4;   // MII data width in 10/100 Mbps mode\r
+parameter HADDR_BUS_WIDTH      = 8;   // CPU I/F address bus width\r
+parameter FIFO_DATA_WIDTH      = 16;  // FIFO I/F data bus width\r
+parameter FIFO_DATA_BYTEN      = 2;   // Byte enable signals for FIFO data\r
+parameter PAUSE_TIME_WIDTH     = 16;  // Pause frame parameter width\r
+parameter TX_STAT_VEC_WIDTH    = 31;  // Transmit Status Vector Width\r
+parameter VLAN_TAG_WIDTH       = 16;  // VLAN Tag Information\r
+parameter TX_BYTEN_WIDTH       = 2;   // Byte enable from Tx MAC to GMII module\r
+parameter TX_IPG_RNG           = 16;  // IPG register\r
+parameter TX_DATA_WIDTH        = 16;  // Tx MAC data path\r
+\r
+///////////////////////////////////////////////////////////////////////\r
+// The following are the text maxros used by the task transmit \r
+// frame generator.\r
+\r
+`ifdef FETH_MODE\r
+ `define DATA_SIZE 4\r
+`else\r
+ `define DATA_SIZE 8\r
+`endif\r
+\r
+\r
+`define TAG_DFL 4'h0\r
+`define TAG_DTY 4'h1\r
+`define TAG_VFL 4'h2\r
+`define TAG_VTY 4'h3\r
+`define TAG_PCO 4'h4\r
+`define TAG_PIO 4'h5\r
+`define TAG_DATA 4'h6\r
+`define TAG_DAPA 4'h7\r
+`define TAG_PAD 4'h8\r
+`define TAG_CRC 4'h9\r
+`define TAG_DACR 4'ha\r
+`define TAG_DA 4'hb\r
+`define TAG_SA 4'hc\r
+`define TAG_PRE 4'hd\r
+`define TAG_PRS 4'he\r
+\r
+`define NEOF 1'b0\r
+`define EOF  1'b1\r
+\r
+`define  PRE_FIRST_WORD  16'b 10101010_10101010\r
+`define  PRE_SECOND_WORD  16'b 10101010_10101010\r
+`define  PRE_THIRD_WORD  16'b 10101010_10101010\r
+`define  PRE_AND_SFD  16'b 10101010_10101011\r
+\r
+\r
+`define TB_CTRL_FRAME 1'b1\r
+`define TB_DATA_FRAME 1'b0\r
+\r
+///////////////////////////////////////////////////////////////////////\r
+// The following are the text maxros used by the task receive \r
+// frame generator.\r
+//      parameter PAUSE_OP_NIB1 = 4'h0;\r
+//      parameter PAUSE_OP_NIB2 = 4'h0;\r
+//      parameter PAUSE_OP_NIB3 = 4'h8;\r
+//      parameter PAUSE_OP_NIB4 = 4'h0;\r
+//`define PAUSE_OP_NIB1  4'h0\r
+//`define PAUSE_OP_NIB2  4'h0\r
+//`define PAUSE_OP_NIB3  4'h8\r
+//`define PAUSE_OP_NIB4  4'h0\r
+\r
+`define RX_GB_EN 1'b1\r
+`define RX_FE_EN 1'b0\r
+`define RX_BAD_CRC 1'b1\r
+`define RX_GOOD_CRC 1'b0\r
+`define RX_NORM_FRM 2'b00\r
+`define RX_VLAN_FRM 2'b01\r
+`define RX_PAUS_FRM 2'b10\r
+`define RX_PAUS_FRM_CUS 2'b11\r
+`define RX_BAD_OPCODE 1'b1\r
+`define RX_GOOD_OPCODE 1'b0\r
+`define RX_LEN_FIELD 1'b0\r
+`define RX_TYP_FIELD 1'b1\r
+`define RX_LENCHK_ER 1'b1\r
+`define RX_LENCHK_NOER 1'b0\r
+`define RX_BAD_SFD 1'b1\r
+`define RX_GOOD_SFD 1'b0\r
+`define RX_RUNT_NOT 3'd0\r
+`define RX_RUNT_PREM 3'd1\r
+`define RX_RUNT_SFD 3'd2\r
+`define RX_RUNT_DES 3'd3\r
+`define RX_RUNT_SRC 3'd4\r
+`define RX_FRMPTN_NOER 4'd0\r
+`define RX_FRMPTN_ER 4'd1\r
+`define RX_FRMPTN_NOPAD 4'd2\r
+`define RX_FRMPTN_DRNOPAD 4'd14\r
+`define RX_FRMPTN_DRIB 4'd15\r
+\r
+`ifdef FETH_MODE\r
+    `define MIN_IPG 5'd16 \r
+    `define STD_IPG 5'd24\r
+    `define ETH_10_100\r
+`endif\r
+`ifdef GETH_MODE\r
+    `define MIN_IPG 5'd8\r
+    `define STD_IPG 5'd12\r
+    `define ETH_GBIT\r
+`endif\r
+`ifdef TSETH_MODE\r
+    `ifdef SET_GIGABIT\r
+        `define MIN_IPG 5'd8\r
+        `define STD_IPG 5'd12\r
+        `define ETH_GBIT\r
+    `else\r
+        `define MIN_IPG 5'd16\r
+        `define STD_IPG 5'd24\r
+        `define ETH_10_100\r
+    `endif\r
+`endif\r
+\r

diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/ts_mac_defines.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/ts_mac_defines.v
new file mode 100644 (file)
index 0000000..d5ac36a
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/ts_mac_defines.v
@@ -0,0 +1,2 @@
+`define SGMII_TSMAC
+`define DEVICE_ECP5UM

diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/tsmac_core_only_eval.ldf b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/tsmac_core_only_eval.ldf
new file mode 100644 (file)
index 0000000..a364ce2
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/tsmac_core_only_eval.ldf
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<BaliProject version="3.2" title="tsmac_core_only_eval" device="LFE5UM-85F-8BG756C" synthesis="synplify" default_implementation="impl">
+    <Implementation title="impl" dir="impl" description="impl" default_strategy="tsmac_core_only_eval_setting">
+        <Options>
+            <Option name="HDL type" value="VHDL"></Option>
+            <Option name="def_top" value="ts_mac_core_only_top"></Option>
+        </Options>
+        <Source name="../../src/rtl/top/ts_mac_core_only_top.vhd" type="VHDL"></Source>
+        <Source name="tsmac_core_only_eval.lpf" type="Logic Preference"></Source>
+    </Implementation>
+    <Strategy name="tsmac_core_only_eval_setting" file="tsmac_core_only_eval_setting.sty"></Strategy>
+</BaliProject>

diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/tsmac_core_only_eval.lpf b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/tsmac_core_only_eval.lpf
new file mode 100644 (file)
index 0000000..0a818b6
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/tsmac_core_only_eval.lpf
@@ -0,0 +1,29 @@
+COMMERCIAL ;
+
+# Period Constraints
+FREQUENCY NET "hclk_c" 100.0 MHz;
+FREQUENCY NET "rxmac_clk_c" 125.0 MHz PAR_ADJ 20;
+FREQUENCY NET "txmac_clk_c" 125.0 MHz PAR_ADJ 20;
+
+BLOCK ASYNCPATHS ;
+BLOCK INTERCLOCKDOMAIN PATHS;
+
+#Begin multicycle path from constraints
+MULTICYCLE TO CELL "U1_ts_mac_core_only_core/U1_LSC_ts_mac_core/U1_gmii/sync_rxd_m*" 2X;
+#MULTICYCLE TO CELL "U1_ts_mac_core_only_core/U1_LSC_ts_mac_core/U1_gmii/sync_rxer_m*" 2X;
+#MULTICYCLE TO CELL "U1_ts_mac_core_only_core/U1_LSC_ts_mac_core/U1_gmii/sync_rxdv_m*" 2X;
+#MULTICYCLE TO CELL "U1_ts_mac_core_only_core/U1_LSC_ts_mac_core/U1_gmii/sync_nibdrib_m*" 2X;
+MULTICYCLE TO CELL "U1_ts_mac_core_only_core/U1_LSC_ts_mac_core/U1_gmii/ipg_shrink_m*" 2X;
+MULTICYCLE TO CELL "U1_ts_mac_core_only_core/U1_LSC_ts_mac_core/U1_gmii/nib_alig*" 2X;
+#MULTICYCLE TO CELL "U1_ts_mac_core_only_core/U1_LSC_ts_mac_core/U1_gmii/enable_sfd_alig*" 2X;
+MULTICYCLE TO CELL "U1_ts_mac_core_only_core/U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/rd_ptr*" 2X;
+MULTICYCLE FROM CELL "U1_ts_mac_core_only_core/U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/rd_ptr*" 2X;
+MULTICYCLE TO CELL "U1_ts_mac_core_only_core/U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/wr_ptr*" 2X;
+MULTICYCLE FROM CELL "U1_ts_mac_core_only_core/U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/wr_ptr*" 2X;
+#End multicycle path from constraints
+
+#Begin false path from constraints
+BLOCK PATH FROM CELL "U1_ts_mac_core_only_core/U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "U1_ts_mac_core_only_core/U1_LSC_ts_mac_core/U1_tx_mac*" ; 
+BLOCK PATH FROM CELL "U1_ts_mac_core_only_core/U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "U1_ts_mac_core_only_core/U1_LSC_ts_mac_core/U1_rx_mac*" ; 
+#End false path from constraints
+

diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/tsmac_core_only_eval_setting.sty b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/tsmac_core_only_eval_setting.sty
new file mode 100644 (file)
index 0000000..e35e905
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/tsmac_core_only_eval_setting.sty
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE strategy>
+<Strategy version="1.0" predefined="0" description="" label="tsmac_core_only_eval_setting">
+    <Property name="PROP_BD_EdfInBusNameConv" value="Synplify" time="0"></Property>
+    <Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup Analysis" time="0"/>
+    <Property name="PROP_PARSTA_SpeedForHoldAnalysis" value="8" time="0"/>
+    <Property name="PROP_PARSTA_SpeedForSetupAnalysis" value="8" time="0"/>
+    <Property name="PROP_BD_EdfInLibPath" value="../../../../" time="0"/>
+    <Property name="PROP_LST_EdfInLibPath" value="../../../../" time="0"/>
+</Strategy>

diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/tsmac_reference_eval.ldf b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/tsmac_reference_eval.ldf
new file mode 100644 (file)
index 0000000..dedb25d
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/tsmac_reference_eval.ldf
@@ -0,0 +1,25 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<BaliProject version="3.2" title="tsmac_reference_eval" device="LFE5UM-85F-8BG756C" synthesis="synplify" default_implementation="impl">
+    <Implementation title="impl" dir="impl" description="impl" default_strategy="tsmac_reference_eval_setting">
+        <Options>
+            <Option name="HDL type" value="VHDL"></Option>
+            <Option name="def_top" value="ts_mac_top"></Option>
+            <Option name="top" value="ts_mac_top"></Option>
+        </Options>
+        <Source name="../../../models/ecp5um/JTAG_ECP5UM.v" type="Verilog"></Source>
+        <Source name="/home/soft/lattice/diamond/3.10_x64/cae_library/simulation/verilog/pmi/pmi_ram_dp.v" type="Verilog"></Source>
+        <Source name="../../src/rtl/template/tst_logic.v" type="Verilog"></Source>
+        <Source name="../../src/rtl/template/reg_intf.v" type="Verilog"></Source>
+        <Source name="../../src/rtl/template/orcastra.v" type="Verilog"></Source>
+        <Source name="../../src/rtl/template/fifo_512_ctl.v" type="Verilog"></Source>
+        <Source name="../../src/rtl/template/fifo_2048x9.v" type="Verilog"></Source>
+        <Source name="../../src/rtl/template/rx_loopbk.v" type="Verilog"></Source>
+        <Source name="../../src/rtl/template/oddrx_soft.v" type="Verilog"></Source>
+        <Source name="../../../models/ecp5um/rxmac_clk_pll.v" type="Verilog"></Source>
+        <Source name="../../../models/ecp5um/txmac_clk_pll.v" type="Verilog"></Source>
+        <Source name="../../src/rtl/top/ts_mac_core_only_top.vhd" type="VHDL"></Source>
+        <Source name="../../src/rtl/top/ts_mac_top.v" type="Verilog"></Source>
+        <Source name="tsmac_reference_eval.lpf" type="Logic Preference"></Source>
+    </Implementation>
+    <Strategy name="tsmac_reference_eval_setting" file="tsmac_reference_eval_setting.sty"></Strategy>
+</BaliProject>

diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/tsmac_reference_eval.lpf b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/tsmac_reference_eval.lpf
new file mode 100644 (file)
index 0000000..bfe1274
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/tsmac_reference_eval.lpf
@@ -0,0 +1,71 @@
+COMMERCIAL ;
+# Period Constraints
+FREQUENCY NET  "hclk_c"        100.00 MHz PAR_ADJ 20;
+FREQUENCY NET  "txmac_clk_c" 125.00 MHz PAR_ADJ 20;
+FREQUENCY NET  "rxmac_clk_c" 125.00 MHz PAR_ADJ 20;
+FREQUENCY NET  "pc_clk_mux"   50.00 MHz ;
+USE PRIMARY PURE NET "txmac_clk_c";
+
+BLOCK ASYNCPATHS ;
+BLOCK INTERCLOCKDOMAIN PATHS ;
+
+#Begin multicycle path from constraints
+MULTICYCLE   TO CELL "U1_ts_mac_core*U1_LSC_ts_mac_core/U1_gmii/sync_rxd_m*"           2.000000 X ;
+#MULTICYCLE   TO CELL "U1_ts_mac_core*U1_LSC_ts_mac_core/U1_gmii/sync_rxer_m*"          2.000000 X ;
+#MULTICYCLE   TO CELL "U1_ts_mac_core*U1_LSC_ts_mac_core/U1_gmii/sync_rxdv_m*"          2.000000 X ;
+#MULTICYCLE   TO CELL "U1_ts_mac_core*U1_LSC_ts_mac_core/U1_gmii/sync_nibdrib_m*"       2.000000 X ;
+MULTICYCLE   TO CELL "U1_ts_mac_core*U1_LSC_ts_mac_core/U1_gmii/ipg_shrink_m*"         2.000000 X ;
+MULTICYCLE   TO CELL "U1_ts_mac_core*U1_LSC_ts_mac_core/U1_gmii/nib_alig*"             2.000000 X ;
+#MULTICYCLE   TO CELL "U1_ts_mac_core*U1_LSC_ts_mac_core/U1_gmii/enable_sfd_alig*"      2.000000 X ;
+MULTICYCLE   TO CELL "U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/rd_ptr*" 2.000000 X ;
+MULTICYCLE FROM CELL "U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/rd_ptr*" 2.000000 X ;
+MULTICYCLE   TO CELL "U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/wr_ptr*" 2.000000 X ;
+MULTICYCLE FROM CELL "U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/wr_ptr*" 2.000000 X ;
+#End multicycle path from constraints
+
+#Begin false path from constraints
+BLOCK PATH FROM CELL "U1_ts_mac_core*U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac*" ;
+BLOCK PATH FROM CELL "U1_ts_mac_core*U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "U1_ts_mac_core*U1_LSC_ts_mac_core/U1_rx_mac*" ;
+#BLOCK NET "pkt_loop_clksel_ri" ;
+BLOCK NET "gbit_en_wire" ;
+#End false path from constraints
+
+# GMII input signals
+# Input setup and hold
+# set these values according to your specific design requirements
+#DEFINE PORT GROUP "TSU_GRP" "rx_dv" 
+#                            "rx_er" 
+#                            "rxd*";
+#INPUT_SETUP GROUP "TSU_GRP" 3.500000 ns HOLD 0.000000 ns CLKPORT "rx_clk" ;
+# GMII output signals
+# Output Clock to Out
+# set these values according to your specific design requirements
+#DEFINE PORT GROUP "TCO_GRP" "tx_en" 
+#                            "rx_er" 
+#                            "txd*";
+#CLOCK_TO_OUT GROUP "TCO_GRP" MAX 5.000000 ns MIN 1.000000 ns CLKNET "txmac_clk_c" CLKOUT PORT "gtx_clk" ;
+
+# If I/O timing for these pins is a problem add these
+#PRIORITIZE NET "rxd_c_0" 100;
+#PRIORITIZE NET "rxd_c_1" 100;
+#PRIORITIZE NET "rxd_c_2" 100;
+#PRIORITIZE NET "rxd_c_3" 100;
+#PRIORITIZE NET "rxd_c_4" 100;
+#PRIORITIZE NET "rxd_c_5" 100;
+#PRIORITIZE NET "rxd_c_6" 100;
+#PRIORITIZE NET "rxd_c_7" 100;
+#PRIORITIZE NET "rx_dv_c" 100;
+#PRIORITIZE NET "rx_er_c" 100;
+#PRIORITIZE NET "rx_clk_c" 80;
+#PRIORITIZE NET "tx_clk_c" 40;
+
+#MAXDELAY NET "rxd_c_0" 1.5 ns;
+#MAXDELAY NET "rxd_c_1" 1.5 ns;
+#MAXDELAY NET "rxd_c_2" 1.5 ns;
+#MAXDELAY NET "rxd_c_3" 1.5 ns;
+#MAXDELAY NET "rxd_c_4" 1.5 ns;
+#MAXDELAY NET "rxd_c_5" 1.5 ns;
+#MAXDELAY NET "rxd_c_6" 1.5 ns;
+#MAXDELAY NET "rxd_c_7" 1.5 ns;
+#MAXDELAY NET "rx_dv_c" 1.5 ns;
+#MAXDELAY NET "rx_er_c" 1.5 ns;

diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/tsmac_reference_eval_setting.sty b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/tsmac_reference_eval_setting.sty
new file mode 100644 (file)
index 0000000..aaaa01e
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/impl/synplify/tsmac_reference_eval_setting.sty
@@ -0,0 +1,8 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE strategy>
+<Strategy version="1.0" predefined="0" description="" label="tsmac_reference_eval_setting">
+    <Property name="PROP_BD_EdfInBusNameConv" value="Synplify" time="0"></Property>
+    <Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup Analysis" time="0"/>
+    <Property name="PROP_BD_EdfInLibPath" value="../../../../" time="0"/>
+    <Property name="PROP_LST_EdfInLibPath" value="../../../../" time="0"/>
+</Strategy>

diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/sim/modelsim/tsmac_eval_se.do b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/sim/modelsim/tsmac_eval_se.do
new file mode 100644 (file)
index 0000000..9f74d40
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/sim/modelsim/tsmac_eval_se.do
@@ -0,0 +1,27 @@
+if {!0} {
+    vlib work 
+}
+vmap work work
+#==== compile
+vlog -novopt -incr \
++incdir+../../src/params \
++incdir+../../../testbench/top \
++incdir+../../../testbench/tests \
+-y /home/soft/lattice/diamond/3.10_x64/cae_library/simulation/verilog/pmi +libext+.v \
+-y /home/soft/lattice/diamond/3.10_x64/cae_library/simulation/verilog/ecp5u +libext+.v \
+-y ../../src/rtl/template +libext+.v \
+-y ../../../models/ecp5um +libext+.v \
+../../src/params/ts_mac_defines.v \
+../../../../tsmac_beh.v \
+../../src/rtl/top/ts_mac_top.v \
+../../../testbench/top/pkt_mon.v \
+../../../testbench/top/orcastra_drv.v \
+../../../testbench/top/test_ts_mac.v
+
+vcom ../../src/rtl/top/ts_mac_core_only_top.vhd
+#==== run the simulation
+vsim -novopt -L work work.test_ts_mac -l tsmac_eval.log 
+
+view structure wave
+do wave.do
+run -all

diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/sim/modelsim/tsmac_eval_timing_synp_se.do b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/sim/modelsim/tsmac_eval_timing_synp_se.do
new file mode 100644 (file)
index 0000000..4ac6dc5
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/sim/modelsim/tsmac_eval_timing_synp_se.do
@@ -0,0 +1,29 @@
+if {!0} {
+    vlib work 
+}
+vmap work work
+
+#==== compile
+vlog -novopt -incr +define+GATE_SIM_VHD \
++incdir+../../src/params \
++incdir+../../../testbench/top \
++incdir+../../../testbench/tests \
+-y /home/soft/lattice/diamond/3.10_x64/cae_library/simulation/verilog/pmi +libext+.v \
+-y /home/soft/lattice/diamond/3.10_x64/cae_library/simulation/verilog/ecp5u +libext+.v \
+-y ../../../models/ecp5um +libext+.v \
+../../impl/synplify/impl/tsmac_reference_eval_impl_vo.vo \
+../../src/params/ts_mac_defines.v \
+../../../testbench/top/pkt_mon.v \
+../../../testbench/top/orcastra_drv.v \
+../../../testbench/top/test_ts_mac.v
+
+#==== run the simulation
+vsim -novopt -L work \
+      +nowarnTFMPC +nowarnPCDPC +notimingchecks \
+      -multisource_delay max +transport_int_delays +transport_path_delays -v2k_int_delays \
+      work.test_ts_mac \
+      -l tsmac_eval.log 
+
+view structure wave
+do wave_sdf.do
+run -all

diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/sim/modelsim/wave.do b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/sim/modelsim/wave.do
new file mode 100644 (file)
index 0000000..4d17855
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/sim/modelsim/wave.do
@@ -0,0 +1,79 @@
+add wave -noupdate -divider {CORE IO Signals}\r
+add wave -noupdate -divider {Tx MAC Application Interface}\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/txmac_clk\r
+add wave -noupdate -format Literal -radix hexadecimal /test_ts_mac/U1_ts_mac_top/tx_fifodata\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/tx_fifoeof\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/tx_fifoavail\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/tx_fifoempty\r
+add wave -noupdate -format Literal -radix hexadecimal /test_ts_mac/U1_ts_mac_top/tx_sndpaustim\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/tx_sndpausreq\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/tx_fifoctrl\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/tx_macread\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/tx_discfrm\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/tx_done\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/tx_staten\r
+add wave -noupdate -format Literal -radix hexadecimal /test_ts_mac/U1_ts_mac_top/tx_statvec\r
+add wave -noupdate -divider {Rx MAC Aplication Interface}\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/rxmac_clk\r
+add wave -noupdate -format Literal -radix hexadecimal /test_ts_mac/U1_ts_mac_top/rx_dbout\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/rx_eof\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/rx_error\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/rx_fifo_error\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/rx_write\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/rx_stat_en\r
+add wave -noupdate -format Literal -radix hexadecimal /test_ts_mac/U1_ts_mac_top/rx_stat_vector\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/rx_fifo_full\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/ignore_pkt\r
+add wave -noupdate -divider {CPU Interface Signals}\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/hclk\r
+add wave -noupdate -format Literal -radix hexadecimal /test_ts_mac/U1_ts_mac_top/haddr\r
+add wave -noupdate -format Literal -radix hexadecimal /test_ts_mac/U1_ts_mac_top/hdatain\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/hcs_n\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/hwrite_n\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/hread_n\r
+add wave -noupdate -format Literal -radix hexadecimal /test_ts_mac/U1_ts_mac_top/hdataout\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/hdataout_en_n\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/hready_n\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/gbit_en\r
+add wave -noupdate -divider {GMII Signals}\r
+add wave -noupdate -format Literal -radix hexadecimal /test_ts_mac/U1_ts_mac_top/txd\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/tx_en\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/tx_er\r
+add wave -noupdate -format Literal -radix hexadecimal /test_ts_mac/U1_ts_mac_top/rxd\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/rx_dv\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/rx_er\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/col\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/U1_ts_mac_top/crs\r
+add wave -noupdate -divider {FPGA IO Signals}\r
+add wave -noupdate -divider {Clocks and Resets}\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/clk_125\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/sys_clk\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/rxmac_clk_wire\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/txmac_clk_wire\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/txmac_clk_en\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/rxmac_clk_en\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/hclk\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/reset_n\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/phy_reset_n\r
+add wave -noupdate -divider {GMII Signals}\r
+add wave -noupdate -divider {Transmit}\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/tx_clk\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/gtx_clk\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/tx_en\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/tx_er\r
+add wave -noupdate -format Literal -radix hexadecimal /test_ts_mac/txd\r
+add wave -noupdate -divider {Receive}\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/rx_clk\r
+add wave -noupdate -format Literal -radix hexadecimal /test_ts_mac/rxd\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/rxer\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/rxdv\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/col\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/crs\r
+add wave -noupdate -divider {Register Read Write Interface}\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/pc_clk\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/pc_datain\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/pc_dataout\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/pc_retry\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/pc_error\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/pc_ready\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/pc_ack\r

diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/sim/modelsim/wave_sdf.do b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/sim/modelsim/wave_sdf.do
new file mode 100644 (file)
index 0000000..999382b
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/sim/modelsim/wave_sdf.do
@@ -0,0 +1,32 @@
+add wave -noupdate -divider {Clocks and Resets}\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/clk_125\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/sys_clk\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/rxmac_clk_wire\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/txmac_clk_wire\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/txmac_clk_en\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/rxmac_clk_en\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/hclk\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/reset_n\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/phy_reset_n\r
+add wave -noupdate -divider {GMII Signals}\r
+add wave -noupdate -divider {Transmit}\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/tx_clk\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/gtx_clk\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/tx_en\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/tx_er\r
+add wave -noupdate -format Literal -radix hexadecimal /test_ts_mac/txd\r
+add wave -noupdate -divider {Receive}\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/rx_clk\r
+add wave -noupdate -format Literal -radix hexadecimal /test_ts_mac/rxd\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/rxer\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/rxdv\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/col\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/crs\r
+add wave -noupdate -divider {Register Read Write Interface}\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/pc_clk\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/pc_datain\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/pc_dataout\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/pc_retry\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/pc_error\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/pc_ready\r
+add wave -noupdate -format Logic -radix hexadecimal /test_ts_mac/pc_ack
\ No newline at end of file

diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/params/ts_mac_defines.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/params/ts_mac_defines.v
new file mode 100644 (file)
index 0000000..d5ac36a
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/params/ts_mac_defines.v
@@ -0,0 +1,2 @@
+`define SGMII_TSMAC
+`define DEVICE_ECP5UM

diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/fifo_2048x9.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/fifo_2048x9.v
new file mode 100644 (file)
index 0000000..3400eca
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/fifo_2048x9.v
@@ -0,0 +1,345 @@
+// ===========================================================================\r
+// Verilog module generated by IPexpress\r
+// Filename: fifo_2048x9.v  \r
+// Copyright 2012 (c) Lattice Semiconductor Corporation. All rights reserved.\r
+// ===========================================================================\r
+\r
+module fifo_2048x9 (\r
+// INPUTS\r
+     wclk,     // write clock for fifo\r
+     wren,     // write select for fifo\r
+     datain,   // 8 data + control for fifo\r
+     reset,    // clear fifo active high\r
+     rclk,     // read clock for fifo\r
+     rden,     // read select for fifo\r
+     aff_thrhd, // 9 bit almost full flag threshold value for fifo\r
+     afe_thrhd, // 9 bit almost full flag threshold value for fifo\r
+     wclk_en,    // RAM write clock enable\r
+     rclk_en,    // RAM read clock enable\r
+\r
+// OUTPUTS     \r
+     daout,            // 8 data + control for outputs\r
+     empty,            // empty flag\r
+     almost_full,      //  almost full flag\r
+     almost_empty,     //  almost empty flag\r
+     full              // full flag\r
+   );\r
+parameter pdevice_family = "ECP";\r
+\r
+input wclk;            // write clock for fifo\r
+input wren;            // write select for fifo\r
+input reset;           // clear fifo - active low\r
+input rclk;            // read clock for fifo\r
+input rden;            // read select for fifo\r
+input [8:0]    datain; // 8 data + control for fifo\r
+input [8:0] aff_thrhd;  // 9 bit almost full flag threshold value \r
+input [8:0] afe_thrhd;  // 9 bit almost empty flag threshold value for output fifo\r
+input wclk_en;\r
+input rclk_en;\r
+\r
+output almost_full, almost_empty, full, empty; \r
+output [8:0]   daout;  // 8 data + control for fifo\r
+\r
+// DECLARATIONS\r
+wire [8:0] wr_addr_a;\r
+wire [8:0] wr_addr_b;\r
+wire [8:0] wr_addr_c;\r
+wire [8:0] wr_addr_d;\r
+wire [8:0] rd_addr_a;\r
+wire [8:0] rd_addr_b;\r
+wire [8:0] rd_addr_c;\r
+wire [8:0] rd_addr_d;\r
+wire wr_en_a_clk_en;   // fifo write enable\r
+wire wr_en_b_clk_en;   // fifo write enable\r
+wire wr_en_c_clk_en;   // fifo write enable\r
+wire wr_en_d_clk_en;   // fifo write enable\r
+wire wr_en_a, rd_en_a; // fifo write enable\r
+wire wr_en_b, rd_en_b; // fifo write enable\r
+wire wr_en_c, rd_en_c; // fifo write enable\r
+wire wr_en_d, rd_en_d; // fifo write enable\r
+wire [8:0] aff_thrhd;\r
+wire [8:0] afe_thrhd;\r
+wire [8:0] ram_da_out_a; // ram_512x9 data output\r
+reg  [8:0] ram_da_out_a_d; // ram_512x9 data output\r
+wire [8:0] ram_da_out_b; // ram_512x9 data output\r
+reg  [8:0] ram_da_out_b_d; // ram_512x9 data output\r
+wire [8:0] ram_da_out_c; // ram_512x9 data output\r
+reg  [8:0] ram_da_out_c_d; // ram_512x9 data output\r
+wire [8:0] ram_da_out_d; // ram_512x9 data output\r
+wire      rd_a; // fifo read/write\r
+wire      rd_b; // fifo read/write\r
+wire      rd_c; // fifo read/write\r
+reg       wr_b; // fifo read/write\r
+reg       wr_b_d; // fifo read/write\r
+reg       wr_c; // fifo read/write\r
+reg       wr_c_d; // fifo read/write\r
+reg       wr_d; // fifo read/write\r
+reg       wr_d_d; // fifo read/write\r
+wire      empty_a; // fifo empty\r
+wire      empty_b; // fifo empty\r
+wire      empty_c; // fifo empty\r
+wire      almost_full_b; // fifo full\r
+wire      almost_full_c; // fifo full\r
+wire      almost_full_d; // fifo full\r
+assign rd_a = ~empty_a & ~almost_full_b;\r
+assign rd_b = ~empty_b & ~almost_full_c;\r
+assign rd_c = ~empty_c & ~almost_full_d;\r
+assign wr_en_a_clk_en = wr_en_a & wclk_en;\r
+assign wr_en_b_clk_en = wr_en_b & rclk_en;\r
+assign wr_en_c_clk_en = wr_en_c & rclk_en;\r
+assign wr_en_d_clk_en = wr_en_d & rclk_en;\r
+\r
+wire [8:0]     daout;  // 8 data + control for fifo\r
+assign         #1 daout[8:0] = ram_da_out_d[8:0];\r
+/* \r
+ * params SYNC_MODE and RAM_MODE set in level above\r
+ * and passed through.\r
+ */\r
+//parameter SYNC_MODE = "SYNC";// rd/wr clocks same\r
+//parameter RAM_MODE = "REG";  //input reg\r
+parameter SYNC_MODE = "ASYNC";\r
+parameter RAM_MODE = "NOREG";\r
+defparam  ff_ctl_a.SYNC_MODE = SYNC_MODE;\r
+defparam  ff_ctl_a.RAM_MODE = RAM_MODE;\r
+defparam  ff_ctl_b.RAM_MODE = RAM_MODE;\r
+defparam  ff_ctl_c.RAM_MODE = RAM_MODE;\r
+defparam  ff_ctl_d.RAM_MODE = RAM_MODE;\r
+\r
+        always @(posedge rclk or negedge reset) begin\r
+          if (~reset) begin\r
+               wr_b <= 1'b0;\r
+               wr_b_d <= 1'b0;\r
+               wr_c <= 1'b0;\r
+               wr_c_d <= 1'b0;\r
+               wr_d <= 1'b0;\r
+               wr_d_d <= 1'b0;\r
+               ram_da_out_a_d <= 9'b000000000;\r
+               ram_da_out_b_d <= 9'b000000000;\r
+               ram_da_out_c_d <= 9'b000000000;\r
+          end\r
+          else begin\r
+               if(rclk_en == 1) begin\r
+               wr_b <= rd_a;\r
+               wr_b_d <= wr_b;\r
+               wr_c <= rd_b;\r
+               wr_c_d <= wr_c;\r
+               wr_d <= rd_c;\r
+               wr_d_d <= wr_d;\r
+               ram_da_out_a_d <= ram_da_out_a;\r
+               ram_da_out_b_d <= ram_da_out_b;\r
+               ram_da_out_c_d <= ram_da_out_c;\r
+               end // if\r
+          end // else\r
+        end // always\r
+\r
+fifo_512_ctl ff_ctl_a(\r
+       // Inputs\r
+       .ckw(wclk),\r
+       .ckw_en(wclk_en),\r
+       .csw(wren),\r
+       .rst_wr(reset),\r
+       .rst_rd(reset),\r
+       .ckr(rclk),\r
+       .ckr_en(rclk_en),\r
+       .csr(rd_a),\r
+       .aff_thrhd(aff_thrhd[8:0]),\r
+       .afe_thrhd(9'b000110000),\r
+       // Outputs\r
+       .wr_adr(wr_addr_a[8:0]),\r
+       .rd_adr(rd_addr_a[8:0]),\r
+       .ff(full),\r
+       .aff(almost_full),\r
+       .afe(almost_empty_a),\r
+       .ef(empty_a),\r
+       .wr_en(wr_en_a),\r
+       .rd_en(rd_en_a),\r
+       .ram_rd_en()\r
+       );\r
+\r
+pmi_ram_dp\r
+  #(.pmi_wr_addr_depth(512),\r
+    .pmi_wr_addr_width(9),\r
+    .pmi_wr_data_width(9),\r
+    .pmi_rd_addr_depth(512),\r
+    .pmi_rd_addr_width(9),  \r
+    .pmi_rd_data_width(9), \r
+    .pmi_regmode("noreg"),\r
+    .pmi_gsr("enable"),\r
+    .pmi_resetmode("sync"),\r
+    .pmi_init_file("none"),\r
+    .pmi_init_file_format("binary"),\r
+    .pmi_family(pdevice_family),           \r
+    .module_type("pmi_ram_dp")\r
+    )\r
+U1_pmi_ram_dp   (.Data(datain[8:0]),\r
+                 .WrAddress(wr_addr_a[8:0]),\r
+                 .RdAddress(rd_addr_a[8:0]),\r
+                 .WrClock(wclk),\r
+                 .RdClock(rclk),\r
+                 .WrClockEn(wr_en_a_clk_en),\r
+                 //.RdClockEn(1'b1),\r
+                 .RdClockEn(rclk_en),\r
+                 .WE(1'b1),\r
+                 .Reset(1'b0),\r
+                 .Q(ram_da_out_a[8:0])\r
+                 );\r
+\r
+fifo_512_ctl ff_ctl_b(\r
+       // Inputs\r
+       .ckw(rclk),\r
+       .ckw_en(rclk_en),\r
+       .csw(wr_b_d),\r
+       .rst_wr(reset),\r
+       .rst_rd(reset),\r
+       .ckr(rclk),\r
+       .ckr_en(rclk_en),\r
+       .csr(rd_b),\r
+       .aff_thrhd(9'b111111100),\r
+       .afe_thrhd(9'b000000000),\r
+       // Outputs\r
+       .wr_adr(wr_addr_b[8:0]),\r
+       .rd_adr(rd_addr_b[8:0]),\r
+       .ff(full_b),\r
+       .aff(almost_full_b),\r
+       .afe(almost_empty_b),\r
+       .ef(empty_b),\r
+       .wr_en(wr_en_b),\r
+       .rd_en(rd_en_b),\r
+       .ram_rd_en()\r
+       );\r
+\r
+pmi_ram_dp\r
+  #(.pmi_wr_addr_depth(512),\r
+    .pmi_wr_addr_width(9),\r
+    .pmi_wr_data_width(9),\r
+    .pmi_rd_addr_depth(512),\r
+    .pmi_rd_addr_width(9),  \r
+    .pmi_rd_data_width(9), \r
+    .pmi_regmode("noreg"),\r
+    .pmi_gsr("enable"),\r
+    .pmi_resetmode("sync"),\r
+    .pmi_init_file("none"),\r
+    .pmi_init_file_format("binary"),\r
+    .pmi_family(pdevice_family),           \r
+    .module_type("pmi_ram_dp")\r
+    )\r
+U2_pmi_ram_dp   (.Data(ram_da_out_a_d[8:0]),\r
+                 .WrAddress(wr_addr_b[8:0]),\r
+                 .RdAddress(rd_addr_b[8:0]),\r
+                 .WrClock(rclk),\r
+                 .RdClock(rclk),\r
+                 .WrClockEn(wr_en_b_clk_en),\r
+                 //.RdClockEn(1'b1),\r
+                 .RdClockEn(rclk_en),\r
+                 .WE(1'b1),\r
+                 .Reset(1'b0),\r
+                 .Q(ram_da_out_b[8:0])\r
+                 );\r
+\r
+\r
+fifo_512_ctl ff_ctl_c(\r
+       // Inputs\r
+       .ckw(rclk),\r
+       .ckw_en(rclk_en),\r
+       .csw(wr_c_d),\r
+       .rst_wr(reset),\r
+       .rst_rd(reset),\r
+       .ckr(rclk),\r
+       .ckr_en(rclk_en),\r
+       .csr(rd_c),\r
+       .aff_thrhd(9'b111111100),\r
+       .afe_thrhd(9'b000000000),\r
+       // Outputs\r
+       .wr_adr(wr_addr_c[8:0]),\r
+       .rd_adr(rd_addr_c[8:0]),\r
+       .ff(full_c),\r
+       .aff(almost_full_c),\r
+       .afe(almost_empty_c),\r
+       .ef(empty_c),\r
+       .wr_en(wr_en_c),\r
+       .rd_en(rd_en_c),\r
+       .ram_rd_en()\r
+       );\r
+\r
+pmi_ram_dp\r
+  #(.pmi_wr_addr_depth(512),\r
+    .pmi_wr_addr_width(9),\r
+    .pmi_wr_data_width(9),\r
+    .pmi_rd_addr_depth(512),\r
+    .pmi_rd_addr_width(9),  \r
+    .pmi_rd_data_width(9), \r
+    .pmi_regmode("noreg"),\r
+    .pmi_gsr("enable"),\r
+    .pmi_resetmode("sync"),\r
+    .pmi_init_file("none"),\r
+    .pmi_init_file_format("binary"),\r
+    .pmi_family(pdevice_family),           \r
+    .module_type("pmi_ram_dp")\r
+    )\r
+U3_pmi_ram_dp   (.Data(ram_da_out_b_d[8:0]),\r
+                 .WrAddress(wr_addr_c[8:0]),\r
+                 .RdAddress(rd_addr_c[8:0]),\r
+                 .WrClock(rclk),\r
+                 .RdClock(rclk),\r
+                 .WrClockEn(wr_en_c_clk_en),\r
+                 //.RdClockEn(1'b1),\r
+                 .RdClockEn(rclk_en),\r
+                 .WE(1'b1),\r
+                 .Reset(1'b0),\r
+                 .Q(ram_da_out_c[8:0])\r
+                 );\r
+\r
+\r
+fifo_512_ctl ff_ctl_d(\r
+       // Inputs\r
+       .ckw(rclk),\r
+       .ckw_en(rclk_en),\r
+       .csw(wr_d_d),\r
+       .rst_wr(reset),\r
+       .rst_rd(reset),\r
+       .ckr(rclk),\r
+       .ckr_en(rclk_en),\r
+       .csr(rden),\r
+       .aff_thrhd(9'b111111100),\r
+       .afe_thrhd(afe_thrhd[8:0]),\r
+       // Outputs\r
+       .wr_adr(wr_addr_d[8:0]),\r
+       .rd_adr(rd_addr_d[8:0]),\r
+       .ff(full_d),\r
+       .aff(almost_full_d),\r
+       .afe(almost_empty),\r
+       .ef(empty),\r
+       .wr_en(wr_en_d),\r
+       .rd_en(rd_en_d),\r
+       .ram_rd_en()\r
+       );\r
+\r
+pmi_ram_dp\r
+  #(.pmi_wr_addr_depth(512),\r
+    .pmi_wr_addr_width(9),\r
+    .pmi_wr_data_width(9),\r
+    .pmi_rd_addr_depth(512),\r
+    .pmi_rd_addr_width(9),  \r
+    .pmi_rd_data_width(9), \r
+    .pmi_regmode("noreg"),\r
+    .pmi_gsr("enable"),\r
+    .pmi_resetmode("sync"),\r
+    .pmi_init_file("none"),\r
+    .pmi_init_file_format("binary"),\r
+    .pmi_family(pdevice_family),           \r
+    .module_type("pmi_ram_dp")\r
+    )\r
+U4_pmi_ram_dp   (.Data(ram_da_out_c_d[8:0]),\r
+                 .WrAddress(wr_addr_d[8:0]),\r
+                 .RdAddress(rd_addr_d[8:0]),\r
+                 .WrClock(rclk),\r
+                 .RdClock(rclk),\r
+                 .WrClockEn(wr_en_d_clk_en),\r
+                 //.RdClockEn(1'b1),\r
+                 .RdClockEn(rclk_en),\r
+                 .WE(1'b1),\r
+                 .Reset(1'b0),\r
+                 .Q(ram_da_out_d[8:0])\r
+                 );\r
+\r
+endmodule    // end of fifo_2048x9\r

diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/fifo_512_ctl.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/fifo_512_ctl.v
new file mode 100644 (file)
index 0000000..7d20d97
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/fifo_512_ctl.v
@@ -0,0 +1,373 @@
+// ===========================================================================\r
+// Verilog module generated by IPexpress\r
+// Filename: fifo_512_ctl.v  \r
+// Copyright 2012 (c) Lattice Semiconductor Corporation. All rights reserved.\r
+// ===========================================================================\r
+\r
+module fifo_512_ctl (\r
+// INPUTS\r
+     ckw,      // write clock for fifo\r
+     ckw_en,   // write clock enable for fifo\r
+     csw,      // write select for fifo\r
+     rst_wr,   // fifo write clock domain reset active low\r
+     rst_rd,   // fifo read clock domain reset active low\r
+     ckr,      // read clock for fifo\r
+     ckr_en,   // read clock enable for fifo\r
+     csr,      // read select for fifo\r
+     aff_thrhd,        // 9 bit almost full flag threshold value\r
+     afe_thrhd,        // 9 bit almost empty flag threshold value\r
+\r
+// OUTPUTS     \r
+     wr_adr,   // FIFO write address to ram\r
+     rd_adr,   // FIFO read address to ram\r
+     ef,       // empty flag\r
+     aff,      // almost full flag \r
+     afe,      // almost empty flag \r
+     ff,       // full flag\r
+     wr_en,    // ram write enable\r
+     rd_en,    // read enable\r
+     ram_rd_en // ram read enable to the ram\r
+   );\r
+\r
+parameter SYNC_MODE = "SYNC";\r
+parameter RAM_MODE = "REG";\r
+\r
+input ckw;             // write clock for fifo\r
+input ckw_en;          // write clock enable for fifo\r
+input csw;             // write select for fifo\r
+input rst_wr;          // fifo write clock domain reset active low\r
+input rst_rd;          // fifo read clock domain reset active low\r
+input ckr;             // read clock for fifo\r
+input ckr_en;          // resd clock enable for fifo\r
+input csr;             // read select for fifo\r
+input  [8:0] aff_thrhd;        // 9 bit almost full flag threshold value\r
+input  [8:0] afe_thrhd;        // 9 bit almost empty flag threshold value\r
+\r
+output [8:0] wr_adr;\r
+output [8:0] rd_adr;\r
+output wr_en, rd_en, ram_rd_en;\r
+output ef, ff, aff, afe;       \r
+\r
+// DECLARATIONS\r
+wire wr_en;\r
+wire rd_en;\r
+wire ram_rd_en;\r
+wire   [9:0] sync_wcnt, sync_rcnt;\r
+wire   [9:0] async_wcnt, async_rcnt;\r
+wire   [9:0] wcnt;\r
+wire   [9:0] rcnt;\r
+wire   [8:0] wr_adr, rd_adr;\r
+\r
+reg    [9:0] wr_addr;\r
+reg    [9:0] rd_addr;\r
+reg    [9:0] rd_addr_reg;\r
+reg    ef, ff, aff, afe;\r
+wire   [8:0] rd_addr_temp;\r
+\r
+// select the old address during fifo empty. This application is\r
+// used for the special ECP ram model with read clock enable input \r
+assign rd_addr_temp[8:0] = (ef) ? rd_addr_reg[8:0] : rd_addr[8:0];\r
+\r
+\r
+// ASSIGN\r
+assign wr_en = csw & (~ff);\r
+assign rd_en = csr & (~ef);\r
+assign ram_rd_en = csr | ef;\r
+assign wr_adr[8:0] = wr_addr[8:0];\r
+\r
+// select the input read address with register mode or without register mode\r
+//assign       rd_adr[8:0] = (RAM_MODE == "REG") ? rd_addr[8:0] : rd_addr_reg[8:0];\r
+assign rd_adr[8:0] = (RAM_MODE == "REG") ? rd_addr_temp[8:0] : rd_addr_reg[8:0];\r
+\r
+// select the SYNC mode or ASYNC mode\r
+assign  wcnt[9:0] = (SYNC_MODE == "SYNC")? sync_wcnt[9:0] : async_wcnt[9:0];   \r
+assign  rcnt[9:0] = (SYNC_MODE == "SYNC")? sync_rcnt[9:0] : async_rcnt[9:0];   \r
+\r
+assign sync_wcnt[9:0] = {rd_addr_reg[9]^wr_addr[9], wr_addr[8:0]} - rd_addr_reg[8:0];\r
+assign sync_rcnt[9:0] = {wr_addr[9]^rd_addr_reg[9], wr_addr[8:0]} - rd_addr_reg[8:0];\r
+       \r
+// DECLARATIONS\r
+reg    [9:0] wr_addr_gc;\r
+reg    [9:0] wr2_addr;\r
+\r
+// wire        [9:0] wr1_addr;\r
+// assign wr1_addr[9:0] = wr_addr[9:0]+1;\r
+// wr2_addr is the same logic function as wr1_addr \r
+// use wr2_addr replace wr1_addr for improve timing.\r
+//assign wr1_addr[9:0] = wr_addr[9:0]+1 after wr_addr\r
+// increased by 1 and wr2_addr[9:0] = wr_addr[9:0]+ 2\r
+// at the same time wr_addr increase by 1;\r
+\r
+\r
+// generate write address\r
+always @(posedge ckw or negedge rst_wr) begin\r
+    if (~rst_wr) begin\r
+        wr_addr[9:0] <= 10'd0;\r
+        wr_addr_gc[9:0] <= 10'd0;\r
+        wr2_addr[9:0] <= 10'd0;\r
+    end // if\r
+    else begin\r
+       if(ckw_en == 1) begin\r
+       if(wr_en == 1) begin\r
+               wr_addr[9:0] <= wr_addr[9:0] + 1;\r
+               wr2_addr[9:0] <= wr_addr[9:0] + 2;\r
+               wr_addr_gc[0] <= wr2_addr[0]^wr2_addr[1];\r
+               wr_addr_gc[1] <= wr2_addr[1]^wr2_addr[2];\r
+               wr_addr_gc[2] <= wr2_addr[2]^wr2_addr[3];\r
+               wr_addr_gc[3] <= wr2_addr[3]^wr2_addr[4];\r
+               wr_addr_gc[4] <= wr2_addr[4]^wr2_addr[5];\r
+               wr_addr_gc[5] <= wr2_addr[5]^wr2_addr[6];\r
+               wr_addr_gc[6] <= wr2_addr[6]^wr2_addr[7];\r
+               wr_addr_gc[7] <= wr2_addr[7]^wr2_addr[8];\r
+               wr_addr_gc[8] <= wr2_addr[8]^wr2_addr[9];\r
+               wr_addr_gc[9] <= wr2_addr[9];\r
+       end // if\r
+       end // if\r
+    end // else\r
+end // always\r
+       \r
+// DECLARATIONS\r
+reg    [9:0] rd_addr_gc;\r
+reg    [9:0] rd2_addr;\r
+\r
+// wire        [9:0] rd1_addr;\r
+// assign rd1_addr[9:0] = rd_addr[9:0]+1;\r
+// rd2_addr is the same logic function as rd1_addr \r
+// use rd2_addr replace rd1_addr for improve timing.\r
+// assign rd1_addr[9:0] = rd_addr[9:0]+1 after rd_addr\r
+// increased by 1 and rd2_addr[9:0] = rd_addr[9:0]+ 2\r
+// at the same time rd_addr increase by 1;\r
+\r
+// generate read address \r
+always @(posedge ckr or negedge rst_rd) begin\r
+    if (~rst_rd) begin\r
+        rd_addr[9:0] <= 10'd1;\r
+        rd_addr_reg[9:0] <= 10'd0;\r
+        rd_addr_gc[9:0] <= 10'd0;\r
+        rd2_addr[9:0] <= 10'd0;\r
+    end // if\r
+    else begin\r
+       if(ckr_en == 1) begin\r
+       if(rd_en == 1) begin\r
+               rd_addr[9:0] <= rd_addr[9:0] + 1;\r
+               rd_addr_reg[9:0] <= rd_addr[9:0];\r
+               rd2_addr[9:0] <= rd_addr_reg[9:0] + 2;\r
+               rd_addr_gc[0] <= rd2_addr[0]^rd2_addr[1];\r
+               rd_addr_gc[1] <= rd2_addr[1]^rd2_addr[2];\r
+               rd_addr_gc[2] <= rd2_addr[2]^rd2_addr[3];\r
+               rd_addr_gc[3] <= rd2_addr[3]^rd2_addr[4];\r
+               rd_addr_gc[4] <= rd2_addr[4]^rd2_addr[5];\r
+               rd_addr_gc[5] <= rd2_addr[5]^rd2_addr[6];\r
+               rd_addr_gc[6] <= rd2_addr[6]^rd2_addr[7];\r
+               rd_addr_gc[7] <= rd2_addr[7]^rd2_addr[8];\r
+               rd_addr_gc[8] <= rd2_addr[8]^rd2_addr[9];\r
+               rd_addr_gc[9] <= rd2_addr[9];\r
+       end // if\r
+       end // if\r
+    end // else\r
+end // always\r
+\r
+reg    [9:0] rd_addr_gcf;\r
+\r
+// convert read address to write clock domain\r
+always @(posedge ckw or negedge rst_wr) begin\r
+    if (~rst_wr) begin\r
+        rd_addr_gcf[9:0] <= 10'd0;\r
+    end // if\r
+    else begin\r
+       if(ckw_en == 1) begin\r
+        rd_addr_gcf[9:0] <= rd_addr_gc[9:0];\r
+       end // if\r
+    end // else\r
+end // always\r
+\r
+reg    [9:0] wr_addr_gcf;\r
+\r
+// convert write address to read clock domain\r
+always @(posedge ckr or negedge rst_rd) begin\r
+    if (~rst_rd) begin\r
+        wr_addr_gcf[9:0] <= 10'd0;\r
+    end // if\r
+    else begin\r
+       if(ckr_en == 1) begin\r
+        wr_addr_gcf[9:0] <= wr_addr_gc[9:0];\r
+       end // if\r
+    end // else\r
+end // always\r
+\r
+// convert write address gray code back to binary code\r
+\r
+/*\r
+wire   [9:0] wr_addr_bin_ckr;\r
+assign wr_addr_bin_ckr[0] = wr_addr_gcf[0]^wr_addr_gcf[1]^wr_addr_gcf[2]\r
+       ^wr_addr_gcf[3]^wr_addr_gcf[4]^wr_addr_gcf[5]^wr_addr_gcf[6]\r
+       ^wr_addr_gcf[7]^wr_addr_gcf[8]^wr_addr_gcf[9];\r
+assign wr_addr_bin_ckr[1] = wr_addr_gcf[1]^wr_addr_gcf[2]^wr_addr_gcf[3]\r
+       ^wr_addr_gcf[4]^wr_addr_gcf[5]^wr_addr_gcf[6]\r
+       ^wr_addr_gcf[7]^wr_addr_gcf[8]^wr_addr_gcf[9];\r
+assign wr_addr_bin_ckr[2] = wr_addr_gcf[2]^wr_addr_gcf[3]^wr_addr_gcf[4]\r
+       ^wr_addr_gcf[5]^wr_addr_gcf[6]^wr_addr_gcf[7]\r
+       ^wr_addr_gcf[8]^wr_addr_gcf[9];\r
+assign wr_addr_bin_ckr[3] = wr_addr_gcf[3]^wr_addr_gcf[4]^wr_addr_gcf[5]\r
+       ^wr_addr_gcf[6]^wr_addr_gcf[7]^wr_addr_gcf[8]^wr_addr_gcf[9];\r
+assign wr_addr_bin_ckr[4] = wr_addr_gcf[4]^wr_addr_gcf[5]^wr_addr_gcf[6]\r
+       ^wr_addr_gcf[7]^wr_addr_gcf[8]^wr_addr_gcf[9];\r
+assign wr_addr_bin_ckr[5] = wr_addr_gcf[5]^wr_addr_gcf[6]\r
+       ^wr_addr_gcf[7]^wr_addr_gcf[8]^wr_addr_gcf[9];\r
+assign wr_addr_bin_ckr[6] = wr_addr_gcf[6]^wr_addr_gcf[7]\r
+        ^wr_addr_gcf[8]^wr_addr_gcf[9];\r
+assign wr_addr_bin_ckr[7] = wr_addr_gcf[7]^wr_addr_gcf[8]^wr_addr_gcf[9];\r
+assign wr_addr_bin_ckr[8] = wr_addr_gcf[8]^wr_addr_gcf[9];\r
+assign wr_addr_bin_ckr[9] = wr_addr_gcf[9];\r
+*/\r
+\r
+// for timing reason  convert wire to register \r
+// the design will add one clock delay for the write counter \r
+// before compare to the read counter\r
+\r
+reg    [9:0] wr_addr_bin_ckr;\r
+always @(posedge ckr or negedge rst_rd) begin\r
+    if (~rst_rd) begin\r
+        wr_addr_bin_ckr[9:0] <= 10'd0;\r
+    end // if\r
+    else begin\r
+       if(ckr_en == 1) begin\r
+       wr_addr_bin_ckr[0] <= wr_addr_gcf[0]^wr_addr_gcf[1]^wr_addr_gcf[2]\r
+       ^wr_addr_gcf[3]^wr_addr_gcf[4]^wr_addr_gcf[5]^wr_addr_gcf[6]\r
+       ^wr_addr_gcf[7]^wr_addr_gcf[8]^wr_addr_gcf[9];\r
+       wr_addr_bin_ckr[1] <= wr_addr_gcf[1]^wr_addr_gcf[2]^wr_addr_gcf[3]\r
+       ^wr_addr_gcf[4]^wr_addr_gcf[5]^wr_addr_gcf[6]\r
+       ^wr_addr_gcf[7]^wr_addr_gcf[8]^wr_addr_gcf[9];\r
+       wr_addr_bin_ckr[2] <= wr_addr_gcf[2]^wr_addr_gcf[3]^wr_addr_gcf[4]\r
+       ^wr_addr_gcf[5]^wr_addr_gcf[6]^wr_addr_gcf[7]^wr_addr_gcf[8]^wr_addr_gcf[9];\r
+       wr_addr_bin_ckr[3] <= wr_addr_gcf[3]^wr_addr_gcf[4]^wr_addr_gcf[5]\r
+       ^wr_addr_gcf[6]^wr_addr_gcf[7]^wr_addr_gcf[8]^wr_addr_gcf[9];\r
+       wr_addr_bin_ckr[4] <= wr_addr_gcf[4]^wr_addr_gcf[5]^wr_addr_gcf[6]\r
+       ^wr_addr_gcf[7]^wr_addr_gcf[8]^wr_addr_gcf[9];\r
+       wr_addr_bin_ckr[5] <= wr_addr_gcf[5]^wr_addr_gcf[6]\r
+       ^wr_addr_gcf[7]^wr_addr_gcf[8]^wr_addr_gcf[9];\r
+       wr_addr_bin_ckr[6] <= wr_addr_gcf[6]^wr_addr_gcf[7]\r
+       ^wr_addr_gcf[8]^wr_addr_gcf[9];\r
+       wr_addr_bin_ckr[7] <= wr_addr_gcf[7]^wr_addr_gcf[8]^wr_addr_gcf[9];\r
+       wr_addr_bin_ckr[8] <= wr_addr_gcf[8]^wr_addr_gcf[9];\r
+       wr_addr_bin_ckr[9] <= wr_addr_gcf[9];\r
+       end //if\r
+    end // else\r
+end // always\r
+\r
+assign async_rcnt[9:0] = {wr_addr_bin_ckr[9]^rd_addr_reg[9], wr_addr_bin_ckr[8:0]} \r
+                       - rd_addr_reg[8:0];\r
+\r
+/*\r
+wire   [9:0] rd_addr_bin_ckw;\r
+assign rd_addr_bin_ckw[0] = rd_addr_gcf[0]^rd_addr_gcf[1]^rd_addr_gcf[2]\r
+       ^rd_addr_gcf[3]^rd_addr_gcf[4]^rd_addr_gcf[5]^rd_addr_gcf[6]\r
+       ^rd_addr_gcf[7]^rd_addr_gcf[8]^rd_addr_gcf[9];\r
+assign rd_addr_bin_ckw[1] = rd_addr_gcf[1]^rd_addr_gcf[2]^rd_addr_gcf[3]\r
+       ^rd_addr_gcf[4]^rd_addr_gcf[5]^rd_addr_gcf[6]\r
+       ^rd_addr_gcf[7]^rd_addr_gcf[8]^rd_addr_gcf[9];\r
+assign rd_addr_bin_ckw[2] = rd_addr_gcf[2]^rd_addr_gcf[3]^rd_addr_gcf[4]\r
+       ^rd_addr_gcf[5]^rd_addr_gcf[6]^rd_addr_gcf[7]\r
+       ^rd_addr_gcf[8]^rd_addr_gcf[9];\r
+assign rd_addr_bin_ckw[3] = rd_addr_gcf[3]^rd_addr_gcf[4]^rd_addr_gcf[5]\r
+       ^rd_addr_gcf[6]^rd_addr_gcf[7]^rd_addr_gcf[8]^rd_addr_gcf[9];\r
+assign rd_addr_bin_ckw[4] = rd_addr_gcf[4]^rd_addr_gcf[5]^rd_addr_gcf[6]\r
+       ^rd_addr_gcf[7]^rd_addr_gcf[8]^rd_addr_gcf[9];\r
+assign rd_addr_bin_ckw[5] = rd_addr_gcf[5]^rd_addr_gcf[6]\r
+       ^rd_addr_gcf[7]^rd_addr_gcf[8]^rd_addr_gcf[9];\r
+assign rd_addr_bin_ckw[6] = rd_addr_gcf[6]^rd_addr_gcf[7]\r
+        ^rd_addr_gcf[8]^rd_addr_gcf[9];\r
+assign rd_addr_bin_ckw[7] = rd_addr_gcf[7]^rd_addr_gcf[8]^rd_addr_gcf[9];\r
+assign rd_addr_bin_ckw[8] = rd_addr_gcf[8]^rd_addr_gcf[9];\r
+assign rd_addr_bin_ckw[9] = rd_addr_gcf[9];\r
+*/\r
+\r
+// for timing reason  convert wire to register \r
+// the design will add one clock delay for the read counter \r
+// before compare to the write counter\r
+\r
+reg    [9:0] rd_addr_bin_ckw;\r
+always @(posedge ckw or negedge rst_wr) begin\r
+    if (~rst_wr) begin\r
+        rd_addr_bin_ckw[9:0] <= 10'd0;\r
+    end // if\r
+    else begin\r
+       if(ckw_en == 1) begin\r
+       rd_addr_bin_ckw[0] <= rd_addr_gcf[0]^rd_addr_gcf[1]^rd_addr_gcf[2]\r
+       ^rd_addr_gcf[3]^rd_addr_gcf[4]^rd_addr_gcf[5]^rd_addr_gcf[6]\r
+       ^rd_addr_gcf[7]^rd_addr_gcf[8]^rd_addr_gcf[9];\r
+       rd_addr_bin_ckw[1] <= rd_addr_gcf[1]^rd_addr_gcf[2]^rd_addr_gcf[3]\r
+       ^rd_addr_gcf[4]^rd_addr_gcf[5]^rd_addr_gcf[6]\r
+       ^rd_addr_gcf[7]^rd_addr_gcf[8]^rd_addr_gcf[9];\r
+       rd_addr_bin_ckw[2] <= rd_addr_gcf[2]^rd_addr_gcf[3]^rd_addr_gcf[4]\r
+       ^rd_addr_gcf[5]^rd_addr_gcf[6]^rd_addr_gcf[7]\r
+       ^rd_addr_gcf[8]^rd_addr_gcf[9];\r
+       rd_addr_bin_ckw[3] <= rd_addr_gcf[3]^rd_addr_gcf[4]^rd_addr_gcf[5]\r
+       ^rd_addr_gcf[6]^rd_addr_gcf[7]^rd_addr_gcf[8]^rd_addr_gcf[9];\r
+       rd_addr_bin_ckw[4] <= rd_addr_gcf[4]^rd_addr_gcf[5]^rd_addr_gcf[6]\r
+       ^rd_addr_gcf[7]^rd_addr_gcf[8]^rd_addr_gcf[9];\r
+       rd_addr_bin_ckw[5] <= rd_addr_gcf[5]^rd_addr_gcf[6]\r
+       ^rd_addr_gcf[7]^rd_addr_gcf[8]^rd_addr_gcf[9];\r
+       rd_addr_bin_ckw[6] <= rd_addr_gcf[6]^rd_addr_gcf[7]\r
+       ^rd_addr_gcf[8]^rd_addr_gcf[9];\r
+       rd_addr_bin_ckw[7] <= rd_addr_gcf[7]^rd_addr_gcf[8]^rd_addr_gcf[9];\r
+       rd_addr_bin_ckw[8] <= rd_addr_gcf[8]^rd_addr_gcf[9];\r
+       rd_addr_bin_ckw[9] <= rd_addr_gcf[9];\r
+       end // if\r
+    end // else\r
+end // always\r
+\r
+assign async_wcnt[9:0] = {rd_addr_bin_ckw[9]^wr_addr[9], wr_addr[8:0]} - rd_addr_bin_ckw[8:0];\r
+\r
+//  detect the fifo full\r
+always @(posedge ckw or negedge rst_wr) begin\r
+    if (~rst_wr) begin\r
+        ff <= 1'b0;\r
+        aff <= 1'b0;\r
+    end // if\r
+    else begin\r
+       if(ckw_en == 1) begin\r
+       if(wcnt[9:0] >= 511 | ((wcnt[9:0] == 510) && (wr_en == 1))) begin\r
+               ff <= 1'b1;\r
+       end // if\r
+       else begin\r
+               ff <= 1'b0;\r
+       end // if\r
+\r
+        // this extra bit is used  to take care of SPYGLASS warning messages\r
+       if(wcnt[9:0] >= {1'b0,aff_thrhd[8:0]}) begin\r
+               aff <= 1'b1;\r
+       end // if\r
+       else begin\r
+               aff <= 1'b0;\r
+       end // else\r
+       end // if\r
+    end // else\r
+end // always\r
+\r
+//  detect the fifo empty\r
+always @(posedge ckr or negedge rst_rd) begin\r
+    if (~rst_rd) begin\r
+        ef <= 1'b1;\r
+        afe <= 1'b1;\r
+    end // if\r
+    else begin\r
+       if(ckr_en == 1) begin\r
+       if((rcnt[9:0] == 0) || ((rcnt[9:0] == 1) && (rd_en == 1))) begin\r
+               ef <= 1'b1;\r
+       end // if\r
+       else begin\r
+               ef <= 1'b0;\r
+       end // else\r
+\r
+        // this extra bit is used  to take care of SPYGLASS warning messages\r
+       if(rcnt[9:0] <= {1'b0,afe_thrhd[8:0]}) begin\r
+               afe <= 1'b1;\r
+       end // if\r
+       else begin\r
+               afe <= 1'b0;\r
+       end // else\r
+       end // if\r
+    end // else\r
+end // always\r
+endmodule    // end of rfifo_ctl\r

diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/oddrx_soft.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/oddrx_soft.v
new file mode 100644 (file)
index 0000000..dfce8d2
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/oddrx_soft.v
@@ -0,0 +1,56 @@
+\r
+// ====================================================================\r
+// File Details\r
+// ====================================================================\r
+// Project              :       TSMAC IP Core For EC2\r
+// Filename             :       ODDRX_SFT.v\r
+// Author               :       lattice Semiconductor\r
+//=====================================================================\r
+//\r
+//* Notes:\r
+//*\r
+//* # Soft ODDR model for TSMAC \r
+//*\r
+\r
+module oddrx_soft\r
+(\r
+// Primary I/O \r
+DA, DB, RST, CLK_I, CLK_IX2, Q\r
+);\r
+\r
+input DA; \r
+input DB; \r
+input CLK_I; \r
+input CLK_IX2; \r
+input RST; \r
+output Q;\r
+\r
+reg  DA_f;\r
+reg  DB_f;\r
+reg  Q;\r
+wire MUX_OUT;\r
+\r
+\r
+   assign MUX_OUT = CLK_I ? DA_f:DB_f;\r
+\r
+   always @(posedge CLK_I or posedge RST) begin\r
+         if (RST) begin\r
+             DA_f <= 1'b0;\r
+             DB_f <= 1'b0;\r
+         end\r
+         else begin\r
+             DA_f <= DA;\r
+             DB_f <= DB;\r
+         end\r
+   end\r
+\r
+   always @(negedge CLK_IX2 or posedge RST) begin\r
+         if (RST) begin\r
+             Q <= 1'b0;\r
+         end\r
+         else begin\r
+             Q <= MUX_OUT;\r
+         end\r
+   end\r
+\r
+endmodule\r

diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/orcastra.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/orcastra.v
new file mode 100644 (file)
index 0000000..64ed991
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/orcastra.v
@@ -0,0 +1,424 @@
+// ===========================================================================\r
+// Verilog module generated by IPexpress\r
+// Filename: orcastra.v  \r
+// Copyright 2005 (c) Lattice Semiconductor Corporation. All rights reserved.\r
+// ===========================================================================\r
+\r
+\r
+\r
+//`timescale 1ns/100ps\r
+\r
+\r
+module orcastra (\r
+        //----------------------\r
+        // inputs to orcastra_intf\r
+        //----------------------\r
+       //\r
+        //************\r
+        // resets \r
+        //************\r
+        reset_n,\r
+        //************\r
+        // clocks \r
+        //************\r
+        hclk,\r
+        pc_clk,\r
+        //************************\r
+        // from pc parallel port \r
+        //************************\r
+        pc_datain,\r
+        pc_ready,\r
+       //****************\r
+       // from host bus \r
+       //****************\r
+       hdataout,\r
+       hready_n,\r
+        //*****************\r
+        //from reg_intf   \r
+        //*****************\r
+       us_rdata,\r
+       us_ack,\r
+        //*****************\r
+        //----------------------------\r
+        // outputs from orcastra_intf \r
+        //----------------------------\r
+       //\r
+        //*****************\r
+        //to reg_intf \r
+        //*****************\r
+       us_wdata,\r
+       us_rdy,\r
+       us_wr,\r
+       us_addr,\r
+       us_size,\r
+        //********************\r
+        // to MAC Host bus intf \r
+        //********************\r
+        hdatain,\r
+        hcs_n,\r
+        hread_n,\r
+        hwrite_n,\r
+        haddr,\r
+        //********************\r
+        // to pc parallel port \r
+        //********************\r
+        pc_dataout,\r
+        pc_error,\r
+        pc_retry,\r
+        pc_ack );\r
+\r
+\r
+//---------\r
+// INPUTS\r
+//---------\r
+//************\r
+// resets \r
+//************\r
+input reset_n;\r
+//************\r
+// clocks \r
+//************\r
+input hclk;\r
+input pc_clk;\r
+//************************\r
+// from pc parallel port \r
+//************************\r
+input pc_datain;\r
+input pc_ready;\r
+//***************\r
+// from host bus \r
+//***************\r
+input [7:0] hdataout;\r
+input hready_n;\r
+//*****************\r
+//from reg_intf   \r
+//*****************\r
+input [7:0] us_rdata;\r
+input us_ack;\r
+//*****************\r
+//---------\r
+// OUTPUTS\r
+//---------\r
+//*****************\r
+//to reg_intf \r
+//*****************\r
+output [7:0] us_wdata;\r
+output us_rdy;\r
+output us_wr;\r
+output [17:0] us_addr;\r
+output [1:0] us_size;\r
+//********************\r
+// to MAC Host bus intf \r
+//********************\r
+output [7:0] hdatain;\r
+output hcs_n;\r
+output hread_n;\r
+output hwrite_n;\r
+output [7:0] haddr;\r
+//********************\r
+// to pc parallel port \r
+//********************\r
+output pc_dataout;\r
+output pc_error;\r
+output pc_retry;\r
+output pc_ack; \r
+\r
+\r
+//-------------------\r
+// SIGNAL assignments\r
+//-------------------\r
+wire [7:0] us_wdata;\r
+reg us_rdy;\r
+reg us_wr;\r
+wire [17:0] us_addr;\r
+wire [1:0] us_size;\r
+wire [7:0] hdatain;\r
+reg hcs_n;\r
+reg hread_n;\r
+reg hwrite_n;\r
+wire [7:0] haddr;\r
+reg pc_dataout;\r
+reg pc_error;\r
+wire pc_retry;\r
+reg pc_ack; \r
+\r
+wire orc_ack;\r
+reg [7:0] sreg_do;\r
+reg [25:0] sreg_di;\r
+reg [25:0] reg_di;\r
+reg [2:0] rdwr_st;\r
+reg pc_ready_1d;\r
+reg pc_ready_2d;\r
+reg pc_ready_3d;\r
+reg orc_ack_1d;\r
+reg orc_ack_2d;\r
+reg orc_ack_3d;\r
+reg pc_rdy_pulse;\r
+wire [7:0] mux_dout;\r
+wire tstl_regs;\r
+\r
+reg gate_clk_ctl1;\r
+reg gate_clk_ctl2;\r
+wire gate_clk;\r
+reg [8:0] timeout_cnt;\r
+wire timeout;\r
+\r
+// PARAMETERS\r
+\r
+parameter [1:0]\r
+       SIZE = 2'b00;\r
+\r
+parameter [2:0]\r
+       IDLE    = 3'b000,       // IDLE State\r
+       READ    = 3'b001,       // READ State\r
+       WRITE   = 3'b010,       // WRITE State\r
+       WAIT1   = 3'b011,       // WAIT1 State\r
+       WAIT2   = 3'b100;       // WAIT2 State\r
+\r
+        assign  gate_clk_ctl = gate_clk_ctl1 & gate_clk_ctl2;\r
+        assign  gate_clk = gate_clk_ctl ? hclk:pc_clk;\r
+        assign  mux_dout = tstl_regs ? us_rdata:hdataout;\r
+\r
+        assign  tstl_regs = (reg_di[17:6] == 12'h200) ? 1'b1:1'b0;\r
+\r
+        assign  us_size[1:0] = SIZE;\r
+        assign  pc_retry = 1'b0;\r
+        assign  timeout = (timeout_cnt[8:0] == 9'h000) ? 1'b1:1'b0;\r
+        assign  orc_ack = (!hready_n | us_ack);\r
+\r
+\r
+        //-------------------------------------------------------------------\r
+        // Pipeline pc_ready and orc_ack and\r
+        // Edge detector for pc_ready signal - generates a one clk wide\r
+        // "pc_rdy_pulse" on a L->H transition of pc_ready\r
+        //-------------------------------------------------------------------\r
+        always @(posedge hclk or negedge reset_n) begin\r
+          if (~reset_n) begin\r
+                pc_ready_1d <= #1 1'b0;\r
+                pc_ready_2d <= #1 1'b0;\r
+                pc_ready_3d <= #1 1'b0;\r
+                orc_ack_1d <= #1 1'b0;\r
+                orc_ack_2d <= #1 1'b0;\r
+                orc_ack_3d <= #1 1'b0;\r
+                pc_rdy_pulse <= #1 1'b0;\r
+          end\r
+          else begin\r
+                pc_ready_1d <= #1 pc_ready;\r
+                pc_ready_2d <= #1 pc_ready_1d;\r
+                pc_ready_3d <= #1 pc_ready_2d;\r
+                orc_ack_1d <= #1 orc_ack;\r
+                orc_ack_2d <= #1 orc_ack_1d;\r
+                orc_ack_3d <= #1 orc_ack_2d;\r
+                pc_rdy_pulse <= (~pc_ready_3d & pc_ready_2d);\r
+          end // else\r
+        end // always\r
+\r
+\r
+       // ---------------------------------------------------------------------------\r
+        // gclk gate control2 on falling edge to prevent runt \r
+       // ---------------------------------------------------------------------------\r
+        always @(negedge hclk or negedge reset_n) begin\r
+          if (~reset_n) begin\r
+                gate_clk_ctl2 <= #1 1'b1;\r
+          end\r
+          else begin\r
+                gate_clk_ctl2 <= #1 !orc_ack_1d;\r
+          end\r
+        end // always\r
+\r
+       // ---------------------------------------------------------------------------\r
+        // shift reg - sreg_di - shift data and address in\r
+       // ---------------------------------------------------------------------------\r
+        always @(negedge pc_clk or negedge reset_n) begin\r
+          if (~reset_n) begin\r
+            sreg_di[25:0] <= #1 26'h0000000;\r
+          end\r
+          else begin\r
+             sreg_di <= sreg_di << 1;  // Shift Left\r
+             sreg_di[0] <= pc_datain;\r
+          end\r
+        end // always\r
+\r
+        //-------------------------------------------------------------------\r
+       // Latch data and address into internal reg clocked by hclk\r
+        //-------------------------------------------------------------------\r
+        always @(posedge hclk or negedge reset_n) begin\r
+          if (~reset_n) begin\r
+                reg_di[25:0] <= #1 26'h0000000;\r
+          end\r
+          else begin\r
+               if (pc_rdy_pulse) begin\r
+                  reg_di[25:0] <= #1 sreg_di[25:0];\r
+                end\r
+          end // else\r
+        end // always\r
+\r
+        assign us_wdata[7] = reg_di[18];\r
+        assign us_wdata[6] = reg_di[19];\r
+        assign us_wdata[5] = reg_di[20];\r
+        assign us_wdata[4] = reg_di[21];\r
+        assign us_wdata[3] = reg_di[22];\r
+        assign us_wdata[2] = reg_di[23];\r
+        assign us_wdata[1] = reg_di[24];\r
+        assign us_wdata[0] = reg_di[25];\r
+\r
+        assign hdatain[7]  = reg_di[18];\r
+        assign hdatain[6]  = reg_di[19];\r
+        assign hdatain[5]  = reg_di[20];\r
+        assign hdatain[4]  = reg_di[21];\r
+        assign hdatain[3]  = reg_di[22];\r
+        assign hdatain[2]  = reg_di[23];\r
+        assign hdatain[1]  = reg_di[24];\r
+        assign hdatain[0]  = reg_di[25];\r
+\r
+        assign haddr[7:0]    = reg_di[7:0];\r
+        assign us_addr[17:0] = reg_di[17:0];\r
+\r
+\r
+       // ---------------------------------------------------------------------------\r
+       // Latch output read data to 8 bit shift reg - sreg_do  \r
+       // ---------------------------------------------------------------------------\r
+        always @(negedge gate_clk or negedge reset_n) begin\r
+          if (~reset_n) begin\r
+            sreg_do[7:0] <= #1 8'h00;\r
+           pc_dataout <= #1 1'b0;\r
+          end\r
+          else begin\r
+           if (orc_ack_1d) begin\r
+             sreg_do[7:0] <= mux_dout[7:0];\r
+            end\r
+            else begin\r
+             sreg_do <= sreg_do >> 1; // shift Left \r
+             sreg_do[7] <= 1;\r
+            end\r
+          pc_dataout <= sreg_do[0];\r
+          end\r
+        end // always\r
+\r
+       \r
+       // ---------------------------------------------------------------------------\r
+\r
+\r
+       // ---------------------------------------------------------------------------\r
+       // Read/Write FSM \r
+       // ---------------------------------------------------------------------------\r
+\r
+        always @(posedge hclk or negedge reset_n) begin\r
+          if (~reset_n) begin\r
+            rdwr_st <= #1 IDLE;\r
+           gate_clk_ctl1 <= #1 1'b0;\r
+           us_rdy <= #1 1'b0;\r
+           us_wr <= #1 1'b0;\r
+            hcs_n <= #1 1'b1;\r
+            hread_n <= #1 1'b1;\r
+            hwrite_n <= #1 1'b1;\r
+            pc_ack <= #1 1'b0;\r
+            pc_error <= #1 1'b0;\r
+            timeout_cnt <= #1 9'h1ff;\r
+          end\r
+          else begin\r
+               // default values\r
+               us_rdy <= #1 1'b0;\r
+\r
+               case (rdwr_st)\r
+\r
+                       IDLE:\r
+                            begin\r
+                               us_wr <= #1 1'b0;\r
+                               hcs_n <= #1 1'b1;\r
+                               hread_n <= #1 1'b1;\r
+                               hwrite_n <= #1 1'b1;\r
+                               gate_clk_ctl1 <= #1 1'b0;\r
+                               timeout_cnt <= #1 9'h1ff;\r
+                               pc_ack <= #1 1'b0;\r
+                               pc_error <= #1 1'b0;\r
+\r
+                               if (pc_rdy_pulse) begin\r
+                                  if (pc_datain == 1'b0) begin // Write\r
+                                    rdwr_st <= #1 WRITE;\r
+                                  end\r
+                                  else begin // read\r
+                                    rdwr_st <= #1 READ;\r
+                                    gate_clk_ctl1 <= #1 1'b1;\r
+                                  end\r
+                               end\r
+                            end\r
+                       READ:\r
+                            begin\r
+                               if (tstl_regs) begin\r
+                                 us_rdy <= #1 1'b1;\r
+                                 us_wr <= #1 1'b0;\r
+                               end\r
+                               else begin\r
+                                 hcs_n <= #1 1'b0;\r
+                                 hread_n <= #1 1'b0;\r
+                                 hwrite_n <= #1 1'b1;\r
+                               end\r
+\r
+                               rdwr_st <= #1 WAIT1;\r
+                            end\r
+                       WRITE:\r
+                            begin\r
+                               if (tstl_regs) begin\r
+                                 us_rdy <= #1 1'b1;\r
+                                 us_wr <= #1 1'b1;\r
+                               end\r
+                               else begin\r
+                                 hcs_n <= #1 1'b0;\r
+                                 hread_n <= #1 1'b1;\r
+                                 hwrite_n <= #1 1'b0;\r
+                               end\r
+\r
+                               rdwr_st <= #1 WAIT1;\r
+                            end\r
+                       WAIT1:\r
+                            begin\r
+                               // timeout_cnt <= #1 timeout_cnt - 1;\r
+                               // if (timeout) begin\r
+                               //     pc_ack <= #1 1'b1;\r
+                               //     pc_error <= #1 1'b1;\r
+                               //     rdwr_st <= #1 WAIT2;\r
+                               // end\r
+                               // else begin\r
+                                 if (orc_ack) begin\r
+                                   us_wr <= #1 1'b0;\r
+                                   hcs_n <= #1 1'b1;\r
+                                   hread_n <= #1 1'b1;\r
+                                   hwrite_n <= #1 1'b1;\r
+                                   pc_ack <= #1 1'b1;\r
+                                   rdwr_st <= #1 WAIT2;\r
+                                 end\r
+                               // end\r
+                            end\r
+                       WAIT2:\r
+                            begin\r
+                               gate_clk_ctl1 <= #1 1'b0;\r
+                               if (pc_ready_3d == 1'b0) begin\r
+                                 pc_ack <= #1 1'b0;\r
+                                 pc_error <= #1 1'b0;\r
+                                 rdwr_st <= #1 IDLE;\r
+                               end\r
+                            end\r
+                       default:\r
+                            begin\r
+                               rdwr_st <= #1 IDLE;\r
+                               gate_clk_ctl1 <= #1 1'b0;\r
+                               us_rdy <= #1 1'b0;\r
+                               us_wr <= #1 1'b0;\r
+                               hcs_n <= #1 1'b1;\r
+                               hread_n <= #1 1'b1;\r
+                               hwrite_n <= #1 1'b1;\r
+                               pc_ack <= #1 1'b0;\r
+                               pc_error <= #1 1'b0;\r
+                               timeout_cnt <= #1 9'h1ff;\r
+                            end\r
+               endcase \r
+          end\r
+        end // always \r
+\r
+\r
+endmodule // orcastra\r
+\r
+\r
+\r
+\r

diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/reg_intf.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/reg_intf.v
new file mode 100644 (file)
index 0000000..bbcbf9d
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/reg_intf.v
@@ -0,0 +1,1790 @@
+// ===========================================================================\r
+// Verilog module generated by IPexpress\r
+// Filename: reg_intf.v  \r
+// Copyright 2005 (c) Lattice Semiconductor Corporation. All rights reserved.\r
+// ===========================================================================\r
+\r
+\r
+//`timescale 1ns/100ps\r
+\r
+\r
+module reg_intf (\r
+        //----------------------\r
+        // inputs to Reg_intf\r
+        //----------------------\r
+       //\r
+        //************\r
+        // resets \r
+        //************\r
+        reset_n,\r
+        //************\r
+        // clocks \r
+        //************\r
+        hclk,\r
+        rxc_clk,\r
+        txc_clk,\r
+        //*******************\r
+        // USI related inputs\r
+       // (User Slave Interface)\r
+        //*******************\r
+        us_wdata,\r
+        us_rdy,\r
+        us_wr,\r
+        us_addr,\r
+        us_size,\r
+       //****************\r
+       // from tst_logic \r
+       //****************\r
+       rx_error_ri,\r
+       rx_fifo_error_ri,\r
+       tx_disfrm_ri,\r
+       tx_fifo_full_ri,\r
+        //*****************\r
+        //from MAC Stat intf  \r
+        //*****************\r
+       rx_stat_vec,\r
+       rx_stat_en,\r
+       tx_stat_vec,\r
+       tx_stat_en,\r
+        //*****************\r
+        //----------------------------\r
+        // outputs from Reg_intf \r
+        //----------------------------\r
+       //\r
+        //*****************\r
+        //to tst_logic \r
+        //*****************\r
+       pkt_add_swap_ri,\r
+       pkt_loop_enb_ri,\r
+       pkt_loop_clksel_ri,\r
+       phy_reset_n_ri,\r
+       tx_sndpaustim_ri,\r
+       tx_sndpausreq_ri,\r
+       tx_fifoctrl_ri,\r
+       rx_fifo_full_ri,\r
+       tx_fifo_empty_ri,\r
+       ignore_next_pkt_ri,\r
+       aff_thrhd,\r
+       afe_thrhd,\r
+        //********************\r
+        // usi related outputs\r
+        //********************\r
+        us_err,\r
+        us_irq,\r
+        us_ack,\r
+        us_rdata );\r
+\r
+\r
+\r
+//---------\r
+// INPUTS\r
+//---------\r
+//************\r
+// resets \r
+//************\r
+input reset_n;                         // system reset\r
+//************\r
+// clocks \r
+//************\r
+input hclk;\r
+input rxc_clk;\r
+input txc_clk;\r
+//****************\r
+input [1:0] us_size;                    // Transfer size 00-byte\r
+input us_rdy;                           // Active high ready respose from USI\r
+input [7:0] us_wdata;                  // register's input data from usi\r
+input us_wr;                            // write/read enable wr=high, read=low\r
+input [17:0] us_addr;                   // 18 bit address\r
+//***********\r
+// tst_logic \r
+//***********\r
+input rx_error_ri;\r
+input rx_fifo_error_ri;\r
+input tx_disfrm_ri;\r
+input tx_fifo_full_ri;\r
+//*****************\r
+//from MAC Stat intf  \r
+//*****************\r
+input [31:0] rx_stat_vec;\r
+input rx_stat_en;\r
+input [30:0] tx_stat_vec;\r
+input tx_stat_en;\r
+//*****************\r
+//----------------------------\r
+// outputs from Reg_intf\r
+//----------------------------\r
+//\r
+//*****************\r
+//to tst_logic\r
+//*****************\r
+output pkt_add_swap_ri;\r
+output pkt_loop_enb_ri;\r
+output pkt_loop_clksel_ri;\r
+output phy_reset_n_ri;\r
+output [15:0] tx_sndpaustim_ri;\r
+output tx_sndpausreq_ri;\r
+output tx_fifoctrl_ri;\r
+output rx_fifo_full_ri;\r
+output tx_fifo_empty_ri;\r
+output ignore_next_pkt_ri;\r
+output [8:0] aff_thrhd;\r
+output [8:0] afe_thrhd;\r
+//*************\r
+//usi related\r
+//*************\r
+output us_err;\r
+output us_irq;                          // active high interrupt out to mpu\r
+output us_ack;                          // active high acknowledge for reads and writes\r
+output [7:0] us_rdata;                  // register's output data to usi\r
+\r
+\r
+\r
+//-------------------\r
+// SIGNAL assignments\r
+//-------------------\r
+wire pkt_add_swap_ri;\r
+wire pkt_loop_enb_ri;\r
+wire pkt_loop_clksel_ri;\r
+wire phy_reset_n_ri;\r
+wire [15:0] tx_sndpaustim_ri;\r
+wire tx_sndpausreq_ri;\r
+wire tx_fifoctrl_ri;\r
+wire rx_fifo_full_ri;\r
+wire tx_fifo_empty_ri;\r
+wire ignore_next_pkt_ri;\r
+wire [8:0] aff_thrhd;\r
+wire [8:0] afe_thrhd;\r
+wire unused_ctl_0; // NOT USED\r
+wire unused_ctl_1; // NOT USED\r
+wire unused_ctl_2; // NOT USED\r
+wire unused_ctl_3; // NOT USED\r
+wire unused_ctl_4; // NOT USED\r
+\r
+reg us_rdy_f0;                         // Active high ready respose from USI pipelined once\r
+reg us_rdy_f1;                         // Active high ready respose from USI pipelined twice\r
+reg us_rdy_wide;                       // Active high ready respose from USI widened to 2 clks \r
+reg [7:0] us_wdata_f;                  // pipelined register's input data from usi\r
+reg [49:0] we;                         // register write enables-used for writes (only 9 used)\r
+reg [49:0] re;                         // register read enables-used for reads   \r
+reg [7:0] us_rdata;                    // register's output data to usi\r
+reg us_ack;                            // active high acknowledge for reads and writes\r
+reg [2:0] cntl_fsm_st;                 // control reg FSM states\r
+reg start_burst;                       // Start Burst signal (pulse) - NOT USED\r
+reg ram_rst;                           // reset the RAM signal (pulse) - NOT USED\r
+reg range_err;                         // Address Out of Range Error   \r
+\r
+wire size_err;                         // Data Size Error   \r
+wire us_err;                           // USI Error\r
+wire [7:0] verid_reg;                  // VERID reg always set to 8'ha0 \r
+wire [1:0]ram_rst_mode;                        // reset RAM mode signal 00 = null, 01 = dc/idle rdy low,\r
+wire us_irq;                           // active high interrupt out to mpu\r
+\r
+\r
+// -----------------------------\r
+// General Registers\r
+// -----------------------------\r
+reg [7:0] tstcntl_reg;                 // Test Control Register  \r
+reg [7:0] tstcntl2_reg;                        // Test Control Register 2 - NOT USED  \r
+reg [7:0] maccntl_reg;                 // MAC control Register  \r
+reg [7:0] paustmrl_reg;                        // Pause timer register low byte\r
+reg [7:0] paustmrh_reg;                        // Pause timer register high byte\r
+reg [7:0] fifoaftl_reg;                        // FIFO Almost full Threshold register low byte \r
+reg [7:0] fifoafth_reg;                        // FIFO Almost full Threshold register high byte \r
+reg [7:0] fifoaetl_reg;                        // FIFO Almost Empty Threshold register low byte \r
+reg [7:0] fifoaeth_reg;                        // FIFO Almost Empty Threshold register high byte \r
+reg [7:0] rxstatus_reg;                        // RX Status Register  \r
+reg [7:0] txstatus_reg;                        // TX Status Register  \r
+\r
+// -----------------------------\r
+// Statistics Counters Registers\r
+// -----------------------------\r
+reg [15:0] rxpicnt_reg;                        // Rx packets ignored counter\r
+reg [15:0] rxlcecnt_reg;               // Rx length check error counter\r
+reg [15:0] rxlfcnt_reg;                        // Rx long frames counter\r
+reg [15:0] rxsfcnt_reg;                        // Rx short frames counter\r
+reg [15:0] rxipgcnt_reg;               // Rx ipg violations counter\r
+reg [15:0] rxcrccnt_reg;               // Rx crc errors counter\r
+reg [15:0] rxokcnt_reg;                        // Rx ok packets counter\r
+reg [15:0] rxcfcnt_reg;                        // Rx control frames counter\r
+reg [15:0] rxpfcnt_reg;                        // Rx pause frames counter\r
+reg [15:0] rxmfcnt_reg;                        // Rx Multicast frames counter\r
+reg [15:0] rxbfcnt_reg;                        // Rx broadcast frames counter\r
+reg [15:0] rxvfcnt_reg;                        // Rx vlan tagged frames counter\r
+\r
+reg [15:0] txufcnt_reg;                        // Tx unicast frames counter\r
+reg [15:0] txpfcnt_reg;                // Tx pause frames counter\r
+reg [15:0] txmfcnt_reg;                        // Tx Multicast frames counter\r
+reg [15:0] txbfcnt_reg;                        // Tx broadcast frames counter\r
+reg [15:0] txvfcnt_reg;                        // Tx vlan tagged frames counter\r
+reg [15:0] txbfccnt_reg;               // Tx bad FCS frames counter\r
+reg [15:0] txjfcnt_reg;                        // Tx jumbo frames counter\r
+\r
+\r
+reg re10_dly;                          // re[10] pipelined once\r
+reg re11_dly;                          // re[11] pipelined once\r
+reg re12_dly;                          // re[12] pipelined once\r
+reg re14_dly;                          // re[14] pipelined once\r
+reg re16_dly;                          // re[16] pipelined once\r
+reg re18_dly;                          // re[18] pipelined once\r
+reg re20_dly;                          // re[20] pipelined once\r
+reg re22_dly;                          // re[22] pipelined once\r
+reg re24_dly;                          // re[24] pipelined once\r
+reg re26_dly;                          // re[26] pipelined once\r
+reg re28_dly;                          // re[28] pipelined once\r
+reg re30_dly;                          // re[30] pipelined once\r
+reg re32_dly;                          // re[32] pipelined once\r
+reg re34_dly;                          // re[34] pipelined once\r
+reg re36_dly;                          // re[36] pipelined once\r
+reg re38_dly;                          // re[38] pipelined once\r
+reg re40_dly;                          // re[40] pipelined once\r
+reg re42_dly;                          // re[42] pipelined once\r
+reg re44_dly;                          // re[44] pipelined once\r
+reg re46_dly;                          // re[46] pipelined once\r
+reg re48_dly;                          // re[48] pipelined once\r
+reg clear_delay;                       // Clear the clear on read bit\r
+reg [6:0]  clear_count;                        // Counter used to generate clear_delay bit\r
+\r
+\r
+//--------------------------\r
+// dbus0 related\r
+//--------------------------\r
+wire [7:0] reg0_tdrive0_data;\r
+wire [7:0] reg1_tdrive0_data;\r
+wire [7:0] reg2_tdrive0_data;\r
+wire [7:0] reg3_tdrive0_data;\r
+wire [7:0] reg4_tdrive0_data;\r
+wire [7:0] reg5_tdrive0_data;\r
+wire [7:0] reg6_tdrive0_data;\r
+wire [7:0] reg7_tdrive0_data;\r
+wire [7:0] reg8_tdrive0_data;\r
+wire [7:0] reg9_tdrive0_data;\r
+wire [7:0] reg10_tdrive0_data;\r
+wire [7:0] reg11_tdrive0_data;\r
+wire [7:0] buskeep0_tdrive0_data;\r
+wire  reg0_tdrive0_en;\r
+wire  reg1_tdrive0_en;\r
+wire  reg2_tdrive0_en;\r
+wire  reg3_tdrive0_en;\r
+wire  reg4_tdrive0_en;\r
+wire  reg5_tdrive0_en;\r
+wire  reg6_tdrive0_en;\r
+wire  reg7_tdrive0_en;\r
+wire  reg8_tdrive0_en;\r
+wire  reg9_tdrive0_en;\r
+wire  reg10_tdrive0_en;\r
+wire  reg11_tdrive0_en;\r
+wire  buskeep0_tdrive0_en;\r
+//--------------------------\r
+\r
+//--------------------------\r
+// dbus1 related\r
+//--------------------------\r
+wire [7:0] reg12_tdrive1_data;\r
+wire [7:0] reg13_tdrive1_data;\r
+wire [7:0] reg14_tdrive1_data;\r
+wire [7:0] reg15_tdrive1_data;\r
+wire [7:0] reg16_tdrive1_data;\r
+wire [7:0] reg17_tdrive1_data;\r
+wire [7:0] reg18_tdrive1_data;\r
+wire [7:0] reg19_tdrive1_data;\r
+wire [7:0] reg20_tdrive1_data;\r
+wire [7:0] reg21_tdrive1_data;\r
+wire [7:0] reg22_tdrive1_data;\r
+wire [7:0] reg23_tdrive1_data;\r
+wire [7:0] buskeep1_tdrive1_data;\r
+wire  reg12_tdrive1_en;\r
+wire  reg13_tdrive1_en;\r
+wire  reg14_tdrive1_en;\r
+wire  reg15_tdrive1_en;\r
+wire  reg16_tdrive1_en;\r
+wire  reg17_tdrive1_en;\r
+wire  reg18_tdrive1_en;\r
+wire  reg19_tdrive1_en;\r
+wire  reg20_tdrive1_en;\r
+wire  reg21_tdrive1_en;\r
+wire  reg22_tdrive1_en;\r
+wire  reg23_tdrive1_en;\r
+wire  buskeep1_tdrive1_en;\r
+//--------------------------\r
+\r
+//--------------------------\r
+// dbus2 related\r
+//--------------------------\r
+wire [7:0] reg24_tdrive2_data;\r
+wire [7:0] reg25_tdrive2_data;\r
+wire [7:0] reg26_tdrive2_data;\r
+wire [7:0] reg27_tdrive2_data;\r
+wire [7:0] reg28_tdrive2_data;\r
+wire [7:0] reg29_tdrive2_data;\r
+wire [7:0] reg30_tdrive2_data;\r
+wire [7:0] reg31_tdrive2_data;\r
+wire [7:0] reg32_tdrive2_data;\r
+wire [7:0] reg33_tdrive2_data;\r
+wire [7:0] reg34_tdrive2_data;\r
+wire [7:0] reg35_tdrive2_data;\r
+wire [7:0] buskeep2_tdrive2_data;\r
+wire  reg24_tdrive2_en;\r
+wire  reg25_tdrive2_en;\r
+wire  reg26_tdrive2_en;\r
+wire  reg27_tdrive2_en;\r
+wire  reg28_tdrive2_en;\r
+wire  reg29_tdrive2_en;\r
+wire  reg30_tdrive2_en;\r
+wire  reg31_tdrive2_en;\r
+wire  reg32_tdrive2_en;\r
+wire  reg33_tdrive2_en;\r
+wire  reg34_tdrive2_en;\r
+wire  reg35_tdrive2_en;\r
+wire  buskeep2_tdrive2_en;\r
+//--------------------------\r
+\r
+//--------------------------\r
+// dbus3 related\r
+//--------------------------\r
+wire [7:0] reg36_tdrive3_data;\r
+wire [7:0] reg37_tdrive3_data;\r
+wire [7:0] reg38_tdrive3_data;\r
+wire [7:0] reg39_tdrive3_data;\r
+wire [7:0] reg40_tdrive3_data;\r
+wire [7:0] reg41_tdrive3_data;\r
+wire [7:0] reg42_tdrive3_data;\r
+wire [7:0] reg43_tdrive3_data;\r
+wire [7:0] reg44_tdrive3_data;\r
+wire [7:0] reg45_tdrive3_data;\r
+wire [7:0] reg46_tdrive3_data;\r
+wire [7:0] reg47_tdrive3_data;\r
+wire [7:0] reg48_tdrive3_data;\r
+wire [7:0] reg49_tdrive3_data;\r
+wire [7:0] buskeep3_tdrive3_data;\r
+wire  reg36_tdrive3_en;\r
+wire  reg37_tdrive3_en;\r
+wire  reg38_tdrive3_en;\r
+wire  reg39_tdrive3_en;\r
+wire  reg40_tdrive3_en;\r
+wire  reg41_tdrive3_en;\r
+wire  reg42_tdrive3_en;\r
+wire  reg43_tdrive3_en;\r
+wire  reg44_tdrive3_en;\r
+wire  reg45_tdrive3_en;\r
+wire  reg46_tdrive3_en;\r
+wire  reg47_tdrive3_en;\r
+wire  reg48_tdrive3_en;\r
+wire  reg49_tdrive3_en;\r
+wire  buskeep3_tdrive3_en;\r
+ \r
+\r
+\r
+wire [7:0] keep0;              // bus keeper values for tdrive0 \r
+wire [7:0] keep1;              // bus keeper values for tdrive1 \r
+wire [7:0] keep2;              // bus keeper values for tdrive2\r
+wire [7:0] keep3;              // bus keeper values for tdrive3\r
+ \r
+wire bkenb0;                   // bus keeper enable for tdrive0 \r
+wire bkenb1;                   // bus keeper enable for tdrive1 \r
+wire bkenb2;                   // bus keeper enable for tdrive2 \r
+wire bkenb3;                   // bus keeper enable for tdrive3 \r
+\r
+wire [3:0] grpsel;             // group select sigs used by add decoder sel between dbus0-dbus3 \r
+\r
+reg [7:0] dbus;                        // register's output data to usi \r
+tri [7:0] dbus0;                // data bus 0\r
+tri [7:0] dbus1;                // data bus 1\r
+tri [7:0] dbus2;                // data bus 2\r
+tri [7:0] dbus3;                // data bus 3\r
+\r
+wire us_clk;                   // tied to hclk\r
+\r
+// PARAMETERS\r
+\r
+parameter [1:0]\r
+        SIZE = 2'b00;          // Size for byte transfers\r
+\r
+parameter [7:0]\r
+        VERID = 8'ha2;\r
+\r
+parameter [1:0]\r
+       IDLE = 2'b00,           // IDLE State\r
+       DELAY = 2'b01,          // DELAY State\r
+       PULSE1 = 2'b10,         // PULSE1 State\r
+       PULSE2 = 2'b11;         // PULSE2 State\r
+\r
+\r
+       assign us_clk = hclk;\r
+       assign us_irq = 1'b0;\r
+\r
+        assign  size_err = (us_size[1:0] != SIZE) ? 1'b1:1'b0;\r
+        assign  us_err = (size_err || range_err) ? 1'b1:1'b0;\r
+\r
+\r
+        // -------------------------------------------\r
+        // generate grpsel signals for address decoder\r
+        // -------------------------------------------\r
+\r
+        assign grpsel[0] = (re[0] | re[1] | re[2] | re[3] | re[4] | re[5] | re[6] |\r
+                            re[7] | re[8] | re[9] | re[10] | re[11]);\r
+\r
+        assign grpsel[1] = (re[12] | re[13] | re[14] | re[15] | re[16] | re[17] | \r
+                            re[18] | re[19] | re[20] | re[21] | re[22] | re[23]);\r
+\r
+        assign grpsel[2] = (re[24] | re[25] | re[26] | re[27] | re[28] | re[29] | \r
+                            re[30] | re[31] | re[32] | re[33] | re[34] | re[35]);\r
+\r
+        assign grpsel[3] = (re[36] | re[37] | re[38] | re[39] | re[40] | re[41] | re[42] |\r
+                            re[43] | re[44] | re[45] | re[46] | re[47] | re[48] | re[49]);\r
+\r
+        // set bus keeper signals to high state\r
+\r
+        assign keep0 =  8'b11111111;\r
+        assign keep1 =  8'b11111111;\r
+        assign keep2 =  8'b11111111;\r
+        assign keep3 =  8'b11111111;\r
+\r
+        // decode bus keeper enable signals\r
+\r
+        assign bkenb0 =  !grpsel[0];\r
+        assign bkenb1 =  !grpsel[1];\r
+        assign bkenb2 =  !grpsel[2];\r
+        assign bkenb3 =  !grpsel[3];\r
+\r
+\r
+        // --------------------------\r
+        // mux selected Register bank\r
+        // --------------------------\r
+\r
+        always @(grpsel[3:0] or dbus0 or dbus1 or dbus2 or dbus3)\r
+        begin\r
+           if (grpsel[0]) begin\r
+                dbus <=  dbus0;\r
+           end\r
+           else if (grpsel[1]) begin\r
+                dbus <=  dbus1;\r
+           end\r
+           else if (grpsel[2]) begin\r
+                dbus <=  dbus2;\r
+           end\r
+           else if (grpsel[3]) begin\r
+                dbus <=  dbus3;\r
+           end\r
+           else\r
+                dbus <=  8'hff;\r
+        end\r
+        // --------------------------\r
+\r
+\r
+\r
+       // Latch register output to us_rdata usi port \r
+       // ---------------------------------------------------------------------------\r
+        always @(posedge us_clk or negedge reset_n) begin\r
+          if (~reset_n) begin\r
+            us_rdata[7:0] <= #1 8'hff;\r
+          end\r
+          else begin\r
+           if (us_rdy_wide && !us_wr) begin\r
+             us_rdata[7:0] <= dbus[7:0];\r
+            end\r
+          end\r
+        end // always\r
+       \r
+       // ---------------------------------------------------------------------------\r
+\r
+\r
+\r
+       // ========================================\r
+       // Register outs - wire assignments\r
+       // ========================================\r
+       \r
+       // ---------------------------------------\r
+       // VERID\r
+       // ---------------------------------------\r
+       assign verid_reg = VERID;\r
+       \r
+       // ---------------------------------------\r
+       // TSTCNTL\r
+       // ---------------------------------------\r
+        assign pkt_add_swap_ri = tstcntl_reg[0];\r
+        assign pkt_loop_enb_ri = tstcntl_reg[1];\r
+        assign phy_reset_n_ri  = tstcntl_reg[2];\r
+        assign pkt_loop_clksel_ri = tstcntl_reg[3];\r
+\r
+       \r
+       // ---------------------------------------\r
+       // SMCNTL\r
+       // ---------------------------------------\r
+       assign unused_ctl_0 = tstcntl2_reg[0];\r
+       assign unused_ctl_1 = tstcntl2_reg[1];\r
+       assign unused_ctl_2 = tstcntl2_reg[2];\r
+       assign unused_ctl_3 = tstcntl2_reg[3];\r
+       assign unused_ctl_4 = tstcntl2_reg[4];\r
+\r
+       // ---------------------------------------\r
+       // MACCNTL\r
+       // ---------------------------------------\r
+       assign tx_sndpausreq_ri = maccntl_reg[0];\r
+       assign tx_fifoctrl_ri = maccntl_reg[1];\r
+       assign rx_fifo_full_ri = maccntl_reg[2];\r
+       assign tx_fifo_empty_ri = maccntl_reg[3];\r
+       assign ignore_next_pkt_ri = maccntl_reg[4];\r
+\r
+       // ---------------------------------------\r
+       // PAUSTMRL\r
+       // ---------------------------------------\r
+       assign tx_sndpaustim_ri[0] = paustmrl_reg[0];\r
+       assign tx_sndpaustim_ri[1] = paustmrl_reg[1];\r
+       assign tx_sndpaustim_ri[2] = paustmrl_reg[2];\r
+       assign tx_sndpaustim_ri[3] = paustmrl_reg[3];\r
+       assign tx_sndpaustim_ri[4] = paustmrl_reg[4];\r
+       assign tx_sndpaustim_ri[5] = paustmrl_reg[5];\r
+       assign tx_sndpaustim_ri[6] = paustmrl_reg[6];\r
+       assign tx_sndpaustim_ri[7] = paustmrl_reg[7];\r
+       \r
+       // ---------------------------------------\r
+       // PAUSTMRH\r
+       // ---------------------------------------\r
+       assign tx_sndpaustim_ri[8] = paustmrh_reg[0];\r
+       assign tx_sndpaustim_ri[9] = paustmrh_reg[1];\r
+       assign tx_sndpaustim_ri[10] = paustmrh_reg[2];\r
+       assign tx_sndpaustim_ri[11] = paustmrh_reg[3];\r
+       assign tx_sndpaustim_ri[12] = paustmrh_reg[4];\r
+       assign tx_sndpaustim_ri[13] = paustmrh_reg[5];\r
+       assign tx_sndpaustim_ri[14] = paustmrh_reg[6];\r
+       assign tx_sndpaustim_ri[15] = paustmrh_reg[7];\r
+       \r
+       // ---------------------------------------\r
+       // FIFOAFTH and FIFOAETH\r
+       // ---------------------------------------\r
+       assign aff_thrhd[7:0] = fifoaftl_reg[7:0];\r
+       assign aff_thrhd[8] = fifoafth_reg[0];\r
+       assign afe_thrhd[7:0] = fifoaetl_reg[7:0];\r
+       assign afe_thrhd[8] = fifoaeth_reg[0];\r
+\r
+       // ---------------------------------------\r
+       // RXSTATUS and TXSTATUS\r
+       // ---------------------------------------\r
+       // RO bits out of reg - see code below\r
+       \r
+       // ---------------------------------------\r
+       // COUNTER REGISTERS\r
+       // ---------------------------------------\r
+       // RO bits out of reg - see code below\r
+       \r
+       // -----------------------------------------\r
+       // *****************************************\r
+       // assign register bits to output TS-drivers\r
+       // -----------------------------------------\r
+       // *****************************************\r
+\r
+       //----------------------------------------\r
+       // dbus0 related \r
+       //----------------------------------------\r
+        assign reg0_tdrive0_data =  verid_reg;\r
+        assign reg0_tdrive0_en =  re[0];\r
+\r
+        assign reg1_tdrive0_data =  tstcntl_reg;\r
+        assign reg1_tdrive0_en =  re[1];\r
+\r
+        assign reg2_tdrive0_data =  tstcntl2_reg;\r
+        assign reg2_tdrive0_en =  re[2];\r
+\r
+        assign reg3_tdrive0_data =  maccntl_reg;\r
+        assign reg3_tdrive0_en =  re[3];\r
+\r
+        assign reg4_tdrive0_data =  paustmrl_reg;\r
+        assign reg4_tdrive0_en =  re[4];\r
+\r
+        assign reg5_tdrive0_data =  paustmrh_reg;\r
+        assign reg5_tdrive0_en =  re[5];\r
+\r
+        assign reg6_tdrive0_data =  fifoaftl_reg;\r
+        assign reg6_tdrive0_en =  re[6];\r
+\r
+        assign reg7_tdrive0_data =  fifoafth_reg;\r
+        assign reg7_tdrive0_en =  re[7];\r
+\r
+        assign reg8_tdrive0_data =  fifoaetl_reg;\r
+        assign reg8_tdrive0_en =  re[8];\r
+\r
+        assign reg9_tdrive0_data =  fifoaeth_reg;\r
+        assign reg9_tdrive0_en =  re[9];\r
+\r
+        assign reg10_tdrive0_data =  rxstatus_reg;\r
+        assign reg10_tdrive0_en =  re[10];\r
+\r
+        assign reg11_tdrive0_data =  txstatus_reg;\r
+        assign reg11_tdrive0_en =  re[11];\r
+\r
+        assign buskeep0_tdrive0_data =  keep0;\r
+        assign buskeep0_tdrive0_en =  bkenb0;\r
+       //----------------------------------------\r
+\r
+        //----------------------------------------\r
+        // dbus1 related\r
+        //----------------------------------------\r
+        assign reg12_tdrive1_data =  rxpicnt_reg[7:0];\r
+        assign reg12_tdrive1_en =  re[12];\r
+\r
+        assign reg13_tdrive1_data =  rxpicnt_reg[15:8];\r
+        assign reg13_tdrive1_en =  re[13];\r
+\r
+        assign reg14_tdrive1_data =  rxlcecnt_reg[7:0];\r
+        assign reg14_tdrive1_en =  re[14];\r
+\r
+        assign reg15_tdrive1_data =  rxlcecnt_reg[15:8];\r
+        assign reg15_tdrive1_en =  re[15];\r
+\r
+        assign reg16_tdrive1_data =  rxlfcnt_reg[7:0];\r
+        assign reg16_tdrive1_en =  re[16];\r
+\r
+        assign reg17_tdrive1_data =  rxlfcnt_reg[15:8];\r
+        assign reg17_tdrive1_en =  re[17];\r
+\r
+        assign reg18_tdrive1_data =  rxsfcnt_reg[7:0];\r
+        assign reg18_tdrive1_en =  re[18];\r
+\r
+        assign reg19_tdrive1_data =  rxsfcnt_reg[15:8];\r
+        assign reg19_tdrive1_en =  re[19];\r
+\r
+        assign reg20_tdrive1_data =  rxipgcnt_reg[7:0];\r
+        assign reg20_tdrive1_en =  re[20];\r
+\r
+        assign reg21_tdrive1_data =  rxipgcnt_reg[15:8];\r
+        assign reg21_tdrive1_en =  re[21];\r
+\r
+        assign reg22_tdrive1_data =  rxcrccnt_reg[7:0];\r
+        assign reg22_tdrive1_en =  re[22];\r
+\r
+        assign reg23_tdrive1_data =  rxcrccnt_reg[15:8];\r
+        assign reg23_tdrive1_en =  re[23];\r
+\r
+        assign buskeep1_tdrive1_data =  keep1;\r
+        assign buskeep1_tdrive1_en =  bkenb1;\r
+        //----------------------------------------\r
+\r
+        //----------------------------------------\r
+        // dbus2 related\r
+        //----------------------------------------\r
+        assign reg24_tdrive2_data =  rxokcnt_reg[7:0];\r
+        assign reg24_tdrive2_en =  re[24];\r
+\r
+        assign reg25_tdrive2_data =  rxokcnt_reg[15:8];\r
+        assign reg25_tdrive2_en =  re[25];\r
+\r
+        assign reg26_tdrive2_data =  rxcfcnt_reg[7:0];\r
+        assign reg26_tdrive2_en =  re[26];\r
+\r
+        assign reg27_tdrive2_data =  rxcfcnt_reg[15:8];\r
+        assign reg27_tdrive2_en =  re[27];\r
+\r
+        assign reg28_tdrive2_data =  rxpfcnt_reg[7:0];\r
+        assign reg28_tdrive2_en =  re[28];\r
+\r
+        assign reg29_tdrive2_data =  rxpfcnt_reg[15:8];\r
+        assign reg29_tdrive2_en =  re[29];\r
+\r
+        assign reg30_tdrive2_data =  rxmfcnt_reg[7:0];\r
+        assign reg30_tdrive2_en =  re[30];\r
+\r
+        assign reg31_tdrive2_data =  rxmfcnt_reg[15:8];\r
+        assign reg31_tdrive2_en =  re[31];\r
+\r
+        assign reg32_tdrive2_data =  rxbfcnt_reg[7:0];\r
+        assign reg32_tdrive2_en =  re[32];\r
+\r
+        assign reg33_tdrive2_data =  rxbfcnt_reg[15:8];\r
+        assign reg33_tdrive2_en =  re[33];\r
+\r
+        assign reg34_tdrive2_data =  rxvfcnt_reg[7:0];\r
+        assign reg34_tdrive2_en =  re[34];\r
+\r
+        assign reg35_tdrive2_data =  rxvfcnt_reg[15:8];\r
+        assign reg35_tdrive2_en =  re[35];\r
+\r
+        assign buskeep2_tdrive2_data =  keep2;\r
+        assign buskeep2_tdrive2_en =  bkenb2;\r
+        //----------------------------------------\r
+\r
+\r
+        //----------------------------------------\r
+        // dbus3 related\r
+        //----------------------------------------\r
+        assign reg36_tdrive3_data =  txufcnt_reg[7:0];\r
+        assign reg36_tdrive3_en =  re[36];\r
+\r
+        assign reg37_tdrive3_data =  txufcnt_reg[15:8];\r
+        assign reg37_tdrive3_en =  re[37];\r
+\r
+        assign reg38_tdrive3_data =  txpfcnt_reg[7:0];\r
+        assign reg38_tdrive3_en =  re[38];\r
+\r
+        assign reg39_tdrive3_data =  txpfcnt_reg[15:8];\r
+        assign reg39_tdrive3_en =  re[39];\r
+\r
+        assign reg40_tdrive3_data =  txmfcnt_reg[7:0];\r
+        assign reg40_tdrive3_en =  re[40];\r
+\r
+        assign reg41_tdrive3_data =  txmfcnt_reg[15:8];\r
+        assign reg41_tdrive3_en =  re[41];\r
+\r
+        assign reg42_tdrive3_data =  txbfcnt_reg[7:0];\r
+        assign reg42_tdrive3_en =  re[42];\r
+\r
+        assign reg43_tdrive3_data =  txbfcnt_reg[15:8];\r
+        assign reg43_tdrive3_en =  re[43];\r
+\r
+        assign reg44_tdrive3_data =  txvfcnt_reg[7:0];\r
+        assign reg44_tdrive3_en =  re[44];\r
+\r
+        assign reg45_tdrive3_data =  txvfcnt_reg[15:8];\r
+        assign reg45_tdrive3_en =  re[45];\r
+\r
+        assign reg46_tdrive3_data =  txbfccnt_reg[7:0];\r
+        assign reg46_tdrive3_en =  re[46];\r
+\r
+        assign reg47_tdrive3_data =  txbfccnt_reg[15:8];\r
+        assign reg47_tdrive3_en =  re[47];\r
+\r
+        assign reg48_tdrive3_data =  txjfcnt_reg[7:0];\r
+        assign reg48_tdrive3_en =  re[48];\r
+\r
+        assign reg49_tdrive3_data =  txjfcnt_reg[15:8];\r
+        assign reg49_tdrive3_en =  re[49];\r
+\r
+        assign buskeep3_tdrive3_data =  keep3;\r
+        assign buskeep3_tdrive3_en =  bkenb3;\r
+        //----------------------------------------\r
+\r
+\r
+\r
+       // instantiate tristate drivers for each register's data Muxing\r
+       // -------------------------------------------------------------\r
+        assign  dbus0 = (reg0_tdrive0_en) ? reg0_tdrive0_data:8'bz;\r
+        assign  dbus0 = (reg1_tdrive0_en) ? reg1_tdrive0_data:8'bz;\r
+        assign  dbus0 = (reg2_tdrive0_en) ? reg2_tdrive0_data:8'bz;\r
+        assign  dbus0 = (reg3_tdrive0_en) ? reg3_tdrive0_data:8'bz;\r
+        assign  dbus0 = (reg4_tdrive0_en) ? reg4_tdrive0_data:8'bz;\r
+        assign  dbus0 = (reg5_tdrive0_en) ? reg5_tdrive0_data:8'bz;\r
+        assign  dbus0 = (reg6_tdrive0_en) ? reg6_tdrive0_data:8'bz;\r
+        assign  dbus0 = (reg7_tdrive0_en) ? reg7_tdrive0_data:8'bz;\r
+        assign  dbus0 = (reg8_tdrive0_en) ? reg8_tdrive0_data:8'bz;\r
+        assign  dbus0 = (reg9_tdrive0_en) ? reg9_tdrive0_data:8'bz;\r
+        assign  dbus0 = (reg10_tdrive0_en) ? reg10_tdrive0_data:8'bz;\r
+        assign  dbus0 = (reg11_tdrive0_en) ? reg11_tdrive0_data:8'bz;\r
+        assign  dbus0 = (buskeep0_tdrive0_en) ? buskeep0_tdrive0_data:8'bz;\r
+\r
+        // ----------------------------------------------------------------\r
+\r
+        assign  dbus1 = (reg12_tdrive1_en) ? reg12_tdrive1_data:8'bz;\r
+        assign  dbus1 = (reg13_tdrive1_en) ? reg13_tdrive1_data:8'bz;\r
+        assign  dbus1 = (reg14_tdrive1_en) ? reg14_tdrive1_data:8'bz;\r
+        assign  dbus1 = (reg15_tdrive1_en) ? reg15_tdrive1_data:8'bz;\r
+        assign  dbus1 = (reg16_tdrive1_en) ? reg16_tdrive1_data:8'bz;\r
+        assign  dbus1 = (reg17_tdrive1_en) ? reg17_tdrive1_data:8'bz;\r
+        assign  dbus1 = (reg18_tdrive1_en) ? reg18_tdrive1_data:8'bz;\r
+        assign  dbus1 = (reg19_tdrive1_en) ? reg19_tdrive1_data:8'bz;\r
+        assign  dbus1 = (reg20_tdrive1_en) ? reg20_tdrive1_data:8'bz;\r
+        assign  dbus1 = (reg21_tdrive1_en) ? reg21_tdrive1_data:8'bz;\r
+        assign  dbus1 = (reg22_tdrive1_en) ? reg22_tdrive1_data:8'bz;\r
+        assign  dbus1 = (reg23_tdrive1_en) ? reg23_tdrive1_data:8'bz;\r
+        assign  dbus1 = (buskeep1_tdrive1_en) ? buskeep1_tdrive1_data:8'bz;\r
+\r
+        // ----------------------------------------------------------------\r
+\r
+        assign  dbus2 = (reg24_tdrive2_en) ? reg24_tdrive2_data:8'bz;\r
+        assign  dbus2 = (reg25_tdrive2_en) ? reg25_tdrive2_data:8'bz;\r
+        assign  dbus2 = (reg26_tdrive2_en) ? reg26_tdrive2_data:8'bz;\r
+        assign  dbus2 = (reg27_tdrive2_en) ? reg27_tdrive2_data:8'bz;\r
+        assign  dbus2 = (reg28_tdrive2_en) ? reg28_tdrive2_data:8'bz;\r
+        assign  dbus2 = (reg29_tdrive2_en) ? reg29_tdrive2_data:8'bz;\r
+        assign  dbus2 = (reg30_tdrive2_en) ? reg30_tdrive2_data:8'bz;\r
+        assign  dbus2 = (reg31_tdrive2_en) ? reg31_tdrive2_data:8'bz;\r
+        assign  dbus2 = (reg32_tdrive2_en) ? reg32_tdrive2_data:8'bz;\r
+        assign  dbus2 = (reg33_tdrive2_en) ? reg33_tdrive2_data:8'bz;\r
+        assign  dbus2 = (reg34_tdrive2_en) ? reg34_tdrive2_data:8'bz;\r
+        assign  dbus2 = (reg35_tdrive2_en) ? reg35_tdrive2_data:8'bz;\r
+        assign  dbus2 = (buskeep2_tdrive2_en) ? buskeep2_tdrive2_data:8'bz;\r
+\r
+        // ----------------------------------------------------------------\r
+\r
+        assign  dbus3 = (reg36_tdrive3_en) ? reg36_tdrive3_data:8'bz;\r
+        assign  dbus3 = (reg37_tdrive3_en) ? reg37_tdrive3_data:8'bz;\r
+        assign  dbus3 = (reg38_tdrive3_en) ? reg38_tdrive3_data:8'bz;\r
+        assign  dbus3 = (reg39_tdrive3_en) ? reg39_tdrive3_data:8'bz;\r
+        assign  dbus3 = (reg40_tdrive3_en) ? reg40_tdrive3_data:8'bz;\r
+        assign  dbus3 = (reg41_tdrive3_en) ? reg41_tdrive3_data:8'bz;\r
+        assign  dbus3 = (reg42_tdrive3_en) ? reg42_tdrive3_data:8'bz;\r
+        assign  dbus3 = (reg43_tdrive3_en) ? reg43_tdrive3_data:8'bz;\r
+        assign  dbus3 = (reg44_tdrive3_en) ? reg44_tdrive3_data:8'bz;\r
+        assign  dbus3 = (reg45_tdrive3_en) ? reg45_tdrive3_data:8'bz;\r
+        assign  dbus3 = (reg46_tdrive3_en) ? reg46_tdrive3_data:8'bz;\r
+        assign  dbus3 = (reg47_tdrive3_en) ? reg47_tdrive3_data:8'bz;\r
+        assign  dbus3 = (reg48_tdrive3_en) ? reg48_tdrive3_data:8'bz;\r
+        assign  dbus3 = (reg49_tdrive3_en) ? reg49_tdrive3_data:8'bz;\r
+        assign  dbus3 = (buskeep3_tdrive3_en) ? buskeep3_tdrive3_data:8'bz;\r
+\r
+       // ----------------------------------------------------------------\r
+\r
+\r
+       // ---------------------------------------------------------------------------\r
+       // Stretch out us_rdy and Generate us_ack  \r
+       // us_ack - is just us_rdy pipelined three times and returned  \r
+       // ---------------------------------------------------------------------------\r
+        always @(posedge us_clk or negedge reset_n) begin\r
+          if (~reset_n) begin\r
+            us_rdy_f0 <= #1 1'b0;\r
+            us_rdy_f1 <= #1 1'b0;\r
+            us_ack <= #1 1'b0;\r
+            us_rdy_wide <= #1 1'b0;\r
+          end\r
+          else begin\r
+            us_rdy_f0 <= #1 us_rdy;\r
+            us_rdy_f1 <= #1 us_rdy_f0;\r
+           us_rdy_wide <= #1 (us_rdy_f0 | us_rdy_f1);\r
+            us_ack <= #1 us_rdy_f1;\r
+          end\r
+        end // always \r
+       // ---------------------------------------------------------------------------\r
+\r
+\r
+\r
+  // ---------------------------------------------------------------------------------\r
+  // *********************************************************************************\r
+  // ADDRESS DECODER\r
+  // ---------------------------------------------------------------------------------\r
+  // *********************************************************************************\r
+  always @(us_addr or us_wr or us_rdy_wide)\r
+    begin \r
+\r
+        // default assignment of we, and re signals\r
+        we <= 0;\r
+        re <= 0;\r
+       range_err <= 0;\r
+\r
+        if (us_rdy_wide == 1'b1) begin\r
+\r
+                  if (us_addr[17:6] == 12'h200) begin\r
+\r
+                case (us_addr[5:0])\r
+\r
+                        6'd0 : // VERID\r
+                            begin\r
+                                if (!us_wr)\r
+                                  re[0] <=  1;\r
+                                else \r
+                                  re[0] <=  0;\r
+                            end\r
+                        6'd1 : // TSTCNTL\r
+                            begin\r
+                                if (us_wr) begin\r
+                                  we[1] <=  1;\r
+                                  re[1] <=  0;\r
+                               end\r
+                                else  begin\r
+                                  we[1] <=  0;\r
+                                  re[1] <=  1;\r
+                               end\r
+                            end\r
+                        6'd2 : // TSTCNTL2\r
+                            begin\r
+                                if (us_wr) begin\r
+                                  we[2] <=  1;\r
+                                  re[2] <=  0;\r
+                               end\r
+                                else  begin\r
+                                  we[2] <=  0;\r
+                                  re[2] <=  1;\r
+                               end\r
+                            end\r
+                        6'd3 : // MACCNTL\r
+                            begin\r
+                                if (us_wr) begin\r
+                                  we[3] <=  1;\r
+                                  re[3] <=  0;\r
+                               end\r
+                                else  begin\r
+                                  we[3] <=  0;\r
+                                  re[3] <=  1;\r
+                               end\r
+                            end\r
+                        6'd4 : // PAUSTMRL\r
+                            begin\r
+                                if (us_wr) begin\r
+                                  we[4] <=  1;\r
+                                  re[4] <=  0;\r
+                               end\r
+                                else  begin\r
+                                  we[4] <=  0;\r
+                                  re[4] <=  1;\r
+                               end\r
+                            end\r
+                        6'd5 : // PAUSTMRH\r
+                            begin\r
+                                if (us_wr) begin\r
+                                  we[5] <=  1;\r
+                                  re[5] <=  0;\r
+                               end\r
+                                else  begin\r
+                                  we[5] <=  0;\r
+                                  re[5] <=  1;\r
+                               end\r
+                            end\r
+                        6'd6 : // FIFOAFTL\r
+                            begin\r
+                                if (us_wr) begin\r
+                                  we[6] <=  1;\r
+                                  re[6] <=  0;\r
+                               end\r
+                                else  begin\r
+                                  we[6] <=  0;\r
+                                  re[6] <=  1;\r
+                               end\r
+                            end\r
+                        6'd7 : // FIFOAFTH\r
+                            begin\r
+                                if (us_wr) begin\r
+                                  we[7] <=  1;\r
+                                  re[7] <=  0;\r
+                               end\r
+                                else  begin\r
+                                  we[7] <=  0;\r
+                                  re[7] <=  1;\r
+                               end\r
+                            end\r
+                        6'd8 : // FIFOAETL\r
+                            begin\r
+                                if (us_wr) begin\r
+                                  we[8] <=  1;\r
+                                  re[8] <=  0;\r
+                               end\r
+                                else  begin\r
+                                  we[8] <=  0;\r
+                                  re[8] <=  1;\r
+                               end\r
+                            end\r
+                        6'd9 : // FIFOAETH\r
+                            begin\r
+                                if (us_wr) begin\r
+                                  we[9] <=  1;\r
+                                  re[9] <=  0;\r
+                               end\r
+                                else  begin\r
+                                  we[9] <=  0;\r
+                                  re[9] <=  1;\r
+                               end\r
+                            end\r
+                        6'd10 : // RXSTATUS\r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[10] <=  1;\r
+                                else \r
+                                  re[10] <=  0;\r
+                            end\r
+                        6'd11 : // TXSTATUS \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[11] <=  1;\r
+                                else \r
+                                  re[11] <=  0;\r
+                            end\r
+                        6'd12 : // RXPICNT_L \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[12] <=  1;\r
+                                else \r
+                                  re[12] <=  0;\r
+                            end\r
+                        6'd13 : // RXPICNT_H \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[13] <=  1;\r
+                                else \r
+                                  re[13] <=  0;\r
+                            end\r
+                        6'd14 : // RXLCECNT_L \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[14] <=  1;\r
+                                else \r
+                                  re[14] <=  0;\r
+                            end\r
+                        6'd15 : // RXLCECNT_H \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[15] <=  1;\r
+                                else \r
+                                  re[15] <=  0;\r
+                            end\r
+                        6'd16 : // RXLFCNT_L \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[16] <=  1;\r
+                                else \r
+                                  re[16] <=  0;\r
+                            end\r
+                        6'd17 : // RXLFCNT_H \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[17] <=  1;\r
+                                else \r
+                                  re[17] <=  0;\r
+                            end\r
+                        6'd18 : // RXSFCNT_L \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[18] <=  1;\r
+                                else \r
+                                  re[18] <=  0;\r
+                            end\r
+                        6'd19 : // RXSFCNT_H \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[19] <=  1;\r
+                                else \r
+                                  re[19] <=  0;\r
+                            end\r
+                        6'd20 : // RXIPGFCNT_L \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[20] <=  1;\r
+                                else \r
+                                  re[20] <=  0;\r
+                            end\r
+                        6'd21 : // RXIPGFCNT_H \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[21] <=  1;\r
+                                else \r
+                                  re[21] <=  0;\r
+                            end\r
+                        6'd22 : // RXCRCCNT_L \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[22] <=  1;\r
+                                else \r
+                                  re[22] <=  0;\r
+                            end\r
+                        6'd23 : // RXCRCCNT_H \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[23] <=  1;\r
+                                else \r
+                                  re[23] <=  0;\r
+                            end\r
+                        6'd24 : // RXOKFCNT_L \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[24] <=  1;\r
+                                else \r
+                                  re[24] <=  0;\r
+                            end\r
+                        6'd25 : // RXOKFCNT_H \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[25] <=  1;\r
+                                else \r
+                                  re[25] <=  0;\r
+                            end\r
+                        6'd26 : // RXCFCNT_L \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[26] <=  1;\r
+                                else \r
+                                  re[26] <=  0;\r
+                            end\r
+                        6'd27 : // RXCFCNT_H \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[27] <=  1;\r
+                                else \r
+                                  re[27] <=  0;\r
+                            end\r
+                        6'd28 : // RXPFCNT_L \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[28] <=  1;\r
+                                else \r
+                                  re[28] <=  0;\r
+                            end\r
+                        6'd29 : // RXPFCNT_H \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[29] <=  1;\r
+                                else \r
+                                  re[29] <=  0;\r
+                            end\r
+                        6'd30 : // RXMFCNT_L \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[30] <=  1;\r
+                                else \r
+                                  re[30] <=  0;\r
+                            end\r
+                        6'd31 : // RXMFCNT_H \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[31] <=  1;\r
+                                else \r
+                                  re[31] <=  0;\r
+                            end\r
+                        6'd32 : // RXBFCNT_L \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[32] <=  1;\r
+                                else \r
+                                  re[32] <=  0;\r
+                            end\r
+                        6'd33 : // RXBFCNT_H \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[33] <=  1;\r
+                                else \r
+                                  re[33] <=  0;\r
+                            end\r
+                        6'd34 : // RXVFCNT_L \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[34] <=  1;\r
+                                else \r
+                                  re[34] <=  0;\r
+                            end\r
+                        6'd35 : // RXVFCNT_H \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[35] <=  1;\r
+                                else \r
+                                  re[35] <=  0;\r
+                            end\r
+                        6'd36 : // TXUFCNT_L \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[36] <=  1;\r
+                                else \r
+                                  re[36] <=  0;\r
+                            end\r
+                        6'd37 : // TXUFCNT_H \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[37] <=  1;\r
+                                else \r
+                                  re[37] <=  0;\r
+                            end\r
+                        6'd38 : // TXPFCNT_L \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[38] <=  1;\r
+                                else \r
+                                  re[38] <=  0;\r
+                            end\r
+                        6'd39 : // TXPFCNT_H \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[39] <=  1;\r
+                                else \r
+                                  re[39] <=  0;\r
+                            end\r
+                        6'd40 : // TXMFCNT_L \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[40] <=  1;\r
+                                else \r
+                                  re[40] <=  0;\r
+                            end\r
+                        6'd41 : // TXMFCNT_H \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[41] <=  1;\r
+                                else \r
+                                  re[41] <=  0;\r
+                            end\r
+                        6'd42 : // TXBFCNT_L \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[42] <=  1;\r
+                                else \r
+                                  re[42] <=  0;\r
+                            end\r
+                        6'd43 : // TXBFCNT_H \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[43] <=  1;\r
+                                else \r
+                                  re[43] <=  0;\r
+                            end\r
+                        6'd44 : // TXVFCNT_L \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[44] <=  1;\r
+                                else \r
+                                  re[44] <=  0;\r
+                            end\r
+                        6'd45 : // TXVFCNT_H \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[45] <=  1;\r
+                                else \r
+                                  re[45] <=  0;\r
+                            end\r
+                        6'd46 : // TXBFCCNT_L \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[46] <=  1;\r
+                                else \r
+                                  re[46] <=  0;\r
+                            end\r
+                        6'd47 : // TXBFCCNT_H \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[47] <=  1;\r
+                                else \r
+                                  re[47] <=  0;\r
+                            end\r
+                        6'd48 : // TXJFCNT_L \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[48] <=  1;\r
+                                else \r
+                                  re[48] <=  0;\r
+                            end\r
+                        6'd49 : // TXJFCNT_H \r
+                            begin\r
+                                if (!us_wr) \r
+                                  re[49] <=  1;\r
+                                else \r
+                                  re[49] <=  0;\r
+                            end\r
+\r
+                        default:\r
+                            begin\r
+                                re <=  0; \r
+                                we <=  0;\r
+                               range_err <= 1'b0;\r
+                            end\r
+\r
+                endcase\r
+\r
+           end // (us_addr[17:6] == 12'h2000) \r
+\r
+\r
+       end // (us_rdy == 1)\r
+\r
+        else begin // (us_rdy == 0) \r
+          we <= 0;\r
+          re <= 0;\r
+        end \r
+\r
+    end //always\r
+  // ---------------------------------------------------------------------------------\r
+  // *********************************************************************************\r
+\r
+\r
+       // ---------------------------------------------------------------------------\r
+       // Delay re[10] - re[48]  by 2 clks to use for Clear on Read \r
+       // ---------------------------------------------------------------------------\r
+        always @(posedge us_clk or negedge reset_n) begin\r
+          if (~reset_n) begin\r
+            re10_dly <= #1 1'b0;\r
+            re11_dly <= #1 1'b0;\r
+           re12_dly <= #1 1'b0;\r
+           re14_dly <= #1 1'b0;\r
+           re16_dly <= #1 1'b0;\r
+           re18_dly <= #1 1'b0;\r
+           re20_dly <= #1 1'b0;\r
+           re22_dly <= #1 1'b0;\r
+           re24_dly <= #1 1'b0;\r
+           re26_dly <= #1 1'b0;\r
+           re28_dly <= #1 1'b0;\r
+           re30_dly <= #1 1'b0;\r
+           re32_dly <= #1 1'b0;\r
+           re34_dly <= #1 1'b0;\r
+           re36_dly <= #1 1'b0;\r
+           re38_dly <= #1 1'b0;\r
+           re40_dly <= #1 1'b0;\r
+           re42_dly <= #1 1'b0;\r
+           re44_dly <= #1 1'b0;\r
+           re46_dly <= #1 1'b0;\r
+           re48_dly <= #1 1'b0;\r
+           clear_delay <= #1 1'b0;\r
+           clear_count <= #1 7'b0000000;\r
+          end\r
+          else begin\r
+           if (us_rdy_wide & !us_wr) begin\r
+               clear_count <= 127;\r
+           end else if (clear_count != 0) begin\r
+               clear_count <= clear_count - 1;\r
+           end\r
+\r
+           if (clear_count == 7'b0000001) begin\r
+              clear_delay <= 1;\r
+           end else begin\r
+              clear_delay <= 0;\r
+            end\r
+\r
+            if (re[10]) begin\r
+              re10_dly <= 1;\r
+           end else if (clear_delay) begin\r
+              re10_dly <= 0;\r
+           end\r
+\r
+            if (re[11]) begin\r
+              re11_dly <= 1;\r
+           end else if (clear_delay) begin\r
+              re11_dly <= 0;\r
+           end\r
+\r
+            if (re[12]) begin\r
+              re12_dly <= 1;\r
+           end else if (clear_delay) begin\r
+              re12_dly <= 0;\r
+           end\r
+\r
+            if (re[14]) begin\r
+              re14_dly <= 1;\r
+           end else if (clear_delay) begin\r
+              re14_dly <= 0;\r
+           end\r
+\r
+            if (re[16]) begin\r
+              re16_dly <= 1;\r
+           end else if (clear_delay) begin\r
+              re16_dly <= 0;\r
+           end\r
+\r
+            if (re[18]) begin\r
+              re18_dly <= 1;\r
+           end else if (clear_delay) begin\r
+              re18_dly <= 0;\r
+           end\r
+\r
+            if (re[20]) begin\r
+              re20_dly <= 1;\r
+           end else if (clear_delay) begin\r
+              re20_dly <= 0;\r
+           end\r
+\r
+            if (re[22]) begin\r
+              re22_dly <= 1;\r
+           end else if (clear_delay) begin\r
+              re22_dly <= 0;\r
+           end\r
+\r
+            if (re[24]) begin\r
+              re24_dly <= 1;\r
+           end else if (clear_delay) begin\r
+              re24_dly <= 0;\r
+           end\r
+\r
+            if (re[26]) begin\r
+              re26_dly <= 1;\r
+           end else if (clear_delay) begin\r
+              re26_dly <= 0;\r
+           end\r
+\r
+            if (re[28]) begin\r
+              re28_dly <= 1;\r
+           end else if (clear_delay) begin\r
+              re28_dly <= 0;\r
+           end\r
+\r
+            if (re[30]) begin\r
+              re30_dly <= 1;\r
+           end else if (clear_delay) begin\r
+              re30_dly <= 0;\r
+           end\r
+\r
+            if (re[32]) begin\r
+              re32_dly <= 1;\r
+           end else if (clear_delay) begin\r
+              re32_dly <= 0;\r
+           end\r
+\r
+            if (re[34]) begin\r
+              re34_dly <= 1;\r
+           end else if (clear_delay) begin\r
+              re34_dly <= 0;\r
+           end\r
+\r
+            if (re[36]) begin\r
+              re36_dly <= 1;\r
+           end else if (clear_delay) begin\r
+              re36_dly <= 0;\r
+           end\r
+\r
+            if (re[38]) begin\r
+              re38_dly <= 1;\r
+           end else if (clear_delay) begin\r
+              re38_dly <= 0;\r
+           end\r
+\r
+            if (re[40]) begin\r
+              re40_dly <= 1;\r
+           end else if (clear_delay) begin\r
+              re40_dly <= 0;\r
+           end\r
+\r
+            if (re[42]) begin\r
+              re42_dly <= 1;\r
+           end else if (clear_delay) begin\r
+              re42_dly <= 0;\r
+           end\r
+\r
+            if (re[44]) begin\r
+              re44_dly <= 1;\r
+           end else if (clear_delay) begin\r
+              re44_dly <= 0;\r
+           end\r
+\r
+            if (re[46]) begin\r
+              re46_dly <= 1;\r
+           end else if (clear_delay) begin\r
+              re46_dly <= 0;\r
+           end\r
+\r
+            if (re[48]) begin\r
+              re48_dly <= 1;\r
+           end else if (clear_delay) begin\r
+              re48_dly <= 0;\r
+           end\r
+          end\r
+        end // always \r
+\r
+\r
+  // ---------------------------------------------------------------------------------\r
+  // WRITE TO REGISTERS LOGIC\r
+  // ---------------------------------------------------------------------------------\r
+\r
+\r
+       // ---------------------------------------------------------------------------\r
+       // PIPELINE us_wdata\r
+       // ---------------------------------------------------------------------------\r
+        always @(posedge us_clk or negedge reset_n) begin\r
+          if (~reset_n) begin\r
+            us_wdata_f[7:0] <= #1 8'h00;\r
+          end\r
+          else begin\r
+            us_wdata_f[7:0] <= #1 us_wdata[7:0];\r
+          end\r
+        end // always \r
+       // ---------------------------------------------------------------------------\r
+\r
+       // ---------------------------------------------------------------------------\r
+       // TSTCNTL REGISTER\r
+       // ---------------------------------------------------------------------------\r
+       // FSM to generate pulses if tstcntl_reg[3] or tstcntl_reg[4] are written to "1" \r
+       // ---------------------------------------------------------------------------\r
+\r
+        always @(posedge us_clk or negedge reset_n) begin\r
+          if (~reset_n) begin\r
+            cntl_fsm_st <= #1 IDLE;\r
+           start_burst <= #1 1'b0;\r
+           ram_rst <= #1 1'b0;\r
+          end\r
+          else begin\r
+\r
+               case (cntl_fsm_st)\r
+\r
+                       IDLE:\r
+                            begin\r
+                               start_burst <= #1 1'b0;\r
+                               ram_rst <= #1 1'b0;\r
+\r
+                               if  (we[1] == 1) \r
+                                  cntl_fsm_st <= #1 DELAY;\r
+                               else\r
+                                  cntl_fsm_st <= #1 IDLE;\r
+                            end\r
+                       DELAY:\r
+                            begin\r
+                               if  (us_wdata_f[3] == 1) \r
+                                  cntl_fsm_st <= #1 PULSE1;\r
+                               else if (us_wdata_f[4] == 1) \r
+                                  cntl_fsm_st <= #1 PULSE2;\r
+                               else\r
+                                  cntl_fsm_st <= #1 IDLE;\r
+                            end\r
+                       PULSE1:\r
+                            begin\r
+                               start_burst <= #1 1'b1;\r
+                               cntl_fsm_st <= #1 IDLE;\r
+                            end\r
+                       PULSE2:\r
+                            begin\r
+                               ram_rst <= #1 1'b1;\r
+                               cntl_fsm_st <= #1 IDLE;\r
+                            end\r
+                       default:\r
+                            begin\r
+                               cntl_fsm_st <= #1 IDLE;\r
+                               start_burst <= #1 1'b0;\r
+                               ram_rst <= #1 1'b0;\r
+                            end\r
+               endcase \r
+          end\r
+        end // always \r
+\r
+       // ---------------------------------------------------------------------------\r
+       // Write data into TSTCNTL bits [3:0]\r
+       // ---------------------------------------------------------------------------\r
+\r
+        always @(posedge us_clk or negedge reset_n) begin\r
+          if (~reset_n) begin\r
+            tstcntl_reg[7:0] <= #1 8'h00;\r
+          end\r
+          else begin\r
+           if (we[1] == 1) begin  \r
+               tstcntl_reg[3:0] <= #1 us_wdata_f[3:0];\r
+               tstcntl_reg[7:4] <= #1 4'b0000;\r
+            end\r
+          end\r
+        end // always \r
+       // ---------------------------------------------------------------------------\r
+\r
+       // ---------------------------------------------------------------------------\r
+       // Write data into TSTCNTL2 - unused \r
+       // ---------------------------------------------------------------------------\r
+\r
+        always @(posedge us_clk or negedge reset_n) begin\r
+          if (~reset_n) begin\r
+            tstcntl2_reg[7:0] <= #1 8'h00;\r
+          end\r
+          else begin\r
+          if (we[2] == 1) \r
+               tstcntl2_reg[7:0] <= #1 us_wdata_f[7:0];\r
+          end\r
+        end // always \r
+       // ---------------------------------------------------------------------------\r
+\r
+       // ---------------------------------------------------------------------------\r
+       // Write data into MACCNTL \r
+       // ---------------------------------------------------------------------------\r
+\r
+        always @(posedge us_clk or negedge reset_n) begin\r
+          if (~reset_n) begin\r
+            maccntl_reg[7:0] <= #1 8'h00;\r
+          end\r
+          else begin\r
+          if (we[3] == 1) \r
+               maccntl_reg[7:0] <= #1 us_wdata_f[7:0];\r
+          end\r
+        end // always \r
+       // ---------------------------------------------------------------------------\r
+\r
+       // ---------------------------------------------------------------------------\r
+       // Write data into PAUSTMR_L, and PAUSTMR_H \r
+       // ---------------------------------------------------------------------------\r
+\r
+        always @(posedge us_clk or negedge reset_n) begin\r
+          if (~reset_n) begin\r
+            paustmrl_reg[7:0] <= #1 8'h00;\r
+            paustmrh_reg[7:0] <= #1 8'h00;\r
+          end\r
+          else begin\r
+          if (we[4] == 1) \r
+               paustmrl_reg[7:0] <= #1 us_wdata_f[7:0];\r
+          if (we[5] == 1) \r
+               paustmrh_reg[7:0] <= #1 us_wdata_f[7:0];\r
+          end\r
+        end // always \r
+       // ---------------------------------------------------------------------------\r
+\r
+       // ---------------------------------------------------------------------------\r
+       // Write data into FIFOAFTL, and FIFOAFTH \r
+       // ---------------------------------------------------------------------------\r
+\r
+        always @(posedge us_clk or negedge reset_n) begin\r
+          if (~reset_n) begin\r
+            fifoaftl_reg[7:0] <= #1 8'hc1;\r
+            fifoafth_reg[7:0] <= #1 8'h01;\r
+          end\r
+          else begin\r
+          if (we[6] == 1) \r
+               fifoaftl_reg[7:0] <= #1 us_wdata_f[7:0];\r
+          if (we[7] == 1) \r
+               fifoafth_reg[7:0] <= #1 us_wdata_f[7:0];\r
+          end\r
+        end // always \r
+       // ---------------------------------------------------------------------------\r
+\r
+       // ---------------------------------------------------------------------------\r
+       // Write data into FIFOAETL, and FIFOAETH \r
+       // ---------------------------------------------------------------------------\r
+\r
+        always @(posedge us_clk or negedge reset_n) begin\r
+          if (~reset_n) begin\r
+            fifoaetl_reg[7:0] <= #1 8'h05;\r
+            fifoaeth_reg[7:0] <= #1 8'h00;\r
+          end\r
+          else begin\r
+          if (we[8] == 1) \r
+               fifoaetl_reg[7:0] <= #1 us_wdata_f[7:0];\r
+          if (we[9] == 1) \r
+               fifoaeth_reg[7:0] <= #1 us_wdata_f[7:0];\r
+          end\r
+        end // always \r
+       // ---------------------------------------------------------------------------\r
+\r
+       // ---------------------------------------------------------------------------\r
+       // Write to RXSTATUS Reg from system side \r
+       // ---------------------------------------------------------------------------\r
+        always @(posedge rxc_clk or negedge reset_n) begin\r
+          if (~reset_n) begin\r
+           rxstatus_reg[7:0] <= #1 8'h00;\r
+          end\r
+          else begin\r
+               if (re10_dly & !us_rdy_wide)\r
+                 rxstatus_reg[7:0] <= #1 8'h00;\r
+               else begin\r
+                 if (rx_error_ri == 1'b1)\r
+                   rxstatus_reg[0] <= #1 1'b1;\r
+                 if (rx_fifo_error_ri == 1'b1)\r
+                   rxstatus_reg[1] <= #1 1'b1;\r
+                end \r
+          end \r
+        end // always \r
+\r
+       // ---------------------------------------------------------------------------\r
+       // Write to TXSTATUS Reg from system side \r
+       // ---------------------------------------------------------------------------\r
+        always @(posedge txc_clk or negedge reset_n) begin\r
+          if (~reset_n) begin\r
+           txstatus_reg[7:0] <= #1 8'h00;\r
+          end\r
+          else begin\r
+               if (re11_dly & !us_rdy_wide)\r
+                 txstatus_reg[7:0] <= #1 8'h00;\r
+               else begin\r
+                 if (tx_disfrm_ri == 1'b1)\r
+                   txstatus_reg[0] <= #1 1'b1;\r
+                 if (tx_fifo_full_ri == 1'b1)\r
+                   txstatus_reg[1] <= #1 1'b1;\r
+                end \r
+          end \r
+        end // always \r
+\r
+       // ---------------------------------------------------------------------------\r
+       // RX STAT COUNTERS \r
+       // ---------------------------------------------------------------------------\r
+        always @(posedge rxc_clk or negedge reset_n) begin\r
+          if (~reset_n) begin\r
+           rxpicnt_reg <= #1 16'h0000;\r
+           rxlcecnt_reg <= #1 16'h0000;\r
+           rxlfcnt_reg <= #1 16'h0000;\r
+           rxsfcnt_reg <= #1 16'h0000; \r
+           rxipgcnt_reg <= #1 16'h0000;\r
+           rxcrccnt_reg <= #1 16'h0000;\r
+           rxokcnt_reg <= #1 16'h0000;\r
+           rxcfcnt_reg <= #1 16'h0000;\r
+           rxpfcnt_reg <= #1 16'h0000;\r
+           rxmfcnt_reg <= #1 16'h0000;\r
+           rxbfcnt_reg <= #1 16'h0000;\r
+           rxvfcnt_reg <= #1 16'h0000;\r
+          end\r
+          else begin\r
+               if (re12_dly & !us_rdy_wide)\r
+                 rxpicnt_reg <= #1 16'h0000;\r
+               if (re14_dly & !us_rdy_wide)\r
+                 rxlcecnt_reg <= #1 16'h0000;\r
+               if (re16_dly & !us_rdy_wide)\r
+                 rxlfcnt_reg <= #1 16'h0000;\r
+               if (re18_dly & !us_rdy_wide)\r
+                 rxsfcnt_reg <= #1 16'h0000;   \r
+               if (re20_dly & !us_rdy_wide)\r
+                 rxipgcnt_reg <= #1 16'h0000;\r
+               if (re22_dly & !us_rdy_wide)\r
+                 rxcrccnt_reg <= #1 16'h0000;\r
+               if (re24_dly & !us_rdy_wide)\r
+                 rxokcnt_reg <= #1 16'h0000;\r
+               if (re26_dly & !us_rdy_wide)\r
+                 rxcfcnt_reg <= #1 16'h0000;\r
+               if (re28_dly & !us_rdy_wide)\r
+                 rxpfcnt_reg <= #1 16'h0000;\r
+               if (re30_dly & !us_rdy_wide)\r
+                 rxmfcnt_reg <= #1 16'h0000;\r
+               if (re32_dly & !us_rdy_wide)\r
+                 rxbfcnt_reg <= #1 16'h0000;\r
+               if (re34_dly & !us_rdy_wide)\r
+                 rxvfcnt_reg <= #1 16'h0000;\r
+               else begin\r
+                 if (rx_stat_en == 1'b1) begin\r
+                   if (rx_stat_vec[26] == 1'b1)\r
+                     rxpicnt_reg <= #1 rxpicnt_reg + 1;\r
+                   if (rx_stat_vec[24] == 1'b1)\r
+                     rxlcecnt_reg <= #1 rxlcecnt_reg + 1;\r
+                   if (rx_stat_vec[31] == 1'b1)\r
+                     rxlfcnt_reg <= #1 rxlfcnt_reg + 1;\r
+                   if (rx_stat_vec[30] == 1'b1)\r
+                     rxsfcnt_reg <= #1 rxsfcnt_reg + 1;        \r
+                   if (rx_stat_vec[29] == 1'b1)\r
+                     rxipgcnt_reg <= #1 rxipgcnt_reg + 1;\r
+                   if (rx_stat_vec[25] == 1'b1)\r
+                     rxcrccnt_reg <= #1 rxcrccnt_reg + 1;\r
+                   if (rx_stat_vec[23] == 1'b1)\r
+                     rxokcnt_reg <= #1 rxokcnt_reg + 1;\r
+                   if (rx_stat_vec[18] == 1'b1)\r
+                     rxcfcnt_reg <= #1 rxcfcnt_reg + 1;\r
+                   if (rx_stat_vec[17] == 1'b1)\r
+                     rxpfcnt_reg <= #1 rxpfcnt_reg + 1;\r
+                   if (rx_stat_vec[22] == 1'b1)\r
+                     rxmfcnt_reg <= #1 rxmfcnt_reg + 1;\r
+                   if (rx_stat_vec[21] == 1'b1)\r
+                     rxbfcnt_reg <= #1 rxbfcnt_reg + 1;\r
+                   if (rx_stat_vec[16] == 1'b1)\r
+                     rxvfcnt_reg <= #1 rxvfcnt_reg + 1;\r
+                  end \r
+                end \r
+          end \r
+        end // always \r
+\r
+\r
+       // ---------------------------------------------------------------------------\r
+       // TX STAT COUNTERS \r
+       // ---------------------------------------------------------------------------\r
+        always @(posedge txc_clk or negedge reset_n) begin\r
+          if (~reset_n) begin\r
+           txufcnt_reg <= #1 16'h0000;\r
+           txpfcnt_reg <= #1 16'h0000;\r
+           txmfcnt_reg <= #1 16'h0000;\r
+           txbfcnt_reg <= #1 16'h0000;\r
+           txvfcnt_reg <= #1 16'h0000;\r
+           txbfccnt_reg <= #1 16'h0000;\r
+           txjfcnt_reg <= #1 16'h0000;\r
+          end\r
+          else begin\r
+               if (re36_dly & !us_rdy_wide)\r
+                 txufcnt_reg <= #1 16'h0000;\r
+               if (re38_dly & !us_rdy_wide)\r
+                 txpfcnt_reg <= #1 16'h0000;\r
+               if (re40_dly & !us_rdy_wide)\r
+                 txmfcnt_reg <= #1 16'h0000;\r
+               if (re42_dly & !us_rdy_wide)\r
+                 txbfcnt_reg <= #1 16'h0000;\r
+               if (re44_dly & !us_rdy_wide)\r
+                 txvfcnt_reg <= #1 16'h0000;\r
+               if (re46_dly & !us_rdy_wide)\r
+                 txbfccnt_reg <= #1 16'h0000;\r
+               if (re48_dly & !us_rdy_wide)\r
+                 txjfcnt_reg <= #1 16'h0000;\r
+               else begin\r
+                 if (tx_stat_en == 1'b1) begin\r
+                   if (tx_stat_vec[0] == 1'b1)\r
+                     txufcnt_reg <= #1 txufcnt_reg + 1;\r
+                   if (tx_stat_vec[6] == 1'b1)\r
+                     txpfcnt_reg <= #1 txpfcnt_reg + 1;\r
+                   if (tx_stat_vec[1] == 1'b1)\r
+                     txmfcnt_reg <= #1 txmfcnt_reg + 1;\r
+                   if (tx_stat_vec[2] == 1'b1)\r
+                     txbfcnt_reg <= #1 txbfcnt_reg + 1;\r
+                   if (tx_stat_vec[7] == 1'b1)\r
+                     txvfcnt_reg <= #1 txvfcnt_reg + 1;\r
+                   if (tx_stat_vec[3] == 1'b1)\r
+                     txbfccnt_reg <= #1 txbfccnt_reg + 1;\r
+                   if (tx_stat_vec[4] == 1'b1)\r
+                     txjfcnt_reg <= #1 txjfcnt_reg + 1;\r
+                  end \r
+                end \r
+          end \r
+        end // always \r
+\r
+\r
+endmodule // reg_intf\r
+\r
+\r
+\r
+\r

diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/rx_loopbk.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/rx_loopbk.v
new file mode 100644 (file)
index 0000000..8c844d5
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/rx_loopbk.v
@@ -0,0 +1,300 @@
+// ===========================================================================\r
+// Verilog module generated by IPexpress\r
+// Filename: rx_loopbk.v  \r
+// Copyright 2012 (c) Lattice Semiconductor Corporation. All rights reserved.\r
+// ===========================================================================\r
+\r
+//`timescale 1ns/100ps\r
+\r
+\r
+// DEFINES\r
+\r
+\r
+module rx_loopbk(\r
+                clk,\r
+                reset_n,\r
+                rxmac_clk_en,\r
+                add_swap,\r
+                loop_enb,\r
+               rx_dbout,\r
+                rx_write,\r
+                rx_eof,\r
+                tx_dbin,\r
+                tx_write,\r
+                tx_eof\r
+               );\r
+\r
+\r
+        input clk;                       // rx fifo clock \r
+        input reset_n;                   // active low global reset\r
+        input rxmac_clk_en;              // rx clk enable \r
+        \r
+        input add_swap;                  // address swap control bit from reg  \r
+        input loop_enb;                  // loop back enable control bit from reg\r
+ \r
+       input [7:0] rx_dbout;           // rxdata input to Rx FIFO \r
+       input rx_eof;                    // rxdata EOF input to Rx FIFO  \r
+       input rx_write;                  // Rx FIFO write enable \r
+\r
+       output [7:0] tx_dbin;           // txdata input to Tx FIFO \r
+       reg [7:0] tx_dbin;              //\r
+  \r
+       output tx_eof;                   // txdata EOF input to Tx FIFO  \r
+       reg tx_eof;                      //  \r
+\r
+       output tx_write;                 // Tx FIFO write enable \r
+       reg tx_write;                    //  \r
+\r
+        \r
+       reg [7:0] rx_dbout_1f;          // rxdata input to Rx FIFO flopped 1 time  \r
+       reg rx_eof_1f;                   // rxdata EOF input to Rx FIFO  flopped 1 time \r
+       reg rx_write_1f;                 // Rx FIFO write enable flopped 1 time \r
+\r
+       reg [7:0] rx_dbout_2f;          // rxdata input to Rx FIFO flopped 2 times  \r
+       reg rx_eof_2f;                   // rxdata EOF input to Rx FIFO  flopped 2 times \r
+       reg rx_write_2f;                 // Rx FIFO write enable flopped 2 times \r
+\r
+       reg [7:0] rx_dbout_3f;          // rxdata input to Rx FIFO flopped 3 times  \r
+       reg rx_eof_3f;                   // rxdata EOF input to Rx FIFO  flopped 3 times \r
+       reg rx_write_3f;                 // Rx FIFO write enable flopped 3 times \r
+\r
+       reg [7:0] rx_dbout_4f;          // rxdata input to Rx FIFO flopped 4 times  \r
+       reg rx_eof_4f;                   // rxdata EOF input to Rx FIFO  flopped 4 times \r
+       reg rx_write_4f;                 // Rx FIFO write enable flopped 4 times \r
+\r
+       reg [7:0] rx_dbout_5f;          // rxdata input to Rx FIFO flopped 5 times  \r
+       reg rx_eof_5f;                   // rxdata EOF input to Rx FIFO  flopped 5 times \r
+       reg rx_write_5f;                 // Rx FIFO write enable flopped 5 times \r
+\r
+       reg [7:0] rx_dbout_6f;          // rxdata input to Rx FIFO flopped 6 times  \r
+       reg rx_eof_6f;                   // rxdata EOF input to Rx FIFO  flopped 6 times \r
+       reg rx_write_6f;                 // Rx FIFO write enable flopped 6 times \r
+\r
+       reg [7:0] rx_dbout_7f;          // rxdata input to Rx FIFO flopped 7 times  \r
+       reg rx_eof_7f;                   // rxdata EOF input to Rx FIFO  flopped 7 times \r
+       reg rx_write_7f;                 // Rx FIFO write enable flopped 7 times \r
+\r
+       reg [7:0] rx_dbout_8f;          // rxdata input to Rx FIFO flopped 8 times  \r
+       reg rx_eof_8f;                   // rxdata EOF input to Rx FIFO  flopped 8 times \r
+       reg rx_write_8f;                 // Rx FIFO write enable flopped 8 times \r
+\r
+       reg [7:0] rx_dbout_9f;          // rxdata input to Rx FIFO flopped 9 times  \r
+       reg [7:0] rx_dbout_10f;          // rxdata input to Rx FIFO flopped 10 times  \r
+       reg [7:0] rx_dbout_11f;          // rxdata input to Rx FIFO flopped 11 times  \r
+       reg [7:0] rx_dbout_12f;          // rxdata input to Rx FIFO flopped 12 times  \r
+       reg [7:0] rx_dbout_13f;          // rxdata input to Rx FIFO flopped 13 times  \r
+\r
+       reg [7:0] add_swap_data;        //  data from add swap mux flopped once\r
+ \r
+       reg mx_ctl_1f;                   //  mux control flopped 1 time  \r
+       reg mx_ctl_2f;                   //  mux control flopped 2 times  \r
+       reg mx_ctl_3f;                   //  mux control flopped 3 times  \r
+       reg mx_ctl_4f;                   //  mux control flopped 4 times  \r
+       reg mx_ctl_5f;                   //  mux control flopped 5 times  \r
+       reg mx_ctl_6f;                   //  mux control flopped 6 times  \r
+       reg mx_ctl_7f;                   //  mux control flopped 7 time  \r
+       reg mx_ctl_8f;                   //  mux control flopped 8 times  \r
+       reg mx_ctl_9f;                   //  mux control flopped 9 times  \r
+       reg mx_ctl_10f;                  //  mux control flopped 10 times  \r
+       reg mx_ctl_11f;                  //  mux control flopped 11 times  \r
+       reg mx_ctl_12f;                  //  mux control flopped 12 times  \r
+       reg addr_detect_en;              //  address detect enable\r
+\r
+       reg [1:0] mux_ctl;               // address swap mux control bits \r
+\r
+        parameter                        \r
+                NO_WRITE = 1'b0;         // write enable low \r
+\r
+        parameter [7:0]               \r
+                NULL_DATA = 8'h00;    // NULL DATA \r
+\r
+        parameter \r
+                NULL_EOF = 1'b0;         // NO EOF \r
+\r
+        parameter [1:0]                         // ADD SWAP MUX SELECTIONS\r
+               DATA_D7  = 2'b00,\r
+               DATA_D1  = 2'b01,\r
+               DATA_D13 = 2'b10,\r
+               NO_SWAP  = 2'b11;\r
+\r
+\r
+\r
+\r
+        //-------------------------------------------------------------------\r
+        // Pipeline rx_dbout, rx_eof and rx_write  \r
+        //-------------------------------------------------------------------\r
+        always @(posedge clk or negedge reset_n) begin\r
+          if (~reset_n) begin\r
+                rx_dbout_1f <=  8'h00;\r
+                rx_eof_1f <=  1'b0;\r
+                rx_write_1f <=  1'b0;\r
+\r
+                rx_dbout_2f <=  8'h00;\r
+                rx_eof_2f <=  1'b0;\r
+                rx_write_2f <=  1'b0;\r
+\r
+                rx_dbout_3f <=  8'h00;\r
+                rx_eof_3f <=  1'b0;\r
+                rx_write_3f <=  1'b0;\r
+\r
+                rx_dbout_4f <=  8'h00;\r
+                rx_eof_4f <=  1'b0;\r
+                rx_write_4f <=  1'b0;\r
+\r
+                rx_dbout_5f <=  8'h00;\r
+                rx_eof_5f <=  1'b0;\r
+                rx_write_5f <=  1'b0;\r
+\r
+                rx_dbout_6f <=  8'h00;\r
+                rx_eof_6f <=  1'b0;\r
+                rx_write_6f <=  1'b0;\r
+\r
+                rx_dbout_7f <=  8'h00;\r
+                rx_eof_7f <=  1'b0;\r
+                rx_write_7f <=  1'b0;\r
+\r
+                rx_dbout_8f <=  8'h00;\r
+                rx_eof_8f <=  1'b0;\r
+                rx_write_8f <=  1'b0;\r
+               \r
+                rx_dbout_9f <=  8'h00;\r
+                rx_dbout_10f <=  8'h00;\r
+                rx_dbout_11f <=  8'h00;\r
+                rx_dbout_12f <=  8'h00;\r
+                rx_dbout_13f <=  8'h00;\r
+          end\r
+          else if (rxmac_clk_en) begin\r
+                rx_dbout_1f <=  rx_dbout;\r
+                rx_eof_1f <=  rx_eof;\r
+                rx_write_1f <=  rx_write;\r
+\r
+                rx_dbout_2f <=  rx_dbout_1f;\r
+                rx_eof_2f <=  rx_eof_1f;\r
+                rx_write_2f <=  rx_write_1f;\r
+\r
+                rx_dbout_3f <=  rx_dbout_2f;\r
+                rx_eof_3f <=  rx_eof_2f;\r
+                rx_write_3f <=  rx_write_2f;\r
+\r
+                rx_dbout_4f <=  rx_dbout_3f;\r
+                rx_eof_4f <=  rx_eof_3f;\r
+                rx_write_4f <=  rx_write_3f;\r
+\r
+                rx_dbout_5f <=  rx_dbout_4f;\r
+                rx_eof_5f <=  rx_eof_4f;\r
+                rx_write_5f <=  rx_write_4f;\r
+\r
+                rx_dbout_6f <=  rx_dbout_5f;\r
+                rx_eof_6f <=  rx_eof_5f;\r
+                rx_write_6f <=  rx_write_5f;\r
+\r
+                rx_dbout_7f <=  rx_dbout_6f;\r
+                rx_eof_7f <=  rx_eof_6f;\r
+                rx_write_7f <=  rx_write_6f;\r
+\r
+                rx_write_8f <=  rx_write_7f;\r
+                rx_eof_8f <=  rx_eof_7f;\r
+                rx_dbout_8f <=  rx_dbout_7f;\r
+\r
+                rx_dbout_9f <=  rx_dbout_8f;\r
+                rx_dbout_10f <=  rx_dbout_9f;\r
+                rx_dbout_11f <=  rx_dbout_10f;\r
+                rx_dbout_12f <=  rx_dbout_11f;\r
+                rx_dbout_13f <=  rx_dbout_12f;\r
+          end // else\r
+        end // always\r
+\r
+        //-------------------------------------------------------------------\r
+        // Pipelined mux control bits \r
+        //-------------------------------------------------------------------\r
+        always @(posedge clk or negedge reset_n) begin\r
+          if (~reset_n) begin\r
+                mx_ctl_1f <=  1'b0;\r
+                mx_ctl_2f <=  1'b0;\r
+                mx_ctl_3f <=  1'b0;\r
+                mx_ctl_4f <=  1'b0;\r
+                mx_ctl_5f <=  1'b0;\r
+                mx_ctl_6f <=  1'b0;\r
+                mx_ctl_7f <=  1'b0;\r
+                mx_ctl_8f <=  1'b0;\r
+                mx_ctl_9f <=  1'b0;\r
+                mx_ctl_10f <=  1'b0;\r
+                mx_ctl_11f <=  1'b0;\r
+                mx_ctl_12f <=  1'b0;\r
+                addr_detect_en <=  1'b1;\r
+          end\r
+          else if (rxmac_clk_en) begin\r
+               if (rx_write_1f & rx_write_7f) begin\r
+                  addr_detect_en <= 0;\r
+               end else if (rx_write_7f & rx_eof_7f) begin\r
+                  addr_detect_en <= 1;\r
+               end\r
+                mx_ctl_1f <=  (rx_write_1f & !rx_write_7f & addr_detect_en);\r
+                mx_ctl_2f <=  mx_ctl_1f;\r
+                mx_ctl_3f <=  mx_ctl_2f;\r
+                mx_ctl_4f <=  mx_ctl_3f;\r
+                mx_ctl_5f <=  mx_ctl_4f;\r
+                mx_ctl_6f <=  mx_ctl_5f;\r
+                mx_ctl_7f <=  mx_ctl_6f;\r
+                mx_ctl_8f <=  mx_ctl_7f;\r
+                mx_ctl_9f <=  mx_ctl_8f;\r
+                mx_ctl_10f <=  mx_ctl_9f;\r
+                mx_ctl_11f <=  mx_ctl_10f;\r
+                mx_ctl_12f <=  mx_ctl_11f;\r
+          end // else\r
+        end // always\r
+\r
+        always @(add_swap, mx_ctl_12f, mx_ctl_6f) begin\r
+           if (add_swap) begin\r
+             mux_ctl[0] <=  mx_ctl_6f;\r
+             mux_ctl[1] <=  mx_ctl_12f;\r
+           end\r
+           else begin\r
+             mux_ctl <=  NO_SWAP;\r
+           end\r
+        end // always\r
+\r
+\r
+        //-------------------------------------------------------------------\r
+        // Pipelined address swap mux\r
+        //-------------------------------------------------------------------\r
+        always @(posedge clk or negedge reset_n) begin\r
+          if (~reset_n) begin\r
+                add_swap_data <=  8'h00;\r
+          end\r
+          else if (rxmac_clk_en) begin\r
+                case (mux_ctl) \r
+                 DATA_D7: add_swap_data <=  rx_dbout_7f;     \r
+                 DATA_D1: add_swap_data <=  rx_dbout_1f;   \r
+                 DATA_D13: add_swap_data <=  rx_dbout_13f;   \r
+                 NO_SWAP: add_swap_data <=  rx_dbout_7f;   \r
+                endcase\r
+          end // else\r
+        end // always\r
+\r
+        //-------------------------------------------------------------------\r
+        // Pipelined muxes - loopback rx data or Null data (place holder \r
+       //                   for a frame buffer etc.) \r
+        //-------------------------------------------------------------------\r
+        always @(posedge clk or negedge reset_n) begin\r
+          if (~reset_n) begin\r
+                tx_dbin <=  8'h00;\r
+                tx_write <=  1'b0;\r
+                tx_eof <=  1'b0;\r
+          end\r
+          else if (rxmac_clk_en) begin\r
+                if (loop_enb) begin    \r
+                  tx_dbin <=  add_swap_data;\r
+                  tx_write <=  rx_write_8f ;\r
+                  tx_eof <=  rx_eof_8f;\r
+                end\r
+                else begin\r
+                  tx_dbin <=  NULL_DATA;\r
+                  tx_write <=  NO_WRITE;\r
+                  tx_eof <=  NULL_EOF;\r
+                end\r
+          end // else\r
+        end // always\r
+\r
+\r
+endmodule//\r

diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/tst_logic.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/tst_logic.v
new file mode 100644 (file)
index 0000000..6e2daf6
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/template/tst_logic.v
@@ -0,0 +1,295 @@
+// ===========================================================================\r
+// Verilog module generated by IPexpress\r
+// Filename: tst_logic.v  \r
+// Copyright 2012 (c) Lattice Semiconductor Corporation. All rights reserved.\r
+// ===========================================================================\r
+\r
+//`timescale 1ns/100ps\r
+\r
+module tst_logic (\r
+\r
+       // -------\r
+       // inputs\r
+       // -------\r
+\r
+       // from IO\r
+        reset_n,\r
+        txmac_clk,\r
+        rxmac_clk,\r
+        txmac_clk_en,\r
+        rxmac_clk_en,\r
+\r
+       // from tsmac core\r
+        rx_write,\r
+        rx_dbout,\r
+        rx_eof,\r
+        rx_error,\r
+        rx_fifo_error,\r
+       tx_macread,\r
+       tx_done,\r
+       tx_disfrm,\r
+//gbit_en,\r
+       \r
+       // from reg_intf\r
+        pkt_add_swap_ri,\r
+        pkt_loop_enb_ri,\r
+       tx_sndpaustim_ri,\r
+       tx_sndpausreq_ri,\r
+       tx_fifoctrl_ri,\r
+       rx_fifo_full_ri,\r
+       tx_fifo_empty_ri,\r
+       ignore_next_pkt_ri,\r
+       aff_thrhd,\r
+       afe_thrhd,\r
+\r
+       // -------\r
+       // outputs\r
+       // -------\r
+\r
+       // to tsmac core\r
+       tx_fifodata,\r
+       tx_fifoeof,\r
+       tx_fifoavail,\r
+       tx_fifoempty,\r
+       tx_sndpaustim,\r
+       tx_sndpausreq,\r
+       tx_fifoctrl,\r
+       rx_fifo_full,\r
+       ignore_next_pkt,\r
+\r
+       // to reg_intf\r
+        rxc_clk,\r
+        txc_clk,\r
+        rx_error_ri,\r
+        rx_fifo_error_ri,\r
+       tx_disfrm_ri,\r
+        tx_fifo_full_ri\r
+       );\r
+\r
+       //======================\r
+       // inputs and outputs \r
+       //======================\r
+       input reset_n;                   // active low global reset\r
+        input txmac_clk;\r
+        input rxmac_clk;\r
+        input txmac_clk_en;\r
+        input rxmac_clk_en;\r
+\r
+        // from tsmac core\r
+        input rx_write;\r
+        input [7:0] rx_dbout;\r
+        input rx_eof;\r
+        input rx_error;\r
+        input rx_fifo_error;\r
+        input tx_macread;\r
+        input tx_done;\r
+        input tx_disfrm;\r
+//        input gbit_en;\r
+\r
+        // from reg_intf\r
+        input pkt_add_swap_ri;\r
+        input pkt_loop_enb_ri;\r
+        input [15:0] tx_sndpaustim_ri;\r
+        input tx_sndpausreq_ri;\r
+        input tx_fifoctrl_ri;\r
+        input rx_fifo_full_ri;\r
+        input tx_fifo_empty_ri;\r
+        input ignore_next_pkt_ri; \r
+       input [8:0] aff_thrhd;          // almost full threshold from reg intf\r
+       input [8:0] afe_thrhd;          // almost empty threshold from reg intf\r
+\r
+        // to tsmac core\r
+        output [7:0] tx_fifodata;\r
+        output tx_fifoeof;\r
+        output tx_fifoavail;\r
+        output tx_fifoempty;\r
+        output [15:0] tx_sndpaustim;\r
+        output tx_sndpausreq;\r
+        output tx_fifoctrl;\r
+        output rx_fifo_full;\r
+        output ignore_next_pkt;\r
+\r
+        // to reg_intf\r
+        output rx_error_ri;\r
+        output rx_fifo_error_ri;\r
+        output tx_disfrm_ri;\r
+        output tx_fifo_full_ri;\r
+        output rxc_clk;                    // MAC Client side Rx clock \r
+        output txc_clk;                    // MAC Client side Tx clock\r
+\r
+parameter pdevice_family = "EC";\r
+\r
+       //======================\r
+       // Regs and wires\r
+       //======================\r
+        wire tx_fifoempty;\r
+        reg [15:0] tx_sndpaustim;\r
+        reg tx_sndpausreq;\r
+        reg tx_fifoctrl;\r
+        reg ignore_next_pkt;\r
+        reg write_eof_rxclk;\r
+        reg [1:0] clr_write_eof_rxclk;\r
+        reg [2:0] write_eof_txclk;\r
+        reg flop_tx_macread;\r
+        reg flop_flop_tx_macread;\r
+        reg flop_tx_fifo_eof;\r
+        reg [3:0] frames_present;\r
+\r
+        reg rx_error_ri;\r
+        reg rx_fifo_error_ri;\r
+        reg tx_disfrm_ri;\r
+        reg tx_fifo_full_ri;\r
+        reg tx_fifo_empty_f;            // tx fifo empty pipelined and synced with clk_enb\r
+\r
+        wire rxc_clk;                    // MAC Client side Rx clock \r
+        wire txc_clk;                    // MAC Client side Tx clock \r
+\r
+        wire [7:0] tx_fifodata;\r
+        wire tx_fifoeof;\r
+        reg  tx_fifoavail;\r
+        reg  tx_fifoavail_int;\r
+        wire rx_fifo_full;\r
+\r
+       wire [8:0] tx_fifo_dout;        // data out of tx_fifo\r
+       wire tx_fifo_full;              // tx fifo full\r
+       wire tx_fifo_afull;             // tx fifo almost full\r
+        wire tx_fifo_empty;            // tx fifo empty\r
+        wire tx_fifo_aempty;           // tx fifo almost empty\r
+\r
+        wire [7:0] tx_dbin;\r
+        wire tx_write;\r
+        wire tx_eof;\r
+\r
+        //-------------------------------------------------------------------\r
+        // glue logic \r
+        //-------------------------------------------------------------------\r
+       assign rxc_clk = rxmac_clk;     \r
+       assign txc_clk = txmac_clk;     \r
+        assign tx_fifodata[7:0] = tx_fifo_dout[7:0];\r
+        assign tx_fifoeof = tx_fifo_dout[8];\r
+        assign rx_fifo_full = (tx_fifo_full | rx_fifo_full_ri);\r
+\r
+        assign tx_fifoempty = (tx_fifo_empty|tx_fifo_empty_ri);\r
+\r
+        always @(posedge rxmac_clk or negedge reset_n) begin\r
+          if (~reset_n) begin\r
+               ignore_next_pkt <=  1'b0;\r
+               tx_fifoavail <=  1'b0;\r
+               tx_fifoavail_int <=  1'b0;\r
+               write_eof_rxclk <=  1'b0;\r
+               clr_write_eof_rxclk <=  2'b00;\r
+               tx_fifo_empty_f <=  1'b1;\r
+           end\r
+          else if (rxmac_clk_en) begin\r
+               tx_fifo_empty_f <=  tx_fifo_empty;\r
+               ignore_next_pkt <=  ignore_next_pkt_ri;\r
+\r
+                tx_fifoavail_int <= (|frames_present) | (~tx_fifo_aempty);\r
+                tx_fifoavail <= tx_fifoavail_int;\r
+\r
+               clr_write_eof_rxclk[1] <= clr_write_eof_rxclk[0];\r
+               clr_write_eof_rxclk[0] <= write_eof_rxclk;\r
+               if (rx_write & rx_eof) begin\r
+                  write_eof_rxclk <= 1;\r
+               end else if (clr_write_eof_rxclk[1]) begin\r
+                  write_eof_rxclk <= 0;\r
+                end               \r
+           end // else\r
+        end // always\r
+\r
+        always @(posedge txmac_clk or negedge reset_n) begin\r
+          if (~reset_n) begin\r
+                tx_sndpausreq <=  1'b0;\r
+                tx_fifo_full_ri <=  1'b0;\r
+               tx_sndpaustim[15:0] <=  16'h0000;\r
+                tx_disfrm_ri <=  1'b0;\r
+                tx_fifoctrl <=  1'b0;\r
+               rx_error_ri <=  1'b0;\r
+               rx_fifo_error_ri <=  1'b0;\r
+               write_eof_txclk <=  1'b0;\r
+               flop_tx_macread <=  1'b0;\r
+               flop_flop_tx_macread <=  1'b0;\r
+               flop_tx_fifo_eof <=  1'b0;\r
+               frames_present <=  1'b0;\r
+          end\r
+          else if (txmac_clk_en) begin\r
+               if (tx_sndpausreq_ri == 1) begin\r
+                      tx_sndpausreq <= 1;\r
+               end else if (tx_macread == 1) begin\r
+                  if (tx_fifo_afull) begin\r
+                      tx_sndpausreq <= 1;\r
+                  end else begin\r
+                      tx_sndpausreq <= 0;\r
+                  end\r
+               end else begin\r
+                   tx_sndpausreq <= 0;\r
+               end\r
+               tx_sndpaustim[15:0] <=  tx_sndpaustim_ri[15:0];\r
+                tx_fifoctrl <=  tx_fifoctrl_ri;\r
+\r
+                tx_disfrm_ri <=  tx_disfrm;    // an error condition -fifo underun etc.\r
+               rx_error_ri <=  rx_error;\r
+               rx_fifo_error_ri <=  rx_fifo_error;\r
+\r
+                tx_fifo_full_ri <=  tx_fifo_full;\r
+\r
+                write_eof_txclk[2] <= write_eof_txclk[1];\r
+                write_eof_txclk[1] <= write_eof_txclk[0];\r
+                write_eof_txclk[0] <= write_eof_rxclk;\r
+                flop_tx_macread    <= tx_macread;\r
+                flop_flop_tx_macread <= flop_tx_macread;\r
+                flop_tx_fifo_eof <= tx_fifo_dout[8];\r
+               if (tx_fifo_empty == 1) begin\r
+                    frames_present <= 0;  // When fifo is empty clear frames present\r
+               end else if ((write_eof_txclk[1] & !write_eof_txclk[2])\r
+                               && !(flop_flop_tx_macread & flop_tx_fifo_eof)) begin\r
+                    frames_present <= frames_present + 4'b0001;  // Increment # frames\r
+                end else if (!(write_eof_txclk[1] & !write_eof_txclk[2])\r
+                               && (flop_flop_tx_macread & flop_tx_fifo_eof)) begin\r
+                    frames_present <= frames_present - 4'b0001;  // Dec # frames in buf\r
+                end\r
+          end // else\r
+        end // always\r
+\r
+        //-------------------------------------------------------------------\r
+        // instanciate modules \r
+        //-------------------------------------------------------------------\r
+\r
+       rx_loopbk rx_loopbk(\r
+                .clk(rxmac_clk),\r
+                .reset_n(reset_n),\r
+                .rxmac_clk_en(rxmac_clk_en),\r
+                .add_swap(pkt_add_swap_ri),\r
+                .loop_enb(pkt_loop_enb_ri),\r
+                .rx_dbout(rx_dbout[7:0]),\r
+                .rx_write(rx_write),\r
+                .rx_eof(rx_eof),\r
+                .tx_dbin(tx_dbin),\r
+                .tx_write(tx_write),\r
+                .tx_eof(tx_eof)\r
+                );\r
+\r
+        //defparam tx_fifo.ff_ctl.SYNC_MODE = "ASYNC"; \r
+        //defparam tx_fifo.ff_ctl.RAM_MODE = "NOREG"; \r
+       fifo_2048x9 #(.pdevice_family(pdevice_family))\r
+             tx_fifo (\r
+                // INPUTS\r
+                .wclk(rxmac_clk),\r
+                .wren(tx_write),\r
+                .datain({tx_eof,tx_dbin}),\r
+                .reset(reset_n),\r
+                .rclk(txmac_clk),\r
+                .rden(tx_macread),\r
+                .aff_thrhd(aff_thrhd),\r
+                .afe_thrhd(afe_thrhd),\r
+                .wclk_en(rxmac_clk_en),\r
+                .rclk_en(txmac_clk_en),\r
+\r
+                // OUTPUTS\r
+                .daout(tx_fifo_dout[8:0]),\r
+                .empty(tx_fifo_empty),\r
+                .almost_full(tx_fifo_afull),\r
+                .almost_empty(tx_fifo_aempty),\r
+                .full(tx_fifo_full)\r
+                );\r
+endmodule\r

diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/top/ts_mac_core_only_top.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/top/ts_mac_core_only_top.v
new file mode 100644 (file)
index 0000000..320160c
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/top/ts_mac_core_only_top.v
@@ -0,0 +1,216 @@
+//=============================================================================\r
+// Verilog module generated by IPExpress    \r
+// Filename: USERNAME.v                                          \r
+// Copyright(c) 2006 Lattice Semiconductor Corporation. All rights reserved.   \r
+//=============================================================================\r
+\r
+/* WARNING - Changes to this file should be performed by re-running IPexpress\r
+or modifying the .LPC file and regenerating the core.  Other changes may lead\r
+to inconsistent simulation and/or implemenation results */\r
+module ts_mac_core_only_top (\r
+       // clock and reset\r
+       hclk,\r
+       txmac_clk,\r
+       rxmac_clk,\r
+       reset_n,\r
+       txmac_clk_en,\r
+       rxmac_clk_en,\r
+\r
+       // Input signals to the GMII\r
+       rxd,\r
+       rx_dv,\r
+       rx_er,\r
+       col,\r
+       crs,\r
+       \r
+       // Input signals to the CPU Interface\r
+       haddr,\r
+       hdatain,\r
+       hcs_n,\r
+       hwrite_n,\r
+       hread_n,\r
+       \r
+       // Input signals to the MII Management Interface\r
+     \r
+       // Input signals to the Tx MAC FIFO Interface\r
+       tx_fifodata,\r
+       tx_fifoavail,\r
+       tx_fifoeof,\r
+       tx_fifoempty,\r
+       tx_sndpaustim,\r
+       tx_sndpausreq,\r
+       tx_fifoctrl,\r
+     \r
+       // Input signals to the Rx MAC FIFO Interface\r
+       rx_fifo_full,\r
+       ignore_pkt,\r
+     \r
+       // Output signals from the GMII\r
+       txd,\r
+       tx_en,\r
+       tx_er,\r
+     \r
+       // Output signals from the CPU Interface\r
+       hdataout,\r
+       hdataout_en_n,\r
+       hready_n,\r
+       cpu_if_gbit_en,\r
+     \r
+       // Output signals from the MII Management Interface\r
+     \r
+       // Output signals from the Tx MAC FIFO Interface\r
+       tx_macread,\r
+       tx_discfrm,\r
+       tx_staten,\r
+       tx_statvec,\r
+       tx_done,\r
+     \r
+       // Output signals from the Rx MAC FIFO Interface\r
+       rx_fifo_error,\r
+       rx_stat_vector,\r
+       rx_dbout,\r
+       rx_write,\r
+       rx_stat_en,\r
+       rx_eof,\r
+       rx_error\r
+     );\r
+     \r
+     // ------------------------- clock and reset inputs ---------------------\r
+     input                            hclk;               // clock to the CPU I/F\r
+     input                            txmac_clk;          // clock to the Tx MAC\r
+     input                            rxmac_clk;          // clock to the RX MAC\r
+     input                            reset_n;            // Global reset\r
+\r
+    input                             txmac_clk_en;       // clock enable to the Tx MAC\r
+    input                             rxmac_clk_en;       // clock enable to the RX MAC\r
+     \r
+     // ----------------------- Input signals to the GMII -------------------\r
+    input  [7:0]                      rxd;                // Receive data\r
+    input                             rx_dv;              // Receive data valid\r
+    input                             rx_er;              // Receive data error\r
+\r
+     input                            col;                // Collision detect\r
+     input                            crs;                // Carrier Sense\r
+     \r
+     // -------------------- Input signals to the CPU I/F -------------------\r
+     input  [7:0]                     haddr;              // Address Bus\r
+     input  [7:0]                     hdatain;            // Input data Bus\r
+     input                            hcs_n;              // Chip select\r
+     input                            hwrite_n;           // Register write\r
+     input                            hread_n;            // Register read\r
+     \r
+     // -------------------- Input signals to the MII I/F -------------------\r
+\r
+     \r
+     // ---------------- Input signals to the Tx MAC FIFO I/F ---------------\r
+     input  [7:0]                     tx_fifodata;        // Data Input from FIFO\r
+     input                            tx_fifoavail;       // Data Available in FIFO\r
+     input                            tx_fifoeof;         // End of Frame\r
+     input                            tx_fifoempty;       // FIFO Empty\r
+     input  [15:0]                    tx_sndpaustim;      // Pause frame parameter\r
+     input                            tx_sndpausreq;      // Transmit PAUSE frame\r
+     input                            tx_fifoctrl;        // Control frame or Not\r
+     \r
+     // ---------------- Input signals to the Rx MAC FIFO I/F ---------------\r
+     input                            rx_fifo_full;       // Receive FIFO Full\r
+     input                            ignore_pkt;         // Ignore the frame\r
+     \r
+     // -------------------- Output signals from the GMII -----------------------\r
+     output [7:0]                     txd;                // Transmit data\r
+     output                           tx_en;              // Transmit Enable\r
+     output                           tx_er;              // Transmit Error\r
+     \r
+     // -------------------- Output signals from the CPU I/F -------------------\r
+     output [7:0]                     hdataout;           // Output data Bus\r
+     output                           hdataout_en_n;      // Data Out Enable\r
+     output                           hready_n;           // Ready signal\r
+     output                           cpu_if_gbit_en;     // Gig or 10/100 mode\r
+     \r
+     // -------------------- Output signals from the MII I/F -------------------\r
+\r
+     \r
+     // ---------------- Output signals from the Tx MAC FIFO I/F ---------------\r
+     output                           tx_macread;         // Read FIFO\r
+     output                           tx_discfrm;         // Discard Frame\r
+     output                           tx_staten;          // Status Vector Valid\r
+     output                           tx_done;            // Transmit of Frame done\r
+     output [30:0]                    tx_statvec;         // Tx Status Vector\r
+     \r
+     // ---------------- Output signals from the Rx MAC FIFO I/F ---------------\r
+     output                           rx_fifo_error;      // FIFO full detected\r
+     output [31:0]                    rx_stat_vector;     // Rx Status Vector\r
+     output [7:0]                     rx_dbout;           // Data Output to FIFO\r
+     output                           rx_write;           // Write FIFO\r
+     output                           rx_stat_en;         // Status Vector Valid\r
+     output                           rx_eof;             // Entire frame written\r
+     output                           rx_error;           // Erroneous frame\r
+     \r
+     tsmac U1_ts_mac_core_only_core ( \r
+\r
+         // clock and reset\r
+         .hclk(hclk),\r
+         .txmac_clk(txmac_clk),\r
+         .rxmac_clk(rxmac_clk),\r
+         .reset_n(reset_n),\r
+         .txmac_clk_en(txmac_clk_en),\r
+         .rxmac_clk_en(rxmac_clk_en),\r
+\r
+     \r
+         // Input signals to the GMII\r
+         .rxd(rxd),\r
+         .rx_dv(rx_dv),\r
+         .rx_er(rx_er),\r
+         .col(col),\r
+         .crs(crs),\r
+         // Input signals to the CPU Interface\r
+         .haddr(haddr),\r
+         .hdatain(hdatain),\r
+         .hcs_n(hcs_n),\r
+         .hwrite_n(hwrite_n),\r
+         .hread_n(hread_n),\r
+     \r
+         // Input signals to the MII Management Interface\r
+     \r
+         // Input signals to the Tx MAC FIFO Interface\r
+         .tx_fifodata(tx_fifodata),\r
+         .tx_fifoavail(tx_fifoavail),\r
+         .tx_fifoeof(tx_fifoeof),\r
+         .tx_fifoempty(tx_fifoempty),\r
+         .tx_sndpaustim(tx_sndpaustim),\r
+         .tx_sndpausreq(tx_sndpausreq),\r
+         .tx_fifoctrl(tx_fifoctrl),\r
+     \r
+         // Input signals to the Rx MAC FIFO Interface\r
+         .rx_fifo_full(rx_fifo_full),\r
+         .ignore_pkt(ignore_pkt),\r
+     \r
+         // Output signals from the GMII\r
+         .txd(txd),\r
+         .tx_en(tx_en),\r
+         .tx_er(tx_er),\r
+     \r
+         // Output signals from the CPU Interface\r
+         .hdataout(hdataout),\r
+         .hdataout_en_n(hdataout_en_n),\r
+         .hready_n(hready_n),\r
+         .cpu_if_gbit_en(cpu_if_gbit_en),\r
+     \r
+         // Output signals from the MII Management Interface\r
+     \r
+         // Output signals from the Tx MAC FIFO Interface\r
+         .tx_macread(tx_macread),\r
+         .tx_discfrm(tx_discfrm),\r
+         .tx_staten(tx_staten),\r
+         .tx_statvec(tx_statvec),\r
+         .tx_done(tx_done),\r
+     \r
+         // Output signals from the Rx MAC FIFO Interface\r
+         .rx_fifo_error(rx_fifo_error),\r
+         .rx_stat_vector(rx_stat_vector),\r
+         .rx_dbout(rx_dbout),\r
+         .rx_write(rx_write),\r
+         .rx_stat_en(rx_stat_en),\r
+         .rx_eof(rx_eof),\r
+         .rx_error(rx_error)\r
+     );\r
+endmodule\r

diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/top/ts_mac_core_only_top.vhd b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/top/ts_mac_core_only_top.vhd
new file mode 100644 (file)
index 0000000..328d770
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/top/ts_mac_core_only_top.vhd
@@ -0,0 +1,201 @@
+-------------------------------------------------------------------------------\r
+-- Verilog module generated by IPExpress    \r
+-- Filename: ts_mac_core_only_top.vhd\r
+-- Copyright(c) 2005 Lattice Semiconductor Corporation. All rights reserved.   \r
+-------------------------------------------------------------------------------\r
+\r
+--WARNING - Changes to this file should be performed by re-running IPexpress\r
+--or modifying the .LPC file and regenerating the core.  Other changes may lead\r
+--to inconsistent simulation and/or implemenation results \r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_arith.all;\r
+\r
+entity ts_mac_core_only_top is \r
+port(\r
+   --------------- clock and reset port declarations ------------------\r
+   hclk             : in std_logic;\r
+   txmac_clk        : in std_logic;\r
+   rxmac_clk        : in std_logic;\r
+   reset_n          : in std_logic;\r
+   txmac_clk_en     : in std_logic;\r
+   rxmac_clk_en     : in std_logic;\r
+   \r
+   ------------------- Input signals to the GMII ----------------\r
+   rxd              : in std_logic_vector(7 downto 0);\r
+   rx_dv            : in std_logic;\r
+   rx_er            : in std_logic;\r
+   col              : in std_logic;\r
+   crs              : in std_logic;\r
+   \r
+   -------------------- Input signals to the CPU I/F -------------------\r
+   haddr            : in std_logic_vector(7 downto 0);\r
+   hdatain          : in std_logic_vector(7 downto 0);\r
+   hcs_n            : in std_logic;\r
+   hwrite_n         : in std_logic;\r
+   hread_n          : in std_logic;\r
+   -------------------- Input signals to the Tx MAC FIFO Interface----\r
+   tx_fifodata      : in std_logic_vector(7 downto 0);\r
+   tx_fifoavail     : in std_logic;\r
+   tx_fifoeof       : in std_logic;\r
+   tx_fifoempty     : in std_logic;\r
+   tx_sndpaustim    : in std_logic_vector(15 downto 0);\r
+   tx_sndpausreq    : in std_logic;\r
+   tx_fifoctrl      : in std_logic;\r
+    \r
+   -------------------- Input signals to the Rx MAC FIFO Interface ----\r
+   rx_fifo_full     : in std_logic;\r
+   ignore_pkt       : in std_logic;\r
+         \r
+   -------------------- Output signals from the GMII -----------------------\r
+   txd              : out std_logic_vector(7 downto 0);  \r
+   tx_en            : out std_logic;\r
+   tx_er            : out std_logic;\r
+   -------------------- Output signals from the CPU I/F -------------------\r
+   hdataout         : out std_logic_vector(7 downto 0);\r
+   hdataout_en_n    : out std_logic;\r
+   hready_n         : out std_logic;\r
+   cpu_if_gbit_en   : out std_logic;\r
+     \r
+   ---------------- Output signals from the Tx MAC FIFO I/F ---------------\r
+   tx_macread       : out std_logic;\r
+   tx_discfrm       : out std_logic;\r
+   tx_staten        : out std_logic;\r
+   tx_done          : out std_logic;\r
+   tx_statvec       : out std_logic_vector(30 downto 0);\r
+     \r
+   ---------------- Output signals from the Rx MAC FIFO I/F --------------- \r
+   rx_fifo_error    : out std_logic;\r
+   rx_stat_vector   : out std_logic_vector(31 downto 0);\r
+   rx_dbout         : out std_logic_vector(7 downto 0);\r
+   rx_write         : out std_logic;\r
+   rx_stat_en       : out std_logic;\r
+   rx_eof           : out std_logic;\r
+   rx_error         : out std_logic\r
+     \r
+   );\r
+end ts_mac_core_only_top;\r
+  \r
+architecture ts_mac_core_only_top_a of ts_mac_core_only_top is\r
+component tsmac            \r
+   port (                            \r
+   --------------- clock and reset port declarations ------------------\r
+   hclk            : in std_logic;\r
+   txmac_clk       : in std_logic;\r
+   rxmac_clk       : in std_logic;\r
+   reset_n         : in std_logic;\r
+   txmac_clk_en     : in std_logic;\r
+   rxmac_clk_en     : in std_logic;\r
+   \r
+   ------------------- Input signals to the GMII ----------------\r
+   rxd              : in std_logic_vector(7 downto 0);\r
+   rx_dv            : in std_logic;\r
+   rx_er            : in std_logic;\r
+   col              : in std_logic;\r
+   crs              : in std_logic;\r
+     \r
+   -------------------- Input signals to the CPU I/F -------------------\r
+   haddr           : in std_logic_vector(7 downto 0);\r
+   hdatain         : in std_logic_vector(7 downto 0);\r
+   hcs_n           : in std_logic;\r
+   hwrite_n        : in std_logic;\r
+   hread_n         : in std_logic;\r
+   \r
+   ---------------- Input signals to the Tx MAC FIFO I/F ---------------\r
+   tx_fifodata     : in std_logic_vector(7 downto 0);\r
+   tx_fifoavail    : in std_logic;\r
+   tx_fifoeof      : in std_logic;\r
+   tx_fifoempty    : in std_logic;\r
+   tx_sndpaustim   : in std_logic_vector(15 downto 0);\r
+   tx_sndpausreq   : in std_logic;\r
+   tx_fifoctrl     : in std_logic;\r
+     \r
+   ---------------- Input signals to the Rx MAC FIFO I/F --------------- \r
+   rx_fifo_full    : in std_logic;\r
+   ignore_pkt      : in std_logic;\r
+     \r
+   -------------------- Output signals from the GMII -----------------------\r
+   txd             : out std_logic_vector(7 downto 0);  \r
+   tx_en           : out std_logic;\r
+   tx_er           : out std_logic;\r
+     \r
+   -------------------- Output signals from the CPU I/F -------------------\r
+   hdataout         : out std_logic_vector(7 downto 0);\r
+   hdataout_en_n    : out std_logic;\r
+   hready_n         : out std_logic;\r
+   cpu_if_gbit_en   : out std_logic;\r
+     \r
+   ---------------- Output signals from the Tx MAC FIFO I/F --------------- \r
+   tx_macread       : out std_logic;\r
+   tx_discfrm       : out std_logic;\r
+   tx_staten        : out std_logic;\r
+   tx_done          : out std_logic;\r
+   tx_statvec       : out std_logic_vector(30 downto 0);\r
+     \r
+   ---------------- Output signals from the Rx MAC FIFO I/F ---------------   \r
+   rx_fifo_error    : out std_logic;\r
+   rx_stat_vector   : out std_logic_vector(31 downto 0);\r
+   rx_dbout         : out std_logic_vector(7 downto 0);\r
+   rx_write         : out std_logic;\r
+   rx_stat_en       : out std_logic;\r
+   rx_eof           : out std_logic;\r
+   rx_error         : out std_logic\r
+   );\r
+end component; \r
+    \r
+begin       \r
+\r
+U1_ts_mac_core_only_core : tsmac            \r
+port map (                          \r
+   hclk                => hclk,     \r
+   txmac_clk           => txmac_clk, \r
+   rxmac_clk           => rxmac_clk, \r
+   reset_n             => reset_n,  \r
+   txmac_clk_en        =>txmac_clk_en,\r
+   rxmac_clk_en        =>rxmac_clk_en,\r
+   rxd                 => rxd,\r
+   rx_dv               => rx_dv,\r
+   rx_er               => rx_er,\r
+   col                 => col,      \r
+   crs                 => crs,      \r
+     \r
+   haddr               => haddr,    \r
+   hdatain             => hdatain,  \r
+   hcs_n               => hcs_n,    \r
+   hwrite_n            => hwrite_n, \r
+   hread_n             => hread_n,  \r
+  \r
+  \r
+   tx_fifodata         => tx_fifodata,    \r
+   tx_fifoavail        => tx_fifoavail,   \r
+   tx_fifoeof          => tx_fifoeof,     \r
+   tx_fifoempty        => tx_fifoempty,   \r
+   tx_sndpaustim       => tx_sndpaustim,  \r
+   tx_sndpausreq       => tx_sndpausreq,  \r
+   tx_fifoctrl         => tx_fifoctrl,    \r
+   rx_fifo_full        => rx_fifo_full,   \r
+   ignore_pkt          => ignore_pkt,     \r
+   txd                 => txd,\r
+   tx_en               => tx_en,          \r
+   tx_er               => tx_er,          \r
+   hdataout            => hdataout,       \r
+   hdataout_en_n       => hdataout_en_n,  \r
+   hready_n            => hready_n,       \r
+   cpu_if_gbit_en      => cpu_if_gbit_en, \r
+   \r
+   tx_macread          => tx_macread,    \r
+   tx_discfrm          => tx_discfrm,    \r
+   tx_staten           => tx_staten ,    \r
+   tx_statvec          => tx_statvec,    \r
+   tx_done             => tx_done,       \r
+   rx_fifo_error       => rx_fifo_error, \r
+   rx_stat_vector      => rx_stat_vector, \r
+   rx_dbout            => rx_dbout,      \r
+   rx_write            => rx_write,      \r
+   rx_stat_en          => rx_stat_en,    \r
+   rx_eof              => rx_eof,        \r
+   rx_error            => rx_error       \r
+ );   \r
+ \r
+end ts_mac_core_only_top_a;\r
+  \r

diff --git a/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/top/ts_mac_top.v b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/top/ts_mac_top.v
new file mode 100644 (file)
index 0000000..c795296
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/ts_mac_eval/tsmac/src/rtl/top/ts_mac_top.v
@@ -0,0 +1,544 @@
+// ===========================================================================\r
+// Verilog module generated by IPexpress\r
+// Filename: ts_mac_top.v\r
+// Copyright 2005 (c) Lattice Semiconductor Corporation. All rights reserved.\r
+// ===========================================================================\r
+//\r
+\r
+`timescale 1 ns/ 1ns\r
+module ts_mac_top (\r
+\r
+    // clock, clock enables and reset\r
+    gtx_clk,\r
+    tx_clk,\r
+\r
+    txmac_clk_en,\r
+    rxmac_clk_en,\r
+\r
+    sys_clk,\r
+    hclk,\r
+    rx_clk,\r
+    rxmac_clk,\r
+    txmac_clk,\r
+    reset_n,\r
+\r
+    // Input signals to the GMII\r
+    rx_dv,\r
+    rx_er,\r
+    rxd,\r
+    col,\r
+    crs,\r
+\r
+    // orcastra interface\r
+    pc_clk,\r
+    pc_datain,\r
+    pc_ready,\r
+    pc_dataout,\r
+    pc_error,\r
+    pc_retry,\r
+    pc_ack,\r
+    jtag_present,\r
+    jtag_parallel,\r
+    // JTAG Port\r
+    tdi,\r
+    tck,\r
+    tms,\r
+    tdo,\r
+\r
+    // Output signals from the MII Management Interface\r
+\r
+    // Output signals from the GMII\r
+    tx_en,\r
+    tx_er,\r
+    txd,\r
+\r
+    // These are test points on the evaluation board\r
+    tx_fifodata,\r
+    tx_fifoavail,\r
+    tx_fifoeof,\r
+    tx_fifoempty,\r
+    tx_sndpausreq,\r
+    tx_fifoctrl,\r
+    tx_fifo_full_ri,\r
+    tx_macread,\r
+    tx_discfrm,\r
+    tx_staten,\r
+    tx_done,\r
+    gbit_en,\r
+    phy_reset_n\r
+);\r
+\r
+// ---------------- clock, clock enables and reset inputs -----------------\r
+output                gtx_clk;            // Gigabit Transmit clock\r
+output                rxmac_clk;          // Rx_clock out to App I/F\r
+output                txmac_clk;          // Tx_clock out to App I/F\r
+input                 tx_clk;             // Transmit clock\r
+\r
+input                 txmac_clk_en;\r
+input                 rxmac_clk_en;\r
+\r
+\r
+input                 sys_clk;            // system clock\r
+input                 rx_clk;             // Receive clock\r
+input                 reset_n;            // Global reset\r
+\r
+// ----------------------- Input signals to the GMII -------------------\r
+input  [7:0]          rxd  /* synthesis syn_useioff=0 */;  // Receive data\r
+input                 rx_dv/* synthesis syn_useioff=0 */;  // Receive data valid\r
+input                 rx_er/* synthesis syn_useioff=0 */;  // Receive data error\r
+\r
+input                 col;                                 // Collision detect\r
+input                 crs;                                 // Carrier Sense\r
+// ------------------ Input/ouputs signals to the Orcastra Interface ----\r
+input                 pc_clk;\r
+input                 pc_datain;\r
+input                 pc_ready;\r
+output                pc_dataout;\r
+output                pc_error;\r
+output                pc_retry;\r
+output                pc_ack;\r
+output                jtag_present;\r
+input                 jtag_parallel;\r
+// ------------------ Input/output signals to the JTAG Port --------------\r
+input                 tdi;\r
+input                 tck;\r
+input                 tms;\r
+output                tdo;\r
+\r
+// -------------------- Output signals from the GMII -----------------------\r
+output [7:0]          txd;                // Transmit data\r
+output                tx_en;              // Transmit Enable\r
+output                tx_er;              // Transmit Error\r
+\r
+// These are test points on the evaluation board\r
+output [7:0]          tx_fifodata;\r
+output                tx_fifoavail;\r
+output                tx_fifoeof;\r
+output                tx_fifoempty;\r
+output                tx_sndpausreq;\r
+output                tx_fifoctrl;\r
+output                tx_fifo_full_ri;\r
+output                tx_macread;\r
+output                tx_discfrm;\r
+output                tx_staten;\r
+output                tx_done;\r
+output                gbit_en;\r
+\r
+// -------------------- Input signals to the CPU I/F -------------------\r
+input                 hclk;        // Clock\r
+\r
+// -------------------- Input/Output signals from the MII I/F ----------------\r
+\r
+// -------------------- Misc Output signals to be used with eval board only --\r
+output                phy_reset_n;  // used to reset PHY device\r
+parameter pdevice_family = "ECP5UM";\r
+//////////////////////////////////////////////////////////////////////////////\r
+// Internal wires related to fifo client interfaces and host bus interface\r
+//////////////////////////////////////////////////////////////////////////////\r
+\r
+// -------------------- Input signals to the CPU I/F -------------------\r
+wire  [7:0]                     haddr;              // Address Bus\r
+wire  [7:0]                     hdatain;            // Input data Bus\r
+wire                            hcs_n;              // Chip select\r
+wire                            hwrite_n;           // Register write\r
+wire                            hread_n;            // Register read\r
+\r
+// -------------------- Output signals from the CPU I/F -------------------\r
+wire [7:0]                      hdataout;           // Output data Bus\r
+wire                            hdataout_en_n;      // Data Out Enable\r
+wire                            hready_n;           // Ready signal\r
+\r
+// ---------------- Input signals to the Tx MAC FIFO I/F ---------------\r
+wire  [7:0]                     tx_fifodata;        // Data Input from FIFO\r
+wire                            tx_fifoavail;       // Data Available in FIFO\r
+wire                            tx_fifoeof;         // End of Frame\r
+wire                            tx_fifoempty;       // FIFO Empty\r
+wire  [15:0]                    tx_sndpaustim;      // Pause frame parameter\r
+wire                            tx_sndpausreq;      // Transmit PAUSE frame\r
+wire                            tx_fifoctrl;        // Control frame or Not\r
+\r
+// ---------------- Input signals to the Rx MAC FIFO I/F ---------------\r
+wire                            rx_fifo_full;       // Receive FIFO Full\r
+wire                            ignore_pkt;         // Ignore the frame\r
+\r
+// ---------------- Output signals from the Tx MAC FIFO I/F ---------------\r
+wire                            tx_macread;         // Read FIFO\r
+wire                            tx_discfrm;         // Discard Frame\r
+wire                            tx_staten;          // Status Vector Valid\r
+wire                            tx_done;            // Transmit of Frame done\r
+wire [30:0]                     tx_statvec;         // Tx Status Vector\r
+\r
+// ---------------- Output signals from the Rx MAC FIFO I/F ---------------\r
+wire                            rx_fifo_error;      // FIFO full detected\r
+wire [31:0]                     rx_stat_vector;     // Rx Status Vector\r
+wire [7:0]                      rx_dbout;           // Data Output to FIFO\r
+wire                            rx_write;           // Write FIFO\r
+wire                            rx_stat_en;         // Status Vector Valid\r
+wire                            rx_eof;             // Entire frame written\r
+wire                            rx_error;           // Erroneous frame\r
+\r
+wire                           rx_write_e;         // Write FIFO conditioned with rx enable\r
+wire                           tx_macread_e;       // Read FIFO conditioned with tx enable\r
+//////////////////////////////////////////////////////////////////////////////\r
+// internal wires related to register interface, and orcastra interface\r
+//////////////////////////////////////////////////////////////////////////////\r
+\r
+wire         pkt_add_swap_ri;\r
+wire         pkt_loop_enb_ri;\r
+wire         pkt_loop_clksel_ri;\r
+wire         phy_reset_n_ri;\r
+wire [15:0]  tx_sndpaustim_ri;\r
+wire         tx_sndpausreq_ri;\r
+wire         tx_fifoctrl_ri;\r
+wire         rx_fifo_full_ri;\r
+wire         tx_fifo_empty_ri;\r
+wire         ignore_next_pkt_ri;\r
+wire [8:0]   aff_thrhd;\r
+wire [8:0]   afe_thrhd;\r
+\r
+wire [7:0]   us_rdata;\r
+wire         us_ack;\r
+wire [7:0]   us_wdata;\r
+wire         us_rdy;\r
+wire         us_wr;\r
+wire [17:0]  us_addr;\r
+wire [1:0]   us_size;\r
+\r
+wire         rxc_clk;\r
+wire         txc_clk;\r
+\r
+// from MAC to status reg bits in reg_intf\r
+wire         rx_error_ri;\r
+wire         rx_fifo_error_ri;\r
+wire         tx_disfrm_ri;\r
+wire         tx_fifo_full_ri;\r
+\r
+wire         gbit_en_wire /*synthesis syn_keep=1 */;  // 1G enable - MAC clock select\r
+\r
+// ------------------ signals related to the Orcastra Interface -------\r
+wire         pc_clk_jtag;\r
+wire         pc_clk_mux /*synthesis syn_keep=1 */;\r
+wire         pc_datain_jtag;\r
+wire         pc_datain_mux;\r
+wire         pc_ready_jtag;\r
+wire         pc_ready_mux;\r
+\r
+assign phy_reset_n = phy_reset_n_ri; // this output is used only when user is using an eval board.\r
+assign gbit_en = gbit_en_wire;\r
+\r
+\r
+//////////////////////////////////////////////////////////////////////////////\r
+// Internal wires related to GMII I/O\r
+reg   [7:0]  rxd_pos;\r
+reg   [3:0]  rxd_neg;\r
+reg          rx_dv_pos;\r
+reg          rx_dv_neg;\r
+reg          rx_er_pos;\r
+reg          rx_er_neg;\r
+wire [7:0]   txd_pos;\r
+wire [3:0]   txd_neg;\r
+wire         tx_en_d;\r
+wire         tx_er_d;\r
+\r
+reg  [7:4]   txd_pos_x;\r
+reg          tx_en_d_x;\r
+reg          tx_er_d_x;\r
+wire [3:0]   txd_int;\r
+reg  [3:0]   txd_10_100;\r
+reg          tx_en_10_100;\r
+reg          tx_er_10_100;\r
+reg  [7:0]   txd_1g;\r
+reg          tx_en_1g;\r
+reg          tx_er_1g;\r
+\r
+// Internal wires related to clock synthesis\r
+reg           tx_clk_div2;             // tx_clk divided by 2\r
+reg           rx_clk_div2;             // rx_clk divided by 2\r
+wire          txmac_clk_c /*synthesis syn_keep=1 */; // Internal txmac_clk\r
+wire          rxmac_clk_c /*synthesis syn_keep=1 */; // Internal rxmac_clk\r
+wire          gtx_clk_src; // for 1GBE\r
+wire          txmac_clk_1g; //\r
+wire          txmac_ref /*synthesis syn_keep=1 */;\r
+\r
+\r
+//////////////////////////////////////////////////////////////////////////////\r
+// Instantiate PLLs, DCS Muxes, and other buffers\r
+\r
+    assign rx_write_e   = rx_write & rxmac_clk_en;\r
+    assign tx_macread_e = tx_macread & txmac_clk_en;\r
+\r
+// SGMII_TSMAC or GBE_MAC\r
+assign rxmac_clk_c = rx_clk;\r
+\r
+// This mux is added to allow a selection of the txmac_clk source\r
+assign txmac_clk_c = pkt_loop_clksel_ri ? rx_clk : sys_clk;\r
+assign gtx_clk_src = txmac_clk_c;\r
+assign rxmac_clk = rxmac_clk_c;\r
+assign txmac_clk = txmac_clk_c;\r
+\r
+\r
+// GMII inputs RXD[3:0], RX_DV RX_ER are sampled on\r
+// both clock edges of rxmac_clk_c\r
+// These flip-flops must be placed close to the associated I/O pins.\r
+// They are given a COMP name here and located in a specific component\r
+// in the preference file.\r
+\r
+always @(posedge rxmac_clk_c or negedge reset_n) begin\r
+  if (~reset_n) begin\r
+     rx_dv_pos    <= 1'b0;\r
+     rx_er_pos    <= 1'b0;\r
+     rxd_pos[7:0] <= 8'h00;\r
+  end\r
+  else begin\r
+     rx_dv_pos    <= rx_dv;\r
+     rx_er_pos    <= rx_er;\r
+     rxd_pos[7:0] <= rxd[7:0];\r
+  end\r
+end\r
+\r
+always @(negedge rxmac_clk_c or negedge reset_n) begin\r
+  if (~reset_n) begin\r
+     rx_dv_neg    <= 1'b0;\r
+     rx_er_neg    <= 1'b0;\r
+     rxd_neg[3:0] <= 4'h0;\r
+  end\r
+  else begin\r
+     rx_dv_neg    <= rx_dv;\r
+     rx_er_neg    <= rx_er;\r
+     rxd_neg[3:0] <= rxd[3:0];\r
+  end\r
+end\r
+\r
+// GBE_MAC OR SGMII_TSMAC\r
+always @(posedge txmac_clk_c or negedge reset_n) begin\r
+  if (~reset_n) begin\r
+     txd_1g    <=  8'h00;\r
+     tx_en_1g  <=  1'b0;\r
+     tx_er_1g  <=  1'b0;\r
+     end\r
+  else begin\r
+     txd_1g    <=  txd_pos;\r
+     tx_en_1g  <=  tx_en_d;\r
+     tx_er_1g  <=  tx_er_d;\r
+     end\r
+end\r
+\r
+assign txd   = txd_1g;\r
+assign tx_en = tx_en_1g;\r
+assign tx_er = tx_er_1g;\r
+\r
+//Note: User may need to invert clock to adjust timing\r
+assign gtx_clk = gtx_clk_src;\r
+\r
+assign pc_datain_mux = (jtag_parallel) ? pc_datain_jtag : pc_datain;\r
+assign pc_ready_mux  = (jtag_parallel) ? pc_ready_jtag  : pc_ready;\r
+assign pc_clk_mux    = (jtag_parallel) ? pc_clk_jtag    : pc_clk;\r
+\r
+////////////////////////////////////////////////////////////////////////////\r
+// Instantiate modules\r
+ts_mac_core_only_top U1_ts_mac_core (\r
+    // clock and reset\r
+    .hclk(hclk),\r
+    .txmac_clk(txmac_clk_c),\r
+    .rxmac_clk(rxmac_clk_c),\r
+    .reset_n(reset_n),\r
+    .txmac_clk_en(txmac_clk_en),\r
+    .rxmac_clk_en(rxmac_clk_en),\r
+\r
+    // Input signals to the GMII\r
+    .rxd(rxd_pos),\r
+    .rx_dv(rx_dv_pos),\r
+    .rx_er(rx_er_pos),\r
+    .col(col),\r
+    .crs(crs),\r
+\r
+    // Input signals to the CPU Interface\r
+    .haddr(haddr),\r
+    .hdatain(hdatain),\r
+    .hcs_n(hcs_n),\r
+    .hwrite_n(hwrite_n),\r
+    .hread_n(hread_n),\r
+\r
+    // Input signals to the MII Management Interface\r
+\r
+    // Input signals to the Tx MAC FIFO Interface\r
+    .tx_fifodata(tx_fifodata),\r
+    .tx_fifoavail(tx_fifoavail),\r
+    .tx_fifoeof(tx_fifoeof),\r
+    .tx_fifoempty(tx_fifoempty),\r
+    .tx_sndpaustim(tx_sndpaustim),\r
+    .tx_sndpausreq(tx_sndpausreq),\r
+    .tx_fifoctrl(tx_fifoctrl),\r
+\r
+    // Input signals to the Rx MAC FIFO Interface\r
+    .rx_fifo_full(rx_fifo_full),\r
+    .ignore_pkt(ignore_pkt),\r
+\r
+    // Output signals from the GMII\r
+    .txd(txd_pos),\r
+    .tx_en(tx_en_d),\r
+    .tx_er(tx_er_d),\r
+\r
+    // Output signals from the CPU Interface\r
+    .hdataout(hdataout),\r
+    .hdataout_en_n(hdataout_en_n),\r
+    .hready_n(hready_n),\r
+    .cpu_if_gbit_en(gbit_en_wire),\r
+\r
+    // Output signals from the MII Management Interface\r
+\r
+    // Output signals from the Tx MAC FIFO Interface\r
+    .tx_macread(tx_macread),\r
+    .tx_discfrm(tx_discfrm),\r
+    .tx_staten(tx_staten),\r
+    .tx_statvec(tx_statvec),\r
+    .tx_done(tx_done),\r
+\r
+    // Output signals from the Rx MAC FIFO Interface\r
+    .rx_fifo_error(rx_fifo_error),\r
+    .rx_stat_vector(rx_stat_vector),\r
+    .rx_dbout(rx_dbout),\r
+    .rx_write(rx_write),\r
+    .rx_stat_en(rx_stat_en),\r
+    .rx_eof(rx_eof),\r
+    .rx_error(rx_error)\r
+);\r
+\r
+\r
+tst_logic #(.pdevice_family(pdevice_family))\r
+    u1_tst_logic (\r
+    // -------\r
+    // inputs\r
+    // -------\r
+    // Clock and Reset\r
+    .reset_n                (reset_n),\r
+    .txmac_clk              (txmac_clk_c),\r
+    .rxmac_clk              (rxmac_clk_c),\r
+    // Clock enables\r
+    .txmac_clk_en           (txmac_clk_en),\r
+    .rxmac_clk_en           (rxmac_clk_en),\r
+    // from tsmac core\r
+    .rx_write               (rx_write_e),\r
+    .tx_macread             (tx_macread_e),\r
+    .rx_dbout               (rx_dbout),\r
+    .rx_eof                 (rx_eof),\r
+    .rx_error               (rx_error),\r
+    .rx_fifo_error          (rx_fifo_error),\r
+    .tx_done                (tx_done),\r
+    .tx_disfrm              (tx_discfrm),\r
+    // from reg_intf\r
+    .pkt_add_swap_ri        (pkt_add_swap_ri),\r
+    .pkt_loop_enb_ri        (pkt_loop_enb_ri),\r
+    .tx_sndpaustim_ri       (tx_sndpaustim_ri),\r
+    .tx_sndpausreq_ri       (tx_sndpausreq_ri),\r
+    .tx_fifoctrl_ri         (tx_fifoctrl_ri),\r
+    .rx_fifo_full_ri        (rx_fifo_full_ri),\r
+    .tx_fifo_empty_ri       (tx_fifo_empty_ri),\r
+    .ignore_next_pkt_ri     (ignore_next_pkt_ri),\r
+    .aff_thrhd              (aff_thrhd[8:0]),\r
+    .afe_thrhd              (afe_thrhd[8:0]),\r
+    // -------\r
+    // outputs\r
+    // -------\r
+    // to tsmac core\r
+    .tx_fifodata            (tx_fifodata),\r
+    .tx_fifoeof             (tx_fifoeof),\r
+    .tx_fifoavail           (tx_fifoavail),\r
+    .tx_fifoempty           (tx_fifoempty),\r
+    .tx_sndpaustim          (tx_sndpaustim),\r
+    .tx_sndpausreq          (tx_sndpausreq),\r
+    .tx_fifoctrl            (tx_fifoctrl),\r
+    .rx_fifo_full           (rx_fifo_full),\r
+    .ignore_next_pkt        (ignore_pkt),\r
+    // to reg_intf\r
+    .rxc_clk               (rxc_clk),\r
+    .txc_clk               (txc_clk),\r
+    .rx_error_ri            (rx_error_ri),\r
+    .rx_fifo_error_ri       (rx_fifo_error_ri),\r
+    .tx_disfrm_ri           (tx_disfrm_ri),\r
+    .tx_fifo_full_ri        (tx_fifo_full_ri)\r
+);\r
+\r
+orcastra orcastra (\r
+    .reset_n (reset_n),\r
+    .hclk (hclk),\r
+    .pc_clk (pc_clk_mux),\r
+    .pc_datain (pc_datain_mux),\r
+    .pc_ready (pc_ready_mux),\r
+    .hdataout (hdataout),\r
+    .hready_n (hready_n),\r
+    .us_rdata (us_rdata),\r
+    .us_ack (us_ack),\r
+    .us_wdata (us_wdata),\r
+    .us_rdy (us_rdy),\r
+    .us_wr (us_wr),\r
+    .us_addr (us_addr),\r
+    .us_size (us_size),\r
+    .hdatain (hdatain),\r
+    .hcs_n (hcs_n),\r
+    .hread_n (hread_n),\r
+    .hwrite_n (hwrite_n),\r
+    .haddr (haddr),\r
+    .pc_dataout (pc_dataout),\r
+    .pc_error (pc_error),\r
+    .pc_retry (pc_retry),\r
+    .pc_ack (pc_ack)\r
+);\r
+\r
+reg_intf reg_intf (\r
+    .reset_n (reset_n),\r
+    .hclk (hclk),\r
+    .rxc_clk (rxc_clk),\r
+    .txc_clk (txc_clk),\r
+    .us_wdata (us_wdata),\r
+    .us_rdy (us_rdy),\r
+    .us_wr (us_wr),\r
+    .us_addr (us_addr),\r
+    .us_size (us_size),\r
+    .rx_error_ri (rx_error_ri),\r
+    .rx_fifo_error_ri (rx_fifo_error_ri),\r
+    .tx_disfrm_ri (tx_disfrm_ri),\r
+    .tx_fifo_full_ri (tx_fifo_full_ri),\r
+    .rx_stat_vec (rx_stat_vector[31:0]),\r
+    .rx_stat_en (rx_stat_en),\r
+    .tx_stat_vec (tx_statvec[30:0]),\r
+    .tx_stat_en (tx_staten),\r
+    .pkt_add_swap_ri (pkt_add_swap_ri),\r
+    .pkt_loop_enb_ri (pkt_loop_enb_ri),\r
+    .pkt_loop_clksel_ri (pkt_loop_clksel_ri),\r
+    .phy_reset_n_ri (phy_reset_n_ri),\r
+    .tx_sndpaustim_ri (tx_sndpaustim_ri),\r
+    .tx_sndpausreq_ri (tx_sndpausreq_ri),\r
+    .tx_fifoctrl_ri (tx_fifoctrl_ri),\r
+    .rx_fifo_full_ri (rx_fifo_full_ri),\r
+    .tx_fifo_empty_ri (tx_fifo_empty_ri),\r
+    .ignore_next_pkt_ri (ignore_next_pkt_ri),\r
+    .aff_thrhd (aff_thrhd[8:0]),\r
+    .afe_thrhd (afe_thrhd[8:0]),\r
+    .us_err (), //no_connect\r
+    .us_irq (), //no_connect\r
+    .us_ack (us_ack),\r
+    .us_rdata (us_rdata)\r
+);\r
+\r
+\r
+\r
+JTAG_ECP5UM JTAG_ECP5UM\r
+    (\r
+    .grst_ni     (reset_n),\r
+    .tck         (tck),\r
+    .tms         (tms),\r
+    .tdi         (tdi),\r
+    .tdo         (tdo),\r
+    .PC_Clk      (pc_clk_jtag),\r
+    .PC_Data_In         (pc_datain_jtag),\r
+    .PC_Ready    (pc_ready_jtag),\r
+    .PC_Reset    (),\r
+    .Cnt         (),\r
+    .PC_Data_Out (pc_dataout),\r
+    .PC_Ack     (pc_ack),\r
+    .PC_Error   (pc_error)\r
+);\r
+\r
+\r
+endmodule\r

diff --git a/gbe/cores/sgmii/tsmac/tsmac.fdc b/gbe/cores/sgmii/tsmac/tsmac.fdc
new file mode 100644 (file)
index 0000000..6fbcac9
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/tsmac.fdc
@@ -0,0 +1,2 @@
+###==== Start Configuration
+

diff --git a/gbe/cores/sgmii/tsmac/tsmac.lpc b/gbe/cores/sgmii/tsmac/tsmac.lpc
new file mode 100644 (file)
index 0000000..5c8ae17
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/tsmac.lpc
@@ -0,0 +1,37 @@
+[Device]
+Family=sa5p00m
+PartType=LFE5UM-85F
+PartName=LFE5UM-85F-8BG756C
+SpeedGrade=8
+Package=CABGA756
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=IPCFG
+CoreStatus=Demo
+CoreName=Tri-Speed Ethernet MAC
+CoreRevision=4.1
+ModuleName=tsmac
+SourceFormat=vhdl
+ParameterFileVersion=1.0
+Date=04/29/2019
+Time=13:44:50
+
+[Parameters]
+MIIM=No
+MODE=SGMII easy connect
+MODS_TOOL=1
+ALDC_TOOL=0
+MULT_WB=NO
+LOOPBACK=NO
+STAT_REGS=NO
+CORE_SYNP=1
+
+[Files]
+Synthesis=
+Simulation=
+Logical=
+Physical=
+Misc=

diff --git a/gbe/cores/sgmii/tsmac/tsmac.ngd b/gbe/cores/sgmii/tsmac/tsmac.ngd
new file mode 100644 (file)
index 0000000..3fe1735
Binary files /dev/null and b/gbe/cores/sgmii/tsmac/tsmac.ngd differ

diff --git a/gbe/cores/sgmii/tsmac/tsmac.ngo b/gbe/cores/sgmii/tsmac/tsmac.ngo
new file mode 100644 (file)
index 0000000..50ccd6f
Binary files /dev/null and b/gbe/cores/sgmii/tsmac/tsmac.ngo differ

diff --git a/gbe/cores/sgmii/tsmac/tsmac.v b/gbe/cores/sgmii/tsmac/tsmac.v
new file mode 100644 (file)
index 0000000..569c933
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/tsmac.v
@@ -0,0 +1,212 @@
+//=============================================================================\r
+// Verilog module generated by IPExpress    \r
+// Filename: USERNAME.v                                          \r
+// Copyright(c) 2006 Lattice Semiconductor Corporation. All rights reserved.   \r
+//=============================================================================\r
+\r
+/* WARNING - Changes to this file should be performed by re-running IPexpress\r
+or modifying the .LPC file and regenerating the core.  Other changes may lead\r
+to inconsistent simulation and/or implemenation results */\r
+`timescale 1 ns/ 1ns\r
+module tsmac (\r
+       // clock and reset\r
+       hclk,\r
+       txmac_clk,\r
+       rxmac_clk,\r
+       reset_n,\r
+       txmac_clk_en,\r
+       rxmac_clk_en,\r
+\r
+       // Input signals to the GMII\r
+       rxd,\r
+       rx_dv,\r
+       rx_er,\r
+       col,\r
+       crs,\r
+       // Input signals to the CPU Interface\r
+       haddr,\r
+       hdatain,\r
+       hcs_n,\r
+       hwrite_n,\r
+       hread_n,\r
+       \r
+       // Input signals to the MII Management Interface\r
+     \r
+       // Input signals to the Tx MAC FIFO Interface\r
+       tx_fifodata,\r
+       tx_fifoavail,\r
+       tx_fifoeof,\r
+       tx_fifoempty,\r
+       tx_sndpaustim,\r
+       tx_sndpausreq,\r
+       tx_fifoctrl,\r
+     \r
+       // Input signals to the Rx MAC FIFO Interface\r
+       rx_fifo_full,\r
+       ignore_pkt,\r
+     \r
+       // Output signals from the GMII\r
+       txd,\r
+       tx_en,\r
+       tx_er,\r
+     \r
+       // Output signals from the CPU Interface\r
+       hdataout,\r
+       hdataout_en_n,\r
+       hready_n,\r
+       cpu_if_gbit_en,\r
+     \r
+       // Output signals from the MII Management Interface\r
+     \r
+       // Output signals from the Tx MAC FIFO Interface\r
+       tx_macread,\r
+       tx_discfrm,\r
+       tx_staten,\r
+       tx_statvec,\r
+       tx_done,\r
+     \r
+       // Output signals from the Rx MAC FIFO Interface\r
+       rx_fifo_error,\r
+       rx_stat_vector,\r
+       rx_dbout,\r
+       rx_write,\r
+       rx_stat_en,\r
+       rx_eof,\r
+       rx_error\r
+     );\r
+     \r
+     // ------------------------- clock and reset inputs ---------------------\r
+     input                            hclk;               // clock to the CPU I/F\r
+     input                            txmac_clk;          // clock to the Tx MAC\r
+     input                            rxmac_clk;          // clock to the RX MAC\r
+     input                            reset_n;            // Global reset\r
+     input                            txmac_clk_en;       // clock enable to the Tx MAC\r
+     input                            rxmac_clk_en;       // clock enable to the RX MAC\r
+     \r
+     // ----------------------- Input signals to the GMII -------------------\r
+     input  [7:0]                     rxd;                // Receive data\r
+     input                            rx_dv;              // Receive data valid\r
+     input                            rx_er;              // Receive data error\r
+     input                            col;                // Collision detect\r
+     input                            crs;                // Carrier Sense\r
+     // -------------------- Input signals to the CPU I/F -------------------\r
+     input  [7:0]                     haddr;              // Address Bus\r
+     input  [7:0]                     hdatain;            // Input data Bus\r
+     input                            hcs_n;              // Chip select\r
+     input                            hwrite_n;           // Register write\r
+     input                            hread_n;            // Register read\r
+     \r
+     // -------------------- Input signals to the MII I/F -------------------\r
+\r
+     \r
+     // ---------------- Input signals to the Tx MAC FIFO I/F ---------------\r
+     input  [7:0]                     tx_fifodata;        // Data Input from FIFO\r
+     input                            tx_fifoavail;       // Data Available in FIFO\r
+     input                            tx_fifoeof;         // End of Frame\r
+     input                            tx_fifoempty;       // FIFO Empty\r
+     input  [15:0]                    tx_sndpaustim;      // Pause frame parameter\r
+     input                            tx_sndpausreq;      // Transmit PAUSE frame\r
+     input                            tx_fifoctrl;        // Control frame or Not\r
+     \r
+     // ---------------- Input signals to the Rx MAC FIFO I/F ---------------\r
+     input                            rx_fifo_full;       // Receive FIFO Full\r
+     input                            ignore_pkt;         // Ignore the frame\r
+     \r
+     // -------------------- Output signals from the GMII -----------------------\r
+     output [7:0]                     txd;                // Transmit data\r
+     output                           tx_en;              // Transmit Enable\r
+     output                           tx_er;              // Transmit Error\r
+     \r
+     // -------------------- Output signals from the CPU I/F -------------------\r
+     output [7:0]                     hdataout;           // Output data Bus\r
+     output                           hdataout_en_n;      // Data Out Enable\r
+     output                           hready_n;           // Ready signal\r
+     output                           cpu_if_gbit_en;     // Gig or 10/100 mode\r
+     \r
+     // -------------------- Output signals from the MII I/F -------------------\r
+\r
+     \r
+     // ---------------- Output signals from the Tx MAC FIFO I/F ---------------\r
+     output                           tx_macread;         // Read FIFO\r
+     output                           tx_discfrm;         // Discard Frame\r
+     output                           tx_staten;          // Status Vector Valid\r
+     output                           tx_done;            // Transmit of Frame done\r
+     output [30:0]                    tx_statvec;         // Tx Status Vector\r
+     \r
+     // ---------------- Output signals from the Rx MAC FIFO I/F ---------------\r
+     output                           rx_fifo_error;      // FIFO full detected\r
+     output [31:0]                    rx_stat_vector;     // Rx Status Vector\r
+     output [7:0]                     rx_dbout;           // Data Output to FIFO\r
+     output                           rx_write;           // Write FIFO\r
+     output                           rx_stat_en;         // Status Vector Valid\r
+     output                           rx_eof;             // Entire frame written\r
+     output                           rx_error;           // Erroneous frame\r
+     \r
+     tsmac_core U1_LSC_ts_mac_core ( \r
+\r
+         // clock and reset\r
+         .hclk(hclk),\r
+         .txmac_clk(txmac_clk),\r
+         .rxmac_clk(rxmac_clk),\r
+         .reset_n(reset_n),\r
+         .txmac_clk_en(txmac_clk_en),\r
+         .rxmac_clk_en(rxmac_clk_en),\r
+     \r
+         // Input signals to the GMII\r
+         .rxd(rxd),\r
+         .rx_dv(rx_dv),\r
+         .rx_er(rx_er),\r
+         .col(col),\r
+         .crs(crs),\r
+         // Input signals to the CPU Interface\r
+         .haddr(haddr),\r
+         .hdatain(hdatain),\r
+         .hcs_n(hcs_n),\r
+         .hwrite_n(hwrite_n),\r
+         .hread_n(hread_n),\r
+     \r
+         // Input signals to the MII Management Interface\r
+     \r
+         // Input signals to the Tx MAC FIFO Interface\r
+         .tx_fifodata(tx_fifodata),\r
+         .tx_fifoavail(tx_fifoavail),\r
+         .tx_fifoeof(tx_fifoeof),\r
+         .tx_fifoempty(tx_fifoempty),\r
+         .tx_sndpaustim(tx_sndpaustim),\r
+         .tx_sndpausreq(tx_sndpausreq),\r
+         .tx_fifoctrl(tx_fifoctrl),\r
+     \r
+         // Input signals to the Rx MAC FIFO Interface\r
+         .rx_fifo_full(rx_fifo_full),\r
+         .ignore_pkt(ignore_pkt),\r
+     \r
+         // Output signals from the GMII\r
+         .txd(txd),\r
+         .tx_en(tx_en),\r
+         .tx_er(tx_er),\r
+     \r
+         // Output signals from the CPU Interface\r
+         .hdataout(hdataout),\r
+         .hdataout_en_n(hdataout_en_n),\r
+         .hready_n(hready_n),\r
+         .cpu_if_gbit_en(cpu_if_gbit_en),\r
+     \r
+         // Output signals from the MII Management Interface\r
+     \r
+         // Output signals from the Tx MAC FIFO Interface\r
+         .tx_macread(tx_macread),\r
+         .tx_discfrm(tx_discfrm),\r
+         .tx_staten(tx_staten),\r
+         .tx_statvec(tx_statvec),\r
+         .tx_done(tx_done),\r
+     \r
+         // Output signals from the Rx MAC FIFO Interface\r
+         .rx_fifo_error(rx_fifo_error),\r
+         .rx_stat_vector(rx_stat_vector),\r
+         .rx_dbout(rx_dbout),\r
+         .rx_write(rx_write),\r
+         .rx_stat_en(rx_stat_en),\r
+         .rx_eof(rx_eof),\r
+         .rx_error(rx_error)\r
+     );\r
+endmodule\r

diff --git a/gbe/cores/sgmii/tsmac/tsmac_bb.v b/gbe/cores/sgmii/tsmac/tsmac_bb.v
new file mode 100644 (file)
index 0000000..4cee903
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/tsmac_bb.v
@@ -0,0 +1,145 @@
+//=============================================================================\r
+// Verilog module generated by IPExpress    \r
+// Filename: USERNAME_bb.v                                          \r
+// Copyright(c) 2006 Lattice Semiconductor Corporation. All rights reserved.   \r
+//=============================================================================\r
+\r
+/* WARNING - Changes to this file should be performed by re-running IPexpress\r
+or modifying the .LPC file and regenerating the core.  Other changes may lead\r
+to inconsistent simulation and/or implemenation results */\r
+module tsmac (\r
+       // clock and reset\r
+       hclk,\r
+       txmac_clk,\r
+       rxmac_clk,\r
+       reset_n,\r
+       txmac_clk_en,\r
+       rxmac_clk_en,\r
+\r
+       // Input signals to the GMII\r
+        rxd,\r
+        rx_dv,\r
+        rx_er,\r
+       col,\r
+       crs,\r
+       \r
+       // Input signals to the CPU Interface\r
+       haddr,\r
+       hdatain,\r
+       hcs_n,\r
+       hwrite_n,\r
+       hread_n,\r
+       \r
+       // Input signals to the MII Management Interface\r
+     \r
+       // Input signals to the Tx MAC FIFO Interface\r
+       tx_fifodata,\r
+       tx_fifoavail,\r
+       tx_fifoeof,\r
+       tx_fifoempty,\r
+       tx_sndpaustim,\r
+       tx_sndpausreq,\r
+       tx_fifoctrl,\r
+     \r
+       // Input signals to the Rx MAC FIFO Interface\r
+       rx_fifo_full,\r
+       ignore_pkt,\r
+     \r
+       // Output signals from the GMII\r
+       txd,\r
+       tx_en,\r
+       tx_er,\r
+     \r
+       // Output signals from the CPU Interface\r
+       hdataout,\r
+       hdataout_en_n,\r
+       hready_n,\r
+       cpu_if_gbit_en,\r
+     \r
+       // Output signals from the MII Management Interface\r
+     \r
+       // Output signals from the Tx MAC FIFO Interface\r
+       tx_macread,\r
+       tx_discfrm,\r
+       tx_staten,\r
+       tx_statvec,\r
+       tx_done,\r
+     \r
+       // Output signals from the Rx MAC FIFO Interface\r
+       rx_fifo_error,\r
+       rx_stat_vector,\r
+       rx_dbout,\r
+       rx_write,\r
+       rx_stat_en,\r
+       rx_eof,\r
+       rx_error\r
+     );\r
+     \r
+     // ------------------------- clock and reset inputs ---------------------\r
+     input                            hclk;               // clock to the CPU I/F\r
+     input                            txmac_clk;          // clock to the Tx MAC\r
+     input                            rxmac_clk;          // clock to the RX MAC\r
+     input                            reset_n;            // Global reset\r
+     input                            txmac_clk_en;       // clock enable to the Tx MAC\r
+     input                            rxmac_clk_en;       // clock enable to the RX MAC\r
+     \r
+     // ----------------------- Input signals to the GMII -------------------\r
+     input  [7:0]                     rxd;                // Receive data\r
+     input                            rx_dv;              // Receive data valid\r
+     input                            rx_er;              // Receive data error\r
+     input                            col;                // Collision detect\r
+     input                            crs;                // Carrier Sense\r
+     // -------------------- Input signals to the CPU I/F -------------------\r
+     input  [7:0]                     haddr;              // Address Bus\r
+     input  [7:0]                     hdatain;            // Input data Bus\r
+     input                            hcs_n;              // Chip select\r
+     input                            hwrite_n;           // Register write\r
+     input                            hread_n;            // Register read\r
+     \r
+     // -------------------- Input signals to the MII I/F -------------------\r
+\r
+     \r
+     // ---------------- Input signals to the Tx MAC FIFO I/F ---------------\r
+     input  [7:0]                     tx_fifodata;        // Data Input from FIFO\r
+     input                            tx_fifoavail;       // Data Available in FIFO\r
+     input                            tx_fifoeof;         // End of Frame\r
+     input                            tx_fifoempty;       // FIFO Empty\r
+     input  [15:0]                    tx_sndpaustim;      // Pause frame parameter\r
+     input                            tx_sndpausreq;      // Transmit PAUSE frame\r
+     input                            tx_fifoctrl;        // Control frame or Not\r
+     \r
+     // ---------------- Input signals to the Rx MAC FIFO I/F ---------------\r
+     input                            rx_fifo_full;       // Receive FIFO Full\r
+     input                            ignore_pkt;         // Ignore the frame\r
+     \r
+     // -------------------- Output signals from the GMII -----------------------\r
+     output [7:0]                     txd;                // Transmit data\r
+     output                           tx_en;              // Transmit Enable\r
+     output                           tx_er;              // Transmit Error\r
+     \r
+     // -------------------- Output signals from the CPU I/F -------------------\r
+     output [7:0]                     hdataout;           // Output data Bus\r
+     output                           hdataout_en_n;      // Data Out Enable\r
+     output                           hready_n;           // Ready signal\r
+     output                           cpu_if_gbit_en;     // Gig or 10/100 mode\r
+     \r
+     // -------------------- Output signals from the MII I/F -------------------\r
+\r
+     \r
+     // ---------------- Output signals from the Tx MAC FIFO I/F ---------------\r
+     output                           tx_macread;         // Read FIFO\r
+     output                           tx_discfrm;         // Discard Frame\r
+     output                           tx_staten;          // Status Vector Valid\r
+     output                           tx_done;            // Transmit of Frame done\r
+     output [30:0]                    tx_statvec;         // Tx Status Vector\r
+     \r
+     // ---------------- Output signals from the Rx MAC FIFO I/F ---------------\r
+     output                           rx_fifo_error;      // FIFO full detected\r
+     output [31:0]                    rx_stat_vector;     // Rx Status Vector\r
+     output [7:0]                     rx_dbout;           // Data Output to FIFO\r
+     output                           rx_write;           // Write FIFO\r
+     output                           rx_stat_en;         // Status Vector Valid\r
+     output                           rx_eof;             // Entire frame written\r
+     output                           rx_error;           // Erroneous frame\r
+     \r
+endmodule\r

diff --git a/gbe/cores/sgmii/tsmac/tsmac_beh.v b/gbe/cores/sgmii/tsmac/tsmac_beh.v
new file mode 100644 (file)
index 0000000..c5f1d57
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/tsmac_beh.v
@@ -0,0 +1,6022 @@
+//=============================================================================
+// Verilog module generated by IPExpress    
+// Filename: USERNAME.v                                          
+// Copyright(c) 2006 Lattice Semiconductor Corporation. All rights reserved.   
+//=============================================================================
+
+/* WARNING - Changes to this file should be performed by re-running IPexpress
+or modifying the .LPC file and regenerating the core.  Other changes may lead
+to inconsistent simulation and/or implemenation results */
+`timescale 1 ns/ 1ns
+module tsmac (
+       // clock and reset
+       hclk,
+       txmac_clk,
+       rxmac_clk,
+       reset_n,
+       txmac_clk_en,
+       rxmac_clk_en,
+
+       // Input signals to the GMII
+       rxd,
+       rx_dv,
+       rx_er,
+       col,
+       crs,
+       // Input signals to the CPU Interface
+       haddr,
+       hdatain,
+       hcs_n,
+       hwrite_n,
+       hread_n,
+       
+       // Input signals to the MII Management Interface
+     
+       // Input signals to the Tx MAC FIFO Interface
+       tx_fifodata,
+       tx_fifoavail,
+       tx_fifoeof,
+       tx_fifoempty,
+       tx_sndpaustim,
+       tx_sndpausreq,
+       tx_fifoctrl,
+     
+       // Input signals to the Rx MAC FIFO Interface
+       rx_fifo_full,
+       ignore_pkt,
+     
+       // Output signals from the GMII
+       txd,
+       tx_en,
+       tx_er,
+     
+       // Output signals from the CPU Interface
+       hdataout,
+       hdataout_en_n,
+       hready_n,
+       cpu_if_gbit_en,
+     
+       // Output signals from the MII Management Interface
+     
+       // Output signals from the Tx MAC FIFO Interface
+       tx_macread,
+       tx_discfrm,
+       tx_staten,
+       tx_statvec,
+       tx_done,
+     
+       // Output signals from the Rx MAC FIFO Interface
+       rx_fifo_error,
+       rx_stat_vector,
+       rx_dbout,
+       rx_write,
+       rx_stat_en,
+       rx_eof,
+       rx_error
+     );
+     
+     // ------------------------- clock and reset inputs ---------------------
+     input                            hclk;               // clock to the CPU I/F
+     input                            txmac_clk;          // clock to the Tx MAC
+     input                            rxmac_clk;          // clock to the RX MAC
+     input                            reset_n;            // Global reset
+     input                            txmac_clk_en;       // clock enable to the Tx MAC
+     input                            rxmac_clk_en;       // clock enable to the RX MAC
+     
+     // ----------------------- Input signals to the GMII -------------------
+     input  [7:0]                     rxd;                // Receive data
+     input                            rx_dv;              // Receive data valid
+     input                            rx_er;              // Receive data error
+     input                            col;                // Collision detect
+     input                            crs;                // Carrier Sense
+     // -------------------- Input signals to the CPU I/F -------------------
+     input  [7:0]                     haddr;              // Address Bus
+     input  [7:0]                     hdatain;            // Input data Bus
+     input                            hcs_n;              // Chip select
+     input                            hwrite_n;           // Register write
+     input                            hread_n;            // Register read
+     
+     // -------------------- Input signals to the MII I/F -------------------
+
+     
+     // ---------------- Input signals to the Tx MAC FIFO I/F ---------------
+     input  [7:0]                     tx_fifodata;        // Data Input from FIFO
+     input                            tx_fifoavail;       // Data Available in FIFO
+     input                            tx_fifoeof;         // End of Frame
+     input                            tx_fifoempty;       // FIFO Empty
+     input  [15:0]                    tx_sndpaustim;      // Pause frame parameter
+     input                            tx_sndpausreq;      // Transmit PAUSE frame
+     input                            tx_fifoctrl;        // Control frame or Not
+     
+     // ---------------- Input signals to the Rx MAC FIFO I/F ---------------
+     input                            rx_fifo_full;       // Receive FIFO Full
+     input                            ignore_pkt;         // Ignore the frame
+     
+     // -------------------- Output signals from the GMII -----------------------
+     output [7:0]                     txd;                // Transmit data
+     output                           tx_en;              // Transmit Enable
+     output                           tx_er;              // Transmit Error
+     
+     // -------------------- Output signals from the CPU I/F -------------------
+     output [7:0]                     hdataout;           // Output data Bus
+     output                           hdataout_en_n;      // Data Out Enable
+     output                           hready_n;           // Ready signal
+     output                           cpu_if_gbit_en;     // Gig or 10/100 mode
+     
+     // -------------------- Output signals from the MII I/F -------------------
+
+     
+     // ---------------- Output signals from the Tx MAC FIFO I/F ---------------
+     output                           tx_macread;         // Read FIFO
+     output                           tx_discfrm;         // Discard Frame
+     output                           tx_staten;          // Status Vector Valid
+     output                           tx_done;            // Transmit of Frame done
+     output [30:0]                    tx_statvec;         // Tx Status Vector
+     
+     // ---------------- Output signals from the Rx MAC FIFO I/F ---------------
+     output                           rx_fifo_error;      // FIFO full detected
+     output [31:0]                    rx_stat_vector;     // Rx Status Vector
+     output [7:0]                     rx_dbout;           // Data Output to FIFO
+     output                           rx_write;           // Write FIFO
+     output                           rx_stat_en;         // Status Vector Valid
+     output                           rx_eof;             // Entire frame written
+     output                           rx_error;           // Erroneous frame
+     
+     tsmac_core U1_LSC_ts_mac_core ( 
+
+         // clock and reset
+         .hclk(hclk),
+         .txmac_clk(txmac_clk),
+         .rxmac_clk(rxmac_clk),
+         .reset_n(reset_n),
+         .txmac_clk_en(txmac_clk_en),
+         .rxmac_clk_en(rxmac_clk_en),
+     
+         // Input signals to the GMII
+         .rxd(rxd),
+         .rx_dv(rx_dv),
+         .rx_er(rx_er),
+         .col(col),
+         .crs(crs),
+         // Input signals to the CPU Interface
+         .haddr(haddr),
+         .hdatain(hdatain),
+         .hcs_n(hcs_n),
+         .hwrite_n(hwrite_n),
+         .hread_n(hread_n),
+     
+         // Input signals to the MII Management Interface
+     
+         // Input signals to the Tx MAC FIFO Interface
+         .tx_fifodata(tx_fifodata),
+         .tx_fifoavail(tx_fifoavail),
+         .tx_fifoeof(tx_fifoeof),
+         .tx_fifoempty(tx_fifoempty),
+         .tx_sndpaustim(tx_sndpaustim),
+         .tx_sndpausreq(tx_sndpausreq),
+         .tx_fifoctrl(tx_fifoctrl),
+     
+         // Input signals to the Rx MAC FIFO Interface
+         .rx_fifo_full(rx_fifo_full),
+         .ignore_pkt(ignore_pkt),
+     
+         // Output signals from the GMII
+         .txd(txd),
+         .tx_en(tx_en),
+         .tx_er(tx_er),
+     
+         // Output signals from the CPU Interface
+         .hdataout(hdataout),
+         .hdataout_en_n(hdataout_en_n),
+         .hready_n(hready_n),
+         .cpu_if_gbit_en(cpu_if_gbit_en),
+     
+         // Output signals from the MII Management Interface
+     
+         // Output signals from the Tx MAC FIFO Interface
+         .tx_macread(tx_macread),
+         .tx_discfrm(tx_discfrm),
+         .tx_staten(tx_staten),
+         .tx_statvec(tx_statvec),
+         .tx_done(tx_done),
+     
+         // Output signals from the Rx MAC FIFO Interface
+         .rx_fifo_error(rx_fifo_error),
+         .rx_stat_vector(rx_stat_vector),
+         .rx_dbout(rx_dbout),
+         .rx_write(rx_write),
+         .rx_stat_en(rx_stat_en),
+         .rx_eof(rx_eof),
+         .rx_error(rx_error)
+     );
+endmodule
+// ts_mac_core_beh.v generated by Lattice IP Model Creator version 1
+// created on Fri, May 23, 2014 10:35:39 AM
+// Copyright(c) 2007 Lattice Semiconductor Corporation. All rights reserved
+// obfuscator_exe version 1.mar0807
+
+// top
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+`timescale 1 ns / 100 ps
+module kdd67f2 (
+       rxmac_clk,
+       reset_n,
+    rxmac_clk_en, 
+       
+       
+       mrf282b,                  
+       tj9415c,                   
+       
+       
+       lfa0ae7,
+       aa573e,
+       
+       
+       aa2b9f0,
+        yk5cf81,
+       yxe7c08,
+       ec3e045
+);
+parameter mef0229         = 8;
+input  rxmac_clk;
+input  reset_n;
+input               rxmac_clk_en;
+input  mrf282b;
+input  lfa0ae7;
+input  aa573e;
+input  [mef0229-1:0]  tj9415c;
+output                          yk5cf81;
+output        yxe7c08;
+output        ec3e045;
+output [mef0229-1:0]  aa2b9f0;
+reg                             yk5cf81;
+reg    yxe7c08;
+reg    ec3e045;
+reg  [mef0229-1:0]    aa2b9f0;
+reg            gd26f72;
+parameter tj37b95 = 2;
+parameter vkbdcae   =   2'b01;
+parameter tuee573    =   2'b10;
+parameter qg72b9a        =   0;
+parameter yz95cd0        =   1;
+parameter uxae684  = 8'hd5;
+parameter zk73424  = 8'h55;
+wire wl9a123;
+wire hod091c;
+reg  ph848e2;
+reg  uk24717;
+reg  an238b9;
+reg  [tj37b95-1:0] uve2e6f;
+reg  [2:0]              an1737d;
+reg  [tj37b95-1:0] vvcdf61;
+reg wj6fb0f;
+reg [mef0229 - 1 : 0] xjec3e9;
+reg dz61f4f;
+reg oufa7e;
+reg me7d3f0;
+reg xje9f80;
+reg zx4fc06;
+reg zx7e036;
+reg ykf01b7;
+reg kf80db8;
+reg [tj37b95 - 1 : 0] wl36e2e;
+reg [2 : 0] twb7174;
+reg [tj37b95 - 1 : 0] zkc5d1b;
+reg [2047:0] wy2e8db;
+wire [12:0] vv746d9;
+
+localparam ksa36ce = 13,tw1b670 = 32'hfdffc68b;
+localparam [31:0] icdb382 = tw1b670;
+localparam mece084 = tw1b670 & 4'hf;
+localparam [11:0] ou8210c = 'h7ff;
+wire [(1 << mece084) -1:0] db84308;
+reg [ksa36ce-1:0] dbc230;
+reg [mece084-1:0] kf8c37 [0:1];
+reg [mece084-1:0] hq30de9;
+reg hq86f4b;
+integer hd37a5a;
+integer dobd2d6;
+
+
+
+
+
+
+                                          
+
+                                                  
+
+
+
+
+                                          
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+always @ (posedge rxmac_clk or negedge reset_n) begin    if (!reset_n) begin        aa2b9f0      <= 0;    end    else if (rxmac_clk_en) begin       if (wj6fb0f) begin          aa2b9f0  <= xjec3e9;       end    end
+end
+
+
+
+
+assign wl9a123 = xjec3e9[7:0] == uxae684;
+assign hod091c = xjec3e9[7:0] == zk73424;
+
+
+
+
+
+
+always @(posedge rxmac_clk or negedge reset_n) begin    if (!reset_n) begin        vvcdf61            <= vkbdcae;                  an1737d    <= 3'b0;        yk5cf81  <= 1'b0;        ec3e045     <= 1'b0;        gd26f72     <= 1'b0;        yxe7c08 <= 1'b0;    end    else if (rxmac_clk_en) begin       vvcdf61        <= wl36e2e;                     gd26f72    <= zx7e036;       yxe7c08 <= me7d3f0;       yk5cf81  <= 1'b0;            
+                                                       an1737d <= kf80db8 ? 3'h1 : (|twb7174) ? (twb7174+3'h1) :       zkc5d1b[qg72b9a] ? 3'h0 : twb7174;
+       if (ykf01b7) begin          ec3e045 <= 1'b1;                       end else if (oufa7e) begin                    ec3e045 <= 1'b0;                       end else if (dz61f4f) begin                      ec3e045 <= 1'b0;                       end    end
+end
+
+
+always @(zkc5d1b or dz61f4f or zx4fc06 or xje9f80 or twb7174) begin    case(zkc5d1b)        vkbdcae : begin                                           if (dz61f4f && xje9f80) begin                    uve2e6f = vkbdcae;                ph848e2 = 1'b1;                uk24717 = 1'b0;        an238b9 = 1'b0;            end else if (dz61f4f && zx4fc06) begin                       uve2e6f = tuee573;                                     ph848e2 = 1'b0;                uk24717 = 1'b0;                an238b9 = 1'b1;            end else if (dz61f4f && !xje9f80 && !zx4fc06) begin                                                uve2e6f = vkbdcae;                                      ph848e2 = 1'b0;                uk24717 = 1'b1;                an238b9 = 1'b0;            end
+            else begin uve2e6f = vkbdcae;      ph848e2 = 1'b0; uk24717 = 1'b0; an238b9 = 1'b0;    end        end
+                       tuee573 : begin                                          if (xje9f80) begin                    uve2e6f = vkbdcae;                               ph848e2 = 1'b1;               uk24717 = 1'b0;               an238b9 = 1'b0;           end else if (~|twb7174 & ~zx4fc06) begin                         uve2e6f = vkbdcae;                               ph848e2 = 1'b0;               uk24717 = 1'b1;               an238b9 = 1'b0;                                    end else begin                              uve2e6f = tuee573;                                   ph848e2 = 1'b0;               uk24717 = 1'b0;               an238b9 = 1'b0;            end
+         end
+ default : begin            uve2e6f = vkbdcae;            ph848e2 = 1'b0;                                 uk24717 = 1'b0;            an238b9 = 1'b0;           end     endcase
+end
+
+always@* begin wj6fb0f<=vv746d9[0];xjec3e9<={tj9415c>>1,vv746d9[1]};dz61f4f<=vv746d9[2];oufa7e<=vv746d9[3];me7d3f0<=vv746d9[4];xje9f80<=vv746d9[5];zx4fc06<=vv746d9[6];zx7e036<=vv746d9[7];ykf01b7<=vv746d9[8];kf80db8<=vv746d9[9];wl36e2e<={uve2e6f>>1,vv746d9[10]};twb7174<={an1737d>>1,vv746d9[11]};zkc5d1b<={vvcdf61>>1,vv746d9[12]};end
+always@* begin wy2e8db[2047]<=tj9415c[0];wy2e8db[2046]<=lfa0ae7;wy2e8db[2044]<=aa573e;wy2e8db[2040]<=gd26f72;wy2e8db[2032]<=wl9a123;wy2e8db[2017]<=hod091c;wy2e8db[1987]<=ph848e2;wy2e8db[1926]<=uk24717;wy2e8db[1805]<=an238b9;wy2e8db[1562]<=uve2e6f[0];wy2e8db[1076]<=an1737d[0];wy2e8db[1023]<=mrf282b;wy2e8db[104]<=vvcdf61[0];end         assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6<ksa36ce; dobd2d6=dobd2d6+1) begin dbc230[dobd2d6] = db84308[hq30de9]; hq86f4b = ^(hq30de9 & kf8c37[0]); hq30de9 = {hq30de9, hq86f4b}; end end 
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+`timescale 1 ns / 100 ps
+module fn6ee52 (
+    rxmac_clk,
+    reset_n,
+    rxmac_clk_en,
+
+    
+    ne52e43,
+    yxe7c08,
+
+    
+    aa573e,
+    fnc86c0,
+
+    
+    su43606,
+    tw1b031,
+    ldd818a,
+    byc0c57,
+    ph62bb,
+    uk315df,
+    ep8aef8,
+    lq577c4,
+    uxbbe22,
+    hodf114,
+    shf88a2,
+    uic4515,
+
+    
+    hd228a8,
+
+    
+    zm14547,
+    fca2a3b,
+    ie151db,
+    zma8ed9,
+    ne476ca,
+    ec3b653,
+    medb299
+);
+parameter mef0229         = 8;
+parameter neca645         = 48;
+parameter ic5322b     = 6;
+parameter vk99158         = 8;
+input           rxmac_clk;
+input           reset_n;
+input           rxmac_clk_en;
+input           yxe7c08;
+input           aa573e;
+input           fnc86c0;
+input  [mef0229-1:0]    ne52e43;
+input  [vk99158-1:0]    su43606;
+input  [vk99158-1:0]    tw1b031;
+input  [vk99158-1:0]    ldd818a;
+input  [vk99158-1:0]    byc0c57;
+input  [vk99158-1:0]    ph62bb;
+input  [vk99158-1:0]    uk315df;
+input  [vk99158-1:0]    ep8aef8;
+input  [vk99158-1:0]    lq577c4;
+input  [neca645-1:0]    uxbbe22;
+input           hodf114;
+input           shf88a2;
+input           uic4515;
+input  [ic5322b-1:0]    hd228a8;
+output          fca2a3b;
+output          ie151db;
+output          zma8ed9;
+output          ne476ca;
+output          ec3b653;
+output          medb299;
+output          zm14547;
+reg             ne476ca;
+reg             ec3b653;
+reg             medb299;
+reg             fca2a3b;
+localparam uk9ddab = 11;
+localparam rgeed58  =    11'b00000000001;
+localparam fa76ac3  =    11'b00000000010;
+localparam phb561a  =    11'b00000000100;
+localparam qvab0d6  =    11'b00000001000;
+localparam tu586b4  =    11'b00000010000;
+localparam ofc35a3  =    11'b00000100000;
+localparam mg1ad1d =   11'b00001000000;
+localparam kdd68e9 =   11'b00010000000;
+localparam qvb474d =   11'b00100000000;
+localparam wya3a6c =   11'b01000000000;
+localparam qv1d361 =   11'b10000000000;
+localparam qg72b9a         =  0;
+localparam yz95cd0         =  1;
+localparam rg6c373         =  2;
+localparam hb61b9b         =  3;
+localparam wldcde         =  4;
+localparam fn6e6f5         =  5;
+localparam jc737ae         =  6;
+localparam zz9bd73         =  7;
+localparam icdeb9f         =  8;
+localparam cmf5cf9         =  9;
+localparam uxae7c9        =  10;
+wire            zk73e4c;
+wire            sj9f262;
+wire            dzf9314;
+wire            czc98a6;
+wire            yk4c535;
+wire            os629a8;
+reg             do14d41;
+reg             gqa6a0a;
+reg  [uk9ddab-1:0] fca828a;
+reg  [uk9ddab-1:0] iea29c;
+wire            wj514e1;
+wire            ir8a70d;
+wire            ui5386d;
+wire            ri9c369;
+wire            xwe1b4b;
+wire            uxda5a;
+reg             me6d2d5;
+reg             rg696a9;
+reg  [uk9ddab-1:0] hb5aa5d;
+reg  [uk9ddab-1:0] yma977b;
+wire            kd4bbd9;
+reg             ho5decc;
+reg  [vk99158-1:0] vv7b310;
+reg             uvd9887;
+reg            shcc43c;
+wire            su621e4;
+reg             ec10f20;
+reg             ou87900;
+reg  [uk9ddab-1:0] jce4005;
+reg  [uk9ddab-1:0] ks15b;
+wire            coad8;
+wire            uk56c1;
+wire            ec2b608;
+reg             cz5b040;
+reg             fnd8204;
+reg             eac1027;
+reg ir8138;
+reg th409c4;
+reg ba4e27;
+reg ph2713b;
+reg jr389de;
+reg zm14547;
+reg [mef0229 - 1 : 0] uk3bdce;
+reg godee70;
+reg oufa7e;
+reg ksb9c0d;
+reg [vk99158 - 1 : 0] wj70349;
+reg [vk99158 - 1 : 0] sjd267;
+reg [vk99158 - 1 : 0] ui499e3;
+reg [vk99158 - 1 : 0] ay678c9;
+reg [vk99158 - 1 : 0] zxe324c;
+reg [vk99158 - 1 : 0] czc9337;
+reg [vk99158 - 1 : 0] me4cde1;
+reg [vk99158 - 1 : 0] fp3784b;
+reg [neca645 - 1 : 0] vie12f0;
+reg jr9783;
+reg al4bc1e;
+reg gb5e0f4;
+reg [ic5322b - 1 : 0] ls83d20;
+reg ls1e902;
+reg byf4813;
+reg mta409b;
+reg ng204dd;
+reg wl26eb;
+reg bn1375d;
+reg tj9baee;
+reg pfdd777;
+reg [uk9ddab - 1 : 0] dm5ddfb;
+reg [uk9ddab - 1 : 0] ic77ed3;
+reg ntbf698;
+reg hofb4c7;
+reg lqda63b;
+reg yxd31da;
+reg sw98ed4;
+reg dzc76a0;
+reg co3b507;
+reg xwda839;
+reg [uk9ddab - 1 : 0] dba0e59;
+reg [uk9ddab - 1 : 0] ep39675;
+reg iccb3ac;
+reg ui59d61;
+reg [vk99158 - 1 : 0] en75840;
+reg ieac205;
+reg nr61029;
+reg wl814f;
+reg bl40a7c;
+reg mg53e7;
+reg [uk9ddab - 1 : 0] bl4f9c4;
+reg [uk9ddab - 1 : 0] ipe7133;
+reg fp3899c;
+reg uic4ce7;
+reg kf26739;
+reg ux339cc;
+reg do9ce64;
+reg mre7322;
+reg kf39914;
+reg kdcc8a5;
+reg nr6452d;
+reg xl2296f;
+reg xy14b7f;
+reg [2047:0] wy2e8db;
+wire [57:0] vv746d9;
+
+localparam ksa36ce = 58,tw1b670 = 32'hfdffc68b;
+localparam [31:0] icdb382 = tw1b670;
+localparam mece084 = tw1b670 & 4'hf;
+localparam [11:0] ou8210c = 'h7ff;
+wire [(1 << mece084) -1:0] db84308;
+reg [ksa36ce-1:0] dbc230;
+reg [mece084-1:0] kf8c37 [0:1];
+reg [mece084-1:0] hq30de9;
+reg hq86f4b;
+integer hd37a5a;
+integer dobd2d6;
+
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+                                   
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+
+
+assign coad8 = (ic77ed3[fn6e6f5] | ic77ed3[uxae7c9]) &                            (gb5e0f4 | tj9baee | co3b507 |                             (al4bc1e & bl40a7c));
+assign ec2b608 = (ic77ed3[fn6e6f5] | ic77ed3[uxae7c9]) &                                       ~fp3899c;
+assign uk56c1 = ux339cc &                                ~(do9ce64 | (nr61029 & jr9783 & ui59d61));
+
+assign ie151db = kdcc8a5 | kf39914;
+
+assign zma8ed9 = nr6452d | mre7322;
+
+always @(posedge rxmac_clk or negedge reset_n) begin    if (!reset_n) begin        ir8138 <= 1'b0;        th409c4 <= 1'b0;        ba4e27 <= 1'b0;        ph2713b <= 1'b0;        jr389de     <= 1'b0;        iea29c          <= rgeed58;        yma977b          <= rgeed58;        ks15b          <= rgeed58;        fca2a3b    <= 1'b0;        fnd8204   <= 1'b0;        medb299         <= 1'b0;        ne476ca          <= 1'b0;        ec3b653          <= 1'b0;        uvd9887    <= 1'b0;        shcc43c      <= 1'b0;        cz5b040    <= 1'b0;        eac1027 <= 1'b0;    end    else if (rxmac_clk_en) begin        jr389de      <= ksb9c0d;        ir8138 <= (nr61029 & jr9783 & ui59d61);        th409c4 <= do9ce64;        ba4e27 <= uic4ce7;        ph2713b <= godee70;                if(xy14b7f) begin            iea29c          <= rgeed58;            yma977b          <= rgeed58;            ks15b          <= rgeed58;        end else begin                                                iea29c          <= dm5ddfb;            yma977b          <= dba0e59;            ks15b          <= bl4f9c4;        end        fnd8204     <= fp3899c;        cz5b040 <= kf26739;        shcc43c   <= iccb3ac;                if (godee70)            uvd9887  <= uk3bdce[0];                        if (tj9baee)            fca2a3b <= tj9baee;        else if (oufa7e)            fca2a3b <= tj9baee;        else            fca2a3b <= fca2a3b;        if (co3b507)            medb299 <= co3b507;        else if (oufa7e)            medb299 <= co3b507;        else            medb299 <= medb299;                        if (uic4ce7 | oufa7e)            eac1027 <= uic4ce7;        else if (godee70)            eac1027 <= 1'b0;        else            eac1027 <= mre7322;                                if (iccb3ac)            ne476ca <= (iccb3ac);        else if (oufa7e)            ne476ca <= iccb3ac;        else if (godee70)            ne476ca <= 1'b0;        else            ne476ca <= ne476ca;        if (bl40a7c)            ec3b653 <= bl40a7c;        else if (oufa7e)            ec3b653 <= bl40a7c;        else if (xl2296f)            ec3b653 <= 1'b0;        else            ec3b653 <= ec3b653;    end
+end
+
+
+
+
+
+assign os629a8 = vie12f0[47:40] == uk3bdce;
+
+assign yk4c535 = vie12f0[39:32] == uk3bdce;
+
+assign czc98a6 = vie12f0[31:24] == uk3bdce;
+
+assign dzf9314 = vie12f0[23:16] == uk3bdce;
+
+assign sj9f262 = vie12f0[15:8] == uk3bdce;
+
+assign zk73e4c = vie12f0[7:0] == uk3bdce;
+
+
+always @(ic77ed3 or godee70 or ls1e902 or byf4813 or mta409b          or ng204dd or wl26eb or bn1375d) begin    zm14547 = 1'b1;    case(ic77ed3)        rgeed58 : begin                                        if (!godee70) begin                fca828a = rgeed58;                                                                                      do14d41 = 1'b0;                gqa6a0a = 1'b0;       zm14547 = 1'b0;            end else if (godee70) begin                if (bn1375d) begin                   fca828a = fa76ac3;                                 do14d41 = 1'b0;                   gqa6a0a = 1'b0;               end else begin                   fca828a = mg1ad1d;                               do14d41 = 1'b0;                   gqa6a0a = 1'b0;               end            end        end                        fa76ac3 : begin            if (wl26eb) begin                                  fca828a = phb561a;                do14d41 = 1'b0;                gqa6a0a = 1'b0;            end            else begin                                                 fca828a = kdd68e9;                do14d41 = 1'b0;                gqa6a0a = 1'b0;            end        end                        phb561a : begin            if (ng204dd) begin                                  fca828a = qvab0d6;                do14d41 = 1'b0;                gqa6a0a = 1'b0;            end            else begin                                                 fca828a = qvb474d;                do14d41 = 1'b0;                gqa6a0a = 1'b0;            end        end                        qvab0d6 : begin            if (mta409b) begin                                  fca828a = tu586b4;                do14d41 = 1'b0;                gqa6a0a = 1'b0;            end            else begin                                                 fca828a = wya3a6c;                do14d41 = 1'b0;                gqa6a0a = 1'b0;            end        end                        tu586b4 : begin            if (byf4813) begin                                  fca828a = ofc35a3;                do14d41 = 1'b0;                gqa6a0a = 1'b0;            end            else begin                                                 fca828a = qv1d361;                do14d41 = 1'b0;                gqa6a0a = 1'b0;            end        end                        ofc35a3 : begin            if (ls1e902) begin                                  fca828a = rgeed58;                do14d41 = 1'b1;                gqa6a0a = 1'b0;            end            else begin                                                 fca828a = rgeed58;                do14d41 = 1'b0;                gqa6a0a = 1'b1;            end        end                                                        mg1ad1d : begin            fca828a = kdd68e9;            do14d41 = 1'b0;            gqa6a0a = 1'b0;        end        kdd68e9 : begin            fca828a = qvb474d;            do14d41 = 1'b0;            gqa6a0a = 1'b0;        end        qvb474d : begin            fca828a = wya3a6c;            do14d41 = 1'b0;            gqa6a0a = 1'b0;        end        wya3a6c : begin            fca828a = qv1d361;            do14d41 = 1'b0;            gqa6a0a = 1'b0;        end        qv1d361 : begin            fca828a = rgeed58;                               do14d41 = 1'b0;            gqa6a0a = 1'b1;        end        default : begin            fca828a = rgeed58;                               do14d41 = 1'b0;            gqa6a0a = 1'b0;        end    endcase
+end
+
+
+
+
+
+
+
+
+
+assign uxda5a = 8'h01 == uk3bdce;
+
+assign xwe1b4b = 8'h80 == uk3bdce;
+
+assign ri9c369 = 8'hc2 == uk3bdce;
+
+assign ui5386d = 8'h00 == uk3bdce;
+
+assign ir8a70d = 8'h00 == uk3bdce;
+
+assign wj514e1 = 8'h01 == uk3bdce;
+
+
+always @(ep39675 or godee70 or ntbf698 or hofb4c7 or lqda63b          or yxd31da or sw98ed4 or dzc76a0) begin    case(ep39675)        rgeed58 : begin                                        if (!godee70) begin                hb5aa5d = rgeed58;                                                                                      me6d2d5 = 1'b0;                rg696a9 = 1'b0;            end else if (godee70) begin                if (dzc76a0) begin                   hb5aa5d = fa76ac3;                                 me6d2d5 = 1'b0;                   rg696a9 = 1'b0;               end else begin                   hb5aa5d = mg1ad1d;                               me6d2d5 = 1'b0;                   rg696a9 = 1'b0;               end            end        end                        fa76ac3 : begin            if (sw98ed4) begin                                  hb5aa5d = phb561a;                me6d2d5 = 1'b0;                rg696a9 = 1'b0;            end            else begin                                                 hb5aa5d = kdd68e9;                me6d2d5 = 1'b0;                rg696a9 = 1'b0;            end        end                        phb561a : begin            if (yxd31da) begin                                  hb5aa5d = qvab0d6;                me6d2d5 = 1'b0;                rg696a9 = 1'b0;            end            else begin                                                 hb5aa5d = qvb474d;                me6d2d5 = 1'b0;                rg696a9 = 1'b0;            end        end                        qvab0d6 : begin            if (lqda63b) begin                                  hb5aa5d = tu586b4;                me6d2d5 = 1'b0;                rg696a9 = 1'b0;            end            else begin                                                 hb5aa5d = wya3a6c;                me6d2d5 = 1'b0;                rg696a9 = 1'b0;            end        end                        tu586b4 : begin            if (hofb4c7) begin                                  hb5aa5d = ofc35a3;                me6d2d5 = 1'b0;                rg696a9 = 1'b0;            end            else begin                                                 hb5aa5d = qv1d361;                me6d2d5 = 1'b0;                rg696a9 = 1'b0;            end        end                        ofc35a3 : begin            if (ntbf698) begin                                  hb5aa5d = rgeed58;                me6d2d5 = 1'b1;                rg696a9 = 1'b0;            end            else begin                                                 hb5aa5d = rgeed58;                me6d2d5 = 1'b0;                rg696a9 = 1'b1;            end        end                                                        mg1ad1d : begin            hb5aa5d = kdd68e9;            me6d2d5 = 1'b0;            rg696a9 = 1'b0;        end        kdd68e9 : begin            hb5aa5d = qvb474d;            me6d2d5 = 1'b0;            rg696a9 = 1'b0;        end        qvb474d : begin            hb5aa5d = wya3a6c;            me6d2d5 = 1'b0;            rg696a9 = 1'b0;        end        wya3a6c : begin            hb5aa5d = qv1d361;            me6d2d5 = 1'b0;            rg696a9 = 1'b0;        end        qv1d361 : begin            hb5aa5d = rgeed58;                               me6d2d5 = 1'b0;            rg696a9 = 1'b1;        end        default : begin            hb5aa5d = rgeed58;                               me6d2d5 = 1'b0;            rg696a9 = 1'b0;        end    endcase
+end
+
+
+
+
+
+
+
+
+
+
+assign kd4bbd9 = ieac205 & ic77ed3[uxae7c9] &                           ~bl40a7c & ~co3b507 ;
+
+always @ (ls83d20[5:3] or wj70349 or sjd267 or          ui499e3 or ay678c9 or zxe324c or          czc9337 or me4cde1 or fp3784b) begin    case (ls83d20[5:3])        3'b000 : begin            vv7b310 = wj70349;        end        3'b001 : begin            vv7b310 = sjd267;        end        3'b010 : begin            vv7b310 = ui499e3;        end        3'b011 : begin            vv7b310 = ay678c9;        end        3'b100 : begin            vv7b310 = zxe324c;        end        3'b101 : begin            vv7b310 = czc9337;        end        3'b110 : begin            vv7b310 = me4cde1;        end        3'b111 : begin            vv7b310 = fp3784b;        end    endcase
+end
+
+always @ (ls83d20[2:0] or en75840) begin    case (ls83d20[2:0])        3'b000 : begin            ho5decc = en75840[0];        end        3'b001 : begin            ho5decc = en75840[1];        end        3'b010 : begin            ho5decc = en75840[2];        end        3'b011 : begin            ho5decc = en75840[3];        end        3'b100 : begin            ho5decc = en75840[4];        end        3'b101 : begin            ho5decc = en75840[5];        end        3'b110 : begin            ho5decc = en75840[6];        end        3'b111 : begin            ho5decc = en75840[7];        end    endcase
+end
+
+
+
+
+
+
+assign su621e4 = 8'hff == uk3bdce;
+
+
+always @(ipe7133 or godee70 or wl814f) begin    case(ipe7133)        rgeed58 : begin                                        if (!godee70) begin                jce4005 = rgeed58;                                                                                      ec10f20 = 1'b0;                ou87900 = 1'b0;            end else if (godee70) begin                if (wl814f) begin                   jce4005 = fa76ac3;                                 ec10f20 = 1'b0;                   ou87900 = 1'b0;               end else begin                   jce4005 = mg1ad1d;                               ec10f20 = 1'b0;                   ou87900 = 1'b0;               end            end        end                        fa76ac3 : begin            if (wl814f) begin                                  jce4005 = phb561a;                ec10f20 = 1'b0;                ou87900 = 1'b0;            end            else begin                                                 jce4005 = kdd68e9;                ec10f20 = 1'b0;                ou87900 = 1'b0;            end        end                        phb561a : begin            if (wl814f) begin                                  jce4005 = qvab0d6;                ec10f20 = 1'b0;                ou87900 = 1'b0;            end            else begin                                                 jce4005 = qvb474d;                ec10f20 = 1'b0;                ou87900 = 1'b0;            end        end                        qvab0d6 : begin            if (wl814f) begin                                  jce4005 = tu586b4;                ec10f20 = 1'b0;                ou87900 = 1'b0;            end            else begin                                                 jce4005 = wya3a6c;                ec10f20 = 1'b0;                ou87900 = 1'b0;            end        end                        tu586b4 : begin            if (wl814f) begin                                  jce4005 = ofc35a3;                ec10f20 = 1'b0;                ou87900 = 1'b0;            end            else begin                                                 jce4005 = qv1d361;                ec10f20 = 1'b0;                ou87900 = 1'b0;            end        end                        ofc35a3 : begin            if (wl814f) begin                                  jce4005 = rgeed58;                ec10f20 = 1'b1;                ou87900 = 1'b0;            end            else begin                                                 jce4005 = rgeed58;                ec10f20 = 1'b0;                ou87900 = 1'b1;            end        end                                                        mg1ad1d : begin            jce4005 = kdd68e9;            ec10f20 = 1'b0;            ou87900 = 1'b0;        end        kdd68e9 : begin            jce4005 = qvb474d;            ec10f20 = 1'b0;            ou87900 = 1'b0;        end        qvb474d : begin            jce4005 = wya3a6c;            ec10f20 = 1'b0;            ou87900 = 1'b0;        end        wya3a6c : begin            jce4005 = qv1d361;            ec10f20 = 1'b0;            ou87900 = 1'b0;        end        qv1d361 : begin            jce4005 = rgeed58;                               ec10f20 = 1'b0;            ou87900 = 1'b1;        end        default : begin            jce4005 = rgeed58;                               ec10f20 = 1'b0;            ou87900 = 1'b0;        end    endcase
+end
+
+always@* begin uk3bdce<={ne52e43>>1,vv746d9[0]};godee70<=vv746d9[1];oufa7e<=vv746d9[2];ksb9c0d<=vv746d9[3];wj70349<={su43606>>1,vv746d9[4]};sjd267<={tw1b031>>1,vv746d9[5]};ui499e3<={ldd818a>>1,vv746d9[6]};ay678c9<={byc0c57>>1,vv746d9[7]};zxe324c<={ph62bb>>1,vv746d9[8]};czc9337<={uk315df>>1,vv746d9[9]};me4cde1<={ep8aef8>>1,vv746d9[10]};fp3784b<={lq577c4>>1,vv746d9[11]};vie12f0<={uxbbe22>>1,vv746d9[12]};jr9783<=vv746d9[13];al4bc1e<=vv746d9[14];gb5e0f4<=vv746d9[15];ls83d20<={hd228a8>>1,vv746d9[16]};ls1e902<=vv746d9[17];byf4813<=vv746d9[18];mta409b<=vv746d9[19];ng204dd<=vv746d9[20];wl26eb<=vv746d9[21];bn1375d<=vv746d9[22];tj9baee<=vv746d9[23];pfdd777<=vv746d9[24];dm5ddfb<={fca828a>>1,vv746d9[25]};ic77ed3<={iea29c>>1,vv746d9[26]};ntbf698<=vv746d9[27];hofb4c7<=vv746d9[28];lqda63b<=vv746d9[29];yxd31da<=vv746d9[30];sw98ed4<=vv746d9[31];dzc76a0<=vv746d9[32];co3b507<=vv746d9[33];xwda839<=vv746d9[34];dba0e59<={hb5aa5d>>1,vv746d9[35]};ep39675<={yma977b>>1,vv746d9[36]};iccb3ac<=vv746d9[37];ui59d61<=vv746d9[38];en75840<={vv7b310>>1,vv746d9[39]};ieac205<=vv746d9[40];nr61029<=vv746d9[41];wl814f<=vv746d9[42];bl40a7c<=vv746d9[43];mg53e7<=vv746d9[44];bl4f9c4<={jce4005>>1,vv746d9[45]};ipe7133<={ks15b>>1,vv746d9[46]};fp3899c<=vv746d9[47];uic4ce7<=vv746d9[48];kf26739<=vv746d9[49];ux339cc<=vv746d9[50];do9ce64<=vv746d9[51];mre7322<=vv746d9[52];kf39914<=vv746d9[53];kdcc8a5<=vv746d9[54];nr6452d<=vv746d9[55];xl2296f<=vv746d9[56];xy14b7f<=vv746d9[57];end
+always@* begin wy2e8db[2047]<=yxe7c08;wy2e8db[2046]<=aa573e;wy2e8db[2044]<=fnc86c0;wy2e8db[2040]<=su43606[0];wy2e8db[2032]<=tw1b031[0];wy2e8db[2017]<=ldd818a[0];wy2e8db[1987]<=byc0c57[0];wy2e8db[1980]<=ec2b608;wy2e8db[1963]<=me6d2d5;wy2e8db[1942]<=th409c4;wy2e8db[1926]<=ph62bb[0];wy2e8db[1921]<=do14d41;wy2e8db[1913]<=cz5b040;wy2e8db[1903]<=su621e4;wy2e8db[1879]<=rg696a9;wy2e8db[1837]<=ba4e27;wy2e8db[1805]<=uk315df[0];wy2e8db[1795]<=gqa6a0a;wy2e8db[1783]<=ks15b[0];wy2e8db[1778]<=fnd8204;wy2e8db[1758]<=ec10f20;wy2e8db[1710]<=hb5aa5d[0];wy2e8db[1679]<=hd228a8[0];wy2e8db[1627]<=ph2713b;wy2e8db[1562]<=ep8aef8[0];wy2e8db[1543]<=fca828a[0];wy2e8db[1519]<=coad8;wy2e8db[1509]<=eac1027;wy2e8db[1499]<=uvd9887;wy2e8db[1469]<=ou87900;wy2e8db[1398]<=ho5decc;wy2e8db[1373]<=yma977b[0];wy2e8db[1310]<=zk73e4c;wy2e8db[1207]<=jr389de;wy2e8db[1144]<=dzf9314;wy2e8db[1076]<=lq577c4[0];wy2e8db[1039]<=iea29c[0];wy2e8db[1023]<=ne52e43[0];wy2e8db[990]<=uk56c1;wy2e8db[981]<=uxda5a;wy2e8db[971]<=ir8138;wy2e8db[960]<=os629a8;wy2e8db[951]<=shcc43c;wy2e8db[891]<=jce4005[0];wy2e8db[839]<=uic4515;wy2e8db[749]<=vv7b310[0];wy2e8db[699]<=kd4bbd9;wy2e8db[572]<=sj9f262;wy2e8db[490]<=xwe1b4b;wy2e8db[480]<=yk4c535;wy2e8db[419]<=shf88a2;wy2e8db[245]<=ri9c369;wy2e8db[240]<=czc98a6;wy2e8db[209]<=hodf114;wy2e8db[122]<=ui5386d;wy2e8db[104]<=uxbbe22[0];wy2e8db[61]<=ir8a70d;wy2e8db[30]<=wj514e1;end         assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6<ksa36ce; dobd2d6=dobd2d6+1) begin dbc230[dobd2d6] = db84308[hq30de9]; hq86f4b = ^(hq30de9 & kf8c37[0]); hq30de9 = {hq30de9, hq86f4b}; end end 
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+`timescale 1 ns / 100 ps
+module jcdfe0e (
+    rxmac_clk,
+    reset_n,
+    rxmac_clk_en,
+
+    
+    lse661,
+    tu7330b,
+    zm9985b,
+
+    
+    rx_fifo_full,
+
+    
+    dz616d4,
+
+    
+    twb6a7,
+    gb5b53b,
+    jcda9dc,
+    kqd4ee3,
+
+    
+    rx_fifo_error,
+    rx_stat_vector,
+    rx_dbout,
+    rx_write,
+    rx_stat_en,
+    rx_eof,
+    rx_error
+);
+parameter mef0229         = 8;
+parameter qi2ebc5         = 20;
+parameter yx75e29         = 32;
+parameter phaf14d        = 8;
+parameter kq78a6e      = 4;
+input           rxmac_clk;
+input           reset_n;
+input           rxmac_clk_en;
+input           tu7330b;
+input           lse661;
+input  [1:0]    zm9985b;
+input           rx_fifo_full;
+input  [qi2ebc5-1:0]  dz616d4;
+output [phaf14d-1:0] twb6a7;
+output [phaf14d-1:0] gb5b53b;
+output                          jcda9dc;
+output                          kqd4ee3;
+output                          rx_fifo_error;
+output [yx75e29-1:0]  rx_stat_vector;
+output [mef0229-1:0]  rx_dbout;
+output                          rx_write;
+output                          rx_stat_en;
+output                          rx_eof;
+output                          rx_error;
+reg    [phaf14d:0]   mgacec5;
+reg    [phaf14d:0]   ie3b140;
+wire                            jcda9dc;
+wire                            kqd4ee3;
+reg                             rx_fifo_error;
+reg    [yx75e29-1:0]  rx_stat_vector;
+reg    [mef0229-1:0]  rx_dbout   ;
+reg    [mef0229-1:0]  qvbe6c1;
+reg    [mef0229-1:0]  jr9b06f;
+reg                             rx_write   ;
+reg                             kqc1bf7;
+reg                             irdfb9;
+reg                             wj6fdcd;
+reg                             rx_stat_en;
+reg                             rx_eof;
+reg                             rx_error;
+reg    [qi2ebc5-1:0]  cm6dd4f;
+reg    nr6ea78;
+wire   al753c7;
+wire   yma9e3c;
+reg    hb4f1e0;
+reg    me78f07;
+reg    blc7839;
+wire                            kf3c1ce;
+reg    [kq78a6e-1:0] yz73a0;
+reg    qv39d05;
+wire   [phaf14d:0]   nr74168;
+reg    [phaf14d:0]   ym5a36;
+reg    rv2d1b1;
+reg    ea68d8f;
+reg    ay46c78;
+reg    cb363c0;
+reg uxb1e05;
+reg ir8f02d;
+reg [1 : 0] ui7816d;
+reg hoc0b68;
+reg [qi2ebc5 - 1 : 0] tj2da19;
+reg [phaf14d : 0] ww68671;
+reg [phaf14d : 0] vx19c49;
+reg [mef0229 - 1 : 0] vv71271;
+reg [mef0229 - 1 : 0] os49c72;
+reg sh4e391;
+reg zx71c8d;
+reg xl8e46f;
+reg [qi2ebc5 - 1 : 0] hd91bf9;
+reg mg8dfce;
+reg cz6fe71;
+reg qt7f38d;
+reg hbf9c6d;
+reg kqce36f;
+reg nr71b79;
+reg co8dbcf;
+reg [kq78a6e - 1 : 0] gb6f3c8;
+reg rg79e44;
+reg [phaf14d : 0] jc7911b;
+reg [phaf14d : 0] cz446d7;
+reg sj236bc;
+reg fc1b5e4;
+reg bydaf22;
+reg bld7913;
+reg [2047:0] wy2e8db;
+wire [27:0] vv746d9;
+
+localparam ksa36ce = 28,tw1b670 = 32'hfdffca8b;
+localparam [31:0] icdb382 = tw1b670;
+localparam mece084 = tw1b670 & 4'hf;
+localparam [11:0] ou8210c = 'h7ff;
+wire [(1 << mece084) -1:0] db84308;
+reg [ksa36ce-1:0] dbc230;
+reg [mece084-1:0] kf8c37 [0:1];
+reg [mece084-1:0] hq30de9;
+reg hq86f4b;
+integer hd37a5a;
+integer dobd2d6;
+
+
+
+
+
+
+
+
+
+                                        
+
+
+
+
+
+
+
+
+
+
+
+
+                                               
+
+
+
+
+
+
+
+
+
+
+
+                                                                                                      
+
+                                                                                                      
+
+
+
+
+
+
+assign twb6a7 = ww68671[phaf14d-1:0];
+assign gb5b53b = vx19c49[phaf14d-1:0];
+assign nr74168    = ({(ww68671[phaf14d] ^ vx19c49[phaf14d]),        ww68671[phaf14d-1:0]}) - ({1'b0, vx19c49[phaf14d-1:0]});
+
+
+always @ (posedge rxmac_clk or negedge reset_n) begin     if (!reset_n) begin        nr6ea78   <= 0;        hb4f1e0   <= 0;     end     else if (rxmac_clk_en) begin        hb4f1e0   <= qt7f38d;        if ((|gb6f3c8) | (cz6fe71)) begin   nr6ea78 <= 1;     end else begin   nr6ea78 <= 0;        end     end
+end
+always @ (posedge rxmac_clk or negedge reset_n) begin    if (!reset_n) begin        yz73a0     <= 4'h0;        qv39d05        <= 1'b0;        blc7839       <= 1'b0;        mgacec5  <= 9'd0;        ie3b140   <= 9'd0;        ym5a36     <= 9'd0;        rv2d1b1      <= 1'b0;        ea68d8f <= 1'b0;        cm6dd4f   <= 1'b0;        rx_stat_vector     <= 32'b0;        rx_dbout           <= 8'd0;        qvbe6c1        <= 8'd0;        jr9b06f        <= 8'd0;        rx_write           <= 1'b0;        kqc1bf7        <= 1'b0;        irdfb9        <= 1'b0;        wj6fdcd     <= 1'b0;        rx_stat_en         <= 1'b0;        rx_eof             <= 1'b0;        rx_error           <= 1'b0;        me78f07     <= 1'b0;        ay46c78 <= 1'b0;        cb363c0  <= 1'b0;        rx_fifo_error       <= 1'b0;    end    else if (rxmac_clk_en) begin            cm6dd4f <= tj2da19;
+                        rx_fifo_error   <= co8dbcf | (rx_fifo_error & ~rx_eof);                if ((uxb1e05 == 1) & (ui7816d == 3)) begin            me78f07 <= 1;     end else begin            me78f07 <= 0; end     ay46c78 <= kqce36f;        cb363c0 <= ir8f02d;  if (nr71b79 == 1) begin            yz73a0 <= 0;         end else if (!qt7f38d && bydaf22) begin            yz73a0 <= gb6f3c8 + 4'b0001;          end else if (qt7f38d && !bydaf22) begin            yz73a0 <= gb6f3c8 - 4'b0001;          end                if ((jc7911b[phaf14d-1:1] == 0) && ((jc7911b[0] == 0)           || (jcda9dc == 1))) begin           blc7839   <= 1;        end else begin           blc7839   <= 0;        end        if (jc7911b[phaf14d-1:2] == 6'b111111) begin           qv39d05    <= 1;        end else begin           qv39d05    <= 0;        end
+       if (kqce36f)            ym5a36 <= ww68671 + 8'd1;         if (uxb1e05)            mgacec5 <= ww68671 + 8'd1;                                                            else if (bld7913)            mgacec5 <= cz446d7;                                                                  if (jcda9dc)            ie3b140 <= vx19c49 + 8'd1;   
+        rv2d1b1    <= jcda9dc;        ea68d8f    <= sj236bc;   if (hd91bf9[18]) begin            rx_stat_vector <= {hd91bf9[15:0], tj2da19[15:0]};     end        jr9b06f        <= hd91bf9[7:0];      qvbe6c1        <= os49c72;      rx_dbout           <= vv71271;        irdfb9        <= fc1b5e4 & ~hoc0b68 &                                ~hd91bf9[19];        kqc1bf7        <= zx71c8d;      rx_write           <= sh4e391;        wj6fdcd     <= sj236bc & hd91bf9[18];        rx_stat_en         <= xl8e46f;        rx_eof             <= fc1b5e4 & hd91bf9[17];        rx_error           <= fc1b5e4 & hd91bf9[16];    end
+end
+
+
+
+
+
+
+assign al753c7 = (jc7911b[phaf14d-1:0] >= 7'h42);
+
+
+assign kqd4ee3 = uxb1e05 & ~rg79e44;
+assign jcda9dc = mg8dfce & ~nr71b79                  & ~qt7f38d & ~hbf9c6d;
+
+
+assign yma9e3c = sj236bc & hd91bf9[18];
+
+
+
+
+
+
+assign kf3c1ce = (mg8dfce | rx_write) & hoc0b68 & ~nr71b79 &                          ~qt7f38d;
+
+always@* begin uxb1e05<=vv746d9[0];ir8f02d<=vv746d9[1];ui7816d<={zm9985b>>1,vv746d9[2]};hoc0b68<=vv746d9[3];tj2da19<={dz616d4>>1,vv746d9[4]};ww68671<={mgacec5>>1,vv746d9[5]};vx19c49<={ie3b140>>1,vv746d9[6]};vv71271<={qvbe6c1>>1,vv746d9[7]};os49c72<={jr9b06f>>1,vv746d9[8]};sh4e391<=vv746d9[9];zx71c8d<=vv746d9[10];xl8e46f<=vv746d9[11];hd91bf9<={cm6dd4f>>1,vv746d9[12]};mg8dfce<=vv746d9[13];cz6fe71<=vv746d9[14];qt7f38d<=vv746d9[15];hbf9c6d<=vv746d9[16];kqce36f<=vv746d9[17];nr71b79<=vv746d9[18];co8dbcf<=vv746d9[19];gb6f3c8<={yz73a0>>1,vv746d9[20]};rg79e44<=vv746d9[21];jc7911b<={nr74168>>1,vv746d9[22]};cz446d7<={ym5a36>>1,vv746d9[23]};sj236bc<=vv746d9[24];fc1b5e4<=vv746d9[25];bydaf22<=vv746d9[26];bld7913<=vv746d9[27];end
+always@* begin wy2e8db[2047]<=tu7330b;wy2e8db[2046]<=zm9985b[0];wy2e8db[2044]<=rx_fifo_full;wy2e8db[2040]<=dz616d4[0];wy2e8db[2032]<=mgacec5[0];wy2e8db[2017]<=ie3b140[0];wy2e8db[1987]<=qvbe6c1[0];wy2e8db[1926]<=jr9b06f[0];wy2e8db[1804]<=kqc1bf7;wy2e8db[1803]<=ym5a36[0];wy2e8db[1560]<=irdfb9;wy2e8db[1558]<=rv2d1b1;wy2e8db[1550]<=hb4f1e0;wy2e8db[1072]<=wj6fdcd;wy2e8db[1069]<=ea68d8f;wy2e8db[1052]<=me78f07;wy2e8db[1023]<=lse661;wy2e8db[901]<=nr74168[0];wy2e8db[775]<=yma9e3c;wy2e8db[450]<=qv39d05;wy2e8db[387]<=al753c7;wy2e8db[225]<=yz73a0[0];wy2e8db[193]<=nr6ea78;wy2e8db[183]<=cb363c0;wy2e8db[112]<=kf3c1ce;wy2e8db[96]<=cm6dd4f[0];wy2e8db[91]<=ay46c78;wy2e8db[56]<=blc7839;end         assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6<ksa36ce; dobd2d6=dobd2d6+1) begin dbc230[dobd2d6] = db84308[hq30de9]; hq86f4b = ^(hq30de9 & kf8c37[0]); hq30de9 = {hq30de9, hq86f4b}; end end 
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+`timescale 1 ns / 100 ps
+module vvc21a9 (
+
+    rxmac_clk,
+    reset_n,
+    rxmac_clk_en,
+
+    
+    ne52e43,
+
+    
+    aa573e,
+    yk78487,
+    fnc86c0,
+    wl121c7,
+
+    
+    ep90e3c,
+
+    
+
+    medb299,
+    fca2a3b,
+
+    
+
+    zxc790f,
+    ux3c87e,
+    lqe43f5,
+    ec21fab,
+    wyfd58,
+    bl7eac0,
+    kqf5606,
+    cbab030,
+    lq58184,
+    byc0c23,
+    ph611b,
+    vk308df,
+    rv846fb,
+    ir237de
+
+);
+parameter mef0229         = 8;
+parameter psdf7a3           = 14;
+parameter dmfbd1a            = 16;
+parameter ayde8d2            = 16;
+input           rxmac_clk;
+input           reset_n;
+input           rxmac_clk_en;
+input           aa573e;
+input           yk78487;
+input           fnc86c0;
+input           wl121c7;
+input           fca2a3b;
+input           medb299;
+input  [mef0229-1:0]  ne52e43;
+input  [dmfbd1a-1:0]  ep90e3c;
+output          zxc790f;
+output          ux3c87e;
+output          lqe43f5;
+output          kqf5606;
+output          cbab030;
+output          lq58184;
+output          ph611b;
+output          rv846fb;
+output          wyfd58;
+output          ir237de;
+output [ayde8d2-1:0]  byc0c23;
+output [dmfbd1a-1:0]  vk308df;
+output [psdf7a3-1:0] ec21fab;
+output [psdf7a3-1:0] bl7eac0;
+reg             zxc790f;
+reg             ux3c87e;
+reg             lqe43f5;
+reg             kqf5606;
+reg             cbab030;
+reg             lq58184;
+reg             rv846fb;
+reg             ir237de;
+reg    [psdf7a3-1:0]    bl7eac0;
+reg    [psdf7a3-1:0]   ec21fab;
+reg    [dmfbd1a-1:0]    vk308df;
+reg    [mef0229-1:0]  vie1324;
+wire            ph611b;
+wire   [ayde8d2-1:0]    byc0c23;
+reg            wyfd58;
+localparam gd23e71          = 16'h8808;
+localparam qi1f38d        = 16'h8100;
+localparam nrf9c68      = 16'd46;
+localparam goce347  = 16'd42;
+localparam hb71a39 = 9;
+localparam gq8d1cf      = 9'b000000001;
+localparam ay68e78     = 9'b000000010;
+localparam vi473c0     = 9'b000000100;
+localparam sj39e03   = 9'b000001000;
+localparam vicf01d   = 9'b000010000;
+localparam ui780eb    = 9'b000100000;
+localparam hoc0758    = 9'b001000000;
+localparam hd3ac2 = 9'b010000000;
+localparam gd1d616 = 9'b100000000;
+wire            neeb0b5;
+wire            vi585aa;
+wire            fnc2d53;
+wire            rv16a9e;
+wire            vxb54f7;
+wire            ntaa7be;
+wire            ui53df6;
+wire            tj9efb1;
+wire            off7d8f;
+reg    [hb71a39-1:0] rtf63e4;
+reg             kfb1f27;
+reg             gd8f93d;
+reg             by7c9ec;
+reg             pse4f63;
+reg   [hb71a39-1:0] rv3d8d7;
+reg jr389de;
+reg [mef0229 - 1 : 0] uk3bdce;
+reg oufa7e;
+reg fpbfe8f;
+reg ksb9c0d;
+reg eafa3f1;
+reg [dmfbd1a - 1 : 0] cb8fc48;
+reg xj7e244;
+reg jcf1227;
+reg [mef0229 - 1 : 0] by489d2;
+reg sh44e93;
+reg vx2749d;
+reg do3a4ee;
+reg hbd2773;
+reg ng93b9e;
+reg mg9dcf3;
+reg faee798;
+reg jc73cc2;
+reg vx9e612;
+reg [hb71a39 - 1 : 0] ks984b7;
+reg vvc25b9;
+reg sj12dcf;
+reg ba96e7d;
+reg vkb73eb;
+reg [hb71a39 - 1 : 0] pscfad9;
+reg xy14b7f;
+reg [2047:0] wy2e8db;
+wire [24:0] vv746d9;
+
+localparam ksa36ce = 25,tw1b670 = 32'hfdffe06b;
+localparam [31:0] icdb382 = tw1b670;
+localparam mece084 = tw1b670 & 4'hf;
+localparam [11:0] ou8210c = 'h7ff;
+wire [(1 << mece084) -1:0] db84308;
+reg [ksa36ce-1:0] dbc230;
+reg [mece084-1:0] kf8c37 [0:1];
+reg [mece084-1:0] hq30de9;
+reg hq86f4b;
+integer hd37a5a;
+integer dobd2d6;
+
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+                                        
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+                                        
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+
+assign neeb0b5 = fpbfe8f && ({by489d2, uk3bdce} == gd23e71);
+assign vi585aa   = fpbfe8f && ({by489d2, uk3bdce} != gd23e71);
+
+
+
+
+assign fnc2d53 = fpbfe8f && ({by489d2, uk3bdce} == qi1f38d);
+
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+
+assign rv16a9e = ((fpbfe8f &                             (sh44e93 |                             (~sh44e93 & ~do3a4ee &&                             {by489d2, uk3bdce} < nrf9c68))) |       (sj12dcf && {by489d2, uk3bdce} < goce347));
+
+
+
+
+
+assign tj9efb1 = (jcf1227 | xj7e244) &                            ba96e7d && ({by489d2, uk3bdce} == cb8fc48);
+assign ui53df6 = ba96e7d && ({by489d2, uk3bdce} != cb8fc48);
+assign off7d8f = xj7e244 & vx2749d;
+
+
+
+
+assign vxb54f7 = ((fpbfe8f & ~do3a4ee) |                           (sj12dcf) &&                           {by489d2, uk3bdce} >= 16'h0600);
+
+
+
+assign ntaa7be = fpbfe8f & ~sh44e93;
+
+assign ph611b = vvc25b9;      
+assign byc0c23 = {by489d2, uk3bdce};  
+
+always @ (posedge rxmac_clk or negedge reset_n) begin    if (!reset_n) begin        zxc790f    <= 1'b0;                        ux3c87e <= 1'b0;        lqe43f5  <= 1'b0;        kqf5606   <= 1'b0;        cbab030  <= 1'b0;        lq58184    <= 1'b0;        ec21fab  <= 14'b0;        bl7eac0  <= 14'b0;        vk308df    <= 16'b0;        jr389de <= 1'b0;        rv3d8d7     <= gq8d1cf;        rv846fb <= 1'b0;        ir237de <= 1'b0;        wyfd58 <= 1'b0;        vie1324 <= 0;    end    else if (rxmac_clk_en) begin
+        vie1324 <= uk3bdce;        jr389de <= ksb9c0d;                wyfd58 <= (fpbfe8f & ~do3a4ee)                                            | sj12dcf;                if (xy14b7f)            rv3d8d7     <= gq8d1cf;        else begin                        rv3d8d7         <= ks984b7;                        if (eafa3f1)               bl7eac0 <= bl7eac0 - 14'd1;        end                        if (fpbfe8f && sh44e93)            bl7eac0 <= 14'd46;        else if ((fpbfe8f && !lqe43f5) || sj12dcf) begin            ec21fab <= {by489d2[5:0], uk3bdce};            bl7eac0 <= {by489d2[5:0], uk3bdce};        end                if (vkb73eb)            vk308df <= {by489d2, uk3bdce};                        if (mg9dcf3)            zxc790f <= mg9dcf3;        else if (oufa7e)            zxc790f <= 1'b0;        else            zxc790f <= zxc790f;        if (sh44e93)            ux3c87e <= sh44e93;        else if (oufa7e)            ux3c87e <= 1'b0;        else            ux3c87e <= ux3c87e;        if (ng93b9e)            lq58184 <= ng93b9e;        else if (oufa7e)            lq58184 <= 1'b0;        else            lq58184 <= lq58184;        if (hbd2773)            cbab030 <= hbd2773;        else if (oufa7e)            cbab030 <= 1'b0;        else            cbab030 <= cbab030;        if (jc73cc2)            kqf5606 <= jc73cc2;        else if (oufa7e)            kqf5606 <= 1'b0;        else            kqf5606 <= kqf5606;        if (faee798)            rv846fb <= faee798;        else if (oufa7e)            rv846fb <= 1'b0;        else            rv846fb <= rv846fb;        if (vx9e612)            ir237de <= vx9e612;        else if (oufa7e)            ir237de <= 1'b0;        else            ir237de <= ir237de;        if (do3a4ee)            lqe43f5 <= do3a4ee;        else if (oufa7e)            lqe43f5 <= 1'b0;        else            lqe43f5 <= lqe43f5;    end
+end
+
+always @ (pscfad9 or fpbfe8f or do3a4ee or          sh44e93 or faee798) begin    case (pscfad9)                gq8d1cf : begin            if (fpbfe8f && do3a4ee) begin                rtf63e4 = ay68e78;                                                                           kfb1f27 = 1'b0;                           gd8f93d = 1'b0;                by7c9ec = 1'b0;                pse4f63 = 1'b0;            end            else if (fpbfe8f && sh44e93) begin                rtf63e4 = ui780eb;                                                                          kfb1f27 = 1'b0;                           gd8f93d = 1'b0;                by7c9ec = 1'b0;                pse4f63 = 1'b0;            end            else begin                rtf63e4 = gq8d1cf;                                                                            kfb1f27 = 1'b0;                gd8f93d = 1'b0;                by7c9ec = 1'b0;                pse4f63 = 1'b0;            end        end           ay68e78 : begin                rtf63e4 = vi473c0;                                                                           kfb1f27 = 1'b0;                           gd8f93d = 1'b0;                by7c9ec = 1'b0;                pse4f63 = 1'b0;        end  vi473c0 : begin            rtf63e4 = sj39e03;                       kfb1f27 = 1'b1;                          gd8f93d = 1'b0;            by7c9ec = 1'b0;            pse4f63 = 1'b0;        end                sj39e03 : begin            rtf63e4 = vicf01d;                      kfb1f27 = 1'b0;            gd8f93d = 1'b0;            by7c9ec = 1'b0;            pse4f63 = 1'b0;        end     vicf01d : begin            rtf63e4 = gq8d1cf;                         kfb1f27 = 1'b0;            gd8f93d = 1'b1;                          by7c9ec = 1'b0;            pse4f63 = 1'b0;        end                ui780eb : begin            rtf63e4 = hoc0758;                      kfb1f27 = 1'b0;            gd8f93d = 1'b0;            by7c9ec = 1'b0;            pse4f63 = 1'b0;        end   hoc0758 : begin            if (faee798) begin                rtf63e4 = gq8d1cf;                         kfb1f27 = 1'b0;                gd8f93d = 1'b0;                by7c9ec = 1'b1;                           pse4f63 = 1'b0;            end            else begin                rtf63e4 = hd3ac2;                     kfb1f27 = 1'b0;                gd8f93d = 1'b0;                by7c9ec = 1'b1;                           pse4f63 = 1'b0;            end        end                hd3ac2 : begin             rtf63e4 = gd1d616;             kfb1f27 = 1'b0;             gd8f93d = 1'b0;             by7c9ec = 1'b0;             pse4f63 = 1'b0;         end        gd1d616 : begin            rtf63e4 = gq8d1cf;                         kfb1f27 = 1'b0;            gd8f93d = 1'b0;            by7c9ec = 1'b0;            pse4f63 = 1'b1;                        end                default : begin            rtf63e4 = gq8d1cf;            kfb1f27 = 1'b0;            gd8f93d = 1'b0;            by7c9ec = 1'b0;            pse4f63 = 1'b0;        end    endcase
+end
+always@* begin uk3bdce<={ne52e43>>1,vv746d9[0]};oufa7e<=vv746d9[1];fpbfe8f<=vv746d9[2];ksb9c0d<=vv746d9[3];eafa3f1<=vv746d9[4];cb8fc48<={ep90e3c>>1,vv746d9[5]};xj7e244<=vv746d9[6];jcf1227<=vv746d9[7];by489d2<={vie1324>>1,vv746d9[8]};sh44e93<=vv746d9[9];vx2749d<=vv746d9[10];do3a4ee<=vv746d9[11];hbd2773<=vv746d9[12];ng93b9e<=vv746d9[13];mg9dcf3<=vv746d9[14];faee798<=vv746d9[15];jc73cc2<=vv746d9[16];vx9e612<=vv746d9[17];ks984b7<={rtf63e4>>1,vv746d9[18]};vvc25b9<=vv746d9[19];sj12dcf<=vv746d9[20];ba96e7d<=vv746d9[21];vkb73eb<=vv746d9[22];pscfad9<={rv3d8d7>>1,vv746d9[23]};xy14b7f<=vv746d9[24];end
+always@* begin wy2e8db[2047]<=aa573e;wy2e8db[2046]<=yk78487;wy2e8db[2044]<=fnc86c0;wy2e8db[2041]<=wl121c7;wy2e8db[2034]<=ep90e3c[0];wy2e8db[2021]<=medb299;wy2e8db[2017]<=by7c9ec;wy2e8db[1995]<=fca2a3b;wy2e8db[1986]<=pse4f63;wy2e8db[1943]<=vie1324[0];wy2e8db[1925]<=rv3d8d7[0];wy2e8db[1855]<=tj9efb1;wy2e8db[1838]<=neeb0b5;wy2e8db[1803]<=jr389de;wy2e8db[1662]<=off7d8f;wy2e8db[1628]<=vi585aa;wy2e8db[1487]<=ntaa7be;wy2e8db[1276]<=rtf63e4[0];wy2e8db[1209]<=fnc2d53;wy2e8db[1023]<=ne52e43[0];wy2e8db[1008]<=gd8f93d;wy2e8db[927]<=ui53df6;wy2e8db[743]<=vxb54f7;wy2e8db[504]<=kfb1f27;wy2e8db[371]<=rv16a9e;end         assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6<ksa36ce; dobd2d6=dobd2d6+1) begin dbc230[dobd2d6] = db84308[hq30de9]; hq86f4b = ^(hq30de9 & kf8c37[0]); hq30de9 = {hq30de9, hq86f4b}; end end 
+endmodule
+
+
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+
+`timescale 1 ns / 100 ps
+module ldd83e0 (
+   ayc1f07, 
+   ecf839, 
+   lq7c1c8,
+   mee0e42,
+   kf7210,
+   ir39085,
+   rtc842c,
+   lq42166,
+   ou10b33,
+   rxmac_clk_en,
+   ux2ccc5
+   );
+output [5:0] ayc1f07;
+output       ecf839;
+input  [7:0]  lq7c1c8;
+input  [31:0]  lq42166;
+input         mee0e42;
+input         kf7210;
+input         ir39085;
+input         rtc842c;
+input         ou10b33;
+input         rxmac_clk_en;
+input         ux2ccc5;
+reg    [31:0] yk4962f;
+reg    [5:0] ayc1f07;
+reg          ecf839;
+wire   [31:0] rgc5e2a;
+wire   [31:0] ls2f153;
+reg [7 : 0] ea78a9a;
+reg nec54d1;
+reg ba2a68a;
+reg cm53452;
+reg an9a290;
+reg [31 : 0] med1484;
+reg [31 : 0] gd8a421;
+reg [31 : 0] fa5210d;
+reg [31 : 0] yz9086a;
+reg [2047:0] wy2e8db;
+wire [8:0] vv746d9;
+
+localparam ksa36ce = 9,tw1b670 = 32'hfdffca8b;
+localparam [31:0] icdb382 = tw1b670;
+localparam mece084 = tw1b670 & 4'hf;
+localparam [11:0] ou8210c = 'h7ff;
+wire [(1 << mece084) -1:0] db84308;
+reg [ksa36ce-1:0] dbc230;
+reg [mece084-1:0] kf8c37 [0:1];
+reg [mece084-1:0] hq30de9;
+reg hq86f4b;
+integer hd37a5a;
+integer dobd2d6;
+
+
+
+
+
+assign ls2f153[0] = ~gd8a421[0];
+assign ls2f153[1] = ~gd8a421[1];
+assign ls2f153[2] = gd8a421[2];
+assign ls2f153[3] = ~gd8a421[3];
+assign ls2f153[4] = ~gd8a421[4];
+assign ls2f153[5] = ~gd8a421[5];
+assign ls2f153[6] = ~gd8a421[6];
+assign ls2f153[7] = gd8a421[7];
+assign ls2f153[8] = ~gd8a421[8];
+assign ls2f153[9] = gd8a421[9];
+assign ls2f153[10] = ~gd8a421[10];
+assign ls2f153[11] = ~gd8a421[11];
+assign ls2f153[12] = ~gd8a421[12];
+assign ls2f153[13] = gd8a421[13];
+assign ls2f153[14] = ~gd8a421[14];
+assign ls2f153[15] = ~gd8a421[15];
+assign ls2f153[16] = gd8a421[16];
+assign ls2f153[17] = gd8a421[17];
+assign ls2f153[18] = ~gd8a421[18];
+assign ls2f153[19] = gd8a421[19];
+assign ls2f153[20] = gd8a421[20];
+assign ls2f153[21] = gd8a421[21];
+assign ls2f153[22] = gd8a421[22];
+assign ls2f153[23] = gd8a421[23];
+assign ls2f153[24] = ~gd8a421[24];
+assign ls2f153[25] = ~gd8a421[25];
+assign ls2f153[26] = ~gd8a421[26];
+assign ls2f153[27] = gd8a421[27];
+assign ls2f153[28] = gd8a421[28];
+assign ls2f153[29] = gd8a421[29];
+assign ls2f153[30] = ~gd8a421[30];
+assign ls2f153[31] = ~gd8a421[31];
+
+always @ (posedge ou10b33 or negedge ux2ccc5)
+begin   if (!ux2ccc5) begin      yk4962f <= 32'hffffffff;      ayc1f07 <= 6'b000000;      ecf839 <= 0;   end   else if (rxmac_clk_en) begin      if (nec54d1) begin         yk4962f <= fa5210d;      end else if (an9a290) begin         yk4962f <= med1484;      end      if (ba2a68a) begin         ayc1f07[5] <= fa5210d[30];         ayc1f07[4] <= fa5210d[29];         ayc1f07[3] <= fa5210d[28];         ayc1f07[2] <= fa5210d[27];         ayc1f07[1] <= fa5210d[26];         ayc1f07[0] <= fa5210d[25];      end      if (cm53452) begin if (yz9086a == 0) begin            ecf839 <= 0; end else begin    ecf839 <= 1; end      end else if (an9a290) begin         ecf839 <= 0;      end   end
+end
+
+assign rgc5e2a[0] = gd8a421[30] ^ ea78a9a[7] ^ ea78a9a[1] ^ gd8a421[24];
+assign rgc5e2a[1] = gd8a421[30] ^ ea78a9a[6] ^ ea78a9a[7] ^ gd8a421[31]                    ^ ea78a9a[0] ^ ea78a9a[1] ^ gd8a421[24] ^ gd8a421[25];
+assign rgc5e2a[2] = gd8a421[30] ^ ea78a9a[6] ^ ea78a9a[7] ^ gd8a421[31]                    ^ ea78a9a[0] ^ ea78a9a[1] ^ gd8a421[24] ^ gd8a421[25]    ^ gd8a421[26] ^ ea78a9a[5];
+assign rgc5e2a[3] = gd8a421[31] ^ ea78a9a[0] ^ gd8a421[25] ^ gd8a421[26]                    ^ ea78a9a[4] ^ gd8a421[27] ^ ea78a9a[5] ^ ea78a9a[6];
+assign rgc5e2a[4] = gd8a421[30] ^ ea78a9a[1] ^ gd8a421[24] ^ gd8a421[26]                  ^ ea78a9a[3] ^ ea78a9a[4] ^ gd8a421[27] ^ ea78a9a[5] ^ gd8a421[28]  ^ ea78a9a[7];
+assign rgc5e2a[5] = gd8a421[30] ^ gd8a421[31] ^ ea78a9a[0] ^ ea78a9a[1]                    ^ gd8a421[24] ^ gd8a421[25] ^ ea78a9a[2] ^ ea78a9a[3]    ^ ea78a9a[4] ^ gd8a421[27] ^ gd8a421[28] ^ ea78a9a[6]    ^ gd8a421[29] ^ ea78a9a[7];
+assign rgc5e2a[6] = gd8a421[30] ^ gd8a421[31] ^ ea78a9a[0] ^ ea78a9a[1]                    ^ gd8a421[25] ^ ea78a9a[2] ^ gd8a421[26] ^ ea78a9a[3]    ^ ea78a9a[5] ^ gd8a421[28] ^ ea78a9a[6] ^ gd8a421[29];
+assign rgc5e2a[7] = gd8a421[31] ^ ea78a9a[0] ^ gd8a421[24] ^ ea78a9a[2]                    ^ gd8a421[26] ^ ea78a9a[4] ^ gd8a421[27] ^ ea78a9a[5]    ^ gd8a421[29] ^ ea78a9a[7];
+assign rgc5e2a[8] = gd8a421[24] ^ gd8a421[25] ^ ea78a9a[3] ^ ea78a9a[4]                    ^ gd8a421[27] ^ gd8a421[28] ^ ea78a9a[6] ^ ea78a9a[7]    ^ gd8a421[0];
+assign rgc5e2a[9] = gd8a421[25] ^ ea78a9a[2] ^ gd8a421[26] ^ ea78a9a[3] ^ ea78a9a[5]                    ^ gd8a421[28] ^ ea78a9a[6] ^ gd8a421[29] ^ gd8a421[1];
+assign rgc5e2a[10] = gd8a421[24] ^ ea78a9a[2] ^ gd8a421[26] ^ ea78a9a[4]                     ^ gd8a421[27] ^ ea78a9a[5] ^ gd8a421[29] ^ ea78a9a[7]     ^ gd8a421[2];
+assign rgc5e2a[11] = gd8a421[3] ^ gd8a421[24] ^ gd8a421[25] ^ ea78a9a[3]                  ^ ea78a9a[4] ^ gd8a421[27] ^ gd8a421[28] ^ ea78a9a[6] ^ ea78a9a[7];
+assign rgc5e2a[12] = gd8a421[30] ^ gd8a421[4] ^ ea78a9a[1] ^ gd8a421[24]                  ^ gd8a421[25] ^ ea78a9a[2] ^ gd8a421[26] ^ ea78a9a[3] ^ ea78a9a[5]  ^ gd8a421[28] ^ ea78a9a[6] ^ gd8a421[29] ^ ea78a9a[7];
+assign rgc5e2a[13] = gd8a421[30] ^ gd8a421[31] ^ ea78a9a[0] ^ gd8a421[5]                  ^ ea78a9a[1] ^ gd8a421[25] ^ ea78a9a[2] ^ gd8a421[26] ^ ea78a9a[4]  ^ gd8a421[27] ^ ea78a9a[5] ^ ea78a9a[6] ^ gd8a421[29];
+assign rgc5e2a[14] = gd8a421[30] ^ gd8a421[31] ^ ea78a9a[0] ^ ea78a9a[1]                      ^ gd8a421[6] ^ gd8a421[26] ^ ea78a9a[3] ^ ea78a9a[4]      ^ gd8a421[27] ^ ea78a9a[5] ^ gd8a421[28];
+assign rgc5e2a[15] = gd8a421[31] ^ ea78a9a[0] ^ ea78a9a[2] ^ gd8a421[7] ^ ea78a9a[3]                     ^ ea78a9a[4] ^ gd8a421[27] ^ gd8a421[28] ^ gd8a421[29];
+assign rgc5e2a[16] = gd8a421[24] ^ ea78a9a[2] ^ ea78a9a[3] ^ gd8a421[8]                     ^ gd8a421[28] ^ gd8a421[29] ^ ea78a9a[7];
+assign rgc5e2a[17] = gd8a421[30] ^ ea78a9a[1] ^ gd8a421[25] ^ ea78a9a[2]                     ^ gd8a421[9] ^ ea78a9a[6] ^ gd8a421[29];
+assign rgc5e2a[18] = gd8a421[30] ^ gd8a421[31] ^ ea78a9a[0] ^ ea78a9a[1]                     ^ gd8a421[26] ^ ea78a9a[5] ^ gd8a421[10];
+assign rgc5e2a[19] = gd8a421[31] ^ ea78a9a[0] ^ ea78a9a[4] ^ gd8a421[27]                     ^ gd8a421[11];
+assign rgc5e2a[20] = gd8a421[12] ^ ea78a9a[3] ^ gd8a421[28];
+assign rgc5e2a[21] = gd8a421[13] ^ ea78a9a[2] ^ gd8a421[29];
+assign rgc5e2a[22] = gd8a421[14] ^ gd8a421[24] ^ ea78a9a[7];
+assign rgc5e2a[23] = gd8a421[30] ^ ea78a9a[1] ^ gd8a421[24] ^ gd8a421[15]                     ^ gd8a421[25] ^ ea78a9a[6] ^ ea78a9a[7];
+assign rgc5e2a[24] = gd8a421[31] ^ ea78a9a[0] ^ gd8a421[25] ^ gd8a421[16]                     ^ gd8a421[26] ^ ea78a9a[5] ^ ea78a9a[6];
+assign rgc5e2a[25] = gd8a421[26] ^ gd8a421[17] ^ ea78a9a[4]                     ^ gd8a421[27] ^ ea78a9a[5];
+assign rgc5e2a[26] = gd8a421[30] ^ ea78a9a[1] ^ gd8a421[24] ^ ea78a9a[3] ^ ea78a9a[4]                     ^ gd8a421[27] ^ gd8a421[18] ^ gd8a421[28] ^ ea78a9a[7];
+assign rgc5e2a[27] = gd8a421[31] ^ ea78a9a[0] ^ gd8a421[25] ^ ea78a9a[2] ^ ea78a9a[3]                     ^ gd8a421[28] ^ gd8a421[19] ^ ea78a9a[6] ^ gd8a421[29];
+assign rgc5e2a[28] = gd8a421[30] ^ ea78a9a[1] ^ ea78a9a[2] ^ gd8a421[26]                     ^ ea78a9a[5] ^ gd8a421[29] ^ gd8a421[20];
+assign rgc5e2a[29] = gd8a421[30] ^ gd8a421[21] ^ gd8a421[31] ^ ea78a9a[0]                     ^ ea78a9a[1] ^ ea78a9a[4] ^ gd8a421[27];
+assign rgc5e2a[30] = gd8a421[31] ^ gd8a421[22] ^ ea78a9a[0] ^ ea78a9a[3]                     ^ gd8a421[28];
+assign rgc5e2a[31] = gd8a421[23] ^ ea78a9a[2] ^ gd8a421[29];
+always@* begin ea78a9a<={lq7c1c8>>1,vv746d9[0]};nec54d1<=vv746d9[1];ba2a68a<=vv746d9[2];cm53452<=vv746d9[3];an9a290<=vv746d9[4];med1484<={lq42166>>1,vv746d9[5]};gd8a421<={yk4962f>>1,vv746d9[6]};fa5210d<={rgc5e2a>>1,vv746d9[7]};yz9086a<={ls2f153>>1,vv746d9[8]};end
+always@* begin wy2e8db[2047]<=mee0e42;wy2e8db[2046]<=kf7210;wy2e8db[2044]<=ir39085;wy2e8db[2040]<=rtc842c;wy2e8db[2032]<=lq42166[0];wy2e8db[2017]<=yk4962f[0];wy2e8db[1987]<=rgc5e2a[0];wy2e8db[1926]<=ls2f153[0];wy2e8db[1023]<=lq7c1c8[0];end         assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6<ksa36ce; dobd2d6=dobd2d6+1) begin dbc230[dobd2d6] = db84308[hq30de9]; hq86f4b = ^(hq30de9 & kf8c37[0]); hq30de9 = {hq30de9, hq86f4b}; end end 
+endmodule
+
+
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+
+
+`timescale 1 ns / 100 ps
+module ieacc06 (
+    rxmac_clk,
+    reset_n,
+    rxmac_clk_en,
+
+    
+    mrf282b,     
+    xy304af,     
+    aa8257a,    
+    gd12bd1,    
+    kf95e8d,
+
+    
+    ne52e43,
+    yxe7c08,
+    ec3e045,
+    yk5cf81,
+
+    
+    ie151db,
+    zma8ed9,
+    ne476ca,
+    ec3b653,
+
+    
+    zxc790f,
+    ux3c87e,
+    lqe43f5,
+    ec21fab,
+    kqf5606,
+    cbab030,
+    lq58184,
+    rv846fb,
+    wyfd58,
+    bl7eac0,
+    uk2b76b,
+
+    
+    ignore_pkt,
+
+    
+    thddac5,
+    kded62e,
+    dz6b175,
+    tu58bae,
+    jcc5d72,
+    ym2eb93,
+
+    
+    ecf839,
+
+    
+    aa573e,
+    fnc86c0,
+
+    
+    ba93361,
+    ri99b0a,
+    vvcd852,
+
+    
+    lfa0ae7,
+    nr614bb,
+
+    
+    uka5df,
+
+    
+    yk78487,
+    wl121c7,
+
+    
+    zm9985b,
+    lse661,
+    tu7330b,
+
+    
+    mecb116,
+    zm14547,
+    ir39085,
+    hd22c50
+);
+parameter mef0229         = 8;
+parameter psdf7a3           = 14;
+parameter qi2ebc5         = 20;
+parameter yx75e29         = 32;
+parameter ec87d2e              = 32;
+parameter gq3e970       = 9;
+input           rxmac_clk;
+input           reset_n;
+input           rxmac_clk_en;
+input           mrf282b;
+input           xy304af;
+input           aa8257a;
+input           gd12bd1;
+input           kf95e8d;
+input           ec3e045;
+input           yk5cf81;
+input           yxe7c08;
+input  [mef0229-1:0]  ne52e43;
+input           ie151db;
+input           zma8ed9;
+input           ne476ca;
+input           ec3b653;
+input           zxc790f;
+input           ux3c87e;
+input           lqe43f5;
+input           kqf5606;
+input           uk2b76b;
+input           cbab030;
+input           lq58184;
+input           rv846fb;
+input           wyfd58;
+input  [psdf7a3-1:0] bl7eac0;
+input  [psdf7a3-1:0]    ec21fab;
+input           ignore_pkt;
+input           thddac5;
+input           kded62e;
+input  [psdf7a3-1:0]    dz6b175;
+input           tu58bae;
+input           jcc5d72;
+input  ym2eb93;
+input           ecf839;
+output          aa573e;
+output          lfa0ae7;
+output          nr614bb;
+output          yk78487;
+output          lse661;
+output          tu7330b;
+output          fnc86c0;
+output          wl121c7;
+output [qi2ebc5-1:0]  zm9985b;
+output          ba93361;
+output [gq3e970-1:0] ri99b0a;
+output          vvcd852;
+output          uka5df;
+output [ec87d2e-1:0]  mecb116;
+output                     zm14547;
+output                     ir39085;
+output                     hd22c50;
+wire            aa573e;
+wire            yk78487;
+wire            lse661;
+wire            tu7330b;
+wire   [qi2ebc5-1:0]  zm9985b;
+reg             ba93361;
+wire   [ec87d2e-1:0]       mecb116;
+wire            zm14547;
+wire            hd22c50;
+reg             uka5df;
+reg    [gq3e970-1:0] ri99b0a;
+reg             vvcd852;
+localparam gbe71fc = 8;
+localparam ph38fe4       = 8'b00000001;
+localparam zxc7f27     = 8'b00000010;
+localparam tw3f93e     = 8'b00000100;
+localparam blfc9f2        = 8'b00001000;
+localparam pse4f97    = 8'b00010000;
+localparam jr27cba   = 8'b00100000;
+localparam ou3e5d7    = 8'b01000000;
+localparam qtf2eb9           = 8'b10000000;
+localparam wy975cc     = 1'b0;
+localparam fpbae60    = 1'b1;
+reg  [gbe71fc-1:0]   ecb9836;
+reg                      lfa0ae7;
+reg                      of60d8c;
+reg                      bn6c64;
+reg                      kf36326;
+reg                      gdb1935;
+reg                      fnc86c0;
+wire                     dz64d6b;
+wire                     wl121c7;
+wire                     tw35af5;
+wire                     zmad7ab;
+wire                     th6bd5b;
+wire                     wj5eadf;
+wire [psdf7a3-1:0] cbab7e8;
+wire                     mr5bf44;
+wire                     jcdfa25;
+reg  [gbe71fc-1:0]   wje895c;
+reg                      qt44ae4;
+reg                      do25725;
+reg  [2:0]               sw2b92b;
+reg                      me5c959;
+reg                  fae4ac8;
+reg [psdf7a3-1:0] ie2b213;
+reg [psdf7a3-1:0] pfc84c1;
+reg                      vi4260e;
+reg                      tj13073;
+reg                      ec9839e;
+reg                      wwc1cf1;
+reg [psdf7a3-1:0] by73c4b;
+reg                      jr9e25a;
+reg                      hof12d6;
+reg                      do896b2;
+reg                      en4b592;
+reg                      rt5ac95;
+reg [psdf7a3-1:0] twb257c;
+reg [psdf7a3-1:0] yz95f19;
+wire          vxaf8cc;
+wire          lq7c667;
+wire          pfe333a;
+wire          jr199d6;
+wire          ipcceb6;
+wire          ui675b5;
+wire          vk3ada8;
+reg  [qi2ebc5-1:0]   ksb6a15;
+reg           dbb50a8;
+wire          xya8546;
+wire          by42a33;
+wire [yx75e29-1:0]   zma8cd1;
+wire          nr614bb;
+reg           yz33451;
+reg           oh9a28d;
+reg           uid146c;
+reg           cb363c0;
+reg           yx51b0d;
+reg           sw8d86c;
+reg  [mef0229-1:0]  dz61b0b;
+reg           qvd85e                ;
+reg           ho6c2f5;
+reg           fn617ab;
+reg           jebd5f;
+reg    [4:0]  al5eafa;
+reg           qgf57d5;
+reg           ph2713b;
+wire          ld5f545;
+reg           wwfaa2e;
+wire          ir39085;
+reg           pua8b83;
+wire          nr45c1a;
+wire          ec2e0d7;
+wire          cz706b8;
+wire          pu835c4;
+wire          uk1ae23;
+reg           xjd7119;
+reg           lsb88ce;
+reg           qgc4673;
+reg           an23398;
+reg           tj19cc4;
+reg           icce626;
+reg           vi73131;
+reg           ou9898b;
+wire   [gq3e970-1:0] kf262c1;
+reg    [3:0] sw3160c;
+reg          ph8b060;
+reg          zk58307;
+reg          icc183b;
+reg wj6fb0f;
+reg cz60ece;
+reg ir7674;
+reg qi3b3a5;
+reg gbd9d29;
+reg [mef0229 - 1 : 0] uk3bdce;
+reg godee70;
+reg ep2983f;
+reg ay4c1fc;
+reg gb60fe0;
+reg oh7f04;
+reg je3f824;
+reg zxfc122;
+reg uie0916;
+reg vk48b0;
+reg qi24583;
+reg [psdf7a3 - 1 : 0] jr160cf;
+reg fpb067e;
+reg ng833f6;
+reg hd19fb3;
+reg rgcfd9e;
+reg nr7ecf2;
+reg [psdf7a3 - 1 : 0] qib3cb7;
+reg zz9e5b8;
+reg gbf2dc6;
+reg vk96e34;
+reg zmb71a3;
+reg [psdf7a3 - 1 : 0] uvc68db;
+reg ec346dc;
+reg eca36e0;
+reg xy1b700;
+reg osdb802;
+reg [gbe71fc - 1 : 0] qge008d;
+reg sw469;
+reg qv2348;
+reg do11a45;
+reg gq8d22a;
+reg by69150;
+reg ho48a83;
+reg pf4541b;
+reg ri2a0de;
+reg dz506f2;
+reg [psdf7a3 - 1 : 0] pu1bcbb;
+reg gode5db;
+reg kdf2ed8;
+reg [gbe71fc - 1 : 0] kfbb620;
+reg icdb105;
+reg bld8828;
+reg [2 : 0] uic4146;
+reg fc20a30;
+reg ec5182;
+reg [psdf7a3 - 1 : 0] os46086;
+reg [psdf7a3 - 1 : 0] ym8218a;
+reg ou10c51;
+reg ri86288;
+reg ks31443;
+reg cb8a218;
+reg [psdf7a3 - 1 : 0] mg8862d;
+reg ww43168;
+reg an18b41;
+reg nec5a0c;
+reg hd2d063;
+reg cm6831f;
+reg [psdf7a3 - 1 : 0] fpc7cd;
+reg [psdf7a3 - 1 : 0] qi1f373;
+reg nrf9b98;
+reg jpcdcc7;
+reg fn6e63f;
+reg jc731fe;
+reg wy98ff3;
+reg jpc7f98;
+reg vk3fcc6;
+reg [qi2ebc5 - 1 : 0] zxf3193;
+reg uk98c9f;
+reg shc64f8;
+reg vx327c5;
+reg [yx75e29 - 1 : 0] ep9f17b;
+reg uvf8bdc;
+reg lqc5ee5;
+reg pu2f72b;
+reg bld7913;
+reg endcad6;
+reg sue56b4;
+reg [mef0229 - 1 : 0] jp5ad08;
+reg mrd6847;
+reg gdb423d;
+reg wla11ec;
+reg qv8f65;
+reg [4 : 0] ho47b2d;
+reg hd3d96a;
+reg xl2296f;
+reg wj65abe;
+reg nt2d5f4;
+reg al6afa7;
+reg zk57d3d;
+reg gdbe9eb;
+reg zkf4f5c;
+reg vka7ae3;
+reg jr3d71b;
+reg xweb8de;
+reg ay5c6f3;
+reg the3799;
+reg ng1bcce;
+reg qgde673;
+reg nrf3398;
+reg do99cc7;
+reg kqce63a;
+reg [gq3e970 - 1 : 0] mg98e8b;
+reg [3 : 0] hbc7458;
+reg je3a2c7;
+reg ayd163b;
+reg ph8b1d9;
+reg [2047:0] wy2e8db;
+wire [111:0] vv746d9;
+
+localparam ksa36ce = 112,tw1b670 = 32'hfdffd42b;
+localparam [31:0] icdb382 = tw1b670;
+localparam mece084 = tw1b670 & 4'hf;
+localparam [11:0] ou8210c = 'h7ff;
+wire [(1 << mece084) -1:0] db84308;
+reg [ksa36ce-1:0] dbc230;
+reg [mece084-1:0] kf8c37 [0:1];
+reg [mece084-1:0] hq30de9;
+reg hq86f4b;
+integer hd37a5a;
+integer dobd2d6;
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+always @ (posedge rxmac_clk or negedge reset_n) begin    if (!reset_n) begin        sw3160c <= 4'h0;        ph8b060    <= wy975cc;        zk58307   <= 1'b0;        icc183b   <= 1'b0;    end    else if (rxmac_clk_en) begin
+       icc183b   <= ayd163b;
+        case (je3a2c7)            wy975cc : begin                          zk58307 <= 1'b0;       if (godee70 && hd3d96a) begin                 sw3160c <= hbc7458 + 1;                 ph8b060    <= fpbae60;       end       else begin                 sw3160c <= 4'h0;                 ph8b060    <= wy975cc;       end    end            fpbae60 : begin                          if (hd3d96a) begin    if (hbc7458 <= 4'd12 ) begin                       sw3160c <= hbc7458 + 1;                       ph8b060    <= fpbae60;            end    else begin                       ph8b060    <= wy975cc;            end       end       else begin     if (~ho47b2d[3] & ho47b2d[4]) begin                        ph8b060    <= wy975cc;    end    if (hbc7458 <= 4'd12) begin                       zk58307    <= 1'b1;            end    else begin                       zk58307    <= 1'b0;            end       end    end            default : begin                                  sw3160c <= 4'h0;       zk58307 <= 1'b0;               ph8b060    <= wy975cc;    end
+         endcase     end 
+
+end 
+
+
+
+
+always @ (posedge rxmac_clk or negedge reset_n) begin    if (!reset_n) begin        hof12d6 <= 1'b0;        do896b2 <= 1'b0;        wje895c           <= ph38fe4;        sw2b92b            <= 3'b000;        me5c959     <= 1'b0;        qgf57d5  <= 1'b0;        qvd85e      <= 1'b0;        ho6c2f5 <= 1'b0;        tj13073     <= 1'b0;        ec9839e <= 1'b0;        wwc1cf1     <= 1'b0;        jr9e25a     <= 1'b0;        vi73131     <= 1'b0;        ou9898b <= 1'b0;        fae4ac8   <= 1'b0;    end    else if (rxmac_clk_en) begin        vi73131    <= eca36e0;        ou9898b <= do99cc7;        if (ww43168)            wwc1cf1 <= ww43168;        else if (aa573e)            wwc1cf1 <= 1'b0;        else if (oh7f04)            wwc1cf1 <= 1'b0;        else            wwc1cf1 <= cb8a218;        jr9e25a          <= gb60fe0;        tj13073          <= gbf2dc6;        ec9839e     <= ri86288;        hof12d6      <= oh7f04;        do896b2 <= an18b41;        qgf57d5       <= wj6fb0f;        qvd85e           <= hd3d96a;        ho6c2f5      <= mrd6847;        me5c959          <= gb60fe0 |                                   (fc20a30 & ~by69150);        fae4ac8 <= sw469;        if(ho48a83)            sw2b92b <= uic4146 + 2'd1;        else if (aa573e)            sw2b92b <= 3'b000;                wje895c          <= qge008d;    end
+end
+
+
+
+
+
+
+
+
+
+assign yk78487 = ec5182;
+
+assign tw35af5 = fc20a30 | gb60fe0;
+assign dz64d6b = uic4146[2] & ~uic4146[1] & uic4146[0];
+
+always @ (kfbb620 or kqce63a or wj6fb0f or          hd3d96a or godee70 or ep2983f or          gb60fe0 or oh7f04 or by69150 or          uie0916 or vk48b0 or ks31443) begin    case (kfbb620)        ph38fe4 : begin                               if (!(kqce63a && wj6fb0f)) begin                ecb9836 = ph38fe4;                lfa0ae7 = 1'b0;                of60d8c = 1'b0;                kf36326 = 1'b0;                gdb1935 = 1'b0;                fnc86c0 = 1'b0;                bn6c64 = 1'b1;            end else begin                if(!ks31443)                            gdb1935 = 1'b0;                else                    gdb1935 = 1'b1;                    ecb9836 = zxc7f27;                    lfa0ae7 = 1'b1;                                of60d8c = 1'b0;                    kf36326 = 1'b0;                    fnc86c0 = 1'b0;                    bn6c64 = 1'b0;            end        end        zxc7f27 : begin                             if (ep2983f) begin                ecb9836 = blfc9f2;                lfa0ae7 = 1'b0;                of60d8c = 1'b0;                kf36326 = 1'b1;                     gdb1935 = 1'b0;                fnc86c0 = 1'b0;                bn6c64 = 1'b0;            end else if (godee70) begin                         ecb9836 = tw3f93e;                lfa0ae7 = 1'b0;                of60d8c = 1'b0;                kf36326 = 1'b0;                gdb1935 = 1'b0;                fnc86c0 = 1'b0;                bn6c64 = 1'b0;            end else if (!wj6fb0f) begin                        ecb9836 = ph38fe4;                lfa0ae7 = 1'b0;                of60d8c = 1'b0;                kf36326 = 1'b0;                gdb1935 = 1'b0;                fnc86c0 = 1'b0;                bn6c64 = 1'b0;            end else begin                                       ecb9836 = zxc7f27;                                                                lfa0ae7 = 1'b0;                of60d8c = 1'b0;                kf36326 = 1'b0;                gdb1935 = 1'b0;                fnc86c0 = 1'b0;                bn6c64 = 1'b0;            end        end        tw3f93e : begin                             if (gb60fe0) begin                             ecb9836 = pse4f97;                   lfa0ae7 = 1'b0;                of60d8c = 1'b0;                kf36326 = 1'b0;                gdb1935 = 1'b0;                fnc86c0 = 1'b0;                bn6c64 = 1'b0;            end else if (oh7f04) begin                    ecb9836 = blfc9f2;                                                                     lfa0ae7 = 1'b0;                of60d8c = 1'b0;                kf36326 = 1'b0;                gdb1935 = 1'b0;                fnc86c0 = 1'b0;                bn6c64 = 1'b0;            end else if (!hd3d96a) begin                  ecb9836 = ph38fe4;                lfa0ae7 = 1'b0;                of60d8c = 1'b0;                kf36326 = 1'b0;                gdb1935 = 1'b0;                fnc86c0 = 1'b1;                bn6c64 = 1'b0;            end else begin                ecb9836 = tw3f93e;                                                                  lfa0ae7 = 1'b0;                             of60d8c = 1'b0;                kf36326 = 1'b0;                gdb1935 = 1'b0;                fnc86c0 = 1'b0;                bn6c64 = 1'b0;            end        end        blfc9f2 : begin                                if (!wj6fb0f) begin                             ecb9836 = ph38fe4;                lfa0ae7 = 1'b0;                of60d8c = 1'b0;                kf36326 = 1'b0;                gdb1935 = 1'b0;                fnc86c0 = 1'b0;                bn6c64 = 1'b0;            end else begin                                         ecb9836 = blfc9f2;                lfa0ae7 = 1'b0;                of60d8c = 1'b0;                kf36326 = 1'b0;                gdb1935 = 1'b0;                fnc86c0 = 1'b0;                bn6c64 = 1'b0;            end        end        pse4f97 : begin                            if (by69150) begin                ecb9836 = jr27cba;                lfa0ae7 = 1'b0;                of60d8c = 1'b1;                      kf36326 = 1'b0;                     gdb1935 = 1'b0;                fnc86c0 = 1'b0;                bn6c64 = 1'b0;            end else if (!hd3d96a) begin                 ecb9836 = ph38fe4;                lfa0ae7 = 1'b0;                of60d8c = 1'b0;                kf36326 = 1'b0;                gdb1935 = 1'b0;                fnc86c0 = 1'b1;                bn6c64 = 1'b0;            end else begin                                    ecb9836 = pse4f97;                lfa0ae7 = 1'b0;                of60d8c = 1'b0;                kf36326 = 1'b0;                gdb1935 = 1'b0;                fnc86c0 = 1'b0;                bn6c64 = 1'b0;            end        end        jr27cba : begin                           if(uie0916 || vk48b0) begin                ecb9836 = ou3e5d7;                lfa0ae7 = 1'b0;                of60d8c = 1'b0;                kf36326 = 1'b0;                gdb1935 = 1'b0;                fnc86c0 = 1'b0;                bn6c64 = 1'b0;            end else if (!wj6fb0f) begin                        ecb9836 = ph38fe4;                lfa0ae7 = 1'b0;                of60d8c = 1'b0;                kf36326 = 1'b0;                gdb1935 = 1'b0;                fnc86c0 = 1'b1;                bn6c64 = 1'b0;            end else begin                                      ecb9836 = jr27cba;                lfa0ae7 = 1'b0;                of60d8c = 1'b0;                kf36326 = 1'b0;                gdb1935 = 1'b0;                fnc86c0 = 1'b0;                bn6c64 = 1'b0;            end        end        ou3e5d7 : begin                            if (!hd3d96a) begin                     ecb9836 = qtf2eb9;                lfa0ae7 = 1'b0;                of60d8c = 1'b0;                kf36326 = 1'b0;                gdb1935 = 1'b0;                fnc86c0 = 1'b0;                bn6c64 = 1'b0;            end else begin                                        ecb9836 = ou3e5d7;                lfa0ae7 = 1'b0;                of60d8c = 1'b0;                kf36326 = 1'b0;                gdb1935 = 1'b0;                fnc86c0 = 1'b0;                bn6c64 = 1'b0;            end        end        qtf2eb9 : begin                                   ecb9836 = ph38fe4;            lfa0ae7 = 1'b0;            of60d8c = 1'b0;            kf36326 = 1'b0;            gdb1935 = 1'b0;            fnc86c0 = 1'b0;            bn6c64 = 1'b0;        end        default : begin                                   ecb9836 = ph38fe4;
+            lfa0ae7 = 1'b0;            of60d8c = 1'b0;            kf36326 = 1'b0;            gdb1935 = 1'b0;            fnc86c0 = 1'b0;            bn6c64 = 1'b0;        end    endcase
+end
+
+
+
+
+
+
+assign zz197c5 = wj6fb0f;
+
+always @ (posedge rxmac_clk or negedge reset_n) begin    if (!reset_n) begin                 yz33451         <= 0;        oh9a28d           <= 0;        qt44ae4          <= 1'b0;        do25725        <= 1'b0;        dz61b0b    <= 8'h00;        uid146c        <= 1'b0;        cb363c0      <= 1'b0;        yx51b0d <= 1'b0;        sw8d86c <= 1'b0;        jebd5f              <= 1'b0;        ba93361                 <= 1'b0;        al5eafa[0] <= 1'b0;        al5eafa[1] <= 1'b0;        al5eafa[2] <= 1'b0;        al5eafa[3] <= 1'b0;        al5eafa[4] <= 1'b0;    end    else if (rxmac_clk_en) begin        al5eafa[0] <= mrd6847;        al5eafa[1] <= ho47b2d[0];        al5eafa[2] <= ho47b2d[1];        al5eafa[3] <= ho47b2d[2];        al5eafa[4] <= ho47b2d[3];                        if (shc64f8)            jebd5f <= shc64f8;        else if (aa573e)            jebd5f <= 1'b0;        else            jebd5f <= qv8f65;        yx51b0d <= wy98ff3;        sw8d86c <= endcad6;                        ba93361                 <= qv2348 & ~endcad6;        uid146c       <= aa573e;        cb363c0     <= tu7330b;        dz61b0b   <= uk3bdce;        yz33451        <= zz197c5;        oh9a28d          <= uk98c9f;                        if (ng833f6)            qt44ae4 <= nr7ecf2 | (icdb105 & uk98c9f);        else            qt44ae4 <= nr7ecf2                              | (icdb105 & uvf8bdc);                do25725 <= godee70           | (bld8828 & nrf9b98   & ~(oh7f04 & ~an18b41));    end
+end
+
+
+
+assign wl121c7 = icdb105 | nr7ecf2;
+assign lq7c667 = (qib3cb7 == 14'd1);
+
+always @ (zz197c5 or wl121c7 or jpcdcc7) begin    casex ({wl121c7, (jpcdcc7 & ec346dc)})             2'b0x : dbb50a8 = zz197c5;        2'b11 : dbb50a8 = 0;        default : dbb50a8 = zz197c5;    endcase
+end
+
+assign vxaf8cc = (ng833f6) ? lqc5ee5 : cz60ece;
+assign pfe333a = ~xweb8de & bld8828;
+assign ipcceb6 = bld8828;
+assign jr199d6 = (aa573e & ~tu7330b) |                           (pu2f72b & ~bld7913);
+assign lse661 = fn6e63f | jc731fe;
+assign vk3ada8 = aa573e | pu2f72b;
+always @ (aa573e or pu2f72b or ep9f17b or qgde673) begin    case({aa573e, pu2f72b})        2'b10 : ksb6a15 = {2'b11,1'b0,1'b0,ep9f17b[31:16]};        2'b01 : ksb6a15 = {2'b10,1'b1,qgde673,ep9f17b[15:0]};        default : ksb6a15 = 20'bxxxxxxxxxxxxxxxxxxxx;    endcase
+end
+assign zm9985b[19:0] = vk3fcc6                       ? zxf3193[19:0]                       : {12'h000, jp5ad08};
+
+
+
+
+
+
+
+
+
+
+assign xya8546 = (~mrd6847 & gdb423d) &                        endcad6;
+assign by42a33 = shc64f8 | qv8f65;
+assign aa573e = vx327c5                     ? sue56b4 & ~endcad6                     : cb8a218 & ~ep2983f & ~an18b41 &                       ~ho47b2d[3] & ho47b2d[4];
+
+
+
+
+
+
+
+assign ui675b5 = (ym8218a >= 14'd64);
+
+
+
+
+assign tu7330b = ((~vk96e34) ? (aa573e & ~wla11ec) : 1'b0) | (an18b41 & ~nec5a0c) | (ayd163b & ~ph8b1d9) | (xy1b700 & vk48b0 & aa573e) | (zz9e5b8 & aa573e);
+
+assign zmad7ab = godee70 | (ou10c51 & uvf8bdc);
+
+
+assign th6bd5b = wl121c7;
+assign wj5eadf = wl121c7 & wy98ff3;
+
+
+assign cbab7e8 = (~ng833f6)                                 ? mg8862d -14'd4                                 : qi1f373;
+
+assign mecb116 = 32'hffffffff;
+
+assign hd22c50  = lfa0ae7;
+assign ir39085 = ~hd3d96a & mrd6847;
+
+assign zm14547 = godee70 | al6afa7;
+
+
+
+assign ld5f545 = zmb71a3 & fpb067e &                           nt2d5f4 & wla11ec &                           ~(ng1bcce | osdb802);
+
+always @ (posedge rxmac_clk or negedge reset_n) begin    if (!reset_n) begin        rt5ac95      <= 1'b0;        en4b592     <= 1'b0;        twb257c <= 14'b0;        ie2b213    <= 14'b0;        pfc84c1 <= 14'b0;        vi4260e <= 1'b0;        fn617ab         <= 1'b0;        pua8b83        <= 1'b0;        lsb88ce     <= 1'b0;        qgc4673  <= 1'b0;        an23398      <= 1'b0;        tj19cc4         <= 1'b0;        wwfaa2e     <= 1'b0;        uka5df       <= 1'b0;        xjd7119      <= 1'b0;        by73c4b    <= 14'd0;        yz95f19    <= 14'd0;        ri99b0a       <= 9'd0;        vvcd852    <= 1'b0;        icce626 <= 1'b0;        ph2713b <= 1'b0;    end    else if (rxmac_clk_en) begin                        vvcd852    <= pu2f72b & ~bld7913;        if (pu2f72b && !bld7913)            ri99b0a   <= mg98e8b;                        wwfaa2e     <= ir39085;        uka5df       <= wj65abe;                        if (gq8d22a)            xjd7119 <= gq8d22a;        else if (lfa0ae7 && !gq8d22a)              xjd7119 <= 1'b0;                                                                                                else if (an18b41)                xjd7119 <= 1'b0;              else            xjd7119 <= xweb8de;        tj19cc4 <= ~jr3d71b;        if (ir7674 & wj6fb0f)            an23398 <= ir7674;        else if (pu2f72b)            an23398 <= 1'b0;        else            an23398 <= ng1bcce;        if (zkf4f5c)            qgc4673 <= zkf4f5c;        else if (pu2f72b)            qgc4673 <= 1'b0;        else            qgc4673 <= the3799;        ph2713b <= godee70;        if (xl2296f)            lsb88ce     <= gbd9d29;        if (nr614bb)                        icce626 <= ay4c1fc;                        pua8b83       <= godee70 | (al6afa7 & wj6fb0f);                        twb257c <= pu1bcbb;        en4b592 <= zk57d3d;        rt5ac95  <= kdf2ed8;        if (ou10c51 && !pf4541b)            fn617ab <= jpc7f98;        vi4260e <= pf4541b;        if (ou10c51 && !pf4541b)            ie2b213 <= ym8218a;        if (pf4541b) begin            pfc84c1 <= ym8218a + 14'd1;        end        else            pfc84c1 <= 14'd0;                if (dz506f2 && ng833f6 && uk98c9f)            yz95f19 <= qi1f373 + 14'd1;        if (ri2a0de && !ng833f6 && uvf8bdc)            by73c4b <= mg8862d + 14'd1;        else if (ww43168)            by73c4b <= 14'd0;    end
+end
+
+
+
+assign nr614bb = ww43168;
+
+
+assign nr45c1a = qi24583                    ? (os46086 > (uvc68db + 14'd4))                    : os46086 > uvc68db;
+assign ec2e0d7 = (os46086 < 14'd64);
+assign cz706b8 = do11a45;
+
+assign mr5bf44 = (os46086[6:0] != 7'd64);
+assign jcdfa25         = (jr160cf != fpc7cd);
+assign pu835c4 = gdbe9eb                            ? 1'b0                            : vk48b0 | ng833f6                              ? gode5db                              : hd19fb3                                ? 1'b0                                : cm6831f;
+
+assign uk1ae23  = ~(ng1bcce | osdb802 | vka7ae3);
+assign zma8cd1[31]   = hd2d063;     
+assign zma8cd1[30]   = gdbe9eb;         
+assign zma8cd1[29]   = ay5c6f3;     
+assign zma8cd1[28]   = nrf3398;
+assign zma8cd1[27]   = the3799;  
+assign zma8cd1[26]   = xweb8de;      
+assign zma8cd1[25]   = osdb802;           
+assign zma8cd1[24]   = vka7ae3;  
+assign zma8cd1[23]   = jr3d71b;          
+assign zma8cd1[22]   = je3f824;           
+assign zma8cd1[21]   = zxfc122;           
+assign zma8cd1[20]   = qi3b3a5;      
+assign zma8cd1[19]   = rgcfd9e;                                                  
+assign zma8cd1[18]   = vk48b0;       
+assign zma8cd1[17]   = fpb067e;         
+assign zma8cd1[16]   = qi24583;        
+assign zma8cd1[15:14] = 2'b00;
+assign zma8cd1[13:0] = os46086;    
+
+assign kf262c1[0] = fpb067e;
+assign kf262c1[1] = osdb802;
+assign kf262c1[2] = ng1bcce;
+assign kf262c1[3] = hd2d063;
+assign kf262c1[4] = gdbe9eb;
+assign kf262c1[5] = ay5c6f3;
+assign kf262c1[6] = je3f824;
+assign kf262c1[7] = zxfc122;
+assign kf262c1[8] = qi24583;
+
+always@* begin wj6fb0f<=vv746d9[0];cz60ece<=vv746d9[1];ir7674<=vv746d9[2];qi3b3a5<=vv746d9[3];gbd9d29<=vv746d9[4];uk3bdce<={ne52e43>>1,vv746d9[5]};godee70<=vv746d9[6];ep2983f<=vv746d9[7];ay4c1fc<=vv746d9[8];gb60fe0<=vv746d9[9];oh7f04<=vv746d9[10];je3f824<=vv746d9[11];zxfc122<=vv746d9[12];uie0916<=vv746d9[13];vk48b0<=vv746d9[14];qi24583<=vv746d9[15];jr160cf<={ec21fab>>1,vv746d9[16]};fpb067e<=vv746d9[17];ng833f6<=vv746d9[18];hd19fb3<=vv746d9[19];rgcfd9e<=vv746d9[20];nr7ecf2<=vv746d9[21];qib3cb7<={bl7eac0>>1,vv746d9[22]};zz9e5b8<=vv746d9[23];gbf2dc6<=vv746d9[24];vk96e34<=vv746d9[25];zmb71a3<=vv746d9[26];uvc68db<={dz6b175>>1,vv746d9[27]};ec346dc<=vv746d9[28];eca36e0<=vv746d9[29];xy1b700<=vv746d9[30];osdb802<=vv746d9[31];qge008d<={ecb9836>>1,vv746d9[32]};sw469<=vv746d9[33];qv2348<=vv746d9[34];do11a45<=vv746d9[35];gq8d22a<=vv746d9[36];by69150<=vv746d9[37];ho48a83<=vv746d9[38];pf4541b<=vv746d9[39];ri2a0de<=vv746d9[40];dz506f2<=vv746d9[41];pu1bcbb<={cbab7e8>>1,vv746d9[42]};gode5db<=vv746d9[43];kdf2ed8<=vv746d9[44];kfbb620<={wje895c>>1,vv746d9[45]};icdb105<=vv746d9[46];bld8828<=vv746d9[47];uic4146<={sw2b92b>>1,vv746d9[48]};fc20a30<=vv746d9[49];ec5182<=vv746d9[50];os46086<={ie2b213>>1,vv746d9[51]};ym8218a<={pfc84c1>>1,vv746d9[52]};ou10c51<=vv746d9[53];ri86288<=vv746d9[54];ks31443<=vv746d9[55];cb8a218<=vv746d9[56];mg8862d<={by73c4b>>1,vv746d9[57]};ww43168<=vv746d9[58];an18b41<=vv746d9[59];nec5a0c<=vv746d9[60];hd2d063<=vv746d9[61];cm6831f<=vv746d9[62];fpc7cd<={twb257c>>1,vv746d9[63]};qi1f373<={yz95f19>>1,vv746d9[64]};nrf9b98<=vv746d9[65];jpcdcc7<=vv746d9[66];fn6e63f<=vv746d9[67];jc731fe<=vv746d9[68];wy98ff3<=vv746d9[69];jpc7f98<=vv746d9[70];vk3fcc6<=vv746d9[71];zxf3193<={ksb6a15>>1,vv746d9[72]};uk98c9f<=vv746d9[73];shc64f8<=vv746d9[74];vx327c5<=vv746d9[75];ep9f17b<={zma8cd1>>1,vv746d9[76]};uvf8bdc<=vv746d9[77];lqc5ee5<=vv746d9[78];pu2f72b<=vv746d9[79];bld7913<=vv746d9[80];endcad6<=vv746d9[81];sue56b4<=vv746d9[82];jp5ad08<={dz61b0b>>1,vv746d9[83]};mrd6847<=vv746d9[84];gdb423d<=vv746d9[85];wla11ec<=vv746d9[86];qv8f65<=vv746d9[87];ho47b2d<={al5eafa>>1,vv746d9[88]};hd3d96a<=vv746d9[89];xl2296f<=vv746d9[90];wj65abe<=vv746d9[91];nt2d5f4<=vv746d9[92];al6afa7<=vv746d9[93];zk57d3d<=vv746d9[94];gdbe9eb<=vv746d9[95];zkf4f5c<=vv746d9[96];vka7ae3<=vv746d9[97];jr3d71b<=vv746d9[98];xweb8de<=vv746d9[99];ay5c6f3<=vv746d9[100];the3799<=vv746d9[101];ng1bcce<=vv746d9[102];qgde673<=vv746d9[103];nrf3398<=vv746d9[104];do99cc7<=vv746d9[105];kqce63a<=vv746d9[106];mg98e8b<={kf262c1>>1,vv746d9[107]};hbc7458<={sw3160c>>1,vv746d9[108]};je3a2c7<=vv746d9[109];ayd163b<=vv746d9[110];ph8b1d9<=vv746d9[111];end
+always@* begin wy2e8db[2047]<=xy304af;wy2e8db[2046]<=aa8257a;wy2e8db[2045]<=ui675b5;wy2e8db[2044]<=gd12bd1;wy2e8db[2043]<=vk3ada8;wy2e8db[2041]<=kf95e8d;wy2e8db[2038]<=ksb6a15[0];wy2e8db[2035]<=ne52e43[0];wy2e8db[2029]<=by73c4b[0];wy2e8db[2028]<=dbb50a8;wy2e8db[2022]<=yxe7c08;wy2e8db[2011]<=jr9e25a;wy2e8db[2009]<=xya8546;wy2e8db[1996]<=ec3e045;wy2e8db[1986]<=icce626;wy2e8db[1974]<=hof12d6;wy2e8db[1971]<=by42a33;wy2e8db[1945]<=yk5cf81;wy2e8db[1943]<=me5c959;wy2e8db[1924]<=vi73131;wy2e8db[1922]<=thddac5;wy2e8db[1901]<=do896b2;wy2e8db[1895]<=zma8cd1[0];wy2e8db[1857]<=qvd85e;wy2e8db[1842]<=ie151db;wy2e8db[1839]<=fae4ac8;wy2e8db[1800]<=ou9898b;wy2e8db[1797]<=kded62e;wy2e8db[1791]<=pfe333a;wy2e8db[1784]<=qgc4673;wy2e8db[1778]<=qt44ae4;wy2e8db[1776]<=bl7eac0[0];wy2e8db[1759]<=yz95f19[0];wy2e8db[1755]<=en4b592;wy2e8db[1742]<=yz33451;wy2e8db[1677]<=nr45c1a;wy2e8db[1667]<=ho6c2f5;wy2e8db[1652]<=cb363c0;wy2e8db[1637]<=zma8ed9;wy2e8db[1631]<=ie2b213[0];wy2e8db[1622]<=ux3c87e;wy2e8db[1552]<=kf262c1[0];wy2e8db[1546]<=dz6b175[0];wy2e8db[1535]<=jr199d6;wy2e8db[1531]<=ec9839e;wy2e8db[1520]<=an23398;wy2e8db[1509]<=do25725;wy2e8db[1504]<=uk2b76b;wy2e8db[1471]<=vxaf8cc;wy2e8db[1468]<=rv846fb;wy2e8db[1463]<=rt5ac95;wy2e8db[1437]<=oh9a28d;wy2e8db[1391]<=cbab030;wy2e8db[1312]<=bn6c64;wy2e8db[1307]<=ec2e0d7;wy2e8db[1286]<=fn617ab;wy2e8db[1256]<=yx51b0d;wy2e8db[1226]<=ne476ca;wy2e8db[1215]<=pfc84c1[0];wy2e8db[1197]<=lqe43f5;wy2e8db[1153]<=gdb1935;wy2e8db[1135]<=pu835c4;wy2e8db[1057]<=sw3160c[0];wy2e8db[1050]<=al5eafa[0];wy2e8db[1044]<=tu58bae;wy2e8db[1037]<=zmad7ab;wy2e8db[1023]<=mrf282b;wy2e8db[1022]<=ipcceb6;wy2e8db[1014]<=wwc1cf1;wy2e8db[993]<=tj19cc4;wy2e8db[971]<=sw2b92b[0];wy2e8db[961]<=ignore_pkt;wy2e8db[928]<=dz61b0b[0];wy2e8db[895]<=lq7c667;wy2e8db[892]<=lsb88ce;wy2e8db[889]<=wje895c[0];wy2e8db[888]<=wyfd58;wy2e8db[879]<=twb257c[0];wy2e8db[838]<=pua8b83;wy2e8db[826]<=uid146c;wy2e8db[811]<=zxc790f;wy2e8db[765]<=tj13073;wy2e8db[734]<=lq58184;wy2e8db[695]<=kqf5606;wy2e8db[656]<=of60d8c;wy2e8db[576]<=kf36326;wy2e8db[567]<=cz706b8;wy2e8db[525]<=jebd5f;wy2e8db[518]<=tw35af5;wy2e8db[464]<=sw8d86c;wy2e8db[446]<=xjd7119;wy2e8db[444]<=jcdfa25;wy2e8db[419]<=wwfaa2e;wy2e8db[405]<=ec3b653;wy2e8db[382]<=vi4260e;wy2e8db[347]<=ec21fab[0];wy2e8db[328]<=ecb9836[0];wy2e8db[269]<=icc183b;wy2e8db[259]<=dz64d6b;wy2e8db[223]<=uk1ae23;wy2e8db[222]<=mr5bf44;wy2e8db[209]<=ld5f545;wy2e8db[164]<=ecf839;wy2e8db[134]<=zk58307;wy2e8db[111]<=cbab7e8[0];wy2e8db[104]<=ph2713b;wy2e8db[82]<=ym2eb93;wy2e8db[67]<=ph8b060;wy2e8db[55]<=wj5eadf;wy2e8db[52]<=qgf57d5;wy2e8db[41]<=jcc5d72;wy2e8db[27]<=th6bd5b;end         assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6<ksa36ce; dobd2d6=dobd2d6+1) begin dbc230[dobd2d6] = db84308[hq30de9]; hq86f4b = ^(hq30de9 & kf8c37[0]); hq30de9 = {hq30de9, hq86f4b}; end end 
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+`timescale 1 ns / 100 ps
+module tja0af6 (
+    
+    rxmac_clk,
+    reset_n,
+    rxmac_clk_en,
+
+    
+    mrf282b,                  
+    xy304af,               
+    tj9415c,                   
+    aa8257a,
+    gd12bd1,
+    kf95e8d,
+
+    
+    su43606,                
+    tw1b031,                
+    ldd818a,                
+    byc0c57,                
+    ph62bb,                
+    uk315df,                
+    ep8aef8,                
+    lq577c4,                
+    uxbbe22,                  
+    hodf114,                 
+    shf88a2,                 
+    uic4515,                       
+    ep90e3c,               
+    thddac5,              
+    kded62e,              
+    dz6b175,              
+    tu58bae,                
+    jcc5d72,                 
+    ym2eb93,               
+
+    
+    rx_fifo_full,               
+    ignore_pkt,                 
+
+    
+    ba93361,                    
+    sw10140,                   
+    cb80a01,                
+    ri99b0a,              
+    vvcd852,           
+
+    
+    vk308df,                 
+    uka5df,              
+
+    
+    rx_fifo_error,              
+    rx_stat_vector,             
+    rx_dbout,                   
+    rx_write,                   
+    rx_stat_en,                 
+    rx_eof,                     
+    rx_error                    
+);
+parameter mef0229     = 8;
+parameter psdf7a3     = 14;
+parameter dmfbd1a     = 16;
+parameter ayde8d2     = 16;
+parameter qi2ebc5     = 20;
+parameter yx75e29     = 32;
+parameter ec87d2e     = 32;
+parameter phaf14d     = 8;
+parameter kq78a6e     = 4;
+parameter dmdad55     = 8;
+parameter neca645     = 48;
+parameter ntb555d     = 2;
+parameter ic5322b     = 6;
+parameter vk99158     = 8;
+parameter gq3e970     = 9;
+input                                 rxmac_clk;
+input                                 reset_n;
+input                                 rxmac_clk_en;
+input                                 mrf282b;
+input                                 xy304af;
+input                                 aa8257a;
+input                                 gd12bd1;
+input                                 kf95e8d;
+input [mef0229-1:0]         tj9415c;
+input [dmdad55-1:0]    su43606;
+input [dmdad55-1:0]    tw1b031;
+input [dmdad55-1:0]    ldd818a;
+input [dmdad55-1:0]    byc0c57;
+input [dmdad55-1:0]    ph62bb;
+input [dmdad55-1:0]    uk315df;
+input [dmdad55-1:0]    ep8aef8;
+input [dmdad55-1:0]    lq577c4;
+input [neca645-1:0]         uxbbe22;
+input [dmfbd1a-1:0]            ep90e3c;
+input [psdf7a3-1:0]           dz6b175;
+input                                 hodf114;
+input                                 shf88a2;
+input                                 uic4515;
+input                                 thddac5;
+input                                 kded62e;
+input                                 tu58bae;
+input                                 jcc5d72;
+input                                 ym2eb93;
+input                                 ignore_pkt;
+input                                 rx_fifo_full;
+output                                ba93361;
+output [gq3e970-1:0]      ri99b0a;
+output                                vvcd852;
+output                                cb80a01;
+output [ayde8d2-1:0]           sw10140;
+output [dmfbd1a-1:0]           vk308df;
+output                                uka5df;
+output                                rx_fifo_error;
+output [yx75e29-1:0]        rx_stat_vector;
+output [mef0229-1:0]        rx_dbout;
+output                                rx_write;
+output                                rx_stat_en;
+output                                rx_eof;
+output                                rx_error;
+parameter pdevice_family = "XP2";
+wire [mef0229-1:0]          gq88cbf;
+wire [mef0229-1:0]          nt32fc9;
+wire                                  ym97e4e;
+wire                                  zzbf271;
+wire                                  blf938f;
+wire                                  mrc9c7e;
+wire                                  cz4e3f5;
+wire [psdf7a3-1:0]            mt8fd6f;
+wire                                  zx7eb7c;
+wire                                  uif5be6;
+wire                                  hqadf31;
+wire                                  al6f98a;
+wire                                  zk7cc55;
+wire [dmfbd1a-1:0]             ym3155e;
+wire [ayde8d2-1:0]             jp55784;
+wire [psdf7a3-1:0]            mr5e13d;
+wire                                  eaf09ec;
+wire                                  lf84f61;
+wire                                  rv27b0f;
+wire                                  db3d87f;
+wire                                  hbec3ff;
+wire                                  fn61fff;
+wire                                  ecfffe;
+wire                                  mr7fff0;
+wire                                  uifff84;
+wire                                  goffc20;
+wire                                  zkfe100;
+wire                                  ykf0803;
+wire                                  ph84019;
+wire                                  ri200ce;
+wire [ec87d2e-1:0]               db3398;
+wire                                  fp19cc7;
+wire                                  ayce63e;
+wire [qi2ebc5-1:0]          wy98f8b;
+wire                                  jpc7c58;
+wire                                  uk3e2c6;
+wire                                  ba93361;
+wire                                  vvcd852;
+wire [gq3e970-1:0]        ri99b0a;
+wire [ntb555d-1:0]      wl8aea8;
+wire [ic5322b-1:0]      dbbaa22;
+wire [phaf14d-1:0]         vka88b3;
+wire [phaf14d-1:0]         ph22cd4;
+wire                                  nt166a7;
+wire                                  ieb353e;
+wire [qi2ebc5-1:0]          osd4f8d;
+reg ria7c68;
+reg wj6fb0f;
+reg cz60ece;
+reg [mef0229 - 1 : 0] xjec3e9;
+reg ir7674;
+reg qi3b3a5;
+reg gbd9d29;
+reg [dmdad55 - 1 : 0] wj70349;
+reg [dmdad55 - 1 : 0] sjd267;
+reg [dmdad55 - 1 : 0] ui499e3;
+reg [dmdad55 - 1 : 0] ay678c9;
+reg [dmdad55 - 1 : 0] zxe324c;
+reg [dmdad55 - 1 : 0] czc9337;
+reg [dmdad55 - 1 : 0] me4cde1;
+reg [dmdad55 - 1 : 0] fp3784b;
+reg [neca645 - 1 : 0] vie12f0;
+reg jr9783;
+reg al4bc1e;
+reg gb5e0f4;
+reg [dmfbd1a - 1 : 0] cb8fc48;
+reg vk96e34;
+reg zmb71a3;
+reg [psdf7a3 - 1 : 0] uvc68db;
+reg ec346dc;
+reg eca36e0;
+reg xy1b700;
+reg hoc0b68;
+reg gbf2dc6;
+reg [mef0229 - 1 : 0] dob70ad;
+reg [mef0229 - 1 : 0] nrc2b5a;
+reg aa15ad6;
+reg jead6b0;
+reg vv6b583;
+reg jp5ac1e;
+reg mrd60f7;
+reg [psdf7a3 - 1 : 0] xy83de6;
+reg do1ef32;
+reg qtf7993;
+reg wybcc9c;
+reg dze64e1;
+reg rv3270e;
+reg [dmfbd1a - 1 : 0] hq9c3bb;
+reg [ayde8d2 - 1 : 0] doeeda;
+reg [psdf7a3 - 1 : 0] uxbb691;
+reg kqdb48d;
+reg psda468;
+reg fnd2342;
+reg zz91a16;
+reg aa8d0b6;
+reg ea685b0;
+reg fa42d81;
+reg rv16c0a;
+reg swb6057;
+reg tjb02b9;
+reg xl815ce;
+reg coae76;
+reg vi573b0;
+reg ukb9d82;
+reg [ec87d2e - 1 : 0] ho76088;
+reg jrb0443;
+reg sw8221e;
+reg [qi2ebc5 - 1 : 0] ie8878b;
+reg qg43c58;
+reg zm1e2c0;
+reg [ntb555d - 1 : 0] ph8b012;
+reg [ic5322b - 1 : 0] jcc04bb;
+reg [phaf14d - 1 : 0] an12ed5;
+reg [phaf14d - 1 : 0] cbbb568;
+reg xwdab45;
+reg tud5a2b;
+reg [qi2ebc5 - 1 : 0] me68ad3;
+reg [2047:0] wy2e8db;
+wire [70:0] vv746d9;
+
+
+
+
+
+
+
+
+localparam ksa36ce = 71,tw1b670 = 32'hfdffd84b;
+localparam [31:0] icdb382 = tw1b670;
+localparam mece084 = tw1b670 & 4'hf;
+localparam [11:0] ou8210c = 'h7ff;
+wire [(1 << mece084) -1:0] db84308;
+reg [ksa36ce-1:0] dbc230;
+reg [mece084-1:0] kf8c37 [0:1];
+reg [mece084-1:0] hq30de9;
+reg hq86f4b;
+integer hd37a5a;
+integer dobd2d6;
+
+
+
+
+
+
+
+
+
+
+
+
+assign nt32fc9 = dob70ad;
+
+
+assign cb80a01 = rv3270e;
+assign sw10140 = doeeda;
+assign vk308df = hq9c3bb;
+
+
+
+
+assign wl8aea8 = ie8878b[19:18];
+
+
+
+
+
+
+
+kdd67f2       #(        .mef0229(mef0229)        )    jcdaa03 (        .rxmac_clk(rxmac_clk),        .rxmac_clk_en(rxmac_clk_en),        .reset_n(ria7c68),        .mrf282b(wj6fb0f),        .tj9415c(xjec3e9),        .lfa0ae7(swb6057),        .aa573e(xl815ce),        .aa2b9f0(gq88cbf),        .yk5cf81(ym97e4e),        .yxe7c08(zzbf271),        .ec3e045(blf938f)        );
+
+vvc21a9       #(        .mef0229(mef0229),        .psdf7a3(psdf7a3),        .dmfbd1a(dmfbd1a),        .ayde8d2(ayde8d2)        )    nta058c (        .rxmac_clk(rxmac_clk),        .reset_n(ria7c68),        .rxmac_clk_en(rxmac_clk_en),        .ne52e43(dob70ad),        .yk78487(coae76),        .aa573e(tjb02b9),        .fnc86c0(vi573b0),        .wl121c7(ukb9d82),        .ep90e3c(cb8fc48),        .medb299(fnd2342),        .fca2a3b(rv16c0a),        .zxc790f(mrc9c7e),        .ux3c87e(qv17e1e),        .lqe43f5(cz4e3f5),        .ec21fab(mt8fd6f),        .wyfd58(eaf09ec),        .bl7eac0(mr5e13d),        .kqf5606(zx7eb7c),        .cbab030(hqadf31),        .lq58184(al6f98a),        .byc0c23(jp55784),        .ph611b(zk7cc55),        .vk308df(ym3155e),        .rv846fb(lf84f61),        .ir237de(uif5be6)        );
+
+fn6ee52       #(        .mef0229(mef0229),        .neca645(neca645),        .ic5322b(ic5322b),        .vk99158(vk99158)        )    ic49b25 (        .rxmac_clk(rxmac_clk),        .reset_n(ria7c68),        .rxmac_clk_en(rxmac_clk_en),        .ne52e43(dob70ad),        .yxe7c08(jead6b0),        .aa573e(tjb02b9),        .fnc86c0(vi573b0),        .su43606(wj70349),        .tw1b031(sjd267),        .ldd818a(ui499e3),        .byc0c57(ay678c9),        .ph62bb(zxe324c),        .uk315df(czc9337),        .ep8aef8(me4cde1),        .lq577c4(fp3784b),        .uxbbe22(vie12f0),        .hodf114(jr9783),        .shf88a2(al4bc1e),        .uic4515(gb5e0f4),        .hd228a8(jcc04bb),        .zm14547(ba8368a),        .ie151db(db3d87f),        .zma8ed9(hbec3ff),        .ne476ca(fn61fff),        .ec3b653(ecfffe),        .medb299(rv27b0f),        .fca2a3b(mr7fff0)        );
+
+
+ieacc06       #(        .mef0229(mef0229),        .psdf7a3(psdf7a3),        .qi2ebc5(qi2ebc5),        .yx75e29(yx75e29),        .ec87d2e(ec87d2e),        .gq3e970(gq3e970)        )    qge0b44 (        .rxmac_clk(rxmac_clk),        .reset_n(ria7c68),        .rxmac_clk_en(rxmac_clk_en),        .mrf282b(wj6fb0f),        .xy304af(cz60ece),        .aa8257a(ir7674),        .gd12bd1(qi3b3a5),        .kf95e8d(gbd9d29),        .ne52e43(dob70ad),        .yxe7c08(jead6b0),        .ec3e045(vv6b583),        .yk5cf81(aa15ad6),                .ie151db(zz91a16),        .zma8ed9(aa8d0b6),        .ne476ca(ea685b0),        .ec3b653(fa42d81),                .zxc790f(jp5ac1e),        .ux3c87e(qv17e1e),        .lqe43f5(mrd60f7),        .ec21fab(xy83de6),        .kqf5606(do1ef32),        .uk2b76b(qtf7993),        .cbab030(wybcc9c),        .lq58184(dze64e1),        .rv846fb(psda468),        .wyfd58(kqdb48d),        .bl7eac0(uxbb691),                .ignore_pkt(gbf2dc6),                .thddac5(vk96e34),        .kded62e(zmb71a3),        .dz6b175(uvc68db),        .tu58bae(ec346dc),        .jcc5d72(eca36e0),        .ym2eb93(xy1b700),                .ecf839(mr60e96),                .aa573e(goffc20),        .fnc86c0(ph84019),
+                .ba93361(ba93361),        .ri99b0a(ri99b0a),        .vvcd852(vvcd852),                .uka5df(uka5df),                .lfa0ae7(uifff84),        .nr614bb(zkfe100),                .yk78487(ykf0803),        .wl121c7(ri200ce),                .zm9985b(wy98f8b),        .lse661(jpc7c58),        .tu7330b(uk3e2c6),                .mecb116(db3398),        .zm14547(fp19cc7),        .ir39085(oh1784d),        .hd22c50(ayce63e)        );
+
+ldd83e0    rg4da1f (        .ayc1f07(dbbaa22),        .ecf839(mr60e96),        .lq7c1c8(dob70ad),        .mee0e42(jrb0443),        .kf7210(ba8368a),        .ir39085(oh1784d),        .rtc842c(sw8221e),        .lq42166(ho76088),        .ou10b33(rxmac_clk),        .ux2ccc5(ria7c68),        .rxmac_clk_en(rxmac_clk_en)        );
+
+jcdfe0e       #(        .mef0229(mef0229),        .qi2ebc5(qi2ebc5),        .yx75e29(yx75e29),        .phaf14d(phaf14d),        .kq78a6e(kq78a6e)        )     dz6e6c7 (        .rxmac_clk(rxmac_clk),        .reset_n(ria7c68),        .rxmac_clk_en(rxmac_clk_en),        .lse661(qg43c58),        .tu7330b(zm1e2c0),        .zm9985b(ph8b012),        .rx_fifo_full(hoc0b68),        .dz616d4(me68ad3),        .twb6a7(vka88b3),        .gb5b53b(ph22cd4),        .jcda9dc(nt166a7),        .kqd4ee3(ieb353e),        .rx_fifo_error(rx_fifo_error),        .rx_stat_vector(rx_stat_vector),        .rx_dbout(rx_dbout),        .rx_write(rx_write),        .rx_stat_en(rx_stat_en),        .rx_eof(rx_eof),        .rx_error(rx_error)        );
+
+pmi_ram_dp  #(.pmi_wr_addr_depth(256),    .pmi_wr_addr_width(8),    .pmi_wr_data_width(20),    .pmi_rd_addr_depth(256),    .pmi_rd_addr_width(8),    .pmi_rd_data_width(20),    .pmi_regmode("noreg"),    .pmi_gsr("disable"),    .pmi_resetmode("sync"),    .pmi_init_file("none"),    .pmi_init_file_format("binary"),    .pmi_family(pdevice_family),    .module_type("pmi_ram_dp")    )
+tj32722   (.Data(wy98f8b),                 .WrAddress(vka88b3),                 .RdAddress(ph22cd4),                 .WrClock(rxmac_clk),                 .RdClock(rxmac_clk),                 .WrClockEn(1'b1),                 .RdClockEn(nt166a7 & rxmac_clk_en),                 .WE(ieb353e),                 .Reset(1'b0),                 .Q(osd4f8d)                 );
+always@* begin ria7c68<=vv746d9[0];wj6fb0f<=vv746d9[1];cz60ece<=vv746d9[2];xjec3e9<={tj9415c>>1,vv746d9[3]};ir7674<=vv746d9[4];qi3b3a5<=vv746d9[5];gbd9d29<=vv746d9[6];wj70349<={su43606>>1,vv746d9[7]};sjd267<={tw1b031>>1,vv746d9[8]};ui499e3<={ldd818a>>1,vv746d9[9]};ay678c9<={byc0c57>>1,vv746d9[10]};zxe324c<={ph62bb>>1,vv746d9[11]};czc9337<={uk315df>>1,vv746d9[12]};me4cde1<={ep8aef8>>1,vv746d9[13]};fp3784b<={lq577c4>>1,vv746d9[14]};vie12f0<={uxbbe22>>1,vv746d9[15]};jr9783<=vv746d9[16];al4bc1e<=vv746d9[17];gb5e0f4<=vv746d9[18];cb8fc48<={ep90e3c>>1,vv746d9[19]};vk96e34<=vv746d9[20];zmb71a3<=vv746d9[21];uvc68db<={dz6b175>>1,vv746d9[22]};ec346dc<=vv746d9[23];eca36e0<=vv746d9[24];xy1b700<=vv746d9[25];hoc0b68<=vv746d9[26];gbf2dc6<=vv746d9[27];dob70ad<={gq88cbf>>1,vv746d9[28]};nrc2b5a<={nt32fc9>>1,vv746d9[29]};aa15ad6<=vv746d9[30];jead6b0<=vv746d9[31];vv6b583<=vv746d9[32];jp5ac1e<=vv746d9[33];mrd60f7<=vv746d9[34];xy83de6<={mt8fd6f>>1,vv746d9[35]};do1ef32<=vv746d9[36];qtf7993<=vv746d9[37];wybcc9c<=vv746d9[38];dze64e1<=vv746d9[39];rv3270e<=vv746d9[40];hq9c3bb<={ym3155e>>1,vv746d9[41]};doeeda<={jp55784>>1,vv746d9[42]};uxbb691<={mr5e13d>>1,vv746d9[43]};kqdb48d<=vv746d9[44];psda468<=vv746d9[45];fnd2342<=vv746d9[46];zz91a16<=vv746d9[47];aa8d0b6<=vv746d9[48];ea685b0<=vv746d9[49];fa42d81<=vv746d9[50];rv16c0a<=vv746d9[51];swb6057<=vv746d9[52];tjb02b9<=vv746d9[53];xl815ce<=vv746d9[54];coae76<=vv746d9[55];vi573b0<=vv746d9[56];ukb9d82<=vv746d9[57];ho76088<={db3398>>1,vv746d9[58]};jrb0443<=vv746d9[59];sw8221e<=vv746d9[60];ie8878b<={wy98f8b>>1,vv746d9[61]};qg43c58<=vv746d9[62];zm1e2c0<=vv746d9[63];ph8b012<={wl8aea8>>1,vv746d9[64]};jcc04bb<={dbbaa22>>1,vv746d9[65]};an12ed5<={vka88b3>>1,vv746d9[66]};cbbb568<={ph22cd4>>1,vv746d9[67]};xwdab45<=vv746d9[68];tud5a2b<=vv746d9[69];me68ad3<={osd4f8d>>1,vv746d9[70]};end
+always@* begin wy2e8db[2047]<=mrf282b;wy2e8db[2046]<=xy304af;wy2e8db[2044]<=tj9415c[0];wy2e8db[2040]<=aa8257a;wy2e8db[2033]<=gd12bd1;wy2e8db[2019]<=kf95e8d;wy2e8db[1999]<=mt8fd6f[0];wy2e8db[1991]<=su43606[0];wy2e8db[1981]<=mr7fff0;wy2e8db[1958]<=ph84019;wy2e8db[1950]<=zx7eb7c;wy2e8db[1947]<=jp55784[0];wy2e8db[1934]<=tw1b031[0];wy2e8db[1914]<=uifff84;wy2e8db[1892]<=thddac5;wy2e8db[1868]<=ri200ce;wy2e8db[1852]<=uif5be6;wy2e8db[1851]<=uxbbe22[0];wy2e8db[1847]<=mr5e13d[0];wy2e8db[1820]<=ldd818a[0];wy2e8db[1783]<=hbec3ff;wy2e8db[1780]<=goffc20;wy2e8db[1737]<=kded62e;wy2e8db[1689]<=db3398[0];wy2e8db[1657]<=hqadf31;wy2e8db[1654]<=hodf114;wy2e8db[1647]<=eaf09ec;wy2e8db[1610]<=jcc5d72;wy2e8db[1608]<=wl8aea8[0];wy2e8db[1593]<=byc0c57[0];wy2e8db[1523]<=mrc9c7e;wy2e8db[1519]<=fn61fff;wy2e8db[1513]<=zkfe100;wy2e8db[1426]<=dz6b175[0];wy2e8db[1404]<=zzbf271;wy2e8db[1330]<=fp19cc7;wy2e8db[1267]<=al6f98a;wy2e8db[1260]<=shf88a2;wy2e8db[1246]<=lf84f61;wy2e8db[1225]<=wy98f8b[0];wy2e8db[1199]<=gq88cbf[0];wy2e8db[1173]<=ym2eb93;wy2e8db[1169]<=dbbaa22[0];wy2e8db[1163]<=nt166a7;wy2e8db[1139]<=ph62bb[0];wy2e8db[1023]<=reset_n;wy2e8db[999]<=cz4e3f5;wy2e8db[990]<=ecfffe;wy2e8db[979]<=ykf0803;wy2e8db[973]<=ym3155e[0];wy2e8db[946]<=ep90e3c[0];wy2e8db[925]<=lq577c4[0];wy2e8db[891]<=db3d87f;wy2e8db[805]<=tu58bae;wy2e8db[804]<=uk3e2c6;wy2e8db[761]<=blf938f;wy2e8db[702]<=ym97e4e;wy2e8db[612]<=ayce63e;wy2e8db[599]<=ignore_pkt;wy2e8db[581]<=ph22cd4[0];wy2e8db[556]<=osd4f8d[0];wy2e8db[486]<=zk7cc55;wy2e8db[473]<=uic4515;wy2e8db[462]<=ep8aef8[0];wy2e8db[445]<=rv27b0f;wy2e8db[402]<=jpc7c58;wy2e8db[351]<=nt32fc9[0];wy2e8db[299]<=rx_fifo_full;wy2e8db[290]<=vka88b3[0];wy2e8db[278]<=ieb353e;wy2e8db[231]<=uk315df[0];end         assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6<ksa36ce; dobd2d6=dobd2d6+1) begin dbc230[dobd2d6] = db84308[hq30de9]; hq86f4b = ^(hq30de9 & kf8c37[0]); hq30de9 = {hq30de9, hq86f4b}; end end 
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+`timescale 1 ns / 100 ps
+module fnd7239 ( wyb91ce,
+                       zxc8e70,
+                       txmac_clk_en,
+
+                       oh39c3b,   
+                       osce1dd,      
+
+                       sh70ee9   
+                       );
+parameter qi8774d = 4;
+input                   wyb91ce;
+input                   zxc8e70;
+input                   txmac_clk_en;
+input                   oh39c3b;
+input [qi8774d-1:0] osce1dd;
+output                  sh70ee9;
+reg                     qi3e4da;
+reg                     gbf26d1;
+reg [15:0]              zm9368d;
+reg [31:0]              db9b46a;
+wire        lqda356 = (~qi3e4da & oh39c3b);
+wire        sh70ee9 = gbf26d1 & (zm9368d == 0);
+wire [31:0] gd90143;
+reg kf80a1d;
+reg [qi8774d - 1 : 0] zz28768;
+reg qg43b47;
+reg an1da38;
+reg [15 : 0] ofed1c4;
+reg [31 : 0] go68e25;
+reg rg47128;
+reg [31 : 0] nt38943;
+reg [2047:0] wy2e8db;
+wire [7:0] vv746d9;
+
+localparam ksa36ce = 8,tw1b670 = 32'hfdffc70b;
+localparam [31:0] icdb382 = tw1b670;
+localparam mece084 = tw1b670 & 4'hf;
+localparam [11:0] ou8210c = 'h7ff;
+wire [(1 << mece084) -1:0] db84308;
+reg [ksa36ce-1:0] dbc230;
+reg [mece084-1:0] kf8c37 [0:1];
+reg [mece084-1:0] hq30de9;
+reg hq86f4b;
+integer hd37a5a;
+integer dobd2d6;
+
+   always @ (posedge wyb91ce or negedge zxc8e70) begin      if(!zxc8e70)        zm9368d <= 0;      else if (txmac_clk_en) begin         if (rg47128) begin            casex(zz28768)              4'h1: begin                 zm9368d[15:0] <= {9'b00000000, go68e25[0], {6{1'b0}}};              end              4'h2: begin                 zm9368d[15:0] <= {8'b00000000, go68e25[1:0], {6{1'b0}}};              end              4'h3: begin                 zm9368d[15:0] <= {7'b0000000, go68e25[2:0], {6{1'b0}}};              end              4'h4: begin                 zm9368d[15:0] <= {6'b000000, go68e25[3:0], {6{1'b0}}};              end              4'h5: begin                 zm9368d[15:0] <= {5'b00000, go68e25[4:0], {6{1'b0}}};              end              4'h6: begin                 zm9368d[15:0] <= {4'b0000, go68e25[5:0], {6{1'b0}}};              end              4'h7: begin                 zm9368d[15:0] <= {3'b000, go68e25[6:0], {6{1'b0}}};              end              4'h8: begin                 zm9368d[15:0] <= {2'b00, go68e25[7:0], {6{1'b0}}};              end              4'h9: begin                 zm9368d[15:0] <= {1'b0, go68e25[8:0], {6{1'b0}}};              end              default: begin                 zm9368d[15:0] <= {go68e25[9:0], {6{1'b0}}};              end            endcase          end          else if (an1da38) begin            zm9368d <= ofed1c4 - {{15{1'b0}}, 1'b1};         end      end   end
+   always @ (posedge wyb91ce or negedge zxc8e70) begin      if(!zxc8e70) begin         qi3e4da <= 1'b0;         gbf26d1 <= 1'b0;      end      else if (txmac_clk_en) begin         qi3e4da <= kf80a1d;         gbf26d1 <= qg43b47;      end   end      assign gd90143[31:1] = go68e25[30:0];   assign gd90143[0] = go68e25[1]^go68e25[5]^go68e25[6]^go68e25[31];
+   always @ (posedge wyb91ce or negedge zxc8e70) begin      if(!zxc8e70) begin         db9b46a <= {32{1'b1}};      end       else if (txmac_clk_en) begin          db9b46a <= nt38943;      end    end 
+
+always@* begin kf80a1d<=vv746d9[0];zz28768<={osce1dd>>1,vv746d9[1]};qg43b47<=vv746d9[2];an1da38<=vv746d9[3];ofed1c4<={zm9368d>>1,vv746d9[4]};go68e25<={db9b46a>>1,vv746d9[5]};rg47128<=vv746d9[6];nt38943<={gd90143>>1,vv746d9[7]};end
+always@* begin wy2e8db[2047]<=osce1dd[0];wy2e8db[2046]<=qi3e4da;wy2e8db[2044]<=gbf26d1;wy2e8db[2040]<=zm9368d[0];wy2e8db[2032]<=db9b46a[0];wy2e8db[2016]<=lqda356;wy2e8db[1985]<=gd90143[0];wy2e8db[1023]<=oh39c3b;end         assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6<ksa36ce; dobd2d6=dobd2d6+1) begin dbc230[dobd2d6] = db84308[hq30de9]; hq86f4b = ^(hq30de9 & kf8c37[0]); hq30de9 = {hq30de9, hq86f4b}; end end 
+endmodule
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+`timescale 1 ns / 100 ps
+module th71cb9 (
+   ls2f153, 
+   lq7c1c8,
+   mee0e42,
+   rtc842c,
+   lq42166,
+   ou10b33,
+   txmac_clk_en,
+   ux2ccc5
+   );
+output [31:0] ls2f153;
+input  [7:0]  lq7c1c8;
+input  [31:0]  lq42166;
+input         mee0e42;
+input         rtc842c;
+input         ou10b33;
+input         txmac_clk_en;
+input         ux2ccc5;
+reg    [31:0] yk4962f;
+wire   [31:0] rgc5e2a;
+wire   [31:0] ls2f153;
+reg [7 : 0] ea78a9a;
+reg nec54d1;
+reg an9a290;
+reg [31 : 0] med1484;
+reg [31 : 0] gd8a421;
+reg [31 : 0] fa5210d;
+reg [2047:0] wy2e8db;
+wire [5:0] vv746d9;
+
+localparam ksa36ce = 6,tw1b670 = 32'hfdffe0cb;
+localparam [31:0] icdb382 = tw1b670;
+localparam mece084 = tw1b670 & 4'hf;
+localparam [11:0] ou8210c = 'h7ff;
+wire [(1 << mece084) -1:0] db84308;
+reg [ksa36ce-1:0] dbc230;
+reg [mece084-1:0] kf8c37 [0:1];
+reg [mece084-1:0] hq30de9;
+reg hq86f4b;
+integer hd37a5a;
+integer dobd2d6;
+
+
+assign ls2f153[31] = ~gd8a421[0];
+assign ls2f153[30] = ~gd8a421[1];
+assign ls2f153[29] = ~gd8a421[2];
+assign ls2f153[28] = ~gd8a421[3];
+assign ls2f153[27] = ~gd8a421[4];
+assign ls2f153[26] = ~gd8a421[5];
+assign ls2f153[25] = ~gd8a421[6];
+assign ls2f153[24] = ~gd8a421[7];
+assign ls2f153[23] = ~gd8a421[8];
+assign ls2f153[22] = ~gd8a421[9];
+assign ls2f153[21] = ~gd8a421[10];
+assign ls2f153[20] = ~gd8a421[11];
+assign ls2f153[19] = ~gd8a421[12];
+assign ls2f153[18] = ~gd8a421[13];
+assign ls2f153[17] = ~gd8a421[14];
+assign ls2f153[16] = ~gd8a421[15];
+assign ls2f153[15] = ~gd8a421[16];
+assign ls2f153[14] = ~gd8a421[17];
+assign ls2f153[13] = ~gd8a421[18];
+assign ls2f153[12] = ~gd8a421[19];
+assign ls2f153[11] = ~gd8a421[20];
+assign ls2f153[10] = ~gd8a421[21];
+assign ls2f153[9] = ~gd8a421[22];
+assign ls2f153[8] = ~gd8a421[23];
+assign ls2f153[7] = ~gd8a421[24];
+assign ls2f153[6] = ~gd8a421[25];
+assign ls2f153[5] = ~gd8a421[26];
+assign ls2f153[4] = ~gd8a421[27];
+assign ls2f153[3] = ~gd8a421[28];
+assign ls2f153[2] = ~gd8a421[29];
+assign ls2f153[1] = ~gd8a421[30];
+assign ls2f153[0] = ~gd8a421[31];
+
+always @ (posedge ou10b33 or negedge ux2ccc5)
+begin   if (!ux2ccc5) begin      yk4962f <= 32'hffffffff;   end   else if (txmac_clk_en) begin      if (nec54d1) begin         yk4962f <= fa5210d;      end else if (an9a290) begin         yk4962f <= med1484;      end   end
+end
+
+assign rgc5e2a[0] = gd8a421[30] ^ ea78a9a[7] ^ ea78a9a[1] ^ gd8a421[24];
+assign rgc5e2a[1] = gd8a421[30] ^ ea78a9a[6] ^ ea78a9a[7] ^ gd8a421[31]                    ^ ea78a9a[0] ^ ea78a9a[1] ^ gd8a421[24] ^ gd8a421[25];
+assign rgc5e2a[2] = gd8a421[30] ^ ea78a9a[6] ^ ea78a9a[7] ^ gd8a421[31]                    ^ ea78a9a[0] ^ ea78a9a[1] ^ gd8a421[24] ^ gd8a421[25]    ^ gd8a421[26] ^ ea78a9a[5];
+assign rgc5e2a[3] = gd8a421[31] ^ ea78a9a[0] ^ gd8a421[25] ^ gd8a421[26]                    ^ ea78a9a[4] ^ gd8a421[27] ^ ea78a9a[5] ^ ea78a9a[6];
+assign rgc5e2a[4] = gd8a421[30] ^ ea78a9a[1] ^ gd8a421[24] ^ gd8a421[26]                  ^ ea78a9a[3] ^ ea78a9a[4] ^ gd8a421[27] ^ ea78a9a[5] ^ gd8a421[28]  ^ ea78a9a[7];
+assign rgc5e2a[5] = gd8a421[30] ^ gd8a421[31] ^ ea78a9a[0] ^ ea78a9a[1]                    ^ gd8a421[24] ^ gd8a421[25] ^ ea78a9a[2] ^ ea78a9a[3]    ^ ea78a9a[4] ^ gd8a421[27] ^ gd8a421[28] ^ ea78a9a[6]    ^ gd8a421[29] ^ ea78a9a[7];
+assign rgc5e2a[6] = gd8a421[30] ^ gd8a421[31] ^ ea78a9a[0] ^ ea78a9a[1]                    ^ gd8a421[25] ^ ea78a9a[2] ^ gd8a421[26] ^ ea78a9a[3]    ^ ea78a9a[5] ^ gd8a421[28] ^ ea78a9a[6] ^ gd8a421[29];
+assign rgc5e2a[7] = gd8a421[31] ^ ea78a9a[0] ^ gd8a421[24] ^ ea78a9a[2]                    ^ gd8a421[26] ^ ea78a9a[4] ^ gd8a421[27] ^ ea78a9a[5]    ^ gd8a421[29] ^ ea78a9a[7];
+assign rgc5e2a[8] = gd8a421[24] ^ gd8a421[25] ^ ea78a9a[3] ^ ea78a9a[4]                    ^ gd8a421[27] ^ gd8a421[28] ^ ea78a9a[6] ^ ea78a9a[7]    ^ gd8a421[0];
+assign rgc5e2a[9] = gd8a421[25] ^ ea78a9a[2] ^ gd8a421[26] ^ ea78a9a[3] ^ ea78a9a[5]                    ^ gd8a421[28] ^ ea78a9a[6] ^ gd8a421[29] ^ gd8a421[1];
+assign rgc5e2a[10] = gd8a421[24] ^ ea78a9a[2] ^ gd8a421[26] ^ ea78a9a[4]                     ^ gd8a421[27] ^ ea78a9a[5] ^ gd8a421[29] ^ ea78a9a[7]     ^ gd8a421[2];
+assign rgc5e2a[11] = gd8a421[3] ^ gd8a421[24] ^ gd8a421[25] ^ ea78a9a[3]                  ^ ea78a9a[4] ^ gd8a421[27] ^ gd8a421[28] ^ ea78a9a[6] ^ ea78a9a[7];
+assign rgc5e2a[12] = gd8a421[30] ^ gd8a421[4] ^ ea78a9a[1] ^ gd8a421[24]                  ^ gd8a421[25] ^ ea78a9a[2] ^ gd8a421[26] ^ ea78a9a[3] ^ ea78a9a[5]  ^ gd8a421[28] ^ ea78a9a[6] ^ gd8a421[29] ^ ea78a9a[7];
+assign rgc5e2a[13] = gd8a421[30] ^ gd8a421[31] ^ ea78a9a[0] ^ gd8a421[5]                  ^ ea78a9a[1] ^ gd8a421[25] ^ ea78a9a[2] ^ gd8a421[26] ^ ea78a9a[4]  ^ gd8a421[27] ^ ea78a9a[5] ^ ea78a9a[6] ^ gd8a421[29];
+assign rgc5e2a[14] = gd8a421[30] ^ gd8a421[31] ^ ea78a9a[0] ^ ea78a9a[1]                      ^ gd8a421[6] ^ gd8a421[26] ^ ea78a9a[3] ^ ea78a9a[4]      ^ gd8a421[27] ^ ea78a9a[5] ^ gd8a421[28];
+assign rgc5e2a[15] = gd8a421[31] ^ ea78a9a[0] ^ ea78a9a[2] ^ gd8a421[7] ^ ea78a9a[3]                     ^ ea78a9a[4] ^ gd8a421[27] ^ gd8a421[28] ^ gd8a421[29];
+assign rgc5e2a[16] = gd8a421[24] ^ ea78a9a[2] ^ ea78a9a[3] ^ gd8a421[8]                     ^ gd8a421[28] ^ gd8a421[29] ^ ea78a9a[7];
+assign rgc5e2a[17] = gd8a421[30] ^ ea78a9a[1] ^ gd8a421[25] ^ ea78a9a[2]                     ^ gd8a421[9] ^ ea78a9a[6] ^ gd8a421[29];
+assign rgc5e2a[18] = gd8a421[30] ^ gd8a421[31] ^ ea78a9a[0] ^ ea78a9a[1]                     ^ gd8a421[26] ^ ea78a9a[5] ^ gd8a421[10];
+assign rgc5e2a[19] = gd8a421[31] ^ ea78a9a[0] ^ ea78a9a[4] ^ gd8a421[27]                     ^ gd8a421[11];
+assign rgc5e2a[20] = gd8a421[12] ^ ea78a9a[3] ^ gd8a421[28];
+assign rgc5e2a[21] = gd8a421[13] ^ ea78a9a[2] ^ gd8a421[29];
+assign rgc5e2a[22] = gd8a421[14] ^ gd8a421[24] ^ ea78a9a[7];
+assign rgc5e2a[23] = gd8a421[30] ^ ea78a9a[1] ^ gd8a421[24] ^ gd8a421[15]                     ^ gd8a421[25] ^ ea78a9a[6] ^ ea78a9a[7];
+assign rgc5e2a[24] = gd8a421[31] ^ ea78a9a[0] ^ gd8a421[25] ^ gd8a421[16]                     ^ gd8a421[26] ^ ea78a9a[5] ^ ea78a9a[6];
+assign rgc5e2a[25] = gd8a421[26] ^ gd8a421[17] ^ ea78a9a[4]                     ^ gd8a421[27] ^ ea78a9a[5];
+assign rgc5e2a[26] = gd8a421[30] ^ ea78a9a[1] ^ gd8a421[24] ^ ea78a9a[3] ^ ea78a9a[4]                     ^ gd8a421[27] ^ gd8a421[18] ^ gd8a421[28] ^ ea78a9a[7];
+assign rgc5e2a[27] = gd8a421[31] ^ ea78a9a[0] ^ gd8a421[25] ^ ea78a9a[2] ^ ea78a9a[3]                     ^ gd8a421[28] ^ gd8a421[19] ^ ea78a9a[6] ^ gd8a421[29];
+assign rgc5e2a[28] = gd8a421[30] ^ ea78a9a[1] ^ ea78a9a[2] ^ gd8a421[26]                     ^ ea78a9a[5] ^ gd8a421[29] ^ gd8a421[20];
+assign rgc5e2a[29] = gd8a421[30] ^ gd8a421[21] ^ gd8a421[31] ^ ea78a9a[0]                     ^ ea78a9a[1] ^ ea78a9a[4] ^ gd8a421[27];
+assign rgc5e2a[30] = gd8a421[31] ^ gd8a421[22] ^ ea78a9a[0] ^ ea78a9a[3]                     ^ gd8a421[28];
+assign rgc5e2a[31] = gd8a421[23] ^ ea78a9a[2] ^ gd8a421[29];
+always@* begin ea78a9a<={lq7c1c8>>1,vv746d9[0]};nec54d1<=vv746d9[1];an9a290<=vv746d9[2];med1484<={lq42166>>1,vv746d9[3]};gd8a421<={yk4962f>>1,vv746d9[4]};fa5210d<={rgc5e2a>>1,vv746d9[5]};end
+always@* begin wy2e8db[2047]<=mee0e42;wy2e8db[2046]<=rtc842c;wy2e8db[2044]<=lq42166[0];wy2e8db[2040]<=yk4962f[0];wy2e8db[2033]<=rgc5e2a[0];wy2e8db[1023]<=lq7c1c8[0];end         assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6<ksa36ce; dobd2d6=dobd2d6+1) begin dbc230[dobd2d6] = db84308[hq30de9]; hq86f4b = ^(hq30de9 & kf8c37[0]); hq30de9 = {hq30de9, hq86f4b}; end end 
+endmodule
+
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+
+`timescale 1 ns / 100 ps
+module oha1c94  ( wyb91ce,
+                    zxc8e70,
+                    txmac_clk_en,
+
+                    fp948c9,       
+                    yza464e,      
+                    gd23275,      
+                    ph193ac,   
+                    ipc9d67,    
+                    wj4eb3d       
+                  );
+parameter al759ec = 5;
+input               wyb91ce;
+input               zxc8e70;
+input               txmac_clk_en;
+input               fp948c9;
+input               gd23275;
+input               ph193ac;
+input [al759ec-1:0] yza464e;
+output              wj4eb3d;
+output              ipc9d67;
+reg [al759ec-1:0]   ui7d18f;
+reg [al759ec-1:0]   go463c4;
+reg                 aa31e21;
+reg                 ipc9d67;
+reg                 os7884d;
+reg                 osc4269;
+reg                 wj4eb3d;
+parameter jr9a41 = 1'b0;
+parameter dm4d20f = 1'b1;
+wire [al759ec-1:0] xw483d3 = yza464e - 5'd1;
+reg [al759ec-1:0] ip7a6a9;
+wire uvd354d = fp948c9 & ~aa31e21;
+reg eca9b2b;
+reg [al759ec - 1 : 0] rg6cac3;
+reg cz6561a;
+reg ks2b0d5;
+reg [al759ec - 1 : 0] uvc3543;
+reg [al759ec - 1 : 0] dmd50e9;
+reg lsa874b;
+reg ic43a5b;
+reg oh1d2d8;
+reg [al759ec - 1 : 0] ip4b62f;
+reg [al759ec - 1 : 0] jpd8bec;
+reg hoc5f66;
+reg [2047:0] wy2e8db;
+wire [11:0] vv746d9;
+
+localparam ksa36ce = 12,tw1b670 = 32'hfdffd48b;
+localparam [31:0] icdb382 = tw1b670;
+localparam mece084 = tw1b670 & 4'hf;
+localparam [11:0] ou8210c = 'h7ff;
+wire [(1 << mece084) -1:0] db84308;
+reg [ksa36ce-1:0] dbc230;
+reg [mece084-1:0] kf8c37 [0:1];
+reg [mece084-1:0] hq30de9;
+reg hq86f4b;
+integer hd37a5a;
+integer dobd2d6;
+
+always @ (uvc3543 or jpd8bec) begin         if(uvc3543 == jpd8bec)           wj4eb3d = 1'b1;         else           wj4eb3d = 1'b0;   end
+      always @ (posedge wyb91ce or negedge zxc8e70) begin      if(!zxc8e70) begin        os7884d <= jr9a41;        ip7a6a9 <= 6'b0;      end      else if (txmac_clk_en) begin        os7884d <= oh1d2d8;        ip7a6a9 <= ip4b62f;      end   end            always @ (ic43a5b or eca9b2b or wj4eb3d) begin      case(ic43a5b)        jr9a41: begin           if(!eca9b2b) begin              osc4269 = jr9a41;           end           else begin              osc4269 = dm4d20f;           end         end        dm4d20f: begin           if(wj4eb3d) begin              osc4269 = jr9a41;           end           else begin              osc4269 = dm4d20f;           end        end      endcase   end      always @ (posedge wyb91ce or negedge zxc8e70) begin      if(!zxc8e70) begin        ui7d18f <= 5'd0;      end      else if (txmac_clk_en) begin         if(cz6561a) begin            ui7d18f <= 5'd0;         end         else if(oh1d2d8) begin            ui7d18f <= uvc3543 + 5'd1;         end         else begin           ui7d18f <= 5'd0;         end     end   end      always @ (posedge wyb91ce or negedge zxc8e70) begin      if(!zxc8e70) begin         aa31e21 <= 1'b0;      end      else if (txmac_clk_en) begin         aa31e21 <= eca9b2b;      end   end      always @ (posedge wyb91ce or negedge zxc8e70) begin      if(!zxc8e70)        go463c4 <= 5'd0;      else if (txmac_clk_en) begin         if( (hoc5f66 || ((dmd50e9 != jpd8bec) && (dmd50e9 != 5'd0)) ) &&              (ipc9d67 || !ks2b0d5) )            go463c4 <= dmd50e9 + 5'd1;         else if(!hoc5f66) begin           go463c4 <= 5'd0;         end      end   end
+   always @ (rg6cac3 or dmd50e9) begin      case(rg6cac3)        5'd24: ipc9d67 = dmd50e9[4];         5'd27: ipc9d67 = dmd50e9[4] & (|dmd50e9[3:1]);         5'd30: ipc9d67 = dmd50e9[4] & (|dmd50e9[3:2]);         default: ipc9d67 = 1'b0;      endcase   end
+always@* begin eca9b2b<=vv746d9[0];rg6cac3<={yza464e>>1,vv746d9[1]};cz6561a<=vv746d9[2];ks2b0d5<=vv746d9[3];uvc3543<={ui7d18f>>1,vv746d9[4]};dmd50e9<={go463c4>>1,vv746d9[5]};lsa874b<=vv746d9[6];ic43a5b<=vv746d9[7];oh1d2d8<=vv746d9[8];ip4b62f<={xw483d3>>1,vv746d9[9]};jpd8bec<={ip7a6a9>>1,vv746d9[10]};hoc5f66<=vv746d9[11];end
+always@* begin wy2e8db[2047]<=yza464e[0];wy2e8db[2046]<=gd23275;wy2e8db[2044]<=ph193ac;wy2e8db[2040]<=ui7d18f[0];wy2e8db[2032]<=go463c4[0];wy2e8db[2017]<=aa31e21;wy2e8db[1987]<=os7884d;wy2e8db[1927]<=osc4269;wy2e8db[1806]<=xw483d3[0];wy2e8db[1565]<=ip7a6a9[0];wy2e8db[1082]<=uvd354d;wy2e8db[1023]<=fp948c9;end         assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6<ksa36ce; dobd2d6=dobd2d6+1) begin dbc230[dobd2d6] = db84308[hq30de9]; hq86f4b = ^(hq30de9 & kf8c37[0]); hq30de9 = {hq30de9, hq86f4b}; end end 
+endmodule
+
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+`timescale 1 ns / 100 ps
+module db3283c (txmac_clk,
+                 zxc8e70,
+                 txmac_clk_en,      
+                 wl3cdf4,          
+                 dze6fa5,           
+                 vx37d2f,           
+                 mtbe97e,         
+                 vif4bf4,            
+                 rva5fa3,            
+                 xy2fd1e,     
+                 dz7e8f3,     
+                 byf479e,   
+                 gqa3cf2,    
+                 ri1e791,   
+                 tx_fifoavail,      
+                 nt9e456,     
+                 off22b6,   
+                 nt915b5,       
+                 oh8adaf, 
+                 me56d7c,   
+                 ecb6be1,   
+                 wj4eb3d,         
+                 jraf847,         
+                 tu7c23f,       
+                 zke11fa,       
+                 oh8fd3,         
+                 sh70ee9,     
+                 ipc9d67,       
+                 kqfa753,    
+                 kdd3a99,     
+                 ou9d4cd,        
+                 tx_discfrm,        
+                 ea53348,     
+                 pu99a40,       
+                 fncd202,          
+                 tu69016,        
+                 vi480b3,         
+                 th4059a,        
+                 yz2cd6,         
+                 fp948c9,          
+                 ieb35a6,          
+                 oh39c3b,      
+                 qtd698d,        
+                 mtb4c6d,      
+                 uka636d,    
+                 uk31b68,         
+                 gq8db41,      
+                 ea6da09,      
+                 ay6d048,    
+                 yk68241,     
+                 kd41209,      
+                 fp904c,    
+                 tu48266,     
+                 cz41332,     
+                 tj9994,        
+                 ea4cca7,        
+                 ps66539,       
+                 osce1dd,         
+                 vx94e56,        
+                 vka72b6,        
+                 ep395b2,      
+                 jccad94,    
+                 yk56ca2,     
+                 gd23275,         
+                 ph193ac,      
+                 db9444a          
+                 );
+parameter lsa2257 = 48;
+parameter ba112ba = 16;
+parameter vk895d3 = 8;
+parameter th4ae9a = 16;
+parameter by574d6 = 32;
+parameter tjba6b2 = 14;
+parameter qi8774d = 4;
+parameter qv9acbc = 22;
+parameter qtd65e5 = 13;
+parameter hqb2f2c = 13'd6072;
+parameter co97962 = 8'h55;
+parameter cobcb11 = 8'hd5;
+parameter wwe5889 = 8'h00;
+parameter mt2c448 = 8'h01;
+parameter qg62245 = 8'h80;
+parameter pu11228 = 8'hc2;
+parameter do89143 = 8'h00;
+parameter dm48a1a = 8'h00;
+parameter jp450d3 = 8'h01;
+parameter xl2869e = 8'h88;
+parameter ay434f7 = 8'h08;
+parameter ec1a7b9 = 8'h00;
+input                            txmac_clk;
+input                            zxc8e70;
+input                            txmac_clk_en;
+input                            wl3cdf4;
+input                            dze6fa5;
+input                            vx37d2f;
+input                            mtbe97e;
+input                            vif4bf4;
+input                            rva5fa3;
+input [lsa2257-1:0]              xy2fd1e;
+input [ba112ba-1:0]       dz7e8f3;
+input [vk895d3-1:0]           byf479e;
+input                            gqa3cf2;
+input                            ri1e791;
+input                            tx_fifoavail;
+input                            nt9e456;
+input                            nt915b5;
+input                            oh8adaf;
+input [th4ae9a-1:0]          me56d7c;
+input                            ecb6be1;
+input                            wj4eb3d;
+input [by574d6-1:0]         jraf847;
+input                            tu7c23f;
+input                            zke11fa;
+input [vk895d3:0]             off22b6;
+input                            oh8fd3;
+input                            sh70ee9;
+input                            ipc9d67;
+input                            kqfa753;
+input                            kdd3a99;
+output                           ou9d4cd;
+output                           tx_discfrm;
+output                           ea53348;
+output                           pu99a40;
+output                           fncd202;
+output [vk895d3-1:0]          tu69016;
+output                           vi480b3;
+output [vk895d3-1:0]          th4059a;
+output                           yz2cd6;
+output                           fp948c9;
+output                           ieb35a6;
+output                           oh39c3b;
+output                           qtd698d;
+output                           mtb4c6d;
+output                           uka636d;
+output                           uk31b68;
+output                           gq8db41;
+output                           ea6da09;
+output                           ay6d048;
+output                           yk68241;
+output                           kd41209;
+output                           fp904c;
+output                           tu48266;
+output                           cz41332;
+output                           tj9994;
+output                           ea4cca7;
+output                           ps66539;
+output [qi8774d-1:0]         osce1dd;
+output                           vx94e56;
+output                           vka72b6;
+output                           ep395b2;
+output                           jccad94;
+output                           yk56ca2;
+output                           gd23275;
+output                           ph193ac;
+output                           db9444a;
+reg [4:0]                        os7884d  ;
+reg [4:0]                        osc4269;
+reg                              fp948c9;
+reg                              zx7eca7;
+reg                              xjf653e;
+reg [vk895d3-1:0]             ph94fba;
+reg [vk895d3-1:0]             mg3eeb3;
+reg [vk895d3-1:0]             zzbacc5;
+reg [vk895d3-1:0]             tu69016;
+reg                              ou9d4cd;
+reg                              byc5d08;
+reg                              mg2e843;
+reg                              th74219;
+reg                              fncd202;
+reg                              qv8675;
+reg                              cm433ac;
+reg                              xl19d61;
+reg  [1:0]                       osceb0e;
+reg  [1:0]                       of75870;
+reg                              ksac385;
+reg                              dz61c29;
+reg                              ea53348;
+reg                              pu99a40;
+reg                              tx_discfrm;
+reg                              ir29cec;
+reg                              ip4e764;
+reg                              vi73b25;
+reg                              vi480b3;
+reg                              ieb35a6;
+reg                              ep395b2;
+reg                              vx94e56;
+reg                              vka72b6;
+reg                              db9444a;
+reg [qi8774d-1:0]            osce1dd;
+reg                              ea4cca7;
+reg                              tj9994;
+reg                              ps66539;
+reg                              oh39c3b;
+reg                              oh95362;
+reg [qtd65e5-1:0]          zk4d8a8;
+reg                              jccad94;
+reg                              yk56ca2;
+reg                              gd23275;
+reg                              lsa86c9;
+reg                              ic4364b;
+reg                              ri1b259;
+reg                              ph193ac;
+reg [3:0]                        wjc9655;
+reg                              al4b2ac;
+reg                              ic59565;
+reg [1:0]                        dmcab29;
+reg                              fn5594a;
+reg                              wyaca56;
+reg                              qt652b0;
+reg                              ux29585;
+parameter fn4ac2d = 5'd0;
+parameter su5616e = 5'd1;
+parameter zzb0b70 = 5'd2;
+parameter wl85b87 = 5'd3;
+parameter bn2dc3d = 5'd4;
+parameter fn6e1ee = 5'd5;
+parameter kd70f76 = 5'd6;
+parameter ec87bb5 = 5'd7;
+parameter jr3dda8 = 5'd8;
+parameter byeed47 = 5'd9;
+parameter ho76a3b = 5'd10;
+parameter fpb51da = 5'd11;
+parameter nga8ed6 = 5'd12;
+parameter vi476b2 = 5'd13;
+parameter qi3b593 = 5'd14;
+parameter fadac99 = 5'd15;
+parameter gbd64cb = 5'd16;
+parameter fcb265c = 5'd17;
+parameter ri932e3 = 5'd18;
+parameter pu9971a = 5'd19;
+parameter gocb8d3 = 5'd20;
+parameter ay5c698 = 5'd21;
+wire      qtd698d = (os7884d == fn4ac2d) ? 1 : 0;
+wire      mtb4c6d = (os7884d == su5616e) ? 1 : 0;
+wire      uka636d = (os7884d == zzb0b70) ? 1 : 0;
+wire      uk31b68 = (os7884d == wl85b87) ? 1 : 0;
+wire      gq8db41 = (os7884d == bn2dc3d) ? 1 : 0;
+wire      ay6d048 = (os7884d == fn6e1ee) ? 1 : 0;
+wire      ea6da09 = (os7884d == kd70f76) ? 1 : 0;
+wire      yk68241 = (os7884d == ec87bb5) ? 1 : 0;
+wire      kd41209 = (os7884d == jr3dda8) ? 1 : 0;
+wire      fp904c = (os7884d == byeed47) ? 1 : 0;
+wire      sj84dc = (os7884d == ho76a3b) ? 1 : 0;
+wire      tu48266 = (os7884d == fpb51da) ? 1 : 0;
+wire      kf23de3 = (os7884d == nga8ed6) ? 1 : 0;
+wire      cobc75c = (os7884d == vi476b2) ? 1 : 0;
+wire      cz41332 = (os7884d == qi3b593) ? 1 : 0;
+wire      ux7ac8 = (os7884d == fadac99) ? 1 : 0;
+wire      yk59132 = (os7884d == gbd64cb) ? 1 : 0;
+wire      sj2647d = (os7884d == fcb265c) ? 1 : 0;
+wire      ep8fb3e = (zk4d8a8 == hqb2f2c);
+wire [vk895d3-1:0] th4059a = mg3eeb3[7:0];
+wire                  yz2cd6 = dz61c29;
+reg [2:0]    th710a3;
+reg [5:0]    uk8851e;
+reg [7:0]    jc428f0;
+reg          vk14782;
+reg          yma3c13;
+reg          fc1e099;
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+reg ayf04ca;
+reg ym82650;
+reg rv13281;
+reg pu9940e;
+reg hoca073;
+reg pf5039b;
+reg [lsa2257 - 1 : 0] twe6ff;
+reg [ba112ba - 1 : 0] tj9bfdb;
+reg [vk895d3 - 1 : 0] qgff6fb;
+reg fafb7d9;
+reg uidbecb;
+reg vidf659;
+reg zkfb2ca;
+reg [vk895d3 : 0] qgcb29d;
+reg go594e9;
+reg neca749;
+reg [th4ae9a - 1 : 0] ym9d259;
+reg dze92c9;
+reg ww4964f;
+reg [by574d6 - 1 : 0] ic593c5;
+reg enc9e29;
+reg rt4f14d;
+reg os78a6f;
+reg psc5379;
+reg sj29bca;
+reg jc4de54;
+reg en6f2a3;
+reg [4 : 0] ic43a5b;
+reg [4 : 0] oh1d2d8;
+reg qt54712;
+reg ksa3895;
+reg [vk895d3 - 1 : 0] kde254f;
+reg [vk895d3 - 1 : 0] sj953e5;
+reg [vk895d3 - 1 : 0] xj4f968;
+reg ho7cb46;
+reg kqe5a33;
+reg vx2d198;
+reg kq68cc7;
+reg ww46638;
+reg an331c1;
+reg [1 : 0] co98e0d;
+reg [1 : 0] fnc7068;
+reg vx38347;
+reg osc1a3e;
+reg ohd1f1;
+reg me68f8c;
+reg ne47c60;
+reg aa3e302;
+reg [qtd65e5 - 1 : 0] hq8c08b;
+reg kd6045a;
+reg yz22d5;
+reg pu116ad;
+reg [3 : 0] fp8b56b;
+reg zx5ab5f;
+reg jcd5aff;
+reg [1 : 0] doad7fa;
+reg zx6bfd3;
+reg th5fe9f;
+reg meff4ff;
+reg ykfa7f9;
+reg shd3fc9;
+reg cb9fe4d;
+reg goff26d;
+reg fnf9369;
+reg shc9b4e;
+reg [2 : 0] xw4da75;
+reg [5 : 0] kq6d3ab;
+reg [7 : 0] by69d59;
+reg en4eaca;
+reg mr75654;
+reg sjab2a4;
+reg [2047:0] wy2e8db;
+wire [70:0] vv746d9;
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+
+localparam ksa36ce = 71,tw1b670 = 32'hfdffe44b;
+localparam [31:0] icdb382 = tw1b670;
+localparam mece084 = tw1b670 & 4'hf;
+localparam [11:0] ou8210c = 'h7ff;
+wire [(1 << mece084) -1:0] db84308;
+reg [ksa36ce-1:0] dbc230;
+reg [mece084-1:0] kf8c37 [0:1];
+reg [mece084-1:0] hq30de9;
+reg hq86f4b;
+integer hd37a5a;
+integer dobd2d6;
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+   always @ (posedge txmac_clk or negedge zxc8e70) begin      if(!zxc8e70) begin         os7884d <= fn4ac2d;         fc1e099 <= 0;         mg3eeb3 <= 0;         mg2e843 <= 0;         ip4e764 <= 0;         dz61c29 <= 0;         xl19d61 <= 0;         of75870 <= 0;         zzbacc5 <= 0;         th74219 <= 0;         vi73b25 <= 0;         tu69016 <= 0;         fncd202 <= 0;         vi480b3 <= 0;         ieb35a6 <= 0;      end      else if (txmac_clk_en) begin ieb35a6 <= neca749 & (qtd698d | mtb4c6d) ? 1'b1 : ~neca749 ? 1'b0 : ieb35a6;         os7884d <= oh1d2d8;         fc1e099 <= go594e9;         mg3eeb3 <= kde254f;         mg2e843 <= ho7cb46;         ip4e764 <= ohd1f1;         dz61c29 <= vx38347;         xl19d61 <= ww46638;         of75870 <= co98e0d;         th74219 <= kqe5a33 | kq68cc7;         vi73b25 <= me68f8c; if (an331c1 == 1) begin    case (fnc7068)       3: begin          zzbacc5 <= ic593c5[7:0];       end       2: begin          zzbacc5 <= ic593c5[15:8];       end       1: begin          zzbacc5 <= ic593c5[23:16];       end       0: begin          zzbacc5 <= ic593c5[31:24];       end    endcase end else begin            zzbacc5 <= sj953e5; end         tu69016 <= xj4f968;         fncd202 <= vx2d198;         vi480b3 <= ne47c60;      end   end      always @ (ic43a5b or vidf659 or qgff6fb or fafb7d9           or sjab2a4 or ayf04ca or pu9940e or ym82650 or ww4964f   or neca749 or rt4f14d   or os78a6f or dze92c9 or ph193ac           or rv13281 or qt54712 or zkfb2ca or enc9e29   or pu116ad or qgcb29d or osce1dd           or sj29bca or jc4de54 or zx6bfd3           or ksa3895 or ux29585 or qt652b0 or jcd5aff           or vka72b6 or vx94e56 or en6f2a3 or xw4da75   or mr75654 or by69d59) begin      fp948c9 = 0;      ph94fba = 0;      ou9d4cd = 0;      byc5d08 = 0;      qv8675 = 0;      ea4cca7 = 0;      ksac385 = 0;      osceb0e = 0;      cm433ac = 0;      pu99a40 = 0;      tx_discfrm = 0;      ir29cec = 0;      tj9994 = 0;      ps66539 = 0;      oh95362 = 0;      oh39c3b = 0;      ea53348 = 0;      yk56ca2 = 0;      gd23275 = 0;      al4b2ac = 0;      wyaca56 = 0;
+      case (ic43a5b)        fn4ac2d: begin           if(ww4964f) begin              osc4269 = su5616e;              fp948c9 = 1'b0;           end           else begin
+
+
+              if(ph193ac && !sj29bca && rv13281) begin                 if(vidf659) begin                    osc4269 = fadac99;                 end                 else begin                    osc4269 = fn4ac2d;                 end                 fp948c9 = 1'b0;                 gd23275 = 1'b1;              end              else begin                osc4269 = fn4ac2d;                fp948c9 = 1'b1;              end
+
+
+           end        end        su5616e: begin
+
+
+           if(ayf04ca) begin              if(rv13281) begin                  if (vidf659) begin                    if(!ph193ac || sj29bca) begin                       osc4269 = zzb0b70;                    end                    else begin                       osc4269 = fadac99;                    end                 end                 else begin                   osc4269 = su5616e; end              end              else begin                  if( (vidf659 && (!neca749 || sjab2a4)) || (ym82650 && dze92c9) ) begin                    osc4269 = zzb0b70;                 end                 else begin                   osc4269 = su5616e;                 end              end            end            else begin              osc4269 = su5616e;           end 
+
+
+
+        end 
+
+
+        fadac99: begin           if(ph193ac) begin              osc4269 = fadac99;              oh95362 = 1'b1;              gd23275 = 1'b1;           end           else begin              osc4269 = gbd64cb;           end        end
+
+
+
+        gbd64cb: begin           if(ww4964f) begin              osc4269 = zzb0b70;              fp948c9 = 1'b0;           end           else begin
+
+
+              if(!ph193ac || sj29bca) begin                osc4269 = gbd64cb;                fp948c9 = 1'b1;              end              else begin                 osc4269 = fadac99;                 fp948c9 = 1'b0;                 gd23275 = 1'b1;              end
+
+
+           end        end
+        zzb0b70: begin              ph94fba = co97962;              byc5d08 = 1;           if(xw4da75 == 0) begin              osc4269 = wl85b87;           end else begin              osc4269 = zzb0b70;           end        end        wl85b87: begin           ph94fba = cobcb11;           byc5d08 = 1;
+
+
+           if(rv13281) begin               if(pu116ad || ksa3895) begin                 if(osce1dd == 4'hf)                   osc4269 = fcb265c;                 else begin                   osc4269 = ho76a3b;                  end              end              else begin                 if(zkfb2ca) begin                    osc4269 = bn2dc3d;                 end                 else begin    tj9994 = 1;                    osc4269 = qi3b593;                 end              end            end           else begin               if(dze92c9 && ym82650)                osc4269 = fn6e1ee;              else begin                 osc4269 = bn2dc3d;              end           end 
+
+
+        end         bn2dc3d: begin   ou9d4cd = 1;           byc5d08 = 1'b1;           ph94fba = qgff6fb[7:0];           ksac385 = 1;
+
+
+           if(jc4de54) begin              if(rt4f14d) begin                osc4269 = kd70f76;              end else begin                osc4269 = jr3dda8;              end           end           else if(rv13281) begin               if(enc9e29) begin                ea4cca7 = 1'b1;      end              if(pu116ad || qt54712) begin                 if(enc9e29 && (osce1dd == 4'hf) ) begin                    osc4269 = fcb265c;                 end else if(enc9e29) begin                     yk56ca2 = 1'b1;                    osc4269 = ho76a3b;                 end                 else begin                     osc4269 = byeed47; end              end              else if (fafb7d9 && !pu9940e) begin                 if(rt4f14d && !os78a6f) begin                   osc4269 = kd70f76;                 end else begin                   osc4269 = ec87bb5; end              end               else if (fafb7d9 && pu9940e) begin                 osc4269 = ri932e3;              end else begin                 osc4269 = bn2dc3d;      end           end           else begin               if(fafb7d9 && !pu9940e) begin                 if(rt4f14d && !os78a6f) begin                      osc4269 = kd70f76;                 end else begin                   osc4269 = ec87bb5; end              end               else if(fafb7d9 && pu9940e) begin                 osc4269 = ri932e3;              end else begin                 osc4269 = bn2dc3d;      end           end 
+
+
+        end 
+        fn6e1ee: begin              ph94fba = by69d59;              byc5d08 = 1;              ksac385 = 1;              if(mr75654) begin                osc4269 = ec87bb5;              end else begin                osc4269 = fn6e1ee;      end        end 
+        kd70f76: begin           byc5d08 = 1;           ksac385 = 1;           ph94fba = wwe5889; 
+
+
+           if(rv13281 && (pu116ad || qt54712)) begin              if(osce1dd == 4'hf) begin                osc4269 = fcb265c;              end else begin                 if(!jc4de54) begin                     yk56ca2 = 1'b1;                    osc4269 = ho76a3b;                 end else begin                    osc4269 = jr3dda8; end              end           end            else if(pu9940e && jc4de54 && en6f2a3) begin              osc4269 = byeed47;           end else if(os78a6f) begin              if(jc4de54) begin                 osc4269 = jr3dda8;              end else begin                 osc4269 = ec87bb5;      end           end           else begin              osc4269 = kd70f76;   end
+
+
+        end        ec87bb5: begin           byc5d08 = 1;           cm433ac = 1;   case (xw4da75[1:0])      3: begin            osceb0e = 2'h3;      end      2: begin            osceb0e = 2'h2;      end      1: begin            osceb0e = 2'h1;      end      0: begin            osceb0e = 2'h0;      end   endcase
+
+
+           if(rv13281 && (pu116ad || qt54712)) begin              osc4269 = byeed47;           end else if (xw4da75[1:0] == 2'b00) begin              osc4269 = ri932e3;           end           else begin              osc4269 = ec87bb5;   end
+
+
+        end
+        ri932e3: begin   qv8675 = 1;
+
+
+           if(rv13281 && (pu116ad || qt54712)) begin              osc4269 = pu9971a;              wyaca56 = 1;           end           else begin              osc4269 = ay5c698;           end 
+
+
+        end 
+        ay5c698: begin
+
+
+           if(rv13281 && (pu116ad || qt54712)) begin              osc4269 = pu9971a;              wyaca56 = 1;      qv8675 = 1;           end           else begin              pu99a40 = 1;              ps66539 = 1;              ea53348 = 1;              osc4269 = fn4ac2d;           end 
+
+
+        end 
+
+
+
+        pu9971a: begin   qv8675 = 1;           wyaca56 = 1;           if(zx6bfd3) begin             osc4269 = gocb8d3;           end else begin             osc4269 = pu9971a;   end        end        gocb8d3: begin   qv8675 = 1;           osc4269 = fn4ac2d;           tx_discfrm = 1;           ea53348 = 1;           ps66539 = 1;        end 
+
+
+
+        jr3dda8: begin           byc5d08 = 1;           cm433ac = 1;        osceb0e = 2'h3;           ir29cec = 1;   if (xw4da75[1:0] == 2'b01) begin            osc4269 = byeed47;           end           else begin            osc4269 = jr3dda8;           end        end
+
+
+
+        fcb265c: begin           byc5d08 = 1;           cm433ac = 1;           osceb0e = 2;                                                    ir29cec = 0;            osc4269 = byeed47;        end
+
+
+
+        byeed47: begin           byc5d08 = 1;
+
+
+           if(vka72b6 || vx94e56) begin              al4b2ac = 1;              if(jcd5aff) begin                                    ir29cec = 0;                  tx_discfrm = 1;                 ps66539 = 1;                 ea53348 = 1;                 osc4269 = fn4ac2d;              end              else begin                 osc4269 = byeed47;              end           end            else begin              cm433ac = 1;              osceb0e = 1;              ir29cec = 1;              tx_discfrm = 1;              ps66539 = 1;              ea53348 = 1;              osc4269 = fn4ac2d;           end
+
+
+        end
+
+
+        ho76a3b: begin           byc5d08 = 1;           al4b2ac = 1;           if(jcd5aff) begin              osc4269 = fpb51da;           end           else begin              osc4269 = ho76a3b;           end        end
+        fpb51da: begin           case ({ux29585, qt652b0})             2'b00: begin                fp948c9 = 1;                oh39c3b = 1;                osc4269 = fpb51da;             end             2'b01: begin                fp948c9 = 1;                oh39c3b = 0;                osc4269 = fpb51da;             end             2'b10: begin                fp948c9 = 0;                oh39c3b = 1;                osc4269 = fpb51da;             end             2'b11: begin                fp948c9 = 0;                oh39c3b = 0;                if(ph193ac) begin                   osc4269 = nga8ed6;                   oh95362 = 1;                end                else begin                   osc4269 = zzb0b70;                end             end            endcase         end         nga8ed6: begin           if(ph193ac) begin              osc4269 = nga8ed6;              oh95362 = 1;           end           else begin              osc4269 = vi476b2;              fp948c9 = 1;           end        end
+
+
+
+        vi476b2: begin           if(ww4964f) begin              osc4269 = zzb0b70;              fp948c9 = 0;           end           else begin
+
+
+              if(ph193ac && !sj29bca && rv13281) begin                 osc4269 = nga8ed6;                 fp948c9 = 0;                 gd23275 = 1;              end              else begin                osc4269 = vi476b2;                fp948c9 = 1;              end
+
+
+           end        end        qi3b593: begin   tj9994 = 1;           byc5d08 = 1;           ph94fba = qgcb29d[7:0];
+
+
+           if(qt54712) begin              if(osce1dd == 4'hf)                 osc4269 = fcb265c;              else begin                 osc4269 = ho76a3b;                 yk56ca2 = 1'b1;              end           end           else if(zkfb2ca) begin      tj9994 = 0;              if(qgcb29d[8])                 osc4269 = kd70f76;              else begin                 osc4269 = bn2dc3d;              end           end           else begin              osc4269 = qi3b593;   end
+
+
+        end         default: osc4269 = fn4ac2d;
+      endcase    end 
+
+
+
+         always @ (posedge txmac_clk or negedge zxc8e70) begin      if(!zxc8e70) begin        zx7eca7 <= 0;      end      else if (txmac_clk_en) begin         if(pu116ad && (uka636d || uk31b68 || gq8db41 ||             ea6da09  || yk68241 || cz41332)) begin           zx7eca7 <= 1;         end else if(qtd698d || tu48266) begin           zx7eca7 <= 0;         end      end   end   always @ (posedge txmac_clk or negedge zxc8e70) begin      if(!zxc8e70) begin        xjf653e <= 0;      end      else if (txmac_clk_en) begin        if(pu116ad && uka636d) begin          xjf653e <= 1;        end        else if(qtd698d || tu48266) begin          xjf653e <= 0;        end      end   end      always @ (posedge txmac_clk or negedge zxc8e70) begin      if(!zxc8e70) begin        osce1dd <= 4'h0;      end      else if (txmac_clk_en) begin        if( jcd5aff ) begin            osce1dd <= osce1dd + 4'h1;        end        else if(qtd698d) begin          osce1dd <= 4'h0;        end      end   end
+
+      always @ (posedge txmac_clk or negedge zxc8e70) begin      if(!zxc8e70) begin         vx94e56 <= 0;      end      else if (txmac_clk_en) begin        if(pu116ad && !enc9e29 && rv13281) begin          vx94e56 <= 1;        end        else if(qtd698d) begin          vx94e56 <= 0;        end      end   end      always @ (posedge txmac_clk or negedge zxc8e70) begin      if(!zxc8e70) begin         ep395b2 <= 0;      end      else if (txmac_clk_en) begin        if(cb9fe4d || ykfa7f9) begin           ep395b2 <= 1;        end        else if(qtd698d) begin           ep395b2 <= 0;        end      end   end      always @ (posedge txmac_clk or negedge zxc8e70) begin      if(!zxc8e70) begin         vka72b6 <= 0;      end      else if (txmac_clk_en) begin        if(fnf9369) begin           vka72b6 <= 1;        end        else if(qtd698d) begin           vka72b6 <= 0;        end      end   end      always @ (posedge txmac_clk or negedge zxc8e70) begin      if(!zxc8e70) begin         jccad94 <= 0;      end      else if (txmac_clk_en) begin        if(shc9b4e) begin           jccad94 <= 1;        end        else if(qtd698d) begin           jccad94 <= 0;        end      end   end      always @ (posedge txmac_clk or negedge zxc8e70) begin      if(!zxc8e70) begin         zk4d8a8 <= 13'd0;      end      else if (txmac_clk_en) begin        if(aa3e302) begin           zk4d8a8 <= hq8c08b + 13'd1;        end        else begin           zk4d8a8 <= 13'd0;        end      end   end
+
+
+
+      always @ (posedge txmac_clk or negedge zxc8e70) begin      if(!zxc8e70) begin         db9444a <= 0;      end      else if (txmac_clk_en) begin        if(kd41209) begin           db9444a <= 1;        end        else if(qtd698d) begin           db9444a <= 0;        end      end   end      always @ (posedge txmac_clk or negedge zxc8e70) begin      if(!zxc8e70) begin         th710a3 <= 0;      end      else if (txmac_clk_en) begin        if ((mtb4c6d) || (goff26d) || (tu48266)                 || (shd3fc9)) begin           th710a3 <= 6;        end        else if ((gq8db41) || (ay6d048) || (ea6da09)) begin           th710a3 <= 3;        end        else if (xw4da75 != 0) begin th710a3 <= xw4da75 - 1;        end      end   end      always @ (posedge txmac_clk or negedge zxc8e70) begin      if(!zxc8e70) begin         jc428f0 <= 0;         uk8851e <= 0;         vk14782 <= 0;         yma3c13 <= 0;      end else if (txmac_clk_en) begin         if (uka636d) begin            uk8851e <= 0;            vk14782 <= 0;            yma3c13 <= 0;         end else begin    uk8851e <= kq6d3ab + 1;    if (kq6d3ab == 18) begin               vk14782 <= 1;            end    if (kq6d3ab == 59) begin               yma3c13 <= 1;            end end         case ({en4eaca,kq6d3ab})            0: begin       jc428f0 <= mt2c448;    end            1: begin       jc428f0 <= qg62245;    end            2: begin       jc428f0 <= pu11228;    end            3: begin       jc428f0 <= do89143;    end            4: begin       jc428f0 <= dm48a1a;    end            5: begin       jc428f0 <= jp450d3;    end            6: begin       jc428f0 <= twe6ff[47:40];    end            7: begin       jc428f0 <= twe6ff[39:32];    end            8: begin       jc428f0 <= twe6ff[31:24];    end            9: begin       jc428f0 <= twe6ff[23:16];    end            10: begin       jc428f0 <= twe6ff[15:8];    end            11: begin       jc428f0 <= twe6ff[7:0];    end            12: begin       jc428f0 <= xl2869e;    end            13: begin       jc428f0 <= ay434f7;    end            14: begin       jc428f0 <= tj9bfdb[15:8];    end            15: begin       jc428f0 <= tj9bfdb[7:0];    end            16: begin       jc428f0 <= ym9d259[15:8];    end            17: begin       jc428f0 <= ym9d259[7:0];    end            default: begin       jc428f0 <= ec1a7b9;    end         endcase       end   end
+
+
+         always @ (posedge txmac_clk or negedge zxc8e70) begin      if(!zxc8e70) begin         dmcab29 <= 0;      end      else if (txmac_clk_en) begin        if(th5fe9f) begin          dmcab29 <= doad7fa + 1;        end        else begin          dmcab29 <= 0;        end      end   end   always @ (doad7fa) begin      if(doad7fa == 2'b11) begin         fn5594a = 1;      end      else begin         fn5594a = 0;      end   end
+      always @ (posedge txmac_clk or negedge zxc8e70) begin      if(!zxc8e70) begin         wjc9655 <= 4'h0;      end      else if (txmac_clk_en) begin        if(zx5ab5f) begin           wjc9655 <= fp8b56b + 4'h1;        end        else begin           wjc9655 <= 4'h0;        end      end   end   always @ (fp8b56b) begin      ic59565 = (fp8b56b == 4'h3) ? 1'b1 : 1'b0;   end
+     always @ (posedge txmac_clk or negedge zxc8e70) begin      if(!zxc8e70) begin         lsa86c9 <= 0;         ic4364b <= 0;         ri1b259 <= 0;         ph193ac <= 0;      end      else if (txmac_clk_en) begin         lsa86c9 <= pf5039b;         ic4364b <= hoca073;         ri1b259 <= kd6045a;         ph193ac <= yz22d5;      end    end 
+   always @ (posedge txmac_clk or negedge zxc8e70) begin      if(!zxc8e70) begin         ux29585 = 0;      end      else if (txmac_clk_en) begin        if(tu48266 && ww4964f) begin           ux29585 = 1;        end        else if(uka636d || ykfa7f9) begin           ux29585 = 0;        end      end   end
+   always @ (posedge txmac_clk or negedge zxc8e70) begin      if(!zxc8e70) begin         qt652b0 = 0;      end      else if (txmac_clk_en) begin        if(tu48266 && psc5379) begin           qt652b0 = 1;        end        else if(uka636d || ykfa7f9) begin           qt652b0 = 0;        end      end   end
+
+
+
+
+always@* begin ayf04ca<=vv746d9[0];ym82650<=vv746d9[1];rv13281<=vv746d9[2];pu9940e<=vv746d9[3];hoca073<=vv746d9[4];pf5039b<=vv746d9[5];twe6ff<={xy2fd1e>>1,vv746d9[6]};tj9bfdb<={dz7e8f3>>1,vv746d9[7]};qgff6fb<={byf479e>>1,vv746d9[8]};fafb7d9<=vv746d9[9];uidbecb<=vv746d9[10];vidf659<=vv746d9[11];zkfb2ca<=vv746d9[12];qgcb29d<={off22b6>>1,vv746d9[13]};go594e9<=vv746d9[14];neca749<=vv746d9[15];ym9d259<={me56d7c>>1,vv746d9[16]};dze92c9<=vv746d9[17];ww4964f<=vv746d9[18];ic593c5<={jraf847>>1,vv746d9[19]};enc9e29<=vv746d9[20];rt4f14d<=vv746d9[21];os78a6f<=vv746d9[22];psc5379<=vv746d9[23];sj29bca<=vv746d9[24];jc4de54<=vv746d9[25];en6f2a3<=vv746d9[26];ic43a5b<={os7884d>>1,vv746d9[27]};oh1d2d8<={osc4269>>1,vv746d9[28]};qt54712<=vv746d9[29];ksa3895<=vv746d9[30];kde254f<={ph94fba>>1,vv746d9[31]};sj953e5<={mg3eeb3>>1,vv746d9[32]};xj4f968<={zzbacc5>>1,vv746d9[33]};ho7cb46<=vv746d9[34];kqe5a33<=vv746d9[35];vx2d198<=vv746d9[36];kq68cc7<=vv746d9[37];ww46638<=vv746d9[38];an331c1<=vv746d9[39];co98e0d<={osceb0e>>1,vv746d9[40]};fnc7068<={of75870>>1,vv746d9[41]};vx38347<=vv746d9[42];osc1a3e<=vv746d9[43];ohd1f1<=vv746d9[44];me68f8c<=vv746d9[45];ne47c60<=vv746d9[46];aa3e302<=vv746d9[47];hq8c08b<={zk4d8a8>>1,vv746d9[48]};kd6045a<=vv746d9[49];yz22d5<=vv746d9[50];pu116ad<=vv746d9[51];fp8b56b<={wjc9655>>1,vv746d9[52]};zx5ab5f<=vv746d9[53];jcd5aff<=vv746d9[54];doad7fa<={dmcab29>>1,vv746d9[55]};zx6bfd3<=vv746d9[56];th5fe9f<=vv746d9[57];meff4ff<=vv746d9[58];ykfa7f9<=vv746d9[59];shd3fc9<=vv746d9[60];cb9fe4d<=vv746d9[61];goff26d<=vv746d9[62];fnf9369<=vv746d9[63];shc9b4e<=vv746d9[64];xw4da75<={th710a3>>1,vv746d9[65]};kq6d3ab<={uk8851e>>1,vv746d9[66]};by69d59<={jc428f0>>1,vv746d9[67]};en4eaca<=vv746d9[68];mr75654<=vv746d9[69];sjab2a4<=vv746d9[70];end
+always@* begin wy2e8db[2047]<=dze6fa5;wy2e8db[2046]<=vx37d2f;wy2e8db[2044]<=mtbe97e;wy2e8db[2040]<=vif4bf4;wy2e8db[2033]<=rva5fa3;wy2e8db[2019]<=xy2fd1e[0];wy2e8db[1991]<=dz7e8f3[0];wy2e8db[1934]<=byf479e[0];wy2e8db[1929]<=oh95362;wy2e8db[1898]<=oh8adaf;wy2e8db[1821]<=gqa3cf2;wy2e8db[1810]<=zk4d8a8[0];wy2e8db[1749]<=me56d7c[0];wy2e8db[1707]<=jraf847[0];wy2e8db[1666]<=osc4269[0];wy2e8db[1630]<=of75870[0];wy2e8db[1617]<=th710a3[0];wy2e8db[1595]<=ri1e791;wy2e8db[1572]<=lsa86c9;wy2e8db[1506]<=ip4e764;wy2e8db[1450]<=ecb6be1;wy2e8db[1440]<=kdd3a99;wy2e8db[1428]<=sj2647d;wy2e8db[1384]<=ipc9d67;wy2e8db[1370]<=oh8fd3;wy2e8db[1366]<=tu7c23f;wy2e8db[1308]<=yma3c13;wy2e8db[1284]<=zx7eca7;wy2e8db[1212]<=ksac385;wy2e8db[1202]<=cobc75c;wy2e8db[1187]<=uk8851e[0];wy2e8db[1174]<=wyaca56;wy2e8db[1170]<=ic59565;wy2e8db[1142]<=tx_fifoavail;wy2e8db[1125]<=qv8675;wy2e8db[1097]<=ic4364b;wy2e8db[1041]<=ph94fba[0];wy2e8db[1023]<=wl3cdf4;wy2e8db[964]<=vi73b25;wy2e8db[949]<=nt915b5;wy2e8db[853]<=wj4eb3d;wy2e8db[833]<=os7884d[0];wy2e8db[815]<=osceb0e[0];wy2e8db[808]<=ep8fb3e;wy2e8db[753]<=ir29cec;wy2e8db[720]<=kqfa753;wy2e8db[714]<=yk59132;wy2e8db[692]<=sh70ee9;wy2e8db[685]<=zke11fa;wy2e8db[654]<=vk14782;wy2e8db[601]<=kf23de3;wy2e8db[587]<=fn5594a;wy2e8db[585]<=al4b2ac;wy2e8db[568]<=fc1e099;wy2e8db[562]<=th74219;wy2e8db[520]<=xjf653e;wy2e8db[474]<=off22b6[0];wy2e8db[407]<=xl19d61;wy2e8db[376]<=dz61c29;wy2e8db[357]<=ux7ac8;wy2e8db[327]<=jc428f0[0];wy2e8db[300]<=sj84dc;wy2e8db[293]<=dmcab29[0];wy2e8db[292]<=wjc9655[0];wy2e8db[281]<=mg2e843;wy2e8db[237]<=nt9e456;wy2e8db[203]<=cm433ac;wy2e8db[146]<=ri1b259;wy2e8db[140]<=byc5d08;wy2e8db[70]<=zzbacc5[0];wy2e8db[35]<=mg3eeb3[0];end         assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6<ksa36ce; dobd2d6=dobd2d6+1) begin dbc230[dobd2d6] = db84308[hq30de9]; hq86f4b = ^(hq30de9 & kf8c37[0]); hq30de9 = {hq30de9, hq86f4b}; end end 
+endmodule 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
+
+
+
+
+`timescale 1 ns / 100 ps
+module db3d84b ( wyb91ce,
+                 zxc8e70,
+                 txmac_clk_en,
+
+                 wl3cdf4,           
+                 dze6fa5,            
+                 tx_sndpausreq,      
+                 tx_sndpaustim,      
+                 psfe9c0,      
+                 tuf4e02,          
+                 th4059a,         
+                 gqa3cf2,     
+                 nec04d6,   
+                 qtd698d,    
+                 gq8db41,  
+                 ea6da09,
+                 kd41209,
+                 yk68241,
+                 tu48266,
+                 cz41332,  
+                 ay6d048,
+                 db9444a,
+                 ou9d4cd,
+                 pu99a40,
+                 tx_discfrm,
+                 ea53348,
+                 osce1dd,
+                 vx94e56,
+                 vka72b6,
+                 go56ec6,
+                 ep395b2,
+                 yzbb18b,         
+                 thd8c5d,          
+                 ecb6be1,    
+                 me56d7c,    
+                 oh8adaf,  
+                 tu7c23f,        
+                 zke11fa,        
+                 oh8fd3,          
+                 tx_statvec,         
+                 tx_staten,          
+                 tx_done,            
+                 ba9388f,       
+                 kdd3a99,      
+                 kqfa753      
+                 );
+parameter th4ae9a = 16;
+parameter vk895d3 = 8;
+parameter qi8774d = 4;
+parameter tjba6b2 = 14;
+parameter yxdc579 = 31;
+input                             wyb91ce;
+input                             zxc8e70;
+input                             txmac_clk_en;
+input                             wl3cdf4;
+input                             dze6fa5;
+input                             tx_sndpausreq;
+input [th4ae9a-1:0]           tx_sndpaustim;
+input                             psfe9c0;
+input                             tuf4e02;
+input [vk895d3-1:0]            th4059a;
+input                             gqa3cf2;
+input                             nec04d6;
+input                             qtd698d;
+input                             gq8db41;
+input                             ea6da09;
+input                             kd41209;
+input                             yk68241;
+input                             tu48266;
+input                             cz41332;
+input                             ay6d048;
+input                             db9444a;
+input                             ou9d4cd;
+input                             pu99a40;
+input                             tx_discfrm;
+input                             ea53348;
+input [qi8774d-1:0]           osce1dd;
+input                             vx94e56;
+input                             vka72b6;
+input                             go56ec6;
+input                             ep395b2;
+output                            yzbb18b;
+output                            thd8c5d;
+output                            ecb6be1;
+output [th4ae9a-1:0]          me56d7c;
+output                            oh8adaf;
+output                            tu7c23f;
+output                            zke11fa;
+output                            oh8fd3;
+output [yxdc579-1:0]        tx_statvec;
+output                            tx_staten;
+output                            tx_done;
+output                            ba9388f;
+output                            kdd3a99;
+output                            kqfa753;
+reg [yxdc579-1:0]           tx_statvec;
+reg                               ecb6be1;
+reg [th4ae9a-1:0]             me56d7c;
+reg                               oh8adaf;
+reg                               co9810d;
+reg [tjba6b2-1:0]             je434b;
+reg                               uk21a5a;
+reg [vk895d3-1:0]              zk69684;
+reg                               yzbb18b;
+reg                               thd8c5d;
+reg           fad08ee   ;
+reg           zz84772  ;
+reg           tx_done     ;
+reg           ba9388f;
+reg           neee5ac ;
+reg           ui72d62;
+reg           tx_staten   ;
+reg           ntb5883;
+reg           coac41f;
+reg           os620f9;
+reg           kqfa753;
+reg           xy83e41;
+reg           co1f20a;
+reg           fnf9050;
+reg           thc8286;
+reg           cz41436;
+reg           qia1b4;
+reg           jp50da1;
+reg           do86d0e;
+reg           an36872;
+reg           oh8fd3;
+reg           kdd3a99;
+reg           zke11fa;
+wire          tu7c23f = zke11fa;
+wire          epa48c6;
+wire          wy24634 = &th4059a;
+wire          qv18d0c = fnf9050 & thc8286 & cz41436                              & qia1b4 & jp50da1 & do86d0e;
+wire                          ng209f1 = ~(|je434b[13:6]);
+wire                       nt27c53 = kqfa753 | db9444a;
+wire [yxdc579-1:0]   kq53e55 = {ng209f1, osce1dd[3:0], vka72b6, vx94e56, go56ec6,                                              ep395b2, je434b[13:0], os620f9,                                              xy83e41 | an36872, kqfa753,                                              epa48c6, nt27c53,                                              qv18d0c, coac41f | co1f20a, ntb5883};
+wire iec4c = gq8db41 | ea6da09 | ay6d048;
+wire ay4c3c3 = iec4c & (~(|je434b[13:4]))              & ~je434b[3] & ~je434b[2] & ~je434b[1] &  je434b[0];
+wire mg31165 = iec4c & (~(|je434b[13:4]))              & ~je434b[3] & ~je434b[2] &  je434b[1] & ~je434b[0];
+wire aaf97d = iec4c & (~(|je434b[13:4]))              & ~je434b[3] & ~je434b[2] &  je434b[1] &  je434b[0];
+wire kf18629 = iec4c & (~(|je434b[13:4]))              & ~je434b[3] &  je434b[2] & ~je434b[1] & ~je434b[0];
+wire lq6c518 = iec4c & (~(|je434b[13:4]))              & ~je434b[3] &  je434b[2] & ~je434b[1] &  je434b[0];
+wire eacb16f = iec4c & (~(|je434b[13:4]))              & ~je434b[3] &  je434b[2] &  je434b[1] & ~je434b[0];
+wire ww53d13 = iec4c & (~(|je434b[13:4]))              &  je434b[3] &  je434b[2] &  je434b[1] & ~je434b[0];
+wire of7a593 = ~os620f9 & ((|je434b[13:11]) | (&je434b[10:9]) |                        (je434b[10] & je434b[8] & (&je434b[7:5]) &                         (je434b[4] | (&je434b[3:0]))));
+wire bn9b02c = (|je434b[13:11]) | (&je434b[10:9]) |                         (je434b[10] & je434b[8] & (&je434b[7:4]) &                          ((|je434b[3:2]) | (&je434b[1:0])));
+reg ayf04ca;
+reg ym82650;
+reg ps63f64;
+reg [th4ae9a - 1 : 0] uvfd919;
+reg nrec8cd;
+reg xj6466e;
+reg [vk895d3 - 1 : 0] db19bbc;
+reg fafb7d9;
+reg ld6ef37;
+reg ic779bf;
+reg ksbcdf8;
+reg lde6fc1;
+reg hd37e0f;
+reg fpbf07e;
+reg wjf83f7;
+reg wwc1fbc;
+reg ymfde1;
+reg rt7ef08;
+reg kdf7846;
+reg aabc234;
+reg dme11a0;
+reg ux8d03;
+reg [qi8774d - 1 : 0] zz28768;
+reg pha0740;
+reg nt3a07;
+reg cb1d03e;
+reg ipe81f5;
+reg nr40fad;
+reg [tjba6b2 - 1 : 0] wy3eb7c;
+reg wwf5be0;
+reg [vk895d3 - 1 : 0] yx6f80a;
+reg jc7c055;
+reg wwe02aa;
+reg pu1551;
+reg qiaa8a;
+reg fn55450;
+reg dbaa287;
+reg uv5143e;
+reg sj8a1f5;
+reg zx50fad;
+reg aa87d6e;
+reg aa3eb70;
+reg cmf5b80;
+reg twadc01;
+reg th6e00a;
+reg sh70056;
+reg oh802b4;
+reg je15a4;
+reg ukad22;
+reg ic56910;
+reg anb4881;
+reg epa440d;
+reg [yxdc579 - 1 : 0] ou1036e;
+reg xl81b71;
+reg irdb8f;
+reg ui6dc7d;
+reg bl6e3e8;
+reg fn71f46;
+reg sj8fa37;
+reg su7d1bc;
+reg she8de0;
+reg ic46f04;
+reg ph37820;
+reg [2047:0] wy2e8db;
+wire [62:0] vv746d9;
+
+localparam ksa36ce = 63,tw1b670 = 32'hfdffd14b;
+localparam [31:0] icdb382 = tw1b670;
+localparam mece084 = tw1b670 & 4'hf;
+localparam [11:0] ou8210c = 'h7ff;
+wire [(1 << mece084) -1:0] db84308;
+reg [ksa36ce-1:0] dbc230;
+reg [mece084-1:0] kf8c37 [0:1];
+reg [mece084-1:0] hq30de9;
+reg hq86f4b;
+integer hd37a5a;
+integer dobd2d6;
+
+   
+      always @ (posedge wyb91ce or negedge zxc8e70) begin      if(!zxc8e70) begin         fad08ee <= 1'b0;         zz84772 <= 1'b0;         tx_done <= 1'b0;         ba9388f <= 1'b0;         neee5ac <= 1'b0;         ui72d62 <= 1'b0;         tx_staten <= 1'b0;      end      else if (txmac_clk_en) begin         tx_done <= wwe02aa;         zz84772 <= jc7c055;         fad08ee <= aabc234;         ba9388f <= dme11a0;         tx_staten <= qiaa8a;         ui72d62 <= pu1551;         neee5ac <= ux8d03;      end    end       always @ (posedge wyb91ce or negedge zxc8e70) begin      if(!zxc8e70) begin         oh8adaf <= 1'b0;      end      else if (txmac_clk_en) begin         if(xj6466e) begin            oh8adaf <= 1'b0;         end         else if(nr40fad) begin            oh8adaf <= nr40fad;         end      end   end   always @ (posedge wyb91ce or negedge zxc8e70) begin      if(!zxc8e70) begin        je434b <= 14'd0;        oh8fd3 <= 0;        kdd3a99 <= 0;        zke11fa <= 1;      end      else if (txmac_clk_en) begin if (wy3eb7c[13:0] == 14'd58) begin    oh8fd3 <= 1; end else begin    oh8fd3 <= 0;         end if (wy3eb7c[13:0] == 14'd63) begin    kdd3a99 <= 1; end else begin    kdd3a99 <= 0;         end if (oh8fd3 == 1) begin    zke11fa <= 0;         end if(hd37e0f) begin            je434b <= wy3eb7c + 14'd4;         end else if(ksbcdf8 || wwc1fbc || fpbf07e || ymfde1        || lde6fc1) begin            je434b <= wy3eb7c + 14'd1;         end else if(ic779bf || wjf83f7) begin            je434b <= 14'd0;    zke11fa <= 1;         end      end   end       always @ (posedge wyb91ce or negedge zxc8e70) begin      if(!zxc8e70) begin         ntb5883 <= 1'b0;         coac41f <= 1'b0;      end      else if (txmac_clk_en) begin         if (irdb8f) begin            if(db19bbc[0]) begin               ntb5883 <= 1'b0;               coac41f <= 1'b1;            end            else begin               ntb5883 <= 1'b1;               coac41f <= 1'b0;            end         end         else if(ic779bf) begin            ntb5883 <= 1'b0;            coac41f <= 1'b0;         end      end   end      always @ (posedge wyb91ce or negedge zxc8e70) begin      if(!zxc8e70)        fnf9050 <= 1'b0;      else if (txmac_clk_en) begin         if (irdb8f) begin            if(ukad22)              fnf9050 <= 1'b1;            else              fnf9050 <= 1'b0;         end         else if(ic779bf)           fnf9050 <= 1'b0;      end   end      always @ (posedge wyb91ce or negedge zxc8e70) begin      if(!zxc8e70)        thc8286 <= 1'b0;      else if (txmac_clk_en) begin         if (ui6dc7d) begin            if(ukad22)              thc8286 <= 1'b1;            else              thc8286 <= 1'b0;         end         else if(ic779bf)           thc8286 <= 1'b0;      end   end      always @ (posedge wyb91ce or negedge zxc8e70) begin      if(!zxc8e70)        cz41436 <= 1'b0;      else if (txmac_clk_en) begin         if (bl6e3e8) begin            if(ukad22)              cz41436 <= 1'b1;            else              cz41436 <= 1'b0;         end         else if(ic779bf)           cz41436 <= 1'b0;      end   end      always @ (posedge wyb91ce or negedge zxc8e70) begin      if(!zxc8e70)        qia1b4 <= 1'b0;      else if (txmac_clk_en) begin         if (fn71f46) begin            if(ukad22)              qia1b4 <= 1'b1;            else              qia1b4 <= 1'b0;         end         else if(ic779bf)           qia1b4 <= 1'b0;      end   end      always @ (posedge wyb91ce or negedge zxc8e70) begin      if(!zxc8e70)        jp50da1 <= 1'b0;      else if (txmac_clk_en) begin         if (sj8fa37) begin            if(ukad22)              jp50da1 <= 1'b1;            else              jp50da1 <= 1'b0;         end         else if(ic779bf)           jp50da1 <= 1'b0;      end   end      always @ (posedge wyb91ce or negedge zxc8e70) begin      if(!zxc8e70)        do86d0e <= 1'b0;      else if (txmac_clk_en) begin         if (su7d1bc) begin            if(ukad22)              do86d0e <= 1'b1;            else              do86d0e <= 1'b0;         end         else if(ic779bf)           do86d0e <= 1'b0;      end   end      always @ (posedge wyb91ce or negedge zxc8e70) begin      if(!zxc8e70) begin         os620f9 <= 1'b0;         an36872 <= 1'b0;      end      else if (txmac_clk_en) begin         if(she8de0) begin            if ((yx6f80a == 8'h81)         && (db19bbc == 8'h00)) begin               os620f9 <= 1'b1;               an36872 <= 1'b0;            end            else if ((yx6f80a == 8'h88)         && (db19bbc == 8'h08)) begin               os620f9 <= 1'b0;               an36872 <= 1'b1;            end            else begin               os620f9 <= 1'b0;               an36872 <= 1'b0;            end         end         else if(ic779bf) begin            os620f9 <= 1'b0;            an36872 <= 1'b0;         end      end   end      
+   assign epa48c6 = ic46f04 | ph37820;
+      always @ (posedge wyb91ce or negedge zxc8e70) begin     if(!zxc8e70)       kqfa753 <= 1'b0;     else if (txmac_clk_en) begin        if(ksbcdf8 && ld6ef37 && !(wwf5be0 || fafb7d9)) begin          kqfa753 <= 1'b1;        end        else if(ic779bf)          kqfa753 <= 1'b0;     end   end      always @ (posedge wyb91ce or negedge zxc8e70) begin      if(!zxc8e70)        xy83e41 <= 1'b0;      else if (txmac_clk_en) begin         if(ymfde1)            xy83e41 <= 1'b1;         else if(ic779bf)           xy83e41 <= 1'b0 ;      end   end   always @ (posedge wyb91ce or negedge zxc8e70) begin      if(!zxc8e70)        co1f20a <= 1'b0;      else if (txmac_clk_en) begin         if (fpbf07e || hd37e0f) begin            co1f20a <= sj8a1f5;         end      end   end 
+      always @ (posedge wyb91ce or negedge zxc8e70) begin      if(!zxc8e70) begin         yzbb18b <= 1'b0;         thd8c5d <= 1'b0;         co9810d <= 1'b0;         tx_statvec <= 31'd0;      end      else if (txmac_clk_en) begin         yzbb18b <= ayf04ca;         thd8c5d <= ym82650;         co9810d <= nrec8cd; if (ux8d03 == 1) begin            tx_statvec <= ou1036e; end      end   end      always @ (posedge wyb91ce or negedge zxc8e70) begin      if(!zxc8e70) begin        uk21a5a <= 0;        zk69684 <= 0;      end      else if (txmac_clk_en) begin zk69684 <= db19bbc;         if(kdf7846) begin            uk21a5a <= fafb7d9;         end      end   end      always @ (posedge wyb91ce or negedge zxc8e70) begin      if(!zxc8e70) begin         ecb6be1 <= 1'b0;         me56d7c <= 16'h0000;      end      else if (txmac_clk_en) begin         if(ymfde1)            ecb6be1 <= 1'b0;         else if(ps63f64) begin            ecb6be1 <= ps63f64;            me56d7c <= uvfd919;         end      end   end
+always@* begin ayf04ca<=vv746d9[0];ym82650<=vv746d9[1];ps63f64<=vv746d9[2];uvfd919<={tx_sndpaustim>>1,vv746d9[3]};nrec8cd<=vv746d9[4];xj6466e<=vv746d9[5];db19bbc<={th4059a>>1,vv746d9[6]};fafb7d9<=vv746d9[7];ld6ef37<=vv746d9[8];ic779bf<=vv746d9[9];ksbcdf8<=vv746d9[10];lde6fc1<=vv746d9[11];hd37e0f<=vv746d9[12];fpbf07e<=vv746d9[13];wjf83f7<=vv746d9[14];wwc1fbc<=vv746d9[15];ymfde1<=vv746d9[16];rt7ef08<=vv746d9[17];kdf7846<=vv746d9[18];aabc234<=vv746d9[19];dme11a0<=vv746d9[20];ux8d03<=vv746d9[21];zz28768<={osce1dd>>1,vv746d9[22]};pha0740<=vv746d9[23];nt3a07<=vv746d9[24];cb1d03e<=vv746d9[25];ipe81f5<=vv746d9[26];nr40fad<=vv746d9[27];wy3eb7c<={je434b>>1,vv746d9[28]};wwf5be0<=vv746d9[29];yx6f80a<={zk69684>>1,vv746d9[30]};jc7c055<=vv746d9[31];wwe02aa<=vv746d9[32];pu1551<=vv746d9[33];qiaa8a<=vv746d9[34];fn55450<=vv746d9[35];dbaa287<=vv746d9[36];uv5143e<=vv746d9[37];sj8a1f5<=vv746d9[38];zx50fad<=vv746d9[39];aa87d6e<=vv746d9[40];aa3eb70<=vv746d9[41];cmf5b80<=vv746d9[42];twadc01<=vv746d9[43];th6e00a<=vv746d9[44];sh70056<=vv746d9[45];oh802b4<=vv746d9[46];je15a4<=vv746d9[47];ukad22<=vv746d9[48];ic56910<=vv746d9[49];anb4881<=vv746d9[50];epa440d<=vv746d9[51];ou1036e<={kq53e55>>1,vv746d9[52]};xl81b71<=vv746d9[53];irdb8f<=vv746d9[54];ui6dc7d<=vv746d9[55];bl6e3e8<=vv746d9[56];fn71f46<=vv746d9[57];sj8fa37<=vv746d9[58];su7d1bc<=vv746d9[59];she8de0<=vv746d9[60];ic46f04<=vv746d9[61];ph37820<=vv746d9[62];end
+always@* begin wy2e8db[2047]<=dze6fa5;wy2e8db[2046]<=tx_sndpausreq;wy2e8db[2044]<=tx_sndpaustim[0];wy2e8db[2040]<=psfe9c0;wy2e8db[2033]<=tuf4e02;wy2e8db[2019]<=th4059a[0];wy2e8db[1994]<=cz41436;wy2e8db[1990]<=gqa3cf2;wy2e8db[1981]<=co9810d;wy2e8db[1965]<=zz84772;wy2e8db[1940]<=qia1b4;wy2e8db[1939]<=ou9d4cd;wy2e8db[1933]<=nec04d6;wy2e8db[1914]<=je434b[0];wy2e8db[1883]<=neee5ac;wy2e8db[1832]<=jp50da1;wy2e8db[1831]<=pu99a40;wy2e8db[1819]<=qtd698d;wy2e8db[1785]<=co1f20a;wy2e8db[1781]<=uk21a5a;wy2e8db[1778]<=cz41332;wy2e8db[1740]<=kf18629;wy2e8db[1719]<=ui72d62;wy2e8db[1634]<=ww53d13;wy2e8db[1616]<=do86d0e;wy2e8db[1615]<=tx_discfrm;wy2e8db[1591]<=gq8db41;wy2e8db[1522]<=fnf9050;wy2e8db[1515]<=zk69684[0];wy2e8db[1508]<=ay6d048;wy2e8db[1470]<=os620f9;wy2e8db[1432]<=lq6c518;wy2e8db[1391]<=ntb5883;wy2e8db[1286]<=qv18d0c;wy2e8db[1271]<=vka72b6;wy2e8db[1221]<=of7a593;wy2e8db[1184]<=an36872;wy2e8db[1182]<=ea53348;wy2e8db[1135]<=ea6da09;wy2e8db[1051]<=nt27c53;wy2e8db[1023]<=wl3cdf4;wy2e8db[997]<=thc8286;wy2e8db[990]<=ep395b2;wy2e8db[982]<=fad08ee;wy2e8db[969]<=db9444a;wy2e8db[892]<=xy83e41;wy2e8db[889]<=tu48266;wy2e8db[870]<=aaf97d;wy2e8db[817]<=eacb16f;wy2e8db[735]<=coac41f;wy2e8db[643]<=wy24634;wy2e8db[635]<=vx94e56;wy2e8db[525]<=ng209f1;wy2e8db[495]<=go56ec6;wy2e8db[444]<=yk68241;wy2e8db[435]<=mg31165;wy2e8db[394]<=bn9b02c;wy2e8db[321]<=epa48c6;wy2e8db[317]<=osce1dd[0];wy2e8db[222]<=kd41209;wy2e8db[217]<=ay4c3c3;wy2e8db[108]<=iec4c;wy2e8db[54]<=kq53e55[0];end         assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6<ksa36ce; dobd2d6=dobd2d6+1) begin dbc230[dobd2d6] = db84308[hq30de9]; hq86f4b = ^(hq30de9 & kf8c37[0]); hq30de9 = {hq30de9, hq86f4b}; end end 
+endmodule 
+
+
+
+
+
+
+
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+
+
+
+`timescale 1 ns / 100 ps
+module bl5a944 ( wyb91ce,
+                    zxc8e70,
+                    txmac_clk_en,
+                    qt44e3e,   
+                    fp271f5,   
+                    hd38fae,   
+                    tuf4e02    
+                   );
+parameter th4ae9a = 16;
+input                   wyb91ce;
+input                   zxc8e70;
+input                   txmac_clk_en;
+input                   qt44e3e;
+input                   fp271f5;
+input [th4ae9a-1:0] hd38fae;
+output                  tuf4e02;
+reg [th4ae9a-1:0]   zz28f06;
+reg [5:0]               ne47836;
+reg       os7884d;
+reg       osc4269;
+reg       tuf4e02;
+reg       gd36506;
+parameter jr9a41 = 1'b0;
+parameter dm4d20f = 1'b1;
+reg lfa0d57;
+reg db6abe;
+reg [th4ae9a - 1 : 0] tjaafb2;
+reg [th4ae9a - 1 : 0] anbecbb;
+reg [5 : 0] fnf65dc;
+reg ic43a5b;
+reg oh1d2d8;
+reg qvbb9d0;
+reg [2047:0] wy2e8db;
+wire [7:0] vv746d9;
+
+localparam ksa36ce = 8,tw1b670 = 32'hfdffd48b;
+localparam [31:0] icdb382 = tw1b670;
+localparam mece084 = tw1b670 & 4'hf;
+localparam [11:0] ou8210c = 'h7ff;
+wire [(1 << mece084) -1:0] db84308;
+reg [ksa36ce-1:0] dbc230;
+reg [mece084-1:0] kf8c37 [0:1];
+reg [mece084-1:0] hq30de9;
+reg hq86f4b;
+integer hd37a5a;
+integer dobd2d6;
+
+   always @ (posedge wyb91ce or negedge zxc8e70) begin      if(!zxc8e70) begin        os7884d <= jr9a41;      end      else if (txmac_clk_en) begin        os7884d <= oh1d2d8;      end   end            always @ (ic43a5b or lfa0d57 or tuf4e02) begin      case(ic43a5b)        jr9a41: begin           if(lfa0d57) begin              osc4269 = dm4d20f;           end           else begin              osc4269 = jr9a41;           end         end        dm4d20f: begin           if(tuf4e02) begin              osc4269 = jr9a41;           end           else begin              osc4269 = dm4d20f;           end        end      endcase    end       always @ (posedge wyb91ce or negedge zxc8e70) begin      if (!zxc8e70) begin         zz28f06 <= 0;         tuf4e02 <= 0;      end      else if (txmac_clk_en) begin if (db6abe == 1) begin            zz28f06 <= tjaafb2; end else if(ic43a5b == dm4d20f) begin    if (qvbb9d0 == 1) begin               zz28f06 <= anbecbb - 1;            end         end else begin            zz28f06 <= tjaafb2; end         if (anbecbb == 0) begin            tuf4e02 <= 1;         end else begin            tuf4e02 <= 0;         end      end   end      always @ (posedge wyb91ce or negedge zxc8e70) begin      if (!zxc8e70) begin         ne47836 <= 0;         gd36506 <= 0;      end      else if (txmac_clk_en) begin if (lfa0d57 && !db6abe) begin            ne47836 <= fnf65dc + 1;         end else begin            ne47836 <= 0; end if ((fnf65dc == 6'h3e) && (!db6abe)) begin            gd36506 <= 1;         end else begin            gd36506 <= 0; end      end   end
+always@* begin lfa0d57<=vv746d9[0];db6abe<=vv746d9[1];tjaafb2<={hd38fae>>1,vv746d9[2]};anbecbb<={zz28f06>>1,vv746d9[3]};fnf65dc<={ne47836>>1,vv746d9[4]};ic43a5b<=vv746d9[5];oh1d2d8<=vv746d9[6];qvbb9d0<=vv746d9[7];end
+always@* begin wy2e8db[2047]<=fp271f5;wy2e8db[2046]<=hd38fae[0];wy2e8db[2044]<=zz28f06[0];wy2e8db[2040]<=ne47836[0];wy2e8db[2032]<=os7884d;wy2e8db[2017]<=osc4269;wy2e8db[1987]<=gd36506;wy2e8db[1023]<=qt44e3e;end         assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6<ksa36ce; dobd2d6=dobd2d6+1) begin dbc230[dobd2d6] = db84308[hq30de9]; hq86f4b = ^(hq30de9 & kf8c37[0]); hq30de9 = {hq30de9, hq86f4b}; end end 
+endmodule
+
+
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+
+
+
+`timescale 1 ns / 100 ps
+module nt81a8b (txmac_clk,
+                   zxc8e70,
+                   txmac_clk_en,
+                   tx_discfrm,
+                   tx_fifodata,        
+                   tx_fifoeof,         
+                   tx_fifoempty,       
+                   tx_fifoctrl,        
+                   tx_macread,         
+                   byf479e,    
+                   gqa3cf2,     
+                   nec04d6,   
+                   nt915b5,    
+                   ri1e791,    
+                   ou9d4cd         
+                   );
+parameter vk895d3 = 8;
+input                      txmac_clk;
+input                      zxc8e70;
+input                      txmac_clk_en;
+input                      tx_discfrm;
+input [vk895d3-1:0]     tx_fifodata;
+input                      tx_fifoeof;
+input                      tx_fifoempty;
+input                      tx_fifoctrl;
+output                     tx_macread;
+output [vk895d3-1:0]    byf479e;
+output                     gqa3cf2;
+output                     nec04d6;
+output                     nt915b5;
+output                     ri1e791;
+input                      ou9d4cd;
+reg [vk895d3+2:0]       yz36b29;
+reg [vk895d3+2:0]       mgaca67;
+reg [vk895d3+2:0]       ep299c5;
+reg [vk895d3+2:0]       ic67161;
+reg [vk895d3+2:0]       vic5847;
+reg [vk895d3+2:0]       pf611dd;
+reg [vk895d3+2:0]       by4777d;
+reg [vk895d3+2:0]       xjddf58;
+reg [vk895d3+2:0]       go7d631;
+reg [vk895d3+2:0]       ne58c42;
+reg [vk895d3+2:0]       mg31095;
+reg [vk895d3+2:0]       dm42540;
+reg [vk895d3+2:0]       ux9501d;
+reg [vk895d3+2:0]       hb4076b;
+reg [vk895d3+2:0]       gd1daf6;
+reg                        kded7b4;
+reg                        dz6bda5;
+wire [vk895d3-1:0]      byf479e;
+wire                       tx_macread;
+wire                       gqa3cf2;
+wire                       nec04d6;
+wire                       nt915b5;
+wire                       ri1e791;
+reg dme11a0;
+reg [vk895d3 - 1 : 0] zk732ec;
+reg vk99763;
+reg cmcbb1b;
+reg vi5d8d8;
+reg kdf7846;
+reg [vk895d3 + 2 : 0] vk1b0ba;
+reg [vk895d3 + 2 : 0] blc2e97;
+reg [vk895d3 + 2 : 0] ntba5f4;
+reg [vk895d3 + 2 : 0] gq97d3f;
+reg [vk895d3 + 2 : 0] faf4fcc;
+reg [vk895d3 + 2 : 0] ba3f31b;
+reg [vk895d3 + 2 : 0] ofcc6df;
+reg [vk895d3 + 2 : 0] ri1b7e2;
+reg [vk895d3 + 2 : 0] fadf891;
+reg [vk895d3 + 2 : 0] ipe245e;
+reg [vk895d3 + 2 : 0] rv917a4;
+reg [vk895d3 + 2 : 0] sh5e93e;
+reg [vk895d3 + 2 : 0] sja4fab;
+reg [vk895d3 + 2 : 0] ym3eae7;
+reg [vk895d3 + 2 : 0] sjab9c0;
+reg me5ce05;
+reg gbe7028;
+reg [2047:0] wy2e8db;
+wire [22:0] vv746d9;
+
+localparam ksa36ce = 23,tw1b670 = 32'hfdffd30b;
+localparam [31:0] icdb382 = tw1b670;
+localparam mece084 = tw1b670 & 4'hf;
+localparam [11:0] ou8210c = 'h7ff;
+wire [(1 << mece084) -1:0] db84308;
+reg [ksa36ce-1:0] dbc230;
+reg [mece084-1:0] kf8c37 [0:1];
+reg [mece084-1:0] hq30de9;
+reg hq86f4b;
+integer hd37a5a;
+integer dobd2d6;
+
+assign tx_macread = me5ce05 & ~cmcbb1b;
+assign byf479e = vk1b0ba[vk895d3-1:0];
+assign gqa3cf2 = vk1b0ba[vk895d3];
+assign nec04d6 = ~(blc2e97[vk895d3+2] | sjab9c0[vk895d3+2]);
+assign nt915b5 = vk1b0ba[vk895d3+1];
+assign ri1e791 = vk1b0ba[vk895d3+2];
+always @ (vk1b0ba or blc2e97 or ntba5f4 or gq97d3f or faf4fcc          or ba3f31b or ofcc6df or sjab9c0 or kdf7846) begin      casex ({ofcc6df[vk895d3+2],ba3f31b[vk895d3+2],      faf4fcc[vk895d3+2],gq97d3f[vk895d3+2],      ntba5f4[vk895d3+2],blc2e97[vk895d3+2],      vk1b0ba[vk895d3+2],kdf7846})         8'bxxxxxx0x,         8'bxxxxx011: begin             xjddf58 = sjab9c0;             go7d631 = ntba5f4;             ne58c42 = gq97d3f;             mg31095 = faf4fcc;             dm42540 = ba3f31b;             ux9501d = ofcc6df;             hb4076b = 11'h000; end         8'bxxxxx010,         8'bxxxx0111: begin             xjddf58 = blc2e97;             go7d631 = sjab9c0;             ne58c42 = gq97d3f;             mg31095 = faf4fcc;             dm42540 = ba3f31b;             ux9501d = ofcc6df;             hb4076b = 11'h000; end         8'bxxxx0110,         8'bxxx01111: begin             xjddf58 = blc2e97;             go7d631 = ntba5f4;             ne58c42 = sjab9c0;             mg31095 = faf4fcc;             dm42540 = ba3f31b;             ux9501d = ofcc6df;             hb4076b = 11'h000; end         8'bxxx01110,         8'bxx011111: begin             xjddf58 = blc2e97;             go7d631 = ntba5f4;             ne58c42 = gq97d3f;             mg31095 = sjab9c0;             dm42540 = ba3f31b;             ux9501d = ofcc6df;             hb4076b = 11'h000; end         8'bxx011110,         8'bx0111111: begin             xjddf58 = blc2e97;             go7d631 = ntba5f4;             ne58c42 = gq97d3f;             mg31095 = faf4fcc;             dm42540 = sjab9c0;             ux9501d = ofcc6df;             hb4076b = 11'h000; end         8'bx0111110,         8'b01111111: begin             xjddf58 = blc2e97;             go7d631 = ntba5f4;             ne58c42 = gq97d3f;             mg31095 = faf4fcc;             dm42540 = ba3f31b;             ux9501d = sjab9c0;             hb4076b = 11'h000; end         8'bx1111110,         8'b11111111: begin             xjddf58 = blc2e97;             go7d631 = ntba5f4;             ne58c42 = gq97d3f;             mg31095 = faf4fcc;             dm42540 = ba3f31b;             ux9501d = ofcc6df;             hb4076b = sjab9c0; end      endcase
+end      always @ (posedge txmac_clk or negedge zxc8e70) begin      if(!zxc8e70) begin         yz36b29 <=  11'h000;         mgaca67 <=  11'h000;         ep299c5 <=  11'h000;         ic67161 <=  11'h000;         vic5847 <=  11'h000;         pf611dd <=  11'h000;         by4777d <=  11'h000;         gd1daf6 <=  11'h000;         kded7b4   <=  0;         dz6bda5   <=  0;      end      else if (txmac_clk_en) begin         gd1daf6 <= {gbe7028, vi5d8d8, vk99763, zk732ec}; if ((vk1b0ba[vk895d3+2] == 0) || (kdf7846 == 1)) begin            yz36b29 <=  ri1b7e2; end if ((blc2e97[vk895d3+2] == 0) || (kdf7846 == 1)) begin            mgaca67 <=  fadf891; end if ((ntba5f4[vk895d3+2] == 0) || (kdf7846 == 1)) begin            ep299c5 <=  ipe245e; end if ((gq97d3f[vk895d3+2] == 0) || (kdf7846 == 1)) begin            ic67161 <=  rv917a4; end if ((faf4fcc[vk895d3+2] == 0) || (kdf7846 == 1)) begin            vic5847 <=  sh5e93e; end if ((ba3f31b[vk895d3+2] == 0) || (kdf7846 == 1)) begin            pf611dd <=  sja4fab; end if ((ofcc6df[vk895d3+2] == 0) || (kdf7846 == 1)) begin            by4777d <=  ym3eae7; end case (me5ce05)    1: begin       if ((gq97d3f[vk895d3+2] == 1)           || (faf4fcc[vk895d3+2] == 1)           || (ba3f31b[vk895d3+2] == 1)   || (ofcc6df[vk895d3+2] == 1)) begin  kded7b4 <= 0;       end    end    0: begin       if ((faf4fcc[vk895d3+2] == 0)           && (ba3f31b[vk895d3+2] == 0)           && (ofcc6df[vk895d3+2] == 0)) begin  kded7b4 <= 1;       end    end endcase dz6bda5 <= tx_macread; if (dme11a0 == 1) begin    gd1daf6[vk895d3+2] <= 0;    by4777d[vk895d3+2] <= 0;    pf611dd[vk895d3+2] <= 0;    vic5847[vk895d3+2] <= 0;    ic67161[vk895d3+2] <= 0;    ep299c5[vk895d3+2] <= 0;    mgaca67[vk895d3+2] <= 0;    yz36b29[vk895d3+2] <= 0;    dz6bda5 <= 0;    kded7b4 <= 0; end      end   end
+always@* begin dme11a0<=vv746d9[0];zk732ec<={tx_fifodata>>1,vv746d9[1]};vk99763<=vv746d9[2];cmcbb1b<=vv746d9[3];vi5d8d8<=vv746d9[4];kdf7846<=vv746d9[5];vk1b0ba<={yz36b29>>1,vv746d9[6]};blc2e97<={mgaca67>>1,vv746d9[7]};ntba5f4<={ep299c5>>1,vv746d9[8]};gq97d3f<={ic67161>>1,vv746d9[9]};faf4fcc<={vic5847>>1,vv746d9[10]};ba3f31b<={pf611dd>>1,vv746d9[11]};ofcc6df<={by4777d>>1,vv746d9[12]};ri1b7e2<={xjddf58>>1,vv746d9[13]};fadf891<={go7d631>>1,vv746d9[14]};ipe245e<={ne58c42>>1,vv746d9[15]};rv917a4<={mg31095>>1,vv746d9[16]};sh5e93e<={dm42540>>1,vv746d9[17]};sja4fab<={ux9501d>>1,vv746d9[18]};ym3eae7<={hb4076b>>1,vv746d9[19]};sjab9c0<={gd1daf6>>1,vv746d9[20]};me5ce05<=vv746d9[21];gbe7028<=vv746d9[22];end
+always@* begin wy2e8db[2047]<=tx_fifodata[0];wy2e8db[2046]<=tx_fifoeof;wy2e8db[2044]<=tx_fifoempty;wy2e8db[2040]<=tx_fifoctrl;wy2e8db[2032]<=ou9d4cd;wy2e8db[2016]<=yz36b29[0];wy2e8db[1985]<=mgaca67[0];wy2e8db[1922]<=ep299c5[0];wy2e8db[1796]<=ic67161[0];wy2e8db[1544]<=vic5847[0];wy2e8db[1302]<=kded7b4;wy2e8db[1105]<=dm42540[0];wy2e8db[1041]<=pf611dd[0];wy2e8db[1023]<=tx_discfrm;wy2e8db[651]<=gd1daf6[0];wy2e8db[557]<=dz6bda5;wy2e8db[552]<=mg31095[0];wy2e8db[325]<=hb4076b[0];wy2e8db[276]<=ne58c42[0];wy2e8db[162]<=ux9501d[0];wy2e8db[138]<=go7d631[0];wy2e8db[69]<=xjddf58[0];wy2e8db[34]<=by4777d[0];end         assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6<ksa36ce; dobd2d6=dobd2d6+1) begin dbc230[dobd2d6] = db84308[hq30de9]; hq86f4b = ^(hq30de9 & kf8c37[0]); hq30de9 = {hq30de9, hq86f4b}; end end 
+endmodule 
+
+
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+
+
+
+
+
+`timescale 1 ns / 100 ps
+module xj7448a ( wyb91ce,
+                  zxc8e70,
+                  txmac_clk_en,
+
+                  yz8aca7,   
+                  os5653c,  
+                  rib29e0,     
+                  hd94f02,     
+
+                  nga7816,     
+                  wl3c0b3,     
+                  wwe059c       
+                  );
+parameter qv2ce1 = 6;
+input                        wyb91ce;
+input                        zxc8e70;
+input                        txmac_clk_en;
+input                        yz8aca7;
+input                        os5653c;
+input                        rib29e0;
+input                        hd94f02;
+output [qv2ce1-1:0] nga7816;
+output [qv2ce1-1:0] wl3c0b3;
+output                       wwe059c;
+reg [qv2ce1-1:0]    nga7816;
+reg [qv2ce1-1:0]    wl3c0b3;
+wire                         wwe059c = (nga7816 == wl3c0b3);
+reg yz90168;
+reg yz80b45;
+reg ou5a2d;
+reg ph2d169;
+reg [2047:0] wy2e8db;
+wire [3:0] vv746d9;
+
+localparam ksa36ce = 4,tw1b670 = 32'hfdffca8b;
+localparam [31:0] icdb382 = tw1b670;
+localparam mece084 = tw1b670 & 4'hf;
+localparam [11:0] ou8210c = 'h7ff;
+wire [(1 << mece084) -1:0] db84308;
+reg [ksa36ce-1:0] dbc230;
+reg [mece084-1:0] kf8c37 [0:1];
+reg [mece084-1:0] hq30de9;
+reg hq86f4b;
+integer hd37a5a;
+integer dobd2d6;
+
+      always @ (posedge wyb91ce or negedge zxc8e70) begin      if(!zxc8e70) begin         nga7816 <= 5'd0;      end      else if (txmac_clk_en) begin         if(yz90168 || yz80b45) begin            nga7816 <= 5'd0;         end         else if(ou5a2d) begin            nga7816 <= nga7816 + 5'd1;         end      end   end      always @ (posedge wyb91ce or negedge zxc8e70) begin      if(!zxc8e70) begin         wl3c0b3 <= 5'd0;      end      else if (txmac_clk_en) begin         if(yz90168) begin            wl3c0b3 <= 5'd0;         end         else if(ph2d169) begin            wl3c0b3 <= wl3c0b3 + 5'd1;         end      end   end
+always@* begin yz90168<=vv746d9[0];yz80b45<=vv746d9[1];ou5a2d<=vv746d9[2];ph2d169<=vv746d9[3];end
+always@* begin wy2e8db[2047]<=os5653c;wy2e8db[2046]<=rib29e0;wy2e8db[2044]<=hd94f02;wy2e8db[1023]<=yz8aca7;end         assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6<ksa36ce; dobd2d6=dobd2d6+1) begin dbc230[dobd2d6] = db84308[hq30de9]; hq86f4b = ^(hq30de9 & kf8c37[0]); hq30de9 = {hq30de9, hq86f4b}; end end 
+endmodule
+
+
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+
+
+
+`timescale 1 ns / 100 ps
+module wwc1ddb ( txmac_clk,
+                  zxc8e70,
+                  txmac_clk_en,
+
+                  
+                  wl3cdf4,         
+                  dze6fa5,          
+                  mtbe97e,        
+                  vx37d2f,          
+                  ou8d15c,           
+                  me68ae0,       
+                  dz7e8f3,    
+
+                  
+                  tx_fifodata,      
+                  tx_fifoeof,       
+                  tx_fifoempty,     
+                  tx_fifoavail,     
+                  tx_sndpaustim,    
+                  tx_sndpausreq,    
+                  tx_fifoctrl,      
+
+                  
+                  kq493c2,       
+                  go49e10,       
+
+                  
+                  rva5fa3,           
+                  vif4bf4,           
+
+                  
+                  xjc2078,          
+                  
+                  
+                  tx_macread,       
+                  tx_discfrm,       
+                  tx_staten,        
+                  tx_statvec,       
+                  tx_done,          
+
+                  
+                  fncd202,         
+                  tu69016,       
+                  vi480b3         
+                  );
+parameter pdevice_family = "XP2";
+parameter al759ec = 5;
+parameter lsa2257 = 48;
+parameter ba112ba = 16;
+parameter vk895d3 = 8;
+parameter th4ae9a = 16;
+parameter yxdc579 = 31;
+parameter by574d6 = 32;
+parameter tjba6b2 = 14;
+parameter qi8774d = 4;
+parameter qv2ce1 = 6;
+parameter qv9acbc = 22;
+parameter qtd65e5 = 13;
+parameter hqb2f2c = 13'd6072;
+parameter co97962 = 8'h55;
+parameter cobcb11 = 8'hd5;
+parameter wwe5889 = 8'h00;
+parameter mt2c448 = 8'h01;
+parameter qg62245 = 8'h80;
+parameter pu11228 = 8'hc2;
+parameter do89143 = 8'h00;
+parameter dm48a1a = 8'h00;
+parameter jp450d3 = 8'h01;
+parameter xl2869e = 8'h88;
+parameter ay434f7 = 8'h08;
+parameter ec1a7b9 = 8'h00;
+input                                 txmac_clk;
+input                                 zxc8e70;
+input                                 txmac_clk_en;
+input                                 wl3cdf4;
+input                                 dze6fa5;
+input                                 mtbe97e;
+input                                 vx37d2f;
+input [al759ec-1:0]                   ou8d15c;
+input [lsa2257-1:0]                   me68ae0;
+input [ba112ba-1:0]            dz7e8f3;
+input [vk895d3-1:0]                tx_fifodata;
+input                                 tx_fifoeof;
+input                                 tx_fifoempty;
+input                                 tx_fifoavail;
+input [th4ae9a-1:0]               tx_sndpaustim;
+input                                 tx_sndpausreq;
+input                                 tx_fifoctrl;
+input                                 kq493c2;
+input [th4ae9a-1:0]               go49e10;
+input                                 rva5fa3;
+input                                 vif4bf4;
+output                                xjc2078;
+output                                tx_macread;
+output                                tx_discfrm;
+output                                tx_staten;
+output [yxdc579-1:0]            tx_statvec;
+output                                tx_done;
+output                                fncd202;
+output [vk895d3-1:0]               tu69016;
+output                                vi480b3;
+wire [vk895d3-1:0]                 byf479e;
+wire [th4ae9a-1:0]                me56d7c;
+wire [by574d6-1:0]               jraf847;
+wire                                  tu7c23f;
+wire [vk895d3-1:0]                 th4059a;
+wire [vk895d3-1:0]                 tu69016;
+wire [vk895d3:0]                   off22b6;
+wire [qi8774d-1:0]                osce1dd;
+wire                                  qtd698d;
+wire                                  mtb4c6d;
+wire [qv2ce1-1:0]    czc621c;
+wire [qv2ce1-1:0]    co88728;
+wire    xjc2078 = qtd698d | mtb4c6d;
+reg vx28031;
+reg ayf04ca;
+reg ym82650;
+reg pu9940e;
+reg rv13281;
+reg [al759ec - 1 : 0] fn7e3cc;
+reg [lsa2257 - 1 : 0] qv8f33b;
+reg [ba112ba - 1 : 0] tj9bfdb;
+reg [vk895d3 - 1 : 0] zk732ec;
+reg vk99763;
+reg cmcbb1b;
+reg vidf659;
+reg [th4ae9a - 1 : 0] uvfd919;
+reg ps63f64;
+reg vi5d8d8;
+reg godbbe9;
+reg [th4ae9a - 1 : 0] cmefa4e;
+reg pf5039b;
+reg hoca073;
+reg [vk895d3 - 1 : 0] qgff6fb;
+reg [th4ae9a - 1 : 0] ym9d259;
+reg [by574d6 - 1 : 0] ic593c5;
+reg enc9e29;
+reg [vk895d3 - 1 : 0] db19bbc;
+reg [vk895d3 : 0] qgcb29d;
+reg [qi8774d - 1 : 0] zz28768;
+reg ic779bf;
+reg aab6476;
+reg [qv2ce1 - 1 : 0] db91d8b;
+reg [qv2ce1 - 1 : 0] zk762f6;
+reg [2047:0] wy2e8db;
+wire [29:0] vv746d9;
+
+
+
+
+
+
+
+
+
+
+localparam ksa36ce = 30,tw1b670 = 32'hfdffe30b;
+localparam [31:0] icdb382 = tw1b670;
+localparam mece084 = tw1b670 & 4'hf;
+localparam [11:0] ou8210c = 'h7ff;
+wire [(1 << mece084) -1:0] db84308;
+reg [ksa36ce-1:0] dbc230;
+reg [mece084-1:0] kf8c37 [0:1];
+reg [mece084-1:0] hq30de9;
+reg hq86f4b;
+integer hd37a5a;
+integer dobd2d6;
+
+nt81a8b       #(        .vk895d3(vk895d3)        )    bl6b460 (        .txmac_clk (txmac_clk),        .zxc8e70 (vx28031),        .txmac_clk_en (txmac_clk_en),        .tx_discfrm (ba9388f),        .tx_fifodata (zk732ec),        .tx_fifoeof (vk99763),        .tx_fifoempty (cmcbb1b),        .tx_fifoctrl (vi5d8d8),        .tx_macread (tx_macread),        .byf479e (byf479e),        .gqa3cf2 (gqa3cf2),        .nec04d6 (nec04d6),        .nt915b5 (nt915b5),        .ri1e791 (ri1e791),        .ou9d4cd (ou9d4cd)        );
+db3283c       #(        .lsa2257( lsa2257),        .ba112ba(ba112ba),        .vk895d3(vk895d3),        .th4ae9a(th4ae9a),      .by574d6(by574d6),        .tjba6b2(tjba6b2),        .qi8774d(qi8774d),        .qv9acbc(qv9acbc),        .qtd65e5(qtd65e5),        .hqb2f2c(hqb2f2c),        .co97962(co97962),        .cobcb11(cobcb11),        .wwe5889(wwe5889),        .mt2c448(mt2c448),        .qg62245(qg62245),        .pu11228(pu11228),        .do89143(do89143),        .dm48a1a(dm48a1a),        .jp450d3(jp450d3),        .xl2869e(xl2869e),        .ay434f7(ay434f7),        .ec1a7b9(ec1a7b9)        )    cz54dd6 (        .txmac_clk (txmac_clk),        .zxc8e70 (vx28031),        .txmac_clk_en (txmac_clk_en),        .wl3cdf4 (yzbb18b),        .dze6fa5 (thd8c5d),        .vx37d2f (rv13281),        .mtbe97e (pu9940e),        .vif4bf4 (hoca073),        .rva5fa3 (pf5039b),        .xy2fd1e (qv8f33b),        .dz7e8f3 (tj9bfdb),        .byf479e (qgff6fb),        .gqa3cf2 (gqa3cf2),        .ri1e791 (ri1e791),        .tx_fifoavail (vidf659),        .nt9e456 (nt9e456),        .off22b6 (qgcb29d),        .nt915b5 (nt915b5),        .oh8adaf (oh8adaf),        .me56d7c (ym9d259),        .ecb6be1 (ecb6be1),        .wj4eb3d (wj4eb3d),        .jraf847 (ic593c5),        .tu7c23f (enc9e29),        .zke11fa (zke11fa),        .oh8fd3 (oh8fd3),        .sh70ee9 (sh70ee9),        .ipc9d67 (ipc9d67),        .kdd3a99 (kdd3a99),        .kqfa753 (kqfa753),        .ou9d4cd (ou9d4cd),        .tx_discfrm (tx_discfrm),        .ea53348 (ea53348),        .pu99a40 (pu99a40),        .fncd202 (fncd202),        .tu69016 (tu69016),        .vi480b3 (vi480b3),        .th4059a (th4059a),        .yz2cd6 (yz2cd6),        .fp948c9 (fp948c9),        .ieb35a6 (ieb35a6),        .oh39c3b (oh39c3b),        .qtd698d (qtd698d),        .mtb4c6d (mtb4c6d),        .uka636d (uka636d),        .uk31b68 (uk31b68),        .gq8db41 (gq8db41),        .ea6da09 (ea6da09),        .ay6d048 (ay6d048),        .yk68241 (yk68241),        .kd41209 (kd41209),        .fp904c (fp904c),        .tu48266 (tu48266),        .cz41332 (cz41332),        .tj9994 (tj9994),        .ea4cca7 (ea4cca7),        .ps66539 (ps66539),        .osce1dd (osce1dd),        .vx94e56 (vx94e56),        .vka72b6 (vka72b6),        .ep395b2 (ep395b2),        .jccad94 (jccad94),        .yk56ca2 (yk56ca2),        .gd23275 (gd23275),        .ph193ac (ph193ac),        .db9444a (db9444a)        );
+
+db3d84b       #(        .th4ae9a(th4ae9a),        .vk895d3(vk895d3),        .qi8774d(qi8774d),        .tjba6b2(tjba6b2),        .yxdc579(yxdc579)        )    gd1dd3f (        .wyb91ce (txmac_clk),        .zxc8e70 (vx28031),        .txmac_clk_en (txmac_clk_en),
+        .wl3cdf4 (ayf04ca),        .dze6fa5 (ym82650),        .tx_sndpausreq (ps63f64),        .tx_sndpaustim (uvfd919),        .psfe9c0 (godbbe9),        .tuf4e02 (tuf4e02),        .tu48266 (tu48266),        .osce1dd (zz28768),        .vx94e56 (vx94e56),        .vka72b6 (vka72b6),        .go56ec6 (jccad94),        .ep395b2 (ep395b2),        .db9444a (db9444a),        .qtd698d (ic779bf),        .gq8db41 (gq8db41),        .cz41332 (cz41332),        .ea6da09 (ea6da09),        .kd41209 (kd41209),        .yk68241 (yk68241),        .ay6d048 (ay6d048),        .ou9d4cd (ou9d4cd),        .pu99a40 (pu99a40),        .tx_discfrm (tx_discfrm),        .ea53348 (ea53348),        .th4059a (db19bbc),        .gqa3cf2 (gqa3cf2),        .nec04d6 (nec04d6),        .yzbb18b (yzbb18b),        .thd8c5d (thd8c5d),        .ecb6be1 (ecb6be1),        .me56d7c (me56d7c),        .oh8adaf (oh8adaf),        .tu7c23f (tu7c23f),        .zke11fa (zke11fa),        .oh8fd3 (oh8fd3),        .tx_statvec (tx_statvec),        .tx_staten (tx_staten),        .tx_done (tx_done),        .ba9388f (ba9388f),        .kdd3a99 (kdd3a99),        .kqfa753 (kqfa753)        );
+fnd7239       #(        .qi8774d(qi8774d)      )    zxc2101 (  .wyb91ce (txmac_clk),        .zxc8e70 (vx28031),        .txmac_clk_en (txmac_clk_en),        .oh39c3b (oh39c3b),        .osce1dd (zz28768),        .sh70ee9 (sh70ee9)        );
+
+oha1c94       #(        .al759ec(al759ec)      )    riad63d (  .wyb91ce (txmac_clk),        .zxc8e70 (vx28031),        .txmac_clk_en (txmac_clk_en),        .yza464e (fn7e3cc),        .fp948c9 (fp948c9),        .gd23275 (gd23275),        .ph193ac (ph193ac),        .ipc9d67 (ipc9d67),        .wj4eb3d (wj4eb3d)        );
+bl5a944       #(        .th4ae9a(th4ae9a)        )    ux9f54e (        .wyb91ce (txmac_clk),        .zxc8e70 (vx28031),        .txmac_clk_en (txmac_clk_en),        .qt44e3e (ieb35a6),        .fp271f5 (godbbe9),        .hd38fae (cmefa4e),        .tuf4e02 (tuf4e02)        );
+th71cb9    dz6ed95 (   .ls2f153(jraf847),        .lq7c1c8 (db19bbc),        .mee0e42 (yz2cd6),        .rtc842c (ic779bf),        .lq42166 (32'hffffffff),        .ou10b33 (txmac_clk),        .ux2ccc5 (vx28031),        .txmac_clk_en (txmac_clk_en)        );   xj7448a       #(        .qv2ce1(qv2ce1)        )    qif27f ( .wyb91ce (txmac_clk),        .zxc8e70 (vx28031),        .txmac_clk_en (txmac_clk_en),        .yz8aca7 (ps66539),        .os5653c (yk56ca2),        .rib29e0 (tj9994),        .hd94f02 (ea4cca7),        .nga7816 (co88728),        .wl3c0b3 (czc621c),        .wwe059c (nt9e456)        );
+pmi_ram_dp  #(.pmi_wr_addr_depth(64),    .pmi_wr_addr_width(6),    .pmi_wr_data_width(9),    .pmi_rd_addr_depth(64),    .pmi_rd_addr_width(6),    .pmi_rd_data_width(9),    .pmi_regmode("noreg"),    .pmi_gsr("disable"),    .pmi_resetmode("sync"),    .pmi_init_file("none"),    .pmi_init_file_format("binary"),    .pmi_family(pdevice_family),    .module_type("pmi_ram_dp")    )
+tj32722   (.Data({gqa3cf2, byf479e}),                 .WrAddress(czc621c),                 .RdAddress(co88728),                 .WrClock(txmac_clk),                 .RdClock(txmac_clk),                 .WrClockEn(1'b1),                 .RdClockEn(txmac_clk_en),                 .WE(ea4cca7),                 .Reset(1'b0),                 .Q(off22b6)                 );
+
+   always@* begin vx28031<=vv746d9[0];ayf04ca<=vv746d9[1];ym82650<=vv746d9[2];pu9940e<=vv746d9[3];rv13281<=vv746d9[4];fn7e3cc<={ou8d15c>>1,vv746d9[5]};qv8f33b<={me68ae0>>1,vv746d9[6]};tj9bfdb<={dz7e8f3>>1,vv746d9[7]};zk732ec<={tx_fifodata>>1,vv746d9[8]};vk99763<=vv746d9[9];cmcbb1b<=vv746d9[10];vidf659<=vv746d9[11];uvfd919<={tx_sndpaustim>>1,vv746d9[12]};ps63f64<=vv746d9[13];vi5d8d8<=vv746d9[14];godbbe9<=vv746d9[15];cmefa4e<={go49e10>>1,vv746d9[16]};pf5039b<=vv746d9[17];hoca073<=vv746d9[18];qgff6fb<={byf479e>>1,vv746d9[19]};ym9d259<={me56d7c>>1,vv746d9[20]};ic593c5<={jraf847>>1,vv746d9[21]};enc9e29<=vv746d9[22];db19bbc<={th4059a>>1,vv746d9[23]};qgcb29d<={off22b6>>1,vv746d9[24]};zz28768<={osce1dd>>1,vv746d9[25]};ic779bf<=vv746d9[26];aab6476<=vv746d9[27];db91d8b<={czc621c>>1,vv746d9[28]};zk762f6<={co88728>>1,vv746d9[29]};end
+always@* begin wy2e8db[2047]<=wl3cdf4;wy2e8db[2046]<=dze6fa5;wy2e8db[2044]<=mtbe97e;wy2e8db[2040]<=vx37d2f;wy2e8db[2032]<=ou8d15c[0];wy2e8db[2016]<=me68ae0[0];wy2e8db[1985]<=dz7e8f3[0];wy2e8db[1922]<=tx_fifodata[0];wy2e8db[1796]<=tx_fifoeof;wy2e8db[1544]<=tx_fifoempty;wy2e8db[1316]<=mtb4c6d;wy2e8db[1169]<=co88728[0];wy2e8db[1106]<=th4059a[0];wy2e8db[1041]<=rva5fa3;wy2e8db[1040]<=tx_fifoavail;wy2e8db[1023]<=zxc8e70;wy2e8db[658]<=qtd698d;wy2e8db[584]<=czc621c[0];wy2e8db[553]<=tu7c23f;wy2e8db[520]<=go49e10[0];wy2e8db[329]<=osce1dd[0];wy2e8db[276]<=jraf847[0];wy2e8db[260]<=kq493c2;wy2e8db[164]<=off22b6[0];wy2e8db[138]<=me56d7c[0];wy2e8db[130]<=tx_fifoctrl;wy2e8db[69]<=byf479e[0];wy2e8db[65]<=tx_sndpausreq;wy2e8db[34]<=vif4bf4;wy2e8db[32]<=tx_sndpaustim[0];end         assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6<ksa36ce; dobd2d6=dobd2d6+1) begin dbc230[dobd2d6] = db84308[hq30de9]; hq86f4b = ^(hq30de9 & kf8c37[0]); hq30de9 = {hq30de9, hq86f4b}; end end 
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+`timescale 1 ns / 100 ps
+module wya61c7(
+    
+    hclk, 
+    reset_n, 
+
+    
+    haddr, 
+    hdatain, 
+    hread_n, 
+    hwrite_n, 
+    hcs_n, 
+
+    
+    hdataout, 
+    hready_n, 
+    hdataout_en_n, 
+
+    
+    tx_en, 
+    sjae511, 
+    ic7288c, 
+    ou8d15c, 
+
+    
+    ym2eb93, 
+    jcc5d72, 
+    pu8c1d2, 
+    kded62e, 
+    uic4515, 
+    xy3a4a5, 
+    ldd252b,
+    sw9295e,
+    db94af1,
+    jra578e,
+    ou2bc77,
+    ip5e3b9,
+    zkf1dcc, 
+    shf88a2, 
+    thddac5, 
+    dz6b175, 
+    tu58bae, 
+
+    
+    ep90e3c, 
+    ri1e263, 
+    tuf131a, 
+    vx37d2f,          
+
+    
+    dzc2191, 
+
+    
+    sw10140, 
+    cb80a01, 
+    ri99b0a, 
+    vvcd852, 
+    ba93361 
+);
+
+parameter ay787f5 = 8;
+
+parameter gq1fd44 = 8;
+parameter nefea21 = 15;
+parameter cmf510a = 15;
+parameter pua8850 = 15;
+parameter mr44282 = 8;
+parameter sw21414 = 3;
+parameter iea0a1 = 7;
+parameter xj50509 = 7;
+parameter ou8284f = 15;
+parameter je14278 = 10;
+parameter ira13c3 = 4;
+parameter jr9e1d = 10;
+parameter fn4f0ef = 15;
+parameter gq3e970 = 8;
+parameter yxc3bf8 = 47;
+input hclk;
+input reset_n;
+input [gq1fd44 - 1:0] haddr;
+input [ay787f5 - 1:0] hdatain;
+input hread_n;
+input hwrite_n;
+input hcs_n;
+output [ay787f5 - 1:0] hdataout;
+output hready_n;
+output hdataout_en_n;
+output  vx37d2f;
+output shf88a2;
+output thddac5;
+output [cmf510a-2:0] dz6b175;
+output tu58bae;
+output tx_en;
+output sjae511;
+output ic7288c;
+output [ira13c3:0] ou8d15c;
+input dzc2191;
+input ba93361;
+input [nefea21:0] sw10140;
+input cb80a01;
+input [gq3e970:0] ri99b0a;
+input vvcd852;
+output ym2eb93;
+output jcc5d72;
+output [yxc3bf8:0] ri1e263;
+output pu8c1d2;
+output kded62e;
+output uic4515;
+output tuf131a;
+output [xj50509:0] xy3a4a5;
+output [xj50509:0] ldd252b;
+output [xj50509:0] sw9295e;
+output [xj50509:0] db94af1;
+output [xj50509:0] jra578e;
+output [xj50509:0] ou2bc77;
+output [xj50509:0] ip5e3b9;
+output [xj50509:0] zkf1dcc;
+output [pua8850:0] ep90e3c;
+
+reg         qg56946;
+reg         mtb4a31;
+reg         xla518d;
+reg         zz28c6f;
+reg         [gq1fd44 - 1:0] wy31bf1;
+reg         [gq1fd44 - 1:0] en6fc49;
+reg         [gq1fd44 - 1:0] lqf126f;
+reg         [gq1fd44 - 1:0] yk49bd2;
+reg         [pua8850:0] ep90e3c;
+reg         hready_n;
+reg         [ay787f5 - 1:0] hdataout;
+reg         hdataout_en_n;
+reg         ui5cbbe;
+reg         [ay787f5 - 1:0] ou2ef80;
+reg         [ay787f5 - 1:0] wlbe008;
+reg         [ay787f5 - 1:0] an80228;
+reg         [ay787f5 - 1:0] kf8a22;
+reg         [ay787f5 - 1:0] db288ae;
+reg         [1:0]               uv44576;
+reg         hd22bb4;
+reg         [iea0a1:0] uxaed38;
+reg         [iea0a1:0] yzb4e2a;
+reg         [iea0a1:0] tj38aaa;
+reg         [iea0a1:0] zm2aaba;
+reg         [iea0a1:0] lfaae9f;
+reg         [iea0a1:0] fpba7fa;
+reg         [iea0a1:0] ir9febd;
+reg         [iea0a1:0] wwfaf69;
+reg         zxd7b48;
+reg         fcbda47;
+reg         [gq3e970:0] tu691dd;
+reg         [ira13c3:0] vi4775b;
+reg         [sw21414:0] dzdd6d8;
+reg         [mr44282:0] mr5b63a;
+reg         [cmf510a:0] vvd8ea0;
+reg         [ou8284f:0] ng3a837;
+reg         [ou8284f:0] fpa0dd1;
+reg         [ou8284f:0] hd37476;
+wire        [15:0] jrba3b7;
+reg         [nefea21:0] lf8edf8;
+reg         [nefea21:0] pub7e32;
+reg         rvbf192;
+reg         off8c97;
+reg         qtc64bd;
+reg         [ay787f5 - 1:0] qi92f6f;
+reg         ks97b79;
+reg         pubdbc9;
+
+
+
+
+
+
+
+
+
+
+reg [gq1fd44 - 1 : 0] rgd5780;
+reg [ay787f5 - 1 : 0] en5e01d;
+reg suf00ec;
+reg oh80760;
+reg lf3b04;
+reg mt1d826;
+reg [nefea21 : 0] en609a7;
+reg xy4d3c;
+reg [gq3e970 : 0] gq34f1d;
+reg zma78e9;
+reg oh3c74b;
+reg nre3a5c;
+reg wl1d2e7;
+reg nre973d;
+reg al4b9ef;
+reg [gq1fd44 - 1 : 0] uve7be0;
+reg [gq1fd44 - 1 : 0] osef82f;
+reg [gq1fd44 - 1 : 0] goe0bca;
+reg [gq1fd44 - 1 : 0] xy2f281;
+reg xw7940a;
+reg [ay787f5 - 1 : 0] zx50293;
+reg [ay787f5 - 1 : 0] eca4fe;
+reg [ay787f5 - 1 : 0] zm93f8a;
+reg [ay787f5 - 1 : 0] nefe29d;
+reg [ay787f5 - 1 : 0] ep8a75a;
+reg [1 : 0] os53ad5;
+reg uk9d6a9;
+reg [iea0a1 : 0] jp5aa4a;
+reg [iea0a1 : 0] wya92bb;
+reg [iea0a1 : 0] vv4aec8;
+reg [iea0a1 : 0] qvbb232;
+reg [iea0a1 : 0] pfc8cad;
+reg [iea0a1 : 0] rv32b79;
+reg [iea0a1 : 0] fcade74;
+reg [iea0a1 : 0] xw79d14;
+reg icce8a3;
+reg th74518;
+reg [gq3e970 : 0] hq14633;
+reg [ira13c3 : 0] qv18cd8;
+reg [sw21414 : 0] yz33625;
+reg [mr44282 : 0] fnd896e;
+reg [cmf510a : 0] fc25bb1;
+reg [ou8284f : 0] bl6ec56;
+reg [ou8284f : 0] irb15bb;
+reg [ou8284f : 0] ww56ee4;
+reg [15 : 0] hqb7721;
+reg [nefea21 : 0] qtdc85c;
+reg [nefea21 : 0] ec21723;
+reg bab919;
+reg me5c8ca;
+reg fae4650;
+reg [ay787f5 - 1 : 0] vx1941c;
+reg dmca0e7;
+reg jp5073b;
+reg [2047:0] wy2e8db;
+wire [53:0] vv746d9;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+localparam ksa36ce = 54,tw1b670 = 32'hfdffd28b;
+localparam [31:0] icdb382 = tw1b670;
+localparam mece084 = tw1b670 & 4'hf;
+localparam [11:0] ou8210c = 'h7ff;
+wire [(1 << mece084) -1:0] db84308;
+reg [ksa36ce-1:0] dbc230;
+reg [mece084-1:0] kf8c37 [0:1];
+reg [mece084-1:0] hq30de9;
+reg hq86f4b;
+integer hd37a5a;
+integer dobd2d6;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+assign xy3a4a5 = jp5aa4a[7:0];
+assign ldd252b = wya92bb[7:0];
+assign sw9295e = vv4aec8[7:0];
+assign db94af1 = qvbb232[7:0];
+assign jra578e = pfc8cad[7:0];
+assign ou2bc77 = rv32b79[7:0];
+assign ip5e3b9 = fcade74[7:0];
+assign zkf1dcc = xw79d14[7:0];
+assign tx_en = yz33625[3];
+assign sjae511 = yz33625[1];
+assign jcc5d72 = yz33625[2];
+assign ri1e263 = {bl6ec56,irb15bb,ww56ee4};
+assign uic4515 = fnd896e[0];
+assign tu58bae = fnd896e[1];
+assign ic7288c = fnd896e[2];
+assign kded62e = fnd896e[3];
+assign pu8c1d2 = fnd896e[4];
+assign ym2eb93 = fnd896e[6];
+assign shf88a2 = fnd896e[7];
+assign thddac5 = fnd896e[8];
+assign dz6b175 = fc25bb1[13:0];
+assign ou8d15c = (qv18cd8 < 4) ? 1 : qv18cd8 - 3;
+assign jrba3b7 = {5'b00000,wl1d2e7,hq14633[8:0],al4b9ef};
+
+
+
+
+
+
+
+
+
+
+
+  assign vx37d2f = yz33625[0] ? 1'b0 : fnd896e[5];  assign tuf131a = yz33625[0];
+
+
+
+
+always @(posedge hclk or negedge reset_n)      if (!reset_n)        begin         wy31bf1 <= 8'h0;         en6fc49 <= 8'h0;         lqf126f <= 8'h0;         yk49bd2 <= 8'h0;         rvbf192 <= 1'b1;         off8c97 <= 1'b1;         qtc64bd <= 1'b1;         qi92f6f <= 0;        end      else        begin         wy31bf1 <= rgd5780;         en6fc49 <= uve7be0;         lqf126f <= osef82f;         yk49bd2 <= goe0bca;         rvbf192 <= lf3b04;         off8c97 <= suf00ec;         qtc64bd <= oh80760;         qi92f6f <= en5e01d;        end
+
+always @(posedge hclk or negedge reset_n)      if (!reset_n)         qg56946 <= 1'b0;      else         qg56946 <= oh3c74b;
+always @(posedge hclk or negedge reset_n)      if (!reset_n)         mtb4a31 <= 1'b0;      else         mtb4a31 <= nre3a5c;
+always @(posedge hclk or negedge reset_n)      if (!reset_n)         xla518d <= 1'b0;      else         xla518d <= mt1d826;
+always @(posedge hclk or negedge reset_n)      if (!reset_n)         zz28c6f <= 1'b0;      else         zz28c6f <= nre973d;
+
+always @(posedge hclk or negedge reset_n)      if (!reset_n)         zxd7b48 <= 1'b0;      else         zxd7b48 <= zma78e9;
+always @(posedge hclk or negedge reset_n)      if (!reset_n)         fcbda47 <= 1'b0;      else         fcbda47 <= icce8a3;
+always @(posedge hclk or negedge reset_n)      if (!reset_n)         tu691dd <= 9'b000000000;      else if (th74518)         tu691dd <= gq34f1d;
+
+
+
+
+
+always @(posedge hclk or negedge reset_n)   if (!reset_n)      begin         lf8edf8 <= 16'h00;      end   else if (xy4d3c)      begin         lf8edf8 <= en609a7;      end
+always @(posedge hclk or negedge reset_n)   if (!reset_n)      begin         pub7e32 <= 16'h00;         ks97b79 <= 1'b1;         pubdbc9 <= 1'b1;      end   else      begin         pub7e32 <= qtdc85c;         ks97b79 <= xw7940a;         pubdbc9 <= dmca0e7;      end
+
+
+
+
+
+
+
+always @(posedge hclk or negedge reset_n)    if (!reset_n)       begin
+         uv44576 <= 2'b00;         uxaed38 <= 8'h00;         yzb4e2a <= 8'h00;         tj38aaa <= 8'h00;         zm2aaba <= 8'h00;         lfaae9f <= 8'h00;         fpba7fa <= 8'h00;         ir9febd <= 8'h00;         wwfaf69 <= 8'h00;         vi4775b <= 5'b01100;         dzdd6d8 <= 4'h0;         mr5b63a <= 8'h0;         vvd8ea0 <= 16'd1518;         ng3a837 <= 16'h00;         fpa0dd1 <= 16'h00;         hd37476 <= 16'h00;         hready_n <= 1'b1;         ep90e3c <= 16'h0001;         hdataout <= 0;         hdataout_en_n <= 1;         hd22bb4 <= 1;         ou2ef80 <= 0;         wlbe008 <= 0;         an80228 <= 0;         kf8a22 <= 0;         db288ae <= 0;         ui5cbbe <= 1'b1;       end  else   begin     hdataout <= zx50293;     hdataout_en_n <= uk9d6a9;     hready_n <= xw7940a;                         if (!xw7940a || !dmca0e7)        begin         ui5cbbe <= 1'b1;         hd22bb4 <= 1'b1;       end    else if (!lf3b04 && !bab919 && !oh80760 && !fae4650 && xw7940a && jp5073b && dmca0e7)       begin          ui5cbbe <= 1'b0;          if (uve7be0 == 8'h00)            begin                dzdd6d8 <= vx1941c;            end          else if (!yz33625[3] && !yz33625[2])            begin              case(uve7be0)                8'h02 : mr5b63a[7:0] <= vx1941c[7:0];                8'h04 : vvd8ea0[7:0] <= vx1941c;                8'h08 : vi4775b[4:0] <= vx1941c;                8'h0A : ng3a837[7:0] <= vx1941c;                8'h0C : fpa0dd1[7:0] <= vx1941c;                8'h0E : hd37476[7:0] <= vx1941c;                8'h22 : uxaed38[7:0] <= vx1941c;                8'h24 : yzb4e2a[7:0] <= vx1941c;                8'h26 : tj38aaa[7:0] <= vx1941c;                8'h28 : zm2aaba[7:0] <= vx1941c;                8'h2A : lfaae9f[7:0] <= vx1941c;                8'h2C : fpba7fa[7:0] <= vx1941c;                8'h2E : ir9febd[7:0] <= vx1941c;                8'h30 : wwfaf69[7:0] <= vx1941c;                8'h34 : ep90e3c[7:0] <= vx1941c;                8'h03 : mr5b63a[8] <= vx1941c[0];                8'h05 : vvd8ea0[15:8] <= vx1941c;                8'h0B : ng3a837[15:8] <= vx1941c;                8'h0D : fpa0dd1[15:8] <= vx1941c;                8'h0F : hd37476[15:8] <= vx1941c;                8'h35 : ep90e3c[15:8] <= vx1941c;                default : dzdd6d8 <= yz33625;              endcase           end         end     else if (!lf3b04 && !bab919 && !suf00ec && !me5c8ca && xw7940a && uve7be0[0] && jp5073b)           begin            hd22bb4 <= 1'b0;            ui5cbbe <= 1'b0;            case(uve7be0)                8'h03 : ou2ef80 <= {7'h0,fnd896e[8]};                8'h05 : ou2ef80 <= fc25bb1[15:8];                8'h0B : ou2ef80 <= bl6ec56[15:8];                8'h0D : ou2ef80 <= irb15bb[15:8];                8'h0F : ou2ef80 <= ww56ee4[15:8];                8'h13 : ou2ef80 <= hqb7721[15:8];                default : ou2ef80 <= 8'h0;            endcase           end     else if (!lf3b04 && !bab919 && !suf00ec && !me5c8ca && xw7940a && !uve7be0[0] && jp5073b)           begin             hd22bb4 <= 1'b0;             ui5cbbe <= 1'b0;             case(uve7be0)                8'h00 : ou2ef80 <= {4'b0000,yz33625};
+
+
+                  8'h02 : ou2ef80 <= fnd896e[7:0];
+
+
+                8'h04 : ou2ef80 <= fc25bb1[7:0];                8'h08 : ou2ef80 <= {3'b000,qv18cd8[4:0]};                8'h0A : ou2ef80 <= bl6ec56[7:0];                8'h0C : ou2ef80 <= irb15bb[7:0];                8'h0E : ou2ef80 <= ww56ee4[7:0];                8'h12 : ou2ef80 <= hqb7721[7:0];                8'h22 : ou2ef80 <= jp5aa4a[7:0];                8'h24 : ou2ef80 <= wya92bb[7:0];                8'h26 : ou2ef80 <= vv4aec8[7:0];                8'h28 : ou2ef80 <= qvbb232[7:0];                8'h2A : ou2ef80 <= pfc8cad[7:0];                8'h2C : ou2ef80 <= rv32b79[7:0];                8'h2E : ou2ef80 <= fcade74[7:0];                8'h30 : ou2ef80 <= xw79d14[7:0];                8'h32 : ou2ef80 <= ec21723[7:0];                8'h34 : ou2ef80 <= ep90e3c[7:0];                default : ou2ef80 <= 8'h0;             endcase          end  end
+
+
+
+
+
+always@* begin rgd5780<={haddr>>1,vv746d9[0]};en5e01d<={hdatain>>1,vv746d9[1]};suf00ec<=vv746d9[2];oh80760<=vv746d9[3];lf3b04<=vv746d9[4];mt1d826<=vv746d9[5];en609a7<={sw10140>>1,vv746d9[6]};xy4d3c<=vv746d9[7];gq34f1d<={ri99b0a>>1,vv746d9[8]};zma78e9<=vv746d9[9];oh3c74b<=vv746d9[10];nre3a5c<=vv746d9[11];wl1d2e7<=vv746d9[12];nre973d<=vv746d9[13];al4b9ef<=vv746d9[14];uve7be0<={wy31bf1>>1,vv746d9[15]};osef82f<={en6fc49>>1,vv746d9[16]};goe0bca<={lqf126f>>1,vv746d9[17]};xy2f281<={yk49bd2>>1,vv746d9[18]};xw7940a<=vv746d9[19];zx50293<={ou2ef80>>1,vv746d9[20]};eca4fe<={wlbe008>>1,vv746d9[21]};zm93f8a<={an80228>>1,vv746d9[22]};nefe29d<={kf8a22>>1,vv746d9[23]};ep8a75a<={db288ae>>1,vv746d9[24]};os53ad5<={uv44576>>1,vv746d9[25]};uk9d6a9<=vv746d9[26];jp5aa4a<={uxaed38>>1,vv746d9[27]};wya92bb<={yzb4e2a>>1,vv746d9[28]};vv4aec8<={tj38aaa>>1,vv746d9[29]};qvbb232<={zm2aaba>>1,vv746d9[30]};pfc8cad<={lfaae9f>>1,vv746d9[31]};rv32b79<={fpba7fa>>1,vv746d9[32]};fcade74<={ir9febd>>1,vv746d9[33]};xw79d14<={wwfaf69>>1,vv746d9[34]};icce8a3<=vv746d9[35];th74518<=vv746d9[36];hq14633<={tu691dd>>1,vv746d9[37]};qv18cd8<={vi4775b>>1,vv746d9[38]};yz33625<={dzdd6d8>>1,vv746d9[39]};fnd896e<={mr5b63a>>1,vv746d9[40]};fc25bb1<={vvd8ea0>>1,vv746d9[41]};bl6ec56<={ng3a837>>1,vv746d9[42]};irb15bb<={fpa0dd1>>1,vv746d9[43]};ww56ee4<={hd37476>>1,vv746d9[44]};hqb7721<={jrba3b7>>1,vv746d9[45]};qtdc85c<={lf8edf8>>1,vv746d9[46]};ec21723<={pub7e32>>1,vv746d9[47]};bab919<=vv746d9[48];me5c8ca<=vv746d9[49];fae4650<=vv746d9[50];vx1941c<={qi92f6f>>1,vv746d9[51]};dmca0e7<=vv746d9[52];jp5073b<=vv746d9[53];end
+always@* begin wy2e8db[2047]<=hdatain[0];wy2e8db[2046]<=hread_n;wy2e8db[2044]<=hwrite_n;wy2e8db[2040]<=hcs_n;wy2e8db[2032]<=dzc2191;wy2e8db[2017]<=sw10140[0];wy2e8db[1987]<=cb80a01;wy2e8db[1963]<=qi92f6f[0];wy2e8db[1950]<=jrba3b7[0];wy2e8db[1926]<=ri99b0a[0];wy2e8db[1878]<=ks97b79;wy2e8db[1853]<=lf8edf8[0];wy2e8db[1839]<=vi4775b[0];wy2e8db[1818]<=kf8a22[0];wy2e8db[1804]<=vvcd852;wy2e8db[1708]<=pubdbc9;wy2e8db[1707]<=tj38aaa[0];wy2e8db[1658]<=pub7e32[0];wy2e8db[1630]<=dzdd6d8[0];wy2e8db[1614]<=en6fc49[0];wy2e8db[1589]<=db288ae[0];wy2e8db[1561]<=ba93361;wy2e8db[1511]<=fpa0dd1[0];wy2e8db[1483]<=fcbda47;wy2e8db[1394]<=wwfaf69[0];wy2e8db[1372]<=fpba7fa[0];wy2e8db[1367]<=zm2aaba[0];wy2e8db[1269]<=rvbf192;wy2e8db[1251]<=ou2ef80[0];wy2e8db[1212]<=mr5b63a[0];wy2e8db[1180]<=lqf126f[0];wy2e8db[1130]<=uv44576[0];wy2e8db[1074]<=qg56946;wy2e8db[1023]<=haddr[0];wy2e8db[981]<=qtc64bd;wy2e8db[975]<=hd37476[0];wy2e8db[919]<=tu691dd[0];wy2e8db[909]<=an80228[0];wy2e8db[853]<=yzb4e2a[0];wy2e8db[807]<=wy31bf1[0];wy2e8db[755]<=ng3a837[0];wy2e8db[741]<=zxd7b48;wy2e8db[697]<=ir9febd[0];wy2e8db[686]<=lfaae9f[0];wy2e8db[625]<=ui5cbbe;wy2e8db[490]<=off8c97;wy2e8db[454]<=wlbe008[0];wy2e8db[426]<=uxaed38[0];wy2e8db[403]<=zz28c6f;wy2e8db[377]<=vvd8ea0[0];wy2e8db[312]<=yk49bd2[0];wy2e8db[213]<=hd22bb4;wy2e8db[201]<=xla518d;wy2e8db[100]<=mtb4a31;end         assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6<ksa36ce; dobd2d6=dobd2d6+1) begin dbc230[dobd2d6] = db84308[hq30de9]; hq86f4b = ^(hq30de9 & kf8c37[0]); hq30de9 = {hq30de9, hq86f4b}; end end 
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+`timescale 1 ns / 100 ps
+module pfcd934(
+ui4c693, 
+jc63498, 
+ks1a4c2, 
+rtd2610, 
+pu93086, 
+ym98432, 
+reset_n, 
+mdc, 
+mdi, 
+mdo, 
+mdio_en 
+);
+localparam wl95c7b     = 14'b00000000000001;
+localparam epae3dc = 14'b00000000000010;
+localparam dz71ee4    = 14'b00000000000100;
+localparam cb8f727    = 14'b00000000001000;
+localparam bl7b93d     = 14'b00000000010000;
+localparam mrdc9ee     = 14'b00000000100000;
+localparam fae4f74    = 14'b00000001000000;
+localparam hd27ba2    = 14'b00000010000000;
+localparam bn3dd17     = 14'b00000100000000;
+localparam psee8bf     = 14'b00001000000000;
+localparam rt745fb  = 14'b00010000000000;
+localparam fca2fde     = 14'b00100000000000;
+localparam kf17ef3    = 14'b01000000000000;
+localparam rvbf79d    = 14'b10000000000000;
+parameter nefbcef = 10;
+parameter cmde77a = 15;
+parameter fnf3bd0 = 4;
+parameter mg9de86 = 2;
+parameter eaef430 = 3;
+parameter cz7a180 = 13;
+input reset_n;
+input mdc;
+input [nefbcef:0] ui4c693;
+input [cmde77a:0] jc63498;
+input rtd2610;
+input mdi;
+output mdo;
+output mdio_en;
+output ym98432;
+output pu93086;
+output [cmde77a:0] ks1a4c2;
+reg [cmde77a:0] ks1a4c2;
+reg pu93086;
+reg mdio_en;
+reg ls20830;
+reg mdo;
+reg [cmde77a:0] nt6092;
+reg [cmde77a:0] mg824ba;
+reg [cmde77a:0] sw92e8c;
+reg [fnf3bd0:0] lfba308;
+reg [mg9de86:0] hq8c238;
+reg [mg9de86:0] gd8e17;
+reg [eaef430:0] vx385eb;
+reg [eaef430:0] ir17af6;
+reg [cz7a180:0] viebdaa;
+reg [cz7a180:0] ldf6a9d;
+reg lfb54ee;
+reg lfaa776;
+reg ea53bb6;
+reg sw9ddb1;
+reg byeed88;
+reg ym98432;
+reg [nefbcef : 0] uxb10d1;
+reg [cmde77a : 0] ui43460;
+reg ie1a301;
+reg ykd1808;
+reg tw8c040;
+reg [cmde77a : 0] ls1015;
+reg [cmde77a : 0] zx40554;
+reg [cmde77a : 0] ec15534;
+reg [fnf3bd0 : 0] mr54d0f;
+reg [mg9de86 : 0] uk343e1;
+reg [mg9de86 : 0] wyf844;
+reg [eaef430 : 0] vie1102;
+reg [eaef430 : 0] wj4409d;
+reg [cz7a180 : 0] ir2763;
+reg [cz7a180 : 0] ie9d8ef;
+reg blec778;
+reg ho63bc7;
+reg an1de3b;
+reg meef1dc;
+reg me78ee0;
+reg [2047:0] wy2e8db;
+wire [19:0] vv746d9;
+
+localparam ksa36ce = 20,tw1b670 = 32'hfdffc70b;
+localparam [31:0] icdb382 = tw1b670;
+localparam mece084 = tw1b670 & 4'hf;
+localparam [11:0] ou8210c = 'h7ff;
+wire [(1 << mece084) -1:0] db84308;
+reg [ksa36ce-1:0] dbc230;
+reg [mece084-1:0] kf8c37 [0:1];
+reg [mece084-1:0] hq30de9;
+reg hq86f4b;
+integer hd37a5a;
+integer dobd2d6;
+
+
+
+
+
+
+
+
+
+
+
+always @(posedge mdc or negedge reset_n)     if (!reset_n)       begin         sw9ddb1 <= 1'b0;       end     else       begin         sw9ddb1 <= ie1a301;       end
+
+always @(posedge mdc or negedge reset_n)     if (!reset_n)       begin         byeed88 <= 1'b0;       end     else       begin         byeed88 <= meef1dc;       end
+
+always @(posedge mdc or negedge reset_n)     if (!reset_n)       begin         ea53bb6 <= 1'b0;         lfb54ee <= 1'b0;         lfaa776 <= 1'b0;         sw92e8c <= 16'h0;         mg824ba <= 16'h0;       end     else if (pu93086)       begin          ea53bb6 <= 1'b0;          lfb54ee <= 1'b0;          lfaa776 <= 1'b0;       end     else if (me78ee0 && !an1de3b)       begin         ea53bb6 <= 1'b1;         sw92e8c <= {3'b000,uxb10d1,2'b00};         mg824ba <= ui43460;         if (uxb10d1[10])             lfb54ee <= 1'b1;         else             lfaa776 <= 1'b1;       end
+
+
+always @(negedge mdc or negedge reset_n) begin     if (!reset_n) begin         mdo <= 1'b0;     end else begin         mdo <= tw8c040;     end
+end
+
+always @(posedge mdc or negedge reset_n)     if (!reset_n)       begin         lfba308 <= 5'b00000;         ls20830 <= 1'b0;         mdio_en <= 1'b0;         pu93086 <= 1'b0;         ks1a4c2 <= 16'h0;         nt6092 <= 16'h0;         hq8c238 <= 3'b000;         gd8e17 <= 3'b110;         vx385eb <= 4'b1011;         ir17af6 <= 4'b1111;       end        else if (ir2763 == wl95c7b)       begin           pu93086 <= 1'b0;                      lfba308 <= 5'b00000;           ls20830 <= 1'b0;           mdio_en <= 1'b0;           hq8c238 <= 3'b000;           gd8e17 <= 3'b110;           vx385eb <= 4'b1011;           ir17af6 <= 4'b1111;       end        else if (ir2763 == epae3dc)       begin         lfba308 <= mr54d0f + 5'b00001;         ls20830 <= 1'b1;         mdio_en <= 1'b1;       end        else if (ir2763 == cb8f727)       begin         lfba308 <= 5'b00000;         ls20830 <= 1'b1;         mdio_en <= 1'b1;       end        else if (ir2763 == dz71ee4)       begin         lfba308 <= 5'b00000;         ls20830 <= 1'b0;         mdio_en <= 1'b1;       end     else if (ir2763 == psee8bf)         begin           if (blec778)             begin              mdio_en <= 1'b1;              ls20830 <= 1'b1;             end           else             begin              mdio_en <= 1'b0;              ls20830 <= 1'b0;             end         end     else if  (ir2763 == bl7b93d)                begin                   ls20830 <= 1'b0;                   mdio_en <= 1'b1;                end     else if  (ir2763 == mrdc9ee)                begin                   ls20830 <= 1'b1;                   mdio_en <= 1'b1;                end        else if (ir2763 == bn3dd17)       begin        if (blec778)         begin            ls20830 <= 1'b0;            mdio_en <= 1'b1;         end        else            ls20830 <= 1'b0;       end         else if (ir2763 == fca2fde)         begin          if (blec778)           begin            ls20830 <= zx40554[wj4409d];            ir17af6 <= wj4409d - 4'b0001;            mdio_en <= 1'b1;           end          else           begin            ls20830 <= 1'b0;            mdio_en <= 1'b0;            nt6092[wj4409d] <= ykd1808;            ir17af6 <= wj4409d - 4'b0001;           end           lfba308 <= mr54d0f + 5'b00001;         end         else if (ir2763 == fae4f74)         begin           mdio_en <= 1'b1;           ls20830 <= ec15534[vie1102];           vx385eb <= vie1102 - 4'b0001;           lfba308 <= mr54d0f + 5'b00001;         end          else if (ir2763 == hd27ba2)         begin           mdio_en <= 1'b1;           ls20830 <= ec15534[wyf844];           gd8e17 <= wyf844 - 3'b001;           hq8c238 <= uk343e1 + 3'b001;           lfba308 <= 5'b00000;         end         else if (ir2763 == kf17ef3)         begin           mdio_en <= 1'b0;           ls20830 <= 1'b0;           lfba308 <= 5'b00000;           pu93086 <= 1'b1;           ks1a4c2 <= ls1015;         end        else if (ir2763 == rvbf79d)         begin           mdio_en <= 1'b0;           ls20830 <= 1'b0;           lfba308 <= 5'b00000;           pu93086 <= 1'b1;           ks1a4c2 <= ls1015;         end
+
+
+always @(posedge mdc or negedge reset_n)     if (!reset_n)       begin          ym98432 <= 1'b1;       end     else if (ir2763 == wl95c7b && !me78ee0)       begin          ym98432 <= 1'b1;       end     else       begin          ym98432 <= 1'b0;       end
+
+always @(posedge mdc or negedge reset_n)     if (!reset_n)       begin         viebdaa <= wl95c7b;       end     else       begin         viebdaa <= ie9d8ef;       end
+always @(ir2763 or blec778 or ho63bc7 or mr54d0f or uk343e1)    begin     case(ir2763)       wl95c7b :                      begin                        if (blec778 || ho63bc7)                          begin                            ldf6a9d = epae3dc;                          end                        else                          begin                            ldf6a9d = wl95c7b;                          end                     end        epae3dc :                      begin                         if (mr54d0f < 5'b11111)                          begin                            ldf6a9d = epae3dc;                          end                         else                          begin                            ldf6a9d = dz71ee4;                          end                     end         dz71ee4 :                      begin                            ldf6a9d = cb8f727;                     end          cb8f727 :                      begin                        if (blec778)                            begin                              ldf6a9d = bl7b93d;                            end                          else                            begin                              ldf6a9d = mrdc9ee;                            end                     end         bl7b93d :                      begin                         if (blec778)                            begin                              ldf6a9d = mrdc9ee;                            end                          else                            begin                              ldf6a9d = fae4f74;                            end                     end          mrdc9ee :                      begin                         if (ho63bc7)                            begin                              ldf6a9d = bl7b93d;                            end                          else                            begin                              ldf6a9d = fae4f74;                            end                     end          fae4f74 :                    begin                         if (mr54d0f < 5'b00100)                           begin                              ldf6a9d = fae4f74;                           end                         else                           begin                              ldf6a9d = hd27ba2;                           end                   end          hd27ba2 :                    begin                   if (uk343e1 < 3'b100)                     begin                              ldf6a9d = hd27ba2;                     end                   else                     begin                              ldf6a9d = psee8bf;                     end                   end
+          psee8bf :                      begin                              ldf6a9d = bn3dd17;                     end          bn3dd17 :                      begin                          if (blec778)                              ldf6a9d = fca2fde;                          else                              ldf6a9d = rt745fb;                     end          rt745fb :                      begin                              ldf6a9d = fca2fde;                     end
+          fca2fde :                    begin                   if (mr54d0f < 5'b01111)                     begin                              ldf6a9d = fca2fde;                     end                   else                     begin                              ldf6a9d = kf17ef3;                     end                   end           kf17ef3 :                    begin                       ldf6a9d = rvbf79d;                   end
+           rvbf79d :                   begin                       ldf6a9d = wl95c7b;                   end           default :                   begin                       ldf6a9d = wl95c7b;                   end          endcase   end
+always@* begin uxb10d1<={ui4c693>>1,vv746d9[0]};ui43460<={jc63498>>1,vv746d9[1]};ie1a301<=vv746d9[2];ykd1808<=vv746d9[3];tw8c040<=vv746d9[4];ls1015<={nt6092>>1,vv746d9[5]};zx40554<={mg824ba>>1,vv746d9[6]};ec15534<={sw92e8c>>1,vv746d9[7]};mr54d0f<={lfba308>>1,vv746d9[8]};uk343e1<={hq8c238>>1,vv746d9[9]};wyf844<={gd8e17>>1,vv746d9[10]};vie1102<={vx385eb>>1,vv746d9[11]};wj4409d<={ir17af6>>1,vv746d9[12]};ir2763<={viebdaa>>1,vv746d9[13]};ie9d8ef<={ldf6a9d>>1,vv746d9[14]};blec778<=vv746d9[15];ho63bc7<=vv746d9[16];an1de3b<=vv746d9[17];meef1dc<=vv746d9[18];me78ee0<=vv746d9[19];end
+always@* begin wy2e8db[2047]<=jc63498[0];wy2e8db[2046]<=rtd2610;wy2e8db[2044]<=mdi;wy2e8db[2040]<=ls20830;wy2e8db[2032]<=nt6092[0];wy2e8db[2016]<=mg824ba[0];wy2e8db[1985]<=sw92e8c[0];wy2e8db[1922]<=lfba308[0];wy2e8db[1867]<=byeed88;wy2e8db[1797]<=hq8c238[0];wy2e8db[1547]<=gd8e17[0];wy2e8db[1490]<=ea53bb6;wy2e8db[1047]<=vx385eb[0];wy2e8db[1023]<=ui4c693[0];wy2e8db[933]<=sw9ddb1;wy2e8db[745]<=lfaa776;wy2e8db[372]<=lfb54ee;wy2e8db[186]<=ldf6a9d[0];wy2e8db[93]<=viebdaa[0];wy2e8db[46]<=ir17af6[0];end         assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6<ksa36ce; dobd2d6=dobd2d6+1) begin dbc230[dobd2d6] = db84308[hq30de9]; hq86f4b = ^(hq30de9 & kf8c37[0]); hq30de9 = {hq30de9, hq86f4b}; end end 
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+`timescale 1 ns / 100 ps
+module twb7994(
+
+  
+txmac_clk, 
+rxmac_clk, 
+reset_n, 
+rxmac_clk_en,   
+txmac_clk_en,   
+
+  
+hq11dba, 
+ph8edd2, 
+vi76e96, 
+
+  
+gd12bd1, 
+aa8257a, 
+mrf282b, 
+xy304af, 
+tj9415c, 
+kf95e8d, 
+
+  
+cb9fe9b, 
+goff4dd, 
+
+  crs, 
+  col, 
+
+
+  
+txd_pos, 
+         
+         
+txd_neg, 
+         
+tx_en, 
+tx_er, 
+
+
+tuf131a, 
+tu58bae, 
+
+  
+rx_dv_pos, 
+rx_dv_neg, 
+rx_er_pos, 
+rx_er_neg, 
+rxd_pos,   
+rxd_neg    
+);
+parameter uv51d07 = 8;
+parameter ph8e83c = 8;
+parameter xj741e6 = 4;
+input txmac_clk;
+input rxmac_clk;
+input reset_n;
+input rxmac_clk_en;
+input txmac_clk_en;
+input [uv51d07-1:0] hq11dba;
+input ph8edd2;
+input vi76e96;
+output gd12bd1;
+output aa8257a;
+output mrf282b;
+output xy304af;
+output [uv51d07-1:0] tj9415c;
+output cb9fe9b;
+output goff4dd;
+input tuf131a;
+input tu58bae;
+
+input col;
+input crs;
+
+output [7:0] txd_pos;
+output [3:0] txd_neg;
+output tx_en;
+output tx_er;
+output kf95e8d;
+input rx_dv_pos;
+input rx_dv_neg;
+input rx_er_pos;
+input rx_er_neg;
+input [7:0] rxd_pos;
+input [3:0] rxd_neg;
+reg sudbb02;
+reg hbdd811;
+reg thec08e;
+reg gd12bd1   ;
+reg qv23bd;
+reg do11ded;
+reg jr8ef6a   ;
+reg yk77b56   ;
+reg jebdab0   ;
+reg aa8257a      ;
+reg qt6ac1d;
+reg ww560ed;
+reg [uv51d07-1:0] ng83b46;
+reg [uv51d07-1:0] ened194;
+reg [uv51d07-1:0] ay46528;
+reg [uv51d07-1:0] tj9415c   ;
+reg [uv51d07-1:0] ph283b7;
+reg [uv51d07-1:0] doedfd;
+reg xy304af ;
+reg xyb7f52 ;
+reg dbbfa92 ;
+reg czfd496 ;
+reg mrf282b    ;
+reg jc525a0;
+reg co92d02;
+reg [7:0] txd_pos;
+reg [3:0] txd_neg;
+reg tx_en;
+reg tx_er;
+reg tw1173d;
+reg lf8b9eb;
+reg os5cf5e;
+reg kf95e8d   ;
+reg rv3d785;
+reg jcebc2e;
+reg [uv51d07-1:0] qgf0b9c;
+reg cb85ce1;
+reg uk2e70d;
+reg zk73868;
+reg ri9c342;
+reg xwe1a13;
+reg uxd09a;
+reg ic684d4;
+reg lq426a1;
+reg [xj741e6-1:0] qv9a85e;
+reg osd42f5;
+reg [ph8e83c-1:0] pubd4d;
+reg [3:0] wj5ea6a;
+reg [3:0] kqf5355;
+reg aaa9aa8;
+reg vi4d540;
+reg sh6aa02;
+reg pf55015;
+reg doa80af;
+reg zx4057b;
+reg ux2bde;
+reg ec15ef4;
+reg rvaf7a0;
+wire cb9fe9b;
+wire goff4dd;
+
+
+
+
+
+
+reg [uv51d07 - 1 : 0] hda0d8a;
+reg xl6c56;
+reg ep362b6;
+reg kfb15b5;
+reg ec346dc;
+reg ui56d64;
+reg qib6b21;
+reg zzb5908;
+reg ukac847;
+reg [7 : 0] bl64238;
+reg [3 : 0] co211c7;
+reg mt8e39;
+reg by471cd;
+reg ph38e6b;
+reg zxc735f;
+reg yz39aff;
+reg thcd7fd;
+reg dz6bfee;
+reg zx5ff77;
+reg icffbbf;
+reg qtfddf8;
+reg [uv51d07 - 1 : 0] me77e2b;
+reg [uv51d07 - 1 : 0] enf8ac7;
+reg [uv51d07 - 1 : 0] aa2b1ea;
+reg [uv51d07 - 1 : 0] blc7a82;
+reg [uv51d07 - 1 : 0] meea0b6;
+reg pf505b0;
+reg co82d87;
+reg tj16c38;
+reg ieb61c7;
+reg rvb0e39;
+reg ie871cf;
+reg tj38e79;
+reg fnc73cf;
+reg ux39e7f;
+reg lqcf3fd;
+reg [uv51d07 - 1 : 0] dmcff5b;
+reg en7fada;
+reg kdfd6d4;
+reg faeb6a4;
+reg kd5b522;
+reg psda914;
+reg god48a3;
+reg gda4518;
+reg tj228c5;
+reg [xj741e6 - 1 : 0] swa317b;
+reg gd18bd8;
+reg [ph8e83c - 1 : 0] zm2f623;
+reg [3 : 0] pf7b11a;
+reg [3 : 0] zxd88d7;
+reg eac46be;
+reg ir235f0;
+reg co1af84;
+reg jpd7c21;
+reg irbe10f;
+reg suf087d;
+reg tj843e9;
+reg wy21f4e;
+reg ksfa70;
+reg [2047:0] wy2e8db;
+wire [58:0] vv746d9;
+
+
+
+
+
+
+
+
+
+localparam ksa36ce = 59,tw1b670 = 32'hfdffd14b;
+localparam [31:0] icdb382 = tw1b670;
+localparam mece084 = tw1b670 & 4'hf;
+localparam [11:0] ou8210c = 'h7ff;
+wire [(1 << mece084) -1:0] db84308;
+reg [ksa36ce-1:0] dbc230;
+reg [mece084-1:0] kf8c37 [0:1];
+reg [mece084-1:0] hq30de9;
+reg hq86f4b;
+integer hd37a5a;
+integer dobd2d6;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+
+
+
+
+
+  
+
+
+
+
+
+
+  
+
+
+
+
+
+  assign goff4dd = col;  assign cb9fe9b = crs;
+
+
+
+
+always @(posedge rxmac_clk or negedge reset_n) begin    if (!reset_n) begin        qv9a85e <= 4'b0000;        osd42f5 <= 1'b1;    end    else if (rxmac_clk_en) begin       if (!gd18bd8 && !eac46be) begin         if (swa317b < 4'b1011) begin           qv9a85e <= swa317b + 4'b0001;         end else begin           qv9a85e <= 4'b0000;           osd42f5 <= 1'b1;         end       end else if (ir235f0) begin          qv9a85e <= 4'b0000;          osd42f5 <= 1'b0;       end   end
+end
+
+
+  always @(posedge rxmac_clk or negedge reset_n) begin      if (!reset_n) begin         xwe1a13 <= 1'b0;         uxd09a <= 1'b0;      end      else if (rxmac_clk_en) begin         xwe1a13 <= 1'b1;         uxd09a <= psda914;      end  end
+
+
+
+
+always @(posedge rxmac_clk or negedge reset_n) begin    if (!reset_n) begin       ic684d4 <= 1'b0;       lq426a1 <= 1'b0;    end    else if (rxmac_clk_en) begin       ic684d4 <= ec346dc;       lq426a1 <= gda4518;    end
+end
+
+
+  always @(posedge txmac_clk or negedge reset_n) begin      if (!reset_n) begin         zk73868 <= 1'b0;         ri9c342 <= 1'b0;      end      else if (txmac_clk_en) begin         zk73868 <= 1'b1;         ri9c342 <= faeb6a4;      end  end
+
+
+
+
+always @(negedge rxmac_clk or negedge reset_n) begin   if (!reset_n) begin      sh6aa02 <= 0;      pf55015 <= 0;      zx4057b <= 0;      ux2bde <= 0;      wj5ea6a <= 0;      kqf5355 <= 0;   end   else if (rxmac_clk_en) begin      sh6aa02 <= qib6b21;      pf55015 <= co1af84;      zx4057b <= ukac847;      ux2bde <= suf087d;      wj5ea6a <= co211c7;      kqf5355 <= pf7b11a;   end
+end
+always @(posedge rxmac_clk or negedge reset_n) begin   if (!reset_n) begin      aaa9aa8 <= 0;      vi4d540 <= 0;      doa80af <= 0;      pubd4d <= 0;   end   else if (rxmac_clk_en) begin      aaa9aa8 <= ui56d64;      vi4d540 <= eac46be;      doa80af <= zzb5908;      pubd4d <= bl64238;   end
+end
+
+
+
+always @(posedge rxmac_clk or negedge reset_n) begin    if (!reset_n) begin       ec15ef4 <= 0;       rvaf7a0 <= 0;       ng83b46 <= 0;       ened194 <= 0;       ay46528 <= 0;       tj9415c <= 0;       ph283b7 <= 0;       doedfd <= 0;       xy304af <= 0;       xyb7f52 <= 0;       dbbfa92 <= 0;       czfd496 <= 0;       mrf282b <= 0;       jc525a0 <= 0;       co92d02 <= 0;       jr8ef6a <= 0;       yk77b56 <= 0;       jebdab0 <= 0;       aa8257a <= 0;       qt6ac1d <= 0;       ww560ed <= 0;       sudbb02 <= 0;       hbdd811 <= 0;       thec08e <= 0;       gd12bd1 <= 0;       qv23bd <= 0;       do11ded <= 0;       tw1173d <= 0;       lf8b9eb <= 0;       os5cf5e <= 0;       kf95e8d <= 0;       jcebc2e <= 0;       rv3d785 <= 0;    end    else if (rxmac_clk_en) begin       tj9415c <= aa2b1ea;       mrf282b <= tj16c38;       aa8257a <= zx5ff77;       gd12bd1 <= ph38e6b;       kf95e8d <= fnc73cf;       ay46528 <= enf8ac7;       czfd496 <= co82d87;       jebdab0 <= dz6bfee;       thec08e <= by471cd;       os5cf5e <= tj38e79;       ened194 <= me77e2b;       dbbfa92 <= pf505b0;       yk77b56 <= thcd7fd;       hbdd811 <= mt8e39;       lf8b9eb <= ie871cf;       if (god48a3) begin                    ng83b46 <= blc7a82;          xyb7f52 <= ieb61c7;          jr8ef6a <= icffbbf;          sudbb02 <= zxc735f;          tw1173d <= ux39e7f;  if (tj228c5) begin             xy304af <= ieb61c7 & mrf282b;  end else begin             xy304af <= mrf282b;          end       end else begin                    ng83b46 <= meea0b6;          xyb7f52 <= rvb0e39;          jr8ef6a <= qtfddf8;          sudbb02 <= yz39aff;          tw1173d <= lqcf3fd;  if (tj228c5) begin             xy304af <= rvb0e39 & mrf282b;  end else begin             xy304af <= mrf282b;          end       end              jc525a0 <= eac46be;       ph283b7 <= zm2f623;       qt6ac1d <= irbe10f;       qv23bd <= 0;       if ((ir235f0 == 0) && (eac46be == 1)) begin          rv3d785 <= ~gd18bd8;       end              if ((ir235f0 == 0) && (jpd7c21 == 1)) begin  ec15ef4 <= 0;          co92d02 <= eac46be & jpd7c21;          doedfd <= {zm2f623[3:0], zxd88d7};          ww560ed <= irbe10f | tj843e9;          jcebc2e <= ~gd18bd8;  if ({zm2f623[3:0], zxd88d7} == 8'hd5) begin             rvaf7a0 <= 0;  end else begin             rvaf7a0 <= 1;  end       end else if ((jpd7c21 == 0) && (eac46be == 1)) begin  ec15ef4 <= 1;          co92d02 <= co1af84 & eac46be;          doedfd <= {pf7b11a, zm2f623[3:0]};          ww560ed <= suf087d | irbe10f;          jcebc2e <= ~gd18bd8;  if ({pf7b11a, zm2f623[3:0]} == 8'hd5) begin             rvaf7a0 <= 0;  end else begin             rvaf7a0 <= 1;  end       end else if ((ksfa70 == 1)        && ({zm2f623[3:0], zxd88d7} == 8'hd5)) begin  ec15ef4 <= 0;          doedfd <= {zm2f623[3:0], zxd88d7};          rvaf7a0 <= 0;       end else if ((ksfa70 == 1)        && ({pf7b11a, zm2f623[3:0]} == 8'hd5)) begin  ec15ef4 <= 1;          doedfd <= {pf7b11a, zm2f623[3:0]};          rvaf7a0 <= 0;       end else if (wy21f4e == 0) begin          co92d02 <= eac46be & jpd7c21;          doedfd <= {zm2f623[3:0], zxd88d7};          ww560ed <= irbe10f | tj843e9;  if (rvb0e39 == 1) begin             do11ded <= eac46be != jpd7c21;  end       end else if (wy21f4e == 1) begin          co92d02 <= co1af84 & eac46be;          doedfd <= {pf7b11a, zm2f623[3:0]};          ww560ed <= suf087d | irbe10f;  if (rvb0e39 == 1) begin             do11ded <= co1af84 != eac46be;  end       end    end
+end
+
+
+always @(posedge txmac_clk or negedge reset_n) begin    if (!reset_n) begin           qgf0b9c <= 0;           cb85ce1 <= 0;    end    else if (txmac_clk_en) begin       if (ep362b6) begin           qgf0b9c <= hda0d8a;           cb85ce1 <= xl6c56;       end else begin           qgf0b9c <= 0;           cb85ce1 <= 0;       end    end
+end
+
+
+always @(posedge txmac_clk or negedge reset_n) begin    if (!reset_n) begin            uk2e70d <= 1'b0;    end    else if (txmac_clk_en) begin            uk2e70d <= ep362b6;    end
+end
+
+
+always @(kd5b522 or kdfd6d4 or dmcff5b         or en7fada) begin            casex({kd5b522, kdfd6d4})             2'bx0 : begin                         txd_pos[7:0] = 0;                         txd_neg[3:0] = 0;                         tx_er = 0;                         tx_en = 0;                        end             2'b11 : begin                         txd_pos[7:0] = dmcff5b[7:0];                         txd_neg[3:0] = dmcff5b[3:0];                         tx_er = en7fada;                         tx_en = kdfd6d4;                        end             2'b01 : begin                         txd_pos[7:0] = {4'h0, dmcff5b[3:0]};                         txd_neg[3:0] = dmcff5b[7:4];                         tx_er = en7fada;                         tx_en = kdfd6d4;                        end             default  : begin                         txd_pos[7:0] = 0;                         txd_neg[3:0] = 0;                         tx_er = 0;                         tx_en = 0;                        end             endcase
+end
+always@* begin hda0d8a<={hq11dba>>1,vv746d9[0]};xl6c56<=vv746d9[1];ep362b6<=vv746d9[2];kfb15b5<=vv746d9[3];ec346dc<=vv746d9[4];ui56d64<=vv746d9[5];qib6b21<=vv746d9[6];zzb5908<=vv746d9[7];ukac847<=vv746d9[8];bl64238<={rxd_pos>>1,vv746d9[9]};co211c7<={rxd_neg>>1,vv746d9[10]};mt8e39<=vv746d9[11];by471cd<=vv746d9[12];ph38e6b<=vv746d9[13];zxc735f<=vv746d9[14];yz39aff<=vv746d9[15];thcd7fd<=vv746d9[16];dz6bfee<=vv746d9[17];zx5ff77<=vv746d9[18];icffbbf<=vv746d9[19];qtfddf8<=vv746d9[20];me77e2b<={ng83b46>>1,vv746d9[21]};enf8ac7<={ened194>>1,vv746d9[22]};aa2b1ea<={ay46528>>1,vv746d9[23]};blc7a82<={ph283b7>>1,vv746d9[24]};meea0b6<={doedfd>>1,vv746d9[25]};pf505b0<=vv746d9[26];co82d87<=vv746d9[27];tj16c38<=vv746d9[28];ieb61c7<=vv746d9[29];rvb0e39<=vv746d9[30];ie871cf<=vv746d9[31];tj38e79<=vv746d9[32];fnc73cf<=vv746d9[33];ux39e7f<=vv746d9[34];lqcf3fd<=vv746d9[35];dmcff5b<={qgf0b9c>>1,vv746d9[36]};en7fada<=vv746d9[37];kdfd6d4<=vv746d9[38];faeb6a4<=vv746d9[39];kd5b522<=vv746d9[40];psda914<=vv746d9[41];god48a3<=vv746d9[42];gda4518<=vv746d9[43];tj228c5<=vv746d9[44];swa317b<={qv9a85e>>1,vv746d9[45]};gd18bd8<=vv746d9[46];zm2f623<={pubd4d>>1,vv746d9[47]};pf7b11a<={wj5ea6a>>1,vv746d9[48]};zxd88d7<={kqf5355>>1,vv746d9[49]};eac46be<=vv746d9[50];ir235f0<=vv746d9[51];co1af84<=vv746d9[52];jpd7c21<=vv746d9[53];irbe10f<=vv746d9[54];suf087d<=vv746d9[55];tj843e9<=vv746d9[56];wy21f4e<=vv746d9[57];ksfa70<=vv746d9[58];end
+always@* begin wy2e8db[2047]<=ph8edd2;wy2e8db[2046]<=vi76e96;wy2e8db[2044]<=tuf131a;wy2e8db[2040]<=tu58bae;wy2e8db[2033]<=rx_dv_pos;wy2e8db[2019]<=rx_dv_neg;wy2e8db[1994]<=uxd09a;wy2e8db[1990]<=rx_er_pos;wy2e8db[1981]<=dbbfa92;wy2e8db[1965]<=lf8b9eb;wy2e8db[1940]<=ic684d4;wy2e8db[1939]<=jebdab0;wy2e8db[1933]<=rx_er_neg;wy2e8db[1914]<=czfd496;wy2e8db[1883]<=os5cf5e;wy2e8db[1832]<=lq426a1;wy2e8db[1831]<=qt6ac1d;wy2e8db[1819]<=rxd_pos[0];wy2e8db[1785]<=zk73868;wy2e8db[1781]<=jc525a0;wy2e8db[1778]<=do11ded;wy2e8db[1740]<=ec15ef4;wy2e8db[1719]<=rv3d785;wy2e8db[1616]<=qv9a85e[0];wy2e8db[1615]<=ww560ed;wy2e8db[1591]<=rxd_neg[0];wy2e8db[1522]<=ri9c342;wy2e8db[1515]<=co92d02;wy2e8db[1508]<=jr8ef6a;wy2e8db[1470]<=cb85ce1;wy2e8db[1432]<=rvaf7a0;wy2e8db[1391]<=jcebc2e;wy2e8db[1286]<=kqf5355[0];wy2e8db[1271]<=ph283b7[0];wy2e8db[1184]<=osd42f5;wy2e8db[1182]<=ng83b46[0];wy2e8db[1135]<=sudbb02;wy2e8db[1051]<=vi4d540;wy2e8db[1023]<=hq11dba[0];wy2e8db[997]<=xwe1a13;wy2e8db[990]<=xyb7f52;wy2e8db[982]<=tw1173d;wy2e8db[969]<=yk77b56;wy2e8db[892]<=uk2e70d;wy2e8db[889]<=qv23bd;wy2e8db[870]<=ux2bde;wy2e8db[735]<=qgf0b9c[0];wy2e8db[643]<=wj5ea6a[0];wy2e8db[635]<=ay46528[0];wy2e8db[525]<=aaa9aa8;wy2e8db[495]<=doedfd[0];wy2e8db[444]<=thec08e;wy2e8db[435]<=zx4057b;wy2e8db[321]<=pubd4d[0];wy2e8db[317]<=ened194[0];wy2e8db[222]<=hbdd811;wy2e8db[217]<=doa80af;wy2e8db[108]<=pf55015;wy2e8db[54]<=sh6aa02;end         assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6<ksa36ce; dobd2d6=dobd2d6+1) begin dbc230[dobd2d6] = db84308[hq30de9]; hq86f4b = ^(hq30de9 & kf8c37[0]); hq30de9 = {hq30de9, hq86f4b}; end end 
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+`timescale 1 ns / 100 ps
+module tsmac_core (
+
+    
+    hclk,
+    txmac_clk,
+    rxmac_clk,
+    reset_n,
+
+       txmac_clk_en,
+       rxmac_clk_en,
+
+
+    
+        rxd,
+        rx_dv,
+        rx_er,
+
+        col,
+        crs,
+
+    
+    haddr,
+    hdatain,
+    hcs_n,
+    hwrite_n,
+    hread_n,
+
+    
+
+    
+    tx_fifodata,
+    tx_fifoavail,
+    tx_fifoeof,
+    tx_fifoempty,
+    tx_sndpaustim,
+    tx_sndpausreq,
+    tx_fifoctrl,
+
+    
+    rx_fifo_full,
+    ignore_pkt,
+
+    
+    tx_en,
+    tx_er,
+
+       txd,
+
+    
+    hdataout,
+    hdataout_en_n,
+    hready_n,
+    cpu_if_gbit_en,
+
+    
+
+    
+    tx_macread,
+    tx_discfrm,
+    tx_staten,
+    tx_statvec,
+    tx_done,
+
+    
+    rx_fifo_error,
+    rx_stat_vector,
+    rx_dbout,
+    rx_write,
+    rx_stat_en,
+    rx_eof,
+    rx_error
+)
+                
+ 
+;
+input                            hclk;
+input                            txmac_clk;
+input                            rxmac_clk;
+input                            reset_n;
+
+input                        txmac_clk_en;
+input                        rxmac_clk_en;
+
+
+
+input  [7:0]                 rxd;
+input                        rx_dv;
+input                        rx_er;
+
+
+input                         col;
+input                         crs;
+
+input  [7:0]                     haddr;
+input  [7:0]                     hdatain;
+input                            hcs_n;
+input                            hwrite_n;
+input                            hread_n;
+
+input  [7:0]                     tx_fifodata;
+input                            tx_fifoavail;
+input                            tx_fifoeof;
+input                            tx_fifoempty;
+input  [15:0]                    tx_sndpaustim;
+input                            tx_sndpausreq;
+input                            tx_fifoctrl;
+input                            rx_fifo_full;
+input                            ignore_pkt;
+
+output [7:0]                  txd;
+
+output                           tx_en;
+output                           tx_er;
+output [7:0]                     hdataout;
+output                           hdataout_en_n;
+output                           hready_n;
+output                           cpu_if_gbit_en;
+
+output                           tx_macread;
+output                           tx_discfrm;
+output                           tx_staten;
+output                           tx_done;
+output [30:0]                    tx_statvec;
+output                           rx_fifo_error;
+output [31:0]                    rx_stat_vector;
+output [7:0]                     rx_dbout;
+output                           rx_write;
+output                           rx_stat_en;
+output                           rx_eof;
+output                           rx_error;
+
+
+
+parameter pdevice_family = "ECP5UM";
+
+
+wire   [15:0]                    hod0a7b;
+wire                             oh853da;
+wire                             kf29ed4;
+wire   [8:0]                     ri99b0a;
+wire                             vvcd852;
+wire   [15:0]                    fada93f;
+wire                             ead49fb;
+wire                             qva4fd8;
+wire   [7:0]                     rv27ec4;
+wire                             ba3f627;
+wire                             psfb13b;
+wire                             zxd89db;
+wire                             eac4ede;
+wire                             nt276f1;
+wire  [4:0]                      qi3b78e;
+wire                             eadbc71;
+wire                             wwde389;
+wire                             hof1c48;
+wire                             jr8e243;
+wire                             fn7121f;
+wire                             ng890fe;
+wire                             fa487f2;
+wire                             su43f92;
+wire                             ou1fc90;
+wire  [13:0]                     zkfe481;
+wire [7:0]                       alf240b;
+wire [7:0]                       co9205d;
+wire [7:0]                       an902e8;
+wire [7:0]                       ph81745;
+wire [7:0]                       riba2e;
+wire [7:0]                       lq5d172;
+wire [7:0]                       cze8b93;
+wire [7:0]                       nr45c9c;
+wire  [15:0]                     ec2e4e7;
+wire  [47:0]                     ay72738;
+wire  [10:0]                     do939c1;
+wire  [15:0]                     ls9ce0b;
+wire                             yxe705a;
+wire  [7:0]                      db382d4;
+wire                             ayc16a6;
+wire                             bab530;
+wire                             th5a983;
+wire                             med4c1f;
+wire                             aaa60f8;
+wire                             ri307c0;
+
+wire                             xwc0484;
+wire                             ep2422;
+wire  [7:0]                      mt12115;
+wire  [3:0]                      cb908ac;
+wire                             bn84564;
+wire                             lf22b26;
+wire                             ec15937;
+wire                             ouac9b8;
+wire  [7:0]                      fn64dc0;
+wire  [3:0]                      gd26e06;
+
+
+
+
+
+
+
+
+
+
+reg ria7c68;
+reg [7 : 0] rgd5780;
+reg [7 : 0] en5e01d;
+reg lf3b04;
+reg oh80760;
+reg suf00ec;
+reg [7 : 0] zk732ec;
+reg vidf659;
+reg vk99763;
+reg cmcbb1b;
+reg [15 : 0] uvfd919;
+reg ps63f64;
+reg vi5d8d8;
+reg hoc0b68;
+reg gbf2dc6;
+reg [15 : 0] jccae98;
+reg zk574c2;
+reg dbba612;
+reg [8 : 0] gq34f1d;
+reg zma78e9;
+reg [15 : 0] zxc25e1;
+reg yz12f0f;
+reg wy9787d;
+reg [7 : 0] gqbc3e9;
+reg zke1f48;
+reg iefa42;
+reg qg7d210;
+reg dze9080;
+reg xw48407;
+reg [4 : 0] ho4203a;
+reg ie101d3;
+reg an80e99;
+reg gd74cd;
+reg ba3a66d;
+reg qtd336b;
+reg hq99b5c;
+reg thcdae2;
+reg ea6d717;
+reg hb6b8b9;
+reg [13 : 0] cm5c5cf;
+reg [7 : 0] ipe2e79;
+reg [7 : 0] ir173cd;
+reg [7 : 0] ukb9e6c;
+reg [7 : 0] lqcf361;
+reg [7 : 0] tu79b0b;
+reg [7 : 0] fncd85b;
+reg [7 : 0] xw6c2df;
+reg [7 : 0] dz616fb;
+reg [15 : 0] twb7df;
+reg [47 : 0] gb5befb;
+reg [10 : 0] nedf7dd;
+reg [15 : 0] nefbeea;
+reg dmdf752;
+reg [7 : 0] lqfba92;
+reg pfdd492;
+reg goea497;
+reg rg524b8;
+reg ou925c2;
+reg qi92e10;
+reg ks97081;
+reg lsb8408;
+reg pfc2042;
+reg [7 : 0] uk10217;
+reg [3 : 0] tj810b9;
+reg yz85ce;
+reg ps42e74;
+reg sj173a2;
+reg wyb9d14;
+reg [7 : 0] ayce8a1;
+reg [3 : 0] hb74508;
+reg [2047:0] wy2e8db;
+wire [69:0] vv746d9;
+
+
+
+
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+
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+
+
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+
+
+
+localparam ksa36ce = 70,tw1b670 = 32'hfdffe0cb;
+localparam [31:0] icdb382 = tw1b670;
+localparam mece084 = tw1b670 & 4'hf;
+localparam [11:0] ou8210c = 'h7ff;
+wire [(1 << mece084) -1:0] db84308;
+reg [ksa36ce-1:0] dbc230;
+reg [mece084-1:0] kf8c37 [0:1];
+reg [mece084-1:0] hq30de9;
+reg hq86f4b;
+integer hd37a5a;
+integer dobd2d6;
+
+
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+
+
+        
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+
+
+
+
+            
+
+
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+
+
+      
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+   
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+
+
+       assign xwc0484 = txmac_clk_en;  assign ep2422 = rxmac_clk_en;
+
+
+
+
+
+       assign mt12115   = rxd; assign cb908ac   = 4'h0;        assign bn84564 = rx_dv; assign lf22b26 = 1'b0;  assign ec15937 = rx_er; assign ouac9b8 = 1'b0;  assign txd            = ayce8a1;
+
+
+
+
+
+tja0af6 #(.pdevice_family(pdevice_family))
+eacb06b (        .rxmac_clk(rxmac_clk),    .reset_n(ria7c68),    .rxmac_clk_en(pfc2042),        .mrf282b(rg524b8),    .xy304af(uk3122a),    .tj9415c(lqfba92),    .aa8257a(goea497),    .gd12bd1(pfdd492),    .kf95e8d(ou925c2),        .su43606(ipe2e79),    .tw1b031(ir173cd),    .ldd818a(ukb9e6c),    .byc0c57(lqcf361),    .ph62bb(tu79b0b),    .uk315df(fncd85b),    .ep8aef8(xw6c2df),    .lq577c4(dz616fb),    .uxbbe22(gb5befb),    .hodf114(ba3a66d),    .shf88a2(qtd336b),    .uic4515(thcdae2),    .ep90e3c(twb7df),    .thddac5(ea6d717),    .kded62e(hq99b5c),    .dz6b175(cm5c5cf),    .tu58bae(hb6b8b9),    .jcc5d72(gd74cd),    .ym2eb93(an80e99),        .rx_fifo_full(hoc0b68),    .ignore_pkt(gbf2dc6),        .ba93361(kf29ed4),    .sw10140(hod0a7b),    .cb80a01(oh853da),    .ri99b0a(ri99b0a),    .vvcd852(vvcd852),        .vk308df(fada93f),    .uka5df(ead49fb),        .rx_fifo_error(rx_fifo_error),    .rx_stat_vector(rx_stat_vector),    .rx_dbout(rx_dbout),    .rx_write(rx_write),    .rx_stat_en(rx_stat_en),    .rx_eof(rx_eof),    .rx_error(rx_error)
+);
+wwc1ddb #(.pdevice_family(pdevice_family))
+db84c39 (        .txmac_clk(txmac_clk),                   .zxc8e70(ria7c68),                         .txmac_clk_en(lsb8408),        .wl3cdf4(qg7d210),              .dze6fa5(dze9080),              .mtbe97e(xw48407),           .vx37d2f(ie101d3),                .ou8d15c(ho4203a),                  .me68ae0(gb5befb),            .dz7e8f3(twb7df),         .tx_fifodata(zk732ec),                .tx_fifoeof(vk99763),                  .tx_fifoempty(cmcbb1b),              .tx_fifoavail(vidf659),              .tx_sndpaustim(uvfd919),            .tx_sndpausreq(ps63f64),            .tx_fifoctrl(vi5d8d8),                    .kq493c2(yz12f0f),        .go49e10(zxc25e1),               .rva5fa3(ks97081),                   .vif4bf4(qi92e10),                       .xjc2078(psfb13b),        .tx_macread(tx_macread),                  .tx_discfrm(tx_discfrm),                  .tx_staten(tx_staten),                    .tx_statvec(tx_statvec),                  .tx_done(tx_done),                            .fncd202(qva4fd8),               .tu69016(rv27ec4),           .vi480b3(ba3f627)                
+);
+    twb7994 dbaf28f (                .txmac_clk(txmac_clk),        .rxmac_clk(rxmac_clk),        .reset_n(ria7c68),        .rxmac_clk_en(pfc2042),        .txmac_clk_en(lsb8408),                .hq11dba(gqbc3e9),        .ph8edd2(zke1f48),        .vi76e96(wy9787d),                .rx_dv_pos(yz85ce),        .rx_dv_neg(ps42e74),        .rx_er_pos(sj173a2),        .rx_er_neg(wyb9d14),        .rxd_pos(uk10217),        .rxd_neg(tj810b9),
+
+
+   .col(col),   .crs(crs),
+
+
+
+                .tuf131a(cpu_if_gbit_en),        .tu58bae(hb6b8b9),                .gd12bd1(ayc16a6),        .aa8257a(bab530),        .mrf282b(th5a983),        .xy304af(uk3122a),        .tj9415c(db382d4),        .kf95e8d(med4c1f),         .cb9fe9b(aaa60f8),        .goff4dd(ri307c0),                .txd_pos(fn64dc0),        .txd_neg(gd26e06),        .tx_en(tx_en),        .tx_er(tx_er)    );
+
+wya61c7 qia32d (        .hclk(hclk),    .reset_n(ria7c68),        .haddr(rgd5780),    .hdatain(en5e01d),    .hread_n(suf00ec),    .hwrite_n(oh80760),    .hcs_n(lf3b04),        .sw10140(jccae98),    .cb80a01(zk574c2),    .ba93361(dbba612),    .ri99b0a(gq34f1d),    .vvcd852(zma78e9),        .dzc2191(iefa42),    
+
+
+
+        .hdataout(hdataout),    .hready_n(hready_n),    .hdataout_en_n(hdataout_en_n),        .tx_en(zxd89db),    .sjae511(eac4ede),    .ic7288c(nt276f1),    .ou8d15c(qi3b78e),    .tuf131a(cpu_if_gbit_en),    .vx37d2f(eadbc71),
+    
+
+
+
+        .ym2eb93(wwde389),    .jcc5d72(hof1c48),    .ri1e263(ay72738),    .pu8c1d2(jr8e243),    .shf88a2(fn7121f),    .kded62e(ng890fe),    .uic4515(fa487f2),    .thddac5(su43f92),    .dz6b175(zkfe481),    .tu58bae(ou1fc90),    .ep90e3c(ec2e4e7),    .xy3a4a5(alf240b),    .ldd252b(co9205d),    .sw9295e(an902e8),    .db94af1(ph81745),    .jra578e(riba2e),    .ou2bc77(lq5d172),    .ip5e3b9(cze8b93),    .zkf1dcc(nr45c9c)
+);
+
+
+
+always@* begin ria7c68<=vv746d9[0];rgd5780<={haddr>>1,vv746d9[1]};en5e01d<={hdatain>>1,vv746d9[2]};lf3b04<=vv746d9[3];oh80760<=vv746d9[4];suf00ec<=vv746d9[5];zk732ec<={tx_fifodata>>1,vv746d9[6]};vidf659<=vv746d9[7];vk99763<=vv746d9[8];cmcbb1b<=vv746d9[9];uvfd919<={tx_sndpaustim>>1,vv746d9[10]};ps63f64<=vv746d9[11];vi5d8d8<=vv746d9[12];hoc0b68<=vv746d9[13];gbf2dc6<=vv746d9[14];jccae98<={hod0a7b>>1,vv746d9[15]};zk574c2<=vv746d9[16];dbba612<=vv746d9[17];gq34f1d<={ri99b0a>>1,vv746d9[18]};zma78e9<=vv746d9[19];zxc25e1<={fada93f>>1,vv746d9[20]};yz12f0f<=vv746d9[21];wy9787d<=vv746d9[22];gqbc3e9<={rv27ec4>>1,vv746d9[23]};zke1f48<=vv746d9[24];iefa42<=vv746d9[25];qg7d210<=vv746d9[26];dze9080<=vv746d9[27];xw48407<=vv746d9[28];ho4203a<={qi3b78e>>1,vv746d9[29]};ie101d3<=vv746d9[30];an80e99<=vv746d9[31];gd74cd<=vv746d9[32];ba3a66d<=vv746d9[33];qtd336b<=vv746d9[34];hq99b5c<=vv746d9[35];thcdae2<=vv746d9[36];ea6d717<=vv746d9[37];hb6b8b9<=vv746d9[38];cm5c5cf<={zkfe481>>1,vv746d9[39]};ipe2e79<={alf240b>>1,vv746d9[40]};ir173cd<={co9205d>>1,vv746d9[41]};ukb9e6c<={an902e8>>1,vv746d9[42]};lqcf361<={ph81745>>1,vv746d9[43]};tu79b0b<={riba2e>>1,vv746d9[44]};fncd85b<={lq5d172>>1,vv746d9[45]};xw6c2df<={cze8b93>>1,vv746d9[46]};dz616fb<={nr45c9c>>1,vv746d9[47]};twb7df<={ec2e4e7>>1,vv746d9[48]};gb5befb<={ay72738>>1,vv746d9[49]};nedf7dd<={do939c1>>1,vv746d9[50]};nefbeea<={ls9ce0b>>1,vv746d9[51]};dmdf752<=vv746d9[52];lqfba92<={db382d4>>1,vv746d9[53]};pfdd492<=vv746d9[54];goea497<=vv746d9[55];rg524b8<=vv746d9[56];ou925c2<=vv746d9[57];qi92e10<=vv746d9[58];ks97081<=vv746d9[59];lsb8408<=vv746d9[60];pfc2042<=vv746d9[61];uk10217<={mt12115>>1,vv746d9[62]};tj810b9<={cb908ac>>1,vv746d9[63]};yz85ce<=vv746d9[64];ps42e74<=vv746d9[65];sj173a2<=vv746d9[66];wyb9d14<=vv746d9[67];ayce8a1<={fn64dc0>>1,vv746d9[68]};hb74508<={gd26e06>>1,vv746d9[69]};end
+always@* begin wy2e8db[2047]<=haddr[0];wy2e8db[2046]<=hdatain[0];wy2e8db[2044]<=hcs_n;wy2e8db[2041]<=db382d4[0];wy2e8db[2040]<=hwrite_n;wy2e8db[2035]<=ayc16a6;wy2e8db[2033]<=hread_n;wy2e8db[2024]<=ead49fb;wy2e8db[2022]<=bab530;wy2e8db[2018]<=tx_fifodata[0];wy2e8db[2001]<=qva4fd8;wy2e8db[1997]<=th5a983;wy2e8db[1988]<=tx_fifoavail;wy2e8db[1954]<=rv27ec4[0];wy2e8db[1946]<=med4c1f;wy2e8db[1929]<=tx_fifoeof;wy2e8db[1874]<=ng890fe;wy2e8db[1860]<=ba3f627;wy2e8db[1851]<=fn64dc0[0];wy2e8db[1845]<=aaa60f8;wy2e8db[1811]<=tx_fifoempty;wy2e8db[1789]<=ri99b0a[0];wy2e8db[1721]<=cb908ac[0];wy2e8db[1700]<=fa487f2;wy2e8db[1673]<=psfb13b;wy2e8db[1655]<=gd26e06[0];wy2e8db[1643]<=ri307c0;wy2e8db[1574]<=tx_sndpaustim[0];wy2e8db[1530]<=vvcd852;wy2e8db[1486]<=ec15937;wy2e8db[1395]<=bn84564;wy2e8db[1353]<=su43f92;wy2e8db[1317]<=zkfe481[0];wy2e8db[1311]<=nr45c9c[0];wy2e8db[1299]<=zxd89db;wy2e8db[1258]<=hof1c48;wy2e8db[1247]<=hod0a7b[0];wy2e8db[1239]<=xwc0484;wy2e8db[1187]<=riba2e[0];wy2e8db[1172]<=co9205d[0];wy2e8db[1151]<=ay72738[0];wy2e8db[1102]<=nt276f1;wy2e8db[1101]<=tx_sndpausreq;wy2e8db[1023]<=reset_n;wy2e8db[1020]<=yxe705a;wy2e8db[1012]<=fada93f[0];wy2e8db[937]<=fn7121f;wy2e8db[925]<=ouac9b8;wy2e8db[894]<=kf29ed4;wy2e8db[860]<=mt12115[0];wy2e8db[743]<=lf22b26;wy2e8db[658]<=ou1fc90;wy2e8db[655]<=cze8b93[0];wy2e8db[629]<=wwde389;wy2e8db[623]<=ignore_pkt;wy2e8db[593]<=ph81745[0];wy2e8db[586]<=alf240b[0];wy2e8db[575]<=ec2e4e7[0];wy2e8db[551]<=eac4ede;wy2e8db[510]<=ls9ce0b[0];wy2e8db[468]<=jr8e243;wy2e8db[447]<=oh853da;wy2e8db[430]<=ep2422;wy2e8db[327]<=lq5d172[0];wy2e8db[314]<=eadbc71;wy2e8db[311]<=rx_fifo_full;wy2e8db[296]<=an902e8[0];wy2e8db[255]<=do939c1[0];wy2e8db[157]<=qi3b78e[0];wy2e8db[155]<=tx_fifoctrl;end         assign db84308 = wy2e8db,vv746d9 = dbc230; initial begin hd37a5a = $fopen(".fred"); $fdisplay( hd37a5a, "%3h\n%3h", (icdb382 >> 4) & ou8210c, (icdb382 >> (mece084+4)) & ou8210c ); $fclose(hd37a5a); $readmemh(".fred", kf8c37); end always @ (db84308) begin hq30de9 = kf8c37[1]; for (dobd2d6=0; dobd2d6<ksa36ce; dobd2d6=dobd2d6+1) begin dbc230[dobd2d6] = db84308[hq30de9]; hq86f4b = ^(hq30de9 & kf8c37[0]); hq30de9 = {hq30de9, hq86f4b}; end end 
+endmodule
+

diff --git a/gbe/cores/sgmii/tsmac/tsmac_inst.v b/gbe/cores/sgmii/tsmac/tsmac_inst.v
new file mode 100644 (file)
index 0000000..61cf48e
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/tsmac_inst.v
@@ -0,0 +1,77 @@
+//=============================================================================\r
+// Verilog module generated by IPExpress    \r
+// Filename: USERNAME_inst.v                                          \r
+// Copyright(c) 2006 Lattice Semiconductor Corporation. All rights reserved.   \r
+//=============================================================================\r
+\r
+/* WARNING - Changes to this file should be performed by re-running IPexpress\r
+or modifying the .LPC file and regenerating the core.  Other changes may lead\r
+to inconsistent simulation and/or implemenation results */\r
+     tsmac DUT_INST ( \r
+\r
+         // clock and reset\r
+         .hclk(hclk),\r
+         .txmac_clk(txmac_clk),\r
+         .rxmac_clk(rxmac_clk),\r
+         .reset_n(reset_n),\r
+         .txmac_clk_en(txmac_clk_en),\r
+         .rxmac_clk_en(rxmac_clk_en),\r
+     \r
+         // Input signals to the GMII\r
+         .rxd(rxd),\r
+         .rx_dv(rx_dv),\r
+         .rx_er(rx_er),\r
+         .col(col),\r
+         .crs(crs),\r
+     \r
+         // Input signals to the CPU Interface\r
+         .haddr(haddr),\r
+         .hdatain(hdatain),\r
+         .hcs_n(hcs_n),\r
+         .hwrite_n(hwrite_n),\r
+         .hread_n(hread_n),\r
+     \r
+         // Input signals to the MII Management Interface\r
+     \r
+         // Input signals to the Tx MAC FIFO Interface\r
+         .tx_fifodata(tx_fifodata),\r
+         .tx_fifoavail(tx_fifoavail),\r
+         .tx_fifoeof(tx_fifoeof),\r
+         .tx_fifoempty(tx_fifoempty),\r
+         .tx_sndpaustim(tx_sndpaustim),\r
+         .tx_sndpausreq(tx_sndpausreq),\r
+         .tx_fifoctrl(tx_fifoctrl),\r
+     \r
+         // Input signals to the Rx MAC FIFO Interface\r
+         .rx_fifo_full(rx_fifo_full),\r
+         .ignore_pkt(ignore_pkt),\r
+     \r
+         // Output signals from the GMII\r
+         .txd(txd),\r
+         .tx_en(tx_en),\r
+         .tx_er(tx_er),\r
+     \r
+         // Output signals from the CPU Interface\r
+         .hdataout(hdataout),\r
+         .hdataout_en_n(hdataout_en_n),\r
+         .hready_n(hready_n),\r
+         .cpu_if_gbit_en(cpu_if_gbit_en),\r
+     \r
+         // Output signals from the MII Management Interface\r
+     \r
+         // Output signals from the Tx MAC FIFO Interface\r
+         .tx_macread(tx_macread),\r
+         .tx_discfrm(tx_discfrm),\r
+         .tx_staten(tx_staten),\r
+         .tx_statvec(tx_statvec),\r
+         .tx_done(tx_done),\r
+     \r
+         // Output signals from the Rx MAC FIFO Interface\r
+         .rx_fifo_error(rx_fifo_error),\r
+         .rx_stat_vector(rx_stat_vector),\r
+         .rx_dbout(rx_dbout),\r
+         .rx_write(rx_write),\r
+         .rx_stat_en(rx_stat_en),\r
+         .rx_eof(rx_eof),\r
+         .rx_error(rx_error)\r
+     );\r

diff --git a/gbe/cores/sgmii/tsmac/tsmac_ngd.asd b/gbe/cores/sgmii/tsmac/tsmac_ngd.asd
new file mode 100644 (file)
index 0000000..412ffed
--- /dev/null
+++ b/gbe/cores/sgmii/tsmac/tsmac_ngd.asd
@@ -0,0 +1,2 @@
+[ActiveSupport NGD]
+IP_1 = LSC_IP_SC_HT_TSMAC

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/sgmii_ecp5.cmd b/gbe/cores/test_gbepcs/sgmii_ecp5/sgmii_ecp5.cmd
new file mode 100644 (file)
index 0000000..a5a9d84
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/sgmii_ecp5.cmd
@@ -0,0 +1,18 @@
+PROJECT: sgmii_ecp5
+               working_path: "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results"
+               module: sgmii_ecp5
+               verilog_file_list: "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd" "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v"
+               vlog_std_v2001: true
+               constraint_file_name: "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.fdc"
+               suffix_name: edn
+               output_file_name: sgmii_ecp5
+               write_prf: true
+               disable_io_insertion: true
+               force_gsr: false
+               frequency: 100
+               fanout_limit: 50
+               retiming: false
+               pipe: false
+               part: LFE5UM-85F
+               speed_grade: 8
+               

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/sgmii_ecp5.fdc b/gbe/cores/test_gbepcs/sgmii_ecp5/sgmii_ecp5.fdc
new file mode 100644 (file)
index 0000000..6fbcac9
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/sgmii_ecp5.fdc
@@ -0,0 +1,2 @@
+###==== Start Configuration
+

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/sgmii_ecp5.lpc b/gbe/cores/test_gbepcs/sgmii_ecp5/sgmii_ecp5.lpc
new file mode 100644 (file)
index 0000000..0639dc2
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/sgmii_ecp5.lpc
@@ -0,0 +1,97 @@
+[Device]
+Family=ecp5um
+OperatingCondition=COM
+Package=CABGA756
+PartName=LFE5UM-85F-8BG756C
+PartType=LFE5UM-85F
+SpeedGrade=8
+Status=P
+[IP]
+CoreName=PCS
+CoreRevision=8.2
+CoreStatus=Demo
+CoreType=LPM
+Date=05/10/2019
+ModuleName=sgmii_ecp5
+ParameterFileVersion=1.0
+SourceFormat=VHDL
+Time=11:58:52
+VendorName=Lattice Semiconductor Corporation
+[Parameters]
+;ACHARA=0 00H
+;ACHARB=0 00H
+;ACHARM=0 00H
+;RXMCAENABLE=Disabled
+CDRLOLACTION=Full Recalibration
+CDRLOLRANGE=0
+CDR_MAX_RATE=2
+CDR_MULT=10X
+CDR_REF_RATE=200.0000
+CH_MODE=Rx and Tx
+Destination=Synplicity
+EDIF=1
+Expression=BusA(0 to 7)
+IO=0
+IO_TYPE=GbE
+LEQ=0
+LOOPBACK=Disabled
+LOSPORT=Enabled
+NUM_CHS=1
+Order=Big Endian [MSB:LSB]
+PPORT_RX_RDY=Enabled
+PPORT_TX_RDY=Enabled
+PROTOCOL=GbE
+PWAIT_RX_RDY=3000
+PWAIT_TX_RDY=3000
+RCSRC=Disabled
+REFCLK_RATE=200.0000
+RSTSEQSEL=Enabled
+RX8B10B=Enabled
+RXCOMMAA=1010000011
+RXCOMMAB=0101111100
+RXCOMMAM=1111111111
+RXCOUPLING=AC
+RXCTC=Enabled
+RXCTCBYTEN=0 00H
+RXCTCBYTEN1=0 00H
+RXCTCBYTEN2=1 BCH
+RXCTCBYTEN3=0 50H
+RXCTCMATCHPATTERN=M2-S2
+RXDIFFTERM=50 ohms
+RXFIFO_ENABLE=Enabled
+RXINVPOL=Non-invert
+RXLDR=Off
+RXLOSTHRESHOLD=2
+RXLSM=Enabled
+RXSC=K28P5
+RXWA=Barrel Shift
+RX_DATA_WIDTH=8/10-Bit
+RX_FICLK_RATE=200.0000
+RX_LINE_RATE=2.0000
+RX_RATE_DIV=Full Rate
+SCIPORT=Enabled
+SOFTLOL=Enabled
+TX8B10B=Enabled
+TXAMPLITUDE=1100
+TXDEPOST=Disabled
+TXDEPRE=Disabled
+TXDIFFTERM=50 ohms
+TXFIFO_ENABLE=Enabled
+TXINVPOL=Non-invert
+TXLDR=Off
+TXPLLLOLTHRESHOLD=0
+TXPLLMULT=10X
+TX_DATA_WIDTH=8/10-Bit
+TX_FICLK_RATE=200.0000
+TX_LINE_RATE=2.0000
+TX_MAX_RATE=2
+TX_RATE_DIV=Full Rate
+VHDL=1
+Verilog=0
+[FilesGenerated]
+sgmii_ecp5.pp=pp
+sgmii_ecp5.sym=sym
+sgmii_ecp5.tft=tft
+sgmii_ecp5.txt=pcs_module
+[SYSTEMPNR]
+LN0=DCU1_CH1

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/sgmii_ecp5.ngd b/gbe/cores/test_gbepcs/sgmii_ecp5/sgmii_ecp5.ngd
new file mode 100644 (file)
index 0000000..ce30a67
Binary files /dev/null and b/gbe/cores/test_gbepcs/sgmii_ecp5/sgmii_ecp5.ngd differ

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/sgmii_ecp5.ngo b/gbe/cores/test_gbepcs/sgmii_ecp5/sgmii_ecp5.ngo
new file mode 100644 (file)
index 0000000..af052b7
Binary files /dev/null and b/gbe/cores/test_gbepcs/sgmii_ecp5/sgmii_ecp5.ngo differ

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd b/gbe/cores/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd
new file mode 100644 (file)
index 0000000..361fb8b
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd
@@ -0,0 +1,433 @@
+
+--
+-- Verific VHDL Description of module DCUA
+--
+
+-- DCUA is a black-box. Cannot print a valid VHDL entity description for it
+
+--
+-- Verific VHDL Description of module sgmii_ecp5rsl_core
+--
+
+-- sgmii_ecp5rsl_core is a black-box. Cannot print a valid VHDL entity description for it
+
+--
+-- Verific VHDL Description of module sgmii_ecp5sll_core
+--
+
+-- sgmii_ecp5sll_core is a black-box. Cannot print a valid VHDL entity description for it
+
+--
+-- Verific VHDL Description of module sgmii_ecp5
+--
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+library ecp5um ;
+use ecp5um.components.all ;
+
+entity sgmii_ecp5 is
+    port (hdoutp: out std_logic;
+        hdoutn: out std_logic;
+        hdinp: in std_logic;
+        hdinn: in std_logic;
+        rxrefclk: in std_logic;
+        tx_pclk: out std_logic;
+        txi_clk: in std_logic;
+        txdata: in std_logic_vector(7 downto 0);
+        tx_k: in std_logic_vector(0 downto 0);
+        xmit: in std_logic_vector(0 downto 0);
+        tx_disp_correct: in std_logic_vector(0 downto 0);
+        rxdata: out std_logic_vector(7 downto 0);
+        rx_k: out std_logic_vector(0 downto 0);
+        rx_disp_err: out std_logic_vector(0 downto 0);
+        rx_cv_err: out std_logic_vector(0 downto 0);
+        signal_detect_c: in std_logic;
+        rx_los_low_s: out std_logic;
+        lsm_status_s: out std_logic;
+        ctc_urun_s: out std_logic;
+        ctc_orun_s: out std_logic;
+        rx_cdr_lol_s: out std_logic;
+        ctc_ins_s: out std_logic;
+        ctc_del_s: out std_logic;
+        sli_rst: in std_logic;
+        tx_pwrup_c: in std_logic;
+        rx_pwrup_c: in std_logic;
+        sci_wrdata: in std_logic_vector(7 downto 0);
+        sci_addr: in std_logic_vector(5 downto 0);
+        sci_rddata: out std_logic_vector(7 downto 0);
+        sci_en_dual: in std_logic;
+        sci_sel_dual: in std_logic;
+        sci_en: in std_logic;
+        sci_sel: in std_logic;
+        sci_rd: in std_logic;
+        sci_wrn: in std_logic;
+        sci_int: out std_logic;
+        cyawstn: in std_logic;
+        serdes_pdb: in std_logic;
+        pll_refclki: in std_logic;
+        rsl_disable: in std_logic;
+        rsl_rst: in std_logic;
+        serdes_rst_dual_c: in std_logic;
+        rst_dual_c: in std_logic;
+        tx_serdes_rst_c: in std_logic;
+        tx_pcs_rst_c: in std_logic;
+        pll_lol: out std_logic;
+        rsl_tx_rdy: out std_logic;
+        rx_serdes_rst_c: in std_logic;
+        rx_pcs_rst_c: in std_logic;
+        rsl_rx_rdy: out std_logic
+    );
+    
+end entity sgmii_ecp5;
+
+architecture v1 of sgmii_ecp5 is 
+    component sgmii_ecp5rsl_core is
+        generic (pnum_channels: integer := 1;
+            pprotocol: string := "GBE";
+            pserdes_mode: string := "RX AND TX";
+            pport_tx_rdy: string := "ENABLED";
+            pwait_tx_rdy: integer := 3000;
+            pport_rx_rdy: string := "ENABLED";
+            pwait_rx_rdy: integer := 3000);
+        port (rui_rst: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(132)
+            rui_serdes_rst_dual_c: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(133)
+            rui_rst_dual_c: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(134)
+            rui_rsl_disable: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(135)
+            rui_tx_ref_clk: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(137)
+            rui_tx_serdes_rst_c: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(138)
+            rui_tx_pcs_rst_c: in std_logic_vector(3 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(139)
+            rdi_pll_lol: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(140)
+            rui_rx_ref_clk: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(142)
+            rui_rx_serdes_rst_c: in std_logic_vector(3 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(143)
+            rui_rx_pcs_rst_c: in std_logic_vector(3 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(144)
+            rdi_rx_los_low_s: in std_logic_vector(3 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(145)
+            rdi_rx_cdr_lol_s: in std_logic_vector(3 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(146)
+            rdo_serdes_rst_dual_c: out std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(149)
+            rdo_rst_dual_c: out std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(150)
+            ruo_tx_rdy: out std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(152)
+            rdo_tx_serdes_rst_c: out std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(153)
+            rdo_tx_pcs_rst_c: out std_logic_vector(3 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(154)
+            ruo_rx_rdy: out std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(156)
+            rdo_rx_serdes_rst_c: out std_logic_vector(3 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(157)
+            rdo_rx_pcs_rst_c: out std_logic_vector(3 downto 0)   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(158)
+        );
+        
+    end component sgmii_ecp5rsl_core; -- syn_black_box=1    -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(88)
+    component sgmii_ecp5sll_core is
+        generic (PPROTOCOL: string := "GBE";
+            PLOL_SETTING: integer := 0;
+            PDYN_RATE_CTRL: string := "DISABLED";
+            PPCIE_MAX_RATE: string := "2.5";
+            PDIFF_VAL_LOCK: integer := 19;
+            PDIFF_VAL_UNLOCK: integer := 39;
+            PPCLK_TC: integer := 65536;
+            PDIFF_DIV11_VAL_LOCK: integer := 0;
+            PDIFF_DIV11_VAL_UNLOCK: integer := 0;
+            PPCLK_DIV11_TC: integer := 0);
+        port (sli_rst: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(125)
+            sli_refclk: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(126)
+            sli_pclk: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(127)
+            sli_div2_rate: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(128)
+            sli_div11_rate: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(129)
+            sli_gear_mode: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(130)
+            sli_cpri_mode: in std_logic_vector(2 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(131)
+            sli_pcie_mode: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(132)
+            slo_plol: out std_logic   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(135)
+        );
+        
+    end component sgmii_ecp5sll_core; -- syn_black_box=1    -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(107)
+    signal n45,n44,n1,n2,n3,n4,tx_pclk_c,n5,n6,n7,n8,n9,n10,n11,
+        n12,n13,rx_los_low_s_c,n14,n15,rx_cdr_lol_s_c,rsl_tx_pcs_rst_c,
+        rsl_rx_pcs_rst_c,rsl_rx_serdes_rst_c,rsl_rst_dual_c,rsl_serdes_rst_dual_c,
+        rsl_tx_serdes_rst_c,n16,n17,n18,n19,n20,n21,n22,n23,n24,n25,
+        n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37,n38,n39,
+        n40,n41,n42,n43,n46,n103,n102,n47,n48,n49,n50,n51,n52,n53,
+        n54,n55,n56,n57,n58,n59,n60,n61,n62,n63,n64,n65,n66,n67,
+        n68,n69,n70,n71,n72,n73,n74,n75,n76,n77,n78,n79,n80,n81,
+        n82,n83,n84,n85,n86,n87,n88,n89,n90,n91,n92,n93,n94,n95,
+        n96,n97,n98,n99,n100,n101,n112,n111,n110,pll_lol_c,n122,n121,
+        n113,n114,n115,n116,n117,n118,n119,n120,\_Z\,n124,n123,gnd,
+        pwr : std_logic; 
+    attribute LOC : string;
+    attribute LOC of DCU1_inst : label is "DCU1";
+    attribute CHAN : string;
+    attribute CHAN of DCU1_inst : label is "CH1";
+begin
+    tx_pclk <= tx_pclk_c;
+    rx_los_low_s <= rx_los_low_s_c;
+    rx_cdr_lol_s <= rx_cdr_lol_s_c;
+    pll_lol <= pll_lol_c;
+    DCU1_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1",
+        D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0",
+        D_CDR_LOL_SET=>"0b00",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1",
+        D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1",
+        D_SYNC_ND_EN=>"0b0",CH1_UC_MODE=>"0b0",CH1_PCIE_MODE=>"0b0",CH1_RIO_MODE=>"0b0",
+        CH1_WA_MODE=>"0b0",CH1_INVERT_RX=>"0b0",CH1_INVERT_TX=>"0b0",CH1_PRBS_SELECTION=>"0b0",
+        CH1_GE_AN_ENABLE=>"0b0",CH1_PRBS_LOCK=>"0b0",CH1_PRBS_ENABLE=>"0b0",
+        CH1_ENABLE_CG_ALIGN=>"0b1",CH1_TX_GEAR_MODE=>"0b0",CH1_RX_GEAR_MODE=>"0b0",
+        CH1_PCS_DET_TIME_SEL=>"0b00",CH1_PCIE_EI_EN=>"0b0",CH1_TX_GEAR_BYPASS=>"0b0",
+        CH1_ENC_BYPASS=>"0b0",CH1_SB_BYPASS=>"0b0",CH1_RX_SB_BYPASS=>"0b0",
+        CH1_WA_BYPASS=>"0b0",CH1_DEC_BYPASS=>"0b0",CH1_CTC_BYPASS=>"0b0",
+        CH1_RX_GEAR_BYPASS=>"0b0",CH1_LSM_DISABLE=>"0b0",CH1_MATCH_2_ENABLE=>"0b1",
+        CH1_MATCH_4_ENABLE=>"0b0",CH1_MIN_IPG_CNT=>"0b11",CH1_CC_MATCH_1=>"0x000",
+        CH1_CC_MATCH_2=>"0x000",CH1_CC_MATCH_3=>"0x1BC",CH1_CC_MATCH_4=>"0x050",
+        CH1_UDF_COMMA_MASK=>"0x3ff",CH1_UDF_COMMA_A=>"0x283",CH1_UDF_COMMA_B=>"0x17C",
+        CH1_RX_DCO_CK_DIV=>"0b000",CH1_RCV_DCC_EN=>"0b0",CH1_TPWDNB=>"0b1",
+        CH1_RATE_MODE_TX=>"0b0",CH1_RTERM_TX=>"0d19",CH1_TX_CM_SEL=>"0b00",
+        CH1_TDRV_PRE_EN=>"0b0",CH1_TDRV_SLICE0_SEL=>"0b01",CH1_TDRV_SLICE1_SEL=>"0b00",
+        CH1_TDRV_SLICE2_SEL=>"0b01",CH1_TDRV_SLICE3_SEL=>"0b01",CH1_TDRV_SLICE4_SEL=>"0b01",
+        CH1_TDRV_SLICE5_SEL=>"0b01",CH1_TDRV_SLICE0_CUR=>"0b101",CH1_TDRV_SLICE1_CUR=>"0b000",
+        CH1_TDRV_SLICE2_CUR=>"0b11",CH1_TDRV_SLICE3_CUR=>"0b11",CH1_TDRV_SLICE4_CUR=>"0b11",
+        CH1_TDRV_SLICE5_CUR=>"0b00",CH1_TDRV_DAT_SEL=>"0b00",CH1_TX_DIV11_SEL=>"0b0",
+        CH1_RPWDNB=>"0b1",CH1_RATE_MODE_RX=>"0b0",CH1_RX_DIV11_SEL=>"0b0",
+        CH1_SEL_SD_RX_CLK=>"0b0",CH1_FF_RX_H_CLK_EN=>"0b0",CH1_FF_RX_F_CLK_DIS=>"0b0",
+        CH1_FF_TX_H_CLK_EN=>"0b0",CH1_FF_TX_F_CLK_DIS=>"0b0",CH1_TDRV_POST_EN=>"0b0",
+        CH1_TX_POST_SIGN=>"0b0",CH1_TX_PRE_SIGN=>"0b0",CH1_REQ_LVL_SET=>"0b00",
+        CH1_REQ_EN=>"0b1",CH1_RTERM_RX=>"0d22",CH1_RXTERM_CM=>"0b11",CH1_PDEN_SEL=>"0b1",
+        CH1_RXIN_CM=>"0b11",CH1_LEQ_OFFSET_SEL=>"0b0",CH1_LEQ_OFFSET_TRIM=>"0b000",
+        CH1_RLOS_SEL=>"0b1",CH1_RX_LOS_LVL=>"0b010",CH1_RX_LOS_CEQ=>"0b11",
+        CH1_RX_LOS_HYST_EN=>"0b0",CH1_RX_LOS_EN=>"0b1",CH1_LDR_RX2CORE_SEL=>"0b0",
+        CH1_LDR_CORE2TX_SEL=>"0b0",D_TX_MAX_RATE=>"2",CH1_CDR_MAX_RATE=>"2",
+        CH1_TXAMPLITUDE=>"0d1100",CH1_TXDEPRE=>"DISABLED",CH1_TXDEPOST=>"DISABLED",
+        CH1_PROTOCOL=>"GBE",D_ISETLOS=>"0d0",D_SETIRPOLY_AUX=>"0b00",D_SETICONST_AUX=>"0b00",
+        D_SETIRPOLY_CH=>"0b00",D_SETICONST_CH=>"0b00",D_REQ_ISET=>"0b000",
+        D_PD_ISET=>"0b00",D_DCO_CALIB_TIME_SEL=>"0b00",CH1_CDR_CNT4SEL=>"0b00",
+        CH1_CDR_CNT8SEL=>"0b00",CH1_DCOATDCFG=>"0b00",CH1_DCOATDDLY=>"0b00",
+        CH1_DCOBYPSATD=>"0b1",CH1_DCOCALDIV=>"0b001",CH1_DCOCTLGI=>"0b010",
+        CH1_DCODISBDAVOID=>"0b0",CH1_DCOFLTDAC=>"0b01",CH1_DCOFTNRG=>"0b110",
+        CH1_DCOIOSTUNE=>"0b000",CH1_DCOITUNE=>"0b00",CH1_DCOITUNE4LSB=>"0b111",
+        CH1_DCOIUPDNX2=>"0b1",CH1_DCONUOFLSB=>"0b101",CH1_DCOSCALEI=>"0b00",
+        CH1_DCOSTARTVAL=>"0b000",CH1_DCOSTEP=>"0b00",CH1_BAND_THRESHOLD=>"0d0",
+        CH1_AUTO_FACQ_EN=>"0b1",CH1_AUTO_CALIB_EN=>"0b1",CH1_CALIB_CK_MODE=>"0b0",
+        CH1_REG_BAND_OFFSET=>"0d0",CH1_REG_BAND_SEL=>"0d0",CH1_REG_IDAC_SEL=>"0d0",
+        CH1_REG_IDAC_EN=>"0b0",D_CMUSETISCL4VCO=>"0b000",D_CMUSETI4VCO=>"0b00",
+        D_CMUSETINITVCT=>"0b00",D_CMUSETZGM=>"0b000",D_CMUSETP2AGM=>"0b000",
+        D_CMUSETP1GM=>"0b000",D_CMUSETI4CPZ=>"0d3",D_CMUSETI4CPP=>"0d3",D_CMUSETICP4Z=>"0b101",
+        D_CMUSETICP4P=>"0b01",D_CMUSETBIASI=>"0b00",D_SETPLLRC=>"0d1",CH1_RX_RATE_SEL=>"0d8",
+        D_REFCK_MODE=>"0b001",D_TX_VCO_CK_DIV=>"0b000",D_PLL_LOL_SET=>"0b00",
+        D_RG_EN=>"0b0",D_RG_SET=>"0b00")
+     port map (CH0_HDINP=>n103,CH1_HDINP=>hdinp,CH0_HDINN=>n103,CH1_HDINN=>hdinn,
+    D_TXBIT_CLKP_FROM_ND=>n44,D_TXBIT_CLKN_FROM_ND=>n44,D_SYNC_ND=>n44,D_TXPLL_LOL_FROM_ND=>n44,
+    CH0_RX_REFCLK=>n103,CH1_RX_REFCLK=>rxrefclk,CH0_FF_RXI_CLK=>n102,CH1_FF_RXI_CLK=>tx_pclk_c,
+    CH0_FF_TXI_CLK=>n102,CH1_FF_TXI_CLK=>txi_clk,CH0_FF_EBRD_CLK=>n102,CH1_FF_EBRD_CLK=>tx_pclk_c,
+    CH0_FF_TX_D_0=>n103,CH1_FF_TX_D_0=>txdata(0),CH0_FF_TX_D_1=>n103,CH1_FF_TX_D_1=>txdata(1),
+    CH0_FF_TX_D_2=>n103,CH1_FF_TX_D_2=>txdata(2),CH0_FF_TX_D_3=>n103,CH1_FF_TX_D_3=>txdata(3),
+    CH0_FF_TX_D_4=>n103,CH1_FF_TX_D_4=>txdata(4),CH0_FF_TX_D_5=>n103,CH1_FF_TX_D_5=>txdata(5),
+    CH0_FF_TX_D_6=>n103,CH1_FF_TX_D_6=>txdata(6),CH0_FF_TX_D_7=>n103,CH1_FF_TX_D_7=>txdata(7),
+    CH0_FF_TX_D_8=>n103,CH1_FF_TX_D_8=>tx_k(0),CH0_FF_TX_D_9=>n103,CH1_FF_TX_D_9=>n44,
+    CH0_FF_TX_D_10=>n103,CH1_FF_TX_D_10=>xmit(0),CH0_FF_TX_D_11=>n103,CH1_FF_TX_D_11=>tx_disp_correct(0),
+    CH0_FF_TX_D_12=>n103,CH1_FF_TX_D_12=>n103,CH0_FF_TX_D_13=>n103,CH1_FF_TX_D_13=>n103,
+    CH0_FF_TX_D_14=>n103,CH1_FF_TX_D_14=>n103,CH0_FF_TX_D_15=>n103,CH1_FF_TX_D_15=>n103,
+    CH0_FF_TX_D_16=>n103,CH1_FF_TX_D_16=>n103,CH0_FF_TX_D_17=>n103,CH1_FF_TX_D_17=>n103,
+    CH0_FF_TX_D_18=>n103,CH1_FF_TX_D_18=>n103,CH0_FF_TX_D_19=>n103,CH1_FF_TX_D_19=>n103,
+    CH0_FF_TX_D_20=>n103,CH1_FF_TX_D_20=>n103,CH0_FF_TX_D_21=>n103,CH1_FF_TX_D_21=>n44,
+    CH0_FF_TX_D_22=>n103,CH1_FF_TX_D_22=>n103,CH0_FF_TX_D_23=>n103,CH1_FF_TX_D_23=>n103,
+    CH0_FFC_EI_EN=>n103,CH1_FFC_EI_EN=>n44,CH0_FFC_PCIE_DET_EN=>n103,CH1_FFC_PCIE_DET_EN=>n44,
+    CH0_FFC_PCIE_CT=>n103,CH1_FFC_PCIE_CT=>n44,CH0_FFC_SB_INV_RX=>n103,CH1_FFC_SB_INV_RX=>n103,
+    CH0_FFC_ENABLE_CGALIGN=>n103,CH1_FFC_ENABLE_CGALIGN=>n103,CH0_FFC_SIGNAL_DETECT=>n103,
+    CH1_FFC_SIGNAL_DETECT=>signal_detect_c,CH0_FFC_FB_LOOPBACK=>n103,CH1_FFC_FB_LOOPBACK=>n44,
+    CH0_FFC_SB_PFIFO_LP=>n103,CH1_FFC_SB_PFIFO_LP=>n44,CH0_FFC_PFIFO_CLR=>n103,
+    CH1_FFC_PFIFO_CLR=>n44,CH0_FFC_RATE_MODE_RX=>n103,CH1_FFC_RATE_MODE_RX=>n44,
+    CH0_FFC_RATE_MODE_TX=>n103,CH1_FFC_RATE_MODE_TX=>n44,CH0_FFC_DIV11_MODE_RX=>n103,
+    CH1_FFC_DIV11_MODE_RX=>n44,CH0_FFC_DIV11_MODE_TX=>n103,CH1_FFC_DIV11_MODE_TX=>n44,
+    CH0_FFC_RX_GEAR_MODE=>n103,CH1_FFC_RX_GEAR_MODE=>n44,CH0_FFC_TX_GEAR_MODE=>n103,
+    CH1_FFC_TX_GEAR_MODE=>n44,CH0_FFC_LDR_CORE2TX_EN=>n103,CH1_FFC_LDR_CORE2TX_EN=>n103,
+    CH0_FFC_LANE_TX_RST=>n103,CH1_FFC_LANE_TX_RST=>rsl_tx_pcs_rst_c,CH0_FFC_LANE_RX_RST=>n103,
+    CH1_FFC_LANE_RX_RST=>rsl_rx_pcs_rst_c,CH0_FFC_RRST=>n103,CH1_FFC_RRST=>rsl_rx_serdes_rst_c,
+    CH0_FFC_TXPWDNB=>n103,CH1_FFC_TXPWDNB=>tx_pwrup_c,CH0_FFC_RXPWDNB=>n103,
+    CH1_FFC_RXPWDNB=>rx_pwrup_c,CH0_LDR_CORE2TX=>n103,CH1_LDR_CORE2TX=>n103,
+    D_SCIWDATA0=>sci_wrdata(0),D_SCIWDATA1=>sci_wrdata(1),D_SCIWDATA2=>sci_wrdata(2),
+    D_SCIWDATA3=>sci_wrdata(3),D_SCIWDATA4=>sci_wrdata(4),D_SCIWDATA5=>sci_wrdata(5),
+    D_SCIWDATA6=>sci_wrdata(6),D_SCIWDATA7=>sci_wrdata(7),D_SCIADDR0=>sci_addr(0),
+    D_SCIADDR1=>sci_addr(1),D_SCIADDR2=>sci_addr(2),D_SCIADDR3=>sci_addr(3),
+    D_SCIADDR4=>sci_addr(4),D_SCIADDR5=>sci_addr(5),D_SCIENAUX=>sci_en_dual,
+    D_SCISELAUX=>sci_sel_dual,CH0_SCIEN=>n103,CH1_SCIEN=>sci_en,CH0_SCISEL=>n103,
+    CH1_SCISEL=>sci_sel,D_SCIRD=>sci_rd,D_SCIWSTN=>sci_wrn,D_CYAWSTN=>cyawstn,
+    D_FFC_SYNC_TOGGLE=>n103,D_FFC_DUAL_RST=>rsl_rst_dual_c,D_FFC_MACRO_RST=>rsl_serdes_rst_dual_c,
+    D_FFC_MACROPDB=>serdes_pdb,D_FFC_TRST=>rsl_tx_serdes_rst_c,CH0_FFC_CDR_EN_BITSLIP=>n103,
+    CH1_FFC_CDR_EN_BITSLIP=>n44,D_SCAN_ENABLE=>n44,D_SCAN_IN_0=>n44,D_SCAN_IN_1=>n44,
+    D_SCAN_IN_2=>n44,D_SCAN_IN_3=>n44,D_SCAN_IN_4=>n44,D_SCAN_IN_5=>n44,
+    D_SCAN_IN_6=>n44,D_SCAN_IN_7=>n44,D_SCAN_MODE=>n44,D_SCAN_RESET=>n44,
+    D_CIN0=>n44,D_CIN1=>n44,D_CIN2=>n44,D_CIN3=>n44,D_CIN4=>n44,D_CIN5=>n44,
+    D_CIN6=>n44,D_CIN7=>n44,D_CIN8=>n44,D_CIN9=>n44,D_CIN10=>n44,D_CIN11=>n44,
+    CH0_HDOUTP=>n47,CH1_HDOUTP=>hdoutp,CH0_HDOUTN=>n48,CH1_HDOUTN=>hdoutn,
+    D_TXBIT_CLKP_TO_ND=>n1,D_TXBIT_CLKN_TO_ND=>n2,D_SYNC_PULSE2ND=>n3,D_TXPLL_LOL_TO_ND=>n4,
+    CH0_FF_RX_F_CLK=>n49,CH1_FF_RX_F_CLK=>n5,CH0_FF_RX_H_CLK=>n50,CH1_FF_RX_H_CLK=>n6,
+    CH0_FF_TX_F_CLK=>n51,CH1_FF_TX_F_CLK=>n7,CH0_FF_TX_H_CLK=>n52,CH1_FF_TX_H_CLK=>n8,
+    CH0_FF_RX_PCLK=>n53,CH1_FF_RX_PCLK=>n9,CH0_FF_TX_PCLK=>n54,CH1_FF_TX_PCLK=>tx_pclk_c,
+    CH0_FF_RX_D_0=>n55,CH1_FF_RX_D_0=>rxdata(0),CH0_FF_RX_D_1=>n56,CH1_FF_RX_D_1=>rxdata(1),
+    CH0_FF_RX_D_2=>n57,CH1_FF_RX_D_2=>rxdata(2),CH0_FF_RX_D_3=>n58,CH1_FF_RX_D_3=>rxdata(3),
+    CH0_FF_RX_D_4=>n59,CH1_FF_RX_D_4=>rxdata(4),CH0_FF_RX_D_5=>n60,CH1_FF_RX_D_5=>rxdata(5),
+    CH0_FF_RX_D_6=>n61,CH1_FF_RX_D_6=>rxdata(6),CH0_FF_RX_D_7=>n62,CH1_FF_RX_D_7=>rxdata(7),
+    CH0_FF_RX_D_8=>n63,CH1_FF_RX_D_8=>rx_k(0),CH0_FF_RX_D_9=>n64,CH1_FF_RX_D_9=>rx_disp_err(0),
+    CH0_FF_RX_D_10=>n65,CH1_FF_RX_D_10=>rx_cv_err(0),CH0_FF_RX_D_11=>n66,
+    CH1_FF_RX_D_11=>n10,CH0_FF_RX_D_12=>n67,CH1_FF_RX_D_12=>n68,CH0_FF_RX_D_13=>n69,
+    CH1_FF_RX_D_13=>n70,CH0_FF_RX_D_14=>n71,CH1_FF_RX_D_14=>n72,CH0_FF_RX_D_15=>n73,
+    CH1_FF_RX_D_15=>n74,CH0_FF_RX_D_16=>n75,CH1_FF_RX_D_16=>n76,CH0_FF_RX_D_17=>n77,
+    CH1_FF_RX_D_17=>n78,CH0_FF_RX_D_18=>n79,CH1_FF_RX_D_18=>n80,CH0_FF_RX_D_19=>n81,
+    CH1_FF_RX_D_19=>n82,CH0_FF_RX_D_20=>n83,CH1_FF_RX_D_20=>n84,CH0_FF_RX_D_21=>n85,
+    CH1_FF_RX_D_21=>n86,CH0_FF_RX_D_22=>n87,CH1_FF_RX_D_22=>n88,CH0_FF_RX_D_23=>n89,
+    CH1_FF_RX_D_23=>n11,CH0_FFS_PCIE_DONE=>n90,CH1_FFS_PCIE_DONE=>n12,CH0_FFS_PCIE_CON=>n91,
+    CH1_FFS_PCIE_CON=>n13,CH0_FFS_RLOS=>n92,CH1_FFS_RLOS=>rx_los_low_s_c,
+    CH0_FFS_LS_SYNC_STATUS=>n93,CH1_FFS_LS_SYNC_STATUS=>lsm_status_s,CH0_FFS_CC_UNDERRUN=>n94,
+    CH1_FFS_CC_UNDERRUN=>ctc_urun_s,CH0_FFS_CC_OVERRUN=>n95,CH1_FFS_CC_OVERRUN=>ctc_orun_s,
+    CH0_FFS_RXFBFIFO_ERROR=>n96,CH1_FFS_RXFBFIFO_ERROR=>n14,CH0_FFS_TXFBFIFO_ERROR=>n97,
+    CH1_FFS_TXFBFIFO_ERROR=>n15,CH0_FFS_RLOL=>n98,CH1_FFS_RLOL=>rx_cdr_lol_s_c,
+    CH0_FFS_SKP_ADDED=>n99,CH1_FFS_SKP_ADDED=>ctc_ins_s,CH0_FFS_SKP_DELETED=>n100,
+    CH1_FFS_SKP_DELETED=>ctc_del_s,CH0_LDR_RX2CORE=>n101,CH1_LDR_RX2CORE=>n112,
+    D_SCIRDATA0=>sci_rddata(0),D_SCIRDATA1=>sci_rddata(1),D_SCIRDATA2=>sci_rddata(2),
+    D_SCIRDATA3=>sci_rddata(3),D_SCIRDATA4=>sci_rddata(4),D_SCIRDATA5=>sci_rddata(5),
+    D_SCIRDATA6=>sci_rddata(6),D_SCIRDATA7=>sci_rddata(7),D_SCIINT=>sci_int,
+    D_SCAN_OUT_0=>n16,D_SCAN_OUT_1=>n17,D_SCAN_OUT_2=>n18,D_SCAN_OUT_3=>n19,
+    D_SCAN_OUT_4=>n20,D_SCAN_OUT_5=>n21,D_SCAN_OUT_6=>n22,D_SCAN_OUT_7=>n23,
+    D_COUT0=>n24,D_COUT1=>n25,D_COUT2=>n26,D_COUT3=>n27,D_COUT4=>n28,D_COUT5=>n29,
+    D_COUT6=>n30,D_COUT7=>n31,D_COUT8=>n32,D_COUT9=>n33,D_COUT10=>n34,D_COUT11=>n35,
+    D_COUT12=>n36,D_COUT13=>n37,D_COUT14=>n38,D_COUT15=>n39,D_COUT16=>n40,
+    D_COUT17=>n41,D_COUT18=>n42,D_COUT19=>n43,D_REFCLKI=>pll_refclki,D_FFS_PLOL=>n46);
+    n45 <= '1' ;
+    n44 <= '0' ;
+    n1 <= 'Z' ;
+    n2 <= 'Z' ;
+    n3 <= 'Z' ;
+    n4 <= 'Z' ;
+    n5 <= 'Z' ;
+    n6 <= 'Z' ;
+    n7 <= 'Z' ;
+    n8 <= 'Z' ;
+    n9 <= 'Z' ;
+    n10 <= 'Z' ;
+    n11 <= 'Z' ;
+    n12 <= 'Z' ;
+    n13 <= 'Z' ;
+    n14 <= 'Z' ;
+    n15 <= 'Z' ;
+    n16 <= 'Z' ;
+    n17 <= 'Z' ;
+    n18 <= 'Z' ;
+    n19 <= 'Z' ;
+    n20 <= 'Z' ;
+    n21 <= 'Z' ;
+    n22 <= 'Z' ;
+    n23 <= 'Z' ;
+    n24 <= 'Z' ;
+    n25 <= 'Z' ;
+    n26 <= 'Z' ;
+    n27 <= 'Z' ;
+    n28 <= 'Z' ;
+    n29 <= 'Z' ;
+    n30 <= 'Z' ;
+    n31 <= 'Z' ;
+    n32 <= 'Z' ;
+    n33 <= 'Z' ;
+    n34 <= 'Z' ;
+    n35 <= 'Z' ;
+    n36 <= 'Z' ;
+    n37 <= 'Z' ;
+    n38 <= 'Z' ;
+    n39 <= 'Z' ;
+    n40 <= 'Z' ;
+    n41 <= 'Z' ;
+    n42 <= 'Z' ;
+    n43 <= 'Z' ;
+    n46 <= 'Z' ;
+    n103 <= '0' ;
+    n102 <= '1' ;
+    n47 <= 'Z' ;
+    n48 <= 'Z' ;
+    n49 <= 'Z' ;
+    n50 <= 'Z' ;
+    n51 <= 'Z' ;
+    n52 <= 'Z' ;
+    n53 <= 'Z' ;
+    n54 <= 'Z' ;
+    n55 <= 'Z' ;
+    n56 <= 'Z' ;
+    n57 <= 'Z' ;
+    n58 <= 'Z' ;
+    n59 <= 'Z' ;
+    n60 <= 'Z' ;
+    n61 <= 'Z' ;
+    n62 <= 'Z' ;
+    n63 <= 'Z' ;
+    n64 <= 'Z' ;
+    n65 <= 'Z' ;
+    n66 <= 'Z' ;
+    n67 <= 'Z' ;
+    n68 <= 'Z' ;
+    n69 <= 'Z' ;
+    n70 <= 'Z' ;
+    n71 <= 'Z' ;
+    n72 <= 'Z' ;
+    n73 <= 'Z' ;
+    n74 <= 'Z' ;
+    n75 <= 'Z' ;
+    n76 <= 'Z' ;
+    n77 <= 'Z' ;
+    n78 <= 'Z' ;
+    n79 <= 'Z' ;
+    n80 <= 'Z' ;
+    n81 <= 'Z' ;
+    n82 <= 'Z' ;
+    n83 <= 'Z' ;
+    n84 <= 'Z' ;
+    n85 <= 'Z' ;
+    n86 <= 'Z' ;
+    n87 <= 'Z' ;
+    n88 <= 'Z' ;
+    n89 <= 'Z' ;
+    n90 <= 'Z' ;
+    n91 <= 'Z' ;
+    n92 <= 'Z' ;
+    n93 <= 'Z' ;
+    n94 <= 'Z' ;
+    n95 <= 'Z' ;
+    n96 <= 'Z' ;
+    n97 <= 'Z' ;
+    n98 <= 'Z' ;
+    n99 <= 'Z' ;
+    n100 <= 'Z' ;
+    n101 <= 'Z' ;
+    n112 <= 'Z' ;
+    rsl_inst: component sgmii_ecp5rsl_core port map (rui_rst=>rsl_rst,rui_serdes_rst_dual_c=>serdes_rst_dual_c,
+            rui_rst_dual_c=>rst_dual_c,rui_rsl_disable=>rsl_disable,rui_tx_ref_clk=>pll_refclki,
+            rui_tx_serdes_rst_c=>tx_serdes_rst_c,rui_tx_pcs_rst_c(3)=>n122,
+            rui_tx_pcs_rst_c(2)=>n122,rui_tx_pcs_rst_c(1)=>n122,rui_tx_pcs_rst_c(0)=>tx_pcs_rst_c,
+            rdi_pll_lol=>pll_lol_c,rui_rx_ref_clk=>rxrefclk,rui_rx_serdes_rst_c(3)=>n122,
+            rui_rx_serdes_rst_c(2)=>n122,rui_rx_serdes_rst_c(1)=>n122,rui_rx_serdes_rst_c(0)=>rx_serdes_rst_c,
+            rui_rx_pcs_rst_c(3)=>n122,rui_rx_pcs_rst_c(2)=>n122,rui_rx_pcs_rst_c(1)=>n122,
+            rui_rx_pcs_rst_c(0)=>rx_pcs_rst_c,rdi_rx_los_low_s(3)=>n122,rdi_rx_los_low_s(2)=>n122,
+            rdi_rx_los_low_s(1)=>n122,rdi_rx_los_low_s(0)=>rx_los_low_s_c,
+            rdi_rx_cdr_lol_s(3)=>n122,rdi_rx_cdr_lol_s(2)=>n122,rdi_rx_cdr_lol_s(1)=>n122,
+            rdi_rx_cdr_lol_s(0)=>rx_cdr_lol_s_c,rdo_serdes_rst_dual_c=>rsl_serdes_rst_dual_c,
+            rdo_rst_dual_c=>rsl_rst_dual_c,ruo_tx_rdy=>rsl_tx_rdy,rdo_tx_serdes_rst_c=>rsl_tx_serdes_rst_c,
+            rdo_tx_pcs_rst_c(3)=>n113,rdo_tx_pcs_rst_c(2)=>n114,rdo_tx_pcs_rst_c(1)=>n115,
+            rdo_tx_pcs_rst_c(0)=>rsl_tx_pcs_rst_c,ruo_rx_rdy=>rsl_rx_rdy,rdo_rx_serdes_rst_c(3)=>n116,
+            rdo_rx_serdes_rst_c(2)=>n117,rdo_rx_serdes_rst_c(1)=>n118,rdo_rx_serdes_rst_c(0)=>rsl_rx_serdes_rst_c,
+            rdo_rx_pcs_rst_c(3)=>n119,rdo_rx_pcs_rst_c(2)=>n120,rdo_rx_pcs_rst_c(1)=>\_Z\,
+            rdo_rx_pcs_rst_c(0)=>rsl_rx_pcs_rst_c);
+    n111 <= '1' ;
+    n110 <= '0' ;
+    n122 <= '0' ;
+    n121 <= '1' ;
+    n113 <= 'Z' ;
+    n114 <= 'Z' ;
+    n115 <= 'Z' ;
+    n116 <= 'Z' ;
+    n117 <= 'Z' ;
+    n118 <= 'Z' ;
+    n119 <= 'Z' ;
+    n120 <= 'Z' ;
+    \_Z\ <= 'Z' ;
+    sll_inst: component sgmii_ecp5sll_core port map (sli_rst=>sli_rst,sli_refclk=>pll_refclki,
+            sli_pclk=>tx_pclk_c,sli_div2_rate=>gnd,sli_div11_rate=>gnd,sli_gear_mode=>gnd,
+            sli_cpri_mode(2)=>gnd,sli_cpri_mode(1)=>gnd,sli_cpri_mode(0)=>gnd,
+            sli_pcie_mode=>gnd,slo_plol=>pll_lol_c);
+    n124 <= '1' ;
+    n123 <= '0' ;
+    gnd <= '0' ;
+    pwr <= '1' ;
+    
+end architecture v1;
+

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/sgmii_ecp5_ngd.asd b/gbe/cores/test_gbepcs/sgmii_ecp5/sgmii_ecp5_ngd.asd
new file mode 100644 (file)
index 0000000..c265c78
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/sgmii_ecp5_ngd.asd
@@ -0,0 +1 @@
+[ActiveSupport NGD]

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v b/gbe/cores/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v
new file mode 100644 (file)
index 0000000..69a023d
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v
@@ -0,0 +1,2003 @@
+
+
+//   ===========================================================================
+//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
+//   ---------------------------------------------------------------------------
+//   Copyright (c) 2016 by Lattice Semiconductor Corporation
+//   ALL RIGHTS RESERVED
+//   ------------------------------------------------------------------
+//
+//   Permission:
+//
+//      Lattice SG Pte. Ltd. grants permission to use this code
+//      pursuant to the terms of the Lattice Reference Design License Agreement.
+//
+//
+//   Disclaimer:
+//
+//      This VHDL or Verilog source code is intended as a design reference
+//      which illustrates how these types of functions can be implemented.
+//      It is the user's responsibility to verify their design for
+//      consistency and functionality through the use of formal
+//      verification methods.  Lattice provides no warranty
+//      regarding the use or functionality of this code.
+//
+//   ---------------------------------------------------------------------------
+//
+//                  Lattice SG Pte. Ltd.
+//                  101 Thomson Road, United Square #07-02
+//                  Singapore 307591
+//
+//
+//                  TEL: 1-800-Lattice (USA and Canada)
+//                       +65-6631-2000 (Singapore)
+//                       +1-503-268-8001 (other locations)
+//
+//                  web: http://www.latticesemi.com/
+//                  email: techsupport@latticesemi.com
+//
+//   ---------------------------------------------------------------------------
+//
+// =============================================================================
+//                         FILE DETAILS
+// Project               : RSL- Reset Sequence Logic
+// File                  : rsl_core.v
+// Title                 : Top-level file for RSL
+// Dependencies          : 1.
+//                       : 2.
+// Description           :
+// =============================================================================
+//                        REVISION HISTORY
+// Version               : 1.0
+// Author(s)             : BM
+// Mod. Date             : October 28, 2013
+// Changes Made          : Initial Creation
+// -----------------------------------------------------------------------------
+// Version               : 1.1
+// Author(s)             : BM
+// Mod. Date             : November 06, 2013
+// Changes Made          : Tx/Rx separation, ready port code exclusion
+// -----------------------------------------------------------------------------
+// Version               : 1.2
+// Author(s)             : BM
+// Mod. Date             : June 13, 2014
+// Changes Made          : Updated Rx PCS reset method
+// -----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
+// Version               : 1.3
+// Author(s)             : UA
+// Mod. Date             : Dec 19, 2014
+// Changes Made          : Added new parameter fro PCIE
+// -----------------------------------------------------------------------------
+// Version               : 1.31
+// Author(s)             : BM/UM
+// Mod. Date             : Feb 23, 2016
+// Changes Made          : Behavior of rx_rdy output modified. The output rx_rdy
+//                         and the rx_rdy wait counter are reset to zero on
+//                         LOL or LOS. Reverted back the counter value change for PCIE.
+// -----------------------------------------------------------------------------
+// Version               : 1.4
+// Author(s)             : EB
+// Mod. Date:            : March 21, 2017
+// Changes Made          :
+// -----------------------------------------------------------------------------
+// Version               : 1.5
+// Author(s)             : ES
+// Mod. Date:            : May 8, 2017
+// Changes Made          : Implemented common RSL behaviour as proposed by BM.
+// =============================================================================
+
+`timescale 1ns/10ps
+
+module sgmii_ecp5rsl_core (
+      // ------------ Inputs
+      // Common
+      rui_rst,               // Active high reset for the RSL module
+      rui_serdes_rst_dual_c, // SERDES macro reset user command
+      rui_rst_dual_c,        // PCS dual reset user command
+      rui_rsl_disable,       // Active high signal that disables all reset outputs of RSL
+      // Tx
+      rui_tx_ref_clk,        // Tx reference clock
+      rui_tx_serdes_rst_c,   // Tx SERDES reset user command
+      rui_tx_pcs_rst_c,      // Tx lane reset user command
+      rdi_pll_lol,           // Tx PLL Loss of Lock status input from the SERDES
+      // Rx
+      rui_rx_ref_clk,        // Rx reference clock
+      rui_rx_serdes_rst_c,   // SERDES Receive channel reset user command
+      rui_rx_pcs_rst_c,      // Rx lane reset user command
+      rdi_rx_los_low_s,      // Receive loss of signal status input from SERDES
+      rdi_rx_cdr_lol_s,      // Receive CDR loss of lock status input from SERDES
+
+      // ------------ Outputs
+      // Common
+      rdo_serdes_rst_dual_c, // SERDES macro reset command output
+      rdo_rst_dual_c,        // PCS dual reset command output
+      // Tx
+      ruo_tx_rdy,            // Tx lane ready status output
+      rdo_tx_serdes_rst_c,   // SERDES Tx reset command output
+      rdo_tx_pcs_rst_c,      // PCS Tx lane reset command output
+      // Rx
+      ruo_rx_rdy,            // Rx lane ready status output
+      rdo_rx_serdes_rst_c,   // SERDES Rx channel reset command output
+      rdo_rx_pcs_rst_c       // PCS Rx lane reset command output
+      );
+
+// ------------ Module parameters
+`ifdef NUM_CHANNELS
+   parameter pnum_channels = `NUM_CHANNELS;    // 1,2,4
+`else
+   parameter pnum_channels = 1;
+`endif
+
+`ifdef PCIE
+   parameter pprotocol    = "PCIE";
+`else
+   parameter pprotocol    = "";
+`endif
+
+`ifdef RX_ONLY
+   parameter pserdes_mode    = "RX ONLY";
+`else
+   `ifdef TX_ONLY
+      parameter pserdes_mode = "TX ONLY";
+   `else
+      parameter pserdes_mode = "RX AND TX";
+   `endif
+`endif
+
+`ifdef PORT_TX_RDY
+   parameter pport_tx_rdy = "ENABLED";
+`else
+   parameter pport_tx_rdy = "DISABLED";
+`endif
+
+`ifdef WAIT_TX_RDY
+   parameter pwait_tx_rdy = `WAIT_TX_RDY;
+`else
+   parameter pwait_tx_rdy = 3000;
+`endif
+
+`ifdef PORT_RX_RDY
+   parameter pport_rx_rdy = "ENABLED";
+`else
+   parameter pport_rx_rdy = "DISABLED";
+`endif
+
+`ifdef WAIT_RX_RDY
+   parameter pwait_rx_rdy = `WAIT_RX_RDY;
+`else
+   parameter pwait_rx_rdy = 3000;
+`endif
+
+// ------------ Local parameters
+   localparam wa_num_cycles      = 1024;
+   localparam dac_num_cycles     = 3;
+   localparam lreset_pwidth      = 3;      // reset pulse width-1, default=4-1=3
+   localparam lwait_b4_trst      = 781250; // 5ms wait with worst-case Fmax=156 MHz
+   localparam lwait_b4_trst_s    = 781;    // for simulation
+   localparam lplol_cnt_width    = 20;     // width for lwait_b4_trst
+   localparam lwait_after_plol0  = 4;
+   localparam lwait_b4_rrst      = 180224; // total calibration time
+   localparam lrrst_wait_width   = 20;
+   localparam lwait_after_rrst   = 800000; // For CPRI- unused
+   localparam lwait_b4_rrst_s    = 460;    // wait cycles provided by design team
+   localparam lrlol_cnt_width    = 19;     // width for lwait_b4_rrst
+   localparam lwait_after_lols   = (16384 * dac_num_cycles) + wa_num_cycles;  // 16384 cycles * dac_num_cycles + 1024 cycles
+   localparam lwait_after_lols_s = 150;    // wait cycles provided by design team
+   localparam llols_cnt_width    = 18;     // lols count width
+   localparam lrdb_max           = 15;     // maximum debounce count
+   localparam ltxr_wait_width    = 12;     // width of tx ready wait counter
+   localparam lrxr_wait_width    = 12;     // width of tx ready wait counter
+
+// ------------ input ports
+   input                         rui_rst;
+   input                         rui_serdes_rst_dual_c;
+   input                         rui_rst_dual_c;
+   input                         rui_rsl_disable;
+
+   input                         rui_tx_ref_clk;
+   input                         rui_tx_serdes_rst_c;
+   input  [3:0]                  rui_tx_pcs_rst_c;
+   input                         rdi_pll_lol;
+
+   input                         rui_rx_ref_clk;
+   input  [3:0]                  rui_rx_serdes_rst_c;
+   input  [3:0]                  rui_rx_pcs_rst_c;
+   input  [3:0]                  rdi_rx_los_low_s;
+   input  [3:0]                  rdi_rx_cdr_lol_s;
+
+// ------------ output ports
+   output                        rdo_serdes_rst_dual_c;
+   output                        rdo_rst_dual_c;
+
+   output                        ruo_tx_rdy;
+   output                        rdo_tx_serdes_rst_c;
+   output [3:0]                  rdo_tx_pcs_rst_c;
+
+   output                        ruo_rx_rdy;
+   output [3:0]                  rdo_rx_serdes_rst_c;
+   output [3:0]                  rdo_rx_pcs_rst_c;
+
+// ------------ Internal registers and wires
+   // inputs
+   wire                          rui_rst;
+   wire                          rui_serdes_rst_dual_c;
+   wire                          rui_rst_dual_c;
+   wire                          rui_rsl_disable;
+   wire                          rui_tx_ref_clk;
+   wire                          rui_tx_serdes_rst_c;
+   wire   [3:0]                  rui_tx_pcs_rst_c;
+   wire                          rdi_pll_lol;
+   wire                          rui_rx_ref_clk;
+   wire   [3:0]                  rui_rx_serdes_rst_c;
+   wire   [3:0]                  rui_rx_pcs_rst_c;
+   wire   [3:0]                  rdi_rx_los_low_s;
+   wire   [3:0]                  rdi_rx_cdr_lol_s;
+
+   // outputs
+   wire                          rdo_serdes_rst_dual_c;
+   wire                          rdo_rst_dual_c;
+   wire                          ruo_tx_rdy;
+   wire                          rdo_tx_serdes_rst_c;
+   wire   [3:0]                  rdo_tx_pcs_rst_c;
+   wire                          ruo_rx_rdy;
+   wire   [3:0]                  rdo_rx_serdes_rst_c;
+   wire   [3:0]                  rdo_rx_pcs_rst_c;
+
+   // internal signals
+   // common
+   wire                          rsl_enable;
+   wire   [lplol_cnt_width-1:0]  wait_b4_trst;
+   wire   [lrlol_cnt_width-1:0]  wait_b4_rrst;
+   wire   [llols_cnt_width-1:0]  wait_after_lols;
+   reg                           pll_lol_p1;
+   reg                           pll_lol_p2;
+   reg                           pll_lol_p3;
+   // ------------ Tx
+   // rdo_tx_serdes_rst_c
+   reg    [lplol_cnt_width-1:0]  plol_cnt;
+   wire                          plol_cnt_tc;
+
+   reg    [2:0]                  txs_cnt;
+   reg                           txs_rst;
+   wire                          txs_cnt_tc;
+   // rdo_tx_pcs_rst_c
+   wire                          plol_fedge;
+   wire                          plol_redge;
+   reg                           waita_plol0;
+   reg    [2:0]                  plol0_cnt;
+   wire                          plol0_cnt_tc;
+   reg    [2:0]                  txp_cnt;
+   reg                           txp_rst;
+   wire                          txp_cnt_tc;
+   // ruo_tx_rdy
+   wire                          dual_or_serd_rst;
+   wire                          tx_any_pcs_rst;
+   wire                          tx_any_rst;
+   reg                           txsr_appd /* synthesis syn_keep=1 */;
+   reg                           txdpr_appd;
+   reg    [pnum_channels-1:0]    txpr_appd;
+   reg                           txr_wt_en;
+   reg    [ltxr_wait_width-1:0]  txr_wt_cnt;
+   wire                          txr_wt_tc;
+   reg                           ruo_tx_rdyr;
+
+   // ------------ Rx
+   wire                          comb_rlos;
+   wire                          comb_rlol;
+   //wire                          rlols;
+   wire                          rx_all_well;
+
+   //reg                           rlols_p1;
+   //reg                           rlols_p2;
+   //reg                           rlols_p3;
+
+   reg                           rlol_p1;
+   reg                           rlol_p2;
+   reg                           rlol_p3;
+   reg                           rlos_p1;
+   reg                           rlos_p2;
+   reg                           rlos_p3;
+
+   //reg    [3:0]                  rdb_cnt;
+   //wire                          rdb_cnt_max;
+   //wire                          rdb_cnt_zero;
+   //reg                           rlols_db;
+   //reg                           rlols_db_p1;
+
+   reg    [3:0]                  rlol_db_cnt;
+   wire                          rlol_db_cnt_max;
+   wire                          rlol_db_cnt_zero;
+   reg                           rlol_db;
+   reg                                  rlol_db_p1;
+
+   reg    [3:0]                  rlos_db_cnt;
+   wire                          rlos_db_cnt_max;
+   wire                          rlos_db_cnt_zero;
+   reg                           rlos_db;
+   reg                                  rlos_db_p1;
+
+   // rdo_rx_serdes_rst_c
+   reg    [lrlol_cnt_width-1:0]  rlol1_cnt;
+   wire                          rlol1_cnt_tc;
+   reg    [2:0]                  rxs_cnt;
+   reg                           rxs_rst;
+   wire                          rxs_cnt_tc;
+   reg    [lrrst_wait_width-1:0] rrst_cnt;
+   wire                          rrst_cnt_tc;
+   reg                           rrst_wait;
+   // rdo_rx_pcs_rst_c
+   //wire                          rlols_fedge;
+   //wire                          rlols_redge;
+   wire                          rlol_fedge;
+   wire                          rlol_redge;
+   wire                          rlos_fedge;
+   wire                          rlos_redge;
+
+   reg                           wait_calib;
+   reg                           waita_rlols0;
+   reg    [llols_cnt_width-1:0]  rlols0_cnt;
+   wire                          rlols0_cnt_tc;
+   reg    [2:0]                  rxp_cnt;
+   reg                           rxp_rst;
+   wire                          rxp_cnt_tc;
+
+   wire                          rx_any_serd_rst;
+   reg    [llols_cnt_width-1:0]  rlolsz_cnt;
+   wire                          rlolsz_cnt_tc;
+   reg [2:0]                    rxp_cnt2;
+   reg                           rxp_rst2;
+   wire                          rxp_cnt2_tc;
+   reg [15:0]                    data_loop_b_cnt;
+   reg                           data_loop_b;
+   wire                          data_loop_b_tc;
+
+   // ruo_rx_rdy
+   reg    [pnum_channels-1:0]    rxsr_appd;
+   reg    [pnum_channels-1:0]    rxpr_appd;
+   reg                           rxsdr_appd /* synthesis syn_keep=1 */;
+   reg                           rxdpr_appd;
+   wire                          rxsdr_or_sr_appd;
+   wire                          dual_or_rserd_rst;
+   wire                          rx_any_pcs_rst;
+   wire                          rx_any_rst;
+   reg                           rxr_wt_en;
+   reg    [lrxr_wait_width-1:0]  rxr_wt_cnt;
+   wire                          rxr_wt_tc;
+   reg                           ruo_rx_rdyr;
+
+// ==================================================================
+//                          Start of code
+// ==================================================================
+   assign rsl_enable = ~rui_rsl_disable;
+
+// ------------ rdo_serdes_rst_dual_c
+   assign rdo_serdes_rst_dual_c = (rui_rst&rsl_enable) | rui_serdes_rst_dual_c;
+
+// ------------ rdo_rst_dual_c
+   assign rdo_rst_dual_c = rui_rst_dual_c;
+
+// ------------ Setting counter values for RSL_SIM_MODE
+   `ifdef RSL_SIM_MODE
+      assign wait_b4_trst    = lwait_b4_trst_s;
+      assign wait_b4_rrst    = lwait_b4_rrst_s;
+      assign wait_after_lols = lwait_after_lols_s;
+   `else
+      assign wait_b4_trst    = lwait_b4_trst;
+      assign wait_b4_rrst    = lwait_b4_rrst;
+      assign wait_after_lols = lwait_after_lols;
+   `endif
+
+// ==================================================================
+//                                 Tx
+// ==================================================================
+   generate
+   if((pserdes_mode=="RX AND TX")||(pserdes_mode=="TX ONLY")) begin
+
+// ------------ Synchronizing pll_lol to the tx clock
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) begin
+         pll_lol_p1 <= 1'd0;
+         pll_lol_p2 <= 1'd0;
+         pll_lol_p3 <= 1'd0;
+      end
+      else begin
+         pll_lol_p1 <= rdi_pll_lol;
+         pll_lol_p2 <= pll_lol_p1;
+         pll_lol_p3 <= pll_lol_p2;
+      end
+   end
+
+// ------------ rdo_tx_serdes_rst_c
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         plol_cnt    <= 'd0;
+      else if((pll_lol_p2==0)||(plol_cnt_tc==1)||(rdo_tx_serdes_rst_c==1))
+         plol_cnt    <= 'd0;
+      else
+         plol_cnt    <= plol_cnt+1;
+   end
+   assign plol_cnt_tc = (plol_cnt==wait_b4_trst)?1'b1:1'b0;
+
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) begin
+         txs_cnt  <= 'd0;   // tx serdes reset pulse count
+         txs_rst  <= 1'b0;  // tx serdes reset
+      end
+      else if(plol_cnt_tc==1)
+         txs_rst  <= 1'b1;
+      else if(txs_cnt_tc==1) begin
+         txs_cnt  <= 'd0;
+         txs_rst  <= 1'b0;
+      end
+      else if(txs_rst==1)
+         txs_cnt  <= txs_cnt+1;
+   end
+   assign txs_cnt_tc = (txs_cnt==lreset_pwidth)?1'b1:1'b0;
+
+   assign rdo_tx_serdes_rst_c = (rsl_enable&txs_rst)| rui_tx_serdes_rst_c;
+
+// ------------ rdo_tx_pcs_rst_c
+   assign plol_fedge = ~pll_lol_p2 & pll_lol_p3;
+   assign plol_redge = pll_lol_p2 & ~pll_lol_p3;
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         waita_plol0  <= 1'd0;
+      else if(plol_fedge==1'b1)
+         waita_plol0  <= 1'b1;
+      else if((plol0_cnt_tc==1)||(plol_redge==1))
+         waita_plol0  <= 1'd0;
+   end
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         plol0_cnt    <= 'd0;
+      else if((pll_lol_p2==1)||(plol0_cnt_tc==1))
+         plol0_cnt    <= 'd0;
+      else if(waita_plol0==1'b1)
+         plol0_cnt    <= plol0_cnt+1;
+   end
+   assign plol0_cnt_tc = (plol0_cnt==lwait_after_plol0)?1'b1:1'b0;
+
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) begin
+         txp_cnt  <= 'd0;   // tx serdes reset pulse count
+         txp_rst  <= 1'b0;  // tx serdes reset
+      end
+      else if(plol0_cnt_tc==1)
+         txp_rst  <= 1'b1;
+      else if(txp_cnt_tc==1) begin
+         txp_cnt  <= 'd0;
+         txp_rst  <= 1'b0;
+      end
+      else if(txp_rst==1)
+         txp_cnt  <= txp_cnt+1;
+   end
+   assign txp_cnt_tc = (txp_cnt==lreset_pwidth)?1'b1:1'b0;
+
+   genvar i;
+   for(i=0;i<pnum_channels;i=i+1) begin : ifor
+      assign rdo_tx_pcs_rst_c[i] = (rsl_enable&txp_rst)| rui_tx_pcs_rst_c[i];
+   end
+   if(pnum_channels==1)
+      assign rdo_tx_pcs_rst_c[3:1] = 3'b000;
+   else if(pnum_channels==2)
+      assign rdo_tx_pcs_rst_c[3:2] = 2'b00;
+
+   // ------------ ruo_tx_rdy
+   if(pport_tx_rdy=="ENABLED") begin
+   assign dual_or_serd_rst = rdo_serdes_rst_dual_c|rdo_tx_serdes_rst_c;
+   assign tx_any_pcs_rst = rdo_rst_dual_c|(|rdo_tx_pcs_rst_c[pnum_channels-1:0]);
+   assign tx_any_rst = dual_or_serd_rst | tx_any_pcs_rst;
+
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         txsr_appd <= 1'b1; // tx serdes reset applied
+      else if(dual_or_serd_rst==1)
+         txsr_appd <= 1'b1;
+   end
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         txdpr_appd <= 1'b0; // tx dual (pcs) reset applied
+      else if(pll_lol_p2|rdo_serdes_rst_dual_c|rdo_tx_serdes_rst_c)
+         txdpr_appd <= 1'b0;
+      else if(rdo_rst_dual_c==1)
+         txdpr_appd <= 1'b1;
+   end
+
+   genvar m;
+   for(m=0;m<pnum_channels;m=m+1) begin :mfor
+      always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         txpr_appd[m] <= 1'b0; // tx pcs reset applied
+      else if(pll_lol_p2|rdo_serdes_rst_dual_c|rdo_tx_serdes_rst_c)
+         txpr_appd[m] <= 1'b0;
+      else if(txsr_appd&(rdo_tx_pcs_rst_c[m]|txdpr_appd))
+         txpr_appd[m] <= 1'b1;
+      end
+   end
+
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         txr_wt_en  <= 0;  // tx ready wait counter enable
+      else if((txr_wt_tc==1)||(dual_or_serd_rst==1))
+         txr_wt_en  <= 0;
+      else if((~ruo_tx_rdyr)&(~pll_lol_p2)&(&txpr_appd))
+         txr_wt_en  <= 1;
+   end
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         txr_wt_cnt  <= 'd0;  // tx ready wait count
+      else if((txr_wt_tc==1)||(tx_any_rst==1))
+         txr_wt_cnt  <= 'd0;
+      else if(txr_wt_en==1)
+         txr_wt_cnt  <= txr_wt_cnt+1;
+   end
+   assign txr_wt_tc = (txr_wt_cnt==pwait_tx_rdy)?1'b1:1'b0;
+
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         ruo_tx_rdyr <= 1'b0; // tx serdes reset applied
+      else if((tx_any_rst==1)||(pll_lol_p2==1))
+         ruo_tx_rdyr <= 1'b0;
+      else if(txr_wt_tc==1)
+         ruo_tx_rdyr <= 1'b1;
+   end
+   assign ruo_tx_rdy = ruo_tx_rdyr;
+   end         // if pport_tx_rdy
+   else
+      assign ruo_tx_rdy = 1'b0;
+   end         // generate if(Rx and Tx) or (Tx only)
+   else begin  // generate else (Rx only)
+      assign rdo_tx_serdes_rst_c = 1'b0;
+      assign rdo_tx_pcs_rst_c = 4'd0;
+      assign ruo_tx_rdy = 1'b0;
+   end
+   endgenerate
+
+// ==================================================================
+//                                 Rx
+// ==================================================================
+   generate
+   if((pserdes_mode=="RX AND TX")||(pserdes_mode=="RX ONLY")) begin
+   assign comb_rlos = |rdi_rx_los_low_s[pnum_channels-1:0];
+   assign comb_rlol = |rdi_rx_cdr_lol_s[pnum_channels-1:0];
+   //assign rlols     = comb_rlos|comb_rlol;
+
+   // ------------ Synchronizing rlols to the rx ref clock
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) begin
+        //rlols_p1    <= 1'd0;
+        //rlols_p2    <= 1'd0;
+        //rlols_p3    <= 1'd0;
+        //rlols_db_p1 <= 1'd1;
+
+        rlol_p1     <= 1'd0;
+        rlol_p2     <= 1'd0;
+        rlol_p3     <= 1'd0;
+        rlol_db_p1  <= 1'd1;
+
+        rlos_p1    <= 1'd0;
+        rlos_p2    <= 1'd0;
+        rlos_p3    <= 1'd0;
+        rlos_db_p1 <= 1'd1;
+      end
+      else begin
+        //rlols_p1    <= rlols;
+        //rlols_p2    <= rlols_p1;
+        //rlols_p3    <= rlols_p2;
+        //rlols_db_p1 <= rlols_db;
+
+        rlol_p1     <= comb_rlol;
+        rlol_p2     <= rlol_p1;
+        rlol_p3     <= rlol_p2;
+       rlol_db_p1  <= rlol_db;
+
+        rlos_p1    <= comb_rlos;
+        rlos_p2    <= rlos_p1;
+        rlos_p3    <= rlos_p2;
+        rlos_db_p1 <= rlos_db;
+      end
+   end
+   assign rx_all_well = ~rlol_db && ~rlos_db;
+
+//******************************************************************************
+// [ES:05.03.17] Unused registers for clean-up
+//------------------------------------------------------------------------------
+// ------------ Debouncing rlols
+//   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+//      if(rui_rst==1'b1) rdb_cnt  <= lrdb_max;
+//      else if(rlols_p2==1) begin
+//         if(!rdb_cnt_max) rdb_cnt <= rdb_cnt+1;
+//      end
+//      else if(!rdb_cnt_zero) rdb_cnt <= rdb_cnt-1;
+//   end
+//   assign rdb_cnt_max  = (rdb_cnt==lrdb_max);
+//   assign rdb_cnt_zero = (rdb_cnt==0);
+//   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+//      if(rui_rst==1'b1) rlols_db <= 1;
+//      else if(rdb_cnt_max)  rlols_db <= 1;
+//      else if(rdb_cnt_zero) rlols_db <= 0;
+//   end
+//******************************************************************************
+
+// ------------ Debouncing rlol
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) rlol_db_cnt  <= lrdb_max;
+      else if(rlol_p2==1) begin
+         if(!rlol_db_cnt_max) rlol_db_cnt <= rlol_db_cnt+1;
+      end
+      else if(!rlol_db_cnt_zero) rlol_db_cnt <= rlol_db_cnt-1;
+   end
+   assign rlol_db_cnt_max  = (rlol_db_cnt==lrdb_max);
+   assign rlol_db_cnt_zero = (rlol_db_cnt==0);
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) rlol_db <= 1;
+      else if(rlol_db_cnt_max)  rlol_db <= 1;
+      else if(rlol_db_cnt_zero) rlol_db <= 0;
+   end
+
+// ------------ Debouncing rlos
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) rlos_db_cnt  <= lrdb_max;
+      else if(rlos_p2==1) begin
+         if(!rlos_db_cnt_max) rlos_db_cnt <= rlos_db_cnt+1;
+      end
+      else if(!rlos_db_cnt_zero) rlos_db_cnt <= rlos_db_cnt-1;
+   end
+   assign rlos_db_cnt_max  = (rlos_db_cnt==lrdb_max);
+   assign rlos_db_cnt_zero = (rlos_db_cnt==0);
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) rlos_db <= 1;
+      else if(rlos_db_cnt_max)  rlos_db <= 1;
+      else if(rlos_db_cnt_zero) rlos_db <= 0;
+   end
+
+// ------------ Calib time trigger
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+     if (rui_rst==1'b1) begin
+       wait_calib <= 1'd1;
+     end
+     else begin
+       if (rlol1_cnt_tc) begin
+         if (rlol_db)
+           wait_calib <= 1'd1;
+         else
+           wait_calib <= 1'd0;
+       end
+       else if (rlos_redge)
+         wait_calib <= 1'd0;
+       else if (rlos_fedge) begin
+         wait_calib <= 1'd1;
+       end
+     end
+   end
+
+   //***************************************************************************
+   // Total calibration time counter
+   // - this covers the band calibration time (256 cycles * 64) and
+   //   DAC calibration time (16384 cycles * 10 bits)
+   //---------------------------------------------------------------------------
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+     if (rui_rst==1'b1) begin
+       rlol1_cnt  <= 'd0;  // Counting when Rx LOL is 1 and Rx LOS is 0
+     end
+     else begin
+       if(rxs_rst || rlol1_cnt_tc || rlos_redge)
+         rlol1_cnt  <= 'd0;
+       else if (wait_calib)
+         rlol1_cnt <= rlol1_cnt+1;
+     end
+   end
+   assign rlol1_cnt_tc = (rlol1_cnt==wait_b4_rrst);
+
+// ------------ rdo_rx_serdes_rst_c
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+     if (rui_rst==1'b1) begin
+       rxs_cnt  <= 'd0;   // rx serdes reset pulse count
+       rxs_rst  <= 1'b0;  // rx serdes reset
+     end
+     else begin
+       if (rlos_db)
+         rxs_rst <= 1'b0;
+       else if (rlol1_cnt_tc && rlol_db)
+         rxs_rst <= 1'b1;
+       else if (rxs_cnt_tc==1) begin
+         rxs_rst  <= 1'b0;
+       end
+
+       if (rxs_cnt_tc)
+         rxs_cnt <= 'd0;
+       else
+         if (rxs_rst==1)
+           rxs_cnt <= rxs_cnt+1;
+     end
+   end
+   assign rxs_cnt_tc  = (rxs_cnt==lreset_pwidth)?1'b1:1'b0;
+
+   //***************************************************************************
+   // [ES:05.03.17] Unused logic from CPRI rrst_wait
+   //---------------------------------------------------------------------------
+   // always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+   //    if(rui_rst==1'b1)
+   //       rrst_cnt    <= 'd0;
+   //    else if(rlol1_cnt_tc)
+   //       rrst_cnt    <= 'd0;
+   //    else if(rrst_wait)
+   //       rrst_cnt    <= rrst_cnt+1;
+   // end
+   // assign rrst_cnt_tc = (rrst_cnt==lwait_after_rrst) ? 1'b1 : 1'b0;
+   // always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+   //    if(rui_rst==1'b1)
+   //       rrst_wait    <= 0;
+   //    else if(pprotocol != "CPRI")
+   //       rrst_wait    <= 0;
+   //    else if(rlol1_cnt_tc)
+   //       rrst_wait    <= 1;
+   //    else if(rrst_cnt_tc==1)
+   //       rrst_wait    <= 0;
+   // end
+   //***************************************************************************
+
+   genvar j;
+   for(j=0;j<pnum_channels;j=j+1) begin :jfor
+      assign rdo_rx_serdes_rst_c[j] = (rsl_enable&rxs_rst)| rui_rx_serdes_rst_c[j];
+   end
+   if(pnum_channels==1)
+      assign rdo_rx_serdes_rst_c[3:1] = 3'b000;
+   else if(pnum_channels==2)
+      assign rdo_rx_serdes_rst_c[3:2] = 2'b00;
+
+// ------------ rdo_rx_pcs_rst_c
+   //assign rlols_fedge = ~rlols_db & rlols_db_p1;
+   //assign rlols_redge = rlols_db & ~rlols_db_p1;
+
+   assign rlol_fedge  = ~rlol_db & rlol_db_p1;
+   assign rlol_redge  = rlol_db & ~rlol_db_p1;
+   assign rlos_fedge  = ~rlos_db & rlos_db_p1;
+   assign rlos_redge  = rlos_db & ~rlos_db_p1;
+
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if (rui_rst==1'b1) begin
+        waita_rlols0 <= 1'd0;
+      end
+      else begin
+        if ((rlos_fedge && ~rlol_db) || (rlol_fedge && ~rlos_db))
+          waita_rlols0 <= 1'b1;
+        else if (rlos_redge || rlol_redge)
+          waita_rlols0 <= 1'd0;
+        else if (rlols0_cnt_tc==1)
+          waita_rlols0 <= 1'd0;
+      end
+   end
+
+   //***************************************************************************
+   // Post RLOL check before pcs_rst deassertion
+   // - allowance of 2-4 DAC calibration cycles + 1024 cycles for WA module
+   //   (word alignment).
+   //---------------------------------------------------------------------------
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+     if (rui_rst==1'b1) begin
+       rlols0_cnt <= 'd0;
+     end
+     else begin
+       if (rlol_redge || rlos_redge || rlols0_cnt_tc)
+         rlols0_cnt <= 'd0;
+       else if (waita_rlols0==1)
+         rlols0_cnt <= rlols0_cnt+1;
+     end
+   end
+   assign rlols0_cnt_tc   = (rlols0_cnt == wait_after_lols);
+   assign rx_any_serd_rst = rdo_serdes_rst_dual_c|(|rdo_rx_serdes_rst_c);
+
+   //***************************************************************************
+   // [ES:05.03.17] Unused registers for clean-up
+   //---------------------------------------------------------------------------
+   // always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+   //    if(rui_rst==1'b1)
+   //       rlolsz_cnt  <= 'd0;  // Counting when both Rx LOL is 0 and Rx LOS is 0
+   //    else if((rlol_db|rx_any_serd_rst)||(rlolsz_cnt_tc==1))
+   //       rlolsz_cnt  <= 'd0;
+   //    else if((rlolsz_cnt_tc==0)&&(rlol_db==0))
+   //       rlolsz_cnt  <= rlolsz_cnt+1;
+   // end
+   // assign rlolsz_cnt_tc = (rlolsz_cnt==wait_after_lols);
+   //***************************************************************************
+
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+     if (rui_rst==1'b1) begin
+       rxp_cnt2  <= 'd0;   // pcs serdes reset pulse count
+       rxp_rst2  <= 1'b1;  // rx pcs reset
+     end
+     else begin
+       if (rx_any_serd_rst || rlos_redge) begin
+         rxp_rst2 <= 1'b1;
+       end
+       else if (rlols0_cnt_tc) begin
+         rxp_rst2 <= 1'b0;
+       end
+       //***********************************************************************
+       // [ES:05.03.17] No need for pulse width
+       //-----------------------------------------------------------------------
+       // else if(rxp_cnt2_tc==1) begin
+       //   rxp_cnt2  <= 'd0;
+       //   rxp_rst2  <= 1'b0;
+       // end
+       //***********************************************************************
+       // [ES:05.03.17] No need for pulse width
+       //-----------------------------------------------------------------------
+       // else if (rxp_rst2==1)
+       //   rxp_cnt2 <= rxp_cnt2+1;
+       //***********************************************************************
+     end // else: !if(rui_rst==1'b1)
+   end // always @ (posedge rui_rx_ref_clk or posedge rui_rst)
+   //assign rxp_cnt2_tc = (rxp_cnt2==lreset_pwidth)?1'b1:1'b0;
+
+   //***************************************************************************
+   // [ES:05.03.17] No need for pulse width
+   //---------------------------------------------------------------------------
+   //else begin
+   //   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+   //      if(rui_rst==1'b1)
+   //         rxp_rst2  <= 1'b1;  // rx pcs reset
+   //      else if(rx_any_serd_rst)
+   //         rxp_rst2  <= 1'b1;
+   //      else if(rlolsz_cnt_tc==1)
+   //         rxp_rst2  <= 1'b0;
+   //   end
+   //end
+   //***************************************************************************
+
+   genvar k;
+   for(k=0;k<pnum_channels;k=k+1) begin: kfor
+      assign rdo_rx_pcs_rst_c[k] = (rsl_enable&rxp_rst2)| rui_rx_pcs_rst_c[k];
+   end
+   if(pnum_channels==1)
+      assign rdo_rx_pcs_rst_c[3:1] = 3'b000;
+   else if(pnum_channels==2)
+      assign rdo_rx_pcs_rst_c[3:2] = 2'b00;
+
+// ------------ ruo_rx_rdy
+   if(pport_rx_rdy=="ENABLED") begin
+   assign dual_or_rserd_rst = rdo_serdes_rst_dual_c|(|rdo_rx_serdes_rst_c[pnum_channels-1:0]);
+   assign rx_any_pcs_rst = rdo_rst_dual_c|(|rdo_rx_pcs_rst_c[pnum_channels-1:0]);
+   assign rx_any_rst = dual_or_rserd_rst | rx_any_pcs_rst;
+
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         rxsdr_appd <= 1'b1;  // Serdes dual reset (macro reset) applied
+      else if(rdo_serdes_rst_dual_c==1)
+         rxsdr_appd <= 1'b1;
+   end
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         rxdpr_appd <= 1'b0;  // Rx dual PCS reset (dual reset) applied
+      else if(~rx_all_well|dual_or_rserd_rst)
+         rxdpr_appd <= 1'b0;
+      else if(rdo_rst_dual_c==1)
+         rxdpr_appd <= 1'b1;
+   end
+
+   genvar l;
+   for(l=0;l<pnum_channels;l=l+1) begin : lfor
+      always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+         if(rui_rst==1'b1)
+            rxsr_appd[l] <= 1'b0; // rx serdes reset applied
+         else if(rdo_rx_serdes_rst_c[l]==1)
+            rxsr_appd[l] <= 1'b1;
+      end
+      always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         rxpr_appd[l] <= 1'b0; // rx pcs reset applied
+      else if(rdi_rx_los_low_s[l]|rdi_rx_cdr_lol_s[l]|rdo_serdes_rst_dual_c|rdo_rx_serdes_rst_c[l])
+         rxpr_appd[l] <= 1'b0;
+      else if(rxsdr_or_sr_appd&(~rx_all_well)&rdo_rx_pcs_rst_c[l])
+         rxpr_appd[l] <= 1'b1;
+      end
+   end
+
+   assign rxsdr_or_sr_appd = rxsdr_appd|(&rxsr_appd);
+
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         rxr_wt_en  <= 0;  // rx ready wait counter enable
+      //else if((rxr_wt_tc==1)||(dual_or_rserd_rst==1))
+      else if((rxr_wt_tc==1)||(dual_or_rserd_rst==1)||(rx_all_well==0)) // BM, 2/4/16
+         rxr_wt_en  <= 0;
+      else if(~ruo_rx_rdyr&rx_all_well&((&rxpr_appd)|rxdpr_appd))
+         rxr_wt_en  <= 1;
+   end
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         rxr_wt_cnt  <= 'd0;  // rx ready wait count
+      //else if((rxr_wt_tc==1)||(rx_any_rst==1))
+      else if((rxr_wt_tc==1)||(rx_any_rst==1)||(rx_all_well==0)) // BM, 2/4/16
+         rxr_wt_cnt  <= 'd0;
+      else if(rxr_wt_en==1)
+         rxr_wt_cnt  <= rxr_wt_cnt+1;
+   end
+   assign rxr_wt_tc = (rxr_wt_cnt==pwait_rx_rdy)?1'b1:1'b0;
+
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         ruo_rx_rdyr <= 1'b0; // rx serdes reset applied
+      else if((rx_any_rst==1)||(rx_all_well==0))
+         ruo_rx_rdyr <= 1'b0;
+      else if(rxr_wt_tc==1)
+         ruo_rx_rdyr <= 1'b1;
+   end
+   assign ruo_rx_rdy = ruo_rx_rdyr;
+   end         // if pport_rx_rdy
+   else
+      assign ruo_rx_rdy = 1'b0;
+   end // if ((pserdes_mode=="RX AND TX")||(pserdes_mode=="RX ONLY"))
+
+   else begin  // generate else (Tx only)
+      assign rdo_rx_serdes_rst_c = 4'd0;
+      assign rdo_rx_pcs_rst_c = 4'd0;
+      assign ruo_rx_rdy = 1'b0;
+   end // else: !if((pserdes_mode=="RX AND TX")||(pserdes_mode=="RX ONLY"))
+
+   endgenerate
+
+endmodule
+
+
+//   ===========================================================================
+//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
+//   ---------------------------------------------------------------------------
+//   Copyright (c) 2015 by Lattice Semiconductor Corporation
+//   ALL RIGHTS RESERVED 
+//   ------------------------------------------------------------------
+//
+//   Permission:
+//
+//      Lattice SG Pte. Ltd. grants permission to use this code
+//      pursuant to the terms of the Lattice Reference Design License Agreement. 
+//
+//
+//   Disclaimer:
+//
+//      This VHDL or Verilog source code is intended as a design reference
+//      which illustrates how these types of functions can be implemented.
+//      It is the user's responsibility to verify their design for
+//      consistency and functionality through the use of formal
+//      verification methods.  Lattice provides no warranty
+//      regarding the use or functionality of this code.
+//
+//   ---------------------------------------------------------------------------
+//
+//                  Lattice SG Pte. Ltd.
+//                  101 Thomson Road, United Square #07-02 
+//                  Singapore 307591
+//
+//
+//                  TEL: 1-800-Lattice (USA and Canada)
+//                       +65-6631-2000 (Singapore)
+//                       +1-503-268-8001 (other locations)
+//
+//                  web: http://www.latticesemi.com/
+//                  email: techsupport@latticesemi.com
+//
+//   ---------------------------------------------------------------------------
+//
+// =============================================================================
+//                         FILE DETAILS         
+// Project               : SLL - Soft Loss Of Lock(LOL) Logic
+// File                  : sll_core.v
+// Title                 : Top-level file for SLL 
+// Dependencies          : 1.
+//                       : 2.
+// Description           : 
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.0
+// Author(s)             : AV
+// Mod. Date             : March 2, 2015
+// Changes Made          : Initial Creation
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.1
+// Author(s)             : AV
+// Mod. Date             : June 8, 2015
+// Changes Made          : Following updates were made 
+//                       : 1. Changed all the PLOL status logic and FSM to run
+//                       :    on sli_refclk. 
+//                       : 2. Added the HB logic for presence of tx_pclk 
+//                       : 3. Changed the lparam assignment scheme for 
+//                       :    simulation purposes. 
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.2
+// Author(s)             : AV
+// Mod. Date             : June 24, 2015
+// Changes Made          : Updated the gearing logic for SDI dynamic rate change
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.3
+// Author(s)             : AV
+// Mod. Date             : July 14, 2015
+// Changes Made          : Added the logic for dynamic rate change in CPRI
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.4
+// Author(s)             : AV
+// Mod. Date             : August 21, 2015
+// Changes Made          : Added the logic for dynamic rate change of 5G CPRI & 
+//                         PCIe.
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.5
+// Author(s)             : ES/EB
+// Mod. Date             : March 21, 2017
+// Changes Made          : 1. Added pdiff_sync signal to syncrhonize pcount_diff 
+//                       :    to sli_refclk.
+//                       : 2. Updated terminal count logic for PCIe 5G
+//                       : 3. Modified checking of pcount_diff in SLL state
+//                       :    machine to cover actual count
+//                       :    (from 16-bits to 22-bits)
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.6
+// Author(s)             : ES
+// Mod. Date             : April 19, 2017
+// Changes Made          : 1. Added registered lock and unlock signal from
+//                            pdiff_sync to totally decouple pcount_diff from
+//                            SLL state machine.
+//                       : 2. Modified LPCLK_TC_4 to 1:1 clock ratio when CPRI
+//                            is operating @ 4.9125Gbps data rate.
+// =============================================================================
+`timescale 1ns/10ps
+
+module sgmii_ecp5sll_core ( 
+  //Reset and Clock inputs
+  sli_rst,         //Active high asynchronous reset input
+  sli_refclk,      //Refclk input to the Tx PLL
+  sli_pclk,        //Tx pclk output from the PCS
+  
+  //Control inputs
+  sli_div2_rate,   //Divide by 2 control; 0 - Full rate; 1 - Half rate
+  sli_div11_rate,  //Divide by 11 control; 0 - Full rate; 1 - Div by 11
+  sli_gear_mode,   //Gear mode control for PCS; 0 - 8/10; 1- 16/20
+  sli_cpri_mode,   //Mode of operation specific to CPRI protocol
+  sli_pcie_mode,   //Mode of operation specific to PCIe mode (2.5G or 5G)
+  
+  //LOL Output
+  slo_plol         //Tx PLL Loss of Lock output to the user logic
+  );
+  
+// Inputs
+input       sli_rst;
+input       sli_refclk;
+input       sli_pclk;
+input       sli_div2_rate;
+input       sli_div11_rate;
+input       sli_gear_mode;
+input [2:0] sli_cpri_mode;
+input       sli_pcie_mode;
+
+// Outputs
+output      slo_plol;
+
+
+// Parameters
+parameter PPROTOCOL              = "PCIE";     //Protocol selected by the User
+parameter PLOL_SETTING           = 0;          //PLL LOL setting. Possible values are 0,1,2,3
+parameter PDYN_RATE_CTRL         = "DISABLED"; //PCS Dynamic Rate control
+parameter PPCIE_MAX_RATE         = "2.5";      //PCIe max data rate
+parameter PDIFF_VAL_LOCK         = 20;         //Differential count value for Lock
+parameter PDIFF_VAL_UNLOCK       = 39;         //Differential count value for Unlock
+parameter PPCLK_TC               = 65535;      //Terminal count value for counter running on sli_pclk
+parameter PDIFF_DIV11_VAL_LOCK   = 3;          //Differential count value for Lock for SDI Div11
+parameter PDIFF_DIV11_VAL_UNLOCK = 3;          //Differential count value for Unlock for SDI Div11
+parameter PPCLK_DIV11_TC         = 2383;       //Terminal count value (SDI Div11) for counter running on sli_pclk
+
+
+// Local Parameters
+localparam [1:0]  LPLL_LOSS_ST         = 2'b00;       //PLL Loss state
+localparam [1:0]  LPLL_PRELOSS_ST      = 2'b01;       //PLL Pre-Loss state
+localparam [1:0]  LPLL_PRELOCK_ST      = 2'b10;       //PLL Pre-Lock state
+localparam [1:0]  LPLL_LOCK_ST         = 2'b11;       //PLL Lock state
+`ifdef RSL_SIM_MODE
+localparam [15:0] LRCLK_TC             = 16'd63;   //Terminal count value for counter running on sli_refclk
+`else
+localparam [15:0] LRCLK_TC             = 16'd65535;   //Terminal count value for counter running on sli_refclk
+`endif
+localparam [15:0] LRCLK_TC_PUL_WIDTH   = 16'd50;      //Pulse width for the Refclk terminal count pulse
+localparam [7:0]  LHB_WAIT_CNT         = 8'd255;      //Wait count for the Heartbeat signal
+
+// Local Parameters related to the CPRI dynamic modes
+// Terminal count values for the four CPRI modes
+localparam LPCLK_TC_0 = 32768;
+localparam LPCLK_TC_1 = 65536;
+localparam LPCLK_TC_2 = 131072;
+localparam LPCLK_TC_3 = 163840;
+localparam LPCLK_TC_4 = 65536;
+
+// Lock values count values for the four CPRI modes and four PLOL settings (4x5)
+// CPRI rate mode 0                CPRI rate mode 1                   CPRI rate mode 2                    CPRI rate mode 3                     CPRI rate mode 4
+localparam LPDIFF_LOCK_00 = 9;     localparam LPDIFF_LOCK_10 = 19;    localparam LPDIFF_LOCK_20 = 39;     localparam LPDIFF_LOCK_30 = 49;      localparam LPDIFF_LOCK_40 = 19;
+localparam LPDIFF_LOCK_01 = 9;     localparam LPDIFF_LOCK_11 = 19;    localparam LPDIFF_LOCK_21 = 39;     localparam LPDIFF_LOCK_31 = 49;      localparam LPDIFF_LOCK_41 = 19;
+localparam LPDIFF_LOCK_02 = 49;    localparam LPDIFF_LOCK_12 = 98;    localparam LPDIFF_LOCK_22 = 196;    localparam LPDIFF_LOCK_32 = 245;     localparam LPDIFF_LOCK_42 = 98;
+localparam LPDIFF_LOCK_03 = 131;   localparam LPDIFF_LOCK_13 = 262;   localparam LPDIFF_LOCK_23 = 524;    localparam LPDIFF_LOCK_33 = 655;     localparam LPDIFF_LOCK_43 = 262;
+
+// Unlock values count values for the four CPRI modes and four PLOL settings (4x5)
+// CPRI rate mode 0                  CPRI rate mode 1                      CPRI rate mode 2                       CPRI rate mode 3                         CPRI rate mode 4
+localparam LPDIFF_UNLOCK_00 = 19;    localparam LPDIFF_UNLOCK_10 = 39;     localparam LPDIFF_UNLOCK_20 = 78;      localparam LPDIFF_UNLOCK_30 = 98;        localparam LPDIFF_UNLOCK_40 = 39;
+localparam LPDIFF_UNLOCK_01 = 65;    localparam LPDIFF_UNLOCK_11 = 131;    localparam LPDIFF_UNLOCK_21 = 262;     localparam LPDIFF_UNLOCK_31 = 327;       localparam LPDIFF_UNLOCK_41 = 131;
+localparam LPDIFF_UNLOCK_02 = 72;    localparam LPDIFF_UNLOCK_12 = 144;    localparam LPDIFF_UNLOCK_22 = 288;     localparam LPDIFF_UNLOCK_32 = 360;       localparam LPDIFF_UNLOCK_42 = 144;
+localparam LPDIFF_UNLOCK_03 = 196;   localparam LPDIFF_UNLOCK_13 = 393;    localparam LPDIFF_UNLOCK_23 = 786;     localparam LPDIFF_UNLOCK_33 = 983;       localparam LPDIFF_UNLOCK_43 = 393;
+
+// Input and Output reg and wire declarations
+wire       sli_rst;
+wire       sli_refclk;
+wire       sli_pclk;
+wire       sli_div2_rate;
+wire       sli_div11_rate;
+wire       sli_gear_mode;
+wire [2:0] sli_cpri_mode;
+wire       sli_pcie_mode;
+wire       slo_plol;
+
+//-------------- Internal signals reg and wire declarations --------------------
+
+//Signals running on sli_refclk
+reg  [15:0] rcount;           //16-bit Counter
+reg         rtc_pul;          //Terminal count pulse
+reg         rtc_pul_p1;       //Terminal count pulse pipeline
+reg         rtc_ctrl;         //Terminal count pulse control
+
+reg  [7:0]  rhb_wait_cnt;     //Heartbeat wait counter
+
+//Heatbeat synchronization and pipeline registers
+wire        rhb_sync;
+reg         rhb_sync_p2;
+reg         rhb_sync_p1;
+
+//Pipeling registers for dynamic control mode
+wire        rgear;
+wire        rdiv2;
+wire        rdiv11;
+reg         rgear_p1;
+reg         rdiv2_p1;
+reg         rdiv11_p1;
+
+reg         rstat_pclk;        //Pclk presence/absence status
+
+reg  [21:0] rcount_tc;         //Tx_pclk terminal count register
+reg  [15:0] rdiff_comp_lock;   //Differential comparison value for Lock
+reg  [15:0] rdiff_comp_unlock; //Differential compariosn value for Unlock
+
+wire        rpcie_mode;        //PCIe mode signal synchronized to refclk
+reg         rpcie_mode_p1;     //PCIe mode pipeline register
+
+wire        rcpri_mod_ch_sync; //CPRI mode change synchronized to refclk
+reg         rcpri_mod_ch_p1;   //CPRI mode change pipeline register
+reg         rcpri_mod_ch_p2;   //CPRI mode change pipeline register
+reg         rcpri_mod_ch_st;   //CPRI mode change status
+
+reg  [1:0]  sll_state;         //Current-state register for LOL FSM
+
+reg         pll_lock;          //PLL Lock signal
+
+//Signals running on sli_pclk
+//Synchronization and pipeline registers
+wire        ppul_sync;
+reg         ppul_sync_p1;
+reg         ppul_sync_p2;
+reg         ppul_sync_p3;
+
+wire        pdiff_sync;
+reg         pdiff_sync_p1;
+   
+reg  [21:0] pcount;            //22-bit counter
+reg  [21:0] pcount_diff;       //Differential value between Tx_pclk counter and theoritical value
+
+//Heartbeat counter and heartbeat signal running on pclk
+reg  [2:0]  phb_cnt;
+reg         phb;
+
+//CPRI dynamic mode releated signals
+reg  [2:0]  pcpri_mode;
+reg         pcpri_mod_ch;
+
+//Assignment scheme changed mainly for simulation purpose
+wire [15:0] LRCLK_TC_w;
+assign LRCLK_TC_w = LRCLK_TC;
+
+reg         unlock;
+reg         lock;
+
+//Heartbeat synchronization
+sync # (.PDATA_RST_VAL(0)) phb_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (phb),
+  .data_out(rhb_sync)
+  );
+  
+  
+//Terminal count pulse synchronization
+sync # (.PDATA_RST_VAL(0)) rtc_sync_inst ( 
+  .clk     (sli_pclk),
+  .rst     (sli_rst),
+  .data_in (rtc_pul),
+  .data_out(ppul_sync)
+  );
+
+//Differential value logic update synchronization
+sync # (.PDATA_RST_VAL(0)) pdiff_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (ppul_sync),
+  .data_out(pdiff_sync)
+  );
+
+//Gear mode synchronization
+sync # (.PDATA_RST_VAL(0)) gear_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (sli_gear_mode),
+  .data_out(rgear)
+  );
+  
+//Div2 synchronization
+sync # (.PDATA_RST_VAL(0)) div2_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (sli_div2_rate),
+  .data_out(rdiv2)
+  );
+  
+//Div11 synchronization
+sync # (.PDATA_RST_VAL(0)) div11_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (sli_div11_rate),
+  .data_out(rdiv11)
+  );
+  
+//CPRI mode change synchronization
+sync # (.PDATA_RST_VAL(0)) cpri_mod_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (pcpri_mod_ch),
+  .data_out(rcpri_mod_ch_sync)
+  );
+  
+//PCIe mode change synchronization
+sync # (.PDATA_RST_VAL(0)) pcie_mod_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (sli_pcie_mode),
+  .data_out(rpcie_mode)
+  );  
+
+// =============================================================================
+// Synchronized Lock/Unlock signals
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    unlock        <= 1'b0;
+    lock          <= 1'b0;
+    pdiff_sync_p1 <= 1'b0;
+  end
+  else begin
+    pdiff_sync_p1 <= pdiff_sync;
+    if (unlock) begin
+      unlock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : unlock;
+    end
+    else begin
+      unlock <= pdiff_sync ? (pcount_diff[21:0] > {6'd0, rdiff_comp_unlock}) : 1'b0;
+    end
+    if (lock) begin
+      lock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : lock;
+    end
+    else begin
+      lock <= pdiff_sync ? (pcount_diff[21:0] <= {6'd0, rdiff_comp_lock}) : 1'b0;
+    end
+  end
+end
+
+// =============================================================================
+// Refclk Counter, pulse generation logic and Heartbeat monitor logic
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rcount     <= 16'd0;
+    rtc_pul    <= 1'b0;
+    rtc_ctrl   <= 1'b0;
+    rtc_pul_p1 <= 1'b0;
+  end
+  else begin
+    //Counter logic
+    if ((rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin
+      if (rtc_ctrl == 1'b1) begin
+        rcount <= LRCLK_TC_PUL_WIDTH;
+      end  
+    end
+    else begin
+      if (rcount != LRCLK_TC_w) begin
+        rcount <= rcount + 1;
+      end
+      else begin
+        rcount <= 16'd0;   
+      end
+    end
+    
+    //Pulse control logic
+    if (rcount == LRCLK_TC_w - 1) begin
+      rtc_ctrl <= 1'b1;
+    end
+    
+    //Pulse Generation logic
+    if (rtc_ctrl == 1'b1) begin
+      if ((rcount == LRCLK_TC_w) || (rcount < LRCLK_TC_PUL_WIDTH)) begin
+        rtc_pul <= 1'b1;
+    end  
+      else begin
+        rtc_pul <= 1'b0;  
+      end
+    end
+    
+    rtc_pul_p1 <= rtc_pul;  
+  end  
+end
+
+
+// =============================================================================
+// Heartbeat synchronization & monitor logic and Dynamic mode pipeline logic 
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rhb_sync_p1     <= 1'b0;
+    rhb_sync_p2     <= 1'b0;
+    rhb_wait_cnt    <= 8'd0;
+    rstat_pclk      <= 1'b0;
+    rgear_p1        <= 1'b0;
+    rdiv2_p1        <= 1'b0;
+    rdiv11_p1       <= 1'b0;
+    rcpri_mod_ch_p1 <= 1'b0;
+    rcpri_mod_ch_p2 <= 1'b0;
+    rcpri_mod_ch_st <= 1'b0;
+    rpcie_mode_p1   <= 1'b0;
+    
+  end
+  else begin
+    //Pipeline stages for the Heartbeat
+    rhb_sync_p1 <= rhb_sync;
+    rhb_sync_p2 <= rhb_sync_p1;
+    
+    //Pipeline stages of the Dynamic rate control signals
+    rgear_p1  <= rgear;
+    rdiv2_p1  <= rdiv2;
+    rdiv11_p1 <= rdiv11;
+    
+    //Pipeline stage for PCIe mode
+    rpcie_mode_p1 <= rpcie_mode;
+    
+    //Pipeline stage for CPRI mode change
+    rcpri_mod_ch_p1 <= rcpri_mod_ch_sync;
+    rcpri_mod_ch_p2 <= rcpri_mod_ch_p1;
+    
+    //CPRI mode change status logic
+    if (rcpri_mod_ch_p1^rcpri_mod_ch_sync == 1'b1) begin
+      rcpri_mod_ch_st <= 1'b1;
+    end 
+    
+    //Heartbeat wait counter and monitor logic
+    if (rtc_ctrl == 1'b1) begin
+      if (rhb_sync_p1 == 1'b1 && rhb_sync_p2 == 1'b0) begin
+        rhb_wait_cnt <= 8'd0;
+        rstat_pclk   <= 1'b1;
+      end
+      else if (rhb_wait_cnt == LHB_WAIT_CNT) begin
+        rhb_wait_cnt <= 8'd0;
+        rstat_pclk   <= 1'b0;
+      end
+      else begin
+        rhb_wait_cnt <= rhb_wait_cnt + 1;
+      end
+    end
+  end  
+end
+
+
+// =============================================================================
+// Pipleline registers for the TC pulse and CPRI mode change logic
+// =============================================================================
+always @(posedge sli_pclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    ppul_sync_p1 <= 1'b0;
+    ppul_sync_p2 <= 1'b0;
+    ppul_sync_p3 <= 1'b0;
+    pcpri_mode   <= 3'b0;
+    pcpri_mod_ch <= 1'b0;
+  end
+  else begin
+    ppul_sync_p1 <= ppul_sync;
+    ppul_sync_p2 <= ppul_sync_p1;
+    ppul_sync_p3 <= ppul_sync_p2;
+    
+    //CPRI mode change logic
+    pcpri_mode <= sli_cpri_mode;
+    
+    if (pcpri_mode != sli_cpri_mode) begin
+      pcpri_mod_ch <= ~pcpri_mod_ch;
+    end 
+  end  
+end
+   
+
+// =============================================================================
+// Terminal count logic
+// =============================================================================
+
+//For SDI protocol with Dynamic rate control enabled
+generate
+if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "SDI")) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rcount_tc         <= 22'd0;
+    rdiff_comp_lock   <= 16'd0;
+    rdiff_comp_unlock <= 16'd0;
+  end
+  else begin
+    //Terminal count logic
+    //Div by 11 is enabled
+    if (rdiv11 == 1'b1) begin
+      //Gear mode is 16/20
+      if (rgear == 1'b1) begin
+        rcount_tc         <= PPCLK_DIV11_TC;
+        rdiff_comp_lock   <= PDIFF_DIV11_VAL_LOCK;
+        rdiff_comp_unlock <= PDIFF_DIV11_VAL_UNLOCK;
+      end
+      else begin
+        rcount_tc         <= {PPCLK_DIV11_TC[20:0], 1'b0};
+        rdiff_comp_lock   <= {PDIFF_DIV11_VAL_LOCK[14:0], 1'b0};
+        rdiff_comp_unlock <= {PDIFF_DIV11_VAL_UNLOCK[14:0], 1'b0};
+      end
+    end
+    //Div by 2 is enabled
+    else if (rdiv2 == 1'b1) begin
+      //Gear mode is 16/20
+      if (rgear == 1'b1) begin
+        rcount_tc         <= {1'b0,PPCLK_TC[21:1]};
+        rdiff_comp_lock   <= {1'b0,PDIFF_VAL_LOCK[15:1]};
+        rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]};
+      end
+      else begin
+        rcount_tc         <= PPCLK_TC;
+        rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+        rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+      end
+    end
+    //Both div by 11 and div by 2 are disabled
+    else begin
+      //Gear mode is 16/20
+      if (rgear == 1'b1) begin
+        rcount_tc         <= PPCLK_TC;
+        rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+        rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+      end
+      else begin
+        rcount_tc         <= {PPCLK_TC[20:0],1'b0};
+        rdiff_comp_lock   <= {PDIFF_VAL_LOCK[14:0],1'b0};
+        rdiff_comp_unlock <= {PDIFF_VAL_UNLOCK[14:0],1'b0};
+      end
+    end
+  end  
+end
+end
+endgenerate
+
+//For G8B10B protocol with Dynamic rate control enabled
+generate
+if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "G8B10B")) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rcount_tc         <= 22'd0;
+    rdiff_comp_lock   <= 16'd0;
+    rdiff_comp_unlock <= 16'd0;
+  end
+  else begin
+    //Terminal count logic
+    //Div by 2 is enabled
+    if (rdiv2 == 1'b1) begin
+      rcount_tc         <= {1'b0,PPCLK_TC[21:1]};
+      rdiff_comp_lock   <= {1'b0,PDIFF_VAL_LOCK[15:1]};
+      rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]};
+    end
+    else begin
+      rcount_tc         <= PPCLK_TC;
+      rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+      rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+    end
+  end  
+end
+end
+endgenerate
+
+
+//For CPRI protocol with Dynamic rate control is disabled
+generate
+if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "CPRI")) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rcount_tc         <= 22'd0;
+    rdiff_comp_lock   <= 16'd0;
+    rdiff_comp_unlock <= 16'd0;
+  end
+  else begin
+    //Terminal count logic for CPRI protocol
+    //Only if there is a change in the rate mode from the default
+    if (rcpri_mod_ch_st == 1'b1) begin
+      if (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) begin
+        case(sli_cpri_mode)
+          3'd0 : begin //For 0.6Gbps
+            rcount_tc         <= LPCLK_TC_0;
+            case(PLOL_SETTING)
+              'd0 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_00;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_00;
+              end
+              
+              'd1 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_01;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_01;
+              end
+              
+              'd2 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_02;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_02;
+              end
+              
+              'd3 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_03;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_03;
+              end
+              
+              default : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_00;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_00;
+              end
+            endcase
+          end
+          
+          3'd1 : begin //For 1.2Gbps
+            rcount_tc         <= LPCLK_TC_1;
+            case(PLOL_SETTING)
+              'd0 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_10;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_10;
+              end
+              
+              'd1 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_11;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_11;
+              end
+              
+              'd2 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_12;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_12;
+              end
+              
+              'd3 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_13;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_13;
+              end
+              
+              default : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_10;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_10;
+              end
+            endcase
+          end
+          
+          3'd2 : begin //For 2.4Gbps
+            rcount_tc         <= LPCLK_TC_2;
+            case(PLOL_SETTING)
+              'd0 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_20;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_20;
+              end
+              
+              'd1 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_21;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_21;
+              end
+              
+              'd2 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_22;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_22;
+              end
+              
+              'd3 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_23;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_23;
+              end
+              
+              default : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_20;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_20;
+              end
+            endcase
+          end
+          
+          3'd3 : begin //For 3.07Gbps
+            rcount_tc         <= LPCLK_TC_3;
+            case(PLOL_SETTING)
+              'd0 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_30;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_30;
+              end
+              
+              'd1 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_31;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_31;
+              end
+              
+              'd2 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_32;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_32;
+              end
+              
+              'd3 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_33;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_33;
+              end
+            endcase
+          end    
+              
+          3'd4 : begin //For 4.9125bps
+            rcount_tc         <= LPCLK_TC_4;
+            case(PLOL_SETTING)
+              'd0 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_40;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_40;
+              end
+              
+              'd1 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_41;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_41;
+              end
+              
+              'd2 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_42;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_42;
+              end
+              
+              'd3 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_43;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_43;
+              end  
+            
+              default : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_40;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_40;
+              end
+            endcase
+          end
+        
+          default : begin
+            rcount_tc         <= LPCLK_TC_0;
+            rdiff_comp_lock   <= LPDIFF_LOCK_00;
+            rdiff_comp_unlock <= LPDIFF_UNLOCK_00;
+          end
+        endcase
+      end
+    end
+    else begin
+      //If there is no change in the CPRI rate mode from default
+      rcount_tc         <= PPCLK_TC;
+      rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+      rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+    end  
+  end  
+end
+end
+endgenerate
+
+//For PCIe protocol with Dynamic rate control disabled
+generate
+if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "PCIE")) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rcount_tc         <= 22'd0;
+    rdiff_comp_lock   <= 16'd0;
+    rdiff_comp_unlock <= 16'd0;
+  end
+  else begin
+    //Terminal count logic
+    if (PPCIE_MAX_RATE == "2.5") begin
+      //2.5G mode is enabled
+      rcount_tc         <= PPCLK_TC;
+      rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+      rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+    end
+    else begin
+      //5G mode is enabled
+      if (rpcie_mode == 1'b1) begin
+        rcount_tc         <= PPCLK_TC;
+        rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+        rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+      end
+      else begin
+        //2.5G mode is enabled
+        rcount_tc         <= {1'b0,PPCLK_TC[21:1]};
+        rdiff_comp_lock   <= {1'b0,PDIFF_VAL_LOCK[15:1]};
+        rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]};
+      end 
+    end          
+  end  
+end
+end
+endgenerate
+
+//For all protocols other than CPRI & PCIe
+generate
+if ((PDYN_RATE_CTRL == "DISABLED") && ((PPROTOCOL != "CPRI") && (PPROTOCOL != "PCIE"))) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rcount_tc         <= 22'd0;
+    rdiff_comp_lock   <= 16'd0;
+    rdiff_comp_unlock <= 16'd0;
+  end
+  else begin
+    //Terminal count logic for all protocols other than CPRI & PCIe
+    rcount_tc         <= PPCLK_TC;
+    rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+    rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+  end  
+end
+end
+endgenerate
+
+
+// =============================================================================
+// Tx_pclk counter, Heartbeat and Differential value logic
+// =============================================================================
+always @(posedge sli_pclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    pcount      <= 22'd0;
+    pcount_diff <= 22'd65535;
+    phb_cnt     <= 3'd0;
+    phb         <= 1'b0;
+  end
+  else begin
+    //Counter logic
+    if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin
+      pcount <= 22'd0;
+    end
+    else begin
+      pcount <= pcount + 1;
+    end
+    
+    //Heartbeat logic
+    phb_cnt <= phb_cnt + 1;
+    
+    if ((phb_cnt < 3'd4) && (phb_cnt >= 3'd0)) begin
+      phb <= 1'b1;
+    end  
+    else begin
+      phb <= 1'b0;  
+    end 
+    
+    //Differential value logic
+    if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin
+      pcount_diff <= rcount_tc + ~(pcount) + 1;
+    end  
+    else if (ppul_sync_p2 == 1'b1 && ppul_sync_p3 == 1'b0) begin
+      if (pcount_diff[21] == 1'b1) begin
+        pcount_diff <= ~(pcount_diff) + 1;
+      end
+    end
+  end  
+end
+
+
+// =============================================================================
+// State transition logic for SLL FSM
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    sll_state <= LPLL_LOSS_ST; 
+  end
+  else begin
+    //Reasons to declare an immediate loss - Absence of Tx_pclk, Dynamic rate change for SDI or CPRI
+    if ((rstat_pclk == 1'b0) || (rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || 
+    (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin
+      sll_state <= LPLL_LOSS_ST;
+    end
+    else begin  
+      case(sll_state)
+        LPLL_LOSS_ST : begin
+          if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin
+            if (unlock) begin
+              sll_state <= LPLL_LOSS_ST;
+            end
+            else if (lock) begin
+              if (PLOL_SETTING == 2'd0) begin
+                sll_state <= LPLL_PRELOCK_ST;
+              end
+              else begin
+                sll_state <= LPLL_LOCK_ST;
+              end
+            end
+          end
+        end
+        
+        LPLL_LOCK_ST : begin
+          if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin
+            if (lock) begin
+              sll_state <= LPLL_LOCK_ST;
+            end
+            else begin
+              if (PLOL_SETTING == 2'd0) begin
+                sll_state <= LPLL_LOSS_ST;
+              end
+              else begin
+                sll_state <= LPLL_PRELOSS_ST;
+              end
+            end
+          end
+        end
+        
+        LPLL_PRELOCK_ST : begin
+          if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin
+            if (lock) begin
+              sll_state <= LPLL_LOCK_ST;
+            end
+            else begin
+              sll_state <= LPLL_PRELOSS_ST;
+            end
+          end
+        end
+        
+        LPLL_PRELOSS_ST : begin
+          if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin
+            if (unlock) begin
+              sll_state <= LPLL_PRELOSS_ST;
+            end
+            else if (lock) begin
+              sll_state <= LPLL_LOCK_ST;
+            end
+          end
+        end
+        
+        default: begin
+          sll_state <= LPLL_LOSS_ST;
+        end
+      endcase
+    end  
+  end  
+end
+
+
+// =============================================================================
+// Logic for Tx PLL Lock
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    pll_lock <= 1'b0; 
+  end
+  else begin
+    case(sll_state)
+      LPLL_LOSS_ST : begin
+        pll_lock <= 1'b0;
+      end
+      
+      LPLL_LOCK_ST : begin
+        pll_lock <= 1'b1;
+      end
+      
+      LPLL_PRELOSS_ST : begin
+        pll_lock <= 1'b0;
+      end
+      
+      default: begin
+        pll_lock <= 1'b0;
+      end
+    endcase
+  end  
+end
+
+assign slo_plol = ~(pll_lock);
+
+endmodule  
+
+
+//   ===========================================================================
+//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
+//   ---------------------------------------------------------------------------
+//   Copyright (c) 2015 by Lattice Semiconductor Corporation
+//   ALL RIGHTS RESERVED 
+//   ------------------------------------------------------------------
+//
+//   Permission:
+//
+//      Lattice SG Pte. Ltd. grants permission to use this code
+//      pursuant to the terms of the Lattice Reference Design License Agreement. 
+//
+//
+//   Disclaimer:
+//
+//      This VHDL or Verilog source code is intended as a design reference
+//      which illustrates how these types of functions can be implemented.
+//      It is the user's responsibility to verify their design for
+//      consistency and functionality through the use of formal
+//      verification methods.  Lattice provides no warranty
+//      regarding the use or functionality of this code.
+//
+//   ---------------------------------------------------------------------------
+//
+//                  Lattice SG Pte. Ltd.
+//                  101 Thomson Road, United Square #07-02 
+//                  Singapore 307591
+//
+//
+//                  TEL: 1-800-Lattice (USA and Canada)
+//                       +65-6631-2000 (Singapore)
+//                       +1-503-268-8001 (other locations)
+//
+//                  web: http://www.latticesemi.com/
+//                  email: techsupport@latticesemi.com
+//
+//   ---------------------------------------------------------------------------
+//
+// =============================================================================
+//                         FILE DETAILS
+// Project               : Synchronizer Logic
+// File                  : sync.v
+// Title                 : Synchronizer module
+// Description           : 
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.0
+// Author(s)             : AV
+// Mod. Date             : July 7, 2015
+// Changes Made          : Initial Creation
+// -----------------------------------------------------------------------------
+// Version               : 1.1
+// Author(s)             : EB
+// Mod. Date             : March 21, 2017
+// Changes Made          : 
+// =============================================================================
+
+`ifndef PCS_SYNC_MODULE
+`define PCS_SYNC_MODULE
+module sync ( 
+  clk,
+  rst,
+  data_in,
+  data_out
+  );
+  
+input  clk;                  //Clock in which the async data needs to be synchronized to
+input  rst;                  //Active high reset
+input  data_in;              //Asynchronous data
+output data_out;             //Synchronized data
+
+parameter PDATA_RST_VAL = 0; //Reset value for the registers
+
+reg data_p1;
+reg data_p2;
+
+// =============================================================================
+// Synchronization logic
+// =============================================================================
+always @(posedge clk or posedge rst) begin
+  if (rst == 1'b1) begin
+    data_p1 <= PDATA_RST_VAL;
+    data_p2 <= PDATA_RST_VAL; 
+  end
+  else begin
+    data_p1 <= data_in;
+    data_p2 <= data_p1;
+  end  
+end
+
+assign data_out = data_p2; 
+
+endmodule    
+`endif
+

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/.recordref b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/.recordref
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/_CMD_.CML b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/_CMD_.CML
new file mode 100644 (file)
index 0000000..9b9aad5
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/_CMD_.CML
@@ -0,0 +1 @@
+ -osyn  /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs  -top  sgmii_ecp5  -hdllog  /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr  -encrypt  -mp  4  -verification_mode 0  -vhdl  -prodtype  synplify_pro  -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver  -encrypt  -pro  -dmgen  /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/dm  -lite -ui -fid2 -ram -sharing on -ll 2000 -autosm  -ignore_undefined_lib  -lib work /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd  -verilog  -prodtype  synplify_pro  -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver   -I /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/  -I /home/soft/lattice/diamond/3.10_x64/synpbase/lib   -v2001  -devicelib  /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v  -devicelib  /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v  -encrypt  -pro  -dmgen  /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/dm  -ui -fid2 -ram -sharing on -ll 2000 -autosm  -lib work /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v  -jobname  "compiler" 
\ No newline at end of file

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/_cmd._cml b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/_cmd._cml
new file mode 100644 (file)
index 0000000..369b52b
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/_cmd._cml
@@ -0,0 +1 @@
+-link    -encrypt        -top sgmii_ecp5 -osyn /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer0.srs /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer1.srs   
\ No newline at end of file

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/dm/layer0.xdm b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/dm/layer0.xdm
new file mode 100644 (file)
index 0000000..44e72f3
--- /dev/null
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diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/run_options.txt b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/run_options.txt
new file mode 100644 (file)
index 0000000..f1e19db
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/run_options.txt
@@ -0,0 +1,76 @@
+#--  Synopsys, Inc.
+#--  Version M-2017.03L-SP1-1
+#--  Project file /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/run_options.txt
+#--  Written on Fri May 10 11:58:54 2019
+
+
+#project files
+add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd"
+add_file -verilog "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v"
+add_file -fpga_constraint "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.fdc"
+
+
+
+#implementation: "syn_results"
+impl -add syn_results -type fpga
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+
+#device options
+set_option -technology ecp5um
+set_option -part LFE5UM_25F
+set_option -package MG285C
+set_option -speed_grade -6
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -top_module "sgmii_ecp5"
+
+# hdl_compiler_options
+set_option -distributed_compile 0
+
+# mapper_without_write_options
+set_option -frequency 100
+set_option -srs_instrumentation 1
+
+# mapper_options
+set_option -write_verilog 1
+set_option -write_vhdl 1
+
+# Lattice XP
+set_option -maxfan 50
+set_option -disable_io_insertion 1
+set_option -retiming 0
+set_option -pipe 0
+set_option -forcegsr false
+set_option -fix_gated_and_generated_clocks 1
+set_option -rw_check_on_ram 1
+set_option -update_models_cp 0
+set_option -syn_edif_array_rename 1
+set_option -Write_declared_clocks_only 1
+
+# NFilter
+set_option -no_sequential_opt 0
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "./sgmii_ecp5.edn"
+
+#set log file 
+set_option log_file "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srf" 
+impl -active "syn_results"

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/scemi_cfg.txt b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/scemi_cfg.txt
new file mode 100644 (file)
index 0000000..868d437
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/scemi_cfg.txt
@@ -0,0 +1,3 @@
+## UMR3 MESSAGE PORT CONFIGURATION FILE
+## ************************************
+XTOR_DPI_MSG_PORT_UMR_ADDR_VERSION=0

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/scratchproject.prs b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/scratchproject.prs
new file mode 100644 (file)
index 0000000..b221cbd
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/scratchproject.prs
@@ -0,0 +1,74 @@
+#--  Synopsys, Inc.
+#--  Version M-2017.03L-SP1-1
+#--  Project file /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/scratchproject.prs
+
+#project files
+add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd"
+add_file -verilog "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v"
+add_file -fpga_constraint "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.fdc"
+
+
+
+#implementation: "syn_results"
+impl -add /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results -type fpga
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+
+#device options
+set_option -technology ecp5um
+set_option -part LFE5UM_25F
+set_option -package MG285C
+set_option -speed_grade -6
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -top_module "sgmii_ecp5"
+
+# hdl_compiler_options
+set_option -distributed_compile 0
+
+# mapper_without_write_options
+set_option -frequency 100
+set_option -srs_instrumentation 1
+
+# mapper_options
+set_option -write_verilog 1
+set_option -write_vhdl 1
+
+# Lattice XP
+set_option -maxfan 50
+set_option -disable_io_insertion 1
+set_option -retiming 0
+set_option -pipe 0
+set_option -forcegsr false
+set_option -fix_gated_and_generated_clocks 1
+set_option -rw_check_on_ram 1
+set_option -update_models_cp 0
+set_option -syn_edif_array_rename 1
+set_option -Write_declared_clocks_only 1
+
+# NFilter
+set_option -no_sequential_opt 0
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.edn"
+
+#set log file 
+set_option log_file "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srf" 
+impl -active "syn_results"

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.areasrr b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.areasrr
new file mode 100644 (file)
index 0000000..270aaa7
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.areasrr
@@ -0,0 +1,97 @@
+----------------------------------------------------------------------
+Report for cell sgmii_ecp5.v1
+
+Register bits: 221 of 24288 (1%)
+PIC Latch:       0
+I/O cells:       0
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                              CCU2C      113       100.0
+                               DCUA        1       100.0
+                            FD1P3BX       20       100.0
+                            FD1P3DX       92       100.0
+                            FD1S3BX       12       100.0
+                            FD1S3DX       97       100.0
+                                GSR        1       100.0
+                                INV        3       100.0
+                           ORCALUT4      153       100.0
+                              PFUMX        2       100.0
+                                PUR        1       100.0
+                                VHI        6       100.0
+                                VLO        6       100.0
+SUB MODULES 
+          sgmii_ecp5rsl_core_Z2_layer1        1       100.0
+          sgmii_ecp5sll_core_Z1_layer1        1       100.0
+                            sync_0s        1       100.0
+                          sync_0s_0        1       100.0
+                          sync_0s_6        1       100.0
+                            
+                         TOTAL           512           
+----------------------------------------------------------------------
+Report for cell sgmii_ecp5rsl_core_Z2_layer1.netlist
+     Instance path:  rsl_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                              CCU2C       51        45.1
+                            FD1P3BX        4        20.0
+                            FD1P3DX       74        80.4
+                            FD1S3BX       12       100.0
+                            FD1S3DX       37        38.1
+                           ORCALUT4       99        64.7
+                              PFUMX        2       100.0
+                                VHI        1        16.7
+                                VLO        1        16.7
+                            
+                         TOTAL           281           
+----------------------------------------------------------------------
+Report for cell sgmii_ecp5sll_core_Z1_layer1.netlist
+     Instance path:  sll_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                              CCU2C       62        54.9
+                            FD1P3BX       16        80.0
+                            FD1P3DX       18        19.6
+                            FD1S3DX       60        61.9
+                                INV        3       100.0
+                           ORCALUT4       54        35.3
+                                VHI        4        66.7
+                                VLO        4        66.7
+SUB MODULES 
+                            sync_0s        1       100.0
+                          sync_0s_0        1       100.0
+                          sync_0s_6        1       100.0
+                            
+                         TOTAL           224           
+----------------------------------------------------------------------
+Report for cell sync_0s_0.netlist
+  Original Cell name sync_0s
+     Instance path:  sll_inst.pdiff_sync_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                            FD1S3DX        2         2.1
+                                VHI        1        16.7
+                                VLO        1        16.7
+                            
+                         TOTAL             4           
+----------------------------------------------------------------------
+Report for cell sync_0s_6.netlist
+  Original Cell name sync_0s
+     Instance path:  sll_inst.rtc_sync_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                            FD1S3DX        2         2.1
+                                VHI        1        16.7
+                                VLO        1        16.7
+                            
+                         TOTAL             4           
+----------------------------------------------------------------------
+Report for cell sync_0s.netlist
+  Original Cell name sync_0s
+     Instance path:  sll_inst.phb_sync_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                            FD1S3DX        2         2.1
+                                VHI        1        16.7
+                                VLO        1        16.7
+                            
+                         TOTAL             4           

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.fse b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.fse
new file mode 100644 (file)
index 0000000..cc147f0
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.fse
@@ -0,0 +1,12 @@
+
+fsm_encoding {61801018011} sequential
+
+fsm_state_encoding {61801018011} LPLL_LOSS_ST {00}
+
+fsm_state_encoding {61801018011} LPLL_PRELOSS_ST {01}
+
+fsm_state_encoding {61801018011} LPLL_PRELOCK_ST {10}
+
+fsm_state_encoding {61801018011} LPLL_LOCK_ST {11}
+
+fsm_registers {61801018011} {sll_state[1]}  {sll_state[0]} 

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.htm b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.htm
new file mode 100644 (file)
index 0000000..31d89ed
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.htm
@@ -0,0 +1,9 @@
+<html>
+ <head>
+ <title>syntmp/sgmii_ecp5_srr.htm log file</title>
+ </head>
+ <frameset cols="20%, 80%">
+ <frame src="syntmp/sgmii_ecp5_toc.htm" name="tocFrame" />
+                                <frame src="syntmp/sgmii_ecp5_srr.htm" name="srrFrame"/>
+</frameset>
+ </html>

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.prj b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.prj
new file mode 100644 (file)
index 0000000..ef8c3fe
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.prj
@@ -0,0 +1,47 @@
+#-- Lattice Semiconductor Corporation Ltd.
+#-- Synplify OEM project file /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.prj
+#-- Written on Fri May 10 11:58:54 2019
+
+
+#device options
+set_option -technology ecp5um
+set_option -part LFE5UM-85F
+set_option -speed_grade 8
+
+#use verilog 2001 standard option
+set_option -vlog_std v2001
+
+#map options
+set_option -frequency 100
+set_option -fanout_limit 50
+set_option -disable_io_insertion true
+set_option -retiming false
+set_option -pipe false
+set_option -pipe false
+set_option -force_gsr false
+
+#simulation options
+set_option -write_verilog true
+set_option -write_vhdl true
+
+#timing analysis options
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#-- add_file options
+add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd"
+add_file -verilog -lib work "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v"
+add_file -constraint {"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.fdc"}
+
+#-- top module name
+set_option -top_module sgmii_ecp5
+
+#-- set result format/file last
+project -result_file "sgmii_ecp5.edn"
+
+#-- error message log file
+project -log_file sgmii_ecp5.srf
+
+#-- run Synplify with 'arrange VHDL file'
+project -run

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srd b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srd
new file mode 100644 (file)
index 0000000..2b7c9f8
Binary files /dev/null and b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srd differ

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srf b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srf
new file mode 100644 (file)
index 0000000..a063791
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srf
@@ -0,0 +1,1144 @@
+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
+#install: /home/soft/lattice/diamond/3.10_x64/synpbase
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Fri May 10 11:58:54 2019
+
+#Implementation: syn_results
+
+Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
+VHDL syntax check successful!
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Fri May 10 11:58:55 2019
+
+###########################################################]
+Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
+Verilog syntax check successful!
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Fri May 10 11:58:55 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
+VHDL syntax check successful!
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1.
+Post processing for work.sgmii_ecp5.v1
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB)
+
+
+Process completed successfully.
+# Fri May 10 11:58:55 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
+Verilog syntax check successful!
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work.
+
+       PDATA_RST_VAL=32'b00000000000000000000000000000000
+   Generated name = sync_0s
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work.
+
+       PPROTOCOL=24'b010001110100001001000101
+       PLOL_SETTING=32'b00000000000000000000000000000000
+       PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100
+       PPCIE_MAX_RATE=24'b001100100010111000110101
+       PDIFF_VAL_LOCK=32'b00000000000000000000000000010011
+       PDIFF_VAL_UNLOCK=32'b00000000000000000000000000100111
+       PPCLK_TC=32'b00000000000000010000000000000000
+       PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000
+       PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000
+       PPCLK_DIV11_TC=32'b00000000000000000000000000000000
+       LPLL_LOSS_ST=2'b00
+       LPLL_PRELOSS_ST=2'b01
+       LPLL_PRELOCK_ST=2'b10
+       LPLL_LOCK_ST=2'b11
+       LRCLK_TC=16'b1111111111111111
+       LRCLK_TC_PUL_WIDTH=16'b0000000000110010
+       LHB_WAIT_CNT=8'b11111111
+       LPCLK_TC_0=32'b00000000000000001000000000000000
+       LPCLK_TC_1=32'b00000000000000010000000000000000
+       LPCLK_TC_2=32'b00000000000000100000000000000000
+       LPCLK_TC_3=32'b00000000000000101000000000000000
+       LPCLK_TC_4=32'b00000000000000010000000000000000
+       LPDIFF_LOCK_00=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_10=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_20=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_30=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_40=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_01=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_11=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_21=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_31=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_41=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_02=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_12=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_22=32'b00000000000000000000000011000100
+       LPDIFF_LOCK_32=32'b00000000000000000000000011110101
+       LPDIFF_LOCK_42=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_03=32'b00000000000000000000000010000011
+       LPDIFF_LOCK_13=32'b00000000000000000000000100000110
+       LPDIFF_LOCK_23=32'b00000000000000000000001000001100
+       LPDIFF_LOCK_33=32'b00000000000000000000001010001111
+       LPDIFF_LOCK_43=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011
+       LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110
+       LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010
+       LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001
+       LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111
+       LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000
+       LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000
+       LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000
+       LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100
+       LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001
+       LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010
+       LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111
+       LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001
+   Generated name = sgmii_ecp5sll_core_Z1_layer1
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment.
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 17 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work.
+
+       pnum_channels=32'b00000000000000000000000000000001
+       pprotocol=24'b010001110100001001000101
+       pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
+       pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_tx_rdy=32'b00000000000000000000101110111000
+       pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_rx_rdy=32'b00000000000000000000101110111000
+       wa_num_cycles=32'b00000000000000000000010000000000
+       dac_num_cycles=32'b00000000000000000000000000000011
+       lreset_pwidth=32'b00000000000000000000000000000011
+       lwait_b4_trst=32'b00000000000010111110101111000010
+       lwait_b4_trst_s=32'b00000000000000000000001100001101
+       lplol_cnt_width=32'b00000000000000000000000000010100
+       lwait_after_plol0=32'b00000000000000000000000000000100
+       lwait_b4_rrst=32'b00000000000000101100000000000000
+       lrrst_wait_width=32'b00000000000000000000000000010100
+       lwait_after_rrst=32'b00000000000011000011010100000000
+       lwait_b4_rrst_s=32'b00000000000000000000000111001100
+       lrlol_cnt_width=32'b00000000000000000000000000010011
+       lwait_after_lols=32'b00000000000000001100010000000000
+       lwait_after_lols_s=32'b00000000000000000000000010010110
+       llols_cnt_width=32'b00000000000000000000000000010010
+       lrdb_max=32'b00000000000000000000000000001111
+       ltxr_wait_width=32'b00000000000000000000000000001100
+       lrxr_wait_width=32'b00000000000000000000000000001100
+   Generated name = sgmii_ecp5rsl_core_Z2_layer1
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_unlock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 4 to 3 of genblk5.rdiff_comp_lock[4:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[2]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[16]. Make sure that there are no unused intermediate registers.
+@N: CL201 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state.
+Extracted state machine for register sll_state
+State machine has 4 reachable states with original encodings of:
+   00
+   01
+   10
+   11
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB)
+
+
+Process completed successfully.
+# Fri May 10 11:58:56 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+
+=======================================================================================
+For a summary of linker messages for components that did not bind, please see log file:
+@L: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.linkerlog
+=======================================================================================
+
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 11:58:56 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 11:58:56 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 11:58:57 2019
+
+###########################################################]
+Pre-mapping Report
+
+# Fri May 10 11:58:57 2019
+
+Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.fdc
+@L: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt 
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt" file 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)
+
+@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances.
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist sgmii_ecp5
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+
+Clock Summary
+******************
+
+          Start                                 Requested     Requested     Clock        Clock                   Clock
+Level     Clock                                 Frequency     Period        Type         Group                   Load 
+----------------------------------------------------------------------------------------------------------------------
+0 -       System                                100.0 MHz     10.000        system       system_clkgroup         0    
+                                                                                                                      
+0 -       sgmii_ecp5|pll_refclki                100.0 MHz     10.000        inferred     Inferred_clkgroup_0     93   
+                                                                                                                      
+0 -       sgmii_ecp5|rxrefclk                   100.0 MHz     10.000        inferred     Inferred_clkgroup_1     77   
+                                                                                                                      
+0 -       sgmii_ecp5|tx_pclk_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_2     53   
+======================================================================================================================
+
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   10 -> 10
+   11 -> 11
+@N: MO225 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 144MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Fri May 10 11:58:58 2019
+
+###########################################################]
+Map & Optimize Report
+
+# Fri May 10 11:58:58 2019
+
+Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   10 -> 10
+   11 -> 11
+@N: MO225 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":909:3:909:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":527:3:527:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] 
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 145MB)
+
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+   1           0h:00m:01s                   5.36ns              154 /       221
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+3 non-gated/non-generated clock tree(s) driving 221 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+============================================= Non-Gated/Non-Generated Clocks =============================================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                                   
+--------------------------------------------------------------------------------------------------------------------------
+@K:CKID0001       pll_refclki         port                   91         rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]
+@K:CKID0002       rxrefclk            port                   77         rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]
+@K:CKID0003       DCU0_inst           DCUA                   53         sll_inst.pcount[21]                               
+==========================================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 148MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 148MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.edn
+M-2017.03L-SP1-1
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 153MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 153MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+@W: MT246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":162:4:162:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"
+@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"
+@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk"
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Fri May 10 11:59:02 2019
+#
+
+
+Top view:               sgmii_ecp5
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.fdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 4.079
+
+                                      Requested     Estimated     Requested     Estimated               Clock        Clock              
+Starting Clock                        Frequency     Frequency     Period        Period        Slack     Type         Group              
+----------------------------------------------------------------------------------------------------------------------------------------
+sgmii_ecp5|pll_refclki                100.0 MHz     168.9 MHz     10.000        5.921         4.079     inferred     Inferred_clkgroup_0
+sgmii_ecp5|rxrefclk                   100.0 MHz     170.5 MHz     10.000        5.864         4.136     inferred     Inferred_clkgroup_1
+sgmii_ecp5|tx_pclk_inferred_clock     100.0 MHz     237.5 MHz     10.000        4.211         5.789     inferred     Inferred_clkgroup_2
+System                                100.0 MHz     840.7 MHz     10.000        1.190         8.810     system       system_clkgroup    
+========================================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                                                                |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+Starting                           Ending                             |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+System                             sgmii_ecp5|rxrefclk                |  10.000      8.811  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             System                             |  10.000      8.253  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             sgmii_ecp5|pll_refclki             |  10.000      4.079  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             sgmii_ecp5|tx_pclk_inferred_clock  |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|rxrefclk                System                             |  10.000      8.184  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|rxrefclk                sgmii_ecp5|rxrefclk                |  10.000      4.136  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|tx_pclk_inferred_clock  sgmii_ecp5|pll_refclki             |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|tx_pclk_inferred_clock  sgmii_ecp5|tx_pclk_inferred_clock  |  10.000      5.789  |  No paths    -      |  No paths    -      |  No paths    -    
+============================================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|pll_refclki
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                   Starting                                                        Arrival          
+Instance                           Reference                  Type        Pin     Net              Time        Slack
+                                   Clock                                                                            
+--------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[2]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[2]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[3]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[3]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[17]     sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[17]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[19]     sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[19]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[1]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[1]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[4]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[4]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[5]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[5]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[6]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[6]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[7]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[7]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[8]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[8]      0.907       4.684
+====================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                   Starting                                                          Required          
+Instance                           Reference                  Type        Pin     Net                Time         Slack
+                                   Clock                                                                               
+-----------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[19]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[19]     9.946        4.079
+rsl_inst.genblk1\.plol_cnt[17]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[17]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[18]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[18]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[15]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[15]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[16]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[16]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[13]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[13]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[14]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[14]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[11]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[11]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[12]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[12]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[9]      sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[9]      9.946        4.383
+=======================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.867
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     4.079
+
+    Number of logic level(s):                15
+    Starting point:                          rsl_inst.genblk1\.plol_cnt[2] / Q
+    Ending point:                            rsl_inst.genblk1\.plol_cnt[19] / D
+    The start point is clocked by            sgmii_ecp5|pll_refclki [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|pll_refclki [rising] on pin CK
+
+Instance / Net                                        Pin      Pin               Arrival     No. of    
+Name                                     Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[2]            FD1S3DX      Q        Out     0.907     0.907       -         
+plol_cnt[2]                              Net          -        -       -         -           2         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     Z        Out     0.606     1.513       -         
+un1_plol_cnt_tc_10                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     Z        Out     0.606     2.119       -         
+un1_plol_cnt_tc_14                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     Z        Out     0.762     2.881       -         
+un1_plol_cnt_tc                          Net          -        -       -         -           5         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     B        In      0.000     2.881       -         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     Z        Out     0.840     3.721       -         
+plol_cnt                                 Net          -        -       -         -           21        
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.721       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.621       -         
+plol_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.621       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.682       -         
+plol_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.682       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.743       -         
+plol_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.743       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.804       -         
+plol_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.804       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.865       -         
+plol_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.865       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.926       -         
+plol_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.926       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.987       -         
+plol_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.987       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.048       -         
+plol_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.048       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.109       -         
+plol_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.109       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        COUT     Out     0.061     5.170       -         
+plol_cnt_cry[18]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        CIN      In      0.000     5.170       -         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        S0       Out     0.698     5.867       -         
+plol_cnt_s[19]                           Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt[19]           FD1S3DX      D        In      0.000     5.867       -         
+=======================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|rxrefclk
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                    Starting                                                      Arrival          
+Instance                            Reference               Type        Pin     Net               Time        Slack
+                                    Clock                                                                          
+-------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[7]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[7]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[8]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[8]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[9]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[9]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[10]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[10]     0.907       4.136
+rsl_inst.genblk2\.rlols0_cnt[1]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[1]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[2]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[2]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[3]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[3]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[4]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[4]     0.907       4.170
+rsl_inst.genblk2\.rxs_rst           sgmii_ecp5|rxrefclk     FD1P3DX     Q       rxs_rst           1.015       4.700
+rsl_inst.genblk2\.rlol1_cnt[0]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[0]      0.907       4.742
+===================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                     Starting                                                         Required          
+Instance                             Reference               Type        Pin     Net                  Time         Slack
+                                     Clock                                                                              
+------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[17]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[17]      9.946        4.136
+rsl_inst.genblk2\.rlol1_cnt[18]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[18]      9.946        4.136
+rsl_inst.genblk2\.rlols0_cnt[17]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rlols0_cnt_s[17]     9.946        4.170
+rsl_inst.genblk2\.rlol1_cnt[15]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[15]      9.946        4.197
+rsl_inst.genblk2\.rlol1_cnt[16]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[16]      9.946        4.197
+rsl_inst.genblk2\.rlols0_cnt[15]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rlols0_cnt_s[15]     9.946        4.231
+rsl_inst.genblk2\.rlols0_cnt[16]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rlols0_cnt_s[16]     9.946        4.231
+rsl_inst.genblk2\.rlol1_cnt[13]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[13]      9.946        4.258
+rsl_inst.genblk2\.rlol1_cnt[14]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[14]      9.946        4.258
+rsl_inst.genblk2\.rlols0_cnt[13]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rlols0_cnt_s[13]     9.946        4.292
+========================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.809
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.136
+
+    Number of logic level(s):                14
+    Starting point:                          rsl_inst.genblk2\.rlol1_cnt[7] / Q
+    Ending point:                            rsl_inst.genblk2\.rlol1_cnt[18] / D
+    The start point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+
+Instance / Net                                         Pin      Pin               Arrival     No. of    
+Name                                      Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[7]            FD1P3DX      Q        Out     0.907     0.907       -         
+rlol1_cnt[7]                              Net          -        -       -         -           2         
+rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     Z        Out     0.606     1.513       -         
+rlol1_cnt_tc_1_10                         Net          -        -       -         -           1         
+rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     Z        Out     0.606     2.119       -         
+rlol1_cnt_tc_1_14                         Net          -        -       -         -           1         
+rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     Z        Out     0.768     2.887       -         
+rlol1_cnt_tc_1                            Net          -        -       -         -           6         
+rsl_inst.genblk2\.rlos_db_p1_RNIS0OP      ORCALUT4     A        In      0.000     2.887       -         
+rsl_inst.genblk2\.rlos_db_p1_RNIS0OP      ORCALUT4     Z        Out     0.837     3.724       -         
+rlol1_cnt                                 Net          -        -       -         -           20        
+rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.724       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.624       -         
+rlol1_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.624       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.685       -         
+rlol1_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.685       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.746       -         
+rlol1_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.746       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.807       -         
+rlol1_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.807       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.868       -         
+rlol1_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.868       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.929       -         
+rlol1_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.929       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.990       -         
+rlol1_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.990       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.051       -         
+rlol1_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.051       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.112       -         
+rlol1_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.112       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        S1       Out     0.698     5.809       -         
+rlol1_cnt_s[18]                           Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt[18]           FD1P3DX      D        In      0.000     5.809       -         
+========================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|tx_pclk_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                            Starting                                                                   Arrival          
+Instance                    Reference                             Type        Pin     Net              Time        Slack
+                            Clock                                                                                       
+------------------------------------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1       sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p1     1.098       5.789
+sll_inst.ppul_sync_p2       sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p2     1.098       5.789
+sll_inst.pcount_diff[0]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_0      0.985       6.147
+sll_inst.pcount[0]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[0]        0.955       6.178
+sll_inst.pcount_diff[1]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_1      0.955       6.239
+sll_inst.pcount_diff[2]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_2      0.955       6.239
+sll_inst.pcount[1]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[1]        0.907       6.287
+sll_inst.pcount[2]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[2]        0.907       6.287
+sll_inst.pcount_diff[3]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_3      0.955       6.300
+sll_inst.pcount_diff[4]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_4      0.955       6.300
+========================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                             Starting                                                                                  Required          
+Instance                     Reference                             Type        Pin     Net                             Time         Slack
+                             Clock                                                                                                       
+-----------------------------------------------------------------------------------------------------------------------------------------
+sll_inst.pcount[21]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[21]                    9.946        5.789
+sll_inst.pcount[19]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[19]                    9.946        5.850
+sll_inst.pcount[20]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[20]                    9.946        5.850
+sll_inst.pcount[17]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[17]                    9.946        5.911
+sll_inst.pcount[18]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[18]                    9.946        5.911
+sll_inst.pcount[15]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[15]                    9.946        5.972
+sll_inst.pcount[16]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[16]                    9.946        5.972
+sll_inst.pcount[13]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[13]                    9.946        6.033
+sll_inst.pcount[14]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[14]                    9.946        6.033
+sll_inst.pcount_diff[21]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3DX     D       un1_pcount_diff_1_s_21_0_S0     9.946        6.034
+=========================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      4.157
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 5.789
+
+    Number of logic level(s):                13
+    Starting point:                          sll_inst.ppul_sync_p1 / Q
+    Ending point:                            sll_inst.pcount[21] / D
+    The start point is clocked by            sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
+
+Instance / Net                             Pin      Pin               Arrival     No. of    
+Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1         FD1S3DX      Q        Out     1.098     1.098       -         
+ppul_sync_p1                  Net          -        -       -         -           25        
+sll_inst.pcount10_0_o3        ORCALUT4     A        In      0.000     1.098       -         
+sll_inst.pcount10_0_o3        ORCALUT4     Z        Out     0.851     1.950       -         
+N_8                           Net          -        -       -         -           25        
+sll_inst.pcount_cry_0[0]      CCU2C        A1       In      0.000     1.950       -         
+sll_inst.pcount_cry_0[0]      CCU2C        COUT     Out     0.900     2.850       -         
+pcount_cry[0]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[1]      CCU2C        CIN      In      0.000     2.850       -         
+sll_inst.pcount_cry_0[1]      CCU2C        COUT     Out     0.061     2.911       -         
+pcount_cry[2]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[3]      CCU2C        CIN      In      0.000     2.911       -         
+sll_inst.pcount_cry_0[3]      CCU2C        COUT     Out     0.061     2.972       -         
+pcount_cry[4]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[5]      CCU2C        CIN      In      0.000     2.972       -         
+sll_inst.pcount_cry_0[5]      CCU2C        COUT     Out     0.061     3.033       -         
+pcount_cry[6]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[7]      CCU2C        CIN      In      0.000     3.033       -         
+sll_inst.pcount_cry_0[7]      CCU2C        COUT     Out     0.061     3.094       -         
+pcount_cry[8]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[9]      CCU2C        CIN      In      0.000     3.094       -         
+sll_inst.pcount_cry_0[9]      CCU2C        COUT     Out     0.061     3.155       -         
+pcount_cry[10]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[11]     CCU2C        CIN      In      0.000     3.155       -         
+sll_inst.pcount_cry_0[11]     CCU2C        COUT     Out     0.061     3.216       -         
+pcount_cry[12]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[13]     CCU2C        CIN      In      0.000     3.216       -         
+sll_inst.pcount_cry_0[13]     CCU2C        COUT     Out     0.061     3.277       -         
+pcount_cry[14]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[15]     CCU2C        CIN      In      0.000     3.277       -         
+sll_inst.pcount_cry_0[15]     CCU2C        COUT     Out     0.061     3.338       -         
+pcount_cry[16]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[17]     CCU2C        CIN      In      0.000     3.338       -         
+sll_inst.pcount_cry_0[17]     CCU2C        COUT     Out     0.061     3.399       -         
+pcount_cry[18]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[19]     CCU2C        CIN      In      0.000     3.399       -         
+sll_inst.pcount_cry_0[19]     CCU2C        COUT     Out     0.061     3.460       -         
+pcount_cry[20]                Net          -        -       -         -           1         
+sll_inst.pcount_s_0[21]       CCU2C        CIN      In      0.000     3.460       -         
+sll_inst.pcount_s_0[21]       CCU2C        S0       Out     0.698     4.157       -         
+pcount_s[21]                  Net          -        -       -         -           1         
+sll_inst.pcount[21]           FD1S3DX      D        In      0.000     4.157       -         
+============================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                                 Arrival          
+Instance      Reference     Type     Pin              Net              Time        Slack
+              Clock                                                                     
+----------------------------------------------------------------------------------------
+DCU0_inst     System        DCUA     CH0_FFS_RLOL     rx_cdr_lol_s     0.000       8.810
+DCU0_inst     System        DCUA     CH0_FFS_RLOS     rx_los_low_s     0.000       8.810
+========================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                       Starting                                                            Required          
+Instance                                               Reference     Type        Pin     Net                               Time         Slack
+                                                       Clock                                                                                 
+---------------------------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     SP      un2_rdo_serdes_rst_dual_c_2_i     9.806        8.810
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     D       rxpr_appd_RNO[0]                  9.946        9.556
+rsl_inst.genblk2\.rlol_p1                              System        FD1S3DX     D       rx_cdr_lol_s                      9.946        9.946
+rsl_inst.genblk2\.rlos_p1                              System        FD1S3DX     D       rx_los_low_s                      9.946        9.946
+=============================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.194
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.806
+
+    - Propagation time:                      0.996
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 8.810
+
+    Number of logic level(s):                2
+    Starting point:                          DCU0_inst / CH0_FFS_RLOL
+    Ending point:                            rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+
+Instance / Net                                                            Pin              Pin               Arrival     No. of    
+Name                                                         Type         Name             Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------------------------------------------------------
+DCU0_inst                                                    DCUA         CH0_FFS_RLOL     Out     0.000     0.000       -         
+rx_cdr_lol_s                                                 Net          -                -       -         -           4         
+rsl_inst.un2_rdo_serdes_rst_dual_c_1_1                       ORCALUT4     A                In      0.000     0.000       -         
+rsl_inst.un2_rdo_serdes_rst_dual_c_1_1                       ORCALUT4     Z                Out     0.606     0.606       -         
+un2_rdo_serdes_rst_dual_c_1_1                                Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0]     ORCALUT4     B                In      0.000     0.606       -         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0]     ORCALUT4     Z                Out     0.390     0.996       -         
+un2_rdo_serdes_rst_dual_c_2_i                                Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]           FD1P3DX      SP               In      0.000     0.996       -         
+===================================================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 221 of 24288 (1%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+CCU2C:          113
+DCUA:           1
+FD1P3BX:        20
+FD1P3DX:        92
+FD1S3BX:        12
+FD1S3DX:        97
+GSR:            1
+INV:            3
+ORCALUT4:       153
+PFUMX:          2
+PUR:            1
+VHI:            6
+VLO:            6
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 153MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Fri May 10 11:59:02 2019
+
+###########################################################]

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srm b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srm
new file mode 100644 (file)
index 0000000..bacca77
Binary files /dev/null and b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srm differ

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srr b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srr
new file mode 100644 (file)
index 0000000..a063791
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srr
@@ -0,0 +1,1144 @@
+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
+#install: /home/soft/lattice/diamond/3.10_x64/synpbase
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Fri May 10 11:58:54 2019
+
+#Implementation: syn_results
+
+Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
+VHDL syntax check successful!
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Fri May 10 11:58:55 2019
+
+###########################################################]
+Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
+Verilog syntax check successful!
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Fri May 10 11:58:55 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
+VHDL syntax check successful!
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1.
+Post processing for work.sgmii_ecp5.v1
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB)
+
+
+Process completed successfully.
+# Fri May 10 11:58:55 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
+Verilog syntax check successful!
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work.
+
+       PDATA_RST_VAL=32'b00000000000000000000000000000000
+   Generated name = sync_0s
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work.
+
+       PPROTOCOL=24'b010001110100001001000101
+       PLOL_SETTING=32'b00000000000000000000000000000000
+       PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100
+       PPCIE_MAX_RATE=24'b001100100010111000110101
+       PDIFF_VAL_LOCK=32'b00000000000000000000000000010011
+       PDIFF_VAL_UNLOCK=32'b00000000000000000000000000100111
+       PPCLK_TC=32'b00000000000000010000000000000000
+       PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000
+       PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000
+       PPCLK_DIV11_TC=32'b00000000000000000000000000000000
+       LPLL_LOSS_ST=2'b00
+       LPLL_PRELOSS_ST=2'b01
+       LPLL_PRELOCK_ST=2'b10
+       LPLL_LOCK_ST=2'b11
+       LRCLK_TC=16'b1111111111111111
+       LRCLK_TC_PUL_WIDTH=16'b0000000000110010
+       LHB_WAIT_CNT=8'b11111111
+       LPCLK_TC_0=32'b00000000000000001000000000000000
+       LPCLK_TC_1=32'b00000000000000010000000000000000
+       LPCLK_TC_2=32'b00000000000000100000000000000000
+       LPCLK_TC_3=32'b00000000000000101000000000000000
+       LPCLK_TC_4=32'b00000000000000010000000000000000
+       LPDIFF_LOCK_00=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_10=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_20=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_30=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_40=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_01=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_11=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_21=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_31=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_41=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_02=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_12=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_22=32'b00000000000000000000000011000100
+       LPDIFF_LOCK_32=32'b00000000000000000000000011110101
+       LPDIFF_LOCK_42=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_03=32'b00000000000000000000000010000011
+       LPDIFF_LOCK_13=32'b00000000000000000000000100000110
+       LPDIFF_LOCK_23=32'b00000000000000000000001000001100
+       LPDIFF_LOCK_33=32'b00000000000000000000001010001111
+       LPDIFF_LOCK_43=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011
+       LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110
+       LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010
+       LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001
+       LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111
+       LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000
+       LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000
+       LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000
+       LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100
+       LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001
+       LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010
+       LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111
+       LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001
+   Generated name = sgmii_ecp5sll_core_Z1_layer1
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment.
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 17 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work.
+
+       pnum_channels=32'b00000000000000000000000000000001
+       pprotocol=24'b010001110100001001000101
+       pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
+       pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_tx_rdy=32'b00000000000000000000101110111000
+       pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_rx_rdy=32'b00000000000000000000101110111000
+       wa_num_cycles=32'b00000000000000000000010000000000
+       dac_num_cycles=32'b00000000000000000000000000000011
+       lreset_pwidth=32'b00000000000000000000000000000011
+       lwait_b4_trst=32'b00000000000010111110101111000010
+       lwait_b4_trst_s=32'b00000000000000000000001100001101
+       lplol_cnt_width=32'b00000000000000000000000000010100
+       lwait_after_plol0=32'b00000000000000000000000000000100
+       lwait_b4_rrst=32'b00000000000000101100000000000000
+       lrrst_wait_width=32'b00000000000000000000000000010100
+       lwait_after_rrst=32'b00000000000011000011010100000000
+       lwait_b4_rrst_s=32'b00000000000000000000000111001100
+       lrlol_cnt_width=32'b00000000000000000000000000010011
+       lwait_after_lols=32'b00000000000000001100010000000000
+       lwait_after_lols_s=32'b00000000000000000000000010010110
+       llols_cnt_width=32'b00000000000000000000000000010010
+       lrdb_max=32'b00000000000000000000000000001111
+       ltxr_wait_width=32'b00000000000000000000000000001100
+       lrxr_wait_width=32'b00000000000000000000000000001100
+   Generated name = sgmii_ecp5rsl_core_Z2_layer1
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_unlock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 4 to 3 of genblk5.rdiff_comp_lock[4:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[2]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[16]. Make sure that there are no unused intermediate registers.
+@N: CL201 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state.
+Extracted state machine for register sll_state
+State machine has 4 reachable states with original encodings of:
+   00
+   01
+   10
+   11
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB)
+
+
+Process completed successfully.
+# Fri May 10 11:58:56 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+
+=======================================================================================
+For a summary of linker messages for components that did not bind, please see log file:
+@L: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.linkerlog
+=======================================================================================
+
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 11:58:56 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 11:58:56 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 11:58:57 2019
+
+###########################################################]
+Pre-mapping Report
+
+# Fri May 10 11:58:57 2019
+
+Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.fdc
+@L: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt 
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt" file 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)
+
+@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances.
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist sgmii_ecp5
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+
+Clock Summary
+******************
+
+          Start                                 Requested     Requested     Clock        Clock                   Clock
+Level     Clock                                 Frequency     Period        Type         Group                   Load 
+----------------------------------------------------------------------------------------------------------------------
+0 -       System                                100.0 MHz     10.000        system       system_clkgroup         0    
+                                                                                                                      
+0 -       sgmii_ecp5|pll_refclki                100.0 MHz     10.000        inferred     Inferred_clkgroup_0     93   
+                                                                                                                      
+0 -       sgmii_ecp5|rxrefclk                   100.0 MHz     10.000        inferred     Inferred_clkgroup_1     77   
+                                                                                                                      
+0 -       sgmii_ecp5|tx_pclk_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_2     53   
+======================================================================================================================
+
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   10 -> 10
+   11 -> 11
+@N: MO225 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 144MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Fri May 10 11:58:58 2019
+
+###########################################################]
+Map & Optimize Report
+
+# Fri May 10 11:58:58 2019
+
+Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   10 -> 10
+   11 -> 11
+@N: MO225 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":909:3:909:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":527:3:527:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] 
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 145MB)
+
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+   1           0h:00m:01s                   5.36ns              154 /       221
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+3 non-gated/non-generated clock tree(s) driving 221 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+============================================= Non-Gated/Non-Generated Clocks =============================================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                                   
+--------------------------------------------------------------------------------------------------------------------------
+@K:CKID0001       pll_refclki         port                   91         rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]
+@K:CKID0002       rxrefclk            port                   77         rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]
+@K:CKID0003       DCU0_inst           DCUA                   53         sll_inst.pcount[21]                               
+==========================================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 148MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 148MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.edn
+M-2017.03L-SP1-1
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 153MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 153MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+@W: MT246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":162:4:162:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"
+@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"
+@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk"
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Fri May 10 11:59:02 2019
+#
+
+
+Top view:               sgmii_ecp5
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.fdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 4.079
+
+                                      Requested     Estimated     Requested     Estimated               Clock        Clock              
+Starting Clock                        Frequency     Frequency     Period        Period        Slack     Type         Group              
+----------------------------------------------------------------------------------------------------------------------------------------
+sgmii_ecp5|pll_refclki                100.0 MHz     168.9 MHz     10.000        5.921         4.079     inferred     Inferred_clkgroup_0
+sgmii_ecp5|rxrefclk                   100.0 MHz     170.5 MHz     10.000        5.864         4.136     inferred     Inferred_clkgroup_1
+sgmii_ecp5|tx_pclk_inferred_clock     100.0 MHz     237.5 MHz     10.000        4.211         5.789     inferred     Inferred_clkgroup_2
+System                                100.0 MHz     840.7 MHz     10.000        1.190         8.810     system       system_clkgroup    
+========================================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                                                                |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+Starting                           Ending                             |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+System                             sgmii_ecp5|rxrefclk                |  10.000      8.811  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             System                             |  10.000      8.253  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             sgmii_ecp5|pll_refclki             |  10.000      4.079  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             sgmii_ecp5|tx_pclk_inferred_clock  |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|rxrefclk                System                             |  10.000      8.184  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|rxrefclk                sgmii_ecp5|rxrefclk                |  10.000      4.136  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|tx_pclk_inferred_clock  sgmii_ecp5|pll_refclki             |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|tx_pclk_inferred_clock  sgmii_ecp5|tx_pclk_inferred_clock  |  10.000      5.789  |  No paths    -      |  No paths    -      |  No paths    -    
+============================================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|pll_refclki
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                   Starting                                                        Arrival          
+Instance                           Reference                  Type        Pin     Net              Time        Slack
+                                   Clock                                                                            
+--------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[2]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[2]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[3]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[3]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[17]     sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[17]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[19]     sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[19]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[1]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[1]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[4]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[4]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[5]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[5]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[6]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[6]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[7]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[7]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[8]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[8]      0.907       4.684
+====================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                   Starting                                                          Required          
+Instance                           Reference                  Type        Pin     Net                Time         Slack
+                                   Clock                                                                               
+-----------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[19]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[19]     9.946        4.079
+rsl_inst.genblk1\.plol_cnt[17]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[17]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[18]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[18]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[15]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[15]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[16]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[16]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[13]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[13]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[14]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[14]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[11]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[11]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[12]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[12]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[9]      sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[9]      9.946        4.383
+=======================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.867
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     4.079
+
+    Number of logic level(s):                15
+    Starting point:                          rsl_inst.genblk1\.plol_cnt[2] / Q
+    Ending point:                            rsl_inst.genblk1\.plol_cnt[19] / D
+    The start point is clocked by            sgmii_ecp5|pll_refclki [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|pll_refclki [rising] on pin CK
+
+Instance / Net                                        Pin      Pin               Arrival     No. of    
+Name                                     Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[2]            FD1S3DX      Q        Out     0.907     0.907       -         
+plol_cnt[2]                              Net          -        -       -         -           2         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     Z        Out     0.606     1.513       -         
+un1_plol_cnt_tc_10                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     Z        Out     0.606     2.119       -         
+un1_plol_cnt_tc_14                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     Z        Out     0.762     2.881       -         
+un1_plol_cnt_tc                          Net          -        -       -         -           5         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     B        In      0.000     2.881       -         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     Z        Out     0.840     3.721       -         
+plol_cnt                                 Net          -        -       -         -           21        
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.721       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.621       -         
+plol_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.621       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.682       -         
+plol_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.682       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.743       -         
+plol_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.743       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.804       -         
+plol_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.804       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.865       -         
+plol_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.865       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.926       -         
+plol_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.926       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.987       -         
+plol_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.987       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.048       -         
+plol_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.048       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.109       -         
+plol_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.109       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        COUT     Out     0.061     5.170       -         
+plol_cnt_cry[18]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        CIN      In      0.000     5.170       -         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        S0       Out     0.698     5.867       -         
+plol_cnt_s[19]                           Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt[19]           FD1S3DX      D        In      0.000     5.867       -         
+=======================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|rxrefclk
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                    Starting                                                      Arrival          
+Instance                            Reference               Type        Pin     Net               Time        Slack
+                                    Clock                                                                          
+-------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[7]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[7]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[8]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[8]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[9]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[9]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[10]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[10]     0.907       4.136
+rsl_inst.genblk2\.rlols0_cnt[1]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[1]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[2]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[2]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[3]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[3]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[4]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[4]     0.907       4.170
+rsl_inst.genblk2\.rxs_rst           sgmii_ecp5|rxrefclk     FD1P3DX     Q       rxs_rst           1.015       4.700
+rsl_inst.genblk2\.rlol1_cnt[0]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[0]      0.907       4.742
+===================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                     Starting                                                         Required          
+Instance                             Reference               Type        Pin     Net                  Time         Slack
+                                     Clock                                                                              
+------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[17]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[17]      9.946        4.136
+rsl_inst.genblk2\.rlol1_cnt[18]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[18]      9.946        4.136
+rsl_inst.genblk2\.rlols0_cnt[17]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rlols0_cnt_s[17]     9.946        4.170
+rsl_inst.genblk2\.rlol1_cnt[15]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[15]      9.946        4.197
+rsl_inst.genblk2\.rlol1_cnt[16]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[16]      9.946        4.197
+rsl_inst.genblk2\.rlols0_cnt[15]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rlols0_cnt_s[15]     9.946        4.231
+rsl_inst.genblk2\.rlols0_cnt[16]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rlols0_cnt_s[16]     9.946        4.231
+rsl_inst.genblk2\.rlol1_cnt[13]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[13]      9.946        4.258
+rsl_inst.genblk2\.rlol1_cnt[14]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[14]      9.946        4.258
+rsl_inst.genblk2\.rlols0_cnt[13]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rlols0_cnt_s[13]     9.946        4.292
+========================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.809
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.136
+
+    Number of logic level(s):                14
+    Starting point:                          rsl_inst.genblk2\.rlol1_cnt[7] / Q
+    Ending point:                            rsl_inst.genblk2\.rlol1_cnt[18] / D
+    The start point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+
+Instance / Net                                         Pin      Pin               Arrival     No. of    
+Name                                      Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[7]            FD1P3DX      Q        Out     0.907     0.907       -         
+rlol1_cnt[7]                              Net          -        -       -         -           2         
+rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     Z        Out     0.606     1.513       -         
+rlol1_cnt_tc_1_10                         Net          -        -       -         -           1         
+rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     Z        Out     0.606     2.119       -         
+rlol1_cnt_tc_1_14                         Net          -        -       -         -           1         
+rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     Z        Out     0.768     2.887       -         
+rlol1_cnt_tc_1                            Net          -        -       -         -           6         
+rsl_inst.genblk2\.rlos_db_p1_RNIS0OP      ORCALUT4     A        In      0.000     2.887       -         
+rsl_inst.genblk2\.rlos_db_p1_RNIS0OP      ORCALUT4     Z        Out     0.837     3.724       -         
+rlol1_cnt                                 Net          -        -       -         -           20        
+rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.724       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.624       -         
+rlol1_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.624       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.685       -         
+rlol1_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.685       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.746       -         
+rlol1_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.746       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.807       -         
+rlol1_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.807       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.868       -         
+rlol1_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.868       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.929       -         
+rlol1_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.929       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.990       -         
+rlol1_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.990       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.051       -         
+rlol1_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.051       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.112       -         
+rlol1_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.112       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        S1       Out     0.698     5.809       -         
+rlol1_cnt_s[18]                           Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt[18]           FD1P3DX      D        In      0.000     5.809       -         
+========================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|tx_pclk_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                            Starting                                                                   Arrival          
+Instance                    Reference                             Type        Pin     Net              Time        Slack
+                            Clock                                                                                       
+------------------------------------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1       sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p1     1.098       5.789
+sll_inst.ppul_sync_p2       sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p2     1.098       5.789
+sll_inst.pcount_diff[0]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_0      0.985       6.147
+sll_inst.pcount[0]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[0]        0.955       6.178
+sll_inst.pcount_diff[1]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_1      0.955       6.239
+sll_inst.pcount_diff[2]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_2      0.955       6.239
+sll_inst.pcount[1]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[1]        0.907       6.287
+sll_inst.pcount[2]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[2]        0.907       6.287
+sll_inst.pcount_diff[3]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_3      0.955       6.300
+sll_inst.pcount_diff[4]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_4      0.955       6.300
+========================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                             Starting                                                                                  Required          
+Instance                     Reference                             Type        Pin     Net                             Time         Slack
+                             Clock                                                                                                       
+-----------------------------------------------------------------------------------------------------------------------------------------
+sll_inst.pcount[21]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[21]                    9.946        5.789
+sll_inst.pcount[19]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[19]                    9.946        5.850
+sll_inst.pcount[20]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[20]                    9.946        5.850
+sll_inst.pcount[17]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[17]                    9.946        5.911
+sll_inst.pcount[18]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[18]                    9.946        5.911
+sll_inst.pcount[15]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[15]                    9.946        5.972
+sll_inst.pcount[16]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[16]                    9.946        5.972
+sll_inst.pcount[13]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[13]                    9.946        6.033
+sll_inst.pcount[14]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[14]                    9.946        6.033
+sll_inst.pcount_diff[21]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3DX     D       un1_pcount_diff_1_s_21_0_S0     9.946        6.034
+=========================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      4.157
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 5.789
+
+    Number of logic level(s):                13
+    Starting point:                          sll_inst.ppul_sync_p1 / Q
+    Ending point:                            sll_inst.pcount[21] / D
+    The start point is clocked by            sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
+
+Instance / Net                             Pin      Pin               Arrival     No. of    
+Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1         FD1S3DX      Q        Out     1.098     1.098       -         
+ppul_sync_p1                  Net          -        -       -         -           25        
+sll_inst.pcount10_0_o3        ORCALUT4     A        In      0.000     1.098       -         
+sll_inst.pcount10_0_o3        ORCALUT4     Z        Out     0.851     1.950       -         
+N_8                           Net          -        -       -         -           25        
+sll_inst.pcount_cry_0[0]      CCU2C        A1       In      0.000     1.950       -         
+sll_inst.pcount_cry_0[0]      CCU2C        COUT     Out     0.900     2.850       -         
+pcount_cry[0]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[1]      CCU2C        CIN      In      0.000     2.850       -         
+sll_inst.pcount_cry_0[1]      CCU2C        COUT     Out     0.061     2.911       -         
+pcount_cry[2]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[3]      CCU2C        CIN      In      0.000     2.911       -         
+sll_inst.pcount_cry_0[3]      CCU2C        COUT     Out     0.061     2.972       -         
+pcount_cry[4]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[5]      CCU2C        CIN      In      0.000     2.972       -         
+sll_inst.pcount_cry_0[5]      CCU2C        COUT     Out     0.061     3.033       -         
+pcount_cry[6]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[7]      CCU2C        CIN      In      0.000     3.033       -         
+sll_inst.pcount_cry_0[7]      CCU2C        COUT     Out     0.061     3.094       -         
+pcount_cry[8]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[9]      CCU2C        CIN      In      0.000     3.094       -         
+sll_inst.pcount_cry_0[9]      CCU2C        COUT     Out     0.061     3.155       -         
+pcount_cry[10]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[11]     CCU2C        CIN      In      0.000     3.155       -         
+sll_inst.pcount_cry_0[11]     CCU2C        COUT     Out     0.061     3.216       -         
+pcount_cry[12]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[13]     CCU2C        CIN      In      0.000     3.216       -         
+sll_inst.pcount_cry_0[13]     CCU2C        COUT     Out     0.061     3.277       -         
+pcount_cry[14]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[15]     CCU2C        CIN      In      0.000     3.277       -         
+sll_inst.pcount_cry_0[15]     CCU2C        COUT     Out     0.061     3.338       -         
+pcount_cry[16]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[17]     CCU2C        CIN      In      0.000     3.338       -         
+sll_inst.pcount_cry_0[17]     CCU2C        COUT     Out     0.061     3.399       -         
+pcount_cry[18]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[19]     CCU2C        CIN      In      0.000     3.399       -         
+sll_inst.pcount_cry_0[19]     CCU2C        COUT     Out     0.061     3.460       -         
+pcount_cry[20]                Net          -        -       -         -           1         
+sll_inst.pcount_s_0[21]       CCU2C        CIN      In      0.000     3.460       -         
+sll_inst.pcount_s_0[21]       CCU2C        S0       Out     0.698     4.157       -         
+pcount_s[21]                  Net          -        -       -         -           1         
+sll_inst.pcount[21]           FD1S3DX      D        In      0.000     4.157       -         
+============================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                                 Arrival          
+Instance      Reference     Type     Pin              Net              Time        Slack
+              Clock                                                                     
+----------------------------------------------------------------------------------------
+DCU0_inst     System        DCUA     CH0_FFS_RLOL     rx_cdr_lol_s     0.000       8.810
+DCU0_inst     System        DCUA     CH0_FFS_RLOS     rx_los_low_s     0.000       8.810
+========================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                       Starting                                                            Required          
+Instance                                               Reference     Type        Pin     Net                               Time         Slack
+                                                       Clock                                                                                 
+---------------------------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     SP      un2_rdo_serdes_rst_dual_c_2_i     9.806        8.810
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     D       rxpr_appd_RNO[0]                  9.946        9.556
+rsl_inst.genblk2\.rlol_p1                              System        FD1S3DX     D       rx_cdr_lol_s                      9.946        9.946
+rsl_inst.genblk2\.rlos_p1                              System        FD1S3DX     D       rx_los_low_s                      9.946        9.946
+=============================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.194
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.806
+
+    - Propagation time:                      0.996
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 8.810
+
+    Number of logic level(s):                2
+    Starting point:                          DCU0_inst / CH0_FFS_RLOL
+    Ending point:                            rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+
+Instance / Net                                                            Pin              Pin               Arrival     No. of    
+Name                                                         Type         Name             Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------------------------------------------------------
+DCU0_inst                                                    DCUA         CH0_FFS_RLOL     Out     0.000     0.000       -         
+rx_cdr_lol_s                                                 Net          -                -       -         -           4         
+rsl_inst.un2_rdo_serdes_rst_dual_c_1_1                       ORCALUT4     A                In      0.000     0.000       -         
+rsl_inst.un2_rdo_serdes_rst_dual_c_1_1                       ORCALUT4     Z                Out     0.606     0.606       -         
+un2_rdo_serdes_rst_dual_c_1_1                                Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0]     ORCALUT4     B                In      0.000     0.606       -         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0]     ORCALUT4     Z                Out     0.390     0.996       -         
+un2_rdo_serdes_rst_dual_c_2_i                                Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]           FD1P3DX      SP               In      0.000     0.996       -         
+===================================================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 221 of 24288 (1%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+CCU2C:          113
+DCUA:           1
+FD1P3BX:        20
+FD1P3DX:        92
+FD1S3BX:        12
+FD1S3DX:        97
+GSR:            1
+INV:            3
+ORCALUT4:       153
+PFUMX:          2
+PUR:            1
+VHI:            6
+VLO:            6
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 153MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Fri May 10 11:59:02 2019
+
+###########################################################]

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srr.db b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srr.db
new file mode 100644 (file)
index 0000000..26e7e95
Binary files /dev/null and b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srr.db differ

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srs b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srs
new file mode 100644 (file)
index 0000000..930c248
Binary files /dev/null and b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srs differ

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.vhm b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.vhm
new file mode 100644 (file)
index 0000000..a16fecf
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.vhm
@@ -0,0 +1,6434 @@
+--
+-- Written by Synplicity
+-- Product Version "M-2017.03L-SP1-1"
+-- Program "Synplify Pro", Mapper "maplat, Build 1796R"
+-- Fri May 10 11:59:01 2019
+--
+
+--
+-- Written by Synplify Pro version Build 1796R
+-- Fri May 10 11:59:01 2019
+--
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library synplify;
+use synplify.components.all;
+library pmi;
+use pmi.pmi_components.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity sync_0s_0 is
+port(
+  ppul_sync :  in std_logic;
+  pdiff_sync :  out std_logic;
+  sli_rst :  in std_logic;
+  pll_refclki :  in std_logic);
+end sync_0s_0;
+
+architecture beh of sync_0s_0 is
+  signal DATA_P1 : std_logic ;
+  signal DATA_P2_QN_1 : std_logic ;
+  signal VCC : std_logic ;
+  signal DATA_P1_QN_1 : std_logic ;
+  signal GND : std_logic ;
+begin
+DATA_P2_REG_Z10: FD1S3DX port map (
+    D => DATA_P1,
+    CK => pll_refclki,
+    CD => sli_rst,
+    Q => pdiff_sync);
+DATA_P1_REG_Z12: FD1S3DX port map (
+    D => ppul_sync,
+    CK => pll_refclki,
+    CD => sli_rst,
+    Q => DATA_P1);
+VCC_0: VHI port map (
+    Z => VCC);
+II_GND: VLO port map (
+    Z => GND);
+end beh;
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library synplify;
+use synplify.components.all;
+library pmi;
+use pmi.pmi_components.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity sync_0s_6 is
+port(
+rtc_pul :  in std_logic;
+ppul_sync :  out std_logic;
+sli_rst :  in std_logic;
+tx_pclk :  in std_logic);
+end sync_0s_6;
+
+architecture beh of sync_0s_6 is
+signal DATA_P1 : std_logic ;
+signal DATA_P2_QN : std_logic ;
+signal VCC : std_logic ;
+signal DATA_P1_QN : std_logic ;
+signal GND : std_logic ;
+begin
+DATA_P2_REG_Z10: FD1S3DX port map (
+  D => DATA_P1,
+  CK => tx_pclk,
+  CD => sli_rst,
+  Q => ppul_sync);
+DATA_P1_REG_Z12: FD1S3DX port map (
+  D => rtc_pul,
+  CK => tx_pclk,
+  CD => sli_rst,
+  Q => DATA_P1);
+VCC_0: VHI port map (
+  Z => VCC);
+II_GND: VLO port map (
+  Z => GND);
+end beh;
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library synplify;
+use synplify.components.all;
+library pmi;
+use pmi.pmi_components.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity sync_0s is
+port(
+phb :  in std_logic;
+rhb_sync :  out std_logic;
+sli_rst :  in std_logic;
+pll_refclki :  in std_logic);
+end sync_0s;
+
+architecture beh of sync_0s is
+signal DATA_P1 : std_logic ;
+signal DATA_P2_QN_0 : std_logic ;
+signal VCC : std_logic ;
+signal DATA_P1_QN_0 : std_logic ;
+signal GND : std_logic ;
+begin
+DATA_P2_REG_Z10: FD1S3DX port map (
+D => DATA_P1,
+CK => pll_refclki,
+CD => sli_rst,
+Q => rhb_sync);
+DATA_P1_REG_Z12: FD1S3DX port map (
+D => phb,
+CK => pll_refclki,
+CD => sli_rst,
+Q => DATA_P1);
+VCC_0: VHI port map (
+Z => VCC);
+II_GND: VLO port map (
+Z => GND);
+end beh;
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library synplify;
+use synplify.components.all;
+library pmi;
+use pmi.pmi_components.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity sgmii_ecp5rsl_core_Z2_layer1 is
+port(
+rx_pcs_rst_c :  in std_logic;
+tx_pcs_rst_c :  in std_logic;
+serdes_rst_dual_c :  in std_logic;
+tx_serdes_rst_c :  in std_logic;
+rsl_rx_pcs_rst_c :  out std_logic;
+rsl_tx_pcs_rst_c :  out std_logic;
+rsl_tx_serdes_rst_c :  out std_logic;
+rsl_tx_rdy :  out std_logic;
+pll_lock_i :  in std_logic;
+pll_refclki :  in std_logic;
+rsl_rx_rdy :  out std_logic;
+rsl_rst :  in std_logic;
+rxrefclk :  in std_logic;
+rsl_disable :  in std_logic;
+rx_serdes_rst_c :  in std_logic;
+rst_dual_c :  in std_logic;
+rx_cdr_lol_s :  in std_logic;
+rx_los_low_s :  in std_logic;
+rsl_rx_serdes_rst_c :  out std_logic;
+rsl_serdes_rst_dual_c :  out std_logic);
+end sgmii_ecp5rsl_core_Z2_layer1;
+
+architecture beh of sgmii_ecp5rsl_core_Z2_layer1 is
+signal RXS_CNT : std_logic_vector(1 downto 0);
+signal RXS_CNT_3 : std_logic_vector(1 downto 0);
+signal RXPR_APPD_RNO : std_logic_vector(0 to 0);
+signal PLOL0_CNT : std_logic_vector(2 downto 0);
+signal PLOL0_CNT_3 : std_logic_vector(2 downto 0);
+signal RXSR_APPD : std_logic_vector(0 to 0);
+signal RXS_CNT_QN : std_logic_vector(1 downto 0);
+signal RLOS_DB_CNT : std_logic_vector(3 downto 0);
+signal RLOS_DB_CNT_QN : std_logic_vector(3 downto 0);
+signal RLOLS0_CNT_S : std_logic_vector(17 downto 0);
+signal RLOLS0_CNT : std_logic_vector(17 downto 0);
+signal RLOLS0_CNT_QN : std_logic_vector(17 downto 0);
+signal RLOL_DB_CNT : std_logic_vector(3 downto 0);
+signal RLOL_DB_CNT_QN : std_logic_vector(3 downto 0);
+signal RLOL1_CNT_S : std_logic_vector(18 downto 0);
+signal RLOL1_CNT : std_logic_vector(18 downto 0);
+signal RLOL1_CNT_QN : std_logic_vector(18 downto 0);
+signal RXR_WT_CNT_S : std_logic_vector(11 downto 0);
+signal RXR_WT_CNT : std_logic_vector(11 downto 0);
+signal RXR_WT_CNT_QN : std_logic_vector(11 downto 0);
+signal RXSR_APPD_QN : std_logic_vector(0 to 0);
+signal RXPR_APPD : std_logic_vector(0 to 0);
+signal RXPR_APPD_QN : std_logic_vector(0 to 0);
+signal TXS_CNT : std_logic_vector(1 downto 0);
+signal TXS_CNT_QN : std_logic_vector(1 downto 0);
+signal TXS_CNT_RNO : std_logic_vector(1 to 1);
+signal TXP_CNT : std_logic_vector(1 downto 0);
+signal TXP_CNT_QN : std_logic_vector(1 downto 0);
+signal TXP_CNT_RNO : std_logic_vector(1 to 1);
+signal PLOL_CNT_S : std_logic_vector(19 downto 0);
+signal PLOL_CNT : std_logic_vector(19 downto 0);
+signal PLOL_CNT_QN : std_logic_vector(19 downto 0);
+signal PLOL0_CNT_QN : std_logic_vector(2 downto 0);
+signal TXR_WT_CNT_S : std_logic_vector(11 downto 0);
+signal TXR_WT_CNT : std_logic_vector(11 downto 0);
+signal TXR_WT_CNT_QN : std_logic_vector(11 downto 0);
+signal TXPR_APPD : std_logic_vector(0 to 0);
+signal TXPR_APPD_QN : std_logic_vector(0 to 0);
+signal UN1_RLOL_DB_CNT_ZERO : std_logic_vector(0 to 0);
+signal UN1_RLOS_DB_CNT_ZERO : std_logic_vector(0 to 0);
+signal UN1_RLOL_DB_CNT_ZERO_BM : std_logic_vector(0 to 0);
+signal UN1_RLOL_DB_CNT_ZERO_AM : std_logic_vector(0 to 0);
+signal UN1_RLOS_DB_CNT_ZERO_BM : std_logic_vector(0 to 0);
+signal UN1_RLOS_DB_CNT_ZERO_AM : std_logic_vector(0 to 0);
+signal RLOL1_CNT_CRY : std_logic_vector(16 downto 0);
+signal RLOL1_CNT_CRY_0_S0 : std_logic_vector(0 to 0);
+signal RLOL1_CNT_CRY_0_COUT : std_logic_vector(17 to 17);
+signal RLOLS0_CNT_CRY : std_logic_vector(16 downto 0);
+signal RLOLS0_CNT_CRY_0_S0 : std_logic_vector(0 to 0);
+signal RLOLS0_CNT_S_0_COUT : std_logic_vector(17 to 17);
+signal RLOLS0_CNT_S_0_S1 : std_logic_vector(17 to 17);
+signal TXR_WT_CNT_CRY : std_logic_vector(10 downto 0);
+signal TXR_WT_CNT_CRY_0_S0 : std_logic_vector(0 to 0);
+signal TXR_WT_CNT_S_0_COUT : std_logic_vector(11 to 11);
+signal TXR_WT_CNT_S_0_S1 : std_logic_vector(11 to 11);
+signal RXR_WT_CNT_CRY : std_logic_vector(10 downto 0);
+signal RXR_WT_CNT_CRY_0_S0 : std_logic_vector(0 to 0);
+signal RXR_WT_CNT_S_0_COUT : std_logic_vector(11 to 11);
+signal RXR_WT_CNT_S_0_S1 : std_logic_vector(11 to 11);
+signal PLOL_CNT_CRY : std_logic_vector(18 downto 0);
+signal PLOL_CNT_CRY_0_S0 : std_logic_vector(0 to 0);
+signal PLOL_CNT_S_0_COUT : std_logic_vector(19 to 19);
+signal PLOL_CNT_S_0_S1 : std_logic_vector(19 to 19);
+signal RXS_RST : std_logic ;
+signal VCC : std_logic ;
+signal RSL_SERDES_RST_DUAL_C_10 : std_logic ;
+signal RSL_RX_SERDES_RST_C_9 : std_logic ;
+signal RLOS_DB_P1 : std_logic ;
+signal RLOS_DB : std_logic ;
+signal RXP_RST25 : std_logic ;
+signal RLOL_DB : std_logic ;
+signal UN1_RUI_RST_DUAL_C_1_1 : std_logic ;
+signal PLOL0_CNT9 : std_logic ;
+signal WAITA_PLOL0 : std_logic ;
+signal RX_ANY_RST : std_logic ;
+signal UN3_RX_ALL_WELL_2 : std_logic ;
+signal UN17_RXR_WT_TC : std_logic ;
+signal RX_ALL_WELL : std_logic ;
+signal UN3_RX_ALL_WELL_1 : std_logic ;
+signal RXR_WT_CNT9 : std_logic ;
+signal UN1_RUI_RST_DUAL_C_1_I : std_logic ;
+signal RLOL1_CNT_TC_1 : std_logic ;
+signal \RLOL1_CNT_\ : std_logic ;
+signal RXR_WT_EN : std_logic ;
+signal RXR_WT_CNTE : std_logic ;
+signal UN18_TXR_WT_TC : std_logic ;
+signal TX_ANY_RST : std_logic ;
+signal PLL_LOL_P2 : std_logic ;
+signal UN2_PLOL_FEDGE_5_I : std_logic ;
+signal N_2160_0 : std_logic ;
+signal WAITA_RLOLS06 : std_logic ;
+signal UN1_RLOLS0_CNT_TC : std_logic ;
+signal WAITA_RLOLS0 : std_logic ;
+signal WAITA_RLOLS0_QN : std_logic ;
+signal WAIT_CALIB_RNO : std_logic ;
+signal UN1_RLOS_FEDGE_1 : std_logic ;
+signal WAIT_CALIB : std_logic ;
+signal WAIT_CALIB_QN : std_logic ;
+signal RXS_RST6 : std_logic ;
+signal UN1_RXS_CNT_TC : std_logic ;
+signal RXS_RST_QN : std_logic ;
+signal UN2_RLOS_REDGE_1_I : std_logic ;
+signal RXP_RST2 : std_logic ;
+signal RXP_RST2_QN : std_logic ;
+signal RLOS_P1 : std_logic ;
+signal RLOS_P2 : std_logic ;
+signal RLOS_P2_QN : std_logic ;
+signal RLOS_P1_QN : std_logic ;
+signal RLOS_DB_P1_QN : std_logic ;
+signal RLOS_DB_CNT_AXB_0 : std_logic ;
+signal RLOS_DB_CNT_CRY_1_0_S0 : std_logic ;
+signal RLOS_DB_CNT_CRY_1_0_S1 : std_logic ;
+signal RLOS_DB_CNT_S_3_0_S0 : std_logic ;
+signal UN1_RLOS_DB_CNT_MAX : std_logic ;
+signal RLOS_DB_QN : std_logic ;
+signal RLOLS0_CNTE : std_logic ;
+signal RLOL_P1 : std_logic ;
+signal RLOL_P2 : std_logic ;
+signal RLOL_P2_QN : std_logic ;
+signal RLOL_P1_QN : std_logic ;
+signal RLOL_DB_P1 : std_logic ;
+signal RLOL_DB_P1_QN : std_logic ;
+signal RLOL_DB_CNT_AXB_0 : std_logic ;
+signal RLOL_DB_CNT_CRY_1_0_S0 : std_logic ;
+signal RLOL_DB_CNT_CRY_1_0_S1 : std_logic ;
+signal RLOL_DB_CNT_S_3_0_S0 : std_logic ;
+signal UN1_RLOL_DB_CNT_MAX : std_logic ;
+signal RLOL_DB_QN : std_logic ;
+signal RLOL1_CNTE : std_logic ;
+signal RXSDR_APPD_2 : std_logic ;
+signal RXSDR_APPD : std_logic ;
+signal RXSDR_APPD_QN : std_logic ;
+signal UN1_DUAL_OR_RSERD_RST_2_I : std_logic ;
+signal RXR_WT_EN_QN : std_logic ;
+signal RXDPR_APPD : std_logic ;
+signal RXDPR_APPD_QN : std_logic ;
+signal RSL_RX_RDY_8 : std_logic ;
+signal RUO_RX_RDYR_QN : std_logic ;
+signal UN2_RDO_SERDES_RST_DUAL_C_2_I : std_logic ;
+signal PLOL_FEDGE : std_logic ;
+signal UN1_PLOL0_CNT_TC_1_I : std_logic ;
+signal WAITA_PLOL0_QN : std_logic ;
+signal UN1_PLOL_CNT_TC : std_logic ;
+signal UN2_PLOL_CNT_TC : std_logic ;
+signal TXS_RST : std_logic ;
+signal TXS_RST_QN : std_logic ;
+signal N_10_I : std_logic ;
+signal UN9_PLOL0_CNT_TC : std_logic ;
+signal UN1_PLOL0_CNT_TC_1 : std_logic ;
+signal TXP_RST : std_logic ;
+signal TXP_RST_QN : std_logic ;
+signal N_11_I : std_logic ;
+signal PLL_LOL_P3 : std_logic ;
+signal PLL_LOL_P3_QN : std_logic ;
+signal PLL_LOL_P1 : std_logic ;
+signal PLL_LOL_P2_QN : std_logic ;
+signal PLL_LOL_P1_QN : std_logic ;
+signal TXSR_APPD_2 : std_logic ;
+signal TXSR_APPD : std_logic ;
+signal TXSR_APPD_QN : std_logic ;
+signal UN1_DUAL_OR_SERD_RST_1_1 : std_logic ;
+signal UN1_DUAL_OR_SERD_RST_1_I : std_logic ;
+signal TXR_WT_EN : std_logic ;
+signal TXR_WT_EN_QN : std_logic ;
+signal TXR_WT_CNTE : std_logic ;
+signal UN2_PLOL_FEDGE_2 : std_logic ;
+signal UN2_PLOL_FEDGE_3_I : std_logic ;
+signal TXDPR_APPD : std_logic ;
+signal TXDPR_APPD_QN : std_logic ;
+signal UN2_PLOL_FEDGE_5_1 : std_logic ;
+signal RSL_TX_RDY_7 : std_logic ;
+signal RUO_TX_RDYR_QN : std_logic ;
+signal UN2_PLOL_FEDGE_8_I : std_logic ;
+signal RLOLS0_CNT_TC_1 : std_logic ;
+signal RLOS_REDGE : std_logic ;
+signal RLOLS0_CNT11_0 : std_logic ;
+signal RSL_TX_SERDES_RST_C_6 : std_logic ;
+signal \PLOL_CNT_\ : std_logic ;
+signal \RLOLS0_CNT_\ : std_logic ;
+signal UN8_RXS_CNT_TC : std_logic ;
+signal UN1_TXSR_APPD : std_logic ;
+signal UN1_DUAL_OR_RSERD_RST_2_0 : std_logic ;
+signal UN1_RXSDR_OR_SR_APPD : std_logic ;
+signal UN2_RDO_SERDES_RST_DUAL_C_1_1 : std_logic ;
+signal RLOLS0_CNT_TC_1_10 : std_logic ;
+signal RLOLS0_CNT_TC_1_11 : std_logic ;
+signal RLOLS0_CNT_TC_1_12 : std_logic ;
+signal RLOLS0_CNT_TC_1_13 : std_logic ;
+signal RLOL1_CNT_TC_1_11 : std_logic ;
+signal RLOL1_CNT_TC_1_12 : std_logic ;
+signal RLOL1_CNT_TC_1_13 : std_logic ;
+signal RLOL1_CNT_TC_1_14 : std_logic ;
+signal UN1_PLOL_CNT_TC_11 : std_logic ;
+signal UN1_PLOL_CNT_TC_12 : std_logic ;
+signal UN1_PLOL_CNT_TC_13 : std_logic ;
+signal UN1_PLOL_CNT_TC_14 : std_logic ;
+signal CO0_2 : std_logic ;
+signal TXSR_APPD_4 : std_logic ;
+signal RSL_TX_PCS_RST_C_5 : std_logic ;
+signal UN17_RXR_WT_TC_6 : std_logic ;
+signal UN17_RXR_WT_TC_7 : std_logic ;
+signal UN17_RXR_WT_TC_8 : std_logic ;
+signal RSL_RX_PCS_RST_C_4 : std_logic ;
+signal UN18_TXR_WT_TC_6 : std_logic ;
+signal UN18_TXR_WT_TC_7 : std_logic ;
+signal UN18_TXR_WT_TC_8 : std_logic ;
+signal RXSDR_APPD_4 : std_logic ;
+signal RLOLS0_CNT_TC_1_9 : std_logic ;
+signal UN1_PLOL_CNT_TC_10 : std_logic ;
+signal RLOL1_CNT_TC_1_10 : std_logic ;
+signal \TXR_WT_CNT_\ : std_logic ;
+signal RLOS_DB_CNT_CRY_0 : std_logic ;
+signal RLOS_DB_CNT_CRY_0_0_S0 : std_logic ;
+signal RLOS_DB_CNT_CRY_0_0_S1 : std_logic ;
+signal RLOS_DB_CNT_CRY_2 : std_logic ;
+signal RLOS_DB_CNT_S_3_0_COUT : std_logic ;
+signal RLOS_DB_CNT_S_3_0_S1 : std_logic ;
+signal RLOL_DB_CNT_CRY_0 : std_logic ;
+signal RLOL_DB_CNT_CRY_0_0_S0 : std_logic ;
+signal RLOL_DB_CNT_CRY_0_0_S1 : std_logic ;
+signal RLOL_DB_CNT_CRY_2 : std_logic ;
+signal RLOL_DB_CNT_S_3_0_COUT : std_logic ;
+signal RLOL_DB_CNT_S_3_0_S1 : std_logic ;
+signal GND : std_logic ;
+signal N_1 : std_logic ;
+signal N_2 : std_logic ;
+signal N_3 : std_logic ;
+signal N_4 : std_logic ;
+signal N_5 : std_logic ;
+signal N_6 : std_logic ;
+signal N_7 : std_logic ;
+begin
+\GENBLK2.RXS_CNT_RNO[0]\: LUT4 
+generic map(
+  init => X"2626"
+)
+port map (
+A => RXS_RST,
+B => RXS_CNT(0),
+C => RXS_CNT(1),
+D => VCC,
+Z => RXS_CNT_3(0));
+\GENBLK2.GENBLK3.LFOR[0].RXPR_APPD_RNO[0]\: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RSL_SERDES_RST_DUAL_C_10,
+B => RSL_RX_SERDES_RST_C_9,
+C => rx_los_low_s,
+D => rx_cdr_lol_s,
+Z => RXPR_APPD_RNO(0));
+\GENBLK2.RXP_RST2_RNO\: LUT4 
+generic map(
+  init => X"EFEE"
+)
+port map (
+A => RSL_SERDES_RST_DUAL_C_10,
+B => RSL_RX_SERDES_RST_C_9,
+C => RLOS_DB_P1,
+D => RLOS_DB,
+Z => RXP_RST25);
+\GENBLK2.GENBLK3.RXDPR_APPD_RNO\: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RSL_SERDES_RST_DUAL_C_10,
+B => RSL_RX_SERDES_RST_C_9,
+C => RLOS_DB,
+D => RLOL_DB,
+Z => UN1_RUI_RST_DUAL_C_1_1);
+\GENBLK1.PLOL0_CNT_RNO[1]\: LUT4 
+generic map(
+  init => X"1222"
+)
+port map (
+A => PLOL0_CNT(1),
+B => PLOL0_CNT9,
+C => WAITA_PLOL0,
+D => PLOL0_CNT(0),
+Z => PLOL0_CNT_3(1));
+\GENBLK2.GENBLK3.RUO_RX_RDYR_RNO\: LUT4 
+generic map(
+  init => X"0101"
+)
+port map (
+A => RX_ANY_RST,
+B => RLOS_DB,
+C => RLOL_DB,
+D => VCC,
+Z => UN3_RX_ALL_WELL_2);
+\GENBLK2.GENBLK3.RXR_WT_EN_RNO\: LUT4 
+generic map(
+  init => X"0100"
+)
+port map (
+A => UN17_RXR_WT_TC,
+B => RSL_SERDES_RST_DUAL_C_10,
+C => RSL_RX_SERDES_RST_C_9,
+D => RX_ALL_WELL,
+Z => UN3_RX_ALL_WELL_1);
+RX_ANY_RST_RNIFD021: LUT4 
+generic map(
+  init => X"FFFE"
+)
+port map (
+A => RX_ANY_RST,
+B => UN17_RXR_WT_TC,
+C => RLOS_DB,
+D => RLOL_DB,
+Z => RXR_WT_CNT9);
+\GENBLK2.GENBLK3.RXDPR_APPD_RNO_0\: LUT4 
+generic map(
+  init => X"FEFF"
+)
+port map (
+A => rst_dual_c,
+B => RSL_SERDES_RST_DUAL_C_10,
+C => RSL_RX_SERDES_RST_C_9,
+D => RX_ALL_WELL,
+Z => UN1_RUI_RST_DUAL_C_1_I);
+\GENBLK2.RLOS_DB_P1_RNIS0OP\: LUT4 
+generic map(
+  init => X"1011"
+)
+port map (
+A => RLOL1_CNT_TC_1,
+B => RXS_RST,
+C => RLOS_DB_P1,
+D => RLOS_DB,
+Z => \RLOL1_CNT_\);
+\GENBLK2.GENBLK3.RXR_WT_EN_RNIQF0H1\: LUT4 
+generic map(
+  init => X"FFEF"
+)
+port map (
+A => RXR_WT_EN,
+B => RX_ANY_RST,
+C => RX_ALL_WELL,
+D => UN17_RXR_WT_TC,
+Z => RXR_WT_CNTE);
+\GENBLK1.GENBLK2.RUO_TX_RDYR_RNO\: LUT4 
+generic map(
+  init => X"FEFE"
+)
+port map (
+A => UN18_TXR_WT_TC,
+B => TX_ANY_RST,
+C => PLL_LOL_P2,
+D => VCC,
+Z => UN2_PLOL_FEDGE_5_I);
+\GENBLK2.GENBLK3.LFOR[0].RXSR_APPD_RNO[0]\: LUT4 
+generic map(
+  init => X"EEFE"
+)
+port map (
+A => RXSR_APPD(0),
+B => rx_serdes_rst_c,
+C => RXS_RST,
+D => rsl_disable,
+Z => N_2160_0);
+\GENBLK2.WAITA_RLOLS0_REG_Z616\: FD1P3DX port map (
+D => WAITA_RLOLS06,
+SP => UN1_RLOLS0_CNT_TC,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => WAITA_RLOLS0);
+\GENBLK2.WAIT_CALIB_REG_Z618\: FD1P3BX port map (
+D => WAIT_CALIB_RNO,
+SP => UN1_RLOS_FEDGE_1,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => WAIT_CALIB);
+\GENBLK2.RXS_RST_REG_Z620\: FD1P3DX port map (
+D => RXS_RST6,
+SP => UN1_RXS_CNT_TC,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXS_RST);
+\GENBLK2.RXS_CNT[0]_REG_Z622\: FD1S3DX port map (
+D => RXS_CNT_3(0),
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXS_CNT(0));
+\GENBLK2.RXS_CNT[1]_REG_Z624\: FD1S3DX port map (
+D => RXS_CNT_3(1),
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXS_CNT(1));
+\GENBLK2.RXP_RST2_REG_Z626\: FD1P3BX port map (
+D => RXP_RST25,
+SP => UN2_RLOS_REDGE_1_I,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RXP_RST2);
+\GENBLK2.RLOS_P2_REG_Z628\: FD1S3DX port map (
+D => RLOS_P1,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOS_P2);
+\GENBLK2.RLOS_P1_REG_Z630\: FD1S3DX port map (
+D => rx_los_low_s,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOS_P1);
+\GENBLK2.RLOS_DB_P1_REG_Z632\: FD1S3BX port map (
+D => RLOS_DB,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOS_DB_P1);
+\GENBLK2.RLOS_DB_CNT[0]_REG_Z634\: FD1S3BX port map (
+D => RLOS_DB_CNT_AXB_0,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOS_DB_CNT(0));
+\GENBLK2.RLOS_DB_CNT[1]_REG_Z636\: FD1S3BX port map (
+D => RLOS_DB_CNT_CRY_1_0_S0,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOS_DB_CNT(1));
+\GENBLK2.RLOS_DB_CNT[2]_REG_Z638\: FD1S3BX port map (
+D => RLOS_DB_CNT_CRY_1_0_S1,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOS_DB_CNT(2));
+\GENBLK2.RLOS_DB_CNT[3]_REG_Z640\: FD1S3BX port map (
+D => RLOS_DB_CNT_S_3_0_S0,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOS_DB_CNT(3));
+\GENBLK2.RLOS_DB_REG_Z642\: FD1P3BX port map (
+D => RLOS_DB_CNT(1),
+SP => UN1_RLOS_DB_CNT_MAX,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOS_DB);
+\GENBLK2.RLOLS0_CNT[0]_REG_Z644\: FD1P3DX port map (
+D => RLOLS0_CNT_S(0),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(0));
+\GENBLK2.RLOLS0_CNT[1]_REG_Z646\: FD1P3DX port map (
+D => RLOLS0_CNT_S(1),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(1));
+\GENBLK2.RLOLS0_CNT[2]_REG_Z648\: FD1P3DX port map (
+D => RLOLS0_CNT_S(2),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(2));
+\GENBLK2.RLOLS0_CNT[3]_REG_Z650\: FD1P3DX port map (
+D => RLOLS0_CNT_S(3),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(3));
+\GENBLK2.RLOLS0_CNT[4]_REG_Z652\: FD1P3DX port map (
+D => RLOLS0_CNT_S(4),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(4));
+\GENBLK2.RLOLS0_CNT[5]_REG_Z654\: FD1P3DX port map (
+D => RLOLS0_CNT_S(5),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(5));
+\GENBLK2.RLOLS0_CNT[6]_REG_Z656\: FD1P3DX port map (
+D => RLOLS0_CNT_S(6),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(6));
+\GENBLK2.RLOLS0_CNT[7]_REG_Z658\: FD1P3DX port map (
+D => RLOLS0_CNT_S(7),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(7));
+\GENBLK2.RLOLS0_CNT[8]_REG_Z660\: FD1P3DX port map (
+D => RLOLS0_CNT_S(8),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(8));
+\GENBLK2.RLOLS0_CNT[9]_REG_Z662\: FD1P3DX port map (
+D => RLOLS0_CNT_S(9),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(9));
+\GENBLK2.RLOLS0_CNT[10]_REG_Z664\: FD1P3DX port map (
+D => RLOLS0_CNT_S(10),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(10));
+\GENBLK2.RLOLS0_CNT[11]_REG_Z666\: FD1P3DX port map (
+D => RLOLS0_CNT_S(11),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(11));
+\GENBLK2.RLOLS0_CNT[12]_REG_Z668\: FD1P3DX port map (
+D => RLOLS0_CNT_S(12),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(12));
+\GENBLK2.RLOLS0_CNT[13]_REG_Z670\: FD1P3DX port map (
+D => RLOLS0_CNT_S(13),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(13));
+\GENBLK2.RLOLS0_CNT[14]_REG_Z672\: FD1P3DX port map (
+D => RLOLS0_CNT_S(14),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(14));
+\GENBLK2.RLOLS0_CNT[15]_REG_Z674\: FD1P3DX port map (
+D => RLOLS0_CNT_S(15),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(15));
+\GENBLK2.RLOLS0_CNT[16]_REG_Z676\: FD1P3DX port map (
+D => RLOLS0_CNT_S(16),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(16));
+\GENBLK2.RLOLS0_CNT[17]_REG_Z678\: FD1P3DX port map (
+D => RLOLS0_CNT_S(17),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(17));
+\GENBLK2.RLOL_P2_REG_Z680\: FD1S3DX port map (
+D => RLOL_P1,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL_P2);
+\GENBLK2.RLOL_P1_REG_Z682\: FD1S3DX port map (
+D => rx_cdr_lol_s,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL_P1);
+\GENBLK2.RLOL_DB_P1_REG_Z684\: FD1S3BX port map (
+D => RLOL_DB,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOL_DB_P1);
+\GENBLK2.RLOL_DB_CNT[0]_REG_Z686\: FD1S3BX port map (
+D => RLOL_DB_CNT_AXB_0,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOL_DB_CNT(0));
+\GENBLK2.RLOL_DB_CNT[1]_REG_Z688\: FD1S3BX port map (
+D => RLOL_DB_CNT_CRY_1_0_S0,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOL_DB_CNT(1));
+\GENBLK2.RLOL_DB_CNT[2]_REG_Z690\: FD1S3BX port map (
+D => RLOL_DB_CNT_CRY_1_0_S1,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOL_DB_CNT(2));
+\GENBLK2.RLOL_DB_CNT[3]_REG_Z692\: FD1S3BX port map (
+D => RLOL_DB_CNT_S_3_0_S0,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOL_DB_CNT(3));
+\GENBLK2.RLOL_DB_REG_Z694\: FD1P3BX port map (
+D => RLOL_DB_CNT(1),
+SP => UN1_RLOL_DB_CNT_MAX,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOL_DB);
+\GENBLK2.RLOL1_CNT[0]_REG_Z696\: FD1P3DX port map (
+D => RLOL1_CNT_S(0),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(0));
+\GENBLK2.RLOL1_CNT[1]_REG_Z698\: FD1P3DX port map (
+D => RLOL1_CNT_S(1),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(1));
+\GENBLK2.RLOL1_CNT[2]_REG_Z700\: FD1P3DX port map (
+D => RLOL1_CNT_S(2),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(2));
+\GENBLK2.RLOL1_CNT[3]_REG_Z702\: FD1P3DX port map (
+D => RLOL1_CNT_S(3),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(3));
+\GENBLK2.RLOL1_CNT[4]_REG_Z704\: FD1P3DX port map (
+D => RLOL1_CNT_S(4),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(4));
+\GENBLK2.RLOL1_CNT[5]_REG_Z706\: FD1P3DX port map (
+D => RLOL1_CNT_S(5),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(5));
+\GENBLK2.RLOL1_CNT[6]_REG_Z708\: FD1P3DX port map (
+D => RLOL1_CNT_S(6),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(6));
+\GENBLK2.RLOL1_CNT[7]_REG_Z710\: FD1P3DX port map (
+D => RLOL1_CNT_S(7),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(7));
+\GENBLK2.RLOL1_CNT[8]_REG_Z712\: FD1P3DX port map (
+D => RLOL1_CNT_S(8),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(8));
+\GENBLK2.RLOL1_CNT[9]_REG_Z714\: FD1P3DX port map (
+D => RLOL1_CNT_S(9),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(9));
+\GENBLK2.RLOL1_CNT[10]_REG_Z716\: FD1P3DX port map (
+D => RLOL1_CNT_S(10),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(10));
+\GENBLK2.RLOL1_CNT[11]_REG_Z718\: FD1P3DX port map (
+D => RLOL1_CNT_S(11),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(11));
+\GENBLK2.RLOL1_CNT[12]_REG_Z720\: FD1P3DX port map (
+D => RLOL1_CNT_S(12),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(12));
+\GENBLK2.RLOL1_CNT[13]_REG_Z722\: FD1P3DX port map (
+D => RLOL1_CNT_S(13),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(13));
+\GENBLK2.RLOL1_CNT[14]_REG_Z724\: FD1P3DX port map (
+D => RLOL1_CNT_S(14),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(14));
+\GENBLK2.RLOL1_CNT[15]_REG_Z726\: FD1P3DX port map (
+D => RLOL1_CNT_S(15),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(15));
+\GENBLK2.RLOL1_CNT[16]_REG_Z728\: FD1P3DX port map (
+D => RLOL1_CNT_S(16),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(16));
+\GENBLK2.RLOL1_CNT[17]_REG_Z730\: FD1P3DX port map (
+D => RLOL1_CNT_S(17),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(17));
+\GENBLK2.RLOL1_CNT[18]_REG_Z732\: FD1P3DX port map (
+D => RLOL1_CNT_S(18),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(18));
+\GENBLK2.GENBLK3.RXSDR_APPD_REG_Z734\: FD1S3BX port map (
+D => RXSDR_APPD_2,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RXSDR_APPD);
+\GENBLK2.GENBLK3.RXR_WT_EN_REG_Z736\: FD1P3DX port map (
+D => UN3_RX_ALL_WELL_1,
+SP => UN1_DUAL_OR_RSERD_RST_2_I,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_EN);
+\GENBLK2.GENBLK3.RXR_WT_CNT[0]_REG_Z738\: FD1P3DX port map (
+D => RXR_WT_CNT_S(0),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(0));
+\GENBLK2.GENBLK3.RXR_WT_CNT[1]_REG_Z740\: FD1P3DX port map (
+D => RXR_WT_CNT_S(1),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(1));
+\GENBLK2.GENBLK3.RXR_WT_CNT[2]_REG_Z742\: FD1P3DX port map (
+D => RXR_WT_CNT_S(2),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(2));
+\GENBLK2.GENBLK3.RXR_WT_CNT[3]_REG_Z744\: FD1P3DX port map (
+D => RXR_WT_CNT_S(3),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(3));
+\GENBLK2.GENBLK3.RXR_WT_CNT[4]_REG_Z746\: FD1P3DX port map (
+D => RXR_WT_CNT_S(4),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(4));
+\GENBLK2.GENBLK3.RXR_WT_CNT[5]_REG_Z748\: FD1P3DX port map (
+D => RXR_WT_CNT_S(5),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(5));
+\GENBLK2.GENBLK3.RXR_WT_CNT[6]_REG_Z750\: FD1P3DX port map (
+D => RXR_WT_CNT_S(6),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(6));
+\GENBLK2.GENBLK3.RXR_WT_CNT[7]_REG_Z752\: FD1P3DX port map (
+D => RXR_WT_CNT_S(7),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(7));
+\GENBLK2.GENBLK3.RXR_WT_CNT[8]_REG_Z754\: FD1P3DX port map (
+D => RXR_WT_CNT_S(8),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(8));
+\GENBLK2.GENBLK3.RXR_WT_CNT[9]_REG_Z756\: FD1P3DX port map (
+D => RXR_WT_CNT_S(9),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(9));
+\GENBLK2.GENBLK3.RXR_WT_CNT[10]_REG_Z758\: FD1P3DX port map (
+D => RXR_WT_CNT_S(10),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(10));
+\GENBLK2.GENBLK3.RXR_WT_CNT[11]_REG_Z760\: FD1P3DX port map (
+D => RXR_WT_CNT_S(11),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(11));
+\GENBLK2.GENBLK3.RXDPR_APPD_REG_Z762\: FD1P3DX port map (
+D => UN1_RUI_RST_DUAL_C_1_1,
+SP => UN1_RUI_RST_DUAL_C_1_I,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXDPR_APPD);
+\GENBLK2.GENBLK3.RUO_RX_RDYR_REG_Z764\: FD1P3DX port map (
+D => UN3_RX_ALL_WELL_2,
+SP => RXR_WT_CNT9,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RSL_RX_RDY_8);
+\GENBLK2.GENBLK3.LFOR[0].RXSR_APPD[0]_REG_Z766\: FD1S3DX port map (
+D => N_2160_0,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXSR_APPD(0));
+\GENBLK2.GENBLK3.LFOR[0].RXPR_APPD[0]_REG_Z768\: FD1P3DX port map (
+D => RXPR_APPD_RNO(0),
+SP => UN2_RDO_SERDES_RST_DUAL_C_2_I,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXPR_APPD(0));
+\GENBLK1.WAITA_PLOL0_REG_Z770\: FD1P3DX port map (
+D => PLOL_FEDGE,
+SP => UN1_PLOL0_CNT_TC_1_I,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => WAITA_PLOL0);
+\GENBLK1.TXS_RST_REG_Z772\: FD1P3DX port map (
+D => UN1_PLOL_CNT_TC,
+SP => UN2_PLOL_CNT_TC,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXS_RST);
+\GENBLK1.TXS_CNT[0]_REG_Z774\: FD1S3DX port map (
+D => N_10_I,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXS_CNT(0));
+\GENBLK1.TXS_CNT[1]_REG_Z776\: FD1S3DX port map (
+D => TXS_CNT_RNO(1),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXS_CNT(1));
+\GENBLK1.TXP_RST_REG_Z778\: FD1P3DX port map (
+D => UN9_PLOL0_CNT_TC,
+SP => UN1_PLOL0_CNT_TC_1,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXP_RST);
+\GENBLK1.TXP_CNT[0]_REG_Z780\: FD1S3DX port map (
+D => N_11_I,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXP_CNT(0));
+\GENBLK1.TXP_CNT[1]_REG_Z782\: FD1S3DX port map (
+D => TXP_CNT_RNO(1),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXP_CNT(1));
+\GENBLK1.PLOL_CNT[0]_REG_Z784\: FD1S3DX port map (
+D => PLOL_CNT_S(0),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(0));
+\GENBLK1.PLOL_CNT[1]_REG_Z786\: FD1S3DX port map (
+D => PLOL_CNT_S(1),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(1));
+\GENBLK1.PLOL_CNT[2]_REG_Z788\: FD1S3DX port map (
+D => PLOL_CNT_S(2),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(2));
+\GENBLK1.PLOL_CNT[3]_REG_Z790\: FD1S3DX port map (
+D => PLOL_CNT_S(3),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(3));
+\GENBLK1.PLOL_CNT[4]_REG_Z792\: FD1S3DX port map (
+D => PLOL_CNT_S(4),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(4));
+\GENBLK1.PLOL_CNT[5]_REG_Z794\: FD1S3DX port map (
+D => PLOL_CNT_S(5),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(5));
+\GENBLK1.PLOL_CNT[6]_REG_Z796\: FD1S3DX port map (
+D => PLOL_CNT_S(6),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(6));
+\GENBLK1.PLOL_CNT[7]_REG_Z798\: FD1S3DX port map (
+D => PLOL_CNT_S(7),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(7));
+\GENBLK1.PLOL_CNT[8]_REG_Z800\: FD1S3DX port map (
+D => PLOL_CNT_S(8),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(8));
+\GENBLK1.PLOL_CNT[9]_REG_Z802\: FD1S3DX port map (
+D => PLOL_CNT_S(9),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(9));
+\GENBLK1.PLOL_CNT[10]_REG_Z804\: FD1S3DX port map (
+D => PLOL_CNT_S(10),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(10));
+\GENBLK1.PLOL_CNT[11]_REG_Z806\: FD1S3DX port map (
+D => PLOL_CNT_S(11),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(11));
+\GENBLK1.PLOL_CNT[12]_REG_Z808\: FD1S3DX port map (
+D => PLOL_CNT_S(12),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(12));
+\GENBLK1.PLOL_CNT[13]_REG_Z810\: FD1S3DX port map (
+D => PLOL_CNT_S(13),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(13));
+\GENBLK1.PLOL_CNT[14]_REG_Z812\: FD1S3DX port map (
+D => PLOL_CNT_S(14),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(14));
+\GENBLK1.PLOL_CNT[15]_REG_Z814\: FD1S3DX port map (
+D => PLOL_CNT_S(15),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(15));
+\GENBLK1.PLOL_CNT[16]_REG_Z816\: FD1S3DX port map (
+D => PLOL_CNT_S(16),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(16));
+\GENBLK1.PLOL_CNT[17]_REG_Z818\: FD1S3DX port map (
+D => PLOL_CNT_S(17),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(17));
+\GENBLK1.PLOL_CNT[18]_REG_Z820\: FD1S3DX port map (
+D => PLOL_CNT_S(18),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(18));
+\GENBLK1.PLOL_CNT[19]_REG_Z822\: FD1S3DX port map (
+D => PLOL_CNT_S(19),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(19));
+\GENBLK1.PLOL0_CNT[0]_REG_Z824\: FD1S3DX port map (
+D => PLOL0_CNT_3(0),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL0_CNT(0));
+\GENBLK1.PLOL0_CNT[1]_REG_Z826\: FD1S3DX port map (
+D => PLOL0_CNT_3(1),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL0_CNT(1));
+\GENBLK1.PLOL0_CNT[2]_REG_Z828\: FD1S3DX port map (
+D => PLOL0_CNT_3(2),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL0_CNT(2));
+\GENBLK1.PLL_LOL_P3_REG_Z830\: FD1S3DX port map (
+D => PLL_LOL_P2,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLL_LOL_P3);
+\GENBLK1.PLL_LOL_P2_REG_Z832\: FD1S3DX port map (
+D => PLL_LOL_P1,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLL_LOL_P2);
+\GENBLK1.PLL_LOL_P1_REG_Z834\: FD1S3DX port map (
+D => pll_lock_i,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLL_LOL_P1);
+\GENBLK1.GENBLK2.TXSR_APPD_REG_Z836\: FD1S3BX port map (
+D => TXSR_APPD_2,
+CK => pll_refclki,
+PD => rsl_rst,
+Q => TXSR_APPD);
+\GENBLK1.GENBLK2.TXR_WT_EN_REG_Z838\: FD1P3DX port map (
+D => UN1_DUAL_OR_SERD_RST_1_1,
+SP => UN1_DUAL_OR_SERD_RST_1_I,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_EN);
+\GENBLK1.GENBLK2.TXR_WT_CNT[0]_REG_Z840\: FD1P3DX port map (
+D => TXR_WT_CNT_S(0),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(0));
+\GENBLK1.GENBLK2.TXR_WT_CNT[1]_REG_Z842\: FD1P3DX port map (
+D => TXR_WT_CNT_S(1),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(1));
+\GENBLK1.GENBLK2.TXR_WT_CNT[2]_REG_Z844\: FD1P3DX port map (
+D => TXR_WT_CNT_S(2),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(2));
+\GENBLK1.GENBLK2.TXR_WT_CNT[3]_REG_Z846\: FD1P3DX port map (
+D => TXR_WT_CNT_S(3),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(3));
+\GENBLK1.GENBLK2.TXR_WT_CNT[4]_REG_Z848\: FD1P3DX port map (
+D => TXR_WT_CNT_S(4),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(4));
+\GENBLK1.GENBLK2.TXR_WT_CNT[5]_REG_Z850\: FD1P3DX port map (
+D => TXR_WT_CNT_S(5),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(5));
+\GENBLK1.GENBLK2.TXR_WT_CNT[6]_REG_Z852\: FD1P3DX port map (
+D => TXR_WT_CNT_S(6),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(6));
+\GENBLK1.GENBLK2.TXR_WT_CNT[7]_REG_Z854\: FD1P3DX port map (
+D => TXR_WT_CNT_S(7),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(7));
+\GENBLK1.GENBLK2.TXR_WT_CNT[8]_REG_Z856\: FD1P3DX port map (
+D => TXR_WT_CNT_S(8),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(8));
+\GENBLK1.GENBLK2.TXR_WT_CNT[9]_REG_Z858\: FD1P3DX port map (
+D => TXR_WT_CNT_S(9),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(9));
+\GENBLK1.GENBLK2.TXR_WT_CNT[10]_REG_Z860\: FD1P3DX port map (
+D => TXR_WT_CNT_S(10),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(10));
+\GENBLK1.GENBLK2.TXR_WT_CNT[11]_REG_Z862\: FD1P3DX port map (
+D => TXR_WT_CNT_S(11),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(11));
+\GENBLK1.GENBLK2.TXDPR_APPD_REG_Z864\: FD1P3DX port map (
+D => UN2_PLOL_FEDGE_2,
+SP => UN2_PLOL_FEDGE_3_I,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXDPR_APPD);
+\GENBLK1.GENBLK2.RUO_TX_RDYR_REG_Z866\: FD1P3DX port map (
+D => UN2_PLOL_FEDGE_5_1,
+SP => UN2_PLOL_FEDGE_5_I,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => RSL_TX_RDY_7);
+\GENBLK1.GENBLK2.MFOR[0].TXPR_APPD[0]_REG_Z868\: FD1P3DX port map (
+D => UN2_PLOL_FEDGE_2,
+SP => UN2_PLOL_FEDGE_8_I,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXPR_APPD(0));
+\GENBLK1.TXS_CNT_RNO[0]\: LUT4 
+generic map(
+  init => X"A6A6"
+)
+port map (
+A => TXS_CNT(0),
+B => TXS_RST,
+C => UN1_PLOL_CNT_TC,
+D => VCC,
+Z => N_10_I);
+\GENBLK1.TXS_CNT_RNO[1]\: LUT4 
+generic map(
+  init => X"CC6C"
+)
+port map (
+A => TXS_CNT(0),
+B => TXS_CNT(1),
+C => TXS_RST,
+D => UN1_PLOL_CNT_TC,
+Z => TXS_CNT_RNO(1));
+\GENBLK2.RXP_RST2_RNO_0\: LUT4 
+generic map(
+  init => X"FFFE"
+)
+port map (
+A => RLOLS0_CNT_TC_1,
+B => RLOS_REDGE,
+C => RSL_RX_SERDES_RST_C_9,
+D => RSL_SERDES_RST_DUAL_C_10,
+Z => UN2_RLOS_REDGE_1_I);
+\GENBLK1.GENBLK2.TXR_WT_EN_RNO\: LUT4 
+generic map(
+  init => X"0F2F"
+)
+port map (
+A => TXPR_APPD(0),
+B => PLL_LOL_P2,
+C => UN1_DUAL_OR_SERD_RST_1_1,
+D => RSL_TX_RDY_7,
+Z => UN1_DUAL_OR_SERD_RST_1_I);
+\GENBLK2.RXS_RST6\: LUT4 
+generic map(
+  init => X"2020"
+)
+port map (
+A => RLOL_DB,
+B => RLOS_DB,
+C => RLOL1_CNT_TC_1,
+D => VCC,
+Z => RXS_RST6);
+\GENBLK2.WAIT_CALIB_RNIKRP81\: LUT4 
+generic map(
+  init => X"FFFE"
+)
+port map (
+A => RXS_RST,
+B => WAIT_CALIB,
+C => RLOL1_CNT_TC_1,
+D => RLOS_REDGE,
+Z => RLOL1_CNTE);
+\GENBLK2.WAITA_RLOLS0_RNI266C\: LUT4 
+generic map(
+  init => X"FEFE"
+)
+port map (
+A => RLOLS0_CNT11_0,
+B => WAITA_RLOLS0,
+C => RLOLS0_CNT_TC_1,
+D => VCC,
+Z => RLOLS0_CNTE);
+\GENBLK1.PLOL_CNT11_I\: LUT4 
+generic map(
+  init => X"0202"
+)
+port map (
+A => PLL_LOL_P2,
+B => UN1_PLOL_CNT_TC,
+C => RSL_TX_SERDES_RST_C_6,
+D => VCC,
+Z => \PLOL_CNT_\);
+\GENBLK2.RLOLS0_CNT11_I\: LUT4 
+generic map(
+  init => X"1111"
+)
+port map (
+A => RLOLS0_CNT11_0,
+B => RLOLS0_CNT_TC_1,
+C => VCC,
+D => VCC,
+Z => \RLOLS0_CNT_\);
+\GENBLK2.UN1_RXS_CNT_TC\: LUT4 
+generic map(
+  init => X"FEFC"
+)
+port map (
+A => RLOL_DB,
+B => RLOS_DB,
+C => UN8_RXS_CNT_TC,
+D => RLOL1_CNT_TC_1,
+Z => UN1_RXS_CNT_TC);
+\GENBLK2.WAIT_CALIB_RNO\: LUT4 
+generic map(
+  init => X"A3A3"
+)
+port map (
+A => RLOL_DB,
+B => RLOS_DB,
+C => RLOL1_CNT_TC_1,
+D => VCC,
+Z => WAIT_CALIB_RNO);
+\GENBLK1.GENBLK2.MFOR[0].TXPR_APPD_RNO[0]\: LUT4 
+generic map(
+  init => X"FFFE"
+)
+port map (
+A => UN1_TXSR_APPD,
+B => PLL_LOL_P2,
+C => RSL_SERDES_RST_DUAL_C_10,
+D => RSL_TX_SERDES_RST_C_6,
+Z => UN2_PLOL_FEDGE_8_I);
+\GENBLK2.GENBLK3.RXR_WT_EN_RNO_0\: LUT4 
+generic map(
+  init => X"FFFB"
+)
+port map (
+A => UN17_RXR_WT_TC,
+B => UN1_DUAL_OR_RSERD_RST_2_0,
+C => RSL_RX_SERDES_RST_C_9,
+D => RSL_SERDES_RST_DUAL_C_10,
+Z => UN1_DUAL_OR_RSERD_RST_2_I);
+\GENBLK2.GENBLK3.LFOR[0].RXPR_APPD_RNO_0[0]\: LUT4 
+generic map(
+  init => X"FFFB"
+)
+port map (
+A => UN1_RXSDR_OR_SR_APPD,
+B => UN2_RDO_SERDES_RST_DUAL_C_1_1,
+C => RSL_RX_SERDES_RST_C_9,
+D => RSL_SERDES_RST_DUAL_C_10,
+Z => UN2_RDO_SERDES_RST_DUAL_C_2_I);
+\GENBLK1.GENBLK2.TXR_WT_EN_RNICEBT\: LUT4 
+generic map(
+  init => X"FEFE"
+)
+port map (
+A => TXR_WT_EN,
+B => UN18_TXR_WT_TC,
+C => TX_ANY_RST,
+D => VCC,
+Z => TXR_WT_CNTE);
+\GENBLK1.UN2_PLOL_CNT_TC\: LUT4 
+generic map(
+  init => X"F8F8"
+)
+port map (
+A => TXS_CNT(0),
+B => TXS_CNT(1),
+C => UN1_PLOL_CNT_TC,
+D => VCC,
+Z => UN2_PLOL_CNT_TC);
+\GENBLK2.UN1_RLOS_FEDGE_1\: LUT4 
+generic map(
+  init => X"F6F6"
+)
+port map (
+A => RLOS_DB,
+B => RLOS_DB_P1,
+C => RLOL1_CNT_TC_1,
+D => VCC,
+Z => UN1_RLOS_FEDGE_1);
+\GENBLK2.UN1_RLOLS0_CNT_TC\: LUT4 
+generic map(
+  init => X"FEFE"
+)
+port map (
+A => RLOLS0_CNT11_0,
+B => WAITA_RLOLS06,
+C => RLOLS0_CNT_TC_1,
+D => VCC,
+Z => UN1_RLOLS0_CNT_TC);
+\GENBLK1.GENBLK2.TXDPR_APPD_RNO\: LUT4 
+generic map(
+  init => X"FFFE"
+)
+port map (
+A => PLL_LOL_P2,
+B => RSL_SERDES_RST_DUAL_C_10,
+C => RSL_TX_SERDES_RST_C_6,
+D => rst_dual_c,
+Z => UN2_PLOL_FEDGE_3_I);
+\GENBLK1.TXP_CNT_RNO[0]\: LUT4 
+generic map(
+  init => X"A6A6"
+)
+port map (
+A => TXP_CNT(0),
+B => TXP_RST,
+C => UN9_PLOL0_CNT_TC,
+D => VCC,
+Z => N_11_I);
+\GENBLK1.TXP_CNT_RNO[1]\: LUT4 
+generic map(
+  init => X"CC6C"
+)
+port map (
+A => TXP_CNT(0),
+B => TXP_CNT(1),
+C => TXP_RST,
+D => UN9_PLOL0_CNT_TC,
+Z => TXP_CNT_RNO(1));
+UN1_DUAL_OR_SERD_RST_1_1_Z890: LUT4 
+generic map(
+  init => X"0101"
+)
+port map (
+A => UN18_TXR_WT_TC,
+B => RSL_SERDES_RST_DUAL_C_10,
+C => RSL_TX_SERDES_RST_C_6,
+D => VCC,
+Z => UN1_DUAL_OR_SERD_RST_1_1);
+UN2_PLOL_FEDGE_5_1_Z891: LUT4 
+generic map(
+  init => X"1111"
+)
+port map (
+A => PLL_LOL_P2,
+B => TX_ANY_RST,
+C => VCC,
+D => VCC,
+Z => UN2_PLOL_FEDGE_5_1);
+RLOLS0_CNT_TC_1_Z892: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RLOLS0_CNT_TC_1_10,
+B => RLOLS0_CNT_TC_1_11,
+C => RLOLS0_CNT_TC_1_12,
+D => RLOLS0_CNT_TC_1_13,
+Z => RLOLS0_CNT_TC_1);
+RLOL1_CNT_TC_1_Z893: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RLOL1_CNT_TC_1_11,
+B => RLOL1_CNT_TC_1_12,
+C => RLOL1_CNT_TC_1_13,
+D => RLOL1_CNT_TC_1_14,
+Z => RLOL1_CNT_TC_1);
+\GENBLK1.UN1_PLOL_CNT_TC\: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => UN1_PLOL_CNT_TC_11,
+B => UN1_PLOL_CNT_TC_12,
+C => UN1_PLOL_CNT_TC_13,
+D => UN1_PLOL_CNT_TC_14,
+Z => UN1_PLOL_CNT_TC);
+\UN1_GENBLK2.RLOL_DB_CNT_AXB_0\: LUT4 
+generic map(
+  init => X"9999"
+)
+port map (
+A => RLOL_DB_CNT(0),
+B => UN1_RLOL_DB_CNT_ZERO(0),
+C => VCC,
+D => VCC,
+Z => RLOL_DB_CNT_AXB_0);
+\UN1_GENBLK2.RLOS_DB_CNT_AXB_0\: LUT4 
+generic map(
+  init => X"9999"
+)
+port map (
+A => RLOS_DB_CNT(0),
+B => UN1_RLOS_DB_CNT_ZERO(0),
+C => VCC,
+D => VCC,
+Z => RLOS_DB_CNT_AXB_0);
+\GENBLK1.WAITA_PLOL0_RNO\: LUT4 
+generic map(
+  init => X"F6F6"
+)
+port map (
+A => PLL_LOL_P2,
+B => PLL_LOL_P3,
+C => UN9_PLOL0_CNT_TC,
+D => VCC,
+Z => UN1_PLOL0_CNT_TC_1_I);
+\GENBLK1.PLOL0_CNT_3[2]\: LUT4 
+generic map(
+  init => X"1320"
+)
+port map (
+A => CO0_2,
+B => PLOL0_CNT9,
+C => PLOL0_CNT(1),
+D => PLOL0_CNT(2),
+Z => PLOL0_CNT_3(2));
+\GENBLK1.PLOL0_CNT_3[0]\: LUT4 
+generic map(
+  init => X"1414"
+)
+port map (
+A => PLOL0_CNT9,
+B => PLOL0_CNT(0),
+C => WAITA_PLOL0,
+D => VCC,
+Z => PLOL0_CNT_3(0));
+\GENBLK1.GENBLK2.TXSR_APPD_2\: LUT4 
+generic map(
+  init => X"FEFE"
+)
+port map (
+A => TXSR_APPD_4,
+B => RSL_SERDES_RST_DUAL_C_10,
+C => RSL_TX_SERDES_RST_C_6,
+D => VCC,
+Z => TXSR_APPD_2);
+\GENBLK1.GENBLK2.MFOR[0].UN1_TXSR_APPD\: LUT4 
+generic map(
+  init => X"C8C8"
+)
+port map (
+A => TXDPR_APPD,
+B => TXSR_APPD_4,
+C => RSL_TX_PCS_RST_C_5,
+D => VCC,
+Z => UN1_TXSR_APPD);
+\GENBLK2.GENBLK3.UN17_RXR_WT_TC\: LUT4 
+generic map(
+  init => X"8080"
+)
+port map (
+A => UN17_RXR_WT_TC_6,
+B => UN17_RXR_WT_TC_7,
+C => UN17_RXR_WT_TC_8,
+D => VCC,
+Z => UN17_RXR_WT_TC);
+RX_ANY_RST_Z903: LUT4 
+generic map(
+  init => X"FFFE"
+)
+port map (
+A => RSL_RX_PCS_RST_C_4,
+B => RSL_RX_SERDES_RST_C_9,
+C => RSL_SERDES_RST_DUAL_C_10,
+D => rst_dual_c,
+Z => RX_ANY_RST);
+TX_ANY_RST_Z904: LUT4 
+generic map(
+  init => X"FFFE"
+)
+port map (
+A => RSL_SERDES_RST_DUAL_C_10,
+B => RSL_TX_PCS_RST_C_5,
+C => RSL_TX_SERDES_RST_C_6,
+D => rst_dual_c,
+Z => TX_ANY_RST);
+UN2_PLOL_FEDGE_2_Z905: LUT4 
+generic map(
+  init => X"0101"
+)
+port map (
+A => PLL_LOL_P2,
+B => RSL_SERDES_RST_DUAL_C_10,
+C => RSL_TX_SERDES_RST_C_6,
+D => VCC,
+Z => UN2_PLOL_FEDGE_2);
+\GENBLK1.GENBLK2.UN18_TXR_WT_TC\: LUT4 
+generic map(
+  init => X"8080"
+)
+port map (
+A => UN18_TXR_WT_TC_6,
+B => UN18_TXR_WT_TC_7,
+C => UN18_TXR_WT_TC_8,
+D => VCC,
+Z => UN18_TXR_WT_TC);
+\UN1_RLOL_DB_CNT_ZERO_BM[0]_Z907\: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RLOL_DB_CNT(0),
+B => RLOL_DB_CNT(1),
+C => RLOL_DB_CNT(2),
+D => RLOL_DB_CNT(3),
+Z => UN1_RLOL_DB_CNT_ZERO_BM(0));
+\UN1_RLOL_DB_CNT_ZERO[0]_Z908\: PFUMX port map (
+ALUT => UN1_RLOL_DB_CNT_ZERO_BM(0),
+BLUT => UN1_RLOL_DB_CNT_ZERO_AM(0),
+C0 => RLOL_P2,
+Z => UN1_RLOL_DB_CNT_ZERO(0));
+\UN1_RLOS_DB_CNT_ZERO_BM[0]_Z909\: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RLOS_DB_CNT(0),
+B => RLOS_DB_CNT(1),
+C => RLOS_DB_CNT(2),
+D => RLOS_DB_CNT(3),
+Z => UN1_RLOS_DB_CNT_ZERO_BM(0));
+\UN1_RLOS_DB_CNT_ZERO[0]_Z910\: PFUMX port map (
+ALUT => UN1_RLOS_DB_CNT_ZERO_BM(0),
+BLUT => UN1_RLOS_DB_CNT_ZERO_AM(0),
+C0 => RLOS_P2,
+Z => UN1_RLOS_DB_CNT_ZERO(0));
+\GENBLK2.UN1_RLOL_DB_CNT_MAX\: LUT4 
+generic map(
+  init => X"8001"
+)
+port map (
+A => RLOL_DB_CNT(0),
+B => RLOL_DB_CNT(1),
+C => RLOL_DB_CNT(2),
+D => RLOL_DB_CNT(3),
+Z => UN1_RLOL_DB_CNT_MAX);
+\GENBLK2.UN1_RLOS_DB_CNT_MAX\: LUT4 
+generic map(
+  init => X"8001"
+)
+port map (
+A => RLOS_DB_CNT(0),
+B => RLOS_DB_CNT(1),
+C => RLOS_DB_CNT(2),
+D => RLOS_DB_CNT(3),
+Z => UN1_RLOS_DB_CNT_MAX);
+\GENBLK1.UN1_PLOL0_CNT_TC_1\: LUT4 
+generic map(
+  init => X"F8F8"
+)
+port map (
+A => TXP_CNT(0),
+B => TXP_CNT(1),
+C => UN9_PLOL0_CNT_TC,
+D => VCC,
+Z => UN1_PLOL0_CNT_TC_1);
+\GENBLK2.WAITA_RLOLS06\: LUT4 
+generic map(
+  init => X"0504"
+)
+port map (
+A => RLOL_DB,
+B => RLOL_DB_P1,
+C => RLOS_DB,
+D => RLOS_DB_P1,
+Z => WAITA_RLOLS06);
+\RXS_CNT_3[1]_Z915\: LUT4 
+generic map(
+  init => X"6464"
+)
+port map (
+A => RXS_CNT(0),
+B => RXS_CNT(1),
+C => RXS_RST,
+D => VCC,
+Z => RXS_CNT_3(1));
+\GENBLK2.GENBLK3.LFOR[0].UN1_RXSDR_OR_SR_APPD\: LUT4 
+generic map(
+  init => X"3200"
+)
+port map (
+A => RXSR_APPD(0),
+B => RX_ALL_WELL,
+C => RXSDR_APPD_4,
+D => RSL_RX_PCS_RST_C_4,
+Z => UN1_RXSDR_OR_SR_APPD);
+RLOLS0_CNT_TC_1_13_Z917: LUT4 
+generic map(
+  init => X"1010"
+)
+port map (
+A => RLOLS0_CNT(16),
+B => RLOLS0_CNT(17),
+C => RLOLS0_CNT_TC_1_9,
+D => VCC,
+Z => RLOLS0_CNT_TC_1_13);
+\GENBLK1.UN1_PLOL_CNT_TC_14\: LUT4 
+generic map(
+  init => X"0100"
+)
+port map (
+A => PLOL_CNT(4),
+B => PLOL_CNT(5),
+C => PLOL_CNT(18),
+D => UN1_PLOL_CNT_TC_10,
+Z => UN1_PLOL_CNT_TC_14);
+RLOL1_CNT_TC_1_14_Z919: LUT4 
+generic map(
+  init => X"0100"
+)
+port map (
+A => RLOL1_CNT(11),
+B => RLOL1_CNT(12),
+C => RLOL1_CNT(18),
+D => RLOL1_CNT_TC_1_10,
+Z => RLOL1_CNT_TC_1_14);
+UN1_DUAL_OR_RSERD_RST_2_0_Z920: LUT4 
+generic map(
+  init => X"F010"
+)
+port map (
+A => RXPR_APPD(0),
+B => RXDPR_APPD,
+C => RX_ALL_WELL,
+D => RSL_RX_RDY_8,
+Z => UN1_DUAL_OR_RSERD_RST_2_0);
+RDO_TX_SERDES_RST_C: LUT4 
+generic map(
+  init => X"F4F4"
+)
+port map (
+A => rsl_disable,
+B => TXS_RST,
+C => tx_serdes_rst_c,
+D => VCC,
+Z => RSL_TX_SERDES_RST_C_6);
+RDO_SERDES_RST_DUAL_C: LUT4 
+generic map(
+  init => X"F4F4"
+)
+port map (
+A => rsl_disable,
+B => rsl_rst,
+C => serdes_rst_dual_c,
+D => VCC,
+Z => RSL_SERDES_RST_DUAL_C_10);
+\RDO_TX_PCS_RST_C_1[0]\: LUT4 
+generic map(
+  init => X"F4F4"
+)
+port map (
+A => rsl_disable,
+B => TXP_RST,
+C => tx_pcs_rst_c,
+D => VCC,
+Z => RSL_TX_PCS_RST_C_5);
+\RDO_RX_SERDES_RST_C_1[0]\: LUT4 
+generic map(
+  init => X"F4F4"
+)
+port map (
+A => rsl_disable,
+B => RXS_RST,
+C => rx_serdes_rst_c,
+D => VCC,
+Z => RSL_RX_SERDES_RST_C_9);
+\RDO_RX_PCS_RST_C_1[0]\: LUT4 
+generic map(
+  init => X"F4F4"
+)
+port map (
+A => rsl_disable,
+B => RXP_RST2,
+C => rx_pcs_rst_c,
+D => VCC,
+Z => RSL_RX_PCS_RST_C_4);
+\GENBLK1.UN9_PLOL0_CNT_TC\: LUT4 
+generic map(
+  init => X"1010"
+)
+port map (
+A => PLOL0_CNT(0),
+B => PLOL0_CNT(1),
+C => PLOL0_CNT(2),
+D => VCC,
+Z => UN9_PLOL0_CNT_TC);
+\GENBLK1.GENBLK2.UN18_TXR_WT_TC_6\: LUT4 
+generic map(
+  init => X"4000"
+)
+port map (
+A => TXR_WT_CNT(0),
+B => TXR_WT_CNT(8),
+C => TXR_WT_CNT(9),
+D => TXR_WT_CNT(11),
+Z => UN18_TXR_WT_TC_6);
+\GENBLK1.GENBLK2.UN18_TXR_WT_TC_7\: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => TXR_WT_CNT(3),
+B => TXR_WT_CNT(4),
+C => TXR_WT_CNT(5),
+D => TXR_WT_CNT(7),
+Z => UN18_TXR_WT_TC_7);
+\GENBLK1.GENBLK2.UN18_TXR_WT_TC_8\: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => TXR_WT_CNT(1),
+B => TXR_WT_CNT(2),
+C => TXR_WT_CNT(6),
+D => TXR_WT_CNT(10),
+Z => UN18_TXR_WT_TC_8);
+\GENBLK2.GENBLK3.UN17_RXR_WT_TC_6\: LUT4 
+generic map(
+  init => X"4000"
+)
+port map (
+A => RXR_WT_CNT(0),
+B => RXR_WT_CNT(8),
+C => RXR_WT_CNT(9),
+D => RXR_WT_CNT(11),
+Z => UN17_RXR_WT_TC_6);
+\GENBLK2.GENBLK3.UN17_RXR_WT_TC_7\: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RXR_WT_CNT(3),
+B => RXR_WT_CNT(4),
+C => RXR_WT_CNT(5),
+D => RXR_WT_CNT(7),
+Z => UN17_RXR_WT_TC_7);
+\GENBLK2.GENBLK3.UN17_RXR_WT_TC_8\: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RXR_WT_CNT(1),
+B => RXR_WT_CNT(2),
+C => RXR_WT_CNT(6),
+D => RXR_WT_CNT(10),
+Z => UN17_RXR_WT_TC_8);
+RLOLS0_CNT_TC_1_9_Z933: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RLOLS0_CNT(1),
+B => RLOLS0_CNT(2),
+C => RLOLS0_CNT(3),
+D => RLOLS0_CNT(4),
+Z => RLOLS0_CNT_TC_1_9);
+RLOLS0_CNT_TC_1_10_Z934: LUT4 
+generic map(
+  init => X"4000"
+)
+port map (
+A => RLOLS0_CNT(0),
+B => RLOLS0_CNT(10),
+C => RLOLS0_CNT(14),
+D => RLOLS0_CNT(15),
+Z => RLOLS0_CNT_TC_1_10);
+RLOLS0_CNT_TC_1_11_Z935: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RLOLS0_CNT(9),
+B => RLOLS0_CNT(11),
+C => RLOLS0_CNT(12),
+D => RLOLS0_CNT(13),
+Z => RLOLS0_CNT_TC_1_11);
+RLOLS0_CNT_TC_1_12_Z936: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RLOLS0_CNT(5),
+B => RLOLS0_CNT(6),
+C => RLOLS0_CNT(7),
+D => RLOLS0_CNT(8),
+Z => RLOLS0_CNT_TC_1_12);
+\GENBLK1.UN1_PLOL_CNT_TC_10\: LUT4 
+generic map(
+  init => X"1000"
+)
+port map (
+A => PLOL_CNT(2),
+B => PLOL_CNT(3),
+C => PLOL_CNT(17),
+D => PLOL_CNT(19),
+Z => UN1_PLOL_CNT_TC_10);
+\GENBLK1.UN1_PLOL_CNT_TC_11\: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => PLOL_CNT(13),
+B => PLOL_CNT(14),
+C => PLOL_CNT(15),
+D => PLOL_CNT(16),
+Z => UN1_PLOL_CNT_TC_11);
+\GENBLK1.UN1_PLOL_CNT_TC_12\: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => PLOL_CNT(7),
+B => PLOL_CNT(8),
+C => PLOL_CNT(9),
+D => PLOL_CNT(11),
+Z => UN1_PLOL_CNT_TC_12);
+\GENBLK1.UN1_PLOL_CNT_TC_13\: LUT4 
+generic map(
+  init => X"0008"
+)
+port map (
+A => PLOL_CNT(1),
+B => PLOL_CNT(6),
+C => PLOL_CNT(10),
+D => PLOL_CNT(12),
+Z => UN1_PLOL_CNT_TC_13);
+RLOL1_CNT_TC_1_10_Z941: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RLOL1_CNT(7),
+B => RLOL1_CNT(8),
+C => RLOL1_CNT(9),
+D => RLOL1_CNT(10),
+Z => RLOL1_CNT_TC_1_10);
+RLOL1_CNT_TC_1_11_Z942: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RLOL1_CNT(3),
+B => RLOL1_CNT(4),
+C => RLOL1_CNT(5),
+D => RLOL1_CNT(6),
+Z => RLOL1_CNT_TC_1_11);
+RLOL1_CNT_TC_1_12_Z943: LUT4 
+generic map(
+  init => X"0100"
+)
+port map (
+A => RLOL1_CNT(0),
+B => RLOL1_CNT(1),
+C => RLOL1_CNT(2),
+D => RLOL1_CNT(17),
+Z => RLOL1_CNT_TC_1_12);
+RLOL1_CNT_TC_1_13_Z944: LUT4 
+generic map(
+  init => X"0040"
+)
+port map (
+A => RLOL1_CNT(13),
+B => RLOL1_CNT(14),
+C => RLOL1_CNT(15),
+D => RLOL1_CNT(16),
+Z => RLOL1_CNT_TC_1_13);
+\GENBLK1.PLOL0_CNT_3_RNO[2]\: LUT4 
+generic map(
+  init => X"8888"
+)
+port map (
+A => PLOL0_CNT(0),
+B => WAITA_PLOL0,
+C => VCC,
+D => VCC,
+Z => CO0_2);
+PLOL_FEDGE_Z946: LUT4 
+generic map(
+  init => X"4444"
+)
+port map (
+A => PLL_LOL_P2,
+B => PLL_LOL_P3,
+C => VCC,
+D => VCC,
+Z => PLOL_FEDGE);
+RX_ALL_WELL_Z947: LUT4 
+generic map(
+  init => X"1111"
+)
+port map (
+A => RLOL_DB,
+B => RLOS_DB,
+C => VCC,
+D => VCC,
+Z => RX_ALL_WELL);
+\GENBLK2.GENBLK3.RXSDR_APPD_2\: LUT4 
+generic map(
+  init => X"EEEE"
+)
+port map (
+A => RXSDR_APPD_4,
+B => serdes_rst_dual_c,
+C => VCC,
+D => VCC,
+Z => RXSDR_APPD_2);
+\GENBLK2.UN8_RXS_CNT_TC\: LUT4 
+generic map(
+  init => X"8888"
+)
+port map (
+A => RXS_CNT(0),
+B => RXS_CNT(1),
+C => VCC,
+D => VCC,
+Z => UN8_RXS_CNT_TC);
+RLOS_REDGE_Z950: LUT4 
+generic map(
+  init => X"2222"
+)
+port map (
+A => RLOS_DB,
+B => RLOS_DB_P1,
+C => VCC,
+D => VCC,
+Z => RLOS_REDGE);
+UN2_RDO_SERDES_RST_DUAL_C_1_1_Z951: LUT4 
+generic map(
+  init => X"1111"
+)
+port map (
+A => rx_cdr_lol_s,
+B => rx_los_low_s,
+C => VCC,
+D => VCC,
+Z => UN2_RDO_SERDES_RST_DUAL_C_1_1);
+\UN1_RLOS_DB_CNT_ZERO_AM[0]_Z952\: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RLOS_DB_CNT(0),
+B => RLOS_DB_CNT(1),
+C => RLOS_DB_CNT(2),
+D => RLOS_DB_CNT(3),
+Z => UN1_RLOS_DB_CNT_ZERO_AM(0));
+\UN1_RLOL_DB_CNT_ZERO_AM[0]_Z953\: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RLOL_DB_CNT(0),
+B => RLOL_DB_CNT(1),
+C => RLOL_DB_CNT(2),
+D => RLOL_DB_CNT(3),
+Z => UN1_RLOL_DB_CNT_ZERO_AM(0));
+\GENBLK1.PLOL0_CNT9\: LUT4 
+generic map(
+  init => X"AAAE"
+)
+port map (
+A => PLL_LOL_P2,
+B => PLOL0_CNT(2),
+C => PLOL0_CNT(1),
+D => PLOL0_CNT(0),
+Z => PLOL0_CNT9);
+\GENBLK2.RLOLS0_CNT11_0\: LUT4 
+generic map(
+  init => X"4F44"
+)
+port map (
+A => RLOL_DB_P1,
+B => RLOL_DB,
+C => RLOS_DB_P1,
+D => RLOS_DB,
+Z => RLOLS0_CNT11_0);
+\GENBLK1.GENBLK2.TXR_WT_CNT9_I\: LUT4 
+generic map(
+  init => X"1555"
+)
+port map (
+A => TX_ANY_RST,
+B => UN18_TXR_WT_TC_8,
+C => UN18_TXR_WT_TC_7,
+D => UN18_TXR_WT_TC_6,
+Z => \TXR_WT_CNT_\);
+\GENBLK2.RLOL1_CNT_CRY_0[0]\: CCU2C 
+generic map(
+  INIT0 => X"500c",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => \RLOL1_CNT_\,
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_7,
+COUT => RLOL1_CNT_CRY(0),
+S0 => RLOL1_CNT_CRY_0_S0(0),
+S1 => RLOL1_CNT_S(0));
+\GENBLK2.RLOL1_CNT_CRY_0[1]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOL1_CNT_\,
+B0 => RLOL1_CNT(1),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(2),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL1_CNT_CRY(0),
+COUT => RLOL1_CNT_CRY(2),
+S0 => RLOL1_CNT_S(1),
+S1 => RLOL1_CNT_S(2));
+\GENBLK2.RLOL1_CNT_CRY_0[3]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOL1_CNT_\,
+B0 => RLOL1_CNT(3),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(4),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL1_CNT_CRY(2),
+COUT => RLOL1_CNT_CRY(4),
+S0 => RLOL1_CNT_S(3),
+S1 => RLOL1_CNT_S(4));
+\GENBLK2.RLOL1_CNT_CRY_0[5]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOL1_CNT_\,
+B0 => RLOL1_CNT(5),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(6),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL1_CNT_CRY(4),
+COUT => RLOL1_CNT_CRY(6),
+S0 => RLOL1_CNT_S(5),
+S1 => RLOL1_CNT_S(6));
+\GENBLK2.RLOL1_CNT_CRY_0[7]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOL1_CNT_\,
+B0 => RLOL1_CNT(7),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(8),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL1_CNT_CRY(6),
+COUT => RLOL1_CNT_CRY(8),
+S0 => RLOL1_CNT_S(7),
+S1 => RLOL1_CNT_S(8));
+\GENBLK2.RLOL1_CNT_CRY_0[9]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOL1_CNT_\,
+B0 => RLOL1_CNT(9),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(10),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL1_CNT_CRY(8),
+COUT => RLOL1_CNT_CRY(10),
+S0 => RLOL1_CNT_S(9),
+S1 => RLOL1_CNT_S(10));
+\GENBLK2.RLOL1_CNT_CRY_0[11]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOL1_CNT_\,
+B0 => RLOL1_CNT(11),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(12),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL1_CNT_CRY(10),
+COUT => RLOL1_CNT_CRY(12),
+S0 => RLOL1_CNT_S(11),
+S1 => RLOL1_CNT_S(12));
+\GENBLK2.RLOL1_CNT_CRY_0[13]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOL1_CNT_\,
+B0 => RLOL1_CNT(13),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(14),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL1_CNT_CRY(12),
+COUT => RLOL1_CNT_CRY(14),
+S0 => RLOL1_CNT_S(13),
+S1 => RLOL1_CNT_S(14));
+\GENBLK2.RLOL1_CNT_CRY_0[15]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOL1_CNT_\,
+B0 => RLOL1_CNT(15),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(16),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL1_CNT_CRY(14),
+COUT => RLOL1_CNT_CRY(16),
+S0 => RLOL1_CNT_S(15),
+S1 => RLOL1_CNT_S(16));
+\GENBLK2.RLOL1_CNT_CRY_0[17]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"800a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOL1_CNT_\,
+B0 => RLOL1_CNT(17),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(18),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL1_CNT_CRY(16),
+COUT => RLOL1_CNT_CRY_0_COUT(17),
+S0 => RLOL1_CNT_S(17),
+S1 => RLOL1_CNT_S(18));
+\GENBLK2.RLOLS0_CNT_CRY_0[0]\: CCU2C 
+generic map(
+  INIT0 => X"500c",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => \RLOLS0_CNT_\,
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOLS0_CNT_\,
+B1 => RLOLS0_CNT(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_6,
+COUT => RLOLS0_CNT_CRY(0),
+S0 => RLOLS0_CNT_CRY_0_S0(0),
+S1 => RLOLS0_CNT_S(0));
+\GENBLK2.RLOLS0_CNT_CRY_0[1]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOLS0_CNT_\,
+B0 => RLOLS0_CNT(1),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOLS0_CNT_\,
+B1 => RLOLS0_CNT(2),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOLS0_CNT_CRY(0),
+COUT => RLOLS0_CNT_CRY(2),
+S0 => RLOLS0_CNT_S(1),
+S1 => RLOLS0_CNT_S(2));
+\GENBLK2.RLOLS0_CNT_CRY_0[3]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOLS0_CNT_\,
+B0 => RLOLS0_CNT(3),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOLS0_CNT_\,
+B1 => RLOLS0_CNT(4),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOLS0_CNT_CRY(2),
+COUT => RLOLS0_CNT_CRY(4),
+S0 => RLOLS0_CNT_S(3),
+S1 => RLOLS0_CNT_S(4));
+\GENBLK2.RLOLS0_CNT_CRY_0[5]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOLS0_CNT_\,
+B0 => RLOLS0_CNT(5),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOLS0_CNT_\,
+B1 => RLOLS0_CNT(6),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOLS0_CNT_CRY(4),
+COUT => RLOLS0_CNT_CRY(6),
+S0 => RLOLS0_CNT_S(5),
+S1 => RLOLS0_CNT_S(6));
+\GENBLK2.RLOLS0_CNT_CRY_0[7]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOLS0_CNT_\,
+B0 => RLOLS0_CNT(7),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOLS0_CNT_\,
+B1 => RLOLS0_CNT(8),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOLS0_CNT_CRY(6),
+COUT => RLOLS0_CNT_CRY(8),
+S0 => RLOLS0_CNT_S(7),
+S1 => RLOLS0_CNT_S(8));
+\GENBLK2.RLOLS0_CNT_CRY_0[9]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOLS0_CNT_\,
+B0 => RLOLS0_CNT(9),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOLS0_CNT_\,
+B1 => RLOLS0_CNT(10),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOLS0_CNT_CRY(8),
+COUT => RLOLS0_CNT_CRY(10),
+S0 => RLOLS0_CNT_S(9),
+S1 => RLOLS0_CNT_S(10));
+\GENBLK2.RLOLS0_CNT_CRY_0[11]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOLS0_CNT_\,
+B0 => RLOLS0_CNT(11),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOLS0_CNT_\,
+B1 => RLOLS0_CNT(12),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOLS0_CNT_CRY(10),
+COUT => RLOLS0_CNT_CRY(12),
+S0 => RLOLS0_CNT_S(11),
+S1 => RLOLS0_CNT_S(12));
+\GENBLK2.RLOLS0_CNT_CRY_0[13]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOLS0_CNT_\,
+B0 => RLOLS0_CNT(13),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOLS0_CNT_\,
+B1 => RLOLS0_CNT(14),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOLS0_CNT_CRY(12),
+COUT => RLOLS0_CNT_CRY(14),
+S0 => RLOLS0_CNT_S(13),
+S1 => RLOLS0_CNT_S(14));
+\GENBLK2.RLOLS0_CNT_CRY_0[15]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOLS0_CNT_\,
+B0 => RLOLS0_CNT(15),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOLS0_CNT_\,
+B1 => RLOLS0_CNT(16),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOLS0_CNT_CRY(14),
+COUT => RLOLS0_CNT_CRY(16),
+S0 => RLOLS0_CNT_S(15),
+S1 => RLOLS0_CNT_S(16));
+\GENBLK2.RLOLS0_CNT_S_0[17]\: CCU2C 
+generic map(
+  INIT0 => X"800a",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOLS0_CNT_\,
+B0 => RLOLS0_CNT(17),
+C0 => VCC,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => RLOLS0_CNT_CRY(16),
+COUT => RLOLS0_CNT_S_0_COUT(17),
+S0 => RLOLS0_CNT_S(17),
+S1 => RLOLS0_CNT_S_0_S1(17));
+\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[0]\: CCU2C 
+generic map(
+  INIT0 => X"500c",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => \TXR_WT_CNT_\,
+C0 => VCC,
+D0 => VCC,
+A1 => \TXR_WT_CNT_\,
+B1 => TXR_WT_CNT(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_5,
+COUT => TXR_WT_CNT_CRY(0),
+S0 => TXR_WT_CNT_CRY_0_S0(0),
+S1 => TXR_WT_CNT_S(0));
+\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[1]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \TXR_WT_CNT_\,
+B0 => TXR_WT_CNT(1),
+C0 => VCC,
+D0 => VCC,
+A1 => \TXR_WT_CNT_\,
+B1 => TXR_WT_CNT(2),
+C1 => VCC,
+D1 => VCC,
+CIN => TXR_WT_CNT_CRY(0),
+COUT => TXR_WT_CNT_CRY(2),
+S0 => TXR_WT_CNT_S(1),
+S1 => TXR_WT_CNT_S(2));
+\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[3]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \TXR_WT_CNT_\,
+B0 => TXR_WT_CNT(3),
+C0 => VCC,
+D0 => VCC,
+A1 => \TXR_WT_CNT_\,
+B1 => TXR_WT_CNT(4),
+C1 => VCC,
+D1 => VCC,
+CIN => TXR_WT_CNT_CRY(2),
+COUT => TXR_WT_CNT_CRY(4),
+S0 => TXR_WT_CNT_S(3),
+S1 => TXR_WT_CNT_S(4));
+\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[5]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \TXR_WT_CNT_\,
+B0 => TXR_WT_CNT(5),
+C0 => VCC,
+D0 => VCC,
+A1 => \TXR_WT_CNT_\,
+B1 => TXR_WT_CNT(6),
+C1 => VCC,
+D1 => VCC,
+CIN => TXR_WT_CNT_CRY(4),
+COUT => TXR_WT_CNT_CRY(6),
+S0 => TXR_WT_CNT_S(5),
+S1 => TXR_WT_CNT_S(6));
+\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[7]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \TXR_WT_CNT_\,
+B0 => TXR_WT_CNT(7),
+C0 => VCC,
+D0 => VCC,
+A1 => \TXR_WT_CNT_\,
+B1 => TXR_WT_CNT(8),
+C1 => VCC,
+D1 => VCC,
+CIN => TXR_WT_CNT_CRY(6),
+COUT => TXR_WT_CNT_CRY(8),
+S0 => TXR_WT_CNT_S(7),
+S1 => TXR_WT_CNT_S(8));
+\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[9]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \TXR_WT_CNT_\,
+B0 => TXR_WT_CNT(9),
+C0 => VCC,
+D0 => VCC,
+A1 => \TXR_WT_CNT_\,
+B1 => TXR_WT_CNT(10),
+C1 => VCC,
+D1 => VCC,
+CIN => TXR_WT_CNT_CRY(8),
+COUT => TXR_WT_CNT_CRY(10),
+S0 => TXR_WT_CNT_S(9),
+S1 => TXR_WT_CNT_S(10));
+\GENBLK1.GENBLK2.TXR_WT_CNT_S_0[11]\: CCU2C 
+generic map(
+  INIT0 => X"800a",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \TXR_WT_CNT_\,
+B0 => TXR_WT_CNT(11),
+C0 => VCC,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => TXR_WT_CNT_CRY(10),
+COUT => TXR_WT_CNT_S_0_COUT(11),
+S0 => TXR_WT_CNT_S(11),
+S1 => TXR_WT_CNT_S_0_S1(11));
+\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[0]\: CCU2C 
+generic map(
+  INIT0 => X"5003",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => RXR_WT_CNT9,
+C0 => VCC,
+D0 => VCC,
+A1 => RXR_WT_CNT9,
+B1 => RXR_WT_CNT(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_4,
+COUT => RXR_WT_CNT_CRY(0),
+S0 => RXR_WT_CNT_CRY_0_S0(0),
+S1 => RXR_WT_CNT_S(0));
+\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[1]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => RXR_WT_CNT9,
+B0 => RXR_WT_CNT(1),
+C0 => VCC,
+D0 => VCC,
+A1 => RXR_WT_CNT9,
+B1 => RXR_WT_CNT(2),
+C1 => VCC,
+D1 => VCC,
+CIN => RXR_WT_CNT_CRY(0),
+COUT => RXR_WT_CNT_CRY(2),
+S0 => RXR_WT_CNT_S(1),
+S1 => RXR_WT_CNT_S(2));
+\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[3]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => RXR_WT_CNT9,
+B0 => RXR_WT_CNT(3),
+C0 => VCC,
+D0 => VCC,
+A1 => RXR_WT_CNT9,
+B1 => RXR_WT_CNT(4),
+C1 => VCC,
+D1 => VCC,
+CIN => RXR_WT_CNT_CRY(2),
+COUT => RXR_WT_CNT_CRY(4),
+S0 => RXR_WT_CNT_S(3),
+S1 => RXR_WT_CNT_S(4));
+\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[5]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => RXR_WT_CNT9,
+B0 => RXR_WT_CNT(5),
+C0 => VCC,
+D0 => VCC,
+A1 => RXR_WT_CNT9,
+B1 => RXR_WT_CNT(6),
+C1 => VCC,
+D1 => VCC,
+CIN => RXR_WT_CNT_CRY(4),
+COUT => RXR_WT_CNT_CRY(6),
+S0 => RXR_WT_CNT_S(5),
+S1 => RXR_WT_CNT_S(6));
+\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[7]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => RXR_WT_CNT9,
+B0 => RXR_WT_CNT(7),
+C0 => VCC,
+D0 => VCC,
+A1 => RXR_WT_CNT9,
+B1 => RXR_WT_CNT(8),
+C1 => VCC,
+D1 => VCC,
+CIN => RXR_WT_CNT_CRY(6),
+COUT => RXR_WT_CNT_CRY(8),
+S0 => RXR_WT_CNT_S(7),
+S1 => RXR_WT_CNT_S(8));
+\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[9]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => RXR_WT_CNT9,
+B0 => RXR_WT_CNT(9),
+C0 => VCC,
+D0 => VCC,
+A1 => RXR_WT_CNT9,
+B1 => RXR_WT_CNT(10),
+C1 => VCC,
+D1 => VCC,
+CIN => RXR_WT_CNT_CRY(8),
+COUT => RXR_WT_CNT_CRY(10),
+S0 => RXR_WT_CNT_S(9),
+S1 => RXR_WT_CNT_S(10));
+\GENBLK2.GENBLK3.RXR_WT_CNT_S_0[11]\: CCU2C 
+generic map(
+  INIT0 => X"4005",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => RXR_WT_CNT9,
+B0 => RXR_WT_CNT(11),
+C0 => VCC,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => RXR_WT_CNT_CRY(10),
+COUT => RXR_WT_CNT_S_0_COUT(11),
+S0 => RXR_WT_CNT_S(11),
+S1 => RXR_WT_CNT_S_0_S1(11));
+\GENBLK1.PLOL_CNT_CRY_0[0]\: CCU2C 
+generic map(
+  INIT0 => X"500c",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => \PLOL_CNT_\,
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_3,
+COUT => PLOL_CNT_CRY(0),
+S0 => PLOL_CNT_CRY_0_S0(0),
+S1 => PLOL_CNT_S(0));
+\GENBLK1.PLOL_CNT_CRY_0[1]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(1),
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(2),
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(0),
+COUT => PLOL_CNT_CRY(2),
+S0 => PLOL_CNT_S(1),
+S1 => PLOL_CNT_S(2));
+\GENBLK1.PLOL_CNT_CRY_0[3]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(3),
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(4),
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(2),
+COUT => PLOL_CNT_CRY(4),
+S0 => PLOL_CNT_S(3),
+S1 => PLOL_CNT_S(4));
+\GENBLK1.PLOL_CNT_CRY_0[5]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(5),
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(6),
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(4),
+COUT => PLOL_CNT_CRY(6),
+S0 => PLOL_CNT_S(5),
+S1 => PLOL_CNT_S(6));
+\GENBLK1.PLOL_CNT_CRY_0[7]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(7),
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(8),
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(6),
+COUT => PLOL_CNT_CRY(8),
+S0 => PLOL_CNT_S(7),
+S1 => PLOL_CNT_S(8));
+\GENBLK1.PLOL_CNT_CRY_0[9]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(9),
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(10),
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(8),
+COUT => PLOL_CNT_CRY(10),
+S0 => PLOL_CNT_S(9),
+S1 => PLOL_CNT_S(10));
+\GENBLK1.PLOL_CNT_CRY_0[11]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(11),
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(12),
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(10),
+COUT => PLOL_CNT_CRY(12),
+S0 => PLOL_CNT_S(11),
+S1 => PLOL_CNT_S(12));
+\GENBLK1.PLOL_CNT_CRY_0[13]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(13),
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(14),
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(12),
+COUT => PLOL_CNT_CRY(14),
+S0 => PLOL_CNT_S(13),
+S1 => PLOL_CNT_S(14));
+\GENBLK1.PLOL_CNT_CRY_0[15]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(15),
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(16),
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(14),
+COUT => PLOL_CNT_CRY(16),
+S0 => PLOL_CNT_S(15),
+S1 => PLOL_CNT_S(16));
+\GENBLK1.PLOL_CNT_CRY_0[17]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(17),
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(18),
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(16),
+COUT => PLOL_CNT_CRY(18),
+S0 => PLOL_CNT_S(17),
+S1 => PLOL_CNT_S(18));
+\GENBLK1.PLOL_CNT_S_0[19]\: CCU2C 
+generic map(
+  INIT0 => X"800a",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(19),
+C0 => VCC,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(18),
+COUT => PLOL_CNT_S_0_COUT(19),
+S0 => PLOL_CNT_S(19),
+S1 => PLOL_CNT_S_0_S1(19));
+\UN1_GENBLK2.RLOS_DB_CNT_CRY_0_0\: CCU2C 
+generic map(
+  INIT0 => X"5003",
+  INIT1 => X"900a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => RLOS_DB_CNT(0),
+B1 => UN1_RLOS_DB_CNT_ZERO(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_2,
+COUT => RLOS_DB_CNT_CRY_0,
+S0 => RLOS_DB_CNT_CRY_0_0_S0,
+S1 => RLOS_DB_CNT_CRY_0_0_S1);
+\UN1_GENBLK2.RLOS_DB_CNT_CRY_1_0\: CCU2C 
+generic map(
+  INIT0 => X"e101",
+  INIT1 => X"e101",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RLOS_DB_CNT_ZERO(0),
+B0 => RLOS_P2,
+C0 => RLOS_DB_CNT(1),
+D0 => VCC,
+A1 => UN1_RLOS_DB_CNT_ZERO(0),
+B1 => RLOS_P2,
+C1 => RLOS_DB_CNT(2),
+D1 => VCC,
+CIN => RLOS_DB_CNT_CRY_0,
+COUT => RLOS_DB_CNT_CRY_2,
+S0 => RLOS_DB_CNT_CRY_1_0_S0,
+S1 => RLOS_DB_CNT_CRY_1_0_S1);
+\UN1_GENBLK2.RLOS_DB_CNT_S_3_0\: CCU2C 
+generic map(
+  INIT0 => X"a90a",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => RLOS_DB_CNT(3),
+B0 => RLOS_P2,
+C0 => UN1_RLOS_DB_CNT_ZERO(0),
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => RLOS_DB_CNT_CRY_2,
+COUT => RLOS_DB_CNT_S_3_0_COUT,
+S0 => RLOS_DB_CNT_S_3_0_S0,
+S1 => RLOS_DB_CNT_S_3_0_S1);
+\UN1_GENBLK2.RLOL_DB_CNT_CRY_0_0\: CCU2C 
+generic map(
+  INIT0 => X"5003",
+  INIT1 => X"900a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => RLOL_DB_CNT(0),
+B1 => UN1_RLOL_DB_CNT_ZERO(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_1,
+COUT => RLOL_DB_CNT_CRY_0,
+S0 => RLOL_DB_CNT_CRY_0_0_S0,
+S1 => RLOL_DB_CNT_CRY_0_0_S1);
+\UN1_GENBLK2.RLOL_DB_CNT_CRY_1_0\: CCU2C 
+generic map(
+  INIT0 => X"e101",
+  INIT1 => X"e101",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RLOL_DB_CNT_ZERO(0),
+B0 => RLOL_P2,
+C0 => RLOL_DB_CNT(1),
+D0 => VCC,
+A1 => UN1_RLOL_DB_CNT_ZERO(0),
+B1 => RLOL_P2,
+C1 => RLOL_DB_CNT(2),
+D1 => VCC,
+CIN => RLOL_DB_CNT_CRY_0,
+COUT => RLOL_DB_CNT_CRY_2,
+S0 => RLOL_DB_CNT_CRY_1_0_S0,
+S1 => RLOL_DB_CNT_CRY_1_0_S1);
+\UN1_GENBLK2.RLOL_DB_CNT_S_3_0\: CCU2C 
+generic map(
+  INIT0 => X"a90a",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => RLOL_DB_CNT(3),
+B0 => RLOL_P2,
+C0 => UN1_RLOL_DB_CNT_ZERO(0),
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL_DB_CNT_CRY_2,
+COUT => RLOL_DB_CNT_S_3_0_COUT,
+S0 => RLOL_DB_CNT_S_3_0_S0,
+S1 => RLOL_DB_CNT_S_3_0_S1);
+RXSDR_APPD_4 <= RXSDR_APPD;
+TXSR_APPD_4 <= TXSR_APPD;
+VCC_0: VHI port map (
+Z => VCC);
+II_GND: VLO port map (
+Z => GND);
+rsl_rx_pcs_rst_c <= RSL_RX_PCS_RST_C_4;
+rsl_tx_pcs_rst_c <= RSL_TX_PCS_RST_C_5;
+rsl_tx_serdes_rst_c <= RSL_TX_SERDES_RST_C_6;
+rsl_tx_rdy <= RSL_TX_RDY_7;
+rsl_rx_rdy <= RSL_RX_RDY_8;
+rsl_rx_serdes_rst_c <= RSL_RX_SERDES_RST_C_9;
+rsl_serdes_rst_dual_c <= RSL_SERDES_RST_DUAL_C_10;
+end beh;
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library synplify;
+use synplify.components.all;
+library pmi;
+use pmi.pmi_components.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity sgmii_ecp5sll_core_Z1_layer1 is
+port(
+tx_pclk :  in std_logic;
+sli_rst :  in std_logic;
+pll_refclki :  in std_logic;
+pll_lock_i :  out std_logic);
+end sgmii_ecp5sll_core_Z1_layer1;
+
+architecture beh of sgmii_ecp5sll_core_Z1_layer1 is
+signal PHB_CNT : std_logic_vector(2 downto 0);
+signal PHB_CNT_I : std_logic_vector(2 downto 0);
+signal RCOUNT : std_logic_vector(15 downto 0);
+signal PCOUNT : std_logic_vector(21 downto 0);
+signal UN1_PCOUNT_DIFF_I : std_logic_vector(0 to 0);
+signal SLL_STATE : std_logic_vector(1 downto 0);
+signal SLL_STATE_QN : std_logic_vector(1 downto 0);
+signal RHB_WAIT_CNT_S : std_logic_vector(7 downto 0);
+signal RHB_WAIT_CNT : std_logic_vector(7 downto 0);
+signal RHB_WAIT_CNT_QN : std_logic_vector(7 downto 0);
+signal RCOUNT_S : std_logic_vector(15 downto 0);
+signal RCOUNT_QN : std_logic_vector(15 downto 0);
+signal PHB_CNT_QN : std_logic_vector(2 downto 0);
+signal PHB_CNT_RNO : std_logic_vector(2 downto 1);
+signal PCOUNT_S : std_logic_vector(21 downto 0);
+signal PCOUNT_QN : std_logic_vector(21 downto 0);
+signal PCOUNT_DIFF_QN : std_logic_vector(21 downto 0);
+signal RDIFF_COMP_LOCK : std_logic_vector(2 to 2);
+signal RDIFF_COMP_LOCK_QN : std_logic_vector(2 to 2);
+signal UN1_PCOUNT_DIFF : std_logic_vector(0 to 0);
+signal PCOUNT_CRY : std_logic_vector(20 downto 0);
+signal PCOUNT_CRY_0_S0 : std_logic_vector(0 to 0);
+signal PCOUNT_S_0_COUT : std_logic_vector(21 to 21);
+signal PCOUNT_S_0_S1 : std_logic_vector(21 to 21);
+signal RCOUNT_CRY : std_logic_vector(14 downto 0);
+signal RCOUNT_CRY_0_S0 : std_logic_vector(0 to 0);
+signal RCOUNT_S_0_COUT : std_logic_vector(15 to 15);
+signal RCOUNT_S_0_S1 : std_logic_vector(15 to 15);
+signal RHB_WAIT_CNT_CRY : std_logic_vector(6 downto 0);
+signal RHB_WAIT_CNT_CRY_0_S0 : std_logic_vector(0 to 0);
+signal RHB_WAIT_CNT_S_0_COUT : std_logic_vector(7 to 7);
+signal RHB_WAIT_CNT_S_0_S1 : std_logic_vector(7 to 7);
+signal PLL_LOCK : std_logic ;
+signal RTC_CTRL4_0_A3_1 : std_logic ;
+signal UN13_LOCK_20 : std_logic ;
+signal PPUL_SYNC_P2 : std_logic ;
+signal PPUL_SYNC_P1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_20 : std_logic ;
+signal UN13_LOCK_19 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_19 : std_logic ;
+signal UN13_LOCK_18 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_18 : std_logic ;
+signal UN13_LOCK_17 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_17 : std_logic ;
+signal UN13_LOCK_16 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_15_0_RNO_0 : std_logic ;
+signal UN13_LOCK_15 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_15 : std_logic ;
+signal UN13_LOCK_14 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_14 : std_logic ;
+signal UN13_LOCK_13 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_13 : std_logic ;
+signal UN13_LOCK_12 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_12 : std_logic ;
+signal UN13_LOCK_11 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_11 : std_logic ;
+signal UN13_LOCK_10 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_10 : std_logic ;
+signal UN13_LOCK_9 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_9 : std_logic ;
+signal UN13_LOCK_8 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_8 : std_logic ;
+signal UN13_LOCK_7 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_7 : std_logic ;
+signal UN13_LOCK_6 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_6 : std_logic ;
+signal UN13_LOCK_5 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_5 : std_logic ;
+signal UN13_LOCK_4 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_4 : std_logic ;
+signal UN13_LOCK_3 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_3 : std_logic ;
+signal UN13_LOCK_2 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_2 : std_logic ;
+signal UN13_LOCK_1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_1 : std_logic ;
+signal UN13_LOCK_21 : std_logic ;
+signal PPUL_SYNC_P3 : std_logic ;
+signal N_7 : std_logic ;
+signal UN13_LOCK_0 : std_logic ;
+signal RTC_CTRL4 : std_logic ;
+signal RTC_CTRL : std_logic ;
+signal VCC : std_logic ;
+signal N_2121_0 : std_logic ;
+signal UNLOCK_5 : std_logic ;
+signal UNLOCK_1_SQMUXA_I : std_logic ;
+signal UNLOCK : std_logic ;
+signal UNLOCK_QN : std_logic ;
+signal N_95_I : std_logic ;
+signal N_97_I : std_logic ;
+signal RTC_PUL : std_logic ;
+signal RTC_PUL_P1 : std_logic ;
+signal RTC_PUL_P1_QN : std_logic ;
+signal RTC_PUL5 : std_logic ;
+signal RTC_PUL_QN : std_logic ;
+signal RTC_CTRL_QN : std_logic ;
+signal RSTAT_PCLK_2 : std_logic ;
+signal RSTAT_PCLK : std_logic ;
+signal RSTAT_PCLK_QN : std_logic ;
+signal RHB_SYNC_P1 : std_logic ;
+signal RHB_SYNC_P2 : std_logic ;
+signal RHB_SYNC_P2_QN : std_logic ;
+signal RHB_SYNC : std_logic ;
+signal RHB_SYNC_P1_QN : std_logic ;
+signal PPUL_SYNC_P3_QN : std_logic ;
+signal PPUL_SYNC_P2_QN : std_logic ;
+signal PPUL_SYNC : std_logic ;
+signal PPUL_SYNC_P1_QN : std_logic ;
+signal N_53_I : std_logic ;
+signal PLL_LOCK_QN : std_logic ;
+signal PHB : std_logic ;
+signal PHB_QN : std_logic ;
+signal PDIFF_SYNC : std_logic ;
+signal PDIFF_SYNC_P1 : std_logic ;
+signal PDIFF_SYNC_P1_QN : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_1_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_1_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_3_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_3_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_5_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_5_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_7_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_7_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_9_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_9_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_11_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_11_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_13_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_13_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_15_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_15_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_17_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_17_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_19_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_19_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_S_21_0_S0 : std_logic ;
+signal LOCK_5 : std_logic ;
+signal LOCK_1_SQMUXA_I : std_logic ;
+signal LOCK : std_logic ;
+signal LOCK_QN : std_logic ;
+signal N_98 : std_logic ;
+signal RTC_PUL5_0_O3 : std_logic ;
+signal RTC_PUL5_0_A3_6 : std_logic ;
+signal RTC_PUL5_0_A3_7 : std_logic ;
+signal UN1_RCOUNT_1_0_A3 : std_logic ;
+signal RHB_WAIT_CNT12 : std_logic ;
+signal UN1_RHB_WAIT_CNT_4 : std_logic ;
+signal UN1_RHB_WAIT_CNT_5 : std_logic ;
+signal N_99 : std_logic ;
+signal RTC_CTRL4_0_A3_12_4 : std_logic ;
+signal RTC_CTRL4_0_A3_12_5 : std_logic ;
+signal RTC_CTRL4_10 : std_logic ;
+signal UN1_RCOUNT_1_0_A3_1 : std_logic ;
+signal N_6 : std_logic ;
+signal RTC_PUL5_0_A3_5 : std_logic ;
+signal N_8 : std_logic ;
+signal UN13_UNLOCK_CRY_21 : std_logic ;
+signal UN13_LOCK_CRY_21_I : std_logic ;
+signal \RHB_WAIT_CNT_\ : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_0_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_0_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_2 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_4 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_6 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_8 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_10 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_12 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_14 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_16 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_18 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_20 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_S_21_0_COUT : std_logic ;
+signal UN1_PCOUNT_DIFF_1_S_21_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_0 : std_logic ;
+signal UN13_LOCK_CRY_0_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_0_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_2 : std_logic ;
+signal UN13_LOCK_CRY_1_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_1_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_4 : std_logic ;
+signal UN13_LOCK_CRY_3_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_3_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_6 : std_logic ;
+signal UN13_LOCK_CRY_5_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_5_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_8 : std_logic ;
+signal UN13_LOCK_CRY_7_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_7_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_10 : std_logic ;
+signal UN13_LOCK_CRY_9_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_9_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_12 : std_logic ;
+signal UN13_LOCK_CRY_11_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_11_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_14 : std_logic ;
+signal UN13_LOCK_CRY_13_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_13_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_16 : std_logic ;
+signal UN13_LOCK_CRY_15_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_15_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_18 : std_logic ;
+signal UN13_LOCK_CRY_17_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_17_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_20 : std_logic ;
+signal UN13_LOCK_CRY_19_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_19_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_21_0_COUT : std_logic ;
+signal UN13_LOCK_CRY_21_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_0 : std_logic ;
+signal UN13_UNLOCK_CRY_0_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_0_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_2 : std_logic ;
+signal UN13_UNLOCK_CRY_1_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_1_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_4 : std_logic ;
+signal UN13_UNLOCK_CRY_3_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_3_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_6 : std_logic ;
+signal UN13_UNLOCK_CRY_5_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_5_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_8 : std_logic ;
+signal UN13_UNLOCK_CRY_7_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_7_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_10 : std_logic ;
+signal UN13_UNLOCK_CRY_9_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_9_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_12 : std_logic ;
+signal UN13_UNLOCK_CRY_11_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_11_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_14 : std_logic ;
+signal UN13_UNLOCK_CRY_13_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_13_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_16 : std_logic ;
+signal UN13_UNLOCK_CRY_15_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_15_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_18 : std_logic ;
+signal UN13_UNLOCK_CRY_17_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_17_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_20 : std_logic ;
+signal UN13_UNLOCK_CRY_19_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_19_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_21_0_COUT : std_logic ;
+signal UN13_UNLOCK_CRY_21_0_S0 : std_logic ;
+signal N_21 : std_logic ;
+signal N_20 : std_logic ;
+signal N_19 : std_logic ;
+signal N_18 : std_logic ;
+signal N_14 : std_logic ;
+signal GND : std_logic ;
+signal N_1 : std_logic ;
+signal N_2 : std_logic ;
+signal N_3 : std_logic ;
+signal N_4 : std_logic ;
+signal N_5 : std_logic ;
+signal N_9 : std_logic ;
+component sync_0s
+port(
+phb :  in std_logic;
+rhb_sync :  out std_logic;
+sli_rst :  in std_logic;
+pll_refclki :  in std_logic  );
+end component;
+component sync_0s_6
+port(
+rtc_pul :  in std_logic;
+ppul_sync :  out std_logic;
+sli_rst :  in std_logic;
+tx_pclk :  in std_logic  );
+end component;
+component sync_0s_0
+port(
+ppul_sync :  in std_logic;
+pdiff_sync :  out std_logic;
+sli_rst :  in std_logic;
+pll_refclki :  in std_logic  );
+end component;
+begin
+PHB_RNO: INV port map (
+A => PHB_CNT(2),
+Z => PHB_CNT_I(2));
+\PHB_CNT_RNO[0]\: INV port map (
+A => PHB_CNT(0),
+Z => PHB_CNT_I(0));
+PLL_LOCK_RNI6JK9: INV port map (
+A => PLL_LOCK,
+Z => pll_lock_i);
+RTC_CTRL4_0_A3_RNO: LUT4 
+generic map(
+  init => X"2000"
+)
+port map (
+A => RCOUNT(2),
+B => RCOUNT(0),
+C => RCOUNT(5),
+D => RCOUNT(4),
+Z => RTC_CTRL4_0_A3_1);
+UN1_PCOUNT_DIFF_1_CRY_19_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_20,
+B => PCOUNT(20),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_20);
+UN1_PCOUNT_DIFF_1_CRY_19_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_19,
+B => PCOUNT(19),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_19);
+UN1_PCOUNT_DIFF_1_CRY_17_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_18,
+B => PCOUNT(18),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_18);
+UN1_PCOUNT_DIFF_1_CRY_17_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_17,
+B => PCOUNT(17),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_17);
+UN1_PCOUNT_DIFF_1_CRY_15_0_RNO_0_Z478: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_16,
+B => PCOUNT(16),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_CRY_15_0_RNO_0);
+UN1_PCOUNT_DIFF_1_CRY_15_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_15,
+B => PCOUNT(15),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_15);
+UN1_PCOUNT_DIFF_1_CRY_13_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_14,
+B => PCOUNT(14),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_14);
+UN1_PCOUNT_DIFF_1_CRY_13_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_13,
+B => PCOUNT(13),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_13);
+UN1_PCOUNT_DIFF_1_CRY_11_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_12,
+B => PCOUNT(12),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_12);
+UN1_PCOUNT_DIFF_1_CRY_11_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_11,
+B => PCOUNT(11),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_11);
+UN1_PCOUNT_DIFF_1_CRY_9_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_10,
+B => PCOUNT(10),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_10);
+UN1_PCOUNT_DIFF_1_CRY_9_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_9,
+B => PCOUNT(9),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_9);
+UN1_PCOUNT_DIFF_1_CRY_7_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_8,
+B => PCOUNT(8),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_8);
+UN1_PCOUNT_DIFF_1_CRY_7_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_7,
+B => PCOUNT(7),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_7);
+UN1_PCOUNT_DIFF_1_CRY_5_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_6,
+B => PCOUNT(6),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_6);
+UN1_PCOUNT_DIFF_1_CRY_5_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_5,
+B => PCOUNT(5),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_5);
+UN1_PCOUNT_DIFF_1_CRY_3_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_4,
+B => PCOUNT(4),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_4);
+UN1_PCOUNT_DIFF_1_CRY_3_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_3,
+B => PCOUNT(3),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_3);
+UN1_PCOUNT_DIFF_1_CRY_1_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_2,
+B => PCOUNT(2),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_2);
+UN1_PCOUNT_DIFF_1_CRY_1_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_1,
+B => PCOUNT(1),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_1);
+PPUL_SYNC_P3_RNIU65C: LUT4 
+generic map(
+  init => X"2F20"
+)
+port map (
+A => UN13_LOCK_21,
+B => PPUL_SYNC_P3,
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => N_7);
+\PCOUNT_DIFF_RNO[0]\: LUT4 
+generic map(
+  init => X"FD20"
+)
+port map (
+A => PPUL_SYNC_P1,
+B => PPUL_SYNC_P2,
+C => PCOUNT(0),
+D => UN13_LOCK_0,
+Z => UN1_PCOUNT_DIFF_I(0));
+RTC_CTRL_0: LUT4 
+generic map(
+  init => X"EEEE"
+)
+port map (
+A => RTC_CTRL4,
+B => RTC_CTRL,
+C => VCC,
+D => VCC,
+Z => N_2121_0);
+UNLOCK_REG_Z498: FD1P3DX port map (
+D => UNLOCK_5,
+SP => UNLOCK_1_SQMUXA_I,
+CK => pll_refclki,
+CD => sli_rst,
+Q => UNLOCK);
+\SLL_STATE[0]_REG_Z500\: FD1S3DX port map (
+D => N_95_I,
+CK => pll_refclki,
+CD => sli_rst,
+Q => SLL_STATE(0));
+\SLL_STATE[1]_REG_Z502\: FD1S3DX port map (
+D => N_97_I,
+CK => pll_refclki,
+CD => sli_rst,
+Q => SLL_STATE(1));
+RTC_PUL_P1_REG_Z504: FD1S3DX port map (
+D => RTC_PUL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RTC_PUL_P1);
+RTC_PUL_REG_Z506: FD1P3DX port map (
+D => RTC_PUL5,
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RTC_PUL);
+RTC_CTRL_REG_Z508: FD1S3DX port map (
+D => N_2121_0,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RTC_CTRL);
+RSTAT_PCLK_REG_Z510: FD1P3DX port map (
+D => RSTAT_PCLK_2,
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RSTAT_PCLK);
+\RHB_WAIT_CNT[0]_REG_Z512\: FD1P3DX port map (
+D => RHB_WAIT_CNT_S(0),
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_WAIT_CNT(0));
+\RHB_WAIT_CNT[1]_REG_Z514\: FD1P3DX port map (
+D => RHB_WAIT_CNT_S(1),
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_WAIT_CNT(1));
+\RHB_WAIT_CNT[2]_REG_Z516\: FD1P3DX port map (
+D => RHB_WAIT_CNT_S(2),
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_WAIT_CNT(2));
+\RHB_WAIT_CNT[3]_REG_Z518\: FD1P3DX port map (
+D => RHB_WAIT_CNT_S(3),
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_WAIT_CNT(3));
+\RHB_WAIT_CNT[4]_REG_Z520\: FD1P3DX port map (
+D => RHB_WAIT_CNT_S(4),
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_WAIT_CNT(4));
+\RHB_WAIT_CNT[5]_REG_Z522\: FD1P3DX port map (
+D => RHB_WAIT_CNT_S(5),
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_WAIT_CNT(5));
+\RHB_WAIT_CNT[6]_REG_Z524\: FD1P3DX port map (
+D => RHB_WAIT_CNT_S(6),
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_WAIT_CNT(6));
+\RHB_WAIT_CNT[7]_REG_Z526\: FD1P3DX port map (
+D => RHB_WAIT_CNT_S(7),
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_WAIT_CNT(7));
+RHB_SYNC_P2_REG_Z528: FD1S3DX port map (
+D => RHB_SYNC_P1,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_SYNC_P2);
+RHB_SYNC_P1_REG_Z530: FD1S3DX port map (
+D => RHB_SYNC,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_SYNC_P1);
+\RCOUNT[0]_REG_Z532\: FD1S3DX port map (
+D => RCOUNT_S(0),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(0));
+\RCOUNT[1]_REG_Z534\: FD1S3DX port map (
+D => RCOUNT_S(1),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(1));
+\RCOUNT[2]_REG_Z536\: FD1S3DX port map (
+D => RCOUNT_S(2),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(2));
+\RCOUNT[3]_REG_Z538\: FD1S3DX port map (
+D => RCOUNT_S(3),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(3));
+\RCOUNT[4]_REG_Z540\: FD1S3DX port map (
+D => RCOUNT_S(4),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(4));
+\RCOUNT[5]_REG_Z542\: FD1S3DX port map (
+D => RCOUNT_S(5),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(5));
+\RCOUNT[6]_REG_Z544\: FD1S3DX port map (
+D => RCOUNT_S(6),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(6));
+\RCOUNT[7]_REG_Z546\: FD1S3DX port map (
+D => RCOUNT_S(7),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(7));
+\RCOUNT[8]_REG_Z548\: FD1S3DX port map (
+D => RCOUNT_S(8),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(8));
+\RCOUNT[9]_REG_Z550\: FD1S3DX port map (
+D => RCOUNT_S(9),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(9));
+\RCOUNT[10]_REG_Z552\: FD1S3DX port map (
+D => RCOUNT_S(10),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(10));
+\RCOUNT[11]_REG_Z554\: FD1S3DX port map (
+D => RCOUNT_S(11),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(11));
+\RCOUNT[12]_REG_Z556\: FD1S3DX port map (
+D => RCOUNT_S(12),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(12));
+\RCOUNT[13]_REG_Z558\: FD1S3DX port map (
+D => RCOUNT_S(13),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(13));
+\RCOUNT[14]_REG_Z560\: FD1S3DX port map (
+D => RCOUNT_S(14),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(14));
+\RCOUNT[15]_REG_Z562\: FD1S3DX port map (
+D => RCOUNT_S(15),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(15));
+PPUL_SYNC_P3_REG_Z564: FD1S3DX port map (
+D => PPUL_SYNC_P2,
+CK => tx_pclk,
+CD => sli_rst,
+Q => PPUL_SYNC_P3);
+PPUL_SYNC_P2_REG_Z566: FD1S3DX port map (
+D => PPUL_SYNC_P1,
+CK => tx_pclk,
+CD => sli_rst,
+Q => PPUL_SYNC_P2);
+PPUL_SYNC_P1_REG_Z568: FD1S3DX port map (
+D => PPUL_SYNC,
+CK => tx_pclk,
+CD => sli_rst,
+Q => PPUL_SYNC_P1);
+PLL_LOCK_REG_Z570: FD1S3DX port map (
+D => N_53_I,
+CK => pll_refclki,
+CD => sli_rst,
+Q => PLL_LOCK);
+\PHB_CNT[0]_REG_Z572\: FD1S3DX port map (
+D => PHB_CNT_I(0),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PHB_CNT(0));
+\PHB_CNT[1]_REG_Z574\: FD1S3DX port map (
+D => PHB_CNT_RNO(1),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PHB_CNT(1));
+\PHB_CNT[2]_REG_Z576\: FD1S3DX port map (
+D => PHB_CNT_RNO(2),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PHB_CNT(2));
+PHB_REG_Z578: FD1S3DX port map (
+D => PHB_CNT_I(2),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PHB);
+PDIFF_SYNC_P1_REG_Z580: FD1S3DX port map (
+D => PDIFF_SYNC,
+CK => pll_refclki,
+CD => sli_rst,
+Q => PDIFF_SYNC_P1);
+\PCOUNT[0]_REG_Z582\: FD1S3DX port map (
+D => PCOUNT_S(0),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(0));
+\PCOUNT_DIFF[0]_REG_Z584\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_I(0),
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_0);
+\PCOUNT[1]_REG_Z586\: FD1S3DX port map (
+D => PCOUNT_S(1),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(1));
+\PCOUNT_DIFF[1]_REG_Z588\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_1_0_S0,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_1);
+\PCOUNT_DIFF[2]_REG_Z590\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_1_0_S1,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_2);
+\PCOUNT[2]_REG_Z592\: FD1S3DX port map (
+D => PCOUNT_S(2),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(2));
+\PCOUNT_DIFF[3]_REG_Z594\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_3_0_S0,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_3);
+\PCOUNT[3]_REG_Z596\: FD1S3DX port map (
+D => PCOUNT_S(3),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(3));
+\PCOUNT_DIFF[4]_REG_Z598\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_3_0_S1,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_4);
+\PCOUNT[4]_REG_Z600\: FD1S3DX port map (
+D => PCOUNT_S(4),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(4));
+\PCOUNT_DIFF[5]_REG_Z602\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_5_0_S0,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_5);
+\PCOUNT[5]_REG_Z604\: FD1S3DX port map (
+D => PCOUNT_S(5),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(5));
+\PCOUNT[6]_REG_Z606\: FD1S3DX port map (
+D => PCOUNT_S(6),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(6));
+\PCOUNT_DIFF[6]_REG_Z608\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_5_0_S1,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_6);
+\PCOUNT[7]_REG_Z610\: FD1S3DX port map (
+D => PCOUNT_S(7),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(7));
+\PCOUNT_DIFF[7]_REG_Z612\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_7_0_S0,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_7);
+\PCOUNT[8]_REG_Z614\: FD1S3DX port map (
+D => PCOUNT_S(8),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(8));
+\PCOUNT_DIFF[8]_REG_Z616\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_7_0_S1,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_8);
+\PCOUNT_DIFF[9]_REG_Z618\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_9_0_S0,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_9);
+\PCOUNT[9]_REG_Z620\: FD1S3DX port map (
+D => PCOUNT_S(9),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(9));
+\PCOUNT[10]_REG_Z622\: FD1S3DX port map (
+D => PCOUNT_S(10),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(10));
+\PCOUNT_DIFF[10]_REG_Z624\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_9_0_S1,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_10);
+\PCOUNT_DIFF[11]_REG_Z626\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_11_0_S0,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_11);
+\PCOUNT[11]_REG_Z628\: FD1S3DX port map (
+D => PCOUNT_S(11),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(11));
+\PCOUNT[12]_REG_Z630\: FD1S3DX port map (
+D => PCOUNT_S(12),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(12));
+\PCOUNT_DIFF[12]_REG_Z632\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_11_0_S1,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_12);
+\PCOUNT_DIFF[13]_REG_Z634\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_13_0_S0,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_13);
+\PCOUNT[13]_REG_Z636\: FD1S3DX port map (
+D => PCOUNT_S(13),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(13));
+\PCOUNT_DIFF[14]_REG_Z638\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_13_0_S1,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_14);
+\PCOUNT[14]_REG_Z640\: FD1S3DX port map (
+D => PCOUNT_S(14),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(14));
+\PCOUNT[15]_REG_Z642\: FD1S3DX port map (
+D => PCOUNT_S(15),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(15));
+\PCOUNT_DIFF[15]_REG_Z644\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_15_0_S0,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_15);
+\PCOUNT[16]_REG_Z646\: FD1S3DX port map (
+D => PCOUNT_S(16),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(16));
+\PCOUNT_DIFF[16]_REG_Z648\: FD1P3DX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_15_0_S1,
+SP => N_7,
+CK => tx_pclk,
+CD => sli_rst,
+Q => UN13_LOCK_16);
+\PCOUNT_DIFF[17]_REG_Z650\: FD1P3DX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_17_0_S0,
+SP => N_7,
+CK => tx_pclk,
+CD => sli_rst,
+Q => UN13_LOCK_17);
+\PCOUNT[17]_REG_Z652\: FD1S3DX port map (
+D => PCOUNT_S(17),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(17));
+\PCOUNT_DIFF[18]_REG_Z654\: FD1P3DX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_17_0_S1,
+SP => N_7,
+CK => tx_pclk,
+CD => sli_rst,
+Q => UN13_LOCK_18);
+\PCOUNT[18]_REG_Z656\: FD1S3DX port map (
+D => PCOUNT_S(18),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(18));
+\PCOUNT[19]_REG_Z658\: FD1S3DX port map (
+D => PCOUNT_S(19),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(19));
+\PCOUNT_DIFF[19]_REG_Z660\: FD1P3DX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_19_0_S0,
+SP => N_7,
+CK => tx_pclk,
+CD => sli_rst,
+Q => UN13_LOCK_19);
+\PCOUNT[20]_REG_Z662\: FD1S3DX port map (
+D => PCOUNT_S(20),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(20));
+\PCOUNT_DIFF[20]_REG_Z664\: FD1P3DX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_19_0_S1,
+SP => N_7,
+CK => tx_pclk,
+CD => sli_rst,
+Q => UN13_LOCK_20);
+\PCOUNT_DIFF[21]_REG_Z666\: FD1P3DX port map (
+D => UN1_PCOUNT_DIFF_1_S_21_0_S0,
+SP => N_7,
+CK => tx_pclk,
+CD => sli_rst,
+Q => UN13_LOCK_21);
+\PCOUNT[21]_REG_Z668\: FD1S3DX port map (
+D => PCOUNT_S(21),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(21));
+LOCK_REG_Z670: FD1P3DX port map (
+D => LOCK_5,
+SP => LOCK_1_SQMUXA_I,
+CK => pll_refclki,
+CD => sli_rst,
+Q => LOCK);
+\GENBLK5.RDIFF_COMP_LOCK[2]_REG_Z672\: FD1S3DX port map (
+D => VCC,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RDIFF_COMP_LOCK(2));
+\SLL_STATE_RNO[0]\: LUT4 
+generic map(
+  init => X"E050"
+)
+port map (
+A => N_98,
+B => LOCK,
+C => RSTAT_PCLK,
+D => SLL_STATE(0),
+Z => N_95_I);
+RTC_PUL5_0_0: LUT4 
+generic map(
+  init => X"FF80"
+)
+port map (
+A => RTC_PUL5_0_O3,
+B => RTC_PUL5_0_A3_6,
+C => RTC_PUL5_0_A3_7,
+D => UN1_RCOUNT_1_0_A3,
+Z => RTC_PUL5);
+RSTAT_PCLK_2_IV: LUT4 
+generic map(
+  init => X"AEEE"
+)
+port map (
+A => RHB_WAIT_CNT12,
+B => RSTAT_PCLK,
+C => UN1_RHB_WAIT_CNT_4,
+D => UN1_RHB_WAIT_CNT_5,
+Z => RSTAT_PCLK_2);
+\SLL_STATE_RNO[1]\: LUT4 
+generic map(
+  init => X"8088"
+)
+port map (
+A => N_99,
+B => RSTAT_PCLK,
+C => SLL_STATE(1),
+D => UNLOCK,
+Z => N_97_I);
+RTC_CTRL4_0_A3: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RTC_CTRL4_0_A3_1,
+B => RTC_CTRL4_0_A3_12_4,
+C => RTC_CTRL4_0_A3_12_5,
+D => RTC_CTRL4_10,
+Z => RTC_CTRL4);
+UN1_RCOUNT_1_0_A3_Z678: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RTC_CTRL4_0_A3_12_4,
+B => RTC_CTRL4_0_A3_12_5,
+C => RTC_CTRL4_10,
+D => UN1_RCOUNT_1_0_A3_1,
+Z => UN1_RCOUNT_1_0_A3);
+LOCK_1_SQMUXA_I_Z679: LUT4 
+generic map(
+  init => X"7575"
+)
+port map (
+A => LOCK,
+B => PDIFF_SYNC,
+C => PDIFF_SYNC_P1,
+D => VCC,
+Z => LOCK_1_SQMUXA_I);
+UNLOCK_1_SQMUXA_I_Z680: LUT4 
+generic map(
+  init => X"4F4F"
+)
+port map (
+A => PDIFF_SYNC,
+B => PDIFF_SYNC_P1,
+C => UNLOCK,
+D => VCC,
+Z => UNLOCK_1_SQMUXA_I);
+RTC_PUL5_0_O3_Z681: LUT4 
+generic map(
+  init => X"AAAB"
+)
+port map (
+A => N_6,
+B => RCOUNT(1),
+C => RCOUNT(2),
+D => RCOUNT(3),
+Z => RTC_PUL5_0_O3);
+RTC_PUL5_0_A3_7_Z682: LUT4 
+generic map(
+  init => X"1010"
+)
+port map (
+A => RCOUNT(7),
+B => RCOUNT(8),
+C => RTC_PUL5_0_A3_5,
+D => VCC,
+Z => RTC_PUL5_0_A3_7);
+\SLL_STATE_NS_I_M4[1]\: LUT4 
+generic map(
+  init => X"EF20"
+)
+port map (
+A => LOCK,
+B => RTC_PUL,
+C => RTC_PUL_P1,
+D => SLL_STATE(1),
+Z => N_99);
+PLL_LOCK_RNO: LUT4 
+generic map(
+  init => X"8888"
+)
+port map (
+A => SLL_STATE(0),
+B => SLL_STATE(1),
+C => VCC,
+D => VCC,
+Z => N_53_I);
+\PHB_CNT_RNO[2]_Z685\: LUT4 
+generic map(
+  init => X"7878"
+)
+port map (
+A => PHB_CNT(0),
+B => PHB_CNT(1),
+C => PHB_CNT(2),
+D => VCC,
+Z => PHB_CNT_RNO(2));
+\SLL_STATE_NS_I_O4[0]\: LUT4 
+generic map(
+  init => X"BFBF"
+)
+port map (
+A => RTC_PUL,
+B => RTC_PUL_P1,
+C => SLL_STATE(1),
+D => VCC,
+Z => N_98);
+RTC_CTRL4_0_A3_10: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RCOUNT(1),
+B => RCOUNT(3),
+C => RCOUNT(6),
+D => RCOUNT(15),
+Z => RTC_CTRL4_10);
+UN1_RHB_WAIT_CNT_4_Z688: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RHB_WAIT_CNT(4),
+B => RHB_WAIT_CNT(5),
+C => RHB_WAIT_CNT(6),
+D => RHB_WAIT_CNT(7),
+Z => UN1_RHB_WAIT_CNT_4);
+UN1_RHB_WAIT_CNT_5_Z689: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RHB_WAIT_CNT(0),
+B => RHB_WAIT_CNT(1),
+C => RHB_WAIT_CNT(2),
+D => RHB_WAIT_CNT(3),
+Z => UN1_RHB_WAIT_CNT_5);
+RTC_CTRL4_0_A3_12_4_Z690: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RCOUNT(11),
+B => RCOUNT(12),
+C => RCOUNT(13),
+D => RCOUNT(14),
+Z => RTC_CTRL4_0_A3_12_4);
+RTC_CTRL4_0_A3_12_5_Z691: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RCOUNT(7),
+B => RCOUNT(8),
+C => RCOUNT(9),
+D => RCOUNT(10),
+Z => RTC_CTRL4_0_A3_12_5);
+RTC_PUL5_0_A3_5_Z692: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RCOUNT(6),
+B => RCOUNT(13),
+C => RCOUNT(14),
+D => RCOUNT(15),
+Z => RTC_PUL5_0_A3_5);
+RTC_PUL5_0_A3_6_Z693: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RCOUNT(9),
+B => RCOUNT(10),
+C => RCOUNT(11),
+D => RCOUNT(12),
+Z => RTC_PUL5_0_A3_6);
+PCOUNT10_0_O3: LUT4 
+generic map(
+  init => X"DDDD"
+)
+port map (
+A => PPUL_SYNC_P1,
+B => PPUL_SYNC_P2,
+C => VCC,
+D => VCC,
+Z => N_8);
+\PHB_CNT_RNO[1]_Z695\: LUT4 
+generic map(
+  init => X"6666"
+)
+port map (
+A => PHB_CNT(0),
+B => PHB_CNT(1),
+C => VCC,
+D => VCC,
+Z => PHB_CNT_RNO(1));
+RTC_CTRL4_0_O3: LUT4 
+generic map(
+  init => X"7777"
+)
+port map (
+A => RCOUNT(4),
+B => RCOUNT(5),
+C => VCC,
+D => VCC,
+Z => N_6);
+UNLOCK_5_Z697: LUT4 
+generic map(
+  init => X"8888"
+)
+port map (
+A => PDIFF_SYNC,
+B => UN13_UNLOCK_CRY_21,
+C => VCC,
+D => VCC,
+Z => UNLOCK_5);
+LOCK_5_Z698: LUT4 
+generic map(
+  init => X"8888"
+)
+port map (
+A => PDIFF_SYNC,
+B => UN13_LOCK_CRY_21_I,
+C => VCC,
+D => VCC,
+Z => LOCK_5);
+RHB_WAIT_CNT12_Z699: LUT4 
+generic map(
+  init => X"2222"
+)
+port map (
+A => RHB_SYNC_P1,
+B => RHB_SYNC_P2,
+C => VCC,
+D => VCC,
+Z => RHB_WAIT_CNT12);
+\UN1_PCOUNT_DIFF[0]_Z700\: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_0,
+B => PCOUNT(0),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF(0));
+UN1_RCOUNT_1_0_A3_1_Z701: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RCOUNT(2),
+B => RCOUNT(0),
+C => RCOUNT(5),
+D => RCOUNT(4),
+Z => UN1_RCOUNT_1_0_A3_1);
+RHB_SYNC_P2_RNIU9TG1: LUT4 
+generic map(
+  init => X"7077"
+)
+port map (
+A => UN1_RHB_WAIT_CNT_5,
+B => UN1_RHB_WAIT_CNT_4,
+C => RHB_SYNC_P2,
+D => RHB_SYNC_P1,
+Z => \RHB_WAIT_CNT_\);
+\PCOUNT_CRY_0[0]\: CCU2C 
+generic map(
+  INIT0 => X"500c",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => N_8,
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_9,
+COUT => PCOUNT_CRY(0),
+S0 => PCOUNT_CRY_0_S0(0),
+S1 => PCOUNT_S(0));
+\PCOUNT_CRY_0[1]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(1),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(2),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(0),
+COUT => PCOUNT_CRY(2),
+S0 => PCOUNT_S(1),
+S1 => PCOUNT_S(2));
+\PCOUNT_CRY_0[3]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(3),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(4),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(2),
+COUT => PCOUNT_CRY(4),
+S0 => PCOUNT_S(3),
+S1 => PCOUNT_S(4));
+\PCOUNT_CRY_0[5]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(5),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(6),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(4),
+COUT => PCOUNT_CRY(6),
+S0 => PCOUNT_S(5),
+S1 => PCOUNT_S(6));
+\PCOUNT_CRY_0[7]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(7),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(8),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(6),
+COUT => PCOUNT_CRY(8),
+S0 => PCOUNT_S(7),
+S1 => PCOUNT_S(8));
+\PCOUNT_CRY_0[9]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(9),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(10),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(8),
+COUT => PCOUNT_CRY(10),
+S0 => PCOUNT_S(9),
+S1 => PCOUNT_S(10));
+\PCOUNT_CRY_0[11]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(11),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(12),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(10),
+COUT => PCOUNT_CRY(12),
+S0 => PCOUNT_S(11),
+S1 => PCOUNT_S(12));
+\PCOUNT_CRY_0[13]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(13),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(14),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(12),
+COUT => PCOUNT_CRY(14),
+S0 => PCOUNT_S(13),
+S1 => PCOUNT_S(14));
+\PCOUNT_CRY_0[15]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(15),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(16),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(14),
+COUT => PCOUNT_CRY(16),
+S0 => PCOUNT_S(15),
+S1 => PCOUNT_S(16));
+\PCOUNT_CRY_0[17]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(17),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(18),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(16),
+COUT => PCOUNT_CRY(18),
+S0 => PCOUNT_S(17),
+S1 => PCOUNT_S(18));
+\PCOUNT_CRY_0[19]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(19),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(20),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(18),
+COUT => PCOUNT_CRY(20),
+S0 => PCOUNT_S(19),
+S1 => PCOUNT_S(20));
+\PCOUNT_S_0[21]\: CCU2C 
+generic map(
+  INIT0 => X"800a",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(21),
+C0 => VCC,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(20),
+COUT => PCOUNT_S_0_COUT(21),
+S0 => PCOUNT_S(21),
+S1 => PCOUNT_S_0_S1(21));
+\RCOUNT_CRY_0[0]\: CCU2C 
+generic map(
+  INIT0 => X"5003",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => UN1_RCOUNT_1_0_A3,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_RCOUNT_1_0_A3,
+B1 => RCOUNT(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_5,
+COUT => RCOUNT_CRY(0),
+S0 => RCOUNT_CRY_0_S0(0),
+S1 => RCOUNT_S(0));
+\RCOUNT_CRY_0[1]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RCOUNT_1_0_A3,
+B0 => RCOUNT(1),
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_RCOUNT_1_0_A3,
+B1 => RCOUNT(2),
+C1 => VCC,
+D1 => VCC,
+CIN => RCOUNT_CRY(0),
+COUT => RCOUNT_CRY(2),
+S0 => RCOUNT_S(1),
+S1 => RCOUNT_S(2));
+\RCOUNT_CRY_0[3]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RCOUNT_1_0_A3,
+B0 => RCOUNT(3),
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_RCOUNT_1_0_A3,
+B1 => RCOUNT(4),
+C1 => VCC,
+D1 => VCC,
+CIN => RCOUNT_CRY(2),
+COUT => RCOUNT_CRY(4),
+S0 => RCOUNT_S(3),
+S1 => RCOUNT_S(4));
+\RCOUNT_CRY_0[5]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RCOUNT_1_0_A3,
+B0 => RCOUNT(5),
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_RCOUNT_1_0_A3,
+B1 => RCOUNT(6),
+C1 => VCC,
+D1 => VCC,
+CIN => RCOUNT_CRY(4),
+COUT => RCOUNT_CRY(6),
+S0 => RCOUNT_S(5),
+S1 => RCOUNT_S(6));
+\RCOUNT_CRY_0[7]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RCOUNT_1_0_A3,
+B0 => RCOUNT(7),
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_RCOUNT_1_0_A3,
+B1 => RCOUNT(8),
+C1 => VCC,
+D1 => VCC,
+CIN => RCOUNT_CRY(6),
+COUT => RCOUNT_CRY(8),
+S0 => RCOUNT_S(7),
+S1 => RCOUNT_S(8));
+\RCOUNT_CRY_0[9]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RCOUNT_1_0_A3,
+B0 => RCOUNT(9),
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_RCOUNT_1_0_A3,
+B1 => RCOUNT(10),
+C1 => VCC,
+D1 => VCC,
+CIN => RCOUNT_CRY(8),
+COUT => RCOUNT_CRY(10),
+S0 => RCOUNT_S(9),
+S1 => RCOUNT_S(10));
+\RCOUNT_CRY_0[11]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RCOUNT_1_0_A3,
+B0 => RCOUNT(11),
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_RCOUNT_1_0_A3,
+B1 => RCOUNT(12),
+C1 => VCC,
+D1 => VCC,
+CIN => RCOUNT_CRY(10),
+COUT => RCOUNT_CRY(12),
+S0 => RCOUNT_S(11),
+S1 => RCOUNT_S(12));
+\RCOUNT_CRY_0[13]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RCOUNT_1_0_A3,
+B0 => RCOUNT(13),
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_RCOUNT_1_0_A3,
+B1 => RCOUNT(14),
+C1 => VCC,
+D1 => VCC,
+CIN => RCOUNT_CRY(12),
+COUT => RCOUNT_CRY(14),
+S0 => RCOUNT_S(13),
+S1 => RCOUNT_S(14));
+\RCOUNT_S_0[15]\: CCU2C 
+generic map(
+  INIT0 => X"4005",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RCOUNT_1_0_A3,
+B0 => RCOUNT(15),
+C0 => VCC,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => RCOUNT_CRY(14),
+COUT => RCOUNT_S_0_COUT(15),
+S0 => RCOUNT_S(15),
+S1 => RCOUNT_S_0_S1(15));
+\RHB_WAIT_CNT_CRY_0[0]\: CCU2C 
+generic map(
+  INIT0 => X"500c",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => \RHB_WAIT_CNT_\,
+C0 => VCC,
+D0 => VCC,
+A1 => \RHB_WAIT_CNT_\,
+B1 => RHB_WAIT_CNT(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_4,
+COUT => RHB_WAIT_CNT_CRY(0),
+S0 => RHB_WAIT_CNT_CRY_0_S0(0),
+S1 => RHB_WAIT_CNT_S(0));
+\RHB_WAIT_CNT_CRY_0[1]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RHB_WAIT_CNT_\,
+B0 => RHB_WAIT_CNT(1),
+C0 => VCC,
+D0 => VCC,
+A1 => \RHB_WAIT_CNT_\,
+B1 => RHB_WAIT_CNT(2),
+C1 => VCC,
+D1 => VCC,
+CIN => RHB_WAIT_CNT_CRY(0),
+COUT => RHB_WAIT_CNT_CRY(2),
+S0 => RHB_WAIT_CNT_S(1),
+S1 => RHB_WAIT_CNT_S(2));
+\RHB_WAIT_CNT_CRY_0[3]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RHB_WAIT_CNT_\,
+B0 => RHB_WAIT_CNT(3),
+C0 => VCC,
+D0 => VCC,
+A1 => \RHB_WAIT_CNT_\,
+B1 => RHB_WAIT_CNT(4),
+C1 => VCC,
+D1 => VCC,
+CIN => RHB_WAIT_CNT_CRY(2),
+COUT => RHB_WAIT_CNT_CRY(4),
+S0 => RHB_WAIT_CNT_S(3),
+S1 => RHB_WAIT_CNT_S(4));
+\RHB_WAIT_CNT_CRY_0[5]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RHB_WAIT_CNT_\,
+B0 => RHB_WAIT_CNT(5),
+C0 => VCC,
+D0 => VCC,
+A1 => \RHB_WAIT_CNT_\,
+B1 => RHB_WAIT_CNT(6),
+C1 => VCC,
+D1 => VCC,
+CIN => RHB_WAIT_CNT_CRY(4),
+COUT => RHB_WAIT_CNT_CRY(6),
+S0 => RHB_WAIT_CNT_S(5),
+S1 => RHB_WAIT_CNT_S(6));
+\RHB_WAIT_CNT_S_0[7]\: CCU2C 
+generic map(
+  INIT0 => X"800a",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RHB_WAIT_CNT_\,
+B0 => RHB_WAIT_CNT(7),
+C0 => VCC,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => RHB_WAIT_CNT_CRY(6),
+COUT => RHB_WAIT_CNT_S_0_COUT(7),
+S0 => RHB_WAIT_CNT_S(7),
+S1 => RHB_WAIT_CNT_S_0_S1(7));
+UN1_PCOUNT_DIFF_1_CRY_0_0: CCU2C 
+generic map(
+  INIT0 => X"5003",
+  INIT1 => X"500f",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF(0),
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => N_3,
+COUT => UN1_PCOUNT_DIFF_1_CRY_0,
+S0 => UN1_PCOUNT_DIFF_1_CRY_0_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_0_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_1_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_1,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_2,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_0,
+COUT => UN1_PCOUNT_DIFF_1_CRY_2,
+S0 => UN1_PCOUNT_DIFF_1_CRY_1_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_1_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_3_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_3,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_4,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_2,
+COUT => UN1_PCOUNT_DIFF_1_CRY_4,
+S0 => UN1_PCOUNT_DIFF_1_CRY_3_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_3_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_5_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_5,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_6,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_4,
+COUT => UN1_PCOUNT_DIFF_1_CRY_6,
+S0 => UN1_PCOUNT_DIFF_1_CRY_5_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_5_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_7_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_7,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_8,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_6,
+COUT => UN1_PCOUNT_DIFF_1_CRY_8,
+S0 => UN1_PCOUNT_DIFF_1_CRY_7_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_7_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_9_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_9,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_10,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_8,
+COUT => UN1_PCOUNT_DIFF_1_CRY_10,
+S0 => UN1_PCOUNT_DIFF_1_CRY_9_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_9_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_11_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_11,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_12,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_10,
+COUT => UN1_PCOUNT_DIFF_1_CRY_12,
+S0 => UN1_PCOUNT_DIFF_1_CRY_11_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_11_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_13_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_13,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_14,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_12,
+COUT => UN1_PCOUNT_DIFF_1_CRY_14,
+S0 => UN1_PCOUNT_DIFF_1_CRY_13_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_13_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_15_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"b404",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_15,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => RDIFF_COMP_LOCK(2),
+C1 => UN1_PCOUNT_DIFF_1_CRY_15_0_RNO_0,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_14,
+COUT => UN1_PCOUNT_DIFF_1_CRY_16,
+S0 => UN1_PCOUNT_DIFF_1_CRY_15_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_15_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_17_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_17,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_18,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_16,
+COUT => UN1_PCOUNT_DIFF_1_CRY_18,
+S0 => UN1_PCOUNT_DIFF_1_CRY_17_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_17_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_19_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_19,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_20,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_18,
+COUT => UN1_PCOUNT_DIFF_1_CRY_20,
+S0 => UN1_PCOUNT_DIFF_1_CRY_19_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_19_0_S1);
+UN1_PCOUNT_DIFF_1_S_21_0: CCU2C 
+generic map(
+  INIT0 => X"350a",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => PCOUNT(21),
+B0 => UN13_LOCK_21,
+C0 => N_8,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_20,
+COUT => UN1_PCOUNT_DIFF_1_S_21_0_COUT,
+S0 => UN1_PCOUNT_DIFF_1_S_21_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_S_21_0_S1);
+UN13_LOCK_CRY_0_0: CCU2C 
+generic map(
+  INIT0 => X"5003",
+  INIT1 => X"900a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_0,
+B1 => RDIFF_COMP_LOCK(2),
+C1 => VCC,
+D1 => VCC,
+CIN => N_2,
+COUT => UN13_LOCK_CRY_0,
+S0 => UN13_LOCK_CRY_0_0_S0,
+S1 => UN13_LOCK_CRY_0_0_S1);
+UN13_LOCK_CRY_1_0: CCU2C 
+generic map(
+  INIT0 => X"900a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_1,
+B0 => RDIFF_COMP_LOCK(2),
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_2,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_0,
+COUT => UN13_LOCK_CRY_2,
+S0 => UN13_LOCK_CRY_1_0_S0,
+S1 => UN13_LOCK_CRY_1_0_S1);
+UN13_LOCK_CRY_3_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"900a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_3,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_4,
+B1 => RDIFF_COMP_LOCK(2),
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_2,
+COUT => UN13_LOCK_CRY_4,
+S0 => UN13_LOCK_CRY_3_0_S0,
+S1 => UN13_LOCK_CRY_3_0_S1);
+UN13_LOCK_CRY_5_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_5,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_6,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_4,
+COUT => UN13_LOCK_CRY_6,
+S0 => UN13_LOCK_CRY_5_0_S0,
+S1 => UN13_LOCK_CRY_5_0_S1);
+UN13_LOCK_CRY_7_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_7,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_8,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_6,
+COUT => UN13_LOCK_CRY_8,
+S0 => UN13_LOCK_CRY_7_0_S0,
+S1 => UN13_LOCK_CRY_7_0_S1);
+UN13_LOCK_CRY_9_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_9,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_10,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_8,
+COUT => UN13_LOCK_CRY_10,
+S0 => UN13_LOCK_CRY_9_0_S0,
+S1 => UN13_LOCK_CRY_9_0_S1);
+UN13_LOCK_CRY_11_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_11,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_12,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_10,
+COUT => UN13_LOCK_CRY_12,
+S0 => UN13_LOCK_CRY_11_0_S0,
+S1 => UN13_LOCK_CRY_11_0_S1);
+UN13_LOCK_CRY_13_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_13,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_14,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_12,
+COUT => UN13_LOCK_CRY_14,
+S0 => UN13_LOCK_CRY_13_0_S0,
+S1 => UN13_LOCK_CRY_13_0_S1);
+UN13_LOCK_CRY_15_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_15,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_16,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_14,
+COUT => UN13_LOCK_CRY_16,
+S0 => UN13_LOCK_CRY_15_0_S0,
+S1 => UN13_LOCK_CRY_15_0_S1);
+UN13_LOCK_CRY_17_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_17,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_18,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_16,
+COUT => UN13_LOCK_CRY_18,
+S0 => UN13_LOCK_CRY_17_0_S0,
+S1 => UN13_LOCK_CRY_17_0_S1);
+UN13_LOCK_CRY_19_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_19,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_20,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_18,
+COUT => UN13_LOCK_CRY_20,
+S0 => UN13_LOCK_CRY_19_0_S0,
+S1 => UN13_LOCK_CRY_19_0_S1);
+UN13_LOCK_CRY_21_0: CCU2C 
+generic map(
+  INIT0 => X"500f",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_21,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_20,
+COUT => UN13_LOCK_CRY_21_0_COUT,
+S0 => UN13_LOCK_CRY_21_0_S0,
+S1 => UN13_LOCK_CRY_21_I);
+UN13_UNLOCK_CRY_0_0: CCU2C 
+generic map(
+  INIT0 => X"5003",
+  INIT1 => X"900a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_0,
+B1 => RDIFF_COMP_LOCK(2),
+C1 => VCC,
+D1 => VCC,
+CIN => N_1,
+COUT => UN13_UNLOCK_CRY_0,
+S0 => UN13_UNLOCK_CRY_0_0_S0,
+S1 => UN13_UNLOCK_CRY_0_0_S1);
+UN13_UNLOCK_CRY_1_0: CCU2C 
+generic map(
+  INIT0 => X"900a",
+  INIT1 => X"900a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_1,
+B0 => RDIFF_COMP_LOCK(2),
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_2,
+B1 => RDIFF_COMP_LOCK(2),
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_0,
+COUT => UN13_UNLOCK_CRY_2,
+S0 => UN13_UNLOCK_CRY_1_0_S0,
+S1 => UN13_UNLOCK_CRY_1_0_S1);
+UN13_UNLOCK_CRY_3_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_3,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_4,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_2,
+COUT => UN13_UNLOCK_CRY_4,
+S0 => UN13_UNLOCK_CRY_3_0_S0,
+S1 => UN13_UNLOCK_CRY_3_0_S1);
+UN13_UNLOCK_CRY_5_0: CCU2C 
+generic map(
+  INIT0 => X"900a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_5,
+B0 => RDIFF_COMP_LOCK(2),
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_6,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_4,
+COUT => UN13_UNLOCK_CRY_6,
+S0 => UN13_UNLOCK_CRY_5_0_S0,
+S1 => UN13_UNLOCK_CRY_5_0_S1);
+UN13_UNLOCK_CRY_7_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_7,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_8,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_6,
+COUT => UN13_UNLOCK_CRY_8,
+S0 => UN13_UNLOCK_CRY_7_0_S0,
+S1 => UN13_UNLOCK_CRY_7_0_S1);
+UN13_UNLOCK_CRY_9_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_9,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_10,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_8,
+COUT => UN13_UNLOCK_CRY_10,
+S0 => UN13_UNLOCK_CRY_9_0_S0,
+S1 => UN13_UNLOCK_CRY_9_0_S1);
+UN13_UNLOCK_CRY_11_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_11,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_12,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_10,
+COUT => UN13_UNLOCK_CRY_12,
+S0 => UN13_UNLOCK_CRY_11_0_S0,
+S1 => UN13_UNLOCK_CRY_11_0_S1);
+UN13_UNLOCK_CRY_13_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_13,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_14,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_12,
+COUT => UN13_UNLOCK_CRY_14,
+S0 => UN13_UNLOCK_CRY_13_0_S0,
+S1 => UN13_UNLOCK_CRY_13_0_S1);
+UN13_UNLOCK_CRY_15_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_15,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_16,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_14,
+COUT => UN13_UNLOCK_CRY_16,
+S0 => UN13_UNLOCK_CRY_15_0_S0,
+S1 => UN13_UNLOCK_CRY_15_0_S1);
+UN13_UNLOCK_CRY_17_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_17,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_18,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_16,
+COUT => UN13_UNLOCK_CRY_18,
+S0 => UN13_UNLOCK_CRY_17_0_S0,
+S1 => UN13_UNLOCK_CRY_17_0_S1);
+UN13_UNLOCK_CRY_19_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_19,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_20,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_18,
+COUT => UN13_UNLOCK_CRY_20,
+S0 => UN13_UNLOCK_CRY_19_0_S0,
+S1 => UN13_UNLOCK_CRY_19_0_S1);
+UN13_UNLOCK_CRY_21_0: CCU2C 
+generic map(
+  INIT0 => X"500f",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_21,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_20,
+COUT => UN13_UNLOCK_CRY_21_0_COUT,
+S0 => UN13_UNLOCK_CRY_21_0_S0,
+S1 => UN13_UNLOCK_CRY_21);
+PHB_SYNC_INST: sync_0s port map (
+phb => PHB,
+rhb_sync => RHB_SYNC,
+sli_rst => sli_rst,
+pll_refclki => pll_refclki);
+RTC_SYNC_INST: sync_0s_6 port map (
+rtc_pul => RTC_PUL,
+ppul_sync => PPUL_SYNC,
+sli_rst => sli_rst,
+tx_pclk => tx_pclk);
+PDIFF_SYNC_INST: sync_0s_0 port map (
+ppul_sync => PPUL_SYNC,
+pdiff_sync => PDIFF_SYNC,
+sli_rst => sli_rst,
+pll_refclki => pll_refclki);
+VCC_0: VHI port map (
+Z => VCC);
+II_GND: VLO port map (
+Z => GND);
+end beh;
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library synplify;
+use synplify.components.all;
+library pmi;
+use pmi.pmi_components.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity sgmii_ecp5 is
+port(
+hdoutp :  out std_logic;
+hdoutn :  out std_logic;
+hdinp :  in std_logic;
+hdinn :  in std_logic;
+rxrefclk :  in std_logic;
+tx_pclk :  out std_logic;
+txi_clk :  in std_logic;
+txdata : in std_logic_vector(7 downto 0);
+tx_k : in std_logic_vector(0 downto 0);
+xmit : in std_logic_vector(0 downto 0);
+tx_disp_correct : in std_logic_vector(0 downto 0);
+rxdata : out std_logic_vector(7 downto 0);
+rx_k : out std_logic_vector(0 downto 0);
+rx_disp_err : out std_logic_vector(0 downto 0);
+rx_cv_err : out std_logic_vector(0 downto 0);
+signal_detect_c :  in std_logic;
+rx_los_low_s :  out std_logic;
+lsm_status_s :  out std_logic;
+ctc_urun_s :  out std_logic;
+ctc_orun_s :  out std_logic;
+rx_cdr_lol_s :  out std_logic;
+ctc_ins_s :  out std_logic;
+ctc_del_s :  out std_logic;
+sli_rst :  in std_logic;
+tx_pwrup_c :  in std_logic;
+rx_pwrup_c :  in std_logic;
+sci_wrdata : in std_logic_vector(7 downto 0);
+sci_addr : in std_logic_vector(5 downto 0);
+sci_rddata : out std_logic_vector(7 downto 0);
+sci_en_dual :  in std_logic;
+sci_sel_dual :  in std_logic;
+sci_en :  in std_logic;
+sci_sel :  in std_logic;
+sci_rd :  in std_logic;
+sci_wrn :  in std_logic;
+sci_int :  out std_logic;
+cyawstn :  in std_logic;
+serdes_pdb :  in std_logic;
+pll_refclki :  in std_logic;
+rsl_disable :  in std_logic;
+rsl_rst :  in std_logic;
+serdes_rst_dual_c :  in std_logic;
+rst_dual_c :  in std_logic;
+tx_serdes_rst_c :  in std_logic;
+tx_pcs_rst_c :  in std_logic;
+pll_lol :  out std_logic;
+rsl_tx_rdy :  out std_logic;
+rx_serdes_rst_c :  in std_logic;
+rx_pcs_rst_c :  in std_logic;
+rsl_rx_rdy :  out std_logic);
+end sgmii_ecp5;
+
+architecture beh of sgmii_ecp5 is
+signal TX_PCLK_11 : std_logic ;
+signal RX_LOS_LOW_S_12 : std_logic ;
+signal RX_CDR_LOL_S_13 : std_logic ;
+signal RSL_TX_PCS_RST_C : std_logic ;
+signal RSL_RX_PCS_RST_C : std_logic ;
+signal RSL_RX_SERDES_RST_C : std_logic ;
+signal RSL_SERDES_RST_DUAL_C : std_logic ;
+signal RSL_TX_SERDES_RST_C : std_logic ;
+signal N47_1 : std_logic ;
+signal N48_1 : std_logic ;
+signal N1_1 : std_logic ;
+signal N2_1 : std_logic ;
+signal N3_1 : std_logic ;
+signal N4_1 : std_logic ;
+signal N5_1 : std_logic ;
+signal N49_1 : std_logic ;
+signal N6_1 : std_logic ;
+signal N50_1 : std_logic ;
+signal N7_1 : std_logic ;
+signal N51_1 : std_logic ;
+signal N8_1 : std_logic ;
+signal N52_1 : std_logic ;
+signal N9_1 : std_logic ;
+signal N53_1 : std_logic ;
+signal N54_1 : std_logic ;
+signal N55_1 : std_logic ;
+signal N56_1 : std_logic ;
+signal N57_1 : std_logic ;
+signal N58_1 : std_logic ;
+signal N59_1 : std_logic ;
+signal N60_1 : std_logic ;
+signal N61_1 : std_logic ;
+signal N62_1 : std_logic ;
+signal N63_1 : std_logic ;
+signal N64_1 : std_logic ;
+signal N65_1 : std_logic ;
+signal N10_1 : std_logic ;
+signal N66_1 : std_logic ;
+signal N67_1 : std_logic ;
+signal N68_1 : std_logic ;
+signal N69_1 : std_logic ;
+signal N70_1 : std_logic ;
+signal N71_1 : std_logic ;
+signal N72_1 : std_logic ;
+signal N73_1 : std_logic ;
+signal N74_1 : std_logic ;
+signal N75_1 : std_logic ;
+signal N76_1 : std_logic ;
+signal N77_1 : std_logic ;
+signal N78_1 : std_logic ;
+signal N79_1 : std_logic ;
+signal N80_1 : std_logic ;
+signal N81_1 : std_logic ;
+signal N82_1 : std_logic ;
+signal N83_1 : std_logic ;
+signal N84_1 : std_logic ;
+signal N85_1 : std_logic ;
+signal N86_1 : std_logic ;
+signal N87_1 : std_logic ;
+signal N88_1 : std_logic ;
+signal N11_1 : std_logic ;
+signal N89_1 : std_logic ;
+signal N12_1 : std_logic ;
+signal N90_1 : std_logic ;
+signal N13_1 : std_logic ;
+signal N91_1 : std_logic ;
+signal N92_1 : std_logic ;
+signal N93_1 : std_logic ;
+signal N94_1 : std_logic ;
+signal N95_1 : std_logic ;
+signal N14_1 : std_logic ;
+signal N96_1 : std_logic ;
+signal N15_1 : std_logic ;
+signal N97_1 : std_logic ;
+signal N98_1 : std_logic ;
+signal N99_1 : std_logic ;
+signal N100_1 : std_logic ;
+signal N101_1 : std_logic ;
+signal N112_1 : std_logic ;
+signal N16_1 : std_logic ;
+signal N17_1 : std_logic ;
+signal N18_1 : std_logic ;
+signal N19_1 : std_logic ;
+signal N20_1 : std_logic ;
+signal N21_1 : std_logic ;
+signal N22_1 : std_logic ;
+signal N23_1 : std_logic ;
+signal N24_1 : std_logic ;
+signal N25_1 : std_logic ;
+signal N26_1 : std_logic ;
+signal N27_1 : std_logic ;
+signal N28_1 : std_logic ;
+signal N29_1 : std_logic ;
+signal N30_1 : std_logic ;
+signal N31_1 : std_logic ;
+signal N32_1 : std_logic ;
+signal N33_1 : std_logic ;
+signal N34_1 : std_logic ;
+signal N35_1 : std_logic ;
+signal N36_1 : std_logic ;
+signal N37_1 : std_logic ;
+signal N38_1 : std_logic ;
+signal N39_1 : std_logic ;
+signal N40_1 : std_logic ;
+signal N41_1 : std_logic ;
+signal N42_1 : std_logic ;
+signal N43_1 : std_logic ;
+signal N46_1 : std_logic ;
+signal TX_PCLK_I : std_logic ;
+signal GND : std_logic ;
+signal VCC : std_logic ;
+signal \SLL_INST.PLL_LOCK_I_14\ : std_logic ;
+component sgmii_ecp5sll_core_Z1_layer1
+port(
+tx_pclk :  in std_logic;
+sli_rst :  in std_logic;
+pll_refclki :  in std_logic;
+pll_lock_i :  out std_logic  );
+end component;
+component sgmii_ecp5rsl_core_Z2_layer1
+port(
+rx_pcs_rst_c :  in std_logic;
+tx_pcs_rst_c :  in std_logic;
+serdes_rst_dual_c :  in std_logic;
+tx_serdes_rst_c :  in std_logic;
+rsl_rx_pcs_rst_c :  out std_logic;
+rsl_tx_pcs_rst_c :  out std_logic;
+rsl_tx_serdes_rst_c :  out std_logic;
+rsl_tx_rdy :  out std_logic;
+pll_lock_i :  in std_logic;
+pll_refclki :  in std_logic;
+rsl_rx_rdy :  out std_logic;
+rsl_rst :  in std_logic;
+rxrefclk :  in std_logic;
+rsl_disable :  in std_logic;
+rx_serdes_rst_c :  in std_logic;
+rst_dual_c :  in std_logic;
+rx_cdr_lol_s :  in std_logic;
+rx_los_low_s :  in std_logic;
+rsl_rx_serdes_rst_c :  out std_logic;
+rsl_serdes_rst_dual_c :  out std_logic  );
+end component;
+begin
+VCC_0: VHI port map (
+Z => VCC);
+GND_0: VLO port map (
+Z => GND);
+PUR_INST: PUR port map (
+PUR => VCC);
+GSR_INST: GSR port map (
+GSR => VCC);
+TX_PCLK_11 <= TX_PCLK_I;
+DCU0_INST: DCUA 
+generic map( 
+  D_MACROPDB => "0b1", 
+  D_IB_PWDNB => "0b1", 
+  D_XGE_MODE => "0b0", 
+  D_LOW_MARK => "0d4", 
+  D_HIGH_MARK => "0d12", 
+  D_BUS8BIT_SEL => "0b0", 
+  D_CDR_LOL_SET => "0b00", 
+  D_BITCLK_LOCAL_EN => "0b1", 
+  D_BITCLK_ND_EN => "0b0", 
+  D_BITCLK_FROM_ND_EN => "0b0", 
+  D_SYNC_LOCAL_EN => "0b1", 
+  D_SYNC_ND_EN => "0b0", 
+  CH0_UC_MODE => "0b0", 
+  CH0_PCIE_MODE => "0b0", 
+  CH0_RIO_MODE => "0b0", 
+  CH0_WA_MODE => "0b0", 
+  CH0_INVERT_RX => "0b0", 
+  CH0_INVERT_TX => "0b0", 
+  CH0_PRBS_SELECTION => "0b0", 
+  CH0_GE_AN_ENABLE => "0b0", 
+  CH0_PRBS_LOCK => "0b0", 
+  CH0_PRBS_ENABLE => "0b0", 
+  CH0_ENABLE_CG_ALIGN => "0b1", 
+  CH0_TX_GEAR_MODE => "0b0", 
+  CH0_RX_GEAR_MODE => "0b0", 
+  CH0_PCS_DET_TIME_SEL => "0b00", 
+  CH0_PCIE_EI_EN => "0b0", 
+  CH0_TX_GEAR_BYPASS => "0b0", 
+  CH0_ENC_BYPASS => "0b0", 
+  CH0_SB_BYPASS => "0b0", 
+  CH0_RX_SB_BYPASS => "0b0", 
+  CH0_WA_BYPASS => "0b0", 
+  CH0_DEC_BYPASS => "0b0", 
+  CH0_CTC_BYPASS => "0b0", 
+  CH0_RX_GEAR_BYPASS => "0b0", 
+  CH0_LSM_DISABLE => "0b0", 
+  CH0_MATCH_2_ENABLE => "0b1", 
+  CH0_MATCH_4_ENABLE => "0b0", 
+  CH0_MIN_IPG_CNT => "0b11", 
+  CH0_CC_MATCH_1 => "0x000", 
+  CH0_CC_MATCH_2 => "0x000", 
+  CH0_CC_MATCH_3 => "0x1BC", 
+  CH0_CC_MATCH_4 => "0x050", 
+  CH0_UDF_COMMA_MASK => "0x3ff", 
+  CH0_UDF_COMMA_A => "0x283", 
+  CH0_UDF_COMMA_B => "0x17C", 
+  CH0_RX_DCO_CK_DIV => "0b000", 
+  CH0_RCV_DCC_EN => "0b0", 
+  CH0_REQ_LVL_SET => "0b00", 
+  CH0_REQ_EN => "0b1", 
+  CH0_RTERM_RX => "0d22", 
+  CH0_PDEN_SEL => "0b1", 
+  CH0_LDR_RX2CORE_SEL => "0b0", 
+  CH0_LDR_CORE2TX_SEL => "0b0", 
+  CH0_TPWDNB => "0b1", 
+  CH0_RATE_MODE_TX => "0b0", 
+  CH0_RTERM_TX => "0d19", 
+  CH0_TX_CM_SEL => "0b00", 
+  CH0_TDRV_PRE_EN => "0b0", 
+  CH0_TDRV_SLICE0_SEL => "0b01", 
+  CH0_TDRV_SLICE1_SEL => "0b00", 
+  CH0_TDRV_SLICE2_SEL => "0b01", 
+  CH0_TDRV_SLICE3_SEL => "0b01", 
+  CH0_TDRV_SLICE4_SEL => "0b01", 
+  CH0_TDRV_SLICE5_SEL => "0b01", 
+  CH0_TDRV_SLICE0_CUR => "0b101", 
+  CH0_TDRV_SLICE1_CUR => "0b000", 
+  CH0_TDRV_SLICE2_CUR => "0b11", 
+  CH0_TDRV_SLICE3_CUR => "0b11", 
+  CH0_TDRV_SLICE4_CUR => "0b11", 
+  CH0_TDRV_SLICE5_CUR => "0b00", 
+  CH0_TDRV_DAT_SEL => "0b00", 
+  CH0_TX_DIV11_SEL => "0b0", 
+  CH0_RPWDNB => "0b1", 
+  CH0_RATE_MODE_RX => "0b0", 
+  CH0_RLOS_SEL => "0b1", 
+  CH0_RX_LOS_LVL => "0b010", 
+  CH0_RX_LOS_CEQ => "0b11", 
+  CH0_RX_LOS_HYST_EN => "0b0", 
+  CH0_RX_LOS_EN => "0b1", 
+  CH0_RX_DIV11_SEL => "0b0", 
+  CH0_SEL_SD_RX_CLK => "0b0", 
+  CH0_FF_RX_H_CLK_EN => "0b0", 
+  CH0_FF_RX_F_CLK_DIS => "0b0", 
+  CH0_FF_TX_H_CLK_EN => "0b0", 
+  CH0_FF_TX_F_CLK_DIS => "0b0", 
+  CH0_RX_RATE_SEL => "0d8", 
+  CH0_TDRV_POST_EN => "0b0", 
+  CH0_TX_POST_SIGN => "0b0", 
+  CH0_TX_PRE_SIGN => "0b0", 
+  CH0_RXTERM_CM => "0b11", 
+  CH0_RXIN_CM => "0b11", 
+  CH0_LEQ_OFFSET_SEL => "0b0", 
+  CH0_LEQ_OFFSET_TRIM => "0b000", 
+  D_TX_MAX_RATE => "2", 
+  CH0_CDR_MAX_RATE => "2", 
+  CH0_TXAMPLITUDE => "0d1100", 
+  CH0_TXDEPRE => "DISABLED", 
+  CH0_TXDEPOST => "DISABLED", 
+  CH0_PROTOCOL => "GBE", 
+  D_ISETLOS => "0d0", 
+  D_SETIRPOLY_AUX => "0b00", 
+  D_SETICONST_AUX => "0b00", 
+  D_SETIRPOLY_CH => "0b00", 
+  D_SETICONST_CH => "0b00", 
+  D_REQ_ISET => "0b000", 
+  D_PD_ISET => "0b00", 
+  D_DCO_CALIB_TIME_SEL => "0b00", 
+  CH0_DCOCTLGI => "0b010", 
+  CH0_DCOATDDLY => "0b00", 
+  CH0_DCOATDCFG => "0b00", 
+  CH0_DCOBYPSATD => "0b1", 
+  CH0_DCOSCALEI => "0b00", 
+  CH0_DCOITUNE4LSB => "0b111", 
+  CH0_DCOIOSTUNE => "0b000", 
+  CH0_DCODISBDAVOID => "0b0", 
+  CH0_DCOCALDIV => "0b001", 
+  CH0_DCONUOFLSB => "0b101", 
+  CH0_DCOIUPDNX2 => "0b1", 
+  CH0_DCOSTEP => "0b00", 
+  CH0_DCOSTARTVAL => "0b000", 
+  CH0_DCOFLTDAC => "0b01", 
+  CH0_DCOITUNE => "0b00", 
+  CH0_DCOFTNRG => "0b110", 
+  CH0_CDR_CNT4SEL => "0b00", 
+  CH0_CDR_CNT8SEL => "0b00", 
+  CH0_BAND_THRESHOLD => "0d0", 
+  CH0_AUTO_FACQ_EN => "0b1", 
+  CH0_AUTO_CALIB_EN => "0b1", 
+  CH0_CALIB_CK_MODE => "0b0", 
+  CH0_REG_BAND_OFFSET => "0d0", 
+  CH0_REG_BAND_SEL => "0d0", 
+  CH0_REG_IDAC_SEL => "0d0", 
+  CH0_REG_IDAC_EN => "0b0", 
+  D_TXPLL_PWDNB => "0b1", 
+  D_SETPLLRC => "0d1", 
+  D_REFCK_MODE => "0b001", 
+  D_TX_VCO_CK_DIV => "0b000", 
+  D_PLL_LOL_SET => "0b00", 
+  D_RG_EN => "0b0", 
+  D_RG_SET => "0b00", 
+  D_CMUSETISCL4VCO => "0b000", 
+  D_CMUSETI4VCO => "0b00", 
+  D_CMUSETINITVCT => "0b00", 
+  D_CMUSETZGM => "0b000", 
+  D_CMUSETP2AGM => "0b000", 
+  D_CMUSETP1GM => "0b000", 
+  D_CMUSETI4CPZ => "0d3", 
+  D_CMUSETI4CPP => "0d3", 
+  D_CMUSETICP4Z => "0b101", 
+  D_CMUSETICP4P => "0b01", 
+  D_CMUSETBIASI => "0b00"
+) 
+port map (
+CH0_HDINP => hdinp,
+CH1_HDINP => GND,
+CH0_HDINN => hdinn,
+CH1_HDINN => GND,
+D_TXBIT_CLKP_FROM_ND => GND,
+D_TXBIT_CLKN_FROM_ND => GND,
+D_SYNC_ND => GND,
+D_TXPLL_LOL_FROM_ND => GND,
+CH0_RX_REFCLK => rxrefclk,
+CH1_RX_REFCLK => GND,
+CH0_FF_RXI_CLK => TX_PCLK_11,
+CH1_FF_RXI_CLK => VCC,
+CH0_FF_TXI_CLK => txi_clk,
+CH1_FF_TXI_CLK => VCC,
+CH0_FF_EBRD_CLK => TX_PCLK_11,
+CH1_FF_EBRD_CLK => VCC,
+CH0_FF_TX_D_0 => txdata(0),
+CH1_FF_TX_D_0 => GND,
+CH0_FF_TX_D_1 => txdata(1),
+CH1_FF_TX_D_1 => GND,
+CH0_FF_TX_D_2 => txdata(2),
+CH1_FF_TX_D_2 => GND,
+CH0_FF_TX_D_3 => txdata(3),
+CH1_FF_TX_D_3 => GND,
+CH0_FF_TX_D_4 => txdata(4),
+CH1_FF_TX_D_4 => GND,
+CH0_FF_TX_D_5 => txdata(5),
+CH1_FF_TX_D_5 => GND,
+CH0_FF_TX_D_6 => txdata(6),
+CH1_FF_TX_D_6 => GND,
+CH0_FF_TX_D_7 => txdata(7),
+CH1_FF_TX_D_7 => GND,
+CH0_FF_TX_D_8 => tx_k(0),
+CH1_FF_TX_D_8 => GND,
+CH0_FF_TX_D_9 => GND,
+CH1_FF_TX_D_9 => GND,
+CH0_FF_TX_D_10 => xmit(0),
+CH1_FF_TX_D_10 => GND,
+CH0_FF_TX_D_11 => tx_disp_correct(0),
+CH1_FF_TX_D_11 => GND,
+CH0_FF_TX_D_12 => GND,
+CH1_FF_TX_D_12 => GND,
+CH0_FF_TX_D_13 => GND,
+CH1_FF_TX_D_13 => GND,
+CH0_FF_TX_D_14 => GND,
+CH1_FF_TX_D_14 => GND,
+CH0_FF_TX_D_15 => GND,
+CH1_FF_TX_D_15 => GND,
+CH0_FF_TX_D_16 => GND,
+CH1_FF_TX_D_16 => GND,
+CH0_FF_TX_D_17 => GND,
+CH1_FF_TX_D_17 => GND,
+CH0_FF_TX_D_18 => GND,
+CH1_FF_TX_D_18 => GND,
+CH0_FF_TX_D_19 => GND,
+CH1_FF_TX_D_19 => GND,
+CH0_FF_TX_D_20 => GND,
+CH1_FF_TX_D_20 => GND,
+CH0_FF_TX_D_21 => GND,
+CH1_FF_TX_D_21 => GND,
+CH0_FF_TX_D_22 => GND,
+CH1_FF_TX_D_22 => GND,
+CH0_FF_TX_D_23 => GND,
+CH1_FF_TX_D_23 => GND,
+CH0_FFC_EI_EN => GND,
+CH1_FFC_EI_EN => GND,
+CH0_FFC_PCIE_DET_EN => GND,
+CH1_FFC_PCIE_DET_EN => GND,
+CH0_FFC_PCIE_CT => GND,
+CH1_FFC_PCIE_CT => GND,
+CH0_FFC_SB_INV_RX => GND,
+CH1_FFC_SB_INV_RX => GND,
+CH0_FFC_ENABLE_CGALIGN => GND,
+CH1_FFC_ENABLE_CGALIGN => GND,
+CH0_FFC_SIGNAL_DETECT => signal_detect_c,
+CH1_FFC_SIGNAL_DETECT => GND,
+CH0_FFC_FB_LOOPBACK => GND,
+CH1_FFC_FB_LOOPBACK => GND,
+CH0_FFC_SB_PFIFO_LP => GND,
+CH1_FFC_SB_PFIFO_LP => GND,
+CH0_FFC_PFIFO_CLR => GND,
+CH1_FFC_PFIFO_CLR => GND,
+CH0_FFC_RATE_MODE_RX => GND,
+CH1_FFC_RATE_MODE_RX => GND,
+CH0_FFC_RATE_MODE_TX => GND,
+CH1_FFC_RATE_MODE_TX => GND,
+CH0_FFC_DIV11_MODE_RX => GND,
+CH1_FFC_DIV11_MODE_RX => GND,
+CH0_FFC_RX_GEAR_MODE => GND,
+CH1_FFC_RX_GEAR_MODE => GND,
+CH0_FFC_TX_GEAR_MODE => GND,
+CH1_FFC_TX_GEAR_MODE => GND,
+CH0_FFC_DIV11_MODE_TX => GND,
+CH1_FFC_DIV11_MODE_TX => GND,
+CH0_FFC_LDR_CORE2TX_EN => GND,
+CH1_FFC_LDR_CORE2TX_EN => GND,
+CH0_FFC_LANE_TX_RST => RSL_TX_PCS_RST_C,
+CH1_FFC_LANE_TX_RST => GND,
+CH0_FFC_LANE_RX_RST => RSL_RX_PCS_RST_C,
+CH1_FFC_LANE_RX_RST => GND,
+CH0_FFC_RRST => RSL_RX_SERDES_RST_C,
+CH1_FFC_RRST => GND,
+CH0_FFC_TXPWDNB => tx_pwrup_c,
+CH1_FFC_TXPWDNB => GND,
+CH0_FFC_RXPWDNB => rx_pwrup_c,
+CH1_FFC_RXPWDNB => GND,
+CH0_LDR_CORE2TX => GND,
+CH1_LDR_CORE2TX => GND,
+D_SCIWDATA0 => sci_wrdata(0),
+D_SCIWDATA1 => sci_wrdata(1),
+D_SCIWDATA2 => sci_wrdata(2),
+D_SCIWDATA3 => sci_wrdata(3),
+D_SCIWDATA4 => sci_wrdata(4),
+D_SCIWDATA5 => sci_wrdata(5),
+D_SCIWDATA6 => sci_wrdata(6),
+D_SCIWDATA7 => sci_wrdata(7),
+D_SCIADDR0 => sci_addr(0),
+D_SCIADDR1 => sci_addr(1),
+D_SCIADDR2 => sci_addr(2),
+D_SCIADDR3 => sci_addr(3),
+D_SCIADDR4 => sci_addr(4),
+D_SCIADDR5 => sci_addr(5),
+D_SCIENAUX => sci_en_dual,
+D_SCISELAUX => sci_sel_dual,
+CH0_SCIEN => sci_en,
+CH1_SCIEN => GND,
+CH0_SCISEL => sci_sel,
+CH1_SCISEL => GND,
+D_SCIRD => sci_rd,
+D_SCIWSTN => sci_wrn,
+D_CYAWSTN => cyawstn,
+D_FFC_SYNC_TOGGLE => GND,
+D_FFC_DUAL_RST => rst_dual_c,
+D_FFC_MACRO_RST => RSL_SERDES_RST_DUAL_C,
+D_FFC_MACROPDB => serdes_pdb,
+D_FFC_TRST => RSL_TX_SERDES_RST_C,
+CH0_FFC_CDR_EN_BITSLIP => GND,
+CH1_FFC_CDR_EN_BITSLIP => GND,
+D_SCAN_ENABLE => GND,
+D_SCAN_IN_0 => GND,
+D_SCAN_IN_1 => GND,
+D_SCAN_IN_2 => GND,
+D_SCAN_IN_3 => GND,
+D_SCAN_IN_4 => GND,
+D_SCAN_IN_5 => GND,
+D_SCAN_IN_6 => GND,
+D_SCAN_IN_7 => GND,
+D_SCAN_MODE => GND,
+D_SCAN_RESET => GND,
+D_CIN0 => GND,
+D_CIN1 => GND,
+D_CIN2 => GND,
+D_CIN3 => GND,
+D_CIN4 => GND,
+D_CIN5 => GND,
+D_CIN6 => GND,
+D_CIN7 => GND,
+D_CIN8 => GND,
+D_CIN9 => GND,
+D_CIN10 => GND,
+D_CIN11 => GND,
+CH0_HDOUTP => hdoutp,
+CH1_HDOUTP => N47_1,
+CH0_HDOUTN => hdoutn,
+CH1_HDOUTN => N48_1,
+D_TXBIT_CLKP_TO_ND => N1_1,
+D_TXBIT_CLKN_TO_ND => N2_1,
+D_SYNC_PULSE2ND => N3_1,
+D_TXPLL_LOL_TO_ND => N4_1,
+CH0_FF_RX_F_CLK => N5_1,
+CH1_FF_RX_F_CLK => N49_1,
+CH0_FF_RX_H_CLK => N6_1,
+CH1_FF_RX_H_CLK => N50_1,
+CH0_FF_TX_F_CLK => N7_1,
+CH1_FF_TX_F_CLK => N51_1,
+CH0_FF_TX_H_CLK => N8_1,
+CH1_FF_TX_H_CLK => N52_1,
+CH0_FF_RX_PCLK => N9_1,
+CH1_FF_RX_PCLK => N53_1,
+CH0_FF_TX_PCLK => TX_PCLK_I,
+CH1_FF_TX_PCLK => N54_1,
+CH0_FF_RX_D_0 => rxdata(0),
+CH1_FF_RX_D_0 => N55_1,
+CH0_FF_RX_D_1 => rxdata(1),
+CH1_FF_RX_D_1 => N56_1,
+CH0_FF_RX_D_2 => rxdata(2),
+CH1_FF_RX_D_2 => N57_1,
+CH0_FF_RX_D_3 => rxdata(3),
+CH1_FF_RX_D_3 => N58_1,
+CH0_FF_RX_D_4 => rxdata(4),
+CH1_FF_RX_D_4 => N59_1,
+CH0_FF_RX_D_5 => rxdata(5),
+CH1_FF_RX_D_5 => N60_1,
+CH0_FF_RX_D_6 => rxdata(6),
+CH1_FF_RX_D_6 => N61_1,
+CH0_FF_RX_D_7 => rxdata(7),
+CH1_FF_RX_D_7 => N62_1,
+CH0_FF_RX_D_8 => rx_k(0),
+CH1_FF_RX_D_8 => N63_1,
+CH0_FF_RX_D_9 => rx_disp_err(0),
+CH1_FF_RX_D_9 => N64_1,
+CH0_FF_RX_D_10 => rx_cv_err(0),
+CH1_FF_RX_D_10 => N65_1,
+CH0_FF_RX_D_11 => N10_1,
+CH1_FF_RX_D_11 => N66_1,
+CH0_FF_RX_D_12 => N67_1,
+CH1_FF_RX_D_12 => N68_1,
+CH0_FF_RX_D_13 => N69_1,
+CH1_FF_RX_D_13 => N70_1,
+CH0_FF_RX_D_14 => N71_1,
+CH1_FF_RX_D_14 => N72_1,
+CH0_FF_RX_D_15 => N73_1,
+CH1_FF_RX_D_15 => N74_1,
+CH0_FF_RX_D_16 => N75_1,
+CH1_FF_RX_D_16 => N76_1,
+CH0_FF_RX_D_17 => N77_1,
+CH1_FF_RX_D_17 => N78_1,
+CH0_FF_RX_D_18 => N79_1,
+CH1_FF_RX_D_18 => N80_1,
+CH0_FF_RX_D_19 => N81_1,
+CH1_FF_RX_D_19 => N82_1,
+CH0_FF_RX_D_20 => N83_1,
+CH1_FF_RX_D_20 => N84_1,
+CH0_FF_RX_D_21 => N85_1,
+CH1_FF_RX_D_21 => N86_1,
+CH0_FF_RX_D_22 => N87_1,
+CH1_FF_RX_D_22 => N88_1,
+CH0_FF_RX_D_23 => N11_1,
+CH1_FF_RX_D_23 => N89_1,
+CH0_FFS_PCIE_DONE => N12_1,
+CH1_FFS_PCIE_DONE => N90_1,
+CH0_FFS_PCIE_CON => N13_1,
+CH1_FFS_PCIE_CON => N91_1,
+CH0_FFS_RLOS => RX_LOS_LOW_S_12,
+CH1_FFS_RLOS => N92_1,
+CH0_FFS_LS_SYNC_STATUS => lsm_status_s,
+CH1_FFS_LS_SYNC_STATUS => N93_1,
+CH0_FFS_CC_UNDERRUN => ctc_urun_s,
+CH1_FFS_CC_UNDERRUN => N94_1,
+CH0_FFS_CC_OVERRUN => ctc_orun_s,
+CH1_FFS_CC_OVERRUN => N95_1,
+CH0_FFS_RXFBFIFO_ERROR => N14_1,
+CH1_FFS_RXFBFIFO_ERROR => N96_1,
+CH0_FFS_TXFBFIFO_ERROR => N15_1,
+CH1_FFS_TXFBFIFO_ERROR => N97_1,
+CH0_FFS_RLOL => RX_CDR_LOL_S_13,
+CH1_FFS_RLOL => N98_1,
+CH0_FFS_SKP_ADDED => ctc_ins_s,
+CH1_FFS_SKP_ADDED => N99_1,
+CH0_FFS_SKP_DELETED => ctc_del_s,
+CH1_FFS_SKP_DELETED => N100_1,
+CH0_LDR_RX2CORE => N101_1,
+CH1_LDR_RX2CORE => N112_1,
+D_SCIRDATA0 => sci_rddata(0),
+D_SCIRDATA1 => sci_rddata(1),
+D_SCIRDATA2 => sci_rddata(2),
+D_SCIRDATA3 => sci_rddata(3),
+D_SCIRDATA4 => sci_rddata(4),
+D_SCIRDATA5 => sci_rddata(5),
+D_SCIRDATA6 => sci_rddata(6),
+D_SCIRDATA7 => sci_rddata(7),
+D_SCIINT => sci_int,
+D_SCAN_OUT_0 => N16_1,
+D_SCAN_OUT_1 => N17_1,
+D_SCAN_OUT_2 => N18_1,
+D_SCAN_OUT_3 => N19_1,
+D_SCAN_OUT_4 => N20_1,
+D_SCAN_OUT_5 => N21_1,
+D_SCAN_OUT_6 => N22_1,
+D_SCAN_OUT_7 => N23_1,
+D_COUT0 => N24_1,
+D_COUT1 => N25_1,
+D_COUT2 => N26_1,
+D_COUT3 => N27_1,
+D_COUT4 => N28_1,
+D_COUT5 => N29_1,
+D_COUT6 => N30_1,
+D_COUT7 => N31_1,
+D_COUT8 => N32_1,
+D_COUT9 => N33_1,
+D_COUT10 => N34_1,
+D_COUT11 => N35_1,
+D_COUT12 => N36_1,
+D_COUT13 => N37_1,
+D_COUT14 => N38_1,
+D_COUT15 => N39_1,
+D_COUT16 => N40_1,
+D_COUT17 => N41_1,
+D_COUT18 => N42_1,
+D_COUT19 => N43_1,
+D_REFCLKI => pll_refclki,
+D_FFS_PLOL => N46_1);
+SLL_INST: sgmii_ecp5sll_core_Z1_layer1 port map (
+tx_pclk => TX_PCLK_11,
+sli_rst => sli_rst,
+pll_refclki => pll_refclki,
+pll_lock_i => \SLL_INST.PLL_LOCK_I_14\);
+RSL_INST: sgmii_ecp5rsl_core_Z2_layer1 port map (
+rx_pcs_rst_c => rx_pcs_rst_c,
+tx_pcs_rst_c => tx_pcs_rst_c,
+serdes_rst_dual_c => serdes_rst_dual_c,
+tx_serdes_rst_c => tx_serdes_rst_c,
+rsl_rx_pcs_rst_c => RSL_RX_PCS_RST_C,
+rsl_tx_pcs_rst_c => RSL_TX_PCS_RST_C,
+rsl_tx_serdes_rst_c => RSL_TX_SERDES_RST_C,
+rsl_tx_rdy => rsl_tx_rdy,
+pll_lock_i => \SLL_INST.PLL_LOCK_I_14\,
+pll_refclki => pll_refclki,
+rsl_rx_rdy => rsl_rx_rdy,
+rsl_rst => rsl_rst,
+rxrefclk => rxrefclk,
+rsl_disable => rsl_disable,
+rx_serdes_rst_c => rx_serdes_rst_c,
+rst_dual_c => rst_dual_c,
+rx_cdr_lol_s => RX_CDR_LOL_S_13,
+rx_los_low_s => RX_LOS_LOW_S_12,
+rsl_rx_serdes_rst_c => RSL_RX_SERDES_RST_C,
+rsl_serdes_rst_dual_c => RSL_SERDES_RST_DUAL_C);
+tx_pclk <= TX_PCLK_11;
+rx_los_low_s <= RX_LOS_LOW_S_12;
+rx_cdr_lol_s <= RX_CDR_LOL_S_13;
+pll_lol <= \SLL_INST.PLL_LOCK_I_14\;
+end beh;
+

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.vm b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.vm
new file mode 100644 (file)
index 0000000..be4d326
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.vm
@@ -0,0 +1,6617 @@
+//
+// Written by Synplify Pro 
+// Product Version "M-2017.03L-SP1-1"
+// Program "Synplify Pro", Mapper "maplat, Build 1796R"
+// Fri May 10 11:59:01 2019
+//
+// Source file index table:
+// Object locations will have the form <file>:<line>
+// file 0 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd "
+// file 1 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd "
+// file 2 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd "
+// file 3 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd "
+// file 4 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd "
+// file 5 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd "
+// file 6 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd "
+// file 7 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd "
+// file 8 "\/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd "
+// file 9 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd "
+// file 10 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v "
+// file 11 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v "
+// file 12 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v "
+// file 13 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v "
+// file 14 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v "
+// file 15 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh "
+// file 16 "\/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v "
+// file 17 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/nlconst.dat "
+// file 18 "\/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.fdc "
+
+`timescale 100 ps/100 ps
+module sync_0s (
+  phb,
+  rhb_sync,
+  sli_rst,
+  pll_refclki
+)
+;
+input phb ;
+output rhb_sync ;
+input sli_rst ;
+input pll_refclki ;
+wire phb ;
+wire rhb_sync ;
+wire sli_rst ;
+wire pll_refclki ;
+wire data_p1 ;
+wire data_p2_QN_0 ;
+wire VCC ;
+wire data_p1_QN_0 ;
+wire GND ;
+// @16:1988
+  FD1S3DX data_p2 (
+       .D(data_p1),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_sync)
+);
+// @16:1988
+  FD1S3DX data_p1_reg (
+       .D(phb),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(data_p1)
+);
+  VHI VCC_0 (
+       .Z(VCC)
+);
+// @16:865
+  VLO GND_cZ (
+       .Z(GND)
+);
+endmodule /* sync_0s */
+
+module sync_0s_6 (
+  rtc_pul,
+  ppul_sync,
+  sli_rst,
+  tx_pclk
+)
+;
+input rtc_pul ;
+output ppul_sync ;
+input sli_rst ;
+input tx_pclk ;
+wire rtc_pul ;
+wire ppul_sync ;
+wire sli_rst ;
+wire tx_pclk ;
+wire data_p1 ;
+wire data_p2_QN ;
+wire VCC ;
+wire data_p1_QN ;
+wire GND ;
+// @16:1988
+  FD1S3DX data_p2 (
+       .D(data_p1),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(ppul_sync)
+);
+// @16:1988
+  FD1S3DX data_p1_reg (
+       .D(rtc_pul),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(data_p1)
+);
+  VHI VCC_0 (
+       .Z(VCC)
+);
+// @16:865
+  VLO GND_cZ (
+       .Z(GND)
+);
+endmodule /* sync_0s_6 */
+
+module sync_0s_0 (
+  ppul_sync,
+  pdiff_sync,
+  sli_rst,
+  pll_refclki
+)
+;
+input ppul_sync ;
+output pdiff_sync ;
+input sli_rst ;
+input pll_refclki ;
+wire ppul_sync ;
+wire pdiff_sync ;
+wire sli_rst ;
+wire pll_refclki ;
+wire data_p1 ;
+wire data_p2_QN_1 ;
+wire VCC ;
+wire data_p1_QN_1 ;
+wire GND ;
+// @16:1988
+  FD1S3DX data_p2 (
+       .D(data_p1),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(pdiff_sync)
+);
+// @16:1988
+  FD1S3DX data_p1_reg (
+       .D(ppul_sync),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(data_p1)
+);
+  VHI VCC_0 (
+       .Z(VCC)
+);
+// @16:865
+  VLO GND_cZ (
+       .Z(GND)
+);
+endmodule /* sync_0s_0 */
+
+module sgmii_ecp5sll_core_Z1_layer1 (
+  tx_pclk,
+  sli_rst,
+  pll_refclki,
+  pll_lock_i
+)
+;
+input tx_pclk ;
+input sli_rst ;
+input pll_refclki ;
+output pll_lock_i ;
+wire tx_pclk ;
+wire sli_rst ;
+wire pll_refclki ;
+wire pll_lock_i ;
+wire [2:0] phb_cnt;
+wire [2:0] phb_cnt_i;
+wire [15:0] rcount;
+wire [21:0] pcount;
+wire [0:0] un1_pcount_diff_i;
+wire [1:0] sll_state;
+wire [1:0] sll_state_QN;
+wire [7:0] rhb_wait_cnt_s;
+wire [7:0] rhb_wait_cnt;
+wire [7:0] rhb_wait_cnt_QN;
+wire [15:0] rcount_s;
+wire [15:0] rcount_QN;
+wire [2:0] phb_cnt_QN;
+wire [2:1] phb_cnt_RNO;
+wire [21:0] pcount_s;
+wire [21:0] pcount_QN;
+wire [21:0] pcount_diff_QN;
+wire [2:2] rdiff_comp_lock;
+wire [2:2] rdiff_comp_lock_QN;
+wire [0:0] un1_pcount_diff;
+wire [20:0] pcount_cry;
+wire [0:0] pcount_cry_0_S0;
+wire [21:21] pcount_s_0_COUT;
+wire [21:21] pcount_s_0_S1;
+wire [14:0] rcount_cry;
+wire [0:0] rcount_cry_0_S0;
+wire [15:15] rcount_s_0_COUT;
+wire [15:15] rcount_s_0_S1;
+wire [6:0] rhb_wait_cnt_cry;
+wire [0:0] rhb_wait_cnt_cry_0_S0;
+wire [7:7] rhb_wait_cnt_s_0_COUT;
+wire [7:7] rhb_wait_cnt_s_0_S1;
+wire pll_lock ;
+wire rtc_ctrl4_0_a3_1 ;
+wire un13_lock_20 ;
+wire ppul_sync_p2 ;
+wire ppul_sync_p1 ;
+wire un1_pcount_diff_1_axb_20 ;
+wire un13_lock_19 ;
+wire un1_pcount_diff_1_axb_19 ;
+wire un13_lock_18 ;
+wire un1_pcount_diff_1_axb_18 ;
+wire un13_lock_17 ;
+wire un1_pcount_diff_1_axb_17 ;
+wire un13_lock_16 ;
+wire un1_pcount_diff_1_cry_15_0_RNO_0 ;
+wire un13_lock_15 ;
+wire un1_pcount_diff_1_axb_15 ;
+wire un13_lock_14 ;
+wire un1_pcount_diff_1_axb_14 ;
+wire un13_lock_13 ;
+wire un1_pcount_diff_1_axb_13 ;
+wire un13_lock_12 ;
+wire un1_pcount_diff_1_axb_12 ;
+wire un13_lock_11 ;
+wire un1_pcount_diff_1_axb_11 ;
+wire un13_lock_10 ;
+wire un1_pcount_diff_1_axb_10 ;
+wire un13_lock_9 ;
+wire un1_pcount_diff_1_axb_9 ;
+wire un13_lock_8 ;
+wire un1_pcount_diff_1_axb_8 ;
+wire un13_lock_7 ;
+wire un1_pcount_diff_1_axb_7 ;
+wire un13_lock_6 ;
+wire un1_pcount_diff_1_axb_6 ;
+wire un13_lock_5 ;
+wire un1_pcount_diff_1_axb_5 ;
+wire un13_lock_4 ;
+wire un1_pcount_diff_1_axb_4 ;
+wire un13_lock_3 ;
+wire un1_pcount_diff_1_axb_3 ;
+wire un13_lock_2 ;
+wire un1_pcount_diff_1_axb_2 ;
+wire un13_lock_1 ;
+wire un1_pcount_diff_1_axb_1 ;
+wire un13_lock_21 ;
+wire ppul_sync_p3 ;
+wire N_7 ;
+wire un13_lock_0 ;
+wire rtc_ctrl4 ;
+wire rtc_ctrl ;
+wire VCC ;
+wire N_2121_0 ;
+wire unlock_5 ;
+wire unlock_1_sqmuxa_i ;
+wire unlock ;
+wire unlock_QN ;
+wire N_95_i ;
+wire N_97_i ;
+wire rtc_pul ;
+wire rtc_pul_p1 ;
+wire rtc_pul_p1_QN ;
+wire rtc_pul5 ;
+wire rtc_pul_QN ;
+wire rtc_ctrl_QN ;
+wire rstat_pclk_2 ;
+wire rstat_pclk ;
+wire rstat_pclk_QN ;
+wire rhb_sync_p1 ;
+wire rhb_sync_p2 ;
+wire rhb_sync_p2_QN ;
+wire rhb_sync ;
+wire rhb_sync_p1_QN ;
+wire ppul_sync_p3_QN ;
+wire ppul_sync_p2_QN ;
+wire ppul_sync ;
+wire ppul_sync_p1_QN ;
+wire N_53_i ;
+wire pll_lock_QN ;
+wire phb ;
+wire phb_QN ;
+wire pdiff_sync ;
+wire pdiff_sync_p1 ;
+wire pdiff_sync_p1_QN ;
+wire un1_pcount_diff_1_cry_1_0_S0 ;
+wire un1_pcount_diff_1_cry_1_0_S1 ;
+wire un1_pcount_diff_1_cry_3_0_S0 ;
+wire un1_pcount_diff_1_cry_3_0_S1 ;
+wire un1_pcount_diff_1_cry_5_0_S0 ;
+wire un1_pcount_diff_1_cry_5_0_S1 ;
+wire un1_pcount_diff_1_cry_7_0_S0 ;
+wire un1_pcount_diff_1_cry_7_0_S1 ;
+wire un1_pcount_diff_1_cry_9_0_S0 ;
+wire un1_pcount_diff_1_cry_9_0_S1 ;
+wire un1_pcount_diff_1_cry_11_0_S0 ;
+wire un1_pcount_diff_1_cry_11_0_S1 ;
+wire un1_pcount_diff_1_cry_13_0_S0 ;
+wire un1_pcount_diff_1_cry_13_0_S1 ;
+wire un1_pcount_diff_1_cry_15_0_S0 ;
+wire un1_pcount_diff_1_cry_15_0_S1 ;
+wire un1_pcount_diff_1_cry_17_0_S0 ;
+wire un1_pcount_diff_1_cry_17_0_S1 ;
+wire un1_pcount_diff_1_cry_19_0_S0 ;
+wire un1_pcount_diff_1_cry_19_0_S1 ;
+wire un1_pcount_diff_1_s_21_0_S0 ;
+wire lock_5 ;
+wire lock_1_sqmuxa_i ;
+wire lock ;
+wire lock_QN ;
+wire N_98 ;
+wire rtc_pul5_0_o3 ;
+wire rtc_pul5_0_a3_6 ;
+wire rtc_pul5_0_a3_7 ;
+wire un1_rcount_1_0_a3 ;
+wire rhb_wait_cnt12 ;
+wire un1_rhb_wait_cnt_4 ;
+wire un1_rhb_wait_cnt_5 ;
+wire N_99 ;
+wire rtc_ctrl4_0_a3_12_4 ;
+wire rtc_ctrl4_0_a3_12_5 ;
+wire rtc_ctrl4_10 ;
+wire un1_rcount_1_0_a3_1 ;
+wire N_6 ;
+wire rtc_pul5_0_a3_5 ;
+wire N_8 ;
+wire un13_unlock_cry_21 ;
+wire un13_lock_cry_21_i ;
+wire rhb_wait_cnt_scalar ;
+wire un1_pcount_diff_1_cry_0 ;
+wire un1_pcount_diff_1_cry_0_0_S0 ;
+wire un1_pcount_diff_1_cry_0_0_S1 ;
+wire un1_pcount_diff_1_cry_2 ;
+wire un1_pcount_diff_1_cry_4 ;
+wire un1_pcount_diff_1_cry_6 ;
+wire un1_pcount_diff_1_cry_8 ;
+wire un1_pcount_diff_1_cry_10 ;
+wire un1_pcount_diff_1_cry_12 ;
+wire un1_pcount_diff_1_cry_14 ;
+wire un1_pcount_diff_1_cry_16 ;
+wire un1_pcount_diff_1_cry_18 ;
+wire un1_pcount_diff_1_cry_20 ;
+wire un1_pcount_diff_1_s_21_0_COUT ;
+wire un1_pcount_diff_1_s_21_0_S1 ;
+wire un13_lock_cry_0 ;
+wire un13_lock_cry_0_0_S0 ;
+wire un13_lock_cry_0_0_S1 ;
+wire un13_lock_cry_2 ;
+wire un13_lock_cry_1_0_S0 ;
+wire un13_lock_cry_1_0_S1 ;
+wire un13_lock_cry_4 ;
+wire un13_lock_cry_3_0_S0 ;
+wire un13_lock_cry_3_0_S1 ;
+wire un13_lock_cry_6 ;
+wire un13_lock_cry_5_0_S0 ;
+wire un13_lock_cry_5_0_S1 ;
+wire un13_lock_cry_8 ;
+wire un13_lock_cry_7_0_S0 ;
+wire un13_lock_cry_7_0_S1 ;
+wire un13_lock_cry_10 ;
+wire un13_lock_cry_9_0_S0 ;
+wire un13_lock_cry_9_0_S1 ;
+wire un13_lock_cry_12 ;
+wire un13_lock_cry_11_0_S0 ;
+wire un13_lock_cry_11_0_S1 ;
+wire un13_lock_cry_14 ;
+wire un13_lock_cry_13_0_S0 ;
+wire un13_lock_cry_13_0_S1 ;
+wire un13_lock_cry_16 ;
+wire un13_lock_cry_15_0_S0 ;
+wire un13_lock_cry_15_0_S1 ;
+wire un13_lock_cry_18 ;
+wire un13_lock_cry_17_0_S0 ;
+wire un13_lock_cry_17_0_S1 ;
+wire un13_lock_cry_20 ;
+wire un13_lock_cry_19_0_S0 ;
+wire un13_lock_cry_19_0_S1 ;
+wire un13_lock_cry_21_0_COUT ;
+wire un13_lock_cry_21_0_S0 ;
+wire un13_unlock_cry_0 ;
+wire un13_unlock_cry_0_0_S0 ;
+wire un13_unlock_cry_0_0_S1 ;
+wire un13_unlock_cry_2 ;
+wire un13_unlock_cry_1_0_S0 ;
+wire un13_unlock_cry_1_0_S1 ;
+wire un13_unlock_cry_4 ;
+wire un13_unlock_cry_3_0_S0 ;
+wire un13_unlock_cry_3_0_S1 ;
+wire un13_unlock_cry_6 ;
+wire un13_unlock_cry_5_0_S0 ;
+wire un13_unlock_cry_5_0_S1 ;
+wire un13_unlock_cry_8 ;
+wire un13_unlock_cry_7_0_S0 ;
+wire un13_unlock_cry_7_0_S1 ;
+wire un13_unlock_cry_10 ;
+wire un13_unlock_cry_9_0_S0 ;
+wire un13_unlock_cry_9_0_S1 ;
+wire un13_unlock_cry_12 ;
+wire un13_unlock_cry_11_0_S0 ;
+wire un13_unlock_cry_11_0_S1 ;
+wire un13_unlock_cry_14 ;
+wire un13_unlock_cry_13_0_S0 ;
+wire un13_unlock_cry_13_0_S1 ;
+wire un13_unlock_cry_16 ;
+wire un13_unlock_cry_15_0_S0 ;
+wire un13_unlock_cry_15_0_S1 ;
+wire un13_unlock_cry_18 ;
+wire un13_unlock_cry_17_0_S0 ;
+wire un13_unlock_cry_17_0_S1 ;
+wire un13_unlock_cry_20 ;
+wire un13_unlock_cry_19_0_S0 ;
+wire un13_unlock_cry_19_0_S1 ;
+wire un13_unlock_cry_21_0_COUT ;
+wire un13_unlock_cry_21_0_S0 ;
+wire N_21 ;
+wire N_20 ;
+wire N_19 ;
+wire N_18 ;
+wire N_14 ;
+wire GND ;
+wire N_1 ;
+wire N_2 ;
+wire N_3 ;
+wire N_4 ;
+wire N_5 ;
+wire N_9 ;
+  INV phb_RNO (
+       .A(phb_cnt[2]),
+       .Z(phb_cnt_i[2])
+);
+  INV \phb_cnt_RNO[0]  (
+       .A(phb_cnt[0]),
+       .Z(phb_cnt_i[0])
+);
+  INV pll_lock_RNI6JK9 (
+       .A(pll_lock),
+       .Z(pll_lock_i)
+);
+  LUT4 rtc_ctrl4_0_a3_RNO (
+       .A(rcount[2]),
+       .B(rcount[0]),
+       .C(rcount[5]),
+       .D(rcount[4]),
+       .Z(rtc_ctrl4_0_a3_1)
+);
+defparam rtc_ctrl4_0_a3_RNO.init=16'h2000;
+  LUT4 un1_pcount_diff_1_cry_19_0_RNO_0 (
+       .A(un13_lock_20),
+       .B(pcount[20]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_20)
+);
+defparam un1_pcount_diff_1_cry_19_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_19_0_RNO (
+       .A(un13_lock_19),
+       .B(pcount[19]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_19)
+);
+defparam un1_pcount_diff_1_cry_19_0_RNO.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_17_0_RNO_0 (
+       .A(un13_lock_18),
+       .B(pcount[18]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_18)
+);
+defparam un1_pcount_diff_1_cry_17_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_17_0_RNO (
+       .A(un13_lock_17),
+       .B(pcount[17]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_17)
+);
+defparam un1_pcount_diff_1_cry_17_0_RNO.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_15_0_RNO_0_cZ (
+       .A(un13_lock_16),
+       .B(pcount[16]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_cry_15_0_RNO_0)
+);
+defparam un1_pcount_diff_1_cry_15_0_RNO_0_cZ.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_15_0_RNO (
+       .A(un13_lock_15),
+       .B(pcount[15]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_15)
+);
+defparam un1_pcount_diff_1_cry_15_0_RNO.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_13_0_RNO_0 (
+       .A(un13_lock_14),
+       .B(pcount[14]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_14)
+);
+defparam un1_pcount_diff_1_cry_13_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_13_0_RNO (
+       .A(un13_lock_13),
+       .B(pcount[13]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_13)
+);
+defparam un1_pcount_diff_1_cry_13_0_RNO.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_11_0_RNO_0 (
+       .A(un13_lock_12),
+       .B(pcount[12]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_12)
+);
+defparam un1_pcount_diff_1_cry_11_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_11_0_RNO (
+       .A(un13_lock_11),
+       .B(pcount[11]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_11)
+);
+defparam un1_pcount_diff_1_cry_11_0_RNO.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_9_0_RNO_0 (
+       .A(un13_lock_10),
+       .B(pcount[10]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_10)
+);
+defparam un1_pcount_diff_1_cry_9_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_9_0_RNO (
+       .A(un13_lock_9),
+       .B(pcount[9]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_9)
+);
+defparam un1_pcount_diff_1_cry_9_0_RNO.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_7_0_RNO_0 (
+       .A(un13_lock_8),
+       .B(pcount[8]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_8)
+);
+defparam un1_pcount_diff_1_cry_7_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_7_0_RNO (
+       .A(un13_lock_7),
+       .B(pcount[7]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_7)
+);
+defparam un1_pcount_diff_1_cry_7_0_RNO.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_5_0_RNO_0 (
+       .A(un13_lock_6),
+       .B(pcount[6]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_6)
+);
+defparam un1_pcount_diff_1_cry_5_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_5_0_RNO (
+       .A(un13_lock_5),
+       .B(pcount[5]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_5)
+);
+defparam un1_pcount_diff_1_cry_5_0_RNO.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_3_0_RNO_0 (
+       .A(un13_lock_4),
+       .B(pcount[4]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_4)
+);
+defparam un1_pcount_diff_1_cry_3_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_3_0_RNO (
+       .A(un13_lock_3),
+       .B(pcount[3]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_3)
+);
+defparam un1_pcount_diff_1_cry_3_0_RNO.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_1_0_RNO_0 (
+       .A(un13_lock_2),
+       .B(pcount[2]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_2)
+);
+defparam un1_pcount_diff_1_cry_1_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_1_0_RNO (
+       .A(un13_lock_1),
+       .B(pcount[1]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_1)
+);
+defparam un1_pcount_diff_1_cry_1_0_RNO.init=16'h5355;
+  LUT4 ppul_sync_p3_RNIU65C (
+       .A(un13_lock_21),
+       .B(ppul_sync_p3),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(N_7)
+);
+defparam ppul_sync_p3_RNIU65C.init=16'h2F20;
+  LUT4 \pcount_diff_RNO[0]  (
+       .A(ppul_sync_p1),
+       .B(ppul_sync_p2),
+       .C(pcount[0]),
+       .D(un13_lock_0),
+       .Z(un1_pcount_diff_i[0])
+);
+defparam \pcount_diff_RNO[0] .init=16'hFD20;
+// @16:1304
+  LUT4 rtc_ctrl_0 (
+       .A(rtc_ctrl4),
+       .B(rtc_ctrl),
+       .C(VCC),
+       .D(VCC),
+       .Z(N_2121_0)
+);
+defparam rtc_ctrl_0.init=16'hEEEE;
+// @16:1278
+  FD1P3DX unlock_reg (
+       .D(unlock_5),
+       .SP(unlock_1_sqmuxa_i),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(unlock)
+);
+// @16:1801
+  FD1S3DX \sll_state_reg[0]  (
+       .D(N_95_i),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(sll_state[0])
+);
+// @16:1801
+  FD1S3DX \sll_state_reg[1]  (
+       .D(N_97_i),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(sll_state[1])
+);
+// @16:1304
+  FD1S3DX rtc_pul_p1_reg (
+       .D(rtc_pul),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rtc_pul_p1)
+);
+// @16:1304
+  FD1P3DX rtc_pul_reg (
+       .D(rtc_pul5),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rtc_pul)
+);
+// @16:1304
+  FD1S3DX rtc_ctrl_reg (
+       .D(N_2121_0),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rtc_ctrl)
+);
+// @16:1350
+  FD1P3DX rstat_pclk_reg (
+       .D(rstat_pclk_2),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rstat_pclk)
+);
+// @16:1350
+  FD1P3DX \rhb_wait_cnt_reg[0]  (
+       .D(rhb_wait_cnt_s[0]),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_wait_cnt[0])
+);
+// @16:1350
+  FD1P3DX \rhb_wait_cnt_reg[1]  (
+       .D(rhb_wait_cnt_s[1]),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_wait_cnt[1])
+);
+// @16:1350
+  FD1P3DX \rhb_wait_cnt_reg[2]  (
+       .D(rhb_wait_cnt_s[2]),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_wait_cnt[2])
+);
+// @16:1350
+  FD1P3DX \rhb_wait_cnt_reg[3]  (
+       .D(rhb_wait_cnt_s[3]),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_wait_cnt[3])
+);
+// @16:1350
+  FD1P3DX \rhb_wait_cnt_reg[4]  (
+       .D(rhb_wait_cnt_s[4]),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_wait_cnt[4])
+);
+// @16:1350
+  FD1P3DX \rhb_wait_cnt_reg[5]  (
+       .D(rhb_wait_cnt_s[5]),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_wait_cnt[5])
+);
+// @16:1350
+  FD1P3DX \rhb_wait_cnt_reg[6]  (
+       .D(rhb_wait_cnt_s[6]),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_wait_cnt[6])
+);
+// @16:1350
+  FD1P3DX \rhb_wait_cnt_reg[7]  (
+       .D(rhb_wait_cnt_s[7]),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_wait_cnt[7])
+);
+// @16:1350
+  FD1S3DX rhb_sync_p2_reg (
+       .D(rhb_sync_p1),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_sync_p2)
+);
+// @16:1350
+  FD1S3DX rhb_sync_p1_reg (
+       .D(rhb_sync),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_sync_p1)
+);
+// @16:1304
+  FD1S3DX \rcount_reg[0]  (
+       .D(rcount_s[0]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[0])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[1]  (
+       .D(rcount_s[1]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[1])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[2]  (
+       .D(rcount_s[2]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[2])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[3]  (
+       .D(rcount_s[3]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[3])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[4]  (
+       .D(rcount_s[4]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[4])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[5]  (
+       .D(rcount_s[5]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[5])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[6]  (
+       .D(rcount_s[6]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[6])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[7]  (
+       .D(rcount_s[7]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[7])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[8]  (
+       .D(rcount_s[8]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[8])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[9]  (
+       .D(rcount_s[9]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[9])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[10]  (
+       .D(rcount_s[10]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[10])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[11]  (
+       .D(rcount_s[11]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[11])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[12]  (
+       .D(rcount_s[12]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[12])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[13]  (
+       .D(rcount_s[13]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[13])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[14]  (
+       .D(rcount_s[14]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[14])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[15]  (
+       .D(rcount_s[15]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[15])
+);
+// @16:1408
+  FD1S3DX ppul_sync_p3_reg (
+       .D(ppul_sync_p2),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(ppul_sync_p3)
+);
+// @16:1408
+  FD1S3DX ppul_sync_p2_reg (
+       .D(ppul_sync_p1),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(ppul_sync_p2)
+);
+// @16:1408
+  FD1S3DX ppul_sync_p1_reg (
+       .D(ppul_sync),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(ppul_sync_p1)
+);
+// @16:1879
+  FD1S3DX pll_lock_reg (
+       .D(N_53_i),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(pll_lock)
+);
+// @16:1759
+  FD1S3DX \phb_cnt_reg[0]  (
+       .D(phb_cnt_i[0]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(phb_cnt[0])
+);
+// @16:1759
+  FD1S3DX \phb_cnt_reg[1]  (
+       .D(phb_cnt_RNO[1]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(phb_cnt[1])
+);
+// @16:1759
+  FD1S3DX \phb_cnt_reg[2]  (
+       .D(phb_cnt_RNO[2]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(phb_cnt[2])
+);
+// @16:1759
+  FD1S3DX phb_reg (
+       .D(phb_cnt_i[2]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(phb)
+);
+// @16:1278
+  FD1S3DX pdiff_sync_p1_reg (
+       .D(pdiff_sync),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(pdiff_sync_p1)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[0]  (
+       .D(pcount_s[0]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[0])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[0]  (
+       .D(un1_pcount_diff_i[0]),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_0)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[1]  (
+       .D(pcount_s[1]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[1])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[1]  (
+       .D(un1_pcount_diff_1_cry_1_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_1)
+);
+// @16:1759
+  FD1P3BX \pcount_diff[2]  (
+       .D(un1_pcount_diff_1_cry_1_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_2)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[2]  (
+       .D(pcount_s[2]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[2])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[3]  (
+       .D(un1_pcount_diff_1_cry_3_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_3)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[3]  (
+       .D(pcount_s[3]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[3])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[4]  (
+       .D(un1_pcount_diff_1_cry_3_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_4)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[4]  (
+       .D(pcount_s[4]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[4])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[5]  (
+       .D(un1_pcount_diff_1_cry_5_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_5)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[5]  (
+       .D(pcount_s[5]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[5])
+);
+// @16:1759
+  FD1S3DX \pcount_reg[6]  (
+       .D(pcount_s[6]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[6])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[6]  (
+       .D(un1_pcount_diff_1_cry_5_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_6)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[7]  (
+       .D(pcount_s[7]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[7])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[7]  (
+       .D(un1_pcount_diff_1_cry_7_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_7)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[8]  (
+       .D(pcount_s[8]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[8])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[8]  (
+       .D(un1_pcount_diff_1_cry_7_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_8)
+);
+// @16:1759
+  FD1P3BX \pcount_diff[9]  (
+       .D(un1_pcount_diff_1_cry_9_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_9)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[9]  (
+       .D(pcount_s[9]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[9])
+);
+// @16:1759
+  FD1S3DX \pcount_reg[10]  (
+       .D(pcount_s[10]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[10])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[10]  (
+       .D(un1_pcount_diff_1_cry_9_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_10)
+);
+// @16:1759
+  FD1P3BX \pcount_diff[11]  (
+       .D(un1_pcount_diff_1_cry_11_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_11)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[11]  (
+       .D(pcount_s[11]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[11])
+);
+// @16:1759
+  FD1S3DX \pcount_reg[12]  (
+       .D(pcount_s[12]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[12])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[12]  (
+       .D(un1_pcount_diff_1_cry_11_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_12)
+);
+// @16:1759
+  FD1P3BX \pcount_diff[13]  (
+       .D(un1_pcount_diff_1_cry_13_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_13)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[13]  (
+       .D(pcount_s[13]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[13])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[14]  (
+       .D(un1_pcount_diff_1_cry_13_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_14)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[14]  (
+       .D(pcount_s[14]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[14])
+);
+// @16:1759
+  FD1S3DX \pcount_reg[15]  (
+       .D(pcount_s[15]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[15])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[15]  (
+       .D(un1_pcount_diff_1_cry_15_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_15)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[16]  (
+       .D(pcount_s[16]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[16])
+);
+// @16:1759
+  FD1P3DX \pcount_diff[16]  (
+       .D(un1_pcount_diff_1_cry_15_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(un13_lock_16)
+);
+// @16:1759
+  FD1P3DX \pcount_diff[17]  (
+       .D(un1_pcount_diff_1_cry_17_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(un13_lock_17)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[17]  (
+       .D(pcount_s[17]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[17])
+);
+// @16:1759
+  FD1P3DX \pcount_diff[18]  (
+       .D(un1_pcount_diff_1_cry_17_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(un13_lock_18)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[18]  (
+       .D(pcount_s[18]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[18])
+);
+// @16:1759
+  FD1S3DX \pcount_reg[19]  (
+       .D(pcount_s[19]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[19])
+);
+// @16:1759
+  FD1P3DX \pcount_diff[19]  (
+       .D(un1_pcount_diff_1_cry_19_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(un13_lock_19)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[20]  (
+       .D(pcount_s[20]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[20])
+);
+// @16:1759
+  FD1P3DX \pcount_diff[20]  (
+       .D(un1_pcount_diff_1_cry_19_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(un13_lock_20)
+);
+// @16:1759
+  FD1P3DX \pcount_diff[21]  (
+       .D(un1_pcount_diff_1_s_21_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(un13_lock_21)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[21]  (
+       .D(pcount_s[21]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[21])
+);
+// @16:1278
+  FD1P3DX lock_reg (
+       .D(lock_5),
+       .SP(lock_1_sqmuxa_i),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(lock)
+);
+// @16:1739
+  FD1S3DX \genblk5.rdiff_comp_lock[2]  (
+       .D(VCC),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rdiff_comp_lock[2])
+);
+// @16:1801
+  LUT4 \sll_state_RNO[0]  (
+       .A(N_98),
+       .B(lock),
+       .C(rstat_pclk),
+       .D(sll_state[0]),
+       .Z(N_95_i)
+);
+defparam \sll_state_RNO[0] .init=16'hE050;
+// @16:1334
+  LUT4 rtc_pul5_0_0 (
+       .A(rtc_pul5_0_o3),
+       .B(rtc_pul5_0_a3_6),
+       .C(rtc_pul5_0_a3_7),
+       .D(un1_rcount_1_0_a3),
+       .Z(rtc_pul5)
+);
+defparam rtc_pul5_0_0.init=16'hFF80;
+// @16:1389
+  LUT4 rstat_pclk_2_iv (
+       .A(rhb_wait_cnt12),
+       .B(rstat_pclk),
+       .C(un1_rhb_wait_cnt_4),
+       .D(un1_rhb_wait_cnt_5),
+       .Z(rstat_pclk_2)
+);
+defparam rstat_pclk_2_iv.init=16'hAEEE;
+// @16:1801
+  LUT4 \sll_state_RNO[1]  (
+       .A(N_99),
+       .B(rstat_pclk),
+       .C(sll_state[1]),
+       .D(unlock),
+       .Z(N_97_i)
+);
+defparam \sll_state_RNO[1] .init=16'h8088;
+// @16:1328
+  LUT4 rtc_ctrl4_0_a3 (
+       .A(rtc_ctrl4_0_a3_1),
+       .B(rtc_ctrl4_0_a3_12_4),
+       .C(rtc_ctrl4_0_a3_12_5),
+       .D(rtc_ctrl4_10),
+       .Z(rtc_ctrl4)
+);
+defparam rtc_ctrl4_0_a3.init=16'h8000;
+// @16:1319
+  LUT4 un1_rcount_1_0_a3_cZ (
+       .A(rtc_ctrl4_0_a3_12_4),
+       .B(rtc_ctrl4_0_a3_12_5),
+       .C(rtc_ctrl4_10),
+       .D(un1_rcount_1_0_a3_1),
+       .Z(un1_rcount_1_0_a3)
+);
+defparam un1_rcount_1_0_a3_cZ.init=16'h8000;
+// @16:1278
+  LUT4 lock_1_sqmuxa_i_cZ (
+       .A(lock),
+       .B(pdiff_sync),
+       .C(pdiff_sync_p1),
+       .D(VCC),
+       .Z(lock_1_sqmuxa_i)
+);
+defparam lock_1_sqmuxa_i_cZ.init=16'h7575;
+// @16:1278
+  LUT4 unlock_1_sqmuxa_i_cZ (
+       .A(pdiff_sync),
+       .B(pdiff_sync_p1),
+       .C(unlock),
+       .D(VCC),
+       .Z(unlock_1_sqmuxa_i)
+);
+defparam unlock_1_sqmuxa_i_cZ.init=16'h4F4F;
+// @16:1334
+  LUT4 rtc_pul5_0_o3_cZ (
+       .A(N_6),
+       .B(rcount[1]),
+       .C(rcount[2]),
+       .D(rcount[3]),
+       .Z(rtc_pul5_0_o3)
+);
+defparam rtc_pul5_0_o3_cZ.init=16'hAAAB;
+// @16:1334
+  LUT4 rtc_pul5_0_a3_7_cZ (
+       .A(rcount[7]),
+       .B(rcount[8]),
+       .C(rtc_pul5_0_a3_5),
+       .D(VCC),
+       .Z(rtc_pul5_0_a3_7)
+);
+defparam rtc_pul5_0_a3_7_cZ.init=16'h1010;
+// @16:1801
+  LUT4 \sll_state_ns_i_m4[1]  (
+       .A(lock),
+       .B(rtc_pul),
+       .C(rtc_pul_p1),
+       .D(sll_state[1]),
+       .Z(N_99)
+);
+defparam \sll_state_ns_i_m4[1] .init=16'hEF20;
+// @16:1879
+  LUT4 pll_lock_RNO (
+       .A(sll_state[0]),
+       .B(sll_state[1]),
+       .C(VCC),
+       .D(VCC),
+       .Z(N_53_i)
+);
+defparam pll_lock_RNO.init=16'h8888;
+// @16:1776
+  LUT4 \phb_cnt_RNO_cZ[2]  (
+       .A(phb_cnt[0]),
+       .B(phb_cnt[1]),
+       .C(phb_cnt[2]),
+       .D(VCC),
+       .Z(phb_cnt_RNO[2])
+);
+defparam \phb_cnt_RNO_cZ[2] .init=16'h7878;
+// @16:1801
+  LUT4 \sll_state_ns_i_o4[0]  (
+       .A(rtc_pul),
+       .B(rtc_pul_p1),
+       .C(sll_state[1]),
+       .D(VCC),
+       .Z(N_98)
+);
+defparam \sll_state_ns_i_o4[0] .init=16'hBFBF;
+// @16:1328
+  LUT4 rtc_ctrl4_0_a3_10 (
+       .A(rcount[1]),
+       .B(rcount[3]),
+       .C(rcount[6]),
+       .D(rcount[15]),
+       .Z(rtc_ctrl4_10)
+);
+defparam rtc_ctrl4_0_a3_10.init=16'h8000;
+// @16:1393
+  LUT4 un1_rhb_wait_cnt_4_cZ (
+       .A(rhb_wait_cnt[4]),
+       .B(rhb_wait_cnt[5]),
+       .C(rhb_wait_cnt[6]),
+       .D(rhb_wait_cnt[7]),
+       .Z(un1_rhb_wait_cnt_4)
+);
+defparam un1_rhb_wait_cnt_4_cZ.init=16'h8000;
+// @16:1393
+  LUT4 un1_rhb_wait_cnt_5_cZ (
+       .A(rhb_wait_cnt[0]),
+       .B(rhb_wait_cnt[1]),
+       .C(rhb_wait_cnt[2]),
+       .D(rhb_wait_cnt[3]),
+       .Z(un1_rhb_wait_cnt_5)
+);
+defparam un1_rhb_wait_cnt_5_cZ.init=16'h8000;
+// @16:1328
+  LUT4 rtc_ctrl4_0_a3_12_4_cZ (
+       .A(rcount[11]),
+       .B(rcount[12]),
+       .C(rcount[13]),
+       .D(rcount[14]),
+       .Z(rtc_ctrl4_0_a3_12_4)
+);
+defparam rtc_ctrl4_0_a3_12_4_cZ.init=16'h8000;
+// @16:1328
+  LUT4 rtc_ctrl4_0_a3_12_5_cZ (
+       .A(rcount[7]),
+       .B(rcount[8]),
+       .C(rcount[9]),
+       .D(rcount[10]),
+       .Z(rtc_ctrl4_0_a3_12_5)
+);
+defparam rtc_ctrl4_0_a3_12_5_cZ.init=16'h8000;
+// @16:1334
+  LUT4 rtc_pul5_0_a3_5_cZ (
+       .A(rcount[6]),
+       .B(rcount[13]),
+       .C(rcount[14]),
+       .D(rcount[15]),
+       .Z(rtc_pul5_0_a3_5)
+);
+defparam rtc_pul5_0_a3_5_cZ.init=16'h0001;
+// @16:1334
+  LUT4 rtc_pul5_0_a3_6_cZ (
+       .A(rcount[9]),
+       .B(rcount[10]),
+       .C(rcount[11]),
+       .D(rcount[12]),
+       .Z(rtc_pul5_0_a3_6)
+);
+defparam rtc_pul5_0_a3_6_cZ.init=16'h0001;
+// @16:1768
+  LUT4 pcount10_0_o3 (
+       .A(ppul_sync_p1),
+       .B(ppul_sync_p2),
+       .C(VCC),
+       .D(VCC),
+       .Z(N_8)
+);
+defparam pcount10_0_o3.init=16'hDDDD;
+// @16:1776
+  LUT4 \phb_cnt_RNO_cZ[1]  (
+       .A(phb_cnt[0]),
+       .B(phb_cnt[1]),
+       .C(VCC),
+       .D(VCC),
+       .Z(phb_cnt_RNO[1])
+);
+defparam \phb_cnt_RNO_cZ[1] .init=16'h6666;
+// @16:1328
+  LUT4 rtc_ctrl4_0_o3 (
+       .A(rcount[4]),
+       .B(rcount[5]),
+       .C(VCC),
+       .D(VCC),
+       .Z(N_6)
+);
+defparam rtc_ctrl4_0_o3.init=16'h7777;
+// @16:1286
+  LUT4 unlock_5_cZ (
+       .A(pdiff_sync),
+       .B(un13_unlock_cry_21),
+       .C(VCC),
+       .D(VCC),
+       .Z(unlock_5)
+);
+defparam unlock_5_cZ.init=16'h8888;
+// @16:1292
+  LUT4 lock_5_cZ (
+       .A(pdiff_sync),
+       .B(un13_lock_cry_21_i),
+       .C(VCC),
+       .D(VCC),
+       .Z(lock_5)
+);
+defparam lock_5_cZ.init=16'h8888;
+// @16:1389
+  LUT4 rhb_wait_cnt12_cZ (
+       .A(rhb_sync_p1),
+       .B(rhb_sync_p2),
+       .C(VCC),
+       .D(VCC),
+       .Z(rhb_wait_cnt12)
+);
+defparam rhb_wait_cnt12_cZ.init=16'h2222;
+// @16:1786
+  LUT4 \un1_pcount_diff_cZ[0]  (
+       .A(un13_lock_0),
+       .B(pcount[0]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff[0])
+);
+defparam \un1_pcount_diff_cZ[0] .init=16'h5355;
+// @16:1319
+  LUT4 un1_rcount_1_0_a3_1_cZ (
+       .A(rcount[2]),
+       .B(rcount[0]),
+       .C(rcount[5]),
+       .D(rcount[4]),
+       .Z(un1_rcount_1_0_a3_1)
+);
+defparam un1_rcount_1_0_a3_1_cZ.init=16'h8000;
+// @16:1350
+  LUT4 rhb_sync_p2_RNIU9TG1 (
+       .A(un1_rhb_wait_cnt_5),
+       .B(un1_rhb_wait_cnt_4),
+       .C(rhb_sync_p2),
+       .D(rhb_sync_p1),
+       .Z(rhb_wait_cnt_scalar)
+);
+defparam rhb_sync_p2_RNIU9TG1.init=16'h7077;
+  CCU2C \pcount_cry_0[0]  (
+       .A0(VCC),
+       .B0(N_8),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_9),
+       .COUT(pcount_cry[0]),
+       .S0(pcount_cry_0_S0[0]),
+       .S1(pcount_s[0])
+);
+defparam \pcount_cry_0[0] .INIT0=16'h500c;
+defparam \pcount_cry_0[0] .INIT1=16'h8000;
+defparam \pcount_cry_0[0] .INJECT1_0="NO";
+defparam \pcount_cry_0[0] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[1]  (
+       .A0(N_8),
+       .B0(pcount[1]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[0]),
+       .COUT(pcount_cry[2]),
+       .S0(pcount_s[1]),
+       .S1(pcount_s[2])
+);
+defparam \pcount_cry_0[1] .INIT0=16'h8000;
+defparam \pcount_cry_0[1] .INIT1=16'h8000;
+defparam \pcount_cry_0[1] .INJECT1_0="NO";
+defparam \pcount_cry_0[1] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[3]  (
+       .A0(N_8),
+       .B0(pcount[3]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[4]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[2]),
+       .COUT(pcount_cry[4]),
+       .S0(pcount_s[3]),
+       .S1(pcount_s[4])
+);
+defparam \pcount_cry_0[3] .INIT0=16'h8000;
+defparam \pcount_cry_0[3] .INIT1=16'h8000;
+defparam \pcount_cry_0[3] .INJECT1_0="NO";
+defparam \pcount_cry_0[3] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[5]  (
+       .A0(N_8),
+       .B0(pcount[5]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[6]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[4]),
+       .COUT(pcount_cry[6]),
+       .S0(pcount_s[5]),
+       .S1(pcount_s[6])
+);
+defparam \pcount_cry_0[5] .INIT0=16'h8000;
+defparam \pcount_cry_0[5] .INIT1=16'h8000;
+defparam \pcount_cry_0[5] .INJECT1_0="NO";
+defparam \pcount_cry_0[5] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[7]  (
+       .A0(N_8),
+       .B0(pcount[7]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[8]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[6]),
+       .COUT(pcount_cry[8]),
+       .S0(pcount_s[7]),
+       .S1(pcount_s[8])
+);
+defparam \pcount_cry_0[7] .INIT0=16'h8000;
+defparam \pcount_cry_0[7] .INIT1=16'h8000;
+defparam \pcount_cry_0[7] .INJECT1_0="NO";
+defparam \pcount_cry_0[7] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[9]  (
+       .A0(N_8),
+       .B0(pcount[9]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[10]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[8]),
+       .COUT(pcount_cry[10]),
+       .S0(pcount_s[9]),
+       .S1(pcount_s[10])
+);
+defparam \pcount_cry_0[9] .INIT0=16'h8000;
+defparam \pcount_cry_0[9] .INIT1=16'h8000;
+defparam \pcount_cry_0[9] .INJECT1_0="NO";
+defparam \pcount_cry_0[9] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[11]  (
+       .A0(N_8),
+       .B0(pcount[11]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[12]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[10]),
+       .COUT(pcount_cry[12]),
+       .S0(pcount_s[11]),
+       .S1(pcount_s[12])
+);
+defparam \pcount_cry_0[11] .INIT0=16'h8000;
+defparam \pcount_cry_0[11] .INIT1=16'h8000;
+defparam \pcount_cry_0[11] .INJECT1_0="NO";
+defparam \pcount_cry_0[11] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[13]  (
+       .A0(N_8),
+       .B0(pcount[13]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[14]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[12]),
+       .COUT(pcount_cry[14]),
+       .S0(pcount_s[13]),
+       .S1(pcount_s[14])
+);
+defparam \pcount_cry_0[13] .INIT0=16'h8000;
+defparam \pcount_cry_0[13] .INIT1=16'h8000;
+defparam \pcount_cry_0[13] .INJECT1_0="NO";
+defparam \pcount_cry_0[13] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[15]  (
+       .A0(N_8),
+       .B0(pcount[15]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[16]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[14]),
+       .COUT(pcount_cry[16]),
+       .S0(pcount_s[15]),
+       .S1(pcount_s[16])
+);
+defparam \pcount_cry_0[15] .INIT0=16'h8000;
+defparam \pcount_cry_0[15] .INIT1=16'h8000;
+defparam \pcount_cry_0[15] .INJECT1_0="NO";
+defparam \pcount_cry_0[15] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[17]  (
+       .A0(N_8),
+       .B0(pcount[17]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[18]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[16]),
+       .COUT(pcount_cry[18]),
+       .S0(pcount_s[17]),
+       .S1(pcount_s[18])
+);
+defparam \pcount_cry_0[17] .INIT0=16'h8000;
+defparam \pcount_cry_0[17] .INIT1=16'h8000;
+defparam \pcount_cry_0[17] .INJECT1_0="NO";
+defparam \pcount_cry_0[17] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[19]  (
+       .A0(N_8),
+       .B0(pcount[19]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[20]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[18]),
+       .COUT(pcount_cry[20]),
+       .S0(pcount_s[19]),
+       .S1(pcount_s[20])
+);
+defparam \pcount_cry_0[19] .INIT0=16'h8000;
+defparam \pcount_cry_0[19] .INIT1=16'h8000;
+defparam \pcount_cry_0[19] .INJECT1_0="NO";
+defparam \pcount_cry_0[19] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_s_0[21]  (
+       .A0(N_8),
+       .B0(pcount[21]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[20]),
+       .COUT(pcount_s_0_COUT[21]),
+       .S0(pcount_s[21]),
+       .S1(pcount_s_0_S1[21])
+);
+defparam \pcount_s_0[21] .INIT0=16'h800a;
+defparam \pcount_s_0[21] .INIT1=16'h5003;
+defparam \pcount_s_0[21] .INJECT1_0="NO";
+defparam \pcount_s_0[21] .INJECT1_1="NO";
+  CCU2C \rcount_cry_0[0]  (
+       .A0(VCC),
+       .B0(un1_rcount_1_0_a3),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_rcount_1_0_a3),
+       .B1(rcount[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_5),
+       .COUT(rcount_cry[0]),
+       .S0(rcount_cry_0_S0[0]),
+       .S1(rcount_s[0])
+);
+defparam \rcount_cry_0[0] .INIT0=16'h5003;
+defparam \rcount_cry_0[0] .INIT1=16'h4000;
+defparam \rcount_cry_0[0] .INJECT1_0="NO";
+defparam \rcount_cry_0[0] .INJECT1_1="NO";
+// @16:1304
+  CCU2C \rcount_cry_0[1]  (
+       .A0(un1_rcount_1_0_a3),
+       .B0(rcount[1]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_rcount_1_0_a3),
+       .B1(rcount[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rcount_cry[0]),
+       .COUT(rcount_cry[2]),
+       .S0(rcount_s[1]),
+       .S1(rcount_s[2])
+);
+defparam \rcount_cry_0[1] .INIT0=16'h4000;
+defparam \rcount_cry_0[1] .INIT1=16'h4000;
+defparam \rcount_cry_0[1] .INJECT1_0="NO";
+defparam \rcount_cry_0[1] .INJECT1_1="NO";
+// @16:1304
+  CCU2C \rcount_cry_0[3]  (
+       .A0(un1_rcount_1_0_a3),
+       .B0(rcount[3]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_rcount_1_0_a3),
+       .B1(rcount[4]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rcount_cry[2]),
+       .COUT(rcount_cry[4]),
+       .S0(rcount_s[3]),
+       .S1(rcount_s[4])
+);
+defparam \rcount_cry_0[3] .INIT0=16'h4000;
+defparam \rcount_cry_0[3] .INIT1=16'h4000;
+defparam \rcount_cry_0[3] .INJECT1_0="NO";
+defparam \rcount_cry_0[3] .INJECT1_1="NO";
+// @16:1304
+  CCU2C \rcount_cry_0[5]  (
+       .A0(un1_rcount_1_0_a3),
+       .B0(rcount[5]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_rcount_1_0_a3),
+       .B1(rcount[6]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rcount_cry[4]),
+       .COUT(rcount_cry[6]),
+       .S0(rcount_s[5]),
+       .S1(rcount_s[6])
+);
+defparam \rcount_cry_0[5] .INIT0=16'h4000;
+defparam \rcount_cry_0[5] .INIT1=16'h4000;
+defparam \rcount_cry_0[5] .INJECT1_0="NO";
+defparam \rcount_cry_0[5] .INJECT1_1="NO";
+// @16:1304
+  CCU2C \rcount_cry_0[7]  (
+       .A0(un1_rcount_1_0_a3),
+       .B0(rcount[7]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_rcount_1_0_a3),
+       .B1(rcount[8]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rcount_cry[6]),
+       .COUT(rcount_cry[8]),
+       .S0(rcount_s[7]),
+       .S1(rcount_s[8])
+);
+defparam \rcount_cry_0[7] .INIT0=16'h4000;
+defparam \rcount_cry_0[7] .INIT1=16'h4000;
+defparam \rcount_cry_0[7] .INJECT1_0="NO";
+defparam \rcount_cry_0[7] .INJECT1_1="NO";
+// @16:1304
+  CCU2C \rcount_cry_0[9]  (
+       .A0(un1_rcount_1_0_a3),
+       .B0(rcount[9]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_rcount_1_0_a3),
+       .B1(rcount[10]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rcount_cry[8]),
+       .COUT(rcount_cry[10]),
+       .S0(rcount_s[9]),
+       .S1(rcount_s[10])
+);
+defparam \rcount_cry_0[9] .INIT0=16'h4000;
+defparam \rcount_cry_0[9] .INIT1=16'h4000;
+defparam \rcount_cry_0[9] .INJECT1_0="NO";
+defparam \rcount_cry_0[9] .INJECT1_1="NO";
+// @16:1304
+  CCU2C \rcount_cry_0[11]  (
+       .A0(un1_rcount_1_0_a3),
+       .B0(rcount[11]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_rcount_1_0_a3),
+       .B1(rcount[12]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rcount_cry[10]),
+       .COUT(rcount_cry[12]),
+       .S0(rcount_s[11]),
+       .S1(rcount_s[12])
+);
+defparam \rcount_cry_0[11] .INIT0=16'h4000;
+defparam \rcount_cry_0[11] .INIT1=16'h4000;
+defparam \rcount_cry_0[11] .INJECT1_0="NO";
+defparam \rcount_cry_0[11] .INJECT1_1="NO";
+// @16:1304
+  CCU2C \rcount_cry_0[13]  (
+       .A0(un1_rcount_1_0_a3),
+       .B0(rcount[13]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_rcount_1_0_a3),
+       .B1(rcount[14]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rcount_cry[12]),
+       .COUT(rcount_cry[14]),
+       .S0(rcount_s[13]),
+       .S1(rcount_s[14])
+);
+defparam \rcount_cry_0[13] .INIT0=16'h4000;
+defparam \rcount_cry_0[13] .INIT1=16'h4000;
+defparam \rcount_cry_0[13] .INJECT1_0="NO";
+defparam \rcount_cry_0[13] .INJECT1_1="NO";
+// @16:1304
+  CCU2C \rcount_s_0[15]  (
+       .A0(un1_rcount_1_0_a3),
+       .B0(rcount[15]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rcount_cry[14]),
+       .COUT(rcount_s_0_COUT[15]),
+       .S0(rcount_s[15]),
+       .S1(rcount_s_0_S1[15])
+);
+defparam \rcount_s_0[15] .INIT0=16'h4005;
+defparam \rcount_s_0[15] .INIT1=16'h5003;
+defparam \rcount_s_0[15] .INJECT1_0="NO";
+defparam \rcount_s_0[15] .INJECT1_1="NO";
+  CCU2C \rhb_wait_cnt_cry_0[0]  (
+       .A0(VCC),
+       .B0(rhb_wait_cnt_scalar),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rhb_wait_cnt_scalar),
+       .B1(rhb_wait_cnt[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_4),
+       .COUT(rhb_wait_cnt_cry[0]),
+       .S0(rhb_wait_cnt_cry_0_S0[0]),
+       .S1(rhb_wait_cnt_s[0])
+);
+defparam \rhb_wait_cnt_cry_0[0] .INIT0=16'h500c;
+defparam \rhb_wait_cnt_cry_0[0] .INIT1=16'h8000;
+defparam \rhb_wait_cnt_cry_0[0] .INJECT1_0="NO";
+defparam \rhb_wait_cnt_cry_0[0] .INJECT1_1="NO";
+// @16:1350
+  CCU2C \rhb_wait_cnt_cry_0[1]  (
+       .A0(rhb_wait_cnt_scalar),
+       .B0(rhb_wait_cnt[1]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rhb_wait_cnt_scalar),
+       .B1(rhb_wait_cnt[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rhb_wait_cnt_cry[0]),
+       .COUT(rhb_wait_cnt_cry[2]),
+       .S0(rhb_wait_cnt_s[1]),
+       .S1(rhb_wait_cnt_s[2])
+);
+defparam \rhb_wait_cnt_cry_0[1] .INIT0=16'h8000;
+defparam \rhb_wait_cnt_cry_0[1] .INIT1=16'h8000;
+defparam \rhb_wait_cnt_cry_0[1] .INJECT1_0="NO";
+defparam \rhb_wait_cnt_cry_0[1] .INJECT1_1="NO";
+// @16:1350
+  CCU2C \rhb_wait_cnt_cry_0[3]  (
+       .A0(rhb_wait_cnt_scalar),
+       .B0(rhb_wait_cnt[3]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rhb_wait_cnt_scalar),
+       .B1(rhb_wait_cnt[4]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rhb_wait_cnt_cry[2]),
+       .COUT(rhb_wait_cnt_cry[4]),
+       .S0(rhb_wait_cnt_s[3]),
+       .S1(rhb_wait_cnt_s[4])
+);
+defparam \rhb_wait_cnt_cry_0[3] .INIT0=16'h8000;
+defparam \rhb_wait_cnt_cry_0[3] .INIT1=16'h8000;
+defparam \rhb_wait_cnt_cry_0[3] .INJECT1_0="NO";
+defparam \rhb_wait_cnt_cry_0[3] .INJECT1_1="NO";
+// @16:1350
+  CCU2C \rhb_wait_cnt_cry_0[5]  (
+       .A0(rhb_wait_cnt_scalar),
+       .B0(rhb_wait_cnt[5]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rhb_wait_cnt_scalar),
+       .B1(rhb_wait_cnt[6]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rhb_wait_cnt_cry[4]),
+       .COUT(rhb_wait_cnt_cry[6]),
+       .S0(rhb_wait_cnt_s[5]),
+       .S1(rhb_wait_cnt_s[6])
+);
+defparam \rhb_wait_cnt_cry_0[5] .INIT0=16'h8000;
+defparam \rhb_wait_cnt_cry_0[5] .INIT1=16'h8000;
+defparam \rhb_wait_cnt_cry_0[5] .INJECT1_0="NO";
+defparam \rhb_wait_cnt_cry_0[5] .INJECT1_1="NO";
+// @16:1350
+  CCU2C \rhb_wait_cnt_s_0[7]  (
+       .A0(rhb_wait_cnt_scalar),
+       .B0(rhb_wait_cnt[7]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rhb_wait_cnt_cry[6]),
+       .COUT(rhb_wait_cnt_s_0_COUT[7]),
+       .S0(rhb_wait_cnt_s[7]),
+       .S1(rhb_wait_cnt_s_0_S1[7])
+);
+defparam \rhb_wait_cnt_s_0[7] .INIT0=16'h800a;
+defparam \rhb_wait_cnt_s_0[7] .INIT1=16'h5003;
+defparam \rhb_wait_cnt_s_0[7] .INJECT1_0="NO";
+defparam \rhb_wait_cnt_s_0[7] .INJECT1_1="NO";
+  CCU2C un1_pcount_diff_1_cry_0_0 (
+       .A0(VCC),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff[0]),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_3),
+       .COUT(un1_pcount_diff_1_cry_0),
+       .S0(un1_pcount_diff_1_cry_0_0_S0),
+       .S1(un1_pcount_diff_1_cry_0_0_S1)
+);
+defparam un1_pcount_diff_1_cry_0_0.INIT0=16'h5003;
+defparam un1_pcount_diff_1_cry_0_0.INIT1=16'h500f;
+defparam un1_pcount_diff_1_cry_0_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_0_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_1_0 (
+       .A0(un1_pcount_diff_1_axb_1),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_2),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_0),
+       .COUT(un1_pcount_diff_1_cry_2),
+       .S0(un1_pcount_diff_1_cry_1_0_S0),
+       .S1(un1_pcount_diff_1_cry_1_0_S1)
+);
+defparam un1_pcount_diff_1_cry_1_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_1_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_1_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_1_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_3_0 (
+       .A0(un1_pcount_diff_1_axb_3),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_4),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_2),
+       .COUT(un1_pcount_diff_1_cry_4),
+       .S0(un1_pcount_diff_1_cry_3_0_S0),
+       .S1(un1_pcount_diff_1_cry_3_0_S1)
+);
+defparam un1_pcount_diff_1_cry_3_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_3_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_3_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_3_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_5_0 (
+       .A0(un1_pcount_diff_1_axb_5),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_6),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_4),
+       .COUT(un1_pcount_diff_1_cry_6),
+       .S0(un1_pcount_diff_1_cry_5_0_S0),
+       .S1(un1_pcount_diff_1_cry_5_0_S1)
+);
+defparam un1_pcount_diff_1_cry_5_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_5_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_5_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_5_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_7_0 (
+       .A0(un1_pcount_diff_1_axb_7),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_8),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_6),
+       .COUT(un1_pcount_diff_1_cry_8),
+       .S0(un1_pcount_diff_1_cry_7_0_S0),
+       .S1(un1_pcount_diff_1_cry_7_0_S1)
+);
+defparam un1_pcount_diff_1_cry_7_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_7_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_7_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_7_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_9_0 (
+       .A0(un1_pcount_diff_1_axb_9),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_10),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_8),
+       .COUT(un1_pcount_diff_1_cry_10),
+       .S0(un1_pcount_diff_1_cry_9_0_S0),
+       .S1(un1_pcount_diff_1_cry_9_0_S1)
+);
+defparam un1_pcount_diff_1_cry_9_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_9_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_9_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_9_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_11_0 (
+       .A0(un1_pcount_diff_1_axb_11),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_12),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_10),
+       .COUT(un1_pcount_diff_1_cry_12),
+       .S0(un1_pcount_diff_1_cry_11_0_S0),
+       .S1(un1_pcount_diff_1_cry_11_0_S1)
+);
+defparam un1_pcount_diff_1_cry_11_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_11_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_11_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_11_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_13_0 (
+       .A0(un1_pcount_diff_1_axb_13),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_14),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_12),
+       .COUT(un1_pcount_diff_1_cry_14),
+       .S0(un1_pcount_diff_1_cry_13_0_S0),
+       .S1(un1_pcount_diff_1_cry_13_0_S1)
+);
+defparam un1_pcount_diff_1_cry_13_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_13_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_13_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_13_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_15_0 (
+       .A0(un1_pcount_diff_1_axb_15),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(rdiff_comp_lock[2]),
+       .C1(un1_pcount_diff_1_cry_15_0_RNO_0),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_14),
+       .COUT(un1_pcount_diff_1_cry_16),
+       .S0(un1_pcount_diff_1_cry_15_0_S0),
+       .S1(un1_pcount_diff_1_cry_15_0_S1)
+);
+defparam un1_pcount_diff_1_cry_15_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_15_0.INIT1=16'hb404;
+defparam un1_pcount_diff_1_cry_15_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_15_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_17_0 (
+       .A0(un1_pcount_diff_1_axb_17),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_18),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_16),
+       .COUT(un1_pcount_diff_1_cry_18),
+       .S0(un1_pcount_diff_1_cry_17_0_S0),
+       .S1(un1_pcount_diff_1_cry_17_0_S1)
+);
+defparam un1_pcount_diff_1_cry_17_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_17_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_17_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_17_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_19_0 (
+       .A0(un1_pcount_diff_1_axb_19),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_20),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_18),
+       .COUT(un1_pcount_diff_1_cry_20),
+       .S0(un1_pcount_diff_1_cry_19_0_S0),
+       .S1(un1_pcount_diff_1_cry_19_0_S1)
+);
+defparam un1_pcount_diff_1_cry_19_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_19_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_19_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_19_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_s_21_0 (
+       .A0(pcount[21]),
+       .B0(un13_lock_21),
+       .C0(N_8),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_20),
+       .COUT(un1_pcount_diff_1_s_21_0_COUT),
+       .S0(un1_pcount_diff_1_s_21_0_S0),
+       .S1(un1_pcount_diff_1_s_21_0_S1)
+);
+defparam un1_pcount_diff_1_s_21_0.INIT0=16'h350a;
+defparam un1_pcount_diff_1_s_21_0.INIT1=16'h5003;
+defparam un1_pcount_diff_1_s_21_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_s_21_0.INJECT1_1="NO";
+  CCU2C un13_lock_cry_0_0 (
+       .A0(VCC),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_0),
+       .B1(rdiff_comp_lock[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_2),
+       .COUT(un13_lock_cry_0),
+       .S0(un13_lock_cry_0_0_S0),
+       .S1(un13_lock_cry_0_0_S1)
+);
+defparam un13_lock_cry_0_0.INIT0=16'h5003;
+defparam un13_lock_cry_0_0.INIT1=16'h900a;
+defparam un13_lock_cry_0_0.INJECT1_0="NO";
+defparam un13_lock_cry_0_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_1_0 (
+       .A0(un13_lock_1),
+       .B0(rdiff_comp_lock[2]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_2),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_0),
+       .COUT(un13_lock_cry_2),
+       .S0(un13_lock_cry_1_0_S0),
+       .S1(un13_lock_cry_1_0_S1)
+);
+defparam un13_lock_cry_1_0.INIT0=16'h900a;
+defparam un13_lock_cry_1_0.INIT1=16'h500a;
+defparam un13_lock_cry_1_0.INJECT1_0="NO";
+defparam un13_lock_cry_1_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_3_0 (
+       .A0(un13_lock_3),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_4),
+       .B1(rdiff_comp_lock[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_2),
+       .COUT(un13_lock_cry_4),
+       .S0(un13_lock_cry_3_0_S0),
+       .S1(un13_lock_cry_3_0_S1)
+);
+defparam un13_lock_cry_3_0.INIT0=16'h500a;
+defparam un13_lock_cry_3_0.INIT1=16'h900a;
+defparam un13_lock_cry_3_0.INJECT1_0="NO";
+defparam un13_lock_cry_3_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_5_0 (
+       .A0(un13_lock_5),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_6),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_4),
+       .COUT(un13_lock_cry_6),
+       .S0(un13_lock_cry_5_0_S0),
+       .S1(un13_lock_cry_5_0_S1)
+);
+defparam un13_lock_cry_5_0.INIT0=16'h500a;
+defparam un13_lock_cry_5_0.INIT1=16'h500a;
+defparam un13_lock_cry_5_0.INJECT1_0="NO";
+defparam un13_lock_cry_5_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_7_0 (
+       .A0(un13_lock_7),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_8),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_6),
+       .COUT(un13_lock_cry_8),
+       .S0(un13_lock_cry_7_0_S0),
+       .S1(un13_lock_cry_7_0_S1)
+);
+defparam un13_lock_cry_7_0.INIT0=16'h500a;
+defparam un13_lock_cry_7_0.INIT1=16'h500a;
+defparam un13_lock_cry_7_0.INJECT1_0="NO";
+defparam un13_lock_cry_7_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_9_0 (
+       .A0(un13_lock_9),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_10),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_8),
+       .COUT(un13_lock_cry_10),
+       .S0(un13_lock_cry_9_0_S0),
+       .S1(un13_lock_cry_9_0_S1)
+);
+defparam un13_lock_cry_9_0.INIT0=16'h500a;
+defparam un13_lock_cry_9_0.INIT1=16'h500a;
+defparam un13_lock_cry_9_0.INJECT1_0="NO";
+defparam un13_lock_cry_9_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_11_0 (
+       .A0(un13_lock_11),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_12),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_10),
+       .COUT(un13_lock_cry_12),
+       .S0(un13_lock_cry_11_0_S0),
+       .S1(un13_lock_cry_11_0_S1)
+);
+defparam un13_lock_cry_11_0.INIT0=16'h500a;
+defparam un13_lock_cry_11_0.INIT1=16'h500a;
+defparam un13_lock_cry_11_0.INJECT1_0="NO";
+defparam un13_lock_cry_11_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_13_0 (
+       .A0(un13_lock_13),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_14),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_12),
+       .COUT(un13_lock_cry_14),
+       .S0(un13_lock_cry_13_0_S0),
+       .S1(un13_lock_cry_13_0_S1)
+);
+defparam un13_lock_cry_13_0.INIT0=16'h500a;
+defparam un13_lock_cry_13_0.INIT1=16'h500a;
+defparam un13_lock_cry_13_0.INJECT1_0="NO";
+defparam un13_lock_cry_13_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_15_0 (
+       .A0(un13_lock_15),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_16),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_14),
+       .COUT(un13_lock_cry_16),
+       .S0(un13_lock_cry_15_0_S0),
+       .S1(un13_lock_cry_15_0_S1)
+);
+defparam un13_lock_cry_15_0.INIT0=16'h500a;
+defparam un13_lock_cry_15_0.INIT1=16'h500a;
+defparam un13_lock_cry_15_0.INJECT1_0="NO";
+defparam un13_lock_cry_15_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_17_0 (
+       .A0(un13_lock_17),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_18),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_16),
+       .COUT(un13_lock_cry_18),
+       .S0(un13_lock_cry_17_0_S0),
+       .S1(un13_lock_cry_17_0_S1)
+);
+defparam un13_lock_cry_17_0.INIT0=16'h500a;
+defparam un13_lock_cry_17_0.INIT1=16'h500a;
+defparam un13_lock_cry_17_0.INJECT1_0="NO";
+defparam un13_lock_cry_17_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_19_0 (
+       .A0(un13_lock_19),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_20),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_18),
+       .COUT(un13_lock_cry_20),
+       .S0(un13_lock_cry_19_0_S0),
+       .S1(un13_lock_cry_19_0_S1)
+);
+defparam un13_lock_cry_19_0.INIT0=16'h500a;
+defparam un13_lock_cry_19_0.INIT1=16'h500a;
+defparam un13_lock_cry_19_0.INJECT1_0="NO";
+defparam un13_lock_cry_19_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_21_0 (
+       .A0(un13_lock_21),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_20),
+       .COUT(un13_lock_cry_21_0_COUT),
+       .S0(un13_lock_cry_21_0_S0),
+       .S1(un13_lock_cry_21_i)
+);
+defparam un13_lock_cry_21_0.INIT0=16'h500f;
+defparam un13_lock_cry_21_0.INIT1=16'ha003;
+defparam un13_lock_cry_21_0.INJECT1_0="NO";
+defparam un13_lock_cry_21_0.INJECT1_1="NO";
+  CCU2C un13_unlock_cry_0_0 (
+       .A0(VCC),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_0),
+       .B1(rdiff_comp_lock[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_1),
+       .COUT(un13_unlock_cry_0),
+       .S0(un13_unlock_cry_0_0_S0),
+       .S1(un13_unlock_cry_0_0_S1)
+);
+defparam un13_unlock_cry_0_0.INIT0=16'h5003;
+defparam un13_unlock_cry_0_0.INIT1=16'h900a;
+defparam un13_unlock_cry_0_0.INJECT1_0="NO";
+defparam un13_unlock_cry_0_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_1_0 (
+       .A0(un13_lock_1),
+       .B0(rdiff_comp_lock[2]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_2),
+       .B1(rdiff_comp_lock[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_0),
+       .COUT(un13_unlock_cry_2),
+       .S0(un13_unlock_cry_1_0_S0),
+       .S1(un13_unlock_cry_1_0_S1)
+);
+defparam un13_unlock_cry_1_0.INIT0=16'h900a;
+defparam un13_unlock_cry_1_0.INIT1=16'h900a;
+defparam un13_unlock_cry_1_0.INJECT1_0="NO";
+defparam un13_unlock_cry_1_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_3_0 (
+       .A0(un13_lock_3),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_4),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_2),
+       .COUT(un13_unlock_cry_4),
+       .S0(un13_unlock_cry_3_0_S0),
+       .S1(un13_unlock_cry_3_0_S1)
+);
+defparam un13_unlock_cry_3_0.INIT0=16'h500a;
+defparam un13_unlock_cry_3_0.INIT1=16'h500a;
+defparam un13_unlock_cry_3_0.INJECT1_0="NO";
+defparam un13_unlock_cry_3_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_5_0 (
+       .A0(un13_lock_5),
+       .B0(rdiff_comp_lock[2]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_6),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_4),
+       .COUT(un13_unlock_cry_6),
+       .S0(un13_unlock_cry_5_0_S0),
+       .S1(un13_unlock_cry_5_0_S1)
+);
+defparam un13_unlock_cry_5_0.INIT0=16'h900a;
+defparam un13_unlock_cry_5_0.INIT1=16'h500a;
+defparam un13_unlock_cry_5_0.INJECT1_0="NO";
+defparam un13_unlock_cry_5_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_7_0 (
+       .A0(un13_lock_7),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_8),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_6),
+       .COUT(un13_unlock_cry_8),
+       .S0(un13_unlock_cry_7_0_S0),
+       .S1(un13_unlock_cry_7_0_S1)
+);
+defparam un13_unlock_cry_7_0.INIT0=16'h500a;
+defparam un13_unlock_cry_7_0.INIT1=16'h500a;
+defparam un13_unlock_cry_7_0.INJECT1_0="NO";
+defparam un13_unlock_cry_7_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_9_0 (
+       .A0(un13_lock_9),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_10),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_8),
+       .COUT(un13_unlock_cry_10),
+       .S0(un13_unlock_cry_9_0_S0),
+       .S1(un13_unlock_cry_9_0_S1)
+);
+defparam un13_unlock_cry_9_0.INIT0=16'h500a;
+defparam un13_unlock_cry_9_0.INIT1=16'h500a;
+defparam un13_unlock_cry_9_0.INJECT1_0="NO";
+defparam un13_unlock_cry_9_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_11_0 (
+       .A0(un13_lock_11),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_12),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_10),
+       .COUT(un13_unlock_cry_12),
+       .S0(un13_unlock_cry_11_0_S0),
+       .S1(un13_unlock_cry_11_0_S1)
+);
+defparam un13_unlock_cry_11_0.INIT0=16'h500a;
+defparam un13_unlock_cry_11_0.INIT1=16'h500a;
+defparam un13_unlock_cry_11_0.INJECT1_0="NO";
+defparam un13_unlock_cry_11_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_13_0 (
+       .A0(un13_lock_13),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_14),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_12),
+       .COUT(un13_unlock_cry_14),
+       .S0(un13_unlock_cry_13_0_S0),
+       .S1(un13_unlock_cry_13_0_S1)
+);
+defparam un13_unlock_cry_13_0.INIT0=16'h500a;
+defparam un13_unlock_cry_13_0.INIT1=16'h500a;
+defparam un13_unlock_cry_13_0.INJECT1_0="NO";
+defparam un13_unlock_cry_13_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_15_0 (
+       .A0(un13_lock_15),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_16),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_14),
+       .COUT(un13_unlock_cry_16),
+       .S0(un13_unlock_cry_15_0_S0),
+       .S1(un13_unlock_cry_15_0_S1)
+);
+defparam un13_unlock_cry_15_0.INIT0=16'h500a;
+defparam un13_unlock_cry_15_0.INIT1=16'h500a;
+defparam un13_unlock_cry_15_0.INJECT1_0="NO";
+defparam un13_unlock_cry_15_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_17_0 (
+       .A0(un13_lock_17),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_18),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_16),
+       .COUT(un13_unlock_cry_18),
+       .S0(un13_unlock_cry_17_0_S0),
+       .S1(un13_unlock_cry_17_0_S1)
+);
+defparam un13_unlock_cry_17_0.INIT0=16'h500a;
+defparam un13_unlock_cry_17_0.INIT1=16'h500a;
+defparam un13_unlock_cry_17_0.INJECT1_0="NO";
+defparam un13_unlock_cry_17_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_19_0 (
+       .A0(un13_lock_19),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_20),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_18),
+       .COUT(un13_unlock_cry_20),
+       .S0(un13_unlock_cry_19_0_S0),
+       .S1(un13_unlock_cry_19_0_S1)
+);
+defparam un13_unlock_cry_19_0.INIT0=16'h500a;
+defparam un13_unlock_cry_19_0.INIT1=16'h500a;
+defparam un13_unlock_cry_19_0.INJECT1_0="NO";
+defparam un13_unlock_cry_19_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_21_0 (
+       .A0(un13_lock_21),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_20),
+       .COUT(un13_unlock_cry_21_0_COUT),
+       .S0(un13_unlock_cry_21_0_S0),
+       .S1(un13_unlock_cry_21)
+);
+defparam un13_unlock_cry_21_0.INIT0=16'h500f;
+defparam un13_unlock_cry_21_0.INIT1=16'h5003;
+defparam un13_unlock_cry_21_0.INJECT1_0="NO";
+defparam un13_unlock_cry_21_0.INJECT1_1="NO";
+//@16:1801
+//@8:424
+// @16:1211
+  sync_0s phb_sync_inst (
+       .phb(phb),
+       .rhb_sync(rhb_sync),
+       .sli_rst(sli_rst),
+       .pll_refclki(pll_refclki)
+);
+// @16:1220
+  sync_0s_6 rtc_sync_inst (
+       .rtc_pul(rtc_pul),
+       .ppul_sync(ppul_sync),
+       .sli_rst(sli_rst),
+       .tx_pclk(tx_pclk)
+);
+// @16:1228
+  sync_0s_0 pdiff_sync_inst (
+       .ppul_sync(ppul_sync),
+       .pdiff_sync(pdiff_sync),
+       .sli_rst(sli_rst),
+       .pll_refclki(pll_refclki)
+);
+  VHI VCC_0 (
+       .Z(VCC)
+);
+// @16:865
+  VLO GND_cZ (
+       .Z(GND)
+);
+endmodule /* sgmii_ecp5sll_core_Z1_layer1 */
+
+module sgmii_ecp5rsl_core_Z2_layer1 (
+  rx_pcs_rst_c,
+  tx_pcs_rst_c,
+  serdes_rst_dual_c,
+  tx_serdes_rst_c,
+  rsl_rx_pcs_rst_c,
+  rsl_tx_pcs_rst_c,
+  rsl_tx_serdes_rst_c,
+  rsl_tx_rdy,
+  pll_lock_i,
+  pll_refclki,
+  rsl_rx_rdy,
+  rsl_rst,
+  rxrefclk,
+  rsl_disable,
+  rx_serdes_rst_c,
+  rst_dual_c,
+  rx_cdr_lol_s,
+  rx_los_low_s,
+  rsl_rx_serdes_rst_c,
+  rsl_serdes_rst_dual_c
+)
+;
+input rx_pcs_rst_c ;
+input tx_pcs_rst_c ;
+input serdes_rst_dual_c ;
+input tx_serdes_rst_c ;
+output rsl_rx_pcs_rst_c ;
+output rsl_tx_pcs_rst_c ;
+output rsl_tx_serdes_rst_c ;
+output rsl_tx_rdy ;
+input pll_lock_i ;
+input pll_refclki ;
+output rsl_rx_rdy ;
+input rsl_rst ;
+input rxrefclk ;
+input rsl_disable ;
+input rx_serdes_rst_c ;
+input rst_dual_c ;
+input rx_cdr_lol_s ;
+input rx_los_low_s ;
+output rsl_rx_serdes_rst_c ;
+output rsl_serdes_rst_dual_c ;
+wire rx_pcs_rst_c ;
+wire tx_pcs_rst_c ;
+wire serdes_rst_dual_c ;
+wire tx_serdes_rst_c ;
+wire rsl_rx_pcs_rst_c ;
+wire rsl_tx_pcs_rst_c ;
+wire rsl_tx_serdes_rst_c ;
+wire rsl_tx_rdy ;
+wire pll_lock_i ;
+wire pll_refclki ;
+wire rsl_rx_rdy ;
+wire rsl_rst ;
+wire rxrefclk ;
+wire rsl_disable ;
+wire rx_serdes_rst_c ;
+wire rst_dual_c ;
+wire rx_cdr_lol_s ;
+wire rx_los_low_s ;
+wire rsl_rx_serdes_rst_c ;
+wire rsl_serdes_rst_dual_c ;
+wire [1:0] rxs_cnt;
+wire [1:0] rxs_cnt_3;
+wire [0:0] rxpr_appd_RNO;
+wire [2:0] plol0_cnt;
+wire [2:0] plol0_cnt_3;
+wire [0:0] rxsr_appd;
+wire [1:0] rxs_cnt_QN;
+wire [3:0] rlos_db_cnt;
+wire [3:0] rlos_db_cnt_QN;
+wire [17:0] rlols0_cnt_s;
+wire [17:0] rlols0_cnt;
+wire [17:0] rlols0_cnt_QN;
+wire [3:0] rlol_db_cnt;
+wire [3:0] rlol_db_cnt_QN;
+wire [18:0] rlol1_cnt_s;
+wire [18:0] rlol1_cnt;
+wire [18:0] rlol1_cnt_QN;
+wire [11:0] rxr_wt_cnt_s;
+wire [11:0] rxr_wt_cnt;
+wire [11:0] rxr_wt_cnt_QN;
+wire [0:0] rxsr_appd_QN;
+wire [0:0] rxpr_appd;
+wire [0:0] rxpr_appd_QN;
+wire [1:0] txs_cnt;
+wire [1:0] txs_cnt_QN;
+wire [1:1] txs_cnt_RNO;
+wire [1:0] txp_cnt;
+wire [1:0] txp_cnt_QN;
+wire [1:1] txp_cnt_RNO;
+wire [19:0] plol_cnt_s;
+wire [19:0] plol_cnt;
+wire [19:0] plol_cnt_QN;
+wire [2:0] plol0_cnt_QN;
+wire [11:0] txr_wt_cnt_s;
+wire [11:0] txr_wt_cnt;
+wire [11:0] txr_wt_cnt_QN;
+wire [0:0] txpr_appd;
+wire [0:0] txpr_appd_QN;
+wire [0:0] un1_rlol_db_cnt_zero;
+wire [0:0] un1_rlos_db_cnt_zero;
+wire [0:0] un1_rlol_db_cnt_zero_bm;
+wire [0:0] un1_rlol_db_cnt_zero_am;
+wire [0:0] un1_rlos_db_cnt_zero_bm;
+wire [0:0] un1_rlos_db_cnt_zero_am;
+wire [16:0] rlol1_cnt_cry;
+wire [0:0] rlol1_cnt_cry_0_S0;
+wire [17:17] rlol1_cnt_cry_0_COUT;
+wire [16:0] rlols0_cnt_cry;
+wire [0:0] rlols0_cnt_cry_0_S0;
+wire [17:17] rlols0_cnt_s_0_COUT;
+wire [17:17] rlols0_cnt_s_0_S1;
+wire [10:0] txr_wt_cnt_cry;
+wire [0:0] txr_wt_cnt_cry_0_S0;
+wire [11:11] txr_wt_cnt_s_0_COUT;
+wire [11:11] txr_wt_cnt_s_0_S1;
+wire [10:0] rxr_wt_cnt_cry;
+wire [0:0] rxr_wt_cnt_cry_0_S0;
+wire [11:11] rxr_wt_cnt_s_0_COUT;
+wire [11:11] rxr_wt_cnt_s_0_S1;
+wire [18:0] plol_cnt_cry;
+wire [0:0] plol_cnt_cry_0_S0;
+wire [19:19] plol_cnt_s_0_COUT;
+wire [19:19] plol_cnt_s_0_S1;
+wire rxs_rst ;
+wire VCC ;
+wire rlos_db_p1 ;
+wire rlos_db ;
+wire rxp_rst25 ;
+wire rlol_db ;
+wire un1_rui_rst_dual_c_1_1 ;
+wire plol0_cnt9 ;
+wire waita_plol0 ;
+wire rx_any_rst ;
+wire un3_rx_all_well_2 ;
+wire un17_rxr_wt_tc ;
+wire rx_all_well ;
+wire un3_rx_all_well_1 ;
+wire rxr_wt_cnt9 ;
+wire un1_rui_rst_dual_c_1_i ;
+wire rlol1_cnt_tc_1 ;
+wire rlol1_cnt_scalar ;
+wire rxr_wt_en ;
+wire rxr_wt_cnte ;
+wire un18_txr_wt_tc ;
+wire tx_any_rst ;
+wire pll_lol_p2 ;
+wire un2_plol_fedge_5_i ;
+wire N_2160_0 ;
+wire waita_rlols06 ;
+wire un1_rlols0_cnt_tc ;
+wire waita_rlols0 ;
+wire waita_rlols0_QN ;
+wire wait_calib_RNO ;
+wire un1_rlos_fedge_1 ;
+wire wait_calib ;
+wire wait_calib_QN ;
+wire rxs_rst6 ;
+wire un1_rxs_cnt_tc ;
+wire rxs_rst_QN ;
+wire un2_rlos_redge_1_i ;
+wire rxp_rst2 ;
+wire rxp_rst2_QN ;
+wire rlos_p1 ;
+wire rlos_p2 ;
+wire rlos_p2_QN ;
+wire rlos_p1_QN ;
+wire rlos_db_p1_QN ;
+wire rlos_db_cnt_axb_0 ;
+wire rlos_db_cnt_cry_1_0_S0 ;
+wire rlos_db_cnt_cry_1_0_S1 ;
+wire rlos_db_cnt_s_3_0_S0 ;
+wire un1_rlos_db_cnt_max ;
+wire rlos_db_QN ;
+wire rlols0_cnte ;
+wire rlol_p1 ;
+wire rlol_p2 ;
+wire rlol_p2_QN ;
+wire rlol_p1_QN ;
+wire rlol_db_p1 ;
+wire rlol_db_p1_QN ;
+wire rlol_db_cnt_axb_0 ;
+wire rlol_db_cnt_cry_1_0_S0 ;
+wire rlol_db_cnt_cry_1_0_S1 ;
+wire rlol_db_cnt_s_3_0_S0 ;
+wire un1_rlol_db_cnt_max ;
+wire rlol_db_QN ;
+wire rlol1_cnte ;
+wire rxsdr_appd_2 ;
+wire rxsdr_appd_4 ;
+wire rxsdr_appd_QN ;
+wire un1_dual_or_rserd_rst_2_i ;
+wire rxr_wt_en_QN ;
+wire rxdpr_appd ;
+wire rxdpr_appd_QN ;
+wire ruo_rx_rdyr_QN ;
+wire un2_rdo_serdes_rst_dual_c_2_i ;
+wire plol_fedge ;
+wire un1_plol0_cnt_tc_1_i ;
+wire waita_plol0_QN ;
+wire un1_plol_cnt_tc ;
+wire un2_plol_cnt_tc ;
+wire txs_rst ;
+wire txs_rst_QN ;
+wire N_10_i ;
+wire un9_plol0_cnt_tc ;
+wire un1_plol0_cnt_tc_1 ;
+wire txp_rst ;
+wire txp_rst_QN ;
+wire N_11_i ;
+wire pll_lol_p3 ;
+wire pll_lol_p3_QN ;
+wire pll_lol_p1 ;
+wire pll_lol_p2_QN ;
+wire pll_lol_p1_QN ;
+wire txsr_appd_2 ;
+wire txsr_appd_4 ;
+wire txsr_appd_QN ;
+wire un1_dual_or_serd_rst_1_1 ;
+wire un1_dual_or_serd_rst_1_i ;
+wire txr_wt_en ;
+wire txr_wt_en_QN ;
+wire txr_wt_cnte ;
+wire un2_plol_fedge_2 ;
+wire un2_plol_fedge_3_i ;
+wire txdpr_appd ;
+wire txdpr_appd_QN ;
+wire un2_plol_fedge_5_1 ;
+wire ruo_tx_rdyr_QN ;
+wire un2_plol_fedge_8_i ;
+wire rlols0_cnt_tc_1 ;
+wire rlos_redge ;
+wire rlols0_cnt11_0 ;
+wire plol_cnt_scalar ;
+wire rlols0_cnt_scalar ;
+wire un8_rxs_cnt_tc ;
+wire un1_txsr_appd ;
+wire un1_dual_or_rserd_rst_2_0 ;
+wire un1_rxsdr_or_sr_appd ;
+wire un2_rdo_serdes_rst_dual_c_1_1 ;
+wire rlols0_cnt_tc_1_10 ;
+wire rlols0_cnt_tc_1_11 ;
+wire rlols0_cnt_tc_1_12 ;
+wire rlols0_cnt_tc_1_13 ;
+wire rlol1_cnt_tc_1_11 ;
+wire rlol1_cnt_tc_1_12 ;
+wire rlol1_cnt_tc_1_13 ;
+wire rlol1_cnt_tc_1_14 ;
+wire un1_plol_cnt_tc_11 ;
+wire un1_plol_cnt_tc_12 ;
+wire un1_plol_cnt_tc_13 ;
+wire un1_plol_cnt_tc_14 ;
+wire CO0_2 ;
+wire un17_rxr_wt_tc_6 ;
+wire un17_rxr_wt_tc_7 ;
+wire un17_rxr_wt_tc_8 ;
+wire un18_txr_wt_tc_6 ;
+wire un18_txr_wt_tc_7 ;
+wire un18_txr_wt_tc_8 ;
+wire rlols0_cnt_tc_1_9 ;
+wire un1_plol_cnt_tc_10 ;
+wire rlol1_cnt_tc_1_10 ;
+wire txr_wt_cnt_scalar ;
+wire rlos_db_cnt_cry_0 ;
+wire rlos_db_cnt_cry_0_0_S0 ;
+wire rlos_db_cnt_cry_0_0_S1 ;
+wire rlos_db_cnt_cry_2 ;
+wire rlos_db_cnt_s_3_0_COUT ;
+wire rlos_db_cnt_s_3_0_S1 ;
+wire rlol_db_cnt_cry_0 ;
+wire rlol_db_cnt_cry_0_0_S0 ;
+wire rlol_db_cnt_cry_0_0_S1 ;
+wire rlol_db_cnt_cry_2 ;
+wire rlol_db_cnt_s_3_0_COUT ;
+wire rlol_db_cnt_s_3_0_S1 ;
+wire GND ;
+wire N_1 ;
+wire N_2 ;
+wire N_3 ;
+wire N_4 ;
+wire N_5 ;
+wire N_6 ;
+wire N_7 ;
+  LUT4 \genblk2.rxs_cnt_RNO[0]  (
+       .A(rxs_rst),
+       .B(rxs_cnt[0]),
+       .C(rxs_cnt[1]),
+       .D(VCC),
+       .Z(rxs_cnt_3[0])
+);
+defparam \genblk2.rxs_cnt_RNO[0] .init=16'h2626;
+  LUT4 \genblk2.genblk3.lfor[0].rxpr_appd_RNO[0]  (
+       .A(rsl_serdes_rst_dual_c),
+       .B(rsl_rx_serdes_rst_c),
+       .C(rx_los_low_s),
+       .D(rx_cdr_lol_s),
+       .Z(rxpr_appd_RNO[0])
+);
+defparam \genblk2.genblk3.lfor[0].rxpr_appd_RNO[0] .init=16'h0001;
+  LUT4 \genblk2.rxp_rst2_RNO  (
+       .A(rsl_serdes_rst_dual_c),
+       .B(rsl_rx_serdes_rst_c),
+       .C(rlos_db_p1),
+       .D(rlos_db),
+       .Z(rxp_rst25)
+);
+defparam \genblk2.rxp_rst2_RNO .init=16'hEFEE;
+  LUT4 \genblk2.genblk3.rxdpr_appd_RNO  (
+       .A(rsl_serdes_rst_dual_c),
+       .B(rsl_rx_serdes_rst_c),
+       .C(rlos_db),
+       .D(rlol_db),
+       .Z(un1_rui_rst_dual_c_1_1)
+);
+defparam \genblk2.genblk3.rxdpr_appd_RNO .init=16'h0001;
+  LUT4 \genblk1.plol0_cnt_RNO[1]  (
+       .A(plol0_cnt[1]),
+       .B(plol0_cnt9),
+       .C(waita_plol0),
+       .D(plol0_cnt[0]),
+       .Z(plol0_cnt_3[1])
+);
+defparam \genblk1.plol0_cnt_RNO[1] .init=16'h1222;
+  LUT4 \genblk2.genblk3.ruo_rx_rdyr_RNO  (
+       .A(rx_any_rst),
+       .B(rlos_db),
+       .C(rlol_db),
+       .D(VCC),
+       .Z(un3_rx_all_well_2)
+);
+defparam \genblk2.genblk3.ruo_rx_rdyr_RNO .init=16'h0101;
+  LUT4 \genblk2.genblk3.rxr_wt_en_RNO  (
+       .A(un17_rxr_wt_tc),
+       .B(rsl_serdes_rst_dual_c),
+       .C(rsl_rx_serdes_rst_c),
+       .D(rx_all_well),
+       .Z(un3_rx_all_well_1)
+);
+defparam \genblk2.genblk3.rxr_wt_en_RNO .init=16'h0100;
+  LUT4 rx_any_rst_RNIFD021 (
+       .A(rx_any_rst),
+       .B(un17_rxr_wt_tc),
+       .C(rlos_db),
+       .D(rlol_db),
+       .Z(rxr_wt_cnt9)
+);
+defparam rx_any_rst_RNIFD021.init=16'hFFFE;
+  LUT4 \genblk2.genblk3.rxdpr_appd_RNO_0  (
+       .A(rst_dual_c),
+       .B(rsl_serdes_rst_dual_c),
+       .C(rsl_rx_serdes_rst_c),
+       .D(rx_all_well),
+       .Z(un1_rui_rst_dual_c_1_i)
+);
+defparam \genblk2.genblk3.rxdpr_appd_RNO_0 .init=16'hFEFF;
+  LUT4 \genblk2.rlos_db_p1_RNIS0OP  (
+       .A(rlol1_cnt_tc_1),
+       .B(rxs_rst),
+       .C(rlos_db_p1),
+       .D(rlos_db),
+       .Z(rlol1_cnt_scalar)
+);
+defparam \genblk2.rlos_db_p1_RNIS0OP .init=16'h1011;
+  LUT4 \genblk2.genblk3.rxr_wt_en_RNIQF0H1  (
+       .A(rxr_wt_en),
+       .B(rx_any_rst),
+       .C(rx_all_well),
+       .D(un17_rxr_wt_tc),
+       .Z(rxr_wt_cnte)
+);
+defparam \genblk2.genblk3.rxr_wt_en_RNIQF0H1 .init=16'hFFEF;
+  LUT4 \genblk1.genblk2.ruo_tx_rdyr_RNO  (
+       .A(un18_txr_wt_tc),
+       .B(tx_any_rst),
+       .C(pll_lol_p2),
+       .D(VCC),
+       .Z(un2_plol_fedge_5_i)
+);
+defparam \genblk1.genblk2.ruo_tx_rdyr_RNO .init=16'hFEFE;
+  LUT4 \genblk2.genblk3.lfor[0].rxsr_appd_RNO[0]  (
+       .A(rxsr_appd[0]),
+       .B(rx_serdes_rst_c),
+       .C(rxs_rst),
+       .D(rsl_disable),
+       .Z(N_2160_0)
+);
+defparam \genblk2.genblk3.lfor[0].rxsr_appd_RNO[0] .init=16'hEEFE;
+// @16:759
+  FD1P3DX \genblk2.waita_rlols0  (
+       .D(waita_rlols06),
+       .SP(un1_rlols0_cnt_tc),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(waita_rlols0)
+);
+// @16:656
+  FD1P3BX \genblk2.wait_calib  (
+       .D(wait_calib_RNO),
+       .SP(un1_rlos_fedge_1),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(wait_calib)
+);
+// @16:694
+  FD1P3DX \genblk2.rxs_rst  (
+       .D(rxs_rst6),
+       .SP(un1_rxs_cnt_tc),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxs_rst)
+);
+// @16:694
+  FD1S3DX \genblk2.rxs_cnt[0]  (
+       .D(rxs_cnt_3[0]),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxs_cnt[0])
+);
+// @16:694
+  FD1S3DX \genblk2.rxs_cnt[1]  (
+       .D(rxs_cnt_3[1]),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxs_cnt[1])
+);
+// @16:806
+  FD1P3BX \genblk2.rxp_rst2  (
+       .D(rxp_rst25),
+       .SP(un2_rlos_redge_1_i),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rxp_rst2)
+);
+// @16:567
+  FD1S3DX \genblk2.rlos_p2  (
+       .D(rlos_p1),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlos_p2)
+);
+// @16:567
+  FD1S3DX \genblk2.rlos_p1  (
+       .D(rx_los_low_s),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlos_p1)
+);
+// @16:567
+  FD1S3BX \genblk2.rlos_db_p1  (
+       .D(rlos_db),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlos_db_p1)
+);
+// @16:640
+  FD1S3BX \genblk2.rlos_db_cnt[0]  (
+       .D(rlos_db_cnt_axb_0),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlos_db_cnt[0])
+);
+// @16:640
+  FD1S3BX \genblk2.rlos_db_cnt[1]  (
+       .D(rlos_db_cnt_cry_1_0_S0),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlos_db_cnt[1])
+);
+// @16:640
+  FD1S3BX \genblk2.rlos_db_cnt[2]  (
+       .D(rlos_db_cnt_cry_1_0_S1),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlos_db_cnt[2])
+);
+// @16:640
+  FD1S3BX \genblk2.rlos_db_cnt[3]  (
+       .D(rlos_db_cnt_s_3_0_S0),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlos_db_cnt[3])
+);
+// @16:649
+  FD1P3BX \genblk2.rlos_db  (
+       .D(rlos_db_cnt[1]),
+       .SP(un1_rlos_db_cnt_max),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlos_db)
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[0]  (
+       .D(rlols0_cnt_s[0]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[0])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[1]  (
+       .D(rlols0_cnt_s[1]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[1])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[2]  (
+       .D(rlols0_cnt_s[2]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[2])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[3]  (
+       .D(rlols0_cnt_s[3]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[3])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[4]  (
+       .D(rlols0_cnt_s[4]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[4])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[5]  (
+       .D(rlols0_cnt_s[5]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[5])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[6]  (
+       .D(rlols0_cnt_s[6]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[6])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[7]  (
+       .D(rlols0_cnt_s[7]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[7])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[8]  (
+       .D(rlols0_cnt_s[8]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[8])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[9]  (
+       .D(rlols0_cnt_s[9]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[9])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[10]  (
+       .D(rlols0_cnt_s[10]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[10])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[11]  (
+       .D(rlols0_cnt_s[11]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[11])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[12]  (
+       .D(rlols0_cnt_s[12]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[12])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[13]  (
+       .D(rlols0_cnt_s[13]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[13])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[14]  (
+       .D(rlols0_cnt_s[14]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[14])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[15]  (
+       .D(rlols0_cnt_s[15]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[15])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[16]  (
+       .D(rlols0_cnt_s[16]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[16])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[17]  (
+       .D(rlols0_cnt_s[17]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[17])
+);
+// @16:567
+  FD1S3DX \genblk2.rlol_p2  (
+       .D(rlol_p1),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol_p2)
+);
+// @16:567
+  FD1S3DX \genblk2.rlol_p1  (
+       .D(rx_cdr_lol_s),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol_p1)
+);
+// @16:567
+  FD1S3BX \genblk2.rlol_db_p1  (
+       .D(rlol_db),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlol_db_p1)
+);
+// @16:624
+  FD1S3BX \genblk2.rlol_db_cnt[0]  (
+       .D(rlol_db_cnt_axb_0),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlol_db_cnt[0])
+);
+// @16:624
+  FD1S3BX \genblk2.rlol_db_cnt[1]  (
+       .D(rlol_db_cnt_cry_1_0_S0),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlol_db_cnt[1])
+);
+// @16:624
+  FD1S3BX \genblk2.rlol_db_cnt[2]  (
+       .D(rlol_db_cnt_cry_1_0_S1),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlol_db_cnt[2])
+);
+// @16:624
+  FD1S3BX \genblk2.rlol_db_cnt[3]  (
+       .D(rlol_db_cnt_s_3_0_S0),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlol_db_cnt[3])
+);
+// @16:633
+  FD1P3BX \genblk2.rlol_db  (
+       .D(rlol_db_cnt[1]),
+       .SP(un1_rlol_db_cnt_max),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlol_db)
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[0]  (
+       .D(rlol1_cnt_s[0]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[0])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[1]  (
+       .D(rlol1_cnt_s[1]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[1])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[2]  (
+       .D(rlol1_cnt_s[2]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[2])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[3]  (
+       .D(rlol1_cnt_s[3]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[3])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[4]  (
+       .D(rlol1_cnt_s[4]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[4])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[5]  (
+       .D(rlol1_cnt_s[5]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[5])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[6]  (
+       .D(rlol1_cnt_s[6]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[6])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[7]  (
+       .D(rlol1_cnt_s[7]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[7])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[8]  (
+       .D(rlol1_cnt_s[8]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[8])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[9]  (
+       .D(rlol1_cnt_s[9]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[9])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[10]  (
+       .D(rlol1_cnt_s[10]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[10])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[11]  (
+       .D(rlol1_cnt_s[11]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[11])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[12]  (
+       .D(rlol1_cnt_s[12]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[12])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[13]  (
+       .D(rlol1_cnt_s[13]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[13])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[14]  (
+       .D(rlol1_cnt_s[14]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[14])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[15]  (
+       .D(rlol1_cnt_s[15]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[15])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[16]  (
+       .D(rlol1_cnt_s[16]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[16])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[17]  (
+       .D(rlol1_cnt_s[17]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[17])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[18]  (
+       .D(rlol1_cnt_s[18]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[18])
+);
+// @16:865
+  FD1S3BX \genblk2.genblk3.rxsdr_appd  (
+       .D(rxsdr_appd_2),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rxsdr_appd_4)
+);
+// @16:900
+  FD1P3DX \genblk2.genblk3.rxr_wt_en  (
+       .D(un3_rx_all_well_1),
+       .SP(un1_dual_or_rserd_rst_2_i),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_en)
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[0]  (
+       .D(rxr_wt_cnt_s[0]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[0])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[1]  (
+       .D(rxr_wt_cnt_s[1]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[1])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[2]  (
+       .D(rxr_wt_cnt_s[2]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[2])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[3]  (
+       .D(rxr_wt_cnt_s[3]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[3])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[4]  (
+       .D(rxr_wt_cnt_s[4]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[4])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[5]  (
+       .D(rxr_wt_cnt_s[5]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[5])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[6]  (
+       .D(rxr_wt_cnt_s[6]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[6])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[7]  (
+       .D(rxr_wt_cnt_s[7]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[7])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[8]  (
+       .D(rxr_wt_cnt_s[8]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[8])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[9]  (
+       .D(rxr_wt_cnt_s[9]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[9])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[10]  (
+       .D(rxr_wt_cnt_s[10]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[10])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[11]  (
+       .D(rxr_wt_cnt_s[11]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[11])
+);
+// @16:871
+  FD1P3DX \genblk2.genblk3.rxdpr_appd  (
+       .D(un1_rui_rst_dual_c_1_1),
+       .SP(un1_rui_rst_dual_c_1_i),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxdpr_appd)
+);
+// @16:920
+  FD1P3DX \genblk2.genblk3.ruo_rx_rdyr  (
+       .D(un3_rx_all_well_2),
+       .SP(rxr_wt_cnt9),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rsl_rx_rdy)
+);
+// @16:882
+  FD1S3DX \genblk2.genblk3.lfor[0].rxsr_appd[0]  (
+       .D(N_2160_0),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxsr_appd[0])
+);
+// @16:888
+  FD1P3DX \genblk2.genblk3.lfor[0].rxpr_appd[0]  (
+       .D(rxpr_appd_RNO[0]),
+       .SP(un2_rdo_serdes_rst_dual_c_2_i),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxpr_appd[0])
+);
+// @16:443
+  FD1P3DX \genblk1.waita_plol0  (
+       .D(plol_fedge),
+       .SP(un1_plol0_cnt_tc_1_i),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(waita_plol0)
+);
+// @16:422
+  FD1P3DX \genblk1.txs_rst  (
+       .D(un1_plol_cnt_tc),
+       .SP(un2_plol_cnt_tc),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txs_rst)
+);
+// @16:422
+  FD1S3DX \genblk1.txs_cnt[0]  (
+       .D(N_10_i),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txs_cnt[0])
+);
+// @16:422
+  FD1S3DX \genblk1.txs_cnt[1]  (
+       .D(txs_cnt_RNO[1]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txs_cnt[1])
+);
+// @16:461
+  FD1P3DX \genblk1.txp_rst  (
+       .D(un9_plol0_cnt_tc),
+       .SP(un1_plol0_cnt_tc_1),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txp_rst)
+);
+// @16:461
+  FD1S3DX \genblk1.txp_cnt[0]  (
+       .D(N_11_i),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txp_cnt[0])
+);
+// @16:461
+  FD1S3DX \genblk1.txp_cnt[1]  (
+       .D(txp_cnt_RNO[1]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txp_cnt[1])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[0]  (
+       .D(plol_cnt_s[0]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[0])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[1]  (
+       .D(plol_cnt_s[1]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[1])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[2]  (
+       .D(plol_cnt_s[2]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[2])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[3]  (
+       .D(plol_cnt_s[3]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[3])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[4]  (
+       .D(plol_cnt_s[4]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[4])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[5]  (
+       .D(plol_cnt_s[5]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[5])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[6]  (
+       .D(plol_cnt_s[6]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[6])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[7]  (
+       .D(plol_cnt_s[7]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[7])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[8]  (
+       .D(plol_cnt_s[8]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[8])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[9]  (
+       .D(plol_cnt_s[9]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[9])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[10]  (
+       .D(plol_cnt_s[10]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[10])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[11]  (
+       .D(plol_cnt_s[11]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[11])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[12]  (
+       .D(plol_cnt_s[12]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[12])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[13]  (
+       .D(plol_cnt_s[13]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[13])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[14]  (
+       .D(plol_cnt_s[14]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[14])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[15]  (
+       .D(plol_cnt_s[15]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[15])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[16]  (
+       .D(plol_cnt_s[16]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[16])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[17]  (
+       .D(plol_cnt_s[17]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[17])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[18]  (
+       .D(plol_cnt_s[18]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[18])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[19]  (
+       .D(plol_cnt_s[19]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[19])
+);
+// @16:451
+  FD1S3DX \genblk1.plol0_cnt[0]  (
+       .D(plol0_cnt_3[0]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol0_cnt[0])
+);
+// @16:451
+  FD1S3DX \genblk1.plol0_cnt[1]  (
+       .D(plol0_cnt_3[1]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol0_cnt[1])
+);
+// @16:451
+  FD1S3DX \genblk1.plol0_cnt[2]  (
+       .D(plol0_cnt_3[2]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol0_cnt[2])
+);
+// @16:398
+  FD1S3DX \genblk1.pll_lol_p3  (
+       .D(pll_lol_p2),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(pll_lol_p3)
+);
+// @16:398
+  FD1S3DX \genblk1.pll_lol_p2  (
+       .D(pll_lol_p1),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(pll_lol_p2)
+);
+// @16:398
+  FD1S3DX \genblk1.pll_lol_p1  (
+       .D(pll_lock_i),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(pll_lol_p1)
+);
+// @16:492
+  FD1S3BX \genblk1.genblk2.txsr_appd  (
+       .D(txsr_appd_2),
+       .CK(pll_refclki),
+       .PD(rsl_rst),
+       .Q(txsr_appd_4)
+);
+// @16:519
+  FD1P3DX \genblk1.genblk2.txr_wt_en  (
+       .D(un1_dual_or_serd_rst_1_1),
+       .SP(un1_dual_or_serd_rst_1_i),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_en)
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[0]  (
+       .D(txr_wt_cnt_s[0]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[0])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[1]  (
+       .D(txr_wt_cnt_s[1]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[1])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[2]  (
+       .D(txr_wt_cnt_s[2]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[2])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[3]  (
+       .D(txr_wt_cnt_s[3]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[3])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[4]  (
+       .D(txr_wt_cnt_s[4]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[4])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[5]  (
+       .D(txr_wt_cnt_s[5]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[5])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[6]  (
+       .D(txr_wt_cnt_s[6]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[6])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[7]  (
+       .D(txr_wt_cnt_s[7]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[7])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[8]  (
+       .D(txr_wt_cnt_s[8]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[8])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[9]  (
+       .D(txr_wt_cnt_s[9]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[9])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[10]  (
+       .D(txr_wt_cnt_s[10]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[10])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[11]  (
+       .D(txr_wt_cnt_s[11]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[11])
+);
+// @16:498
+  FD1P3DX \genblk1.genblk2.txdpr_appd  (
+       .D(un2_plol_fedge_2),
+       .SP(un2_plol_fedge_3_i),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txdpr_appd)
+);
+// @16:537
+  FD1P3DX \genblk1.genblk2.ruo_tx_rdyr  (
+       .D(un2_plol_fedge_5_1),
+       .SP(un2_plol_fedge_5_i),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(rsl_tx_rdy)
+);
+// @16:509
+  FD1P3DX \genblk1.genblk2.mfor[0].txpr_appd[0]  (
+       .D(un2_plol_fedge_2),
+       .SP(un2_plol_fedge_8_i),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txpr_appd[0])
+);
+// @16:422
+  LUT4 \genblk1.txs_cnt_RNO[0]  (
+       .A(txs_cnt[0]),
+       .B(txs_rst),
+       .C(un1_plol_cnt_tc),
+       .D(VCC),
+       .Z(N_10_i)
+);
+defparam \genblk1.txs_cnt_RNO[0] .init=16'hA6A6;
+// @16:434
+  LUT4 \genblk1.txs_cnt_RNO[1]  (
+       .A(txs_cnt[0]),
+       .B(txs_cnt[1]),
+       .C(txs_rst),
+       .D(un1_plol_cnt_tc),
+       .Z(txs_cnt_RNO[1])
+);
+defparam \genblk1.txs_cnt_RNO[1] .init=16'hCC6C;
+// @16:806
+  LUT4 \genblk2.rxp_rst2_RNO_0  (
+       .A(rlols0_cnt_tc_1),
+       .B(rlos_redge),
+       .C(rsl_rx_serdes_rst_c),
+       .D(rsl_serdes_rst_dual_c),
+       .Z(un2_rlos_redge_1_i)
+);
+defparam \genblk2.rxp_rst2_RNO_0 .init=16'hFFFE;
+// @16:519
+  LUT4 \genblk1.genblk2.txr_wt_en_RNO  (
+       .A(txpr_appd[0]),
+       .B(pll_lol_p2),
+       .C(un1_dual_or_serd_rst_1_1),
+       .D(rsl_tx_rdy),
+       .Z(un1_dual_or_serd_rst_1_i)
+);
+defparam \genblk1.genblk2.txr_wt_en_RNO .init=16'h0F2F;
+// @16:317
+  LUT4 \genblk2.rxs_rst6  (
+       .A(rlol_db),
+       .B(rlos_db),
+       .C(rlol1_cnt_tc_1),
+       .D(VCC),
+       .Z(rxs_rst6)
+);
+defparam \genblk2.rxs_rst6 .init=16'h2020;
+// @8:394
+  LUT4 \genblk2.wait_calib_RNIKRP81  (
+       .A(rxs_rst),
+       .B(wait_calib),
+       .C(rlol1_cnt_tc_1),
+       .D(rlos_redge),
+       .Z(rlol1_cnte)
+);
+defparam \genblk2.wait_calib_RNIKRP81 .init=16'hFFFE;
+// @8:394
+  LUT4 \genblk2.waita_rlols0_RNI266C  (
+       .A(rlols0_cnt11_0),
+       .B(waita_rlols0),
+       .C(rlols0_cnt_tc_1),
+       .D(VCC),
+       .Z(rlols0_cnte)
+);
+defparam \genblk2.waita_rlols0_RNI266C .init=16'hFEFE;
+// @16:412
+  LUT4 \genblk1.plol_cnt11_i  (
+       .A(pll_lol_p2),
+       .B(un1_plol_cnt_tc),
+       .C(rsl_tx_serdes_rst_c),
+       .D(VCC),
+       .Z(plol_cnt_scalar)
+);
+defparam \genblk1.plol_cnt11_i .init=16'h0202;
+// @16:778
+  LUT4 \genblk2.rlols0_cnt11_i  (
+       .A(rlols0_cnt11_0),
+       .B(rlols0_cnt_tc_1),
+       .C(VCC),
+       .D(VCC),
+       .Z(rlols0_cnt_scalar)
+);
+defparam \genblk2.rlols0_cnt11_i .init=16'h1111;
+// @16:317
+  LUT4 \genblk2.un1_rxs_cnt_tc  (
+       .A(rlol_db),
+       .B(rlos_db),
+       .C(un8_rxs_cnt_tc),
+       .D(rlol1_cnt_tc_1),
+       .Z(un1_rxs_cnt_tc)
+);
+defparam \genblk2.un1_rxs_cnt_tc .init=16'hFEFC;
+// @8:394
+  LUT4 \genblk2.wait_calib_RNO  (
+       .A(rlol_db),
+       .B(rlos_db),
+       .C(rlol1_cnt_tc_1),
+       .D(VCC),
+       .Z(wait_calib_RNO)
+);
+defparam \genblk2.wait_calib_RNO .init=16'hA3A3;
+// @16:509
+  LUT4 \genblk1.genblk2.mfor[0].txpr_appd_RNO[0]  (
+       .A(un1_txsr_appd),
+       .B(pll_lol_p2),
+       .C(rsl_serdes_rst_dual_c),
+       .D(rsl_tx_serdes_rst_c),
+       .Z(un2_plol_fedge_8_i)
+);
+defparam \genblk1.genblk2.mfor[0].txpr_appd_RNO[0] .init=16'hFFFE;
+// @16:900
+  LUT4 \genblk2.genblk3.rxr_wt_en_RNO_0  (
+       .A(un17_rxr_wt_tc),
+       .B(un1_dual_or_rserd_rst_2_0),
+       .C(rsl_rx_serdes_rst_c),
+       .D(rsl_serdes_rst_dual_c),
+       .Z(un1_dual_or_rserd_rst_2_i)
+);
+defparam \genblk2.genblk3.rxr_wt_en_RNO_0 .init=16'hFFFB;
+// @16:888
+  LUT4 \genblk2.genblk3.lfor[0].rxpr_appd_RNO_0[0]  (
+       .A(un1_rxsdr_or_sr_appd),
+       .B(un2_rdo_serdes_rst_dual_c_1_1),
+       .C(rsl_rx_serdes_rst_c),
+       .D(rsl_serdes_rst_dual_c),
+       .Z(un2_rdo_serdes_rst_dual_c_2_i)
+);
+defparam \genblk2.genblk3.lfor[0].rxpr_appd_RNO_0[0] .init=16'hFFFB;
+// @8:394
+  LUT4 \genblk1.genblk2.txr_wt_en_RNICEBT  (
+       .A(txr_wt_en),
+       .B(un18_txr_wt_tc),
+       .C(tx_any_rst),
+       .D(VCC),
+       .Z(txr_wt_cnte)
+);
+defparam \genblk1.genblk2.txr_wt_en_RNICEBT .init=16'hFEFE;
+// @16:259
+  LUT4 \genblk1.un2_plol_cnt_tc  (
+       .A(txs_cnt[0]),
+       .B(txs_cnt[1]),
+       .C(un1_plol_cnt_tc),
+       .D(VCC),
+       .Z(un2_plol_cnt_tc)
+);
+defparam \genblk1.un2_plol_cnt_tc .init=16'hF8F8;
+// @16:322
+  LUT4 \genblk2.un1_rlos_fedge_1  (
+       .A(rlos_db),
+       .B(rlos_db_p1),
+       .C(rlol1_cnt_tc_1),
+       .D(VCC),
+       .Z(un1_rlos_fedge_1)
+);
+defparam \genblk2.un1_rlos_fedge_1 .init=16'hF6F6;
+// @16:340
+  LUT4 \genblk2.un1_rlols0_cnt_tc  (
+       .A(rlols0_cnt11_0),
+       .B(waita_rlols06),
+       .C(rlols0_cnt_tc_1),
+       .D(VCC),
+       .Z(un1_rlols0_cnt_tc)
+);
+defparam \genblk2.un1_rlols0_cnt_tc .init=16'hFEFE;
+// @16:498
+  LUT4 \genblk1.genblk2.txdpr_appd_RNO  (
+       .A(pll_lol_p2),
+       .B(rsl_serdes_rst_dual_c),
+       .C(rsl_tx_serdes_rst_c),
+       .D(rst_dual_c),
+       .Z(un2_plol_fedge_3_i)
+);
+defparam \genblk1.genblk2.txdpr_appd_RNO .init=16'hFFFE;
+// @16:461
+  LUT4 \genblk1.txp_cnt_RNO[0]  (
+       .A(txp_cnt[0]),
+       .B(txp_rst),
+       .C(un9_plol0_cnt_tc),
+       .D(VCC),
+       .Z(N_11_i)
+);
+defparam \genblk1.txp_cnt_RNO[0] .init=16'hA6A6;
+// @16:473
+  LUT4 \genblk1.txp_cnt_RNO[1]  (
+       .A(txp_cnt[0]),
+       .B(txp_cnt[1]),
+       .C(txp_rst),
+       .D(un9_plol0_cnt_tc),
+       .Z(txp_cnt_RNO[1])
+);
+defparam \genblk1.txp_cnt_RNO[1] .init=16'hCC6C;
+// @16:522
+  LUT4 un1_dual_or_serd_rst_1_1_cZ (
+       .A(un18_txr_wt_tc),
+       .B(rsl_serdes_rst_dual_c),
+       .C(rsl_tx_serdes_rst_c),
+       .D(VCC),
+       .Z(un1_dual_or_serd_rst_1_1)
+);
+defparam un1_dual_or_serd_rst_1_1_cZ.init=16'h0101;
+// @16:282
+  LUT4 un2_plol_fedge_5_1_cZ (
+       .A(pll_lol_p2),
+       .B(tx_any_rst),
+       .C(VCC),
+       .D(VCC),
+       .Z(un2_plol_fedge_5_1)
+);
+defparam un2_plol_fedge_5_1_cZ.init=16'h1111;
+// @16:388
+  LUT4 rlols0_cnt_tc_1_cZ (
+       .A(rlols0_cnt_tc_1_10),
+       .B(rlols0_cnt_tc_1_11),
+       .C(rlols0_cnt_tc_1_12),
+       .D(rlols0_cnt_tc_1_13),
+       .Z(rlols0_cnt_tc_1)
+);
+defparam rlols0_cnt_tc_1_cZ.init=16'h8000;
+// @16:387
+  LUT4 rlol1_cnt_tc_1_cZ (
+       .A(rlol1_cnt_tc_1_11),
+       .B(rlol1_cnt_tc_1_12),
+       .C(rlol1_cnt_tc_1_13),
+       .D(rlol1_cnt_tc_1_14),
+       .Z(rlol1_cnt_tc_1)
+);
+defparam rlol1_cnt_tc_1_cZ.init=16'h8000;
+// @16:386
+  LUT4 \genblk1.un1_plol_cnt_tc  (
+       .A(un1_plol_cnt_tc_11),
+       .B(un1_plol_cnt_tc_12),
+       .C(un1_plol_cnt_tc_13),
+       .D(un1_plol_cnt_tc_14),
+       .Z(un1_plol_cnt_tc)
+);
+defparam \genblk1.un1_plol_cnt_tc .init=16'h8000;
+// @16:625
+  LUT4 \un1_genblk2.rlol_db_cnt_axb_0  (
+       .A(rlol_db_cnt[0]),
+       .B(un1_rlol_db_cnt_zero[0]),
+       .C(VCC),
+       .D(VCC),
+       .Z(rlol_db_cnt_axb_0)
+);
+defparam \un1_genblk2.rlol_db_cnt_axb_0 .init=16'h9999;
+// @16:641
+  LUT4 \un1_genblk2.rlos_db_cnt_axb_0  (
+       .A(rlos_db_cnt[0]),
+       .B(un1_rlos_db_cnt_zero[0]),
+       .C(VCC),
+       .D(VCC),
+       .Z(rlos_db_cnt_axb_0)
+);
+defparam \un1_genblk2.rlos_db_cnt_axb_0 .init=16'h9999;
+// @16:443
+  LUT4 \genblk1.waita_plol0_RNO  (
+       .A(pll_lol_p2),
+       .B(pll_lol_p3),
+       .C(un9_plol0_cnt_tc),
+       .D(VCC),
+       .Z(un1_plol0_cnt_tc_1_i)
+);
+defparam \genblk1.waita_plol0_RNO .init=16'hF6F6;
+// @16:452
+  LUT4 \genblk1.plol0_cnt_3[2]  (
+       .A(CO0_2),
+       .B(plol0_cnt9),
+       .C(plol0_cnt[1]),
+       .D(plol0_cnt[2]),
+       .Z(plol0_cnt_3[2])
+);
+defparam \genblk1.plol0_cnt_3[2] .init=16'h1320;
+// @16:452
+  LUT4 \genblk1.plol0_cnt_3[0]  (
+       .A(plol0_cnt9),
+       .B(plol0_cnt[0]),
+       .C(waita_plol0),
+       .D(VCC),
+       .Z(plol0_cnt_3[0])
+);
+defparam \genblk1.plol0_cnt_3[0] .init=16'h1414;
+// @16:493
+  LUT4 \genblk1.genblk2.txsr_appd_2  (
+       .A(txsr_appd_4),
+       .B(rsl_serdes_rst_dual_c),
+       .C(rsl_tx_serdes_rst_c),
+       .D(VCC),
+       .Z(txsr_appd_2)
+);
+defparam \genblk1.genblk2.txsr_appd_2 .init=16'hFEFE;
+// @16:514
+  LUT4 \genblk1.genblk2.mfor[0].un1_txsr_appd  (
+       .A(txdpr_appd),
+       .B(txsr_appd_4),
+       .C(rsl_tx_pcs_rst_c),
+       .D(VCC),
+       .Z(un1_txsr_appd)
+);
+defparam \genblk1.genblk2.mfor[0].un1_txsr_appd .init=16'hC8C8;
+// @16:535
+  LUT4 \genblk2.genblk3.un17_rxr_wt_tc  (
+       .A(un17_rxr_wt_tc_6),
+       .B(un17_rxr_wt_tc_7),
+       .C(un17_rxr_wt_tc_8),
+       .D(VCC),
+       .Z(un17_rxr_wt_tc)
+);
+defparam \genblk2.genblk3.un17_rxr_wt_tc .init=16'h8080;
+// @16:863
+  LUT4 rx_any_rst_cZ (
+       .A(rsl_rx_pcs_rst_c),
+       .B(rsl_rx_serdes_rst_c),
+       .C(rsl_serdes_rst_dual_c),
+       .D(rst_dual_c),
+       .Z(rx_any_rst)
+);
+defparam rx_any_rst_cZ.init=16'hFFFE;
+// @16:490
+  LUT4 tx_any_rst_cZ (
+       .A(rsl_serdes_rst_dual_c),
+       .B(rsl_tx_pcs_rst_c),
+       .C(rsl_tx_serdes_rst_c),
+       .D(rst_dual_c),
+       .Z(tx_any_rst)
+);
+defparam tx_any_rst_cZ.init=16'hFFFE;
+// @16:211
+  LUT4 un2_plol_fedge_2_cZ (
+       .A(pll_lol_p2),
+       .B(rsl_serdes_rst_dual_c),
+       .C(rsl_tx_serdes_rst_c),
+       .D(VCC),
+       .Z(un2_plol_fedge_2)
+);
+defparam un2_plol_fedge_2_cZ.init=16'h0101;
+// @16:535
+  LUT4 \genblk1.genblk2.un18_txr_wt_tc  (
+       .A(un18_txr_wt_tc_6),
+       .B(un18_txr_wt_tc_7),
+       .C(un18_txr_wt_tc_8),
+       .D(VCC),
+       .Z(un18_txr_wt_tc)
+);
+defparam \genblk1.genblk2.un18_txr_wt_tc .init=16'h8080;
+// @16:219
+  LUT4 \un1_rlol_db_cnt_zero_bm_cZ[0]  (
+       .A(rlol_db_cnt[0]),
+       .B(rlol_db_cnt[1]),
+       .C(rlol_db_cnt[2]),
+       .D(rlol_db_cnt[3]),
+       .Z(un1_rlol_db_cnt_zero_bm[0])
+);
+defparam \un1_rlol_db_cnt_zero_bm_cZ[0] .init=16'h8000;
+// @16:219
+  PFUMX \un1_rlol_db_cnt_zero_cZ[0]  (
+       .ALUT(un1_rlol_db_cnt_zero_bm[0]),
+       .BLUT(un1_rlol_db_cnt_zero_am[0]),
+       .C0(rlol_p2),
+       .Z(un1_rlol_db_cnt_zero[0])
+);
+// @16:219
+  LUT4 \un1_rlos_db_cnt_zero_bm_cZ[0]  (
+       .A(rlos_db_cnt[0]),
+       .B(rlos_db_cnt[1]),
+       .C(rlos_db_cnt[2]),
+       .D(rlos_db_cnt[3]),
+       .Z(un1_rlos_db_cnt_zero_bm[0])
+);
+defparam \un1_rlos_db_cnt_zero_bm_cZ[0] .init=16'h8000;
+// @16:219
+  PFUMX \un1_rlos_db_cnt_zero_cZ[0]  (
+       .ALUT(un1_rlos_db_cnt_zero_bm[0]),
+       .BLUT(un1_rlos_db_cnt_zero_am[0]),
+       .C0(rlos_p2),
+       .Z(un1_rlos_db_cnt_zero[0])
+);
+// @16:309
+  LUT4 \genblk2.un1_rlol_db_cnt_max  (
+       .A(rlol_db_cnt[0]),
+       .B(rlol_db_cnt[1]),
+       .C(rlol_db_cnt[2]),
+       .D(rlol_db_cnt[3]),
+       .Z(un1_rlol_db_cnt_max)
+);
+defparam \genblk2.un1_rlol_db_cnt_max .init=16'h8001;
+// @16:315
+  LUT4 \genblk2.un1_rlos_db_cnt_max  (
+       .A(rlos_db_cnt[0]),
+       .B(rlos_db_cnt[1]),
+       .C(rlos_db_cnt[2]),
+       .D(rlos_db_cnt[3]),
+       .Z(un1_rlos_db_cnt_max)
+);
+defparam \genblk2.un1_rlos_db_cnt_max .init=16'h8001;
+// @16:269
+  LUT4 \genblk1.un1_plol0_cnt_tc_1  (
+       .A(txp_cnt[0]),
+       .B(txp_cnt[1]),
+       .C(un9_plol0_cnt_tc),
+       .D(VCC),
+       .Z(un1_plol0_cnt_tc_1)
+);
+defparam \genblk1.un1_plol0_cnt_tc_1 .init=16'hF8F8;
+// @16:764
+  LUT4 \genblk2.waita_rlols06  (
+       .A(rlol_db),
+       .B(rlol_db_p1),
+       .C(rlos_db),
+       .D(rlos_db_p1),
+       .Z(waita_rlols06)
+);
+defparam \genblk2.waita_rlols06 .init=16'h0504;
+// @16:708
+  LUT4 \rxs_cnt_3_cZ[1]  (
+       .A(rxs_cnt[0]),
+       .B(rxs_cnt[1]),
+       .C(rxs_rst),
+       .D(VCC),
+       .Z(rxs_cnt_3[1])
+);
+defparam \rxs_cnt_3_cZ[1] .init=16'h6464;
+// @16:893
+  LUT4 \genblk2.genblk3.lfor[0].un1_rxsdr_or_sr_appd  (
+       .A(rxsr_appd[0]),
+       .B(rx_all_well),
+       .C(rxsdr_appd_4),
+       .D(rsl_rx_pcs_rst_c),
+       .Z(un1_rxsdr_or_sr_appd)
+);
+defparam \genblk2.genblk3.lfor[0].un1_rxsdr_or_sr_appd .init=16'h3200;
+// @16:388
+  LUT4 rlols0_cnt_tc_1_13_cZ (
+       .A(rlols0_cnt[16]),
+       .B(rlols0_cnt[17]),
+       .C(rlols0_cnt_tc_1_9),
+       .D(VCC),
+       .Z(rlols0_cnt_tc_1_13)
+);
+defparam rlols0_cnt_tc_1_13_cZ.init=16'h1010;
+// @16:386
+  LUT4 \genblk1.un1_plol_cnt_tc_14  (
+       .A(plol_cnt[4]),
+       .B(plol_cnt[5]),
+       .C(plol_cnt[18]),
+       .D(un1_plol_cnt_tc_10),
+       .Z(un1_plol_cnt_tc_14)
+);
+defparam \genblk1.un1_plol_cnt_tc_14 .init=16'h0100;
+// @16:387
+  LUT4 rlol1_cnt_tc_1_14_cZ (
+       .A(rlol1_cnt[11]),
+       .B(rlol1_cnt[12]),
+       .C(rlol1_cnt[18]),
+       .D(rlol1_cnt_tc_1_10),
+       .Z(rlol1_cnt_tc_1_14)
+);
+defparam rlol1_cnt_tc_1_14_cZ.init=16'h0100;
+// @16:904
+  LUT4 un1_dual_or_rserd_rst_2_0_cZ (
+       .A(rxpr_appd[0]),
+       .B(rxdpr_appd),
+       .C(rx_all_well),
+       .D(rsl_rx_rdy),
+       .Z(un1_dual_or_rserd_rst_2_0)
+);
+defparam un1_dual_or_rserd_rst_2_0_cZ.init=16'hF010;
+// @16:438
+  LUT4 rdo_tx_serdes_rst_c (
+       .A(rsl_disable),
+       .B(txs_rst),
+       .C(tx_serdes_rst_c),
+       .D(VCC),
+       .Z(rsl_tx_serdes_rst_c)
+);
+defparam rdo_tx_serdes_rst_c.init=16'hF4F4;
+// @16:375
+  LUT4 rdo_serdes_rst_dual_c (
+       .A(rsl_disable),
+       .B(rsl_rst),
+       .C(serdes_rst_dual_c),
+       .D(VCC),
+       .Z(rsl_serdes_rst_dual_c)
+);
+defparam rdo_serdes_rst_dual_c.init=16'hF4F4;
+// @16:479
+  LUT4 \rdo_tx_pcs_rst_c_1[0]  (
+       .A(rsl_disable),
+       .B(txp_rst),
+       .C(tx_pcs_rst_c),
+       .D(VCC),
+       .Z(rsl_tx_pcs_rst_c)
+);
+defparam \rdo_tx_pcs_rst_c_1[0] .init=16'hF4F4;
+// @16:743
+  LUT4 \rdo_rx_serdes_rst_c_1[0]  (
+       .A(rsl_disable),
+       .B(rxs_rst),
+       .C(rx_serdes_rst_c),
+       .D(VCC),
+       .Z(rsl_rx_serdes_rst_c)
+);
+defparam \rdo_rx_serdes_rst_c_1[0] .init=16'hF4F4;
+// @16:852
+  LUT4 \rdo_rx_pcs_rst_c_1[0]  (
+       .A(rsl_disable),
+       .B(rxp_rst2),
+       .C(rx_pcs_rst_c),
+       .D(VCC),
+       .Z(rsl_rx_pcs_rst_c)
+);
+defparam \rdo_rx_pcs_rst_c_1[0] .init=16'hF4F4;
+// @16:459
+  LUT4 \genblk1.un9_plol0_cnt_tc  (
+       .A(plol0_cnt[0]),
+       .B(plol0_cnt[1]),
+       .C(plol0_cnt[2]),
+       .D(VCC),
+       .Z(un9_plol0_cnt_tc)
+);
+defparam \genblk1.un9_plol0_cnt_tc .init=16'h1010;
+// @16:535
+  LUT4 \genblk1.genblk2.un18_txr_wt_tc_6  (
+       .A(txr_wt_cnt[0]),
+       .B(txr_wt_cnt[8]),
+       .C(txr_wt_cnt[9]),
+       .D(txr_wt_cnt[11]),
+       .Z(un18_txr_wt_tc_6)
+);
+defparam \genblk1.genblk2.un18_txr_wt_tc_6 .init=16'h4000;
+// @16:535
+  LUT4 \genblk1.genblk2.un18_txr_wt_tc_7  (
+       .A(txr_wt_cnt[3]),
+       .B(txr_wt_cnt[4]),
+       .C(txr_wt_cnt[5]),
+       .D(txr_wt_cnt[7]),
+       .Z(un18_txr_wt_tc_7)
+);
+defparam \genblk1.genblk2.un18_txr_wt_tc_7 .init=16'h8000;
+// @16:535
+  LUT4 \genblk1.genblk2.un18_txr_wt_tc_8  (
+       .A(txr_wt_cnt[1]),
+       .B(txr_wt_cnt[2]),
+       .C(txr_wt_cnt[6]),
+       .D(txr_wt_cnt[10]),
+       .Z(un18_txr_wt_tc_8)
+);
+defparam \genblk1.genblk2.un18_txr_wt_tc_8 .init=16'h0001;
+// @16:535
+  LUT4 \genblk2.genblk3.un17_rxr_wt_tc_6  (
+       .A(rxr_wt_cnt[0]),
+       .B(rxr_wt_cnt[8]),
+       .C(rxr_wt_cnt[9]),
+       .D(rxr_wt_cnt[11]),
+       .Z(un17_rxr_wt_tc_6)
+);
+defparam \genblk2.genblk3.un17_rxr_wt_tc_6 .init=16'h4000;
+// @16:535
+  LUT4 \genblk2.genblk3.un17_rxr_wt_tc_7  (
+       .A(rxr_wt_cnt[3]),
+       .B(rxr_wt_cnt[4]),
+       .C(rxr_wt_cnt[5]),
+       .D(rxr_wt_cnt[7]),
+       .Z(un17_rxr_wt_tc_7)
+);
+defparam \genblk2.genblk3.un17_rxr_wt_tc_7 .init=16'h8000;
+// @16:535
+  LUT4 \genblk2.genblk3.un17_rxr_wt_tc_8  (
+       .A(rxr_wt_cnt[1]),
+       .B(rxr_wt_cnt[2]),
+       .C(rxr_wt_cnt[6]),
+       .D(rxr_wt_cnt[10]),
+       .Z(un17_rxr_wt_tc_8)
+);
+defparam \genblk2.genblk3.un17_rxr_wt_tc_8 .init=16'h0001;
+// @16:388
+  LUT4 rlols0_cnt_tc_1_9_cZ (
+       .A(rlols0_cnt[1]),
+       .B(rlols0_cnt[2]),
+       .C(rlols0_cnt[3]),
+       .D(rlols0_cnt[4]),
+       .Z(rlols0_cnt_tc_1_9)
+);
+defparam rlols0_cnt_tc_1_9_cZ.init=16'h0001;
+// @16:388
+  LUT4 rlols0_cnt_tc_1_10_cZ (
+       .A(rlols0_cnt[0]),
+       .B(rlols0_cnt[10]),
+       .C(rlols0_cnt[14]),
+       .D(rlols0_cnt[15]),
+       .Z(rlols0_cnt_tc_1_10)
+);
+defparam rlols0_cnt_tc_1_10_cZ.init=16'h4000;
+// @16:388
+  LUT4 rlols0_cnt_tc_1_11_cZ (
+       .A(rlols0_cnt[9]),
+       .B(rlols0_cnt[11]),
+       .C(rlols0_cnt[12]),
+       .D(rlols0_cnt[13]),
+       .Z(rlols0_cnt_tc_1_11)
+);
+defparam rlols0_cnt_tc_1_11_cZ.init=16'h0001;
+// @16:388
+  LUT4 rlols0_cnt_tc_1_12_cZ (
+       .A(rlols0_cnt[5]),
+       .B(rlols0_cnt[6]),
+       .C(rlols0_cnt[7]),
+       .D(rlols0_cnt[8]),
+       .Z(rlols0_cnt_tc_1_12)
+);
+defparam rlols0_cnt_tc_1_12_cZ.init=16'h0001;
+// @16:386
+  LUT4 \genblk1.un1_plol_cnt_tc_10  (
+       .A(plol_cnt[2]),
+       .B(plol_cnt[3]),
+       .C(plol_cnt[17]),
+       .D(plol_cnt[19]),
+       .Z(un1_plol_cnt_tc_10)
+);
+defparam \genblk1.un1_plol_cnt_tc_10 .init=16'h1000;
+// @16:386
+  LUT4 \genblk1.un1_plol_cnt_tc_11  (
+       .A(plol_cnt[13]),
+       .B(plol_cnt[14]),
+       .C(plol_cnt[15]),
+       .D(plol_cnt[16]),
+       .Z(un1_plol_cnt_tc_11)
+);
+defparam \genblk1.un1_plol_cnt_tc_11 .init=16'h8000;
+// @16:386
+  LUT4 \genblk1.un1_plol_cnt_tc_12  (
+       .A(plol_cnt[7]),
+       .B(plol_cnt[8]),
+       .C(plol_cnt[9]),
+       .D(plol_cnt[11]),
+       .Z(un1_plol_cnt_tc_12)
+);
+defparam \genblk1.un1_plol_cnt_tc_12 .init=16'h8000;
+// @16:386
+  LUT4 \genblk1.un1_plol_cnt_tc_13  (
+       .A(plol_cnt[1]),
+       .B(plol_cnt[6]),
+       .C(plol_cnt[10]),
+       .D(plol_cnt[12]),
+       .Z(un1_plol_cnt_tc_13)
+);
+defparam \genblk1.un1_plol_cnt_tc_13 .init=16'h0008;
+// @16:387
+  LUT4 rlol1_cnt_tc_1_10_cZ (
+       .A(rlol1_cnt[7]),
+       .B(rlol1_cnt[8]),
+       .C(rlol1_cnt[9]),
+       .D(rlol1_cnt[10]),
+       .Z(rlol1_cnt_tc_1_10)
+);
+defparam rlol1_cnt_tc_1_10_cZ.init=16'h0001;
+// @16:387
+  LUT4 rlol1_cnt_tc_1_11_cZ (
+       .A(rlol1_cnt[3]),
+       .B(rlol1_cnt[4]),
+       .C(rlol1_cnt[5]),
+       .D(rlol1_cnt[6]),
+       .Z(rlol1_cnt_tc_1_11)
+);
+defparam rlol1_cnt_tc_1_11_cZ.init=16'h0001;
+// @16:387
+  LUT4 rlol1_cnt_tc_1_12_cZ (
+       .A(rlol1_cnt[0]),
+       .B(rlol1_cnt[1]),
+       .C(rlol1_cnt[2]),
+       .D(rlol1_cnt[17]),
+       .Z(rlol1_cnt_tc_1_12)
+);
+defparam rlol1_cnt_tc_1_12_cZ.init=16'h0100;
+// @16:387
+  LUT4 rlol1_cnt_tc_1_13_cZ (
+       .A(rlol1_cnt[13]),
+       .B(rlol1_cnt[14]),
+       .C(rlol1_cnt[15]),
+       .D(rlol1_cnt[16]),
+       .Z(rlol1_cnt_tc_1_13)
+);
+defparam rlol1_cnt_tc_1_13_cZ.init=16'h0040;
+// @16:457
+  LUT4 \genblk1.plol0_cnt_3_RNO[2]  (
+       .A(plol0_cnt[0]),
+       .B(waita_plol0),
+       .C(VCC),
+       .D(VCC),
+       .Z(CO0_2)
+);
+defparam \genblk1.plol0_cnt_3_RNO[2] .init=16'h8888;
+// @16:441
+  LUT4 plol_fedge_cZ (
+       .A(pll_lol_p2),
+       .B(pll_lol_p3),
+       .C(VCC),
+       .D(VCC),
+       .Z(plol_fedge)
+);
+defparam plol_fedge_cZ.init=16'h4444;
+// @16:601
+  LUT4 rx_all_well_cZ (
+       .A(rlol_db),
+       .B(rlos_db),
+       .C(VCC),
+       .D(VCC),
+       .Z(rx_all_well)
+);
+defparam rx_all_well_cZ.init=16'h1111;
+// @16:866
+  LUT4 \genblk2.genblk3.rxsdr_appd_2  (
+       .A(rxsdr_appd_4),
+       .B(serdes_rst_dual_c),
+       .C(VCC),
+       .D(VCC),
+       .Z(rxsdr_appd_2)
+);
+defparam \genblk2.genblk3.rxsdr_appd_2 .init=16'hEEEE;
+// @16:436
+  LUT4 \genblk2.un8_rxs_cnt_tc  (
+       .A(rxs_cnt[0]),
+       .B(rxs_cnt[1]),
+       .C(VCC),
+       .D(VCC),
+       .Z(un8_rxs_cnt_tc)
+);
+defparam \genblk2.un8_rxs_cnt_tc .init=16'h8888;
+// @16:757
+  LUT4 rlos_redge_cZ (
+       .A(rlos_db),
+       .B(rlos_db_p1),
+       .C(VCC),
+       .D(VCC),
+       .Z(rlos_redge)
+);
+defparam rlos_redge_cZ.init=16'h2222;
+// @16:891
+  LUT4 un2_rdo_serdes_rst_dual_c_1_1_cZ (
+       .A(rx_cdr_lol_s),
+       .B(rx_los_low_s),
+       .C(VCC),
+       .D(VCC),
+       .Z(un2_rdo_serdes_rst_dual_c_1_1)
+);
+defparam un2_rdo_serdes_rst_dual_c_1_1_cZ.init=16'h1111;
+// @16:219
+  LUT4 \un1_rlos_db_cnt_zero_am_cZ[0]  (
+       .A(rlos_db_cnt[0]),
+       .B(rlos_db_cnt[1]),
+       .C(rlos_db_cnt[2]),
+       .D(rlos_db_cnt[3]),
+       .Z(un1_rlos_db_cnt_zero_am[0])
+);
+defparam \un1_rlos_db_cnt_zero_am_cZ[0] .init=16'h0001;
+// @16:219
+  LUT4 \un1_rlol_db_cnt_zero_am_cZ[0]  (
+       .A(rlol_db_cnt[0]),
+       .B(rlol_db_cnt[1]),
+       .C(rlol_db_cnt[2]),
+       .D(rlol_db_cnt[3]),
+       .Z(un1_rlol_db_cnt_zero_am[0])
+);
+defparam \un1_rlol_db_cnt_zero_am_cZ[0] .init=16'h0001;
+// @16:454
+  LUT4 \genblk1.plol0_cnt9  (
+       .A(pll_lol_p2),
+       .B(plol0_cnt[2]),
+       .C(plol0_cnt[1]),
+       .D(plol0_cnt[0]),
+       .Z(plol0_cnt9)
+);
+defparam \genblk1.plol0_cnt9 .init=16'hAAAE;
+// @16:783
+  LUT4 \genblk2.rlols0_cnt11_0  (
+       .A(rlol_db_p1),
+       .B(rlol_db),
+       .C(rlos_db_p1),
+       .D(rlos_db),
+       .Z(rlols0_cnt11_0)
+);
+defparam \genblk2.rlols0_cnt11_0 .init=16'h4F44;
+// @16:527
+  LUT4 \genblk1.genblk2.txr_wt_cnt9_i  (
+       .A(tx_any_rst),
+       .B(un18_txr_wt_tc_8),
+       .C(un18_txr_wt_tc_7),
+       .D(un18_txr_wt_tc_6),
+       .Z(txr_wt_cnt_scalar)
+);
+defparam \genblk1.genblk2.txr_wt_cnt9_i .init=16'h1555;
+  CCU2C \genblk2.rlol1_cnt_cry_0[0]  (
+       .A0(VCC),
+       .B0(rlol1_cnt_scalar),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_7),
+       .COUT(rlol1_cnt_cry[0]),
+       .S0(rlol1_cnt_cry_0_S0[0]),
+       .S1(rlol1_cnt_s[0])
+);
+defparam \genblk2.rlol1_cnt_cry_0[0] .INIT0=16'h500c;
+defparam \genblk2.rlol1_cnt_cry_0[0] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[0] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[0] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[1]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[1]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[0]),
+       .COUT(rlol1_cnt_cry[2]),
+       .S0(rlol1_cnt_s[1]),
+       .S1(rlol1_cnt_s[2])
+);
+defparam \genblk2.rlol1_cnt_cry_0[1] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[1] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[1] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[1] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[3]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[3]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[4]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[2]),
+       .COUT(rlol1_cnt_cry[4]),
+       .S0(rlol1_cnt_s[3]),
+       .S1(rlol1_cnt_s[4])
+);
+defparam \genblk2.rlol1_cnt_cry_0[3] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[3] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[3] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[3] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[5]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[5]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[6]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[4]),
+       .COUT(rlol1_cnt_cry[6]),
+       .S0(rlol1_cnt_s[5]),
+       .S1(rlol1_cnt_s[6])
+);
+defparam \genblk2.rlol1_cnt_cry_0[5] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[5] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[5] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[5] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[7]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[7]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[8]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[6]),
+       .COUT(rlol1_cnt_cry[8]),
+       .S0(rlol1_cnt_s[7]),
+       .S1(rlol1_cnt_s[8])
+);
+defparam \genblk2.rlol1_cnt_cry_0[7] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[7] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[7] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[7] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[9]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[9]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[10]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[8]),
+       .COUT(rlol1_cnt_cry[10]),
+       .S0(rlol1_cnt_s[9]),
+       .S1(rlol1_cnt_s[10])
+);
+defparam \genblk2.rlol1_cnt_cry_0[9] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[9] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[9] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[9] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[11]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[11]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[12]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[10]),
+       .COUT(rlol1_cnt_cry[12]),
+       .S0(rlol1_cnt_s[11]),
+       .S1(rlol1_cnt_s[12])
+);
+defparam \genblk2.rlol1_cnt_cry_0[11] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[11] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[11] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[11] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[13]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[13]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[14]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[12]),
+       .COUT(rlol1_cnt_cry[14]),
+       .S0(rlol1_cnt_s[13]),
+       .S1(rlol1_cnt_s[14])
+);
+defparam \genblk2.rlol1_cnt_cry_0[13] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[13] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[13] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[13] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[15]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[15]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[16]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[14]),
+       .COUT(rlol1_cnt_cry[16]),
+       .S0(rlol1_cnt_s[15]),
+       .S1(rlol1_cnt_s[16])
+);
+defparam \genblk2.rlol1_cnt_cry_0[15] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[15] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[15] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[15] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[17]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[17]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[18]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[16]),
+       .COUT(rlol1_cnt_cry_0_COUT[17]),
+       .S0(rlol1_cnt_s[17]),
+       .S1(rlol1_cnt_s[18])
+);
+defparam \genblk2.rlol1_cnt_cry_0[17] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[17] .INIT1=16'h800a;
+defparam \genblk2.rlol1_cnt_cry_0[17] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[17] .INJECT1_1="NO";
+  CCU2C \genblk2.rlols0_cnt_cry_0[0]  (
+       .A0(VCC),
+       .B0(rlols0_cnt_scalar),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_6),
+       .COUT(rlols0_cnt_cry[0]),
+       .S0(rlols0_cnt_cry_0_S0[0]),
+       .S1(rlols0_cnt_s[0])
+);
+defparam \genblk2.rlols0_cnt_cry_0[0] .INIT0=16'h500c;
+defparam \genblk2.rlols0_cnt_cry_0[0] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[0] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[0] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[1]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[1]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[0]),
+       .COUT(rlols0_cnt_cry[2]),
+       .S0(rlols0_cnt_s[1]),
+       .S1(rlols0_cnt_s[2])
+);
+defparam \genblk2.rlols0_cnt_cry_0[1] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[1] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[1] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[1] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[3]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[3]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[4]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[2]),
+       .COUT(rlols0_cnt_cry[4]),
+       .S0(rlols0_cnt_s[3]),
+       .S1(rlols0_cnt_s[4])
+);
+defparam \genblk2.rlols0_cnt_cry_0[3] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[3] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[3] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[3] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[5]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[5]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[6]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[4]),
+       .COUT(rlols0_cnt_cry[6]),
+       .S0(rlols0_cnt_s[5]),
+       .S1(rlols0_cnt_s[6])
+);
+defparam \genblk2.rlols0_cnt_cry_0[5] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[5] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[5] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[5] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[7]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[7]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[8]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[6]),
+       .COUT(rlols0_cnt_cry[8]),
+       .S0(rlols0_cnt_s[7]),
+       .S1(rlols0_cnt_s[8])
+);
+defparam \genblk2.rlols0_cnt_cry_0[7] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[7] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[7] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[7] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[9]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[9]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[10]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[8]),
+       .COUT(rlols0_cnt_cry[10]),
+       .S0(rlols0_cnt_s[9]),
+       .S1(rlols0_cnt_s[10])
+);
+defparam \genblk2.rlols0_cnt_cry_0[9] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[9] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[9] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[9] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[11]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[11]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[12]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[10]),
+       .COUT(rlols0_cnt_cry[12]),
+       .S0(rlols0_cnt_s[11]),
+       .S1(rlols0_cnt_s[12])
+);
+defparam \genblk2.rlols0_cnt_cry_0[11] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[11] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[11] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[11] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[13]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[13]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[14]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[12]),
+       .COUT(rlols0_cnt_cry[14]),
+       .S0(rlols0_cnt_s[13]),
+       .S1(rlols0_cnt_s[14])
+);
+defparam \genblk2.rlols0_cnt_cry_0[13] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[13] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[13] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[13] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[15]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[15]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[16]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[14]),
+       .COUT(rlols0_cnt_cry[16]),
+       .S0(rlols0_cnt_s[15]),
+       .S1(rlols0_cnt_s[16])
+);
+defparam \genblk2.rlols0_cnt_cry_0[15] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[15] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[15] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[15] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_s_0[17]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[17]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[16]),
+       .COUT(rlols0_cnt_s_0_COUT[17]),
+       .S0(rlols0_cnt_s[17]),
+       .S1(rlols0_cnt_s_0_S1[17])
+);
+defparam \genblk2.rlols0_cnt_s_0[17] .INIT0=16'h800a;
+defparam \genblk2.rlols0_cnt_s_0[17] .INIT1=16'h5003;
+defparam \genblk2.rlols0_cnt_s_0[17] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_s_0[17] .INJECT1_1="NO";
+  CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[0]  (
+       .A0(VCC),
+       .B0(txr_wt_cnt_scalar),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(txr_wt_cnt_scalar),
+       .B1(txr_wt_cnt[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_5),
+       .COUT(txr_wt_cnt_cry[0]),
+       .S0(txr_wt_cnt_cry_0_S0[0]),
+       .S1(txr_wt_cnt_s[0])
+);
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[0] .INIT0=16'h500c;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[0] .INIT1=16'h8000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[0] .INJECT1_0="NO";
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[0] .INJECT1_1="NO";
+// @16:527
+  CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[1]  (
+       .A0(txr_wt_cnt_scalar),
+       .B0(txr_wt_cnt[1]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(txr_wt_cnt_scalar),
+       .B1(txr_wt_cnt[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(txr_wt_cnt_cry[0]),
+       .COUT(txr_wt_cnt_cry[2]),
+       .S0(txr_wt_cnt_s[1]),
+       .S1(txr_wt_cnt_s[2])
+);
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[1] .INIT0=16'h8000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[1] .INIT1=16'h8000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[1] .INJECT1_0="NO";
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[1] .INJECT1_1="NO";
+// @16:527
+  CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[3]  (
+       .A0(txr_wt_cnt_scalar),
+       .B0(txr_wt_cnt[3]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(txr_wt_cnt_scalar),
+       .B1(txr_wt_cnt[4]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(txr_wt_cnt_cry[2]),
+       .COUT(txr_wt_cnt_cry[4]),
+       .S0(txr_wt_cnt_s[3]),
+       .S1(txr_wt_cnt_s[4])
+);
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[3] .INIT0=16'h8000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[3] .INIT1=16'h8000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[3] .INJECT1_0="NO";
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[3] .INJECT1_1="NO";
+// @16:527
+  CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[5]  (
+       .A0(txr_wt_cnt_scalar),
+       .B0(txr_wt_cnt[5]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(txr_wt_cnt_scalar),
+       .B1(txr_wt_cnt[6]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(txr_wt_cnt_cry[4]),
+       .COUT(txr_wt_cnt_cry[6]),
+       .S0(txr_wt_cnt_s[5]),
+       .S1(txr_wt_cnt_s[6])
+);
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[5] .INIT0=16'h8000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[5] .INIT1=16'h8000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[5] .INJECT1_0="NO";
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[5] .INJECT1_1="NO";
+// @16:527
+  CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[7]  (
+       .A0(txr_wt_cnt_scalar),
+       .B0(txr_wt_cnt[7]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(txr_wt_cnt_scalar),
+       .B1(txr_wt_cnt[8]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(txr_wt_cnt_cry[6]),
+       .COUT(txr_wt_cnt_cry[8]),
+       .S0(txr_wt_cnt_s[7]),
+       .S1(txr_wt_cnt_s[8])
+);
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[7] .INIT0=16'h8000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[7] .INIT1=16'h8000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[7] .INJECT1_0="NO";
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[7] .INJECT1_1="NO";
+// @16:527
+  CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[9]  (
+       .A0(txr_wt_cnt_scalar),
+       .B0(txr_wt_cnt[9]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(txr_wt_cnt_scalar),
+       .B1(txr_wt_cnt[10]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(txr_wt_cnt_cry[8]),
+       .COUT(txr_wt_cnt_cry[10]),
+       .S0(txr_wt_cnt_s[9]),
+       .S1(txr_wt_cnt_s[10])
+);
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[9] .INIT0=16'h8000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[9] .INIT1=16'h8000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[9] .INJECT1_0="NO";
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[9] .INJECT1_1="NO";
+// @16:527
+  CCU2C \genblk1.genblk2.txr_wt_cnt_s_0[11]  (
+       .A0(txr_wt_cnt_scalar),
+       .B0(txr_wt_cnt[11]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(txr_wt_cnt_cry[10]),
+       .COUT(txr_wt_cnt_s_0_COUT[11]),
+       .S0(txr_wt_cnt_s[11]),
+       .S1(txr_wt_cnt_s_0_S1[11])
+);
+defparam \genblk1.genblk2.txr_wt_cnt_s_0[11] .INIT0=16'h800a;
+defparam \genblk1.genblk2.txr_wt_cnt_s_0[11] .INIT1=16'h5003;
+defparam \genblk1.genblk2.txr_wt_cnt_s_0[11] .INJECT1_0="NO";
+defparam \genblk1.genblk2.txr_wt_cnt_s_0[11] .INJECT1_1="NO";
+  CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[0]  (
+       .A0(VCC),
+       .B0(rxr_wt_cnt9),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rxr_wt_cnt9),
+       .B1(rxr_wt_cnt[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_4),
+       .COUT(rxr_wt_cnt_cry[0]),
+       .S0(rxr_wt_cnt_cry_0_S0[0]),
+       .S1(rxr_wt_cnt_s[0])
+);
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[0] .INIT0=16'h5003;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[0] .INIT1=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[0] .INJECT1_0="NO";
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[0] .INJECT1_1="NO";
+// @16:909
+  CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[1]  (
+       .A0(rxr_wt_cnt9),
+       .B0(rxr_wt_cnt[1]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rxr_wt_cnt9),
+       .B1(rxr_wt_cnt[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rxr_wt_cnt_cry[0]),
+       .COUT(rxr_wt_cnt_cry[2]),
+       .S0(rxr_wt_cnt_s[1]),
+       .S1(rxr_wt_cnt_s[2])
+);
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[1] .INIT0=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[1] .INIT1=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[1] .INJECT1_0="NO";
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[1] .INJECT1_1="NO";
+// @16:909
+  CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[3]  (
+       .A0(rxr_wt_cnt9),
+       .B0(rxr_wt_cnt[3]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rxr_wt_cnt9),
+       .B1(rxr_wt_cnt[4]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rxr_wt_cnt_cry[2]),
+       .COUT(rxr_wt_cnt_cry[4]),
+       .S0(rxr_wt_cnt_s[3]),
+       .S1(rxr_wt_cnt_s[4])
+);
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[3] .INIT0=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[3] .INIT1=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[3] .INJECT1_0="NO";
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[3] .INJECT1_1="NO";
+// @16:909
+  CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[5]  (
+       .A0(rxr_wt_cnt9),
+       .B0(rxr_wt_cnt[5]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rxr_wt_cnt9),
+       .B1(rxr_wt_cnt[6]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rxr_wt_cnt_cry[4]),
+       .COUT(rxr_wt_cnt_cry[6]),
+       .S0(rxr_wt_cnt_s[5]),
+       .S1(rxr_wt_cnt_s[6])
+);
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[5] .INIT0=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[5] .INIT1=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[5] .INJECT1_0="NO";
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[5] .INJECT1_1="NO";
+// @16:909
+  CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[7]  (
+       .A0(rxr_wt_cnt9),
+       .B0(rxr_wt_cnt[7]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rxr_wt_cnt9),
+       .B1(rxr_wt_cnt[8]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rxr_wt_cnt_cry[6]),
+       .COUT(rxr_wt_cnt_cry[8]),
+       .S0(rxr_wt_cnt_s[7]),
+       .S1(rxr_wt_cnt_s[8])
+);
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[7] .INIT0=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[7] .INIT1=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[7] .INJECT1_0="NO";
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[7] .INJECT1_1="NO";
+// @16:909
+  CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[9]  (
+       .A0(rxr_wt_cnt9),
+       .B0(rxr_wt_cnt[9]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rxr_wt_cnt9),
+       .B1(rxr_wt_cnt[10]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rxr_wt_cnt_cry[8]),
+       .COUT(rxr_wt_cnt_cry[10]),
+       .S0(rxr_wt_cnt_s[9]),
+       .S1(rxr_wt_cnt_s[10])
+);
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[9] .INIT0=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[9] .INIT1=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[9] .INJECT1_0="NO";
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[9] .INJECT1_1="NO";
+// @16:909
+  CCU2C \genblk2.genblk3.rxr_wt_cnt_s_0[11]  (
+       .A0(rxr_wt_cnt9),
+       .B0(rxr_wt_cnt[11]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rxr_wt_cnt_cry[10]),
+       .COUT(rxr_wt_cnt_s_0_COUT[11]),
+       .S0(rxr_wt_cnt_s[11]),
+       .S1(rxr_wt_cnt_s_0_S1[11])
+);
+defparam \genblk2.genblk3.rxr_wt_cnt_s_0[11] .INIT0=16'h4005;
+defparam \genblk2.genblk3.rxr_wt_cnt_s_0[11] .INIT1=16'h5003;
+defparam \genblk2.genblk3.rxr_wt_cnt_s_0[11] .INJECT1_0="NO";
+defparam \genblk2.genblk3.rxr_wt_cnt_s_0[11] .INJECT1_1="NO";
+  CCU2C \genblk1.plol_cnt_cry_0[0]  (
+       .A0(VCC),
+       .B0(plol_cnt_scalar),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_3),
+       .COUT(plol_cnt_cry[0]),
+       .S0(plol_cnt_cry_0_S0[0]),
+       .S1(plol_cnt_s[0])
+);
+defparam \genblk1.plol_cnt_cry_0[0] .INIT0=16'h500c;
+defparam \genblk1.plol_cnt_cry_0[0] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[0] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[0] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[1]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[1]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[0]),
+       .COUT(plol_cnt_cry[2]),
+       .S0(plol_cnt_s[1]),
+       .S1(plol_cnt_s[2])
+);
+defparam \genblk1.plol_cnt_cry_0[1] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[1] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[1] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[1] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[3]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[3]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[4]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[2]),
+       .COUT(plol_cnt_cry[4]),
+       .S0(plol_cnt_s[3]),
+       .S1(plol_cnt_s[4])
+);
+defparam \genblk1.plol_cnt_cry_0[3] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[3] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[3] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[3] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[5]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[5]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[6]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[4]),
+       .COUT(plol_cnt_cry[6]),
+       .S0(plol_cnt_s[5]),
+       .S1(plol_cnt_s[6])
+);
+defparam \genblk1.plol_cnt_cry_0[5] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[5] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[5] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[5] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[7]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[7]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[8]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[6]),
+       .COUT(plol_cnt_cry[8]),
+       .S0(plol_cnt_s[7]),
+       .S1(plol_cnt_s[8])
+);
+defparam \genblk1.plol_cnt_cry_0[7] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[7] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[7] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[7] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[9]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[9]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[10]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[8]),
+       .COUT(plol_cnt_cry[10]),
+       .S0(plol_cnt_s[9]),
+       .S1(plol_cnt_s[10])
+);
+defparam \genblk1.plol_cnt_cry_0[9] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[9] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[9] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[9] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[11]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[11]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[12]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[10]),
+       .COUT(plol_cnt_cry[12]),
+       .S0(plol_cnt_s[11]),
+       .S1(plol_cnt_s[12])
+);
+defparam \genblk1.plol_cnt_cry_0[11] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[11] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[11] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[11] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[13]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[13]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[14]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[12]),
+       .COUT(plol_cnt_cry[14]),
+       .S0(plol_cnt_s[13]),
+       .S1(plol_cnt_s[14])
+);
+defparam \genblk1.plol_cnt_cry_0[13] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[13] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[13] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[13] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[15]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[15]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[16]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[14]),
+       .COUT(plol_cnt_cry[16]),
+       .S0(plol_cnt_s[15]),
+       .S1(plol_cnt_s[16])
+);
+defparam \genblk1.plol_cnt_cry_0[15] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[15] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[15] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[15] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[17]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[17]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[18]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[16]),
+       .COUT(plol_cnt_cry[18]),
+       .S0(plol_cnt_s[17]),
+       .S1(plol_cnt_s[18])
+);
+defparam \genblk1.plol_cnt_cry_0[17] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[17] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[17] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[17] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_s_0[19]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[19]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[18]),
+       .COUT(plol_cnt_s_0_COUT[19]),
+       .S0(plol_cnt_s[19]),
+       .S1(plol_cnt_s_0_S1[19])
+);
+defparam \genblk1.plol_cnt_s_0[19] .INIT0=16'h800a;
+defparam \genblk1.plol_cnt_s_0[19] .INIT1=16'h5003;
+defparam \genblk1.plol_cnt_s_0[19] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_s_0[19] .INJECT1_1="NO";
+  CCU2C \un1_genblk2.rlos_db_cnt_cry_0_0  (
+       .A0(VCC),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlos_db_cnt[0]),
+       .B1(un1_rlos_db_cnt_zero[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_2),
+       .COUT(rlos_db_cnt_cry_0),
+       .S0(rlos_db_cnt_cry_0_0_S0),
+       .S1(rlos_db_cnt_cry_0_0_S1)
+);
+defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INIT0=16'h5003;
+defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INIT1=16'h900a;
+defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INJECT1_0="NO";
+defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INJECT1_1="NO";
+// @16:641
+  CCU2C \un1_genblk2.rlos_db_cnt_cry_1_0  (
+       .A0(un1_rlos_db_cnt_zero[0]),
+       .B0(rlos_p2),
+       .C0(rlos_db_cnt[1]),
+       .D0(VCC),
+       .A1(un1_rlos_db_cnt_zero[0]),
+       .B1(rlos_p2),
+       .C1(rlos_db_cnt[2]),
+       .D1(VCC),
+       .CIN(rlos_db_cnt_cry_0),
+       .COUT(rlos_db_cnt_cry_2),
+       .S0(rlos_db_cnt_cry_1_0_S0),
+       .S1(rlos_db_cnt_cry_1_0_S1)
+);
+defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INIT0=16'he101;
+defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INIT1=16'he101;
+defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INJECT1_0="NO";
+defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INJECT1_1="NO";
+// @16:641
+  CCU2C \un1_genblk2.rlos_db_cnt_s_3_0  (
+       .A0(rlos_db_cnt[3]),
+       .B0(rlos_p2),
+       .C0(un1_rlos_db_cnt_zero[0]),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlos_db_cnt_cry_2),
+       .COUT(rlos_db_cnt_s_3_0_COUT),
+       .S0(rlos_db_cnt_s_3_0_S0),
+       .S1(rlos_db_cnt_s_3_0_S1)
+);
+defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INIT0=16'ha90a;
+defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INIT1=16'h5003;
+defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INJECT1_0="NO";
+defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INJECT1_1="NO";
+  CCU2C \un1_genblk2.rlol_db_cnt_cry_0_0  (
+       .A0(VCC),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol_db_cnt[0]),
+       .B1(un1_rlol_db_cnt_zero[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_1),
+       .COUT(rlol_db_cnt_cry_0),
+       .S0(rlol_db_cnt_cry_0_0_S0),
+       .S1(rlol_db_cnt_cry_0_0_S1)
+);
+defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INIT0=16'h5003;
+defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INIT1=16'h900a;
+defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INJECT1_0="NO";
+defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INJECT1_1="NO";
+// @16:625
+  CCU2C \un1_genblk2.rlol_db_cnt_cry_1_0  (
+       .A0(un1_rlol_db_cnt_zero[0]),
+       .B0(rlol_p2),
+       .C0(rlol_db_cnt[1]),
+       .D0(VCC),
+       .A1(un1_rlol_db_cnt_zero[0]),
+       .B1(rlol_p2),
+       .C1(rlol_db_cnt[2]),
+       .D1(VCC),
+       .CIN(rlol_db_cnt_cry_0),
+       .COUT(rlol_db_cnt_cry_2),
+       .S0(rlol_db_cnt_cry_1_0_S0),
+       .S1(rlol_db_cnt_cry_1_0_S1)
+);
+defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INIT0=16'he101;
+defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INIT1=16'he101;
+defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INJECT1_0="NO";
+defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INJECT1_1="NO";
+// @16:625
+  CCU2C \un1_genblk2.rlol_db_cnt_s_3_0  (
+       .A0(rlol_db_cnt[3]),
+       .B0(rlol_p2),
+       .C0(un1_rlol_db_cnt_zero[0]),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol_db_cnt_cry_2),
+       .COUT(rlol_db_cnt_s_3_0_COUT),
+       .S0(rlol_db_cnt_s_3_0_S0),
+       .S1(rlol_db_cnt_s_3_0_S1)
+);
+defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INIT0=16'ha90a;
+defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INIT1=16'h5003;
+defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INJECT1_0="NO";
+defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INJECT1_1="NO";
+//@16:865
+//@16:492
+  VHI VCC_0 (
+       .Z(VCC)
+);
+// @16:865
+  VLO GND_cZ (
+       .Z(GND)
+);
+endmodule /* sgmii_ecp5rsl_core_Z2_layer1 */
+
+module sgmii_ecp5 (
+  hdoutp,
+  hdoutn,
+  hdinp,
+  hdinn,
+  rxrefclk,
+  tx_pclk,
+  txi_clk,
+  txdata,
+  tx_k,
+  xmit,
+  tx_disp_correct,
+  rxdata,
+  rx_k,
+  rx_disp_err,
+  rx_cv_err,
+  signal_detect_c,
+  rx_los_low_s,
+  lsm_status_s,
+  ctc_urun_s,
+  ctc_orun_s,
+  rx_cdr_lol_s,
+  ctc_ins_s,
+  ctc_del_s,
+  sli_rst,
+  tx_pwrup_c,
+  rx_pwrup_c,
+  sci_wrdata,
+  sci_addr,
+  sci_rddata,
+  sci_en_dual,
+  sci_sel_dual,
+  sci_en,
+  sci_sel,
+  sci_rd,
+  sci_wrn,
+  sci_int,
+  cyawstn,
+  serdes_pdb,
+  pll_refclki,
+  rsl_disable,
+  rsl_rst,
+  serdes_rst_dual_c,
+  rst_dual_c,
+  tx_serdes_rst_c,
+  tx_pcs_rst_c,
+  pll_lol,
+  rsl_tx_rdy,
+  rx_serdes_rst_c,
+  rx_pcs_rst_c,
+  rsl_rx_rdy
+)
+;
+output hdoutp ;
+output hdoutn ;
+input hdinp ;
+input hdinn ;
+input rxrefclk ;
+output tx_pclk ;
+input txi_clk ;
+input [7:0] txdata ;
+input [0:0] tx_k ;
+input [0:0] xmit ;
+input [0:0] tx_disp_correct ;
+output [7:0] rxdata ;
+output [0:0] rx_k ;
+output [0:0] rx_disp_err ;
+output [0:0] rx_cv_err ;
+input signal_detect_c ;
+output rx_los_low_s ;
+output lsm_status_s ;
+output ctc_urun_s ;
+output ctc_orun_s ;
+output rx_cdr_lol_s ;
+output ctc_ins_s ;
+output ctc_del_s ;
+input sli_rst ;
+input tx_pwrup_c ;
+input rx_pwrup_c ;
+input [7:0] sci_wrdata ;
+input [5:0] sci_addr ;
+output [7:0] sci_rddata ;
+input sci_en_dual ;
+input sci_sel_dual ;
+input sci_en ;
+input sci_sel ;
+input sci_rd ;
+input sci_wrn ;
+output sci_int ;
+input cyawstn ;
+input serdes_pdb ;
+input pll_refclki ;
+input rsl_disable ;
+input rsl_rst ;
+input serdes_rst_dual_c ;
+input rst_dual_c ;
+input tx_serdes_rst_c ;
+input tx_pcs_rst_c ;
+output pll_lol ;
+output rsl_tx_rdy ;
+input rx_serdes_rst_c ;
+input rx_pcs_rst_c ;
+output rsl_rx_rdy ;
+wire hdoutp ;
+wire hdoutn ;
+wire hdinp ;
+wire hdinn ;
+wire rxrefclk ;
+wire tx_pclk ;
+wire txi_clk ;
+wire signal_detect_c ;
+wire rx_los_low_s ;
+wire lsm_status_s ;
+wire ctc_urun_s ;
+wire ctc_orun_s ;
+wire rx_cdr_lol_s ;
+wire ctc_ins_s ;
+wire ctc_del_s ;
+wire sli_rst ;
+wire tx_pwrup_c ;
+wire rx_pwrup_c ;
+wire sci_en_dual ;
+wire sci_sel_dual ;
+wire sci_en ;
+wire sci_sel ;
+wire sci_rd ;
+wire sci_wrn ;
+wire sci_int ;
+wire cyawstn ;
+wire serdes_pdb ;
+wire pll_refclki ;
+wire rsl_disable ;
+wire rsl_rst ;
+wire serdes_rst_dual_c ;
+wire rst_dual_c ;
+wire tx_serdes_rst_c ;
+wire tx_pcs_rst_c ;
+wire pll_lol ;
+wire rsl_tx_rdy ;
+wire rx_serdes_rst_c ;
+wire rx_pcs_rst_c ;
+wire rsl_rx_rdy ;
+wire rsl_tx_pcs_rst_c ;
+wire rsl_rx_pcs_rst_c ;
+wire rsl_rx_serdes_rst_c ;
+wire rsl_serdes_rst_dual_c ;
+wire rsl_tx_serdes_rst_c ;
+wire n47_1 ;
+wire n48_1 ;
+wire n1_1 ;
+wire n2_1 ;
+wire n3_1 ;
+wire n4_1 ;
+wire n5_1 ;
+wire n49_1 ;
+wire n6_1 ;
+wire n50_1 ;
+wire n7_1 ;
+wire n51_1 ;
+wire n8_1 ;
+wire n52_1 ;
+wire n9_1 ;
+wire n53_1 ;
+wire n54_1 ;
+wire n55_1 ;
+wire n56_1 ;
+wire n57_1 ;
+wire n58_1 ;
+wire n59_1 ;
+wire n60_1 ;
+wire n61_1 ;
+wire n62_1 ;
+wire n63_1 ;
+wire n64_1 ;
+wire n65_1 ;
+wire n10_1 ;
+wire n66_1 ;
+wire n67_1 ;
+wire n68_1 ;
+wire n69_1 ;
+wire n70_1 ;
+wire n71_1 ;
+wire n72_1 ;
+wire n73_1 ;
+wire n74_1 ;
+wire n75_1 ;
+wire n76_1 ;
+wire n77_1 ;
+wire n78_1 ;
+wire n79_1 ;
+wire n80_1 ;
+wire n81_1 ;
+wire n82_1 ;
+wire n83_1 ;
+wire n84_1 ;
+wire n85_1 ;
+wire n86_1 ;
+wire n87_1 ;
+wire n88_1 ;
+wire n11_1 ;
+wire n89_1 ;
+wire n12_1 ;
+wire n90_1 ;
+wire n13_1 ;
+wire n91_1 ;
+wire n92_1 ;
+wire n93_1 ;
+wire n94_1 ;
+wire n95_1 ;
+wire n14_1 ;
+wire n96_1 ;
+wire n15_1 ;
+wire n97_1 ;
+wire n98_1 ;
+wire n99_1 ;
+wire n100_1 ;
+wire n101_1 ;
+wire n112_1 ;
+wire n16_1 ;
+wire n17_1 ;
+wire n18_1 ;
+wire n19_1 ;
+wire n20_1 ;
+wire n21_1 ;
+wire n22_1 ;
+wire n23_1 ;
+wire n24_1 ;
+wire n25_1 ;
+wire n26_1 ;
+wire n27_1 ;
+wire n28_1 ;
+wire n29_1 ;
+wire n30_1 ;
+wire n31_1 ;
+wire n32_1 ;
+wire n33_1 ;
+wire n34_1 ;
+wire n35_1 ;
+wire n36_1 ;
+wire n37_1 ;
+wire n38_1 ;
+wire n39_1 ;
+wire n40_1 ;
+wire n41_1 ;
+wire n42_1 ;
+wire n43_1 ;
+wire n46_1 ;
+wire GND ;
+wire VCC ;
+  VHI VCC_0 (
+       .Z(VCC)
+);
+  VLO GND_0 (
+       .Z(GND)
+);
+// @16:865
+  PUR PUR_INST (
+       .PUR(VCC)
+);
+// @16:865
+  GSR GSR_INST (
+       .GSR(VCC)
+);
+// @8:162
+(* CHAN="CH0" *)  DCUA DCU0_inst (
+       .CH0_HDINP(hdinp),
+       .CH1_HDINP(GND),
+       .CH0_HDINN(hdinn),
+       .CH1_HDINN(GND),
+       .D_TXBIT_CLKP_FROM_ND(GND),
+       .D_TXBIT_CLKN_FROM_ND(GND),
+       .D_SYNC_ND(GND),
+       .D_TXPLL_LOL_FROM_ND(GND),
+       .CH0_RX_REFCLK(rxrefclk),
+       .CH1_RX_REFCLK(GND),
+       .CH0_FF_RXI_CLK(tx_pclk),
+       .CH1_FF_RXI_CLK(VCC),
+       .CH0_FF_TXI_CLK(txi_clk),
+       .CH1_FF_TXI_CLK(VCC),
+       .CH0_FF_EBRD_CLK(tx_pclk),
+       .CH1_FF_EBRD_CLK(VCC),
+       .CH0_FF_TX_D_0(txdata[0]),
+       .CH1_FF_TX_D_0(GND),
+       .CH0_FF_TX_D_1(txdata[1]),
+       .CH1_FF_TX_D_1(GND),
+       .CH0_FF_TX_D_2(txdata[2]),
+       .CH1_FF_TX_D_2(GND),
+       .CH0_FF_TX_D_3(txdata[3]),
+       .CH1_FF_TX_D_3(GND),
+       .CH0_FF_TX_D_4(txdata[4]),
+       .CH1_FF_TX_D_4(GND),
+       .CH0_FF_TX_D_5(txdata[5]),
+       .CH1_FF_TX_D_5(GND),
+       .CH0_FF_TX_D_6(txdata[6]),
+       .CH1_FF_TX_D_6(GND),
+       .CH0_FF_TX_D_7(txdata[7]),
+       .CH1_FF_TX_D_7(GND),
+       .CH0_FF_TX_D_8(tx_k[0]),
+       .CH1_FF_TX_D_8(GND),
+       .CH0_FF_TX_D_9(GND),
+       .CH1_FF_TX_D_9(GND),
+       .CH0_FF_TX_D_10(xmit[0]),
+       .CH1_FF_TX_D_10(GND),
+       .CH0_FF_TX_D_11(tx_disp_correct[0]),
+       .CH1_FF_TX_D_11(GND),
+       .CH0_FF_TX_D_12(GND),
+       .CH1_FF_TX_D_12(GND),
+       .CH0_FF_TX_D_13(GND),
+       .CH1_FF_TX_D_13(GND),
+       .CH0_FF_TX_D_14(GND),
+       .CH1_FF_TX_D_14(GND),
+       .CH0_FF_TX_D_15(GND),
+       .CH1_FF_TX_D_15(GND),
+       .CH0_FF_TX_D_16(GND),
+       .CH1_FF_TX_D_16(GND),
+       .CH0_FF_TX_D_17(GND),
+       .CH1_FF_TX_D_17(GND),
+       .CH0_FF_TX_D_18(GND),
+       .CH1_FF_TX_D_18(GND),
+       .CH0_FF_TX_D_19(GND),
+       .CH1_FF_TX_D_19(GND),
+       .CH0_FF_TX_D_20(GND),
+       .CH1_FF_TX_D_20(GND),
+       .CH0_FF_TX_D_21(GND),
+       .CH1_FF_TX_D_21(GND),
+       .CH0_FF_TX_D_22(GND),
+       .CH1_FF_TX_D_22(GND),
+       .CH0_FF_TX_D_23(GND),
+       .CH1_FF_TX_D_23(GND),
+       .CH0_FFC_EI_EN(GND),
+       .CH1_FFC_EI_EN(GND),
+       .CH0_FFC_PCIE_DET_EN(GND),
+       .CH1_FFC_PCIE_DET_EN(GND),
+       .CH0_FFC_PCIE_CT(GND),
+       .CH1_FFC_PCIE_CT(GND),
+       .CH0_FFC_SB_INV_RX(GND),
+       .CH1_FFC_SB_INV_RX(GND),
+       .CH0_FFC_ENABLE_CGALIGN(GND),
+       .CH1_FFC_ENABLE_CGALIGN(GND),
+       .CH0_FFC_SIGNAL_DETECT(signal_detect_c),
+       .CH1_FFC_SIGNAL_DETECT(GND),
+       .CH0_FFC_FB_LOOPBACK(GND),
+       .CH1_FFC_FB_LOOPBACK(GND),
+       .CH0_FFC_SB_PFIFO_LP(GND),
+       .CH1_FFC_SB_PFIFO_LP(GND),
+       .CH0_FFC_PFIFO_CLR(GND),
+       .CH1_FFC_PFIFO_CLR(GND),
+       .CH0_FFC_RATE_MODE_RX(GND),
+       .CH1_FFC_RATE_MODE_RX(GND),
+       .CH0_FFC_RATE_MODE_TX(GND),
+       .CH1_FFC_RATE_MODE_TX(GND),
+       .CH0_FFC_DIV11_MODE_RX(GND),
+       .CH1_FFC_DIV11_MODE_RX(GND),
+       .CH0_FFC_RX_GEAR_MODE(GND),
+       .CH1_FFC_RX_GEAR_MODE(GND),
+       .CH0_FFC_TX_GEAR_MODE(GND),
+       .CH1_FFC_TX_GEAR_MODE(GND),
+       .CH0_FFC_DIV11_MODE_TX(GND),
+       .CH1_FFC_DIV11_MODE_TX(GND),
+       .CH0_FFC_LDR_CORE2TX_EN(GND),
+       .CH1_FFC_LDR_CORE2TX_EN(GND),
+       .CH0_FFC_LANE_TX_RST(rsl_tx_pcs_rst_c),
+       .CH1_FFC_LANE_TX_RST(GND),
+       .CH0_FFC_LANE_RX_RST(rsl_rx_pcs_rst_c),
+       .CH1_FFC_LANE_RX_RST(GND),
+       .CH0_FFC_RRST(rsl_rx_serdes_rst_c),
+       .CH1_FFC_RRST(GND),
+       .CH0_FFC_TXPWDNB(tx_pwrup_c),
+       .CH1_FFC_TXPWDNB(GND),
+       .CH0_FFC_RXPWDNB(rx_pwrup_c),
+       .CH1_FFC_RXPWDNB(GND),
+       .CH0_LDR_CORE2TX(GND),
+       .CH1_LDR_CORE2TX(GND),
+       .D_SCIWDATA0(sci_wrdata[0]),
+       .D_SCIWDATA1(sci_wrdata[1]),
+       .D_SCIWDATA2(sci_wrdata[2]),
+       .D_SCIWDATA3(sci_wrdata[3]),
+       .D_SCIWDATA4(sci_wrdata[4]),
+       .D_SCIWDATA5(sci_wrdata[5]),
+       .D_SCIWDATA6(sci_wrdata[6]),
+       .D_SCIWDATA7(sci_wrdata[7]),
+       .D_SCIADDR0(sci_addr[0]),
+       .D_SCIADDR1(sci_addr[1]),
+       .D_SCIADDR2(sci_addr[2]),
+       .D_SCIADDR3(sci_addr[3]),
+       .D_SCIADDR4(sci_addr[4]),
+       .D_SCIADDR5(sci_addr[5]),
+       .D_SCIENAUX(sci_en_dual),
+       .D_SCISELAUX(sci_sel_dual),
+       .CH0_SCIEN(sci_en),
+       .CH1_SCIEN(GND),
+       .CH0_SCISEL(sci_sel),
+       .CH1_SCISEL(GND),
+       .D_SCIRD(sci_rd),
+       .D_SCIWSTN(sci_wrn),
+       .D_CYAWSTN(cyawstn),
+       .D_FFC_SYNC_TOGGLE(GND),
+       .D_FFC_DUAL_RST(rst_dual_c),
+       .D_FFC_MACRO_RST(rsl_serdes_rst_dual_c),
+       .D_FFC_MACROPDB(serdes_pdb),
+       .D_FFC_TRST(rsl_tx_serdes_rst_c),
+       .CH0_FFC_CDR_EN_BITSLIP(GND),
+       .CH1_FFC_CDR_EN_BITSLIP(GND),
+       .D_SCAN_ENABLE(GND),
+       .D_SCAN_IN_0(GND),
+       .D_SCAN_IN_1(GND),
+       .D_SCAN_IN_2(GND),
+       .D_SCAN_IN_3(GND),
+       .D_SCAN_IN_4(GND),
+       .D_SCAN_IN_5(GND),
+       .D_SCAN_IN_6(GND),
+       .D_SCAN_IN_7(GND),
+       .D_SCAN_MODE(GND),
+       .D_SCAN_RESET(GND),
+       .D_CIN0(GND),
+       .D_CIN1(GND),
+       .D_CIN2(GND),
+       .D_CIN3(GND),
+       .D_CIN4(GND),
+       .D_CIN5(GND),
+       .D_CIN6(GND),
+       .D_CIN7(GND),
+       .D_CIN8(GND),
+       .D_CIN9(GND),
+       .D_CIN10(GND),
+       .D_CIN11(GND),
+       .CH0_HDOUTP(hdoutp),
+       .CH1_HDOUTP(n47_1),
+       .CH0_HDOUTN(hdoutn),
+       .CH1_HDOUTN(n48_1),
+       .D_TXBIT_CLKP_TO_ND(n1_1),
+       .D_TXBIT_CLKN_TO_ND(n2_1),
+       .D_SYNC_PULSE2ND(n3_1),
+       .D_TXPLL_LOL_TO_ND(n4_1),
+       .CH0_FF_RX_F_CLK(n5_1),
+       .CH1_FF_RX_F_CLK(n49_1),
+       .CH0_FF_RX_H_CLK(n6_1),
+       .CH1_FF_RX_H_CLK(n50_1),
+       .CH0_FF_TX_F_CLK(n7_1),
+       .CH1_FF_TX_F_CLK(n51_1),
+       .CH0_FF_TX_H_CLK(n8_1),
+       .CH1_FF_TX_H_CLK(n52_1),
+       .CH0_FF_RX_PCLK(n9_1),
+       .CH1_FF_RX_PCLK(n53_1),
+       .CH0_FF_TX_PCLK(tx_pclk),
+       .CH1_FF_TX_PCLK(n54_1),
+       .CH0_FF_RX_D_0(rxdata[0]),
+       .CH1_FF_RX_D_0(n55_1),
+       .CH0_FF_RX_D_1(rxdata[1]),
+       .CH1_FF_RX_D_1(n56_1),
+       .CH0_FF_RX_D_2(rxdata[2]),
+       .CH1_FF_RX_D_2(n57_1),
+       .CH0_FF_RX_D_3(rxdata[3]),
+       .CH1_FF_RX_D_3(n58_1),
+       .CH0_FF_RX_D_4(rxdata[4]),
+       .CH1_FF_RX_D_4(n59_1),
+       .CH0_FF_RX_D_5(rxdata[5]),
+       .CH1_FF_RX_D_5(n60_1),
+       .CH0_FF_RX_D_6(rxdata[6]),
+       .CH1_FF_RX_D_6(n61_1),
+       .CH0_FF_RX_D_7(rxdata[7]),
+       .CH1_FF_RX_D_7(n62_1),
+       .CH0_FF_RX_D_8(rx_k[0]),
+       .CH1_FF_RX_D_8(n63_1),
+       .CH0_FF_RX_D_9(rx_disp_err[0]),
+       .CH1_FF_RX_D_9(n64_1),
+       .CH0_FF_RX_D_10(rx_cv_err[0]),
+       .CH1_FF_RX_D_10(n65_1),
+       .CH0_FF_RX_D_11(n10_1),
+       .CH1_FF_RX_D_11(n66_1),
+       .CH0_FF_RX_D_12(n67_1),
+       .CH1_FF_RX_D_12(n68_1),
+       .CH0_FF_RX_D_13(n69_1),
+       .CH1_FF_RX_D_13(n70_1),
+       .CH0_FF_RX_D_14(n71_1),
+       .CH1_FF_RX_D_14(n72_1),
+       .CH0_FF_RX_D_15(n73_1),
+       .CH1_FF_RX_D_15(n74_1),
+       .CH0_FF_RX_D_16(n75_1),
+       .CH1_FF_RX_D_16(n76_1),
+       .CH0_FF_RX_D_17(n77_1),
+       .CH1_FF_RX_D_17(n78_1),
+       .CH0_FF_RX_D_18(n79_1),
+       .CH1_FF_RX_D_18(n80_1),
+       .CH0_FF_RX_D_19(n81_1),
+       .CH1_FF_RX_D_19(n82_1),
+       .CH0_FF_RX_D_20(n83_1),
+       .CH1_FF_RX_D_20(n84_1),
+       .CH0_FF_RX_D_21(n85_1),
+       .CH1_FF_RX_D_21(n86_1),
+       .CH0_FF_RX_D_22(n87_1),
+       .CH1_FF_RX_D_22(n88_1),
+       .CH0_FF_RX_D_23(n11_1),
+       .CH1_FF_RX_D_23(n89_1),
+       .CH0_FFS_PCIE_DONE(n12_1),
+       .CH1_FFS_PCIE_DONE(n90_1),
+       .CH0_FFS_PCIE_CON(n13_1),
+       .CH1_FFS_PCIE_CON(n91_1),
+       .CH0_FFS_RLOS(rx_los_low_s),
+       .CH1_FFS_RLOS(n92_1),
+       .CH0_FFS_LS_SYNC_STATUS(lsm_status_s),
+       .CH1_FFS_LS_SYNC_STATUS(n93_1),
+       .CH0_FFS_CC_UNDERRUN(ctc_urun_s),
+       .CH1_FFS_CC_UNDERRUN(n94_1),
+       .CH0_FFS_CC_OVERRUN(ctc_orun_s),
+       .CH1_FFS_CC_OVERRUN(n95_1),
+       .CH0_FFS_RXFBFIFO_ERROR(n14_1),
+       .CH1_FFS_RXFBFIFO_ERROR(n96_1),
+       .CH0_FFS_TXFBFIFO_ERROR(n15_1),
+       .CH1_FFS_TXFBFIFO_ERROR(n97_1),
+       .CH0_FFS_RLOL(rx_cdr_lol_s),
+       .CH1_FFS_RLOL(n98_1),
+       .CH0_FFS_SKP_ADDED(ctc_ins_s),
+       .CH1_FFS_SKP_ADDED(n99_1),
+       .CH0_FFS_SKP_DELETED(ctc_del_s),
+       .CH1_FFS_SKP_DELETED(n100_1),
+       .CH0_LDR_RX2CORE(n101_1),
+       .CH1_LDR_RX2CORE(n112_1),
+       .D_SCIRDATA0(sci_rddata[0]),
+       .D_SCIRDATA1(sci_rddata[1]),
+       .D_SCIRDATA2(sci_rddata[2]),
+       .D_SCIRDATA3(sci_rddata[3]),
+       .D_SCIRDATA4(sci_rddata[4]),
+       .D_SCIRDATA5(sci_rddata[5]),
+       .D_SCIRDATA6(sci_rddata[6]),
+       .D_SCIRDATA7(sci_rddata[7]),
+       .D_SCIINT(sci_int),
+       .D_SCAN_OUT_0(n16_1),
+       .D_SCAN_OUT_1(n17_1),
+       .D_SCAN_OUT_2(n18_1),
+       .D_SCAN_OUT_3(n19_1),
+       .D_SCAN_OUT_4(n20_1),
+       .D_SCAN_OUT_5(n21_1),
+       .D_SCAN_OUT_6(n22_1),
+       .D_SCAN_OUT_7(n23_1),
+       .D_COUT0(n24_1),
+       .D_COUT1(n25_1),
+       .D_COUT2(n26_1),
+       .D_COUT3(n27_1),
+       .D_COUT4(n28_1),
+       .D_COUT5(n29_1),
+       .D_COUT6(n30_1),
+       .D_COUT7(n31_1),
+       .D_COUT8(n32_1),
+       .D_COUT9(n33_1),
+       .D_COUT10(n34_1),
+       .D_COUT11(n35_1),
+       .D_COUT12(n36_1),
+       .D_COUT13(n37_1),
+       .D_COUT14(n38_1),
+       .D_COUT15(n39_1),
+       .D_COUT16(n40_1),
+       .D_COUT17(n41_1),
+       .D_COUT18(n42_1),
+       .D_COUT19(n43_1),
+       .D_REFCLKI(pll_refclki),
+       .D_FFS_PLOL(n46_1)
+);
+defparam DCU0_inst.D_MACROPDB = "0b1";
+defparam DCU0_inst.D_IB_PWDNB = "0b1";
+defparam DCU0_inst.D_XGE_MODE = "0b0";
+defparam DCU0_inst.D_LOW_MARK = "0d4";
+defparam DCU0_inst.D_HIGH_MARK = "0d12";
+defparam DCU0_inst.D_BUS8BIT_SEL = "0b0";
+defparam DCU0_inst.D_CDR_LOL_SET = "0b00";
+defparam DCU0_inst.D_BITCLK_LOCAL_EN = "0b1";
+defparam DCU0_inst.D_BITCLK_ND_EN = "0b0";
+defparam DCU0_inst.D_BITCLK_FROM_ND_EN = "0b0";
+defparam DCU0_inst.D_SYNC_LOCAL_EN = "0b1";
+defparam DCU0_inst.D_SYNC_ND_EN = "0b0";
+defparam DCU0_inst.CH0_UC_MODE = "0b0";
+defparam DCU0_inst.CH0_PCIE_MODE = "0b0";
+defparam DCU0_inst.CH0_RIO_MODE = "0b0";
+defparam DCU0_inst.CH0_WA_MODE = "0b0";
+defparam DCU0_inst.CH0_INVERT_RX = "0b0";
+defparam DCU0_inst.CH0_INVERT_TX = "0b0";
+defparam DCU0_inst.CH0_PRBS_SELECTION = "0b0";
+defparam DCU0_inst.CH0_GE_AN_ENABLE = "0b0";
+defparam DCU0_inst.CH0_PRBS_LOCK = "0b0";
+defparam DCU0_inst.CH0_PRBS_ENABLE = "0b0";
+defparam DCU0_inst.CH0_ENABLE_CG_ALIGN = "0b1";
+defparam DCU0_inst.CH0_TX_GEAR_MODE = "0b0";
+defparam DCU0_inst.CH0_RX_GEAR_MODE = "0b0";
+defparam DCU0_inst.CH0_PCS_DET_TIME_SEL = "0b00";
+defparam DCU0_inst.CH0_PCIE_EI_EN = "0b0";
+defparam DCU0_inst.CH0_TX_GEAR_BYPASS = "0b0";
+defparam DCU0_inst.CH0_ENC_BYPASS = "0b0";
+defparam DCU0_inst.CH0_SB_BYPASS = "0b0";
+defparam DCU0_inst.CH0_RX_SB_BYPASS = "0b0";
+defparam DCU0_inst.CH0_WA_BYPASS = "0b0";
+defparam DCU0_inst.CH0_DEC_BYPASS = "0b0";
+defparam DCU0_inst.CH0_CTC_BYPASS = "0b0";
+defparam DCU0_inst.CH0_RX_GEAR_BYPASS = "0b0";
+defparam DCU0_inst.CH0_LSM_DISABLE = "0b0";
+defparam DCU0_inst.CH0_MATCH_2_ENABLE = "0b1";
+defparam DCU0_inst.CH0_MATCH_4_ENABLE = "0b0";
+defparam DCU0_inst.CH0_MIN_IPG_CNT = "0b11";
+defparam DCU0_inst.CH0_CC_MATCH_1 = "0x000";
+defparam DCU0_inst.CH0_CC_MATCH_2 = "0x000";
+defparam DCU0_inst.CH0_CC_MATCH_3 = "0x1BC";
+defparam DCU0_inst.CH0_CC_MATCH_4 = "0x050";
+defparam DCU0_inst.CH0_UDF_COMMA_MASK = "0x3ff";
+defparam DCU0_inst.CH0_UDF_COMMA_A = "0x283";
+defparam DCU0_inst.CH0_UDF_COMMA_B = "0x17C";
+defparam DCU0_inst.CH0_RX_DCO_CK_DIV = "0b000";
+defparam DCU0_inst.CH0_RCV_DCC_EN = "0b0";
+defparam DCU0_inst.CH0_REQ_LVL_SET = "0b00";
+defparam DCU0_inst.CH0_REQ_EN = "0b1";
+defparam DCU0_inst.CH0_RTERM_RX = "0d22";
+defparam DCU0_inst.CH0_PDEN_SEL = "0b1";
+defparam DCU0_inst.CH0_LDR_RX2CORE_SEL = "0b0";
+defparam DCU0_inst.CH0_LDR_CORE2TX_SEL = "0b0";
+defparam DCU0_inst.CH0_TPWDNB = "0b1";
+defparam DCU0_inst.CH0_RATE_MODE_TX = "0b0";
+defparam DCU0_inst.CH0_RTERM_TX = "0d19";
+defparam DCU0_inst.CH0_TX_CM_SEL = "0b00";
+defparam DCU0_inst.CH0_TDRV_PRE_EN = "0b0";
+defparam DCU0_inst.CH0_TDRV_SLICE0_SEL = "0b01";
+defparam DCU0_inst.CH0_TDRV_SLICE1_SEL = "0b00";
+defparam DCU0_inst.CH0_TDRV_SLICE2_SEL = "0b01";
+defparam DCU0_inst.CH0_TDRV_SLICE3_SEL = "0b01";
+defparam DCU0_inst.CH0_TDRV_SLICE4_SEL = "0b01";
+defparam DCU0_inst.CH0_TDRV_SLICE5_SEL = "0b01";
+defparam DCU0_inst.CH0_TDRV_SLICE0_CUR = "0b101";
+defparam DCU0_inst.CH0_TDRV_SLICE1_CUR = "0b000";
+defparam DCU0_inst.CH0_TDRV_SLICE2_CUR = "0b11";
+defparam DCU0_inst.CH0_TDRV_SLICE3_CUR = "0b11";
+defparam DCU0_inst.CH0_TDRV_SLICE4_CUR = "0b11";
+defparam DCU0_inst.CH0_TDRV_SLICE5_CUR = "0b00";
+defparam DCU0_inst.CH0_TDRV_DAT_SEL = "0b00";
+defparam DCU0_inst.CH0_TX_DIV11_SEL = "0b0";
+defparam DCU0_inst.CH0_RPWDNB = "0b1";
+defparam DCU0_inst.CH0_RATE_MODE_RX = "0b0";
+defparam DCU0_inst.CH0_RLOS_SEL = "0b1";
+defparam DCU0_inst.CH0_RX_LOS_LVL = "0b010";
+defparam DCU0_inst.CH0_RX_LOS_CEQ = "0b11";
+defparam DCU0_inst.CH0_RX_LOS_HYST_EN = "0b0";
+defparam DCU0_inst.CH0_RX_LOS_EN = "0b1";
+defparam DCU0_inst.CH0_RX_DIV11_SEL = "0b0";
+defparam DCU0_inst.CH0_SEL_SD_RX_CLK = "0b0";
+defparam DCU0_inst.CH0_FF_RX_H_CLK_EN = "0b0";
+defparam DCU0_inst.CH0_FF_RX_F_CLK_DIS = "0b0";
+defparam DCU0_inst.CH0_FF_TX_H_CLK_EN = "0b0";
+defparam DCU0_inst.CH0_FF_TX_F_CLK_DIS = "0b0";
+defparam DCU0_inst.CH0_RX_RATE_SEL = "0d8";
+defparam DCU0_inst.CH0_TDRV_POST_EN = "0b0";
+defparam DCU0_inst.CH0_TX_POST_SIGN = "0b0";
+defparam DCU0_inst.CH0_TX_PRE_SIGN = "0b0";
+defparam DCU0_inst.CH0_RXTERM_CM = "0b11";
+defparam DCU0_inst.CH0_RXIN_CM = "0b11";
+defparam DCU0_inst.CH0_LEQ_OFFSET_SEL = "0b0";
+defparam DCU0_inst.CH0_LEQ_OFFSET_TRIM = "0b000";
+defparam DCU0_inst.D_TX_MAX_RATE = "2";
+defparam DCU0_inst.CH0_CDR_MAX_RATE = "2";
+defparam DCU0_inst.CH0_TXAMPLITUDE = "0d1100";
+defparam DCU0_inst.CH0_TXDEPRE = "DISABLED";
+defparam DCU0_inst.CH0_TXDEPOST = "DISABLED";
+defparam DCU0_inst.CH0_PROTOCOL = "GBE";
+defparam DCU0_inst.D_ISETLOS = "0d0";
+defparam DCU0_inst.D_SETIRPOLY_AUX = "0b00";
+defparam DCU0_inst.D_SETICONST_AUX = "0b00";
+defparam DCU0_inst.D_SETIRPOLY_CH = "0b00";
+defparam DCU0_inst.D_SETICONST_CH = "0b00";
+defparam DCU0_inst.D_REQ_ISET = "0b000";
+defparam DCU0_inst.D_PD_ISET = "0b00";
+defparam DCU0_inst.D_DCO_CALIB_TIME_SEL = "0b00";
+defparam DCU0_inst.CH0_DCOCTLGI = "0b010";
+defparam DCU0_inst.CH0_DCOATDDLY = "0b00";
+defparam DCU0_inst.CH0_DCOATDCFG = "0b00";
+defparam DCU0_inst.CH0_DCOBYPSATD = "0b1";
+defparam DCU0_inst.CH0_DCOSCALEI = "0b00";
+defparam DCU0_inst.CH0_DCOITUNE4LSB = "0b111";
+defparam DCU0_inst.CH0_DCOIOSTUNE = "0b000";
+defparam DCU0_inst.CH0_DCODISBDAVOID = "0b0";
+defparam DCU0_inst.CH0_DCOCALDIV = "0b001";
+defparam DCU0_inst.CH0_DCONUOFLSB = "0b101";
+defparam DCU0_inst.CH0_DCOIUPDNX2 = "0b1";
+defparam DCU0_inst.CH0_DCOSTEP = "0b00";
+defparam DCU0_inst.CH0_DCOSTARTVAL = "0b000";
+defparam DCU0_inst.CH0_DCOFLTDAC = "0b01";
+defparam DCU0_inst.CH0_DCOITUNE = "0b00";
+defparam DCU0_inst.CH0_DCOFTNRG = "0b110";
+defparam DCU0_inst.CH0_CDR_CNT4SEL = "0b00";
+defparam DCU0_inst.CH0_CDR_CNT8SEL = "0b00";
+defparam DCU0_inst.CH0_BAND_THRESHOLD = "0d0";
+defparam DCU0_inst.CH0_AUTO_FACQ_EN = "0b1";
+defparam DCU0_inst.CH0_AUTO_CALIB_EN = "0b1";
+defparam DCU0_inst.CH0_CALIB_CK_MODE = "0b0";
+defparam DCU0_inst.CH0_REG_BAND_OFFSET = "0d0";
+defparam DCU0_inst.CH0_REG_BAND_SEL = "0d0";
+defparam DCU0_inst.CH0_REG_IDAC_SEL = "0d0";
+defparam DCU0_inst.CH0_REG_IDAC_EN = "0b0";
+defparam DCU0_inst.D_TXPLL_PWDNB = "0b1";
+defparam DCU0_inst.D_SETPLLRC = "0d1";
+defparam DCU0_inst.D_REFCK_MODE = "0b001";
+defparam DCU0_inst.D_TX_VCO_CK_DIV = "0b000";
+defparam DCU0_inst.D_PLL_LOL_SET = "0b00";
+defparam DCU0_inst.D_RG_EN = "0b0";
+defparam DCU0_inst.D_RG_SET = "0b00";
+defparam DCU0_inst.D_CMUSETISCL4VCO = "0b000";
+defparam DCU0_inst.D_CMUSETI4VCO = "0b00";
+defparam DCU0_inst.D_CMUSETINITVCT = "0b00";
+defparam DCU0_inst.D_CMUSETZGM = "0b000";
+defparam DCU0_inst.D_CMUSETP2AGM = "0b000";
+defparam DCU0_inst.D_CMUSETP1GM = "0b000";
+defparam DCU0_inst.D_CMUSETI4CPZ = "0d3";
+defparam DCU0_inst.D_CMUSETI4CPP = "0d3";
+defparam DCU0_inst.D_CMUSETICP4Z = "0b101";
+defparam DCU0_inst.D_CMUSETICP4P = "0b01";
+defparam DCU0_inst.D_CMUSETBIASI = "0b00";
+// @8:424
+  sgmii_ecp5sll_core_Z1_layer1 sll_inst (
+       .tx_pclk(tx_pclk),
+       .sli_rst(sli_rst),
+       .pll_refclki(pll_refclki),
+       .pll_lock_i(pll_lol)
+);
+// @8:394
+  sgmii_ecp5rsl_core_Z2_layer1 rsl_inst (
+       .rx_pcs_rst_c(rx_pcs_rst_c),
+       .tx_pcs_rst_c(tx_pcs_rst_c),
+       .serdes_rst_dual_c(serdes_rst_dual_c),
+       .tx_serdes_rst_c(tx_serdes_rst_c),
+       .rsl_rx_pcs_rst_c(rsl_rx_pcs_rst_c),
+       .rsl_tx_pcs_rst_c(rsl_tx_pcs_rst_c),
+       .rsl_tx_serdes_rst_c(rsl_tx_serdes_rst_c),
+       .rsl_tx_rdy(rsl_tx_rdy),
+       .pll_lock_i(pll_lol),
+       .pll_refclki(pll_refclki),
+       .rsl_rx_rdy(rsl_rx_rdy),
+       .rsl_rst(rsl_rst),
+       .rxrefclk(rxrefclk),
+       .rsl_disable(rsl_disable),
+       .rx_serdes_rst_c(rx_serdes_rst_c),
+       .rst_dual_c(rst_dual_c),
+       .rx_cdr_lol_s(rx_cdr_lol_s),
+       .rx_los_low_s(rx_los_low_s),
+       .rsl_rx_serdes_rst_c(rsl_rx_serdes_rst_c),
+       .rsl_serdes_rst_dual_c(rsl_serdes_rst_dual_c)
+);
+endmodule /* sgmii_ecp5 */
+

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_cck.rpt.db b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_cck.rpt.db
new file mode 100644 (file)
index 0000000..029fa7a
Binary files /dev/null and b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_cck.rpt.db differ

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt.db b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt.db
new file mode 100644 (file)
index 0000000..029fa7a
Binary files /dev/null and b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt.db differ

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_synplify.lpf b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_synplify.lpf
new file mode 100644 (file)
index 0000000..9cbac38
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_synplify.lpf
@@ -0,0 +1,29 @@
+#
+# Logical Preferences generated for Lattice by Synplify maplat, Build 1796R.
+#
+
+# Period Constraints 
+#FREQUENCY PORT "pll_refclki" 100.0 MHz;
+#FREQUENCY PORT "rxrefclk" 100.0 MHz;
+#FREQUENCY NET "tx_pclk" 100.0 MHz;
+
+
+# Output Constraints 
+
+# Input Constraints 
+
+# Point-to-point Delay Constraints 
+
+
+
+# Block Path Constraints 
+#BLOCK PATH FROM CLKNET "tx_pclk" TO CLKNET "rxrefclk";
+#BLOCK PATH FROM CLKNET "tx_pclk" TO CLKNET "pll_refclki";
+#BLOCK PATH FROM CLKNET "rxrefclk" TO CLKNET "tx_pclk";
+#BLOCK PATH FROM CLKNET "rxrefclk" TO CLKNET "pll_refclki";
+#BLOCK PATH FROM CLKNET "pll_refclki" TO CLKNET "tx_pclk";
+#BLOCK PATH FROM CLKNET "pll_refclki" TO CLKNET "rxrefclk";
+
+BLOCK ASYNCPATHS;
+
+# End of generated Logical Preferences.

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_synplify_tmp2.lpf b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_synplify_tmp2.lpf
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_synplify_tmp4.lpf b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_synplify_tmp4.lpf
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_synplify_tmp8.lpf b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_synplify_tmp8.lpf
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/layer0.tlg.rptmap b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/layer0.tlg.rptmap
new file mode 100644 (file)
index 0000000..3910cac
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/layer0.tlg.rptmap
@@ -0,0 +1 @@
+./synwork/layer0.tlg,layer0.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages.

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/layer1.tlg.rptmap b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/layer1.tlg.rptmap
new file mode 100644 (file)
index 0000000..af92e0b
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/layer1.tlg.rptmap
@@ -0,0 +1 @@
+./synwork/layer1.tlg,layer1.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages.

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/linker.rpt.rptmap b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/linker.rpt.rptmap
new file mode 100644 (file)
index 0000000..3793ead
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/linker.rpt.rptmap
@@ -0,0 +1 @@
+./synwork/sgmii_ecp5_comp.linkerlog,linker.rpt,Summary of linker messages for components that did not bind

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/metrics.db b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/metrics.db
new file mode 100644 (file)
index 0000000..4a54f9a
Binary files /dev/null and b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/metrics.db differ

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_notes.txt b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_notes.txt
new file mode 100644 (file)
index 0000000..ae389c2
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_notes.txt
@@ -0,0 +1,16 @@
+@N|Running in 64-bit mode
+@N|Running in 64-bit mode
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
+@N|Running in 64-bit mode
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1.
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work.
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work.
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment.
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment.
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work.
+@N: CL201 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state.
+@N|Running in 64-bit mode
+

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_runstatus.xml b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_runstatus.xml
new file mode 100644 (file)
index 0000000..ca7d50b
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_runstatus.xml
@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the job information from compiler to be displayed as part of the summary report.
+*******************************************************************************************-->
+
+<job_run_status name="compiler"> 
+  <report_link name="Detailed report">
+    <data>/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr</data>
+    <title>Synopsys HDL Compiler</title>
+  </report_link> 
+  <job_status>
+    <data>Completed    </data>
+  </job_status>
+<job_info> 
+                       <info name="Notes">
+  <data>15</data>
+  <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_notes.txt</data></report_link>
+  </info>
+                       <info name="Warnings">
+  <data>77</data>
+  <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt</data></report_link>
+  </info>
+                       <info name="Errors">
+  <data>0</data>
+  <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_errors.txt</data></report_link>
+  </info>
+                       <info name="CPU Time">
+  <data>-</data>
+  </info>
+                       <info name="Real Time">
+  <data>00h:00m:02s</data>
+  </info>
+                       <info name="Peak Memory">
+  <data>-</data>
+  </info>
+                       <info name="Date &amp;Time">
+  <data type="timestamp">1557482336</data>
+  </info>
+                       </job_info>
+</job_run_status>
\ No newline at end of file

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt
new file mode 100644 (file)
index 0000000..0eac89c
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_compiler_warnings.txt
@@ -0,0 +1,78 @@
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 17 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_unlock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 4 to 3 of genblk5.rdiff_comp_lock[4:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[2]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[16]. Make sure that there are no unused intermediate registers.
+

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_area_report.xml b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_area_report.xml
new file mode 100644 (file)
index 0000000..58aa421
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_area_report.xml
@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the area information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<report_table display_priority="1" name="Area Summary">
+<report_link name="Detailed report">
+<data>/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_resourceusage.rpt</data>
+<title>Resource Usage</title>
+</report_link>
+<parameter tooltip="Total Register bits used" name="Register bits">
+<data>221</data>
+</parameter>
+<parameter tooltip="Total I/O cells used" name="I/O cells">
+<data>0</data>
+</parameter>
+<parameter tcl_name="v_ram" tooltip="Total Block RAMs used" name="Block RAMs">
+<data>0</data>
+</parameter>
+<parameter tcl_name="dsp_used" tooltip="Total DSPs used" name="DSPs">
+<data>0</data>
+</parameter>
+<parameter tcl_name="total_luts" tooltip="Total ORCA LUTs used" name="ORCA LUTs">
+<data>153</data>
+</parameter>
+</report_table>

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_errors.txt b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_errors.txt
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt
new file mode 100644 (file)
index 0000000..89ed59a
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt
@@ -0,0 +1,22 @@
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+@N: MO225 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":909:3:909:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":527:3:527:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] 
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.edn
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_opt_report.xml b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_opt_report.xml
new file mode 100644 (file)
index 0000000..37c27e7
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_opt_report.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the optimization information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<report_table display_priority="3" name="Optimizations Summary">
+<parameter tooltip="Non-gated/non-generated clock trees / Gated/generated clock trees" name="Combined Clock Conversion">
+<data>3 / 0</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_combined_clk.rpt</data>
+<title>START OF CLOCK OPTIMIZATION REPORT</title>
+</report_link>
+</parameter>
+</report_table>

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_runstatus.xml b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_runstatus.xml
new file mode 100644 (file)
index 0000000..aa1f7f0
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_runstatus.xml
@@ -0,0 +1,46 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the job information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<job_run_status name="Mapper">
+<report_link name="Detailed report">
+<data>/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr</data>
+<title>Synopsys Lattice Technology Mapper</title>
+</report_link>
+<job_status>
+<data>Completed</data>
+</job_status>
+<job_info>
+<info name="Notes">
+<data>22</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_notes.txt</data>
+</report_link>
+</info>
+<info name="Warnings">
+<data>4</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt</data>
+</report_link>
+</info>
+<info name="Errors">
+<data>0</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_errors.txt</data>
+</report_link>
+</info>
+<info name="CPU Time">
+<data>0h:00m:03s</data>
+</info>
+<info name="Real Time">
+<data>0h:00m:03s</data>
+</info>
+<info name="Peak Memory">
+<data>153MB</data>
+</info>
+<info name="Date &amp; Time">
+<data type="timestamp">1557482342</data>
+</info>
+</job_info>
+</job_run_status>

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_timing_report.xml b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_timing_report.xml
new file mode 100644 (file)
index 0000000..354cbb6
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_timing_report.xml
@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+Max Top 5 critical clocks will be reported. For rest user needs to refer to Detailed report
+*******************************************************************************************-->
+<report_table display_priority="2" name="Timing Summary">
+<report_link name="Detailed report">
+<data>/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr</data>
+<title>START OF TIMING REPORT</title>
+</report_link>
+<row>
+<data tcl_name="clock_name">Clock Name</data>
+<data tcl_name="req_freq">Req Freq</data>
+<data tcl_name="est_freq">Est Freq</data>
+<data tcl_name="slack">Slack</data>
+</row>
+<row>
+<data>sgmii_ecp5|pll_refclki</data>
+<data>100.0 MHz</data>
+<data>168.9 MHz</data>
+<data>4.079</data>
+</row>
+<row>
+<data>sgmii_ecp5|rxrefclk</data>
+<data>100.0 MHz</data>
+<data>170.5 MHz</data>
+<data>4.136</data>
+</row>
+<row>
+<data>sgmii_ecp5|tx_pclk_inferred_clock</data>
+<data>100.0 MHz</data>
+<data>237.5 MHz</data>
+<data>5.789</data>
+</row>
+<row>
+<data>System</data>
+<data>100.0 MHz</data>
+<data>840.7 MHz</data>
+<data>8.810</data>
+</row>
+</report_table>

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt
new file mode 100644 (file)
index 0000000..d44b509
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_fpga_mapper_warnings.txt
@@ -0,0 +1,4 @@
+@W: MT246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":162:4:162:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"
+@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"
+@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk"

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_errors.txt b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_errors.txt
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt
new file mode 100644 (file)
index 0000000..a540d08
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt
@@ -0,0 +1,9 @@
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances.
+@N: MO225 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_runstatus.xml b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_runstatus.xml
new file mode 100644 (file)
index 0000000..127251d
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_runstatus.xml
@@ -0,0 +1,46 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the job information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<job_run_status name="Mapper">
+<report_link name="Detailed report">
+<data>/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr</data>
+<title>Synopsys Lattice Technology Pre-mapping</title>
+</report_link>
+<job_status>
+<data>Completed</data>
+</job_status>
+<job_info>
+<info name="Notes">
+<data>9</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_notes.txt</data>
+</report_link>
+</info>
+<info name="Warnings">
+<data>3</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt</data>
+</report_link>
+</info>
+<info name="Errors">
+<data>0</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_errors.txt</data>
+</report_link>
+</info>
+<info name="CPU Time">
+<data>0h:00m:00s</data>
+</info>
+<info name="Real Time">
+<data>0h:00m:00s</data>
+</info>
+<info name="Peak Memory">
+<data>144MB</data>
+</info>
+<info name="Date &amp; Time">
+<data type="timestamp">1557482338</data>
+</info>
+</job_info>
+</job_run_status>

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt
new file mode 100644 (file)
index 0000000..47b05ba
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/report/sgmii_ecp5_premap_warnings.txt
@@ -0,0 +1,3 @@
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr
new file mode 100644 (file)
index 0000000..77a0cae
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr
@@ -0,0 +1,352 @@
+Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
+VHDL syntax check successful!
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Fri May 10 11:58:55 2019
+
+###########################################################]
+Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
+Verilog syntax check successful!
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Fri May 10 11:58:55 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Top entity is set to sgmii_ecp5.
+VHDL syntax check successful!
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1.
+Post processing for work.sgmii_ecp5.v1
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB)
+
+
+Process completed successfully.
+# Fri May 10 11:58:55 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
+Verilog syntax check successful!
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work.
+
+       PDATA_RST_VAL=32'b00000000000000000000000000000000
+   Generated name = sync_0s
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work.
+
+       PPROTOCOL=24'b010001110100001001000101
+       PLOL_SETTING=32'b00000000000000000000000000000000
+       PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100
+       PPCIE_MAX_RATE=24'b001100100010111000110101
+       PDIFF_VAL_LOCK=32'b00000000000000000000000000010011
+       PDIFF_VAL_UNLOCK=32'b00000000000000000000000000100111
+       PPCLK_TC=32'b00000000000000010000000000000000
+       PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000
+       PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000
+       PPCLK_DIV11_TC=32'b00000000000000000000000000000000
+       LPLL_LOSS_ST=2'b00
+       LPLL_PRELOSS_ST=2'b01
+       LPLL_PRELOCK_ST=2'b10
+       LPLL_LOCK_ST=2'b11
+       LRCLK_TC=16'b1111111111111111
+       LRCLK_TC_PUL_WIDTH=16'b0000000000110010
+       LHB_WAIT_CNT=8'b11111111
+       LPCLK_TC_0=32'b00000000000000001000000000000000
+       LPCLK_TC_1=32'b00000000000000010000000000000000
+       LPCLK_TC_2=32'b00000000000000100000000000000000
+       LPCLK_TC_3=32'b00000000000000101000000000000000
+       LPCLK_TC_4=32'b00000000000000010000000000000000
+       LPDIFF_LOCK_00=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_10=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_20=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_30=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_40=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_01=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_11=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_21=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_31=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_41=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_02=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_12=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_22=32'b00000000000000000000000011000100
+       LPDIFF_LOCK_32=32'b00000000000000000000000011110101
+       LPDIFF_LOCK_42=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_03=32'b00000000000000000000000010000011
+       LPDIFF_LOCK_13=32'b00000000000000000000000100000110
+       LPDIFF_LOCK_23=32'b00000000000000000000001000001100
+       LPDIFF_LOCK_33=32'b00000000000000000000001010001111
+       LPDIFF_LOCK_43=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011
+       LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110
+       LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010
+       LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001
+       LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111
+       LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000
+       LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000
+       LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000
+       LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100
+       LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001
+       LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010
+       LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111
+       LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001
+   Generated name = sgmii_ecp5sll_core_Z1_layer1
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment.
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 17 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work.
+
+       pnum_channels=32'b00000000000000000000000000000001
+       pprotocol=24'b010001110100001001000101
+       pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
+       pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_tx_rdy=32'b00000000000000000000101110111000
+       pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_rx_rdy=32'b00000000000000000000101110111000
+       wa_num_cycles=32'b00000000000000000000010000000000
+       dac_num_cycles=32'b00000000000000000000000000000011
+       lreset_pwidth=32'b00000000000000000000000000000011
+       lwait_b4_trst=32'b00000000000010111110101111000010
+       lwait_b4_trst_s=32'b00000000000000000000001100001101
+       lplol_cnt_width=32'b00000000000000000000000000010100
+       lwait_after_plol0=32'b00000000000000000000000000000100
+       lwait_b4_rrst=32'b00000000000000101100000000000000
+       lrrst_wait_width=32'b00000000000000000000000000010100
+       lwait_after_rrst=32'b00000000000011000011010100000000
+       lwait_b4_rrst_s=32'b00000000000000000000000111001100
+       lrlol_cnt_width=32'b00000000000000000000000000010011
+       lwait_after_lols=32'b00000000000000001100010000000000
+       lwait_after_lols_s=32'b00000000000000000000000010010110
+       llols_cnt_width=32'b00000000000000000000000000010010
+       lrdb_max=32'b00000000000000000000000000001111
+       ltxr_wait_width=32'b00000000000000000000000000001100
+       lrxr_wait_width=32'b00000000000000000000000000001100
+   Generated name = sgmii_ecp5rsl_core_Z2_layer1
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_unlock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 4 to 3 of genblk5.rdiff_comp_lock[4:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[2]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[16]. Make sure that there are no unused intermediate registers.
+@N: CL201 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state.
+Extracted state machine for register sll_state
+State machine has 4 reachable states with original encodings of:
+   00
+   01
+   10
+   11
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB)
+
+
+Process completed successfully.
+# Fri May 10 11:58:56 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+
+=======================================================================================
+For a summary of linker messages for components that did not bind, please see log file:
+@L: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.linkerlog
+=======================================================================================
+
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 11:58:56 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 11:58:56 2019
+
+###########################################################]

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr.db b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr.db
new file mode 100644 (file)
index 0000000..d028ab5
Binary files /dev/null and b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr.db differ

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr.rptmap b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr.rptmap
new file mode 100644 (file)
index 0000000..14937c8
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_compiler.srr.rptmap
@@ -0,0 +1 @@
+./synlog/sgmii_ecp5_compiler.srr,sgmii_ecp5_compiler.srr,Compile Log

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr
new file mode 100644 (file)
index 0000000..bc02d12
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr
@@ -0,0 +1,682 @@
+# Fri May 10 11:58:58 2019
+
+Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   10 -> 10
+   11 -> 11
+@N: MO225 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1304:0:1304:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1759:0:1759:5|Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":412:3:412:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":909:3:909:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":527:3:527:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":778:3:778:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":680:3:680:8|Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] 
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 145MB)
+
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+   1           0h:00m:01s                   5.36ns              154 /       221
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+3 non-gated/non-generated clock tree(s) driving 221 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+============================================= Non-Gated/Non-Generated Clocks =============================================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                                   
+--------------------------------------------------------------------------------------------------------------------------
+@K:CKID0001       pll_refclki         port                   91         rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]
+@K:CKID0002       rxrefclk            port                   77         rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]
+@K:CKID0003       DCU0_inst           DCUA                   53         sll_inst.pcount[21]                               
+==========================================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 148MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 148MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.edn
+M-2017.03L-SP1-1
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 153MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 153MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+@W: MT246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":162:4:162:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+@W: MT420 |Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"
+@W: MT420 |Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"
+@W: MT420 |Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk"
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Fri May 10 11:59:02 2019
+#
+
+
+Top view:               sgmii_ecp5
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.fdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 4.079
+
+                                      Requested     Estimated     Requested     Estimated               Clock        Clock              
+Starting Clock                        Frequency     Frequency     Period        Period        Slack     Type         Group              
+----------------------------------------------------------------------------------------------------------------------------------------
+sgmii_ecp5|pll_refclki                100.0 MHz     168.9 MHz     10.000        5.921         4.079     inferred     Inferred_clkgroup_0
+sgmii_ecp5|rxrefclk                   100.0 MHz     170.5 MHz     10.000        5.864         4.136     inferred     Inferred_clkgroup_1
+sgmii_ecp5|tx_pclk_inferred_clock     100.0 MHz     237.5 MHz     10.000        4.211         5.789     inferred     Inferred_clkgroup_2
+System                                100.0 MHz     840.7 MHz     10.000        1.190         8.810     system       system_clkgroup    
+========================================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                                                                |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+Starting                           Ending                             |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+System                             sgmii_ecp5|rxrefclk                |  10.000      8.811  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             System                             |  10.000      8.253  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             sgmii_ecp5|pll_refclki             |  10.000      4.079  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             sgmii_ecp5|tx_pclk_inferred_clock  |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|rxrefclk                System                             |  10.000      8.184  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|rxrefclk                sgmii_ecp5|rxrefclk                |  10.000      4.136  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|tx_pclk_inferred_clock  sgmii_ecp5|pll_refclki             |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|tx_pclk_inferred_clock  sgmii_ecp5|tx_pclk_inferred_clock  |  10.000      5.789  |  No paths    -      |  No paths    -      |  No paths    -    
+============================================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|pll_refclki
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                   Starting                                                        Arrival          
+Instance                           Reference                  Type        Pin     Net              Time        Slack
+                                   Clock                                                                            
+--------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[2]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[2]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[3]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[3]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[17]     sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[17]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[19]     sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[19]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[1]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[1]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[4]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[4]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[5]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[5]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[6]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[6]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[7]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[7]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[8]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[8]      0.907       4.684
+====================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                   Starting                                                          Required          
+Instance                           Reference                  Type        Pin     Net                Time         Slack
+                                   Clock                                                                               
+-----------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[19]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[19]     9.946        4.079
+rsl_inst.genblk1\.plol_cnt[17]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[17]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[18]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[18]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[15]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[15]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[16]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[16]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[13]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[13]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[14]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[14]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[11]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[11]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[12]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[12]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[9]      sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[9]      9.946        4.383
+=======================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.867
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     4.079
+
+    Number of logic level(s):                15
+    Starting point:                          rsl_inst.genblk1\.plol_cnt[2] / Q
+    Ending point:                            rsl_inst.genblk1\.plol_cnt[19] / D
+    The start point is clocked by            sgmii_ecp5|pll_refclki [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|pll_refclki [rising] on pin CK
+
+Instance / Net                                        Pin      Pin               Arrival     No. of    
+Name                                     Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[2]            FD1S3DX      Q        Out     0.907     0.907       -         
+plol_cnt[2]                              Net          -        -       -         -           2         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     Z        Out     0.606     1.513       -         
+un1_plol_cnt_tc_10                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     Z        Out     0.606     2.119       -         
+un1_plol_cnt_tc_14                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     Z        Out     0.762     2.881       -         
+un1_plol_cnt_tc                          Net          -        -       -         -           5         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     B        In      0.000     2.881       -         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     Z        Out     0.840     3.721       -         
+plol_cnt                                 Net          -        -       -         -           21        
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.721       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.621       -         
+plol_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.621       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.682       -         
+plol_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.682       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.743       -         
+plol_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.743       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.804       -         
+plol_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.804       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.865       -         
+plol_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.865       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.926       -         
+plol_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.926       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.987       -         
+plol_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.987       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.048       -         
+plol_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.048       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.109       -         
+plol_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.109       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        COUT     Out     0.061     5.170       -         
+plol_cnt_cry[18]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        CIN      In      0.000     5.170       -         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        S0       Out     0.698     5.867       -         
+plol_cnt_s[19]                           Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt[19]           FD1S3DX      D        In      0.000     5.867       -         
+=======================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|rxrefclk
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                    Starting                                                      Arrival          
+Instance                            Reference               Type        Pin     Net               Time        Slack
+                                    Clock                                                                          
+-------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[7]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[7]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[8]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[8]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[9]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[9]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[10]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[10]     0.907       4.136
+rsl_inst.genblk2\.rlols0_cnt[1]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[1]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[2]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[2]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[3]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[3]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[4]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[4]     0.907       4.170
+rsl_inst.genblk2\.rxs_rst           sgmii_ecp5|rxrefclk     FD1P3DX     Q       rxs_rst           1.015       4.700
+rsl_inst.genblk2\.rlol1_cnt[0]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[0]      0.907       4.742
+===================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                     Starting                                                         Required          
+Instance                             Reference               Type        Pin     Net                  Time         Slack
+                                     Clock                                                                              
+------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[17]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[17]      9.946        4.136
+rsl_inst.genblk2\.rlol1_cnt[18]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[18]      9.946        4.136
+rsl_inst.genblk2\.rlols0_cnt[17]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rlols0_cnt_s[17]     9.946        4.170
+rsl_inst.genblk2\.rlol1_cnt[15]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[15]      9.946        4.197
+rsl_inst.genblk2\.rlol1_cnt[16]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[16]      9.946        4.197
+rsl_inst.genblk2\.rlols0_cnt[15]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rlols0_cnt_s[15]     9.946        4.231
+rsl_inst.genblk2\.rlols0_cnt[16]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rlols0_cnt_s[16]     9.946        4.231
+rsl_inst.genblk2\.rlol1_cnt[13]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[13]      9.946        4.258
+rsl_inst.genblk2\.rlol1_cnt[14]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[14]      9.946        4.258
+rsl_inst.genblk2\.rlols0_cnt[13]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rlols0_cnt_s[13]     9.946        4.292
+========================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.809
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.136
+
+    Number of logic level(s):                14
+    Starting point:                          rsl_inst.genblk2\.rlol1_cnt[7] / Q
+    Ending point:                            rsl_inst.genblk2\.rlol1_cnt[18] / D
+    The start point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+
+Instance / Net                                         Pin      Pin               Arrival     No. of    
+Name                                      Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[7]            FD1P3DX      Q        Out     0.907     0.907       -         
+rlol1_cnt[7]                              Net          -        -       -         -           2         
+rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     Z        Out     0.606     1.513       -         
+rlol1_cnt_tc_1_10                         Net          -        -       -         -           1         
+rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     Z        Out     0.606     2.119       -         
+rlol1_cnt_tc_1_14                         Net          -        -       -         -           1         
+rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     Z        Out     0.768     2.887       -         
+rlol1_cnt_tc_1                            Net          -        -       -         -           6         
+rsl_inst.genblk2\.rlos_db_p1_RNIS0OP      ORCALUT4     A        In      0.000     2.887       -         
+rsl_inst.genblk2\.rlos_db_p1_RNIS0OP      ORCALUT4     Z        Out     0.837     3.724       -         
+rlol1_cnt                                 Net          -        -       -         -           20        
+rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.724       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.624       -         
+rlol1_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.624       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.685       -         
+rlol1_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.685       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.746       -         
+rlol1_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.746       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.807       -         
+rlol1_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.807       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.868       -         
+rlol1_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.868       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.929       -         
+rlol1_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.929       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.990       -         
+rlol1_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.990       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.051       -         
+rlol1_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.051       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.112       -         
+rlol1_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.112       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        S1       Out     0.698     5.809       -         
+rlol1_cnt_s[18]                           Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt[18]           FD1P3DX      D        In      0.000     5.809       -         
+========================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: sgmii_ecp5|tx_pclk_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                            Starting                                                                   Arrival          
+Instance                    Reference                             Type        Pin     Net              Time        Slack
+                            Clock                                                                                       
+------------------------------------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1       sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p1     1.098       5.789
+sll_inst.ppul_sync_p2       sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p2     1.098       5.789
+sll_inst.pcount_diff[0]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_0      0.985       6.147
+sll_inst.pcount[0]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[0]        0.955       6.178
+sll_inst.pcount_diff[1]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_1      0.955       6.239
+sll_inst.pcount_diff[2]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_2      0.955       6.239
+sll_inst.pcount[1]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[1]        0.907       6.287
+sll_inst.pcount[2]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[2]        0.907       6.287
+sll_inst.pcount_diff[3]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_3      0.955       6.300
+sll_inst.pcount_diff[4]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_4      0.955       6.300
+========================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                             Starting                                                                                  Required          
+Instance                     Reference                             Type        Pin     Net                             Time         Slack
+                             Clock                                                                                                       
+-----------------------------------------------------------------------------------------------------------------------------------------
+sll_inst.pcount[21]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[21]                    9.946        5.789
+sll_inst.pcount[19]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[19]                    9.946        5.850
+sll_inst.pcount[20]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[20]                    9.946        5.850
+sll_inst.pcount[17]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[17]                    9.946        5.911
+sll_inst.pcount[18]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[18]                    9.946        5.911
+sll_inst.pcount[15]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[15]                    9.946        5.972
+sll_inst.pcount[16]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[16]                    9.946        5.972
+sll_inst.pcount[13]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[13]                    9.946        6.033
+sll_inst.pcount[14]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[14]                    9.946        6.033
+sll_inst.pcount_diff[21]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3DX     D       un1_pcount_diff_1_s_21_0_S0     9.946        6.034
+=========================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      4.157
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 5.789
+
+    Number of logic level(s):                13
+    Starting point:                          sll_inst.ppul_sync_p1 / Q
+    Ending point:                            sll_inst.pcount[21] / D
+    The start point is clocked by            sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
+
+Instance / Net                             Pin      Pin               Arrival     No. of    
+Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1         FD1S3DX      Q        Out     1.098     1.098       -         
+ppul_sync_p1                  Net          -        -       -         -           25        
+sll_inst.pcount10_0_o3        ORCALUT4     A        In      0.000     1.098       -         
+sll_inst.pcount10_0_o3        ORCALUT4     Z        Out     0.851     1.950       -         
+N_8                           Net          -        -       -         -           25        
+sll_inst.pcount_cry_0[0]      CCU2C        A1       In      0.000     1.950       -         
+sll_inst.pcount_cry_0[0]      CCU2C        COUT     Out     0.900     2.850       -         
+pcount_cry[0]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[1]      CCU2C        CIN      In      0.000     2.850       -         
+sll_inst.pcount_cry_0[1]      CCU2C        COUT     Out     0.061     2.911       -         
+pcount_cry[2]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[3]      CCU2C        CIN      In      0.000     2.911       -         
+sll_inst.pcount_cry_0[3]      CCU2C        COUT     Out     0.061     2.972       -         
+pcount_cry[4]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[5]      CCU2C        CIN      In      0.000     2.972       -         
+sll_inst.pcount_cry_0[5]      CCU2C        COUT     Out     0.061     3.033       -         
+pcount_cry[6]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[7]      CCU2C        CIN      In      0.000     3.033       -         
+sll_inst.pcount_cry_0[7]      CCU2C        COUT     Out     0.061     3.094       -         
+pcount_cry[8]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[9]      CCU2C        CIN      In      0.000     3.094       -         
+sll_inst.pcount_cry_0[9]      CCU2C        COUT     Out     0.061     3.155       -         
+pcount_cry[10]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[11]     CCU2C        CIN      In      0.000     3.155       -         
+sll_inst.pcount_cry_0[11]     CCU2C        COUT     Out     0.061     3.216       -         
+pcount_cry[12]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[13]     CCU2C        CIN      In      0.000     3.216       -         
+sll_inst.pcount_cry_0[13]     CCU2C        COUT     Out     0.061     3.277       -         
+pcount_cry[14]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[15]     CCU2C        CIN      In      0.000     3.277       -         
+sll_inst.pcount_cry_0[15]     CCU2C        COUT     Out     0.061     3.338       -         
+pcount_cry[16]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[17]     CCU2C        CIN      In      0.000     3.338       -         
+sll_inst.pcount_cry_0[17]     CCU2C        COUT     Out     0.061     3.399       -         
+pcount_cry[18]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[19]     CCU2C        CIN      In      0.000     3.399       -         
+sll_inst.pcount_cry_0[19]     CCU2C        COUT     Out     0.061     3.460       -         
+pcount_cry[20]                Net          -        -       -         -           1         
+sll_inst.pcount_s_0[21]       CCU2C        CIN      In      0.000     3.460       -         
+sll_inst.pcount_s_0[21]       CCU2C        S0       Out     0.698     4.157       -         
+pcount_s[21]                  Net          -        -       -         -           1         
+sll_inst.pcount[21]           FD1S3DX      D        In      0.000     4.157       -         
+============================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                                 Arrival          
+Instance      Reference     Type     Pin              Net              Time        Slack
+              Clock                                                                     
+----------------------------------------------------------------------------------------
+DCU0_inst     System        DCUA     CH0_FFS_RLOL     rx_cdr_lol_s     0.000       8.810
+DCU0_inst     System        DCUA     CH0_FFS_RLOS     rx_los_low_s     0.000       8.810
+========================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                       Starting                                                            Required          
+Instance                                               Reference     Type        Pin     Net                               Time         Slack
+                                                       Clock                                                                                 
+---------------------------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     SP      un2_rdo_serdes_rst_dual_c_2_i     9.806        8.810
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     D       rxpr_appd_RNO[0]                  9.946        9.556
+rsl_inst.genblk2\.rlol_p1                              System        FD1S3DX     D       rx_cdr_lol_s                      9.946        9.946
+rsl_inst.genblk2\.rlos_p1                              System        FD1S3DX     D       rx_los_low_s                      9.946        9.946
+=============================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.194
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.806
+
+    - Propagation time:                      0.996
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 8.810
+
+    Number of logic level(s):                2
+    Starting point:                          DCU0_inst / CH0_FFS_RLOL
+    Ending point:                            rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+
+Instance / Net                                                            Pin              Pin               Arrival     No. of    
+Name                                                         Type         Name             Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------------------------------------------------------
+DCU0_inst                                                    DCUA         CH0_FFS_RLOL     Out     0.000     0.000       -         
+rx_cdr_lol_s                                                 Net          -                -       -         -           4         
+rsl_inst.un2_rdo_serdes_rst_dual_c_1_1                       ORCALUT4     A                In      0.000     0.000       -         
+rsl_inst.un2_rdo_serdes_rst_dual_c_1_1                       ORCALUT4     Z                Out     0.606     0.606       -         
+un2_rdo_serdes_rst_dual_c_1_1                                Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0]     ORCALUT4     B                In      0.000     0.606       -         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0]     ORCALUT4     Z                Out     0.390     0.996       -         
+un2_rdo_serdes_rst_dual_c_2_i                                Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]           FD1P3DX      SP               In      0.000     0.996       -         
+===================================================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 221 of 24288 (1%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+CCU2C:          113
+DCUA:           1
+FD1P3BX:        20
+FD1P3DX:        92
+FD1S3BX:        12
+FD1S3DX:        97
+GSR:            1
+INV:            3
+ORCALUT4:       153
+PFUMX:          2
+PUR:            1
+VHI:            6
+VLO:            6
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 153MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Fri May 10 11:59:02 2019
+
+###########################################################]

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr.db b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr.db
new file mode 100644 (file)
index 0000000..1e1a850
Binary files /dev/null and b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.srr.db differ

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.szr b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.szr
new file mode 100644 (file)
index 0000000..014df6d
Binary files /dev/null and b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.szr differ

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.xck b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.xck
new file mode 100644 (file)
index 0000000..eb3488c
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_fpga_mapper.xck
@@ -0,0 +1,3 @@
+CKID0001:@|S:pll_refclki@|E:rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001 
+CKID0002:@|S:rxrefclk@|E:rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]@|F:@syn_sample_clock_path==CKID0002@|M:ClockId0002 
+CKID0003:@|S:DCU0_inst@|E:sll_inst.pcount[21]@|F:@syn_sample_clock_path==CKID0003@|M:ClockId0003 

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_multi_srs_gen.srr b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_multi_srs_gen.srr
new file mode 100644 (file)
index 0000000..be17fbb
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_multi_srs_gen.srr
@@ -0,0 +1,11 @@
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 11:58:57 2019
+
+###########################################################]

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_multi_srs_gen.srr.db b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_multi_srs_gen.srr.db
new file mode 100644 (file)
index 0000000..029fa7a
Binary files /dev/null and b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_multi_srs_gen.srr.db differ

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr
new file mode 100644 (file)
index 0000000..f8ac3ec
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr
@@ -0,0 +1,86 @@
+# Fri May 10 11:58:57 2019
+
+Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.fdc
+@L: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt 
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt" file 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)
+
+@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances.
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist sgmii_ecp5
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+
+Clock Summary
+******************
+
+          Start                                 Requested     Requested     Clock        Clock                   Clock
+Level     Clock                                 Frequency     Period        Type         Group                   Load 
+----------------------------------------------------------------------------------------------------------------------
+0 -       System                                100.0 MHz     10.000        system       system_clkgroup         0    
+                                                                                                                      
+0 -       sgmii_ecp5|pll_refclki                100.0 MHz     10.000        inferred     Inferred_clkgroup_0     93   
+                                                                                                                      
+0 -       sgmii_ecp5|rxrefclk                   100.0 MHz     10.000        inferred     Inferred_clkgroup_1     77   
+                                                                                                                      
+0 -       sgmii_ecp5|tx_pclk_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_2     53   
+======================================================================================================================
+
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1988:0:1988:5|Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   10 -> 10
+   11 -> 11
+@N: MO225 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 144MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Fri May 10 11:58:58 2019
+
+###########################################################]

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr.db b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr.db
new file mode 100644 (file)
index 0000000..150e92a
Binary files /dev/null and b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.srr.db differ

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.szr b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.szr
new file mode 100644 (file)
index 0000000..fcf9743
Binary files /dev/null and b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/sgmii_ecp5_premap.szr differ

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/syntax_constraint_check.rpt.rptmap b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/syntax_constraint_check.rpt.rptmap
new file mode 100644 (file)
index 0000000..fe7eb22
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synlog/syntax_constraint_check.rpt.rptmap
@@ -0,0 +1 @@
+./sgmii_ecp5_scck.rpt,syntax_constraint_check.rpt,Syntax Constraint Check Report

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/syntmp/closed.png b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/syntmp/closed.png
new file mode 100644 (file)
index 0000000..0d78634
Binary files /dev/null and b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/syntmp/closed.png differ

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/syntmp/open.png b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/syntmp/open.png
new file mode 100644 (file)
index 0000000..a227005
Binary files /dev/null and b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/syntmp/open.png differ

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/syntmp/run_option.xml b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/syntmp/run_option.xml
new file mode 100644 (file)
index 0000000..4c321a3
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/syntmp/run_option.xml
@@ -0,0 +1,24 @@
+<?xml version="1.0" encoding="utf-8"?> 
+<!-- 
+  Synopsys, Inc.
+  Version M-2017.03L-SP1-1
+  Project file /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/syntmp/run_option.xml
+  Written on Fri May 10 11:58:54 2019
+
+
+--> 
+<project_attribute_list name="Project Settings"> 
+     <option name="project_name" display_name="Project Name">sgmii_ecp5</option>
+     <option name="device_name" display_name="Device Name">syn_results: Lattice ECP5UM : LFE5UM_25F</option>
+     <option name="impl_name" display_name="Implementation Name">syn_results</option>
+     <option name="top_module" display_name="Top Module">sgmii_ecp5</option>
+     <option name="pipe" display_name="Pipelining">0</option>
+     <option name="retiming" display_name="Retiming">0</option>
+     <option name="resource_sharing" display_name="Resource Sharing">1</option>
+     <option name="maxfan" display_name="Fanout Guide">50</option>
+     <option name="disable_io_insertion" display_name="Disable I/O Insertion">1</option>
+     <option name="no_sequential_opt" display_name="Disable Sequential Optimizations">0</option>
+     <option name="fix_gated_and_generated_clocks" display_name="Clock Conversion">1</option>
+     <option name="symbolic_fsm_compiler" display_name="FSM Compiler">1</option>
+</project_attribute_list>
+

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5.plg b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5.plg
new file mode 100644 (file)
index 0000000..384936b
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5.plg
@@ -0,0 +1,28 @@
+@P:  Worst Slack : 4.079
+@P:  sgmii_ecp5|pll_refclki - Estimated Frequency : 168.9 MHz
+@P:  sgmii_ecp5|pll_refclki - Requested Frequency : 100.0 MHz
+@P:  sgmii_ecp5|pll_refclki - Estimated Period : 5.921
+@P:  sgmii_ecp5|pll_refclki - Requested Period : 10.000
+@P:  sgmii_ecp5|pll_refclki - Slack : 4.079
+@P:  sgmii_ecp5|rxrefclk - Estimated Frequency : 170.5 MHz
+@P:  sgmii_ecp5|rxrefclk - Requested Frequency : 100.0 MHz
+@P:  sgmii_ecp5|rxrefclk - Estimated Period : 5.864
+@P:  sgmii_ecp5|rxrefclk - Requested Period : 10.000
+@P:  sgmii_ecp5|rxrefclk - Slack : 4.136
+@P:  sgmii_ecp5|tx_pclk_inferred_clock - Estimated Frequency : 237.5 MHz
+@P:  sgmii_ecp5|tx_pclk_inferred_clock - Requested Frequency : 100.0 MHz
+@P:  sgmii_ecp5|tx_pclk_inferred_clock - Estimated Period : 4.211
+@P:  sgmii_ecp5|tx_pclk_inferred_clock - Requested Period : 10.000
+@P:  sgmii_ecp5|tx_pclk_inferred_clock - Slack : 5.789
+@P:  System - Estimated Frequency : 840.7 MHz
+@P:  System - Requested Frequency : 100.0 MHz
+@P:  System - Estimated Period : 1.190
+@P:  System - Requested Period : 10.000
+@P:  System - Slack : 8.810
+@P:  Total Area : 156.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  CPU Time : 0h:00m:03s

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm
new file mode 100644 (file)
index 0000000..e9ac698
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm
@@ -0,0 +1,1172 @@
+<html><body><samp><pre>
+<!@TC:1557482334>
+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
+#install: /home/soft/lattice/diamond/3.10_x64/synpbase
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Fri May 10 11:58:54 2019
+
+#Implementation: syn_results
+
+<a name=compilerReport1></a>Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1557482336> | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+<a name=compilerReport2></a>Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1557482336> | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1557482336> | Setting time resolution to ps
+@N: : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd:30:7:30:17:@N::@XP_MSG">sgmii_ecp5.vhd(30)</a><!@TM:1557482336> | Top entity is set to sgmii_ecp5.
+VHDL syntax check successful!
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Fri May 10 11:58:55 2019
+
+###########################################################]
+<a name=compilerReport3></a>Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1557482336> | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
+Verilog syntax check successful!
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Fri May 10 11:58:55 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1557482336> | Setting time resolution to ps
+@N: : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd:30:7:30:17:@N::@XP_MSG">sgmii_ecp5.vhd(30)</a><!@TM:1557482336> | Top entity is set to sgmii_ecp5.
+VHDL syntax check successful!
+@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd:30:7:30:17:@N:CD630:@XP_MSG">sgmii_ecp5.vhd(30)</a><!@TM:1557482336> | Synthesizing work.sgmii_ecp5.v1.
+Post processing for work.sgmii_ecp5.v1
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB)
+
+
+Process completed successfully.
+# Fri May 10 11:58:55 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v" (library work)
+Verilog syntax check successful!
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1968:7:1968:11:@N:CG364:@XP_MSG">sgmii_ecp5_softlogic.v(1968)</a><!@TM:1557482336> | Synthesizing module sync in library work.
+
+       PDATA_RST_VAL=32'b00000000000000000000000000000000
+   Generated name = sync_0s
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1051:7:1051:25:@N:CG364:@XP_MSG">sgmii_ecp5_softlogic.v(1051)</a><!@TM:1557482336> | Synthesizing module sgmii_ecp5sll_core in library work.
+
+       PPROTOCOL=24'b010001110100001001000101
+       PLOL_SETTING=32'b00000000000000000000000000000000
+       PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100
+       PPCIE_MAX_RATE=24'b001100100010111000110101
+       PDIFF_VAL_LOCK=32'b00000000000000000000000000010011
+       PDIFF_VAL_UNLOCK=32'b00000000000000000000000000100111
+       PPCLK_TC=32'b00000000000000010000000000000000
+       PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000
+       PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000
+       PPCLK_DIV11_TC=32'b00000000000000000000000000000000
+       LPLL_LOSS_ST=2'b00
+       LPLL_PRELOSS_ST=2'b01
+       LPLL_PRELOCK_ST=2'b10
+       LPLL_LOCK_ST=2'b11
+       LRCLK_TC=16'b1111111111111111
+       LRCLK_TC_PUL_WIDTH=16'b0000000000110010
+       LHB_WAIT_CNT=8'b11111111
+       LPCLK_TC_0=32'b00000000000000001000000000000000
+       LPCLK_TC_1=32'b00000000000000010000000000000000
+       LPCLK_TC_2=32'b00000000000000100000000000000000
+       LPCLK_TC_3=32'b00000000000000101000000000000000
+       LPCLK_TC_4=32'b00000000000000010000000000000000
+       LPDIFF_LOCK_00=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_10=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_20=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_30=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_40=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_01=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_11=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_21=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_31=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_41=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_02=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_12=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_22=32'b00000000000000000000000011000100
+       LPDIFF_LOCK_32=32'b00000000000000000000000011110101
+       LPDIFF_LOCK_42=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_03=32'b00000000000000000000000010000011
+       LPDIFF_LOCK_13=32'b00000000000000000000000100000110
+       LPDIFF_LOCK_23=32'b00000000000000000000001000001100
+       LPDIFF_LOCK_33=32'b00000000000000000000001010001111
+       LPDIFF_LOCK_43=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011
+       LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110
+       LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010
+       LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001
+       LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111
+       LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000
+       LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000
+       LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000
+       LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100
+       LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001
+       LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010
+       LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111
+       LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001
+   Generated name = sgmii_ecp5sll_core_Z1_layer1
+@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1287:54:1287:60:@N:CG179:@XP_MSG">sgmii_ecp5_softlogic.v(1287)</a><!@TM:1557482336> | Removing redundant assignment.
+@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1293:52:1293:56:@N:CG179:@XP_MSG">sgmii_ecp5_softlogic.v(1293)</a><!@TM:1557482336> | Removing redundant assignment.
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1350:0:1350:6:@W:CL169:@XP_MSG">sgmii_ecp5_softlogic.v(1350)</a><!@TM:1557482336> | Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 3 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 6 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 2 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 5 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 17 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:92:7:92:25:@N:CG364:@XP_MSG">sgmii_ecp5_softlogic.v(92)</a><!@TM:1557482336> | Synthesizing module sgmii_ecp5rsl_core in library work.
+
+       pnum_channels=32'b00000000000000000000000000000001
+       pprotocol=24'b010001110100001001000101
+       pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
+       pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_tx_rdy=32'b00000000000000000000101110111000
+       pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_rx_rdy=32'b00000000000000000000101110111000
+       wa_num_cycles=32'b00000000000000000000010000000000
+       dac_num_cycles=32'b00000000000000000000000000000011
+       lreset_pwidth=32'b00000000000000000000000000000011
+       lwait_b4_trst=32'b00000000000010111110101111000010
+       lwait_b4_trst_s=32'b00000000000000000000001100001101
+       lplol_cnt_width=32'b00000000000000000000000000010100
+       lwait_after_plol0=32'b00000000000000000000000000000100
+       lwait_b4_rrst=32'b00000000000000101100000000000000
+       lrrst_wait_width=32'b00000000000000000000000000010100
+       lwait_after_rrst=32'b00000000000011000011010100000000
+       lwait_b4_rrst_s=32'b00000000000000000000000111001100
+       lrlol_cnt_width=32'b00000000000000000000000000010011
+       lwait_after_lols=32'b00000000000000001100010000000000
+       lwait_after_lols_s=32'b00000000000000000000000010010110
+       llols_cnt_width=32'b00000000000000000000000000010010
+       lrdb_max=32'b00000000000000000000000000001111
+       ltxr_wait_width=32'b00000000000000000000000000001100
+       lrxr_wait_width=32'b00000000000000000000000000001100
+   Generated name = sgmii_ecp5rsl_core_Z2_layer1
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:326:33:326:41:@W:CG133:@XP_MSG">sgmii_ecp5_softlogic.v(326)</a><!@TM:1557482336> | Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:327:33:327:44:@W:CG360:@XP_MSG">sgmii_ecp5_softlogic.v(327)</a><!@TM:1557482336> | Removing wire rrst_cnt_tc, as there is no assignment to it.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:328:33:328:42:@W:CG133:@XP_MSG">sgmii_ecp5_softlogic.v(328)</a><!@TM:1557482336> | Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:341:33:341:40:@W:CG133:@XP_MSG">sgmii_ecp5_softlogic.v(341)</a><!@TM:1557482336> | Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:342:33:342:40:@W:CG133:@XP_MSG">sgmii_ecp5_softlogic.v(342)</a><!@TM:1557482336> | Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:343:33:343:43:@W:CG360:@XP_MSG">sgmii_ecp5_softlogic.v(343)</a><!@TM:1557482336> | Removing wire rxp_cnt_tc, as there is no assignment to it.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:346:33:346:43:@W:CG133:@XP_MSG">sgmii_ecp5_softlogic.v(346)</a><!@TM:1557482336> | Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:347:33:347:46:@W:CG360:@XP_MSG">sgmii_ecp5_softlogic.v(347)</a><!@TM:1557482336> | Removing wire rlolsz_cnt_tc, as there is no assignment to it.</font>
+<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:350:33:350:44:@W:CG360:@XP_MSG">sgmii_ecp5_softlogic.v(350)</a><!@TM:1557482336> | Removing wire rxp_cnt2_tc, as there is no assignment to it.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:351:33:351:48:@W:CG133:@XP_MSG">sgmii_ecp5_softlogic.v(351)</a><!@TM:1557482336> | Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:352:33:352:44:@W:CG133:@XP_MSG">sgmii_ecp5_softlogic.v(352)</a><!@TM:1557482336> | Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:353:33:353:47:@W:CG360:@XP_MSG">sgmii_ecp5_softlogic.v(353)</a><!@TM:1557482336> | Removing wire data_loop_b_tc, as there is no assignment to it.</font>
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:806:3:806:9:@W:CL169:@XP_MSG">sgmii_ecp5_softlogic.v(806)</a><!@TM:1557482336> | Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.</font>
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:567:3:567:9:@W:CL169:@XP_MSG">sgmii_ecp5_softlogic.v(567)</a><!@TM:1557482336> | Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.</font>
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:567:3:567:9:@W:CL169:@XP_MSG">sgmii_ecp5_softlogic.v(567)</a><!@TM:1557482336> | Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.</font>
+<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:694:3:694:9:@W:CL190:@XP_MSG">sgmii_ecp5_softlogic.v(694)</a><!@TM:1557482336> | Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
+<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:461:3:461:9:@W:CL190:@XP_MSG">sgmii_ecp5_softlogic.v(461)</a><!@TM:1557482336> | Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
+<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:422:3:422:9:@W:CL190:@XP_MSG">sgmii_ecp5_softlogic.v(422)</a><!@TM:1557482336> | Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
+<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:422:3:422:9:@W:CL260:@XP_MSG">sgmii_ecp5_softlogic.v(422)</a><!@TM:1557482336> | Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
+<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:461:3:461:9:@W:CL260:@XP_MSG">sgmii_ecp5_softlogic.v(461)</a><!@TM:1557482336> | Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
+<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:694:3:694:9:@W:CL260:@XP_MSG">sgmii_ecp5_softlogic.v(694)</a><!@TM:1557482336> | Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
+<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:200:33:200:49:@W:CL246:@XP_MSG">sgmii_ecp5_softlogic.v(200)</a><!@TM:1557482336> | Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.</font>
+<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:204:33:204:52:@W:CL246:@XP_MSG">sgmii_ecp5_softlogic.v(204)</a><!@TM:1557482336> | Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.</font>
+<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:205:33:205:49:@W:CL246:@XP_MSG">sgmii_ecp5_softlogic.v(205)</a><!@TM:1557482336> | Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.</font>
+<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:206:33:206:49:@W:CL246:@XP_MSG">sgmii_ecp5_softlogic.v(206)</a><!@TM:1557482336> | Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.</font>
+<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:207:33:207:49:@W:CL246:@XP_MSG">sgmii_ecp5_softlogic.v(207)</a><!@TM:1557482336> | Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.</font>
+<font color=#A52A2A>@W:<a href="@W:CL279:@XP_HELP">CL279</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL279:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | Pruning register bits 5 to 3 of genblk5.rdiff_comp_unlock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.</font>
+<font color=#A52A2A>@W:<a href="@W:CL279:@XP_HELP">CL279</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL279:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | Pruning register bits 4 to 3 of genblk5.rdiff_comp_lock[4:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.</font>
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL169:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | Pruning unused register genblk5.rdiff_comp_unlock[2]. Make sure that there are no unused intermediate registers.</font>
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1739:0:1739:6:@W:CL169:@XP_MSG">sgmii_ecp5_softlogic.v(1739)</a><!@TM:1557482336> | Pruning unused register genblk5.rcount_tc[16]. Make sure that there are no unused intermediate registers.</font>
+@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1801:0:1801:6:@N:CL201:@XP_MSG">sgmii_ecp5_softlogic.v(1801)</a><!@TM:1557482336> | Trying to extract state machine for register sll_state.
+Extracted state machine for register sll_state
+State machine has 4 reachable states with original encodings of:
+   00
+   01
+   10
+   11
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB)
+
+
+Process completed successfully.
+# Fri May 10 11:58:56 2019
+
+###########################################################]
+<a name=compilerReport4></a>Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1557482336> | Running in 64-bit mode 
+
+=======================================================================================
+For a summary of linker messages for components that did not bind, please see log file:
+Linked File: <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.linkerlog:@XP_FILE">sgmii_ecp5_comp.linkerlog</a>
+=======================================================================================
+
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 11:58:56 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 11:58:56 2019
+
+###########################################################]
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1557482334>
+<a name=compilerReport5></a>Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1557482337> | Running in 64-bit mode 
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 11:58:57 2019
+
+###########################################################]
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1557482334>
+Pre-mapping Report
+
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1557482334>
+# Fri May 10 11:58:57 2019
+
+<a name=mapperReport6></a>Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35</a>
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.fdc
+Linked File: <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt:@XP_FILE">sgmii_ecp5_scck.rpt</a>
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_scck.rpt" file 
+@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1557482338> | Running in 64-bit mode. 
+@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1557482338> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)
+
+@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1408:0:1408:6:@N:BN362:@XP_MSG">sgmii_ecp5_softlogic.v(1408)</a><!@TM:1557482338> | Removing sequential instance pcpri_mod_ch (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
+@N:<a href="@N:BN115:@XP_HELP">BN115</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1244:27:1244:41:@N:BN115:@XP_MSG">sgmii_ecp5_softlogic.v(1244)</a><!@TM:1557482338> | Removing instance div2_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances.
+@N:<a href="@N:BN115:@XP_HELP">BN115</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1252:27:1252:42:@N:BN115:@XP_MSG">sgmii_ecp5_softlogic.v(1252)</a><!@TM:1557482338> | Removing instance div11_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances.
+@N:<a href="@N:BN115:@XP_HELP">BN115</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1236:27:1236:41:@N:BN115:@XP_MSG">sgmii_ecp5_softlogic.v(1236)</a><!@TM:1557482338> | Removing instance gear_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances.
+@N:<a href="@N:BN115:@XP_HELP">BN115</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1268:27:1268:45:@N:BN115:@XP_MSG">sgmii_ecp5_softlogic.v(1268)</a><!@TM:1557482338> | Removing instance pcie_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances.
+@N:<a href="@N:BN115:@XP_HELP">BN115</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1260:27:1260:45:@N:BN115:@XP_MSG">sgmii_ecp5_softlogic.v(1260)</a><!@TM:1557482338> | Removing instance cpri_mod_sync_inst (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances.
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist sgmii_ecp5
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+
+<a name=mapperReport7></a>Clock Summary</a>
+******************
+
+          Start                                 Requested     Requested     Clock        Clock                   Clock
+Level     Clock                                 Frequency     Period        Type         Group                   Load 
+----------------------------------------------------------------------------------------------------------------------
+0 -       System                                100.0 MHz     10.000        system       system_clkgroup         0    
+                                                                                                                      
+0 -       sgmii_ecp5|pll_refclki                100.0 MHz     10.000        inferred     Inferred_clkgroup_0     93   
+                                                                                                                      
+0 -       sgmii_ecp5|rxrefclk                   100.0 MHz     10.000        inferred     Inferred_clkgroup_1     77   
+                                                                                                                      
+0 -       sgmii_ecp5|tx_pclk_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_2     53   
+======================================================================================================================
+
+<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1988:0:1988:6:@W:MT529:@XP_MSG">sgmii_ecp5_softlogic.v(1988)</a><!@TM:1557482338> | Found inferred clock sgmii_ecp5|pll_refclki which controls 93 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
+<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:567:3:567:9:@W:MT529:@XP_MSG">sgmii_ecp5_softlogic.v(567)</a><!@TM:1557482338> | Found inferred clock sgmii_ecp5|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
+<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1988:0:1988:6:@W:MT529:@XP_MSG">sgmii_ecp5_softlogic.v(1988)</a><!@TM:1557482338> | Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   10 -> 10
+   11 -> 11
+@N:<a href="@N:MO225:@XP_HELP">MO225</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1801:0:1801:6:@N:MO225:@XP_MSG">sgmii_ecp5_softlogic.v(1801)</a><!@TM:1557482338> | There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 144MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Fri May 10 11:58:58 2019
+
+###########################################################]
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1557482334>
+Map & Optimize Report
+
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1557482334>
+# Fri May 10 11:58:58 2019
+
+<a name=mapperReport8></a>Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35</a>
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
+
+@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1557482342> | Running in 64-bit mode. 
+@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1557482342> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   10 -> 10
+   11 -> 11
+@N:<a href="@N:MO225:@XP_HELP">MO225</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1801:0:1801:6:@N:MO225:@XP_MSG">sgmii_ecp5_softlogic.v(1801)</a><!@TM:1557482342> | There are no possible illegal states for state machine sll_state[3:0] (in view: work.sgmii_ecp5sll_core_Z1_layer1(verilog)); safe FSM implementation is not required.
+@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1350:0:1350:6:@N:MO231:@XP_MSG">sgmii_ecp5_softlogic.v(1350)</a><!@TM:1557482342> | Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] 
+@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1304:0:1304:6:@N:MO231:@XP_MSG">sgmii_ecp5_softlogic.v(1304)</a><!@TM:1557482342> | Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance rcount[15:0] 
+@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1759:0:1759:6:@N:MO231:@XP_MSG">sgmii_ecp5_softlogic.v(1759)</a><!@TM:1557482342> | Found counter in view:work.sgmii_ecp5sll_core_Z1_layer1(verilog) instance pcount[21:0] 
+@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:412:3:412:9:@N:MO231:@XP_MSG">sgmii_ecp5_softlogic.v(412)</a><!@TM:1557482342> | Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] 
+@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:909:3:909:9:@N:MO231:@XP_MSG">sgmii_ecp5_softlogic.v(909)</a><!@TM:1557482342> | Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] 
+@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:527:3:527:9:@N:MO231:@XP_MSG">sgmii_ecp5_softlogic.v(527)</a><!@TM:1557482342> | Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] 
+@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:778:3:778:9:@N:MO231:@XP_MSG">sgmii_ecp5_softlogic.v(778)</a><!@TM:1557482342> | Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] 
+@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:680:3:680:9:@N:MO231:@XP_MSG">sgmii_ecp5_softlogic.v(680)</a><!@TM:1557482342> | Found counter in view:work.sgmii_ecp5rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] 
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 145MB)
+
+@N:<a href="@N:FX1019:@XP_HELP">FX1019</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1988:0:1988:6:@N:FX1019:@XP_MSG">sgmii_ecp5_softlogic.v(1988)</a><!@TM:1557482342> | Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N:<a href="@N:FX1019:@XP_HELP">FX1019</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1988:0:1988:6:@N:FX1019:@XP_MSG">sgmii_ecp5_softlogic.v(1988)</a><!@TM:1557482342> | Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N:<a href="@N:FX1019:@XP_HELP">FX1019</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1988:0:1988:6:@N:FX1019:@XP_MSG">sgmii_ecp5_softlogic.v(1988)</a><!@TM:1557482342> | Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+   1           0h:00m:01s                   5.36ns              154 /       221
+@N:<a href="@N:FX1019:@XP_HELP">FX1019</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1988:0:1988:6:@N:FX1019:@XP_MSG">sgmii_ecp5_softlogic.v(1988)</a><!@TM:1557482342> | Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N:<a href="@N:FX1019:@XP_HELP">FX1019</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1988:0:1988:6:@N:FX1019:@XP_MSG">sgmii_ecp5_softlogic.v(1988)</a><!@TM:1557482342> | Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+@N:<a href="@N:FX1019:@XP_HELP">FX1019</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v:1988:0:1988:6:@N:FX1019:@XP_MSG">sgmii_ecp5_softlogic.v(1988)</a><!@TM:1557482342> | Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.sgmii_ecp5(v1)).
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB)
+
+@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1557482342> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 148MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+<a name=clockReport9></a>#### START OF CLOCK OPTIMIZATION REPORT #####[</a>
+
+3 non-gated/non-generated clock tree(s) driving 221 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+============================================= Non-Gated/Non-Generated Clocks =============================================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                                   
+--------------------------------------------------------------------------------------------------------------------------
+<a href="@|S:pll_refclki@|E:rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001  @XP_NAMES_BY_PROP">ClockId0001 </a>       pll_refclki         port                   91         rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]
+<a href="@|S:rxrefclk@|E:rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]@|F:@syn_sample_clock_path==CKID0002@|M:ClockId0002  @XP_NAMES_BY_PROP">ClockId0002 </a>       rxrefclk            port                   77         rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]
+<a href="@|S:DCU0_inst@|E:sll_inst.pcount[21]@|F:@syn_sample_clock_path==CKID0003@|M:ClockId0003  @XP_NAMES_BY_PROP">ClockId0003 </a>       DCU0_inst           DCUA                   53         sll_inst.pcount[21]                               
+==========================================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 148MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 148MB)
+
+Writing EDIF Netlist and constraint files
+@N:<a href="@N:FX1056:@XP_HELP">FX1056</a> : <!@TM:1557482342> | Writing EDF file: /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.edn 
+M-2017.03L-SP1-1
+@N:<a href="@N:BW106:@XP_HELP">BW106</a> : <!@TM:1557482342> | Synplicity Constraint File capacitance units using default value of 1pF  
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 153MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 151MB peak: 153MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+<font color=#A52A2A>@W:<a href="@W:MT246:@XP_HELP">MT246</a> : <a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd:162:4:162:13:@W:MT246:@XP_MSG">sgmii_ecp5.vhd(162)</a><!@TM:1557482342> | Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) </font>
+<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1557482342> | Found inferred clock sgmii_ecp5|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"</font> 
+<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1557482342> | Found inferred clock sgmii_ecp5|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"</font> 
+<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1557482342> | Found inferred clock sgmii_ecp5|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk"</font> 
+
+
+<a name=timingReport10></a>##### START OF TIMING REPORT #####[</a>
+# Timing Report written on Fri May 10 11:59:02 2019
+#
+
+
+Top view:               sgmii_ecp5
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.fdc
+                       
+@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1557482342> | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 
+
+@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1557482342> | Clock constraints include only register-to-register paths associated with each individual clock. 
+
+
+
+<a name=performanceSummary11></a>Performance Summary</a>
+*******************
+
+
+Worst slack in design: 4.079
+
+                                      Requested     Estimated     Requested     Estimated               Clock        Clock              
+Starting Clock                        Frequency     Frequency     Period        Period        Slack     Type         Group              
+----------------------------------------------------------------------------------------------------------------------------------------
+sgmii_ecp5|pll_refclki                100.0 MHz     168.9 MHz     10.000        5.921         4.079     inferred     Inferred_clkgroup_0
+sgmii_ecp5|rxrefclk                   100.0 MHz     170.5 MHz     10.000        5.864         4.136     inferred     Inferred_clkgroup_1
+sgmii_ecp5|tx_pclk_inferred_clock     100.0 MHz     237.5 MHz     10.000        4.211         5.789     inferred     Inferred_clkgroup_2
+System                                100.0 MHz     840.7 MHz     10.000        1.190         8.810     system       system_clkgroup    
+========================================================================================================================================
+
+
+
+
+
+<a name=clockRelationships12></a>Clock Relationships</a>
+*******************
+
+Clocks                                                                |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+Starting                           Ending                             |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+System                             sgmii_ecp5|rxrefclk                |  10.000      8.811  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             System                             |  10.000      8.253  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             sgmii_ecp5|pll_refclki             |  10.000      4.079  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|pll_refclki             sgmii_ecp5|tx_pclk_inferred_clock  |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|rxrefclk                System                             |  10.000      8.184  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|rxrefclk                sgmii_ecp5|rxrefclk                |  10.000      4.136  |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|tx_pclk_inferred_clock  sgmii_ecp5|pll_refclki             |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
+sgmii_ecp5|tx_pclk_inferred_clock  sgmii_ecp5|tx_pclk_inferred_clock  |  10.000      5.789  |  No paths    -      |  No paths    -      |  No paths    -    
+============================================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+<a name=interfaceInfo13></a>Interface Information </a>
+*********************
+
+No IO constraint found
+
+
+
+====================================
+<a name=clockReport14></a>Detailed Report for Clock: sgmii_ecp5|pll_refclki</a>
+====================================
+
+
+
+<a name=startingSlack15></a>Starting Points with Worst Slack</a>
+********************************
+
+                                   Starting                                                        Arrival          
+Instance                           Reference                  Type        Pin     Net              Time        Slack
+                                   Clock                                                                            
+--------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[2]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[2]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[3]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[3]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[17]     sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[17]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[19]     sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[19]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[1]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[1]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[4]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[4]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[5]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[5]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[6]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[6]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[7]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[7]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[8]      sgmii_ecp5|pll_refclki     FD1S3DX     Q       plol_cnt[8]      0.907       4.684
+====================================================================================================================
+
+
+<a name=endingSlack16></a>Ending Points with Worst Slack</a>
+******************************
+
+                                   Starting                                                          Required          
+Instance                           Reference                  Type        Pin     Net                Time         Slack
+                                   Clock                                                                               
+-----------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[19]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[19]     9.946        4.079
+rsl_inst.genblk1\.plol_cnt[17]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[17]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[18]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[18]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[15]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[15]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[16]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[16]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[13]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[13]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[14]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[14]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[11]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[11]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[12]     sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[12]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[9]      sgmii_ecp5|pll_refclki     FD1S3DX     D       plol_cnt_s[9]      9.946        4.383
+=======================================================================================================================
+
+
+
+<a name=worstPaths17></a>Worst Path Information</a>
+<a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srr:srsf/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srs:fp:61166:66158:@XP_NAMES_GATE">View Worst Path in Analyst</a>
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.867
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     4.079
+
+    Number of logic level(s):                15
+    Starting point:                          rsl_inst.genblk1\.plol_cnt[2] / Q
+    Ending point:                            rsl_inst.genblk1\.plol_cnt[19] / D
+    The start point is clocked by            sgmii_ecp5|pll_refclki [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|pll_refclki [rising] on pin CK
+
+Instance / Net                                        Pin      Pin               Arrival     No. of    
+Name                                     Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[2]            FD1S3DX      Q        Out     0.907     0.907       -         
+plol_cnt[2]                              Net          -        -       -         -           2         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     Z        Out     0.606     1.513       -         
+un1_plol_cnt_tc_10                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     Z        Out     0.606     2.119       -         
+un1_plol_cnt_tc_14                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     Z        Out     0.762     2.881       -         
+un1_plol_cnt_tc                          Net          -        -       -         -           5         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     B        In      0.000     2.881       -         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     Z        Out     0.840     3.721       -         
+plol_cnt                                 Net          -        -       -         -           21        
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.721       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.621       -         
+plol_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.621       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.682       -         
+plol_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.682       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.743       -         
+plol_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.743       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.804       -         
+plol_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.804       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.865       -         
+plol_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.865       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.926       -         
+plol_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.926       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.987       -         
+plol_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.987       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.048       -         
+plol_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.048       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.109       -         
+plol_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.109       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        COUT     Out     0.061     5.170       -         
+plol_cnt_cry[18]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        CIN      In      0.000     5.170       -         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        S0       Out     0.698     5.867       -         
+plol_cnt_s[19]                           Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt[19]           FD1S3DX      D        In      0.000     5.867       -         
+=======================================================================================================
+
+
+
+
+====================================
+<a name=clockReport18></a>Detailed Report for Clock: sgmii_ecp5|rxrefclk</a>
+====================================
+
+
+
+<a name=startingSlack19></a>Starting Points with Worst Slack</a>
+********************************
+
+                                    Starting                                                      Arrival          
+Instance                            Reference               Type        Pin     Net               Time        Slack
+                                    Clock                                                                          
+-------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[7]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[7]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[8]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[8]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[9]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[9]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[10]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[10]     0.907       4.136
+rsl_inst.genblk2\.rlols0_cnt[1]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[1]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[2]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[2]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[3]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[3]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[4]     sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlols0_cnt[4]     0.907       4.170
+rsl_inst.genblk2\.rxs_rst           sgmii_ecp5|rxrefclk     FD1P3DX     Q       rxs_rst           1.015       4.700
+rsl_inst.genblk2\.rlol1_cnt[0]      sgmii_ecp5|rxrefclk     FD1P3DX     Q       rlol1_cnt[0]      0.907       4.742
+===================================================================================================================
+
+
+<a name=endingSlack20></a>Ending Points with Worst Slack</a>
+******************************
+
+                                     Starting                                                         Required          
+Instance                             Reference               Type        Pin     Net                  Time         Slack
+                                     Clock                                                                              
+------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[17]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[17]      9.946        4.136
+rsl_inst.genblk2\.rlol1_cnt[18]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[18]      9.946        4.136
+rsl_inst.genblk2\.rlols0_cnt[17]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rlols0_cnt_s[17]     9.946        4.170
+rsl_inst.genblk2\.rlol1_cnt[15]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[15]      9.946        4.197
+rsl_inst.genblk2\.rlol1_cnt[16]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[16]      9.946        4.197
+rsl_inst.genblk2\.rlols0_cnt[15]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rlols0_cnt_s[15]     9.946        4.231
+rsl_inst.genblk2\.rlols0_cnt[16]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rlols0_cnt_s[16]     9.946        4.231
+rsl_inst.genblk2\.rlol1_cnt[13]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[13]      9.946        4.258
+rsl_inst.genblk2\.rlol1_cnt[14]      sgmii_ecp5|rxrefclk     FD1P3DX     D       rlol1_cnt_s[14]      9.946        4.258
+rsl_inst.genblk2\.rlols0_cnt[13]     sgmii_ecp5|rxrefclk     FD1P3DX     D       rlols0_cnt_s[13]     9.946        4.292
+========================================================================================================================
+
+
+
+<a name=worstPaths21></a>Worst Path Information</a>
+<a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srr:srsf/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srs:fp:71235:75960:@XP_NAMES_GATE">View Worst Path in Analyst</a>
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.809
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.136
+
+    Number of logic level(s):                14
+    Starting point:                          rsl_inst.genblk2\.rlol1_cnt[7] / Q
+    Ending point:                            rsl_inst.genblk2\.rlol1_cnt[18] / D
+    The start point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+
+Instance / Net                                         Pin      Pin               Arrival     No. of    
+Name                                      Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[7]            FD1P3DX      Q        Out     0.907     0.907       -         
+rlol1_cnt[7]                              Net          -        -       -         -           2         
+rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     Z        Out     0.606     1.513       -         
+rlol1_cnt_tc_1_10                         Net          -        -       -         -           1         
+rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     Z        Out     0.606     2.119       -         
+rlol1_cnt_tc_1_14                         Net          -        -       -         -           1         
+rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     Z        Out     0.768     2.887       -         
+rlol1_cnt_tc_1                            Net          -        -       -         -           6         
+rsl_inst.genblk2\.rlos_db_p1_RNIS0OP      ORCALUT4     A        In      0.000     2.887       -         
+rsl_inst.genblk2\.rlos_db_p1_RNIS0OP      ORCALUT4     Z        Out     0.837     3.724       -         
+rlol1_cnt                                 Net          -        -       -         -           20        
+rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.724       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.624       -         
+rlol1_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.624       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.685       -         
+rlol1_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.685       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.746       -         
+rlol1_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.746       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.807       -         
+rlol1_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.807       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.868       -         
+rlol1_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.868       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.929       -         
+rlol1_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.929       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.990       -         
+rlol1_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.990       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.051       -         
+rlol1_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.051       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.112       -         
+rlol1_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.112       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        S1       Out     0.698     5.809       -         
+rlol1_cnt_s[18]                           Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt[18]           FD1P3DX      D        In      0.000     5.809       -         
+========================================================================================================
+
+
+
+
+====================================
+<a name=clockReport22></a>Detailed Report for Clock: sgmii_ecp5|tx_pclk_inferred_clock</a>
+====================================
+
+
+
+<a name=startingSlack23></a>Starting Points with Worst Slack</a>
+********************************
+
+                            Starting                                                                   Arrival          
+Instance                    Reference                             Type        Pin     Net              Time        Slack
+                            Clock                                                                                       
+------------------------------------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1       sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p1     1.098       5.789
+sll_inst.ppul_sync_p2       sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p2     1.098       5.789
+sll_inst.pcount_diff[0]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_0      0.985       6.147
+sll_inst.pcount[0]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[0]        0.955       6.178
+sll_inst.pcount_diff[1]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_1      0.955       6.239
+sll_inst.pcount_diff[2]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_2      0.955       6.239
+sll_inst.pcount[1]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[1]        0.907       6.287
+sll_inst.pcount[2]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[2]        0.907       6.287
+sll_inst.pcount_diff[3]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_3      0.955       6.300
+sll_inst.pcount_diff[4]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_4      0.955       6.300
+========================================================================================================================
+
+
+<a name=endingSlack24></a>Ending Points with Worst Slack</a>
+******************************
+
+                             Starting                                                                                  Required          
+Instance                     Reference                             Type        Pin     Net                             Time         Slack
+                             Clock                                                                                                       
+-----------------------------------------------------------------------------------------------------------------------------------------
+sll_inst.pcount[21]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[21]                    9.946        5.789
+sll_inst.pcount[19]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[19]                    9.946        5.850
+sll_inst.pcount[20]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[20]                    9.946        5.850
+sll_inst.pcount[17]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[17]                    9.946        5.911
+sll_inst.pcount[18]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[18]                    9.946        5.911
+sll_inst.pcount[15]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[15]                    9.946        5.972
+sll_inst.pcount[16]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[16]                    9.946        5.972
+sll_inst.pcount[13]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[13]                    9.946        6.033
+sll_inst.pcount[14]          sgmii_ecp5|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[14]                    9.946        6.033
+sll_inst.pcount_diff[21]     sgmii_ecp5|tx_pclk_inferred_clock     FD1P3DX     D       un1_pcount_diff_1_s_21_0_S0     9.946        6.034
+=========================================================================================================================================
+
+
+
+<a name=worstPaths25></a>Worst Path Information</a>
+<a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srr:srsf/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srs:fp:81353:85259:@XP_NAMES_GATE">View Worst Path in Analyst</a>
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      4.157
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 5.789
+
+    Number of logic level(s):                13
+    Starting point:                          sll_inst.ppul_sync_p1 / Q
+    Ending point:                            sll_inst.pcount[21] / D
+    The start point is clocked by            sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
+    The end   point is clocked by            sgmii_ecp5|tx_pclk_inferred_clock [rising] on pin CK
+
+Instance / Net                             Pin      Pin               Arrival     No. of    
+Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1         FD1S3DX      Q        Out     1.098     1.098       -         
+ppul_sync_p1                  Net          -        -       -         -           25        
+sll_inst.pcount10_0_o3        ORCALUT4     A        In      0.000     1.098       -         
+sll_inst.pcount10_0_o3        ORCALUT4     Z        Out     0.851     1.950       -         
+N_8                           Net          -        -       -         -           25        
+sll_inst.pcount_cry_0[0]      CCU2C        A1       In      0.000     1.950       -         
+sll_inst.pcount_cry_0[0]      CCU2C        COUT     Out     0.900     2.850       -         
+pcount_cry[0]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[1]      CCU2C        CIN      In      0.000     2.850       -         
+sll_inst.pcount_cry_0[1]      CCU2C        COUT     Out     0.061     2.911       -         
+pcount_cry[2]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[3]      CCU2C        CIN      In      0.000     2.911       -         
+sll_inst.pcount_cry_0[3]      CCU2C        COUT     Out     0.061     2.972       -         
+pcount_cry[4]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[5]      CCU2C        CIN      In      0.000     2.972       -         
+sll_inst.pcount_cry_0[5]      CCU2C        COUT     Out     0.061     3.033       -         
+pcount_cry[6]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[7]      CCU2C        CIN      In      0.000     3.033       -         
+sll_inst.pcount_cry_0[7]      CCU2C        COUT     Out     0.061     3.094       -         
+pcount_cry[8]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[9]      CCU2C        CIN      In      0.000     3.094       -         
+sll_inst.pcount_cry_0[9]      CCU2C        COUT     Out     0.061     3.155       -         
+pcount_cry[10]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[11]     CCU2C        CIN      In      0.000     3.155       -         
+sll_inst.pcount_cry_0[11]     CCU2C        COUT     Out     0.061     3.216       -         
+pcount_cry[12]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[13]     CCU2C        CIN      In      0.000     3.216       -         
+sll_inst.pcount_cry_0[13]     CCU2C        COUT     Out     0.061     3.277       -         
+pcount_cry[14]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[15]     CCU2C        CIN      In      0.000     3.277       -         
+sll_inst.pcount_cry_0[15]     CCU2C        COUT     Out     0.061     3.338       -         
+pcount_cry[16]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[17]     CCU2C        CIN      In      0.000     3.338       -         
+sll_inst.pcount_cry_0[17]     CCU2C        COUT     Out     0.061     3.399       -         
+pcount_cry[18]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[19]     CCU2C        CIN      In      0.000     3.399       -         
+sll_inst.pcount_cry_0[19]     CCU2C        COUT     Out     0.061     3.460       -         
+pcount_cry[20]                Net          -        -       -         -           1         
+sll_inst.pcount_s_0[21]       CCU2C        CIN      In      0.000     3.460       -         
+sll_inst.pcount_s_0[21]       CCU2C        S0       Out     0.698     4.157       -         
+pcount_s[21]                  Net          -        -       -         -           1         
+sll_inst.pcount[21]           FD1S3DX      D        In      0.000     4.157       -         
+============================================================================================
+
+
+
+
+====================================
+<a name=clockReport26></a>Detailed Report for Clock: System</a>
+====================================
+
+
+
+<a name=startingSlack27></a>Starting Points with Worst Slack</a>
+********************************
+
+              Starting                                                 Arrival          
+Instance      Reference     Type     Pin              Net              Time        Slack
+              Clock                                                                     
+----------------------------------------------------------------------------------------
+DCU0_inst     System        DCUA     CH0_FFS_RLOL     rx_cdr_lol_s     0.000       8.810
+DCU0_inst     System        DCUA     CH0_FFS_RLOS     rx_los_low_s     0.000       8.810
+========================================================================================
+
+
+<a name=endingSlack28></a>Ending Points with Worst Slack</a>
+******************************
+
+                                                       Starting                                                            Required          
+Instance                                               Reference     Type        Pin     Net                               Time         Slack
+                                                       Clock                                                                                 
+---------------------------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     SP      un2_rdo_serdes_rst_dual_c_2_i     9.806        8.810
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     D       rxpr_appd_RNO[0]                  9.946        9.556
+rsl_inst.genblk2\.rlol_p1                              System        FD1S3DX     D       rx_cdr_lol_s                      9.946        9.946
+rsl_inst.genblk2\.rlos_p1                              System        FD1S3DX     D       rx_los_low_s                      9.946        9.946
+=============================================================================================================================================
+
+
+
+<a name=worstPaths29></a>Worst Path Information</a>
+<a href="/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srr:srsf/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5.srs:fp:88777:89965:@XP_NAMES_GATE">View Worst Path in Analyst</a>
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.194
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.806
+
+    - Propagation time:                      0.996
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 8.810
+
+    Number of logic level(s):                2
+    Starting point:                          DCU0_inst / CH0_FFS_RLOL
+    Ending point:                            rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            sgmii_ecp5|rxrefclk [rising] on pin CK
+
+Instance / Net                                                            Pin              Pin               Arrival     No. of    
+Name                                                         Type         Name             Dir     Delay     Time        Fan Out(s)
+-----------------------------------------------------------------------------------------------------------------------------------
+DCU0_inst                                                    DCUA         CH0_FFS_RLOL     Out     0.000     0.000       -         
+rx_cdr_lol_s                                                 Net          -                -       -         -           4         
+rsl_inst.un2_rdo_serdes_rst_dual_c_1_1                       ORCALUT4     A                In      0.000     0.000       -         
+rsl_inst.un2_rdo_serdes_rst_dual_c_1_1                       ORCALUT4     Z                Out     0.606     0.606       -         
+un2_rdo_serdes_rst_dual_c_1_1                                Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0]     ORCALUT4     B                In      0.000     0.606       -         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO_0[0]     ORCALUT4     Z                Out     0.390     0.996       -         
+un2_rdo_serdes_rst_dual_c_2_i                                Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]           FD1P3DX      SP               In      0.000     0.996       -         
+===================================================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 151MB peak: 153MB)
+
+---------------------------------------
+<a name=resourceUsage30></a>Resource Usage Report</a>
+Part: lfe5um_25f-6
+
+Register bits: 221 of 24288 (1%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+CCU2C:          113
+DCUA:           1
+FD1P3BX:        20
+FD1P3DX:        92
+FD1S3BX:        12
+FD1S3DX:        97
+GSR:            1
+INV:            3
+ORCALUT4:       153
+PFUMX:          2
+PUR:            1
+VHI:            6
+VLO:            6
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 153MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Fri May 10 11:59:02 2019
+
+###########################################################]
+
+</pre></samp></body></html>

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_toc.htm b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_toc.htm
new file mode 100644 (file)
index 0000000..50ff329
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_toc.htm
@@ -0,0 +1,60 @@
+ <html> 
+  <head>
+    <script type="text/javascript" src="file:///home/soft/lattice/diamond/3.10_x64/synpbase/lib/report/reportlog_tree.js"></script>
+    <link rel="stylesheet" type="text/css" href="file:///home/soft/lattice/diamond/3.10_x64/synpbase/lib/report/reportlog_tree.css" />  
+  </head> 
+
+  <body style="background-color:#e0e0ff;">
+   <script type="text/javascript"> reportLogObj.loadImage("closed.png", "open.png")</script>
+    <ul id="syn_results-menu" class="treeview" style="padding-left:12;">
+        <li style="font-size:12; font-style:normal"> <b style="background-color:#a2bff0; font-weight:bold">sgmii_ecp5 (syn_results)</b> 
+         <ul rel="open" style="font-size:small;">
+
+<li style="font-size:12; font-style:normal"><b style="background-color:#a2bff0; font-weight:bold">Synthesis -  </b> 
+<ul rel="open">
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#compilerReport1" target="srrFrame" title="">Compiler Report</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#compilerReport4" target="srrFrame" title="">Compiler Constraint Applicator</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#mapperReport6" target="srrFrame" title="">Pre-mapping Report</a>  
+<ul rel="open" >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#mapperReport7" target="srrFrame" title="">Clock Summary</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#mapperReport8" target="srrFrame" title="">Mapper Report</a>  
+<ul rel="open" >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#clockReport9" target="srrFrame" title="">Clock Conversion</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#timingReport10" target="srrFrame" title="">Timing Report</a>  
+<ul rel="open" >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#performanceSummary11" target="srrFrame" title="">Performance Summary</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#clockRelationships12" target="srrFrame" title="">Clock Relationships</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#interfaceInfo13" target="srrFrame" title="">Interface Information</a>  </li>
+<li><a href="file://#" target="srrFrame" title="">Detailed Report for Clocks</a>  
+<ul  >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#clockReport14" target="srrFrame" title="">Clock: sgmii_ecp5|pll_refclki</a>  
+<ul  >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#startingSlack15" target="srrFrame" title="">Starting Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#endingSlack16" target="srrFrame" title="">Ending Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#worstPaths17" target="srrFrame" title="">Worst Path Information</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#clockReport18" target="srrFrame" title="">Clock: sgmii_ecp5|rxrefclk</a>  
+<ul  >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#startingSlack19" target="srrFrame" title="">Starting Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#endingSlack20" target="srrFrame" title="">Ending Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#worstPaths21" target="srrFrame" title="">Worst Path Information</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#clockReport22" target="srrFrame" title="">Clock: sgmii_ecp5|tx_pclk_inferred_clock</a>  
+<ul  >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#startingSlack23" target="srrFrame" title="">Starting Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#endingSlack24" target="srrFrame" title="">Ending Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#worstPaths25" target="srrFrame" title="">Worst Path Information</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#clockReport26" target="srrFrame" title="">Clock: System</a>  
+<ul  >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#startingSlack27" target="srrFrame" title="">Starting Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#endingSlack28" target="srrFrame" title="">Ending Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#worstPaths29" target="srrFrame" title="">Worst Path Information</a>  </li></ul></li></ul></li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/syntmp/sgmii_ecp5_srr.htm#resourceUsage30" target="srrFrame" title="">Resource Utilization</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/sgmii_ecp5_cck.rpt" target="srrFrame" title="">Constraint Checker Report (11:58 10-May)</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/stdout.log" target="srrFrame" title="">Session Log (11:58 10-May)</a>  
+<ul  ></ul></li>         </ul>
+        </li>
+   </ul>
+
+   <script type="text/javascript"> reportLogObj.generateLog("syn_results-menu")</script>
+
+  </body>
+ </html>
\ No newline at end of file

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/syntmp/statusReport.html b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/syntmp/statusReport.html
new file mode 100644 (file)
index 0000000..e6db2e2
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/syntmp/statusReport.html
@@ -0,0 +1,115 @@
+<html> 
+                       <head>                  <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1" />
+                       <title>Project Status Summary Page</title>
+                       <link rel="stylesheet" type="text/css" href="projectstatuspage.css" />
+                       <script type = "text/javascript" src="projectstatuspage.js"></script>
+                       </head>
+
+                       <body style="background-color:#f0f0ff;">
+                       
+<table style="border:none;" width="100%" ><tr> <td class="outline">
+<table width="100%" border="0" cellspacing="0" cellpadding="0">             <thead class="tablehead"><tr><th colspan="4">Project Settings</th><tr> 
+ <tr> <td class="optionTitle" align="left"> Project Name</td> <td> sgmii_ecp5</td> <td class="optionTitle" align="left"> Device Name</td> <td> syn_results: Lattice ECP5UM : LFE5UM_25F</td> </tr>
+<tr> <td class="optionTitle" align="left"> Implementation Name</td> <td> syn_results</td> <td class="optionTitle" align="left"> Top Module</td> <td> sgmii_ecp5</td> </tr>
+                </thead> 
+                <tbody> <tr> <td class="optionTitle" align="left"> Pipelining</td> <td> 0</td> <td class="optionTitle" align="left"> Retiming</td> <td> 0</td> </tr>
+<tr> <td class="optionTitle" align="left"> Resource Sharing</td> <td> 1</td> <td class="optionTitle" align="left"> Fanout Guide</td> <td> 50</td> </tr>
+<tr> <td class="optionTitle" align="left"> Disable I/O Insertion</td> <td> 1</td> <td class="optionTitle" align="left"> Disable Sequential Optimizations</td> <td> 0</td> </tr>
+<tr> <td class="optionTitle" align="left"> Clock Conversion</td> <td> 1</td> <td class="optionTitle" align="left"> FSM Compiler</td> <td> 1</td> </tr>
+ 
+</tbody> 
+  </table><br>  <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
+                                  <thead class="tablehead"><tr><th   colspan="9">Run Status</th></tr></thead>
+         <tbody>
+               <tr>
+                       <th align="left" width="17%">Job Name</th>
+                       <th align="left">Status</th>
+                       <td class="lnote" align="center" title="Notes"></td>
+                       <td class="lwarn" align="center" title="Warnings"></td>
+                       <td class="lerror" align="center" title="Errors"></td>
+                       <th align="left">CPU Time</th>
+                       <th align="left">Real Time</th>
+                       <th align="left">Memory</th>
+                       <th align="left">Date/Time</th>
+         </tr>
+  <tr>
+  <td class="optionTitle"> (compiler)</td><td>Complete</td>
+ <td>15</td>
+ <td>77</td>
+<td>0</td>
+<td>-</td>
+<td>00m:02s</td>
+<td>-</td>
+<td><font size="-1">5/10/19</font><br/><font size="-2">11:58 AM</font></td>
+</tr> 
+
+ <tr>
+  <td class="optionTitle"> (premap)</td><td>Complete</td>
+ <td>9</td>
+ <td>3</td>
+<td>0</td>
+<td>0m:00s</td>
+<td>0m:00s</td>
+<td>144MB</td>
+<td><font size="-1">5/10/19</font><br/><font size="-2">11:58 AM</font></td>
+</tr> 
+
+ <tr>
+  <td class="optionTitle"> (fpga_mapper)</td><td>Complete</td>
+ <td>22</td>
+ <td>4</td>
+<td>0</td>
+<td>0m:03s</td>
+<td>0m:03s</td>
+<td>153MB</td>
+<td><font size="-1">5/10/19</font><br/><font size="-2">11:59 AM</font></td>
+</tr> 
+
+<tr>
+  <td class="optionTitle">Multi-srs Generator</td>
+  <td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td></td><td class="empty"></td><td class="empty"></td><td><font size="-1">5/10/19</font><br/><font size="-2">11:58 AM</font></td>             </tbody>
+     </table>
+ <br> 
+ <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
+                                  <thead class="tablehead"><tr><th   colspan="4">Area Summary</th></tr></thead>
+<tfoot> <tr> <td class="optionTitle" colspan="4"></td></tr> 
+ </tfoot> 
+ <tbody> <tr> 
+<td title ="Total Register bits used" class="optionTitle" align="left">Register bits</td> <td>221</td>
+<td title ="Total I/O cells used" class="optionTitle" align="left">I/O cells</td> <td>0</td>
+</tr>
+<tr> 
+<td title ="Total Block RAMs used" class="optionTitle" align="left">Block RAMs
+(v_ram)</td> <td>0</td>
+<td title ="Total DSPs used" class="optionTitle" align="left">DSPs
+(dsp_used)</td> <td>0</td>
+</tr>
+<tr> 
+<td title ="Total ORCA LUTs used" class="optionTitle" align="left">ORCA LUTs
+(total_luts)</td> <td>153</td>
+<td class="optionTitle"></td><td></td></tr> 
+</tbody>
+    </table><br>
+ <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
+                                  <thead class="tablehead"><tr><th   colspan="4">Timing Summary</th></tr></thead>
+<tfoot> <tr> <td class="optionTitle" colspan="2"></td></tr> 
+ </tfoot> 
+<tbody> 
+   <tr><th class="optionTitle" align= "left ">Clock Name</th><th class="optionTitle" align= "left ">Req Freq</th><th class="optionTitle" align= "left ">Est Freq</th><th class="optionTitle" align= "left ">Slack</th></tr> 
+<tr> <td  align="left">sgmii_ecp5|pll_refclki</td><td  align="left">100.0 MHz</td><td  align="left">168.9 MHz</td><td  align="left">4.079</td></tr> 
+<tr> <td  align="left">sgmii_ecp5|rxrefclk</td><td  align="left">100.0 MHz</td><td  align="left">170.5 MHz</td><td  align="left">4.136</td></tr> 
+<tr> <td  align="left">sgmii_ecp5|tx_pclk_inferred_clock</td><td  align="left">100.0 MHz</td><td  align="left">237.5 MHz</td><td  align="left">5.789</td></tr> 
+<tr> <td  align="left">System</td><td  align="left">100.0 MHz</td><td  align="left">840.7 MHz</td><td  align="left">8.810</td></tr> 
+</tbody> 
+ </table>
+<br>
+ <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
+                                  <thead class="tablehead"><tr><th   colspan="4">Optimizations Summary</th></tr></thead>
+ <tbody> <tr> 
+<td title ="Non-gated/non-generated clock trees / Gated/generated clock trees" class="optionTitle" align="left">Combined Clock Conversion</td> <td>3 / 0</td>
+<td class="optionTitle"></td><td></td></tr> 
+</tbody>
+    </table><br>
+<br> 
+</td></tr></table></body> 
+ </html>
\ No newline at end of file

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/.cckTransfer b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/.cckTransfer
new file mode 100644 (file)
index 0000000..2c37cc7
Binary files /dev/null and b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/.cckTransfer differ

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/_mh_info b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/_mh_info
new file mode 100644 (file)
index 0000000..88b9f85
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/_mh_info
@@ -0,0 +1,2 @@
+|/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer1.info|
+|2|

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/_verilog_hintfile b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/_verilog_hintfile
new file mode 100644 (file)
index 0000000..1141ff7
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/_verilog_hintfile
@@ -0,0 +1,69 @@
+%%% protect protected_file
+#OPTIONS:"|-bldtbl|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
+#CUR:"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":1557482333
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599
+@E8lFkRDC#HolHO_CbD6
+HNLssI$RF
+s      Fbk0kE0R80Fkb
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+R4HkMb08REHRMb4M
+HbRk0EM8HM
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+HbRk00_GHORD   4M
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+bHMk#0RHNoMDC_800CO_4OR
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+M0bkR_0G#8CsCs#_#O0_RH4
+M0bkR_0Gb_O#s_#0O
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+0FkbRk0s_#D0sG_84$R
+bHMks0RGC_#s#8C_0s#_4OR
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+F00bkRDs#__sGsR8$4M
+C88lFk
+DC
+
+@ 

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer0.fdep b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer0.fdep
new file mode 100644 (file)
index 0000000..de7e201
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer0.fdep
@@ -0,0 +1,33 @@
+#defaultlanguage:vhdl
+#OPTIONS:"|-mixedhdl|-top|sgmii_ecp5|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610
+#CUR:"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":1557482333
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599
+0 "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd" vhdl
+
+# Dependency Lists (Uses list)
+0 -1
+
+# Dependency Lists (Users Of)
+0 -1
+
+# Design Unit to File Association
+arch work sgmii_ecp5 v1 0
+module work sgmii_ecp5 0
+
+# Unbound Instances to File Association
+inst work sgmii_ecp5 sgmii_ecp5sll_core 0
+inst work sgmii_ecp5 sgmii_ecp5rsl_core 0
+inst work sgmii_ecp5 dcua 0
+
+
+# Configuration files used

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer0.fdeporig b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer0.fdeporig
new file mode 100644 (file)
index 0000000..8ad50c3
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer0.fdeporig
@@ -0,0 +1,29 @@
+#defaultlanguage:vhdl
+#OPTIONS:"|-mixedhdl|-top|sgmii_ecp5|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610
+#CUR:"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":1557482333
+0 "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd" vhdl
+
+# Dependency Lists (Uses list)
+0 -1
+
+# Dependency Lists (Users Of)
+0 -1
+
+# Design Unit to File Association
+arch work sgmii_ecp5 v1 0
+module work sgmii_ecp5 0
+
+# Unbound Instances to File Association
+inst work sgmii_ecp5 sgmii_ecp5sll_core 0
+inst work sgmii_ecp5 sgmii_ecp5rsl_core 0
+inst work sgmii_ecp5 dcua 0

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer0.srs b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer0.srs
new file mode 100644 (file)
index 0000000..df69de7
Binary files /dev/null and b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer0.srs differ

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer0.tlg b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer0.tlg
new file mode 100644 (file)
index 0000000..10b82d6
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer0.tlg
@@ -0,0 +1,2 @@
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":30:7:30:16|Synthesizing work.sgmii_ecp5.v1.
+Post processing for work.sgmii_ecp5.v1

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer0.tlg.db b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer0.tlg.db
new file mode 100644 (file)
index 0000000..7105d57
Binary files /dev/null and b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer0.tlg.db differ

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer1.fdep b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer1.fdep
new file mode 100644 (file)
index 0000000..18f4970
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer1.fdep
@@ -0,0 +1,22 @@
+#OPTIONS:"|-mixedhdl|-modhint|/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/_verilog_hintfile|-top|work.sgmii_ecp5sll_core|-top|work.sgmii_ecp5rsl_core|-mpparams|/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/_mh_params|-layerid|1|-orig_srs|/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/|-I|/home/soft/lattice/diamond/3.10_x64/synpbase/lib|-v2001|-devicelib|/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v|-devicelib|/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_ver":1542167761
+#CUR:"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/_verilog_hintfile":1557482335
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v":1542167595
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v":1542167597
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v":1542167630
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v":1542167630
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v":1542167630
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh":1542167630
+#CUR:"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1557482333
+#numinternalfiles:6
+#defaultlanguage:verilog
+0                      "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v" verilog
+#Dependency Lists(Uses List)
+0 -1
+#Dependency Lists(Users Of)
+0 -1
+#Design Unit to File Association
+module work sgmii_ecp5rsl_core 0
+module work sync 0
+module work sgmii_ecp5sll_core 0
+#Unbound instances to file Association.

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer1.fdepxmr b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer1.fdepxmr
new file mode 100644 (file)
index 0000000..37d628b
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer1.fdepxmr
@@ -0,0 +1 @@
+#XMR Information

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer1.info b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer1.info
new file mode 100644 (file)
index 0000000..defe9c7
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer1.info
@@ -0,0 +1,2 @@
+|work.sgmii_ecp5rsl_core|parameter pnum_channels 1;,parameter pprotocol "GBE";,parameter pserdes_mode "RX AND TX";,parameter pport_tx_rdy "ENABLED";,parameter pwait_tx_rdy 3000;,parameter pport_rx_rdy "ENABLED";,parameter pwait_rx_rdy 3000;|
+|work.sgmii_ecp5sll_core|parameter PPROTOCOL "GBE";,parameter PLOL_SETTING 0;,parameter PDYN_RATE_CTRL "DISABLED";,parameter PPCIE_MAX_RATE "2.5";,parameter PDIFF_VAL_LOCK 19;,parameter PDIFF_VAL_UNLOCK 39;,parameter PPCLK_TC 65536;,parameter PDIFF_DIV11_VAL_LOCK 0;,parameter PDIFF_DIV11_VAL_UNLOCK 0;,parameter PPCLK_DIV11_TC 0;|

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer1.srs b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer1.srs
new file mode 100644 (file)
index 0000000..e9a57b6
Binary files /dev/null and b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer1.srs differ

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer1.tlg b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer1.tlg
new file mode 100644 (file)
index 0000000..7191c18
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer1.tlg
@@ -0,0 +1,253 @@
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work.
+
+       PDATA_RST_VAL=32'b00000000000000000000000000000000
+   Generated name = sync_0s
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1051:7:1051:24|Synthesizing module sgmii_ecp5sll_core in library work.
+
+       PPROTOCOL=24'b010001110100001001000101
+       PLOL_SETTING=32'b00000000000000000000000000000000
+       PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100
+       PPCIE_MAX_RATE=24'b001100100010111000110101
+       PDIFF_VAL_LOCK=32'b00000000000000000000000000010011
+       PDIFF_VAL_UNLOCK=32'b00000000000000000000000000100111
+       PPCLK_TC=32'b00000000000000010000000000000000
+       PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000
+       PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000
+       PPCLK_DIV11_TC=32'b00000000000000000000000000000000
+       LPLL_LOSS_ST=2'b00
+       LPLL_PRELOSS_ST=2'b01
+       LPLL_PRELOCK_ST=2'b10
+       LPLL_LOCK_ST=2'b11
+       LRCLK_TC=16'b1111111111111111
+       LRCLK_TC_PUL_WIDTH=16'b0000000000110010
+       LHB_WAIT_CNT=8'b11111111
+       LPCLK_TC_0=32'b00000000000000001000000000000000
+       LPCLK_TC_1=32'b00000000000000010000000000000000
+       LPCLK_TC_2=32'b00000000000000100000000000000000
+       LPCLK_TC_3=32'b00000000000000101000000000000000
+       LPCLK_TC_4=32'b00000000000000010000000000000000
+       LPDIFF_LOCK_00=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_10=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_20=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_30=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_40=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_01=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_11=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_21=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_31=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_41=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_02=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_12=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_22=32'b00000000000000000000000011000100
+       LPDIFF_LOCK_32=32'b00000000000000000000000011110101
+       LPDIFF_LOCK_42=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_03=32'b00000000000000000000000010000011
+       LPDIFF_LOCK_13=32'b00000000000000000000000100000110
+       LPDIFF_LOCK_23=32'b00000000000000000000001000001100
+       LPDIFF_LOCK_33=32'b00000000000000000000001010001111
+       LPDIFF_LOCK_43=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011
+       LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110
+       LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010
+       LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001
+       LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111
+       LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000
+       LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000
+       LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000
+       LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100
+       LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001
+       LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010
+       LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111
+       LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001
+   Generated name = sgmii_ecp5sll_core_Z1_layer1
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1287:54:1287:59|Removing redundant assignment.
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1293:52:1293:55|Removing redundant assignment.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 17 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":92:7:92:24|Synthesizing module sgmii_ecp5rsl_core in library work.
+
+       pnum_channels=32'b00000000000000000000000000000001
+       pprotocol=24'b010001110100001001000101
+       pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
+       pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_tx_rdy=32'b00000000000000000000101110111000
+       pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_rx_rdy=32'b00000000000000000000101110111000
+       wa_num_cycles=32'b00000000000000000000010000000000
+       dac_num_cycles=32'b00000000000000000000000000000011
+       lreset_pwidth=32'b00000000000000000000000000000011
+       lwait_b4_trst=32'b00000000000010111110101111000010
+       lwait_b4_trst_s=32'b00000000000000000000001100001101
+       lplol_cnt_width=32'b00000000000000000000000000010100
+       lwait_after_plol0=32'b00000000000000000000000000000100
+       lwait_b4_rrst=32'b00000000000000101100000000000000
+       lrrst_wait_width=32'b00000000000000000000000000010100
+       lwait_after_rrst=32'b00000000000011000011010100000000
+       lwait_b4_rrst_s=32'b00000000000000000000000111001100
+       lrlol_cnt_width=32'b00000000000000000000000000010011
+       lwait_after_lols=32'b00000000000000001100010000000000
+       lwait_after_lols_s=32'b00000000000000000000000010010110
+       llols_cnt_width=32'b00000000000000000000000000010010
+       lrdb_max=32'b00000000000000000000000000001111
+       ltxr_wait_width=32'b00000000000000000000000000001100
+       lrxr_wait_width=32'b00000000000000000000000000001100
+   Generated name = sgmii_ecp5rsl_core_Z2_layer1
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_unlock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning register bits 4 to 3 of genblk5.rdiff_comp_lock[4:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[2]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[16]. Make sure that there are no unused intermediate registers.
+@N: CL201 :"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state.
+Extracted state machine for register sll_state
+State machine has 4 reachable states with original encodings of:
+   00
+   01
+   10
+   11

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer1.tlg.db b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer1.tlg.db
new file mode 100644 (file)
index 0000000..bd40751
Binary files /dev/null and b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/layer1.tlg.db differ

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/modulechange.db b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/modulechange.db
new file mode 100644 (file)
index 0000000..40736e7
Binary files /dev/null and b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/modulechange.db differ

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/modulechange_mixhdl/layer0/modulechange.db b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/modulechange_mixhdl/layer0/modulechange.db
new file mode 100644 (file)
index 0000000..8054ea0
Binary files /dev/null and b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/modulechange_mixhdl/layer0/modulechange.db differ

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/modulechange_mixhdl/layer1/modulechange.db b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/modulechange_mixhdl/layer1/modulechange.db
new file mode 100644 (file)
index 0000000..a52bea9
Binary files /dev/null and b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/modulechange_mixhdl/layer1/modulechange.db differ

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.fdep b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.fdep
new file mode 100644 (file)
index 0000000..fbb2b43
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.fdep
@@ -0,0 +1,37 @@
+#OPTIONS:"|-mixedhdl|-top|sgmii_ecp5|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610
+#CUR:"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd":1557482333
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599
+#OPTIONS:"|-mixedhdl|-modhint|/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/_verilog_hintfile|-top|work.sgmii_ecp5sll_core|-top|work.sgmii_ecp5rsl_core|-mpparams|/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/_mh_params|-layerid|1|-orig_srs|/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/|-I|/home/soft/lattice/diamond/3.10_x64/synpbase/lib|-v2001|-devicelib|/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v|-devicelib|/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_ver":1542167761
+#CUR:"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/syn_results/synwork/_verilog_hintfile":1557482335
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v":1542167595
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v":1542167597
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v":1542167630
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v":1542167630
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v":1542167630
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh":1542167630
+#CUR:"/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v":1557482333
+0                      "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd" vhdl
+1                      "/home/adrian/git/trb5sc/template/project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v" verilog
+#Dependency Lists(Uses List)
+0 1
+1 -1
+#Dependency Lists(Users Of)
+0 -1
+1 0
+#Design Unit to File Association
+module work sgmii_ecp5sll_core 1
+module work sync 1
+module work sgmii_ecp5rsl_core 1
+module work sgmii_ecp5 0
+arch work sgmii_ecp5 v1 0

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.linkerlog b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.linkerlog
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs
new file mode 100644 (file)
index 0000000..c2c1102
Binary files /dev/null and b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_comp.srs differ

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm
new file mode 100644 (file)
index 0000000..bacca77
Binary files /dev/null and b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m.srm differ

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m_srm/1.srm b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m_srm/1.srm
new file mode 100644 (file)
index 0000000..a467cd3
Binary files /dev/null and b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m_srm/1.srm differ

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m_srm/fileinfo.srm b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m_srm/fileinfo.srm
new file mode 100644 (file)
index 0000000..67b488a
Binary files /dev/null and b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_m_srm/fileinfo.srm differ

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult.srs b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult.srs
new file mode 100644 (file)
index 0000000..930c248
Binary files /dev/null and b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult.srs differ

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult_srs/1.srs b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult_srs/1.srs
new file mode 100644 (file)
index 0000000..de48e47
Binary files /dev/null and b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult_srs/1.srs differ

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult_srs/fileinfo.srs b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult_srs/fileinfo.srs
new file mode 100644 (file)
index 0000000..7df2507
Binary files /dev/null and b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult_srs/fileinfo.srs differ

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult_srs/skeleton.srs b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult_srs/skeleton.srs
new file mode 100644 (file)
index 0000000..6e5c30e
Binary files /dev/null and b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_mult_srs/skeleton.srs differ

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_prem.fse b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_prem.fse
new file mode 100644 (file)
index 0000000..cc147f0
--- /dev/null
+++ b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_prem.fse
@@ -0,0 +1,12 @@
+
+fsm_encoding {61801018011} sequential
+
+fsm_state_encoding {61801018011} LPLL_LOSS_ST {00}
+
+fsm_state_encoding {61801018011} LPLL_PRELOSS_ST {01}
+
+fsm_state_encoding {61801018011} LPLL_PRELOCK_ST {10}
+
+fsm_state_encoding {61801018011} LPLL_LOCK_ST {11}
+
+fsm_registers {61801018011} {sll_state[1]}  {sll_state[0]} 

diff --git a/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_prem.srd b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_prem.srd
new file mode 100644 (file)
index 0000000..3f73aac
Binary files /dev/null and b/gbe/cores/test_gbepcs/sgmii_ecp5/syn_results/synwork/sgmii_ecp5_prem.srd differ

diff --git a/gbe/cores/test_gbepcs/test_gbepcs.sbx b/gbe/cores/test_gbepcs/test_gbepcs.sbx
new file mode 100644 (file)
index 0000000..63e4629
--- /dev/null
+++ b/gbe/cores/test_gbepcs/test_gbepcs.sbx
@@ -0,0 +1,2171 @@
+<!DOCTYPE test_gbepcs>
+<lattice:project>
+    <spirit:component>
+        <spirit:vendor>LATTICE</spirit:vendor>
+        <spirit:library>LOCAL</spirit:library>
+        <spirit:name>test_gbepcs</spirit:name>
+        <spirit:version>1.0</spirit:version>
+        <spirit:fileSets>
+            <spirit:fileset>
+                <spirit:name>Diamond_Synthesis</spirit:name>
+                <spirit:group>synthesis</spirit:group>
+                <spirit:file>
+                    <spirit:name>./test_gbepcs.vhd</spirit:name>
+                    <spirit:fileType>vhdlSource</spirit:fileType>
+                </spirit:file>
+            </spirit:fileset>
+            <spirit:fileset>
+                <spirit:name>Diamond_Simulation</spirit:name>
+                <spirit:group>simulation</spirit:group>
+                <spirit:file>
+                    <spirit:name>./test_gbepcs.vhd</spirit:name>
+                    <spirit:fileType>vhdlSource</spirit:fileType>
+                </spirit:file>
+            </spirit:fileset>
+        </spirit:fileSets>
+        <spirit:componentGenerators/>
+        <spirit:model>
+            <spirit:views/>
+            <spirit:ports>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_ctc_del_s</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_ctc_del_s</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.ctc_del_s</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_ctc_ins_s</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_ctc_ins_s</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.ctc_ins_s</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_ctc_orun_s</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_ctc_orun_s</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.ctc_orun_s</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_ctc_urun_s</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_ctc_urun_s</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.ctc_urun_s</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_cyawstn</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_cyawstn</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.cyawstn</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_hdinn</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_hdinn</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.hdinn</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_hdinp</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_hdinp</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.hdinp</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_hdoutn</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_hdoutn</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.hdoutn</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_hdoutp</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_hdoutp</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.hdoutp</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_lsm_status_s</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_lsm_status_s</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.lsm_status_s</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_pll_lol</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_pll_lol</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.pll_lol</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_pll_refclki</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_pll_refclki</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.pll_refclki</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_rsl_disable</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_rsl_disable</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.rsl_disable</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_rsl_rst</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_rsl_rst</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.rsl_rst</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_rsl_rx_rdy</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_rsl_rx_rdy</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
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+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.rsl_rx_rdy</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_rsl_tx_rdy</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_rsl_tx_rdy</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.rsl_tx_rdy</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
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+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_rst_dual_c</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_rst_dual_c</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.rst_dual_c</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_rx_cdr_lol_s</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_rx_cdr_lol_s</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.rx_cdr_lol_s</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
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+                    <spirit:name>sgmii_ecp5_rx_los_low_s</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_rx_los_low_s</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
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+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.rx_los_low_s</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
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+                    <spirit:name>sgmii_ecp5_rx_pcs_rst_c</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_rx_pcs_rst_c</spirit:displayName>
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+                        <spirit:direction>in</spirit:direction>
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+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.rx_pcs_rst_c</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
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+                        <spirit:direction>in</spirit:direction>
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+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.rx_pwrup_c</lattice:attribute>
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+                    <spirit:displayName>sgmii_ecp5_rx_serdes_rst_c</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.rx_serdes_rst_c</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
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+                    <spirit:name>sgmii_ecp5_rxrefclk</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_rxrefclk</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.rxrefclk</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_sci_en</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_sci_en</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.sci_en</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_sci_en_dual</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_sci_en_dual</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.sci_en_dual</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_sci_int</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_sci_int</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.sci_int</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_sci_rd</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_sci_rd</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.sci_rd</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_sci_sel</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_sci_sel</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.sci_sel</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_sci_sel_dual</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_sci_sel_dual</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.sci_sel_dual</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
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+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_sci_wrn</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_sci_wrn</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.sci_wrn</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_serdes_pdb</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_serdes_pdb</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.serdes_pdb</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_serdes_rst_dual_c</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_serdes_rst_dual_c</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.serdes_rst_dual_c</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_signal_detect_c</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_signal_detect_c</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.signal_detect_c</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_tx_pclk</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_tx_pclk</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.tx_pclk</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
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+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_tx_pcs_rst_c</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_tx_pcs_rst_c</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.tx_pcs_rst_c</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>sgmii_ecp5_tx_pwrup_c</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_tx_pwrup_c</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.tx_pwrup_c</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
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+                    <spirit:name>sgmii_ecp5_tx_serdes_rst_c</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_tx_serdes_rst_c</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.tx_serdes_rst_c</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
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+                    <spirit:name>sgmii_ecp5_txi_clk</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_txi_clk</spirit:displayName>
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+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.txi_clk</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
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+                    <spirit:name>sgmii_ecp5_rx_cv_err</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_rx_cv_err</spirit:displayName>
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+                        <spirit:direction>out</spirit:direction>
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+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.rx_cv_err</lattice:attribute>
+                        </lattice:attributes>
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+                    <spirit:name>sgmii_ecp5_rx_disp_err</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_rx_disp_err</spirit:displayName>
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+                        <spirit:direction>out</spirit:direction>
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+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.rx_disp_err</lattice:attribute>
+                        </lattice:attributes>
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+                    <spirit:name>sgmii_ecp5_rx_k</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_rx_k</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
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+                            <spirit:left>0</spirit:left>
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+                        </spirit:vector>
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+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.rx_k</lattice:attribute>
+                        </lattice:attributes>
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+                    <spirit:name>sgmii_ecp5_rxdata</spirit:name>
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+                        <spirit:direction>out</spirit:direction>
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+                            <spirit:left>7</spirit:left>
+                            <spirit:right>0</spirit:right>
+                        </spirit:vector>
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+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.rxdata</lattice:attribute>
+                        </lattice:attributes>
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+                    <spirit:name>sgmii_ecp5_sci_addr</spirit:name>
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+                        <spirit:direction>in</spirit:direction>
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+                            <spirit:left>5</spirit:left>
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+                        </spirit:vector>
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+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.sci_addr</lattice:attribute>
+                        </lattice:attributes>
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+                    <spirit:name>sgmii_ecp5_sci_rddata</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_sci_rddata</spirit:displayName>
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+                        <spirit:direction>out</spirit:direction>
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+                            <spirit:left>7</spirit:left>
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+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.sci_rddata</lattice:attribute>
+                        </lattice:attributes>
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+                    <spirit:name>sgmii_ecp5_sci_wrdata</spirit:name>
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+                        <spirit:direction>in</spirit:direction>
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+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.sci_wrdata</lattice:attribute>
+                        </lattice:attributes>
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+                    <spirit:name>sgmii_ecp5_tx_disp_correct</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_tx_disp_correct</spirit:displayName>
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+                        <spirit:direction>in</spirit:direction>
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+                            <spirit:left>0</spirit:left>
+                            <spirit:right>0</spirit:right>
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+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.tx_disp_correct</lattice:attribute>
+                        </lattice:attributes>
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+                    <spirit:name>sgmii_ecp5_tx_k</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_tx_k</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
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+                            <spirit:left>0</spirit:left>
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+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.tx_k</lattice:attribute>
+                        </lattice:attributes>
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+                    <spirit:name>sgmii_ecp5_txdata</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_txdata</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
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+                            <spirit:left>7</spirit:left>
+                            <spirit:right>0</spirit:right>
+                        </spirit:vector>
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+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.txdata</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
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+                    <spirit:name>sgmii_ecp5_xmit</spirit:name>
+                    <spirit:displayName>sgmii_ecp5_xmit</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                        <spirit:vector>
+                            <spirit:left>0</spirit:left>
+                            <spirit:right>0</spirit:right>
+                        </spirit:vector>
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+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">sgmii_ecp5.xmit</lattice:attribute>
+                        </lattice:attributes>
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+        <spirit:vendorExtensions>
+            <lattice:device>LFE5UM-85F-8BG756C</lattice:device>
+            <lattice:synthesis>synplify</lattice:synthesis>
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+            <lattice:modified>2019-05-10.11:59:27 AM</lattice:modified>
+            <lattice:diamond>3.10.3.144</lattice:diamond>
+            <lattice:language>VHDL</lattice:language>
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+                <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+                <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+                <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+                <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+            </lattice:attributes>
+            <lattice:elements/>
+            <lattice:lpc/>
+            <lattice:groups/>
+        </spirit:vendorExtensions>
+    </spirit:component>
+    <spirit:design>
+        <spirit:vendor>LATTICE</spirit:vendor>
+        <spirit:library>LOCAL</spirit:library>
+        <spirit:name>test_gbepcs</spirit:name>
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+        <spirit:componentInstances>
+            <spirit:componentInstance>
+                <spirit:instanceName>sgmii_ecp5</spirit:instanceName>
+                <spirit:componentRef>
+                    <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
+                    <spirit:library>LEGACY</spirit:library>
+                    <spirit:name>PCS</spirit:name>
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+                    <spirit:fileSets>
+                        <spirit:fileset>
+                            <spirit:name>Diamond_Simulation</spirit:name>
+                            <spirit:group>simulation</spirit:group>
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+                                <spirit:name>./sgmii_ecp5/sgmii_ecp5_softlogic.v</spirit:name>
+                                <spirit:fileType>verilogSource</spirit:fileType>
+                            </spirit:file>
+                            <spirit:file>
+                                <spirit:name>./sgmii_ecp5/sgmii_ecp5.vhd</spirit:name>
+                                <spirit:fileType>vhdlSource</spirit:fileType>
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+                            <spirit:name>Diamond_Synthesis</spirit:name>
+                            <spirit:group>synthesis</spirit:group>
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+                                <spirit:name>./sgmii_ecp5/sgmii_ecp5_softlogic.v</spirit:name>
+                                <spirit:fileType>verilogSource</spirit:fileType>
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+                            <spirit:file>
+                                <spirit:name>./sgmii_ecp5/sgmii_ecp5.vhd</spirit:name>
+                                <spirit:fileType>vhdlSource</spirit:fileType>
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+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>Configuration</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
+                            <spirit:group>CONFIG</spirit:group>
+                        </spirit:componentGenerator>
+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>CreateNGD</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_ngd.tcl</spirit:generatorExe>
+                            <spirit:group>CONFIG</spirit:group>
+                        </spirit:componentGenerator>
+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>Generation</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
+                            <spirit:group>GENERATE</spirit:group>
+                        </spirit:componentGenerator>
+                    </spirit:componentGenerators>
+                    <spirit:model>
+                        <spirit:views/>
+                        <spirit:ports>
+                            <spirit:port>
+                                <spirit:name>ctc_del_s</spirit:name>
+                                <spirit:displayName>ctc_del_s</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>ctc_ins_s</spirit:name>
+                                <spirit:displayName>ctc_ins_s</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>ctc_orun_s</spirit:name>
+                                <spirit:displayName>ctc_orun_s</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>ctc_urun_s</spirit:name>
+                                <spirit:displayName>ctc_urun_s</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>cyawstn</spirit:name>
+                                <spirit:displayName>cyawstn</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>hdinn</spirit:name>
+                                <spirit:displayName>hdinn</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                                <spirit:vendorExtensions>
+                                    <lattice:attributes>
+                                        <lattice:attribute lattice:name="PadPin">true</lattice:attribute>
+                                    </lattice:attributes>
+                                </spirit:vendorExtensions>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>hdinp</spirit:name>
+                                <spirit:displayName>hdinp</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                                <spirit:vendorExtensions>
+                                    <lattice:attributes>
+                                        <lattice:attribute lattice:name="PadPin">true</lattice:attribute>
+                                    </lattice:attributes>
+                                </spirit:vendorExtensions>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>hdoutn</spirit:name>
+                                <spirit:displayName>hdoutn</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                                <spirit:vendorExtensions>
+                                    <lattice:attributes>
+                                        <lattice:attribute lattice:name="PadPin">true</lattice:attribute>
+                                    </lattice:attributes>
+                                </spirit:vendorExtensions>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>hdoutp</spirit:name>
+                                <spirit:displayName>hdoutp</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                                <spirit:vendorExtensions>
+                                    <lattice:attributes>
+                                        <lattice:attribute lattice:name="PadPin">true</lattice:attribute>
+                                    </lattice:attributes>
+                                </spirit:vendorExtensions>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>lsm_status_s</spirit:name>
+                                <spirit:displayName>lsm_status_s</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>pll_lol</spirit:name>
+                                <spirit:displayName>pll_lol</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>pll_refclki</spirit:name>
+                                <spirit:displayName>pll_refclki</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rsl_disable</spirit:name>
+                                <spirit:displayName>rsl_disable</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rsl_rst</spirit:name>
+                                <spirit:displayName>rsl_rst</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rsl_rx_rdy</spirit:name>
+                                <spirit:displayName>rsl_rx_rdy</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rsl_tx_rdy</spirit:name>
+                                <spirit:displayName>rsl_tx_rdy</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rst_dual_c</spirit:name>
+                                <spirit:displayName>rst_dual_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_cdr_lol_s</spirit:name>
+                                <spirit:displayName>rx_cdr_lol_s</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_los_low_s</spirit:name>
+                                <spirit:displayName>rx_los_low_s</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_pcs_rst_c</spirit:name>
+                                <spirit:displayName>rx_pcs_rst_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_pwrup_c</spirit:name>
+                                <spirit:displayName>rx_pwrup_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_serdes_rst_c</spirit:name>
+                                <spirit:displayName>rx_serdes_rst_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rxrefclk</spirit:name>
+                                <spirit:displayName>rxrefclk</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_en</spirit:name>
+                                <spirit:displayName>sci_en</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_en_dual</spirit:name>
+                                <spirit:displayName>sci_en_dual</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_int</spirit:name>
+                                <spirit:displayName>sci_int</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_rd</spirit:name>
+                                <spirit:displayName>sci_rd</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_sel</spirit:name>
+                                <spirit:displayName>sci_sel</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_sel_dual</spirit:name>
+                                <spirit:displayName>sci_sel_dual</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_wrn</spirit:name>
+                                <spirit:displayName>sci_wrn</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>serdes_pdb</spirit:name>
+                                <spirit:displayName>serdes_pdb</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>serdes_rst_dual_c</spirit:name>
+                                <spirit:displayName>serdes_rst_dual_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>signal_detect_c</spirit:name>
+                                <spirit:displayName>signal_detect_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sli_rst</spirit:name>
+                                <spirit:displayName>sli_rst</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                                <spirit:vendorExtensions>
+                                    <lattice:attributes>
+                                        <lattice:attribute lattice:name="Hide">true</lattice:attribute>
+                                    </lattice:attributes>
+                                </spirit:vendorExtensions>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_pclk</spirit:name>
+                                <spirit:displayName>tx_pclk</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_pcs_rst_c</spirit:name>
+                                <spirit:displayName>tx_pcs_rst_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_pwrup_c</spirit:name>
+                                <spirit:displayName>tx_pwrup_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_serdes_rst_c</spirit:name>
+                                <spirit:displayName>tx_serdes_rst_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>txi_clk</spirit:name>
+                                <spirit:displayName>txi_clk</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_cv_err</spirit:name>
+                                <spirit:displayName>rx_cv_err</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>0</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_disp_err</spirit:name>
+                                <spirit:displayName>rx_disp_err</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>0</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_k</spirit:name>
+                                <spirit:displayName>rx_k</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>0</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rxdata</spirit:name>
+                                <spirit:displayName>rxdata</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>7</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_addr</spirit:name>
+                                <spirit:displayName>sci_addr</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>5</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_rddata</spirit:name>
+                                <spirit:displayName>sci_rddata</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>7</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_wrdata</spirit:name>
+                                <spirit:displayName>sci_wrdata</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>7</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_disp_correct</spirit:name>
+                                <spirit:displayName>tx_disp_correct</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>0</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_k</spirit:name>
+                                <spirit:displayName>tx_k</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>0</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>txdata</spirit:name>
+                                <spirit:displayName>txdata</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>7</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>xmit</spirit:name>
+                                <spirit:displayName>xmit</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>0</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                        </spirit:ports>
+                    </spirit:model>
+                    <spirit:vendorExtensions>
+                        <lattice:synthesis>synplify</lattice:synthesis>
+                        <lattice:modified>2019-05-10.11:59:27 AM</lattice:modified>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+                            <lattice:attribute lattice:name="BBox">false</lattice:attribute>
+                            <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+                            <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute>
+                            <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute>
+                            <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute>
+                            <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+                            <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+                        </lattice:attributes>
+                        <lattice:elements>
+                            <lattice:element>
+                                <lattice:name>Lane0</lattice:name>
+                                <lattice:type>DCUCHANNEL</lattice:type>
+                                <lattice:attributes>
+                                    <lattice:attribute lattice:name="ElementDrag">true</lattice:attribute>
+                                    <lattice:attribute lattice:name="ElementHide">false</lattice:attribute>
+                                    <lattice:attribute lattice:name="ElementType">DCUCHANNEL</lattice:attribute>
+                                    <lattice:attribute lattice:name="Locate">9</lattice:attribute>
+                                </lattice:attributes>
+                            </lattice:element>
+                        </lattice:elements>
+                        <lattice:lpc>
+                            <lattice:lpcsection lattice:name="Device"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Family</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">ecp5um</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>OperatingCondition</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Package</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">CABGA756</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PartName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F-8BG756C</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PartType</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SpeedGrade</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Status</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">P</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="IP"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">PCS</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreRevision</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">8.2</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreStatus</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreType</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Date</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">05/10/2019</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ModuleName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">sgmii_ecp5</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SourceFormat</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">VHDL</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Time</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">11:58:52</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>VendorName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="Parameters"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>;ACHARA</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>;ACHARB</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>;ACHARM</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>;RXMCAENABLE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CDRLOLACTION</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Full Recalibration</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CDRLOLRANGE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CDR_MAX_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">2</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CDR_MULT</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">10X</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CDR_REF_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">200.0000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CH_MODE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Rx and Tx</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Destination</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>EDIF</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Expression</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">BusA(0 to 7)</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>IO</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>IO_TYPE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">GbE</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>LEQ</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>LOOPBACK</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>LOSPORT</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>NUM_CHS</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Order</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PPORT_RX_RDY</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PPORT_TX_RDY</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PROTOCOL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">GbE</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PWAIT_RX_RDY</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">3000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PWAIT_TX_RDY</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">3000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RCSRC</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>REFCLK_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">200.0000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RSTSEQSEL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RX8B10B</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCOMMAA</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1010000011</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCOMMAB</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0101111100</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCOMMAM</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1111111111</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCOUPLING</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">AC</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCTC</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCTCBYTEN</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCTCBYTEN1</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCTCBYTEN2</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1 BCH</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCTCBYTEN3</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0 50H</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCTCMATCHPATTERN</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">M2-S2</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXDIFFTERM</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">50 ohms</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXFIFO_ENABLE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXINVPOL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Non-invert</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXLDR</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Off</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXLOSTHRESHOLD</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">2</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXLSM</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXSC</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">K28P5</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXWA</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Barrel Shift</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RX_DATA_WIDTH</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">8/10-Bit</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RX_FICLK_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">200.0000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RX_LINE_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">2.0000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RX_RATE_DIV</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Full Rate</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SCIPORT</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SOFTLOL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TX8B10B</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXAMPLITUDE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1100</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXDEPOST</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXDEPRE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXDIFFTERM</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">50 ohms</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXFIFO_ENABLE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXINVPOL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Non-invert</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXLDR</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Off</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXPLLLOLTHRESHOLD</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXPLLMULT</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">10X</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TX_DATA_WIDTH</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">8/10-Bit</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TX_FICLK_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">200.0000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TX_LINE_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">2.0000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TX_MAX_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">2</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TX_RATE_DIV</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Full Rate</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>VHDL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Verilog</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="FilesGenerated"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>sgmii_ecp5.pp</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">pp</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>sgmii_ecp5.sym</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">sym</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>sgmii_ecp5.tft</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">tft</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>sgmii_ecp5.txt</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">pcs_module</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                        </lattice:lpc>
+                        <lattice:groups>
+                            <lattice:group>
+                                <lattice:name>DCUCHANNEL</lattice:name>
+                                <lattice:category>1</lattice:category>
+                                <lattice:attributes>
+                                    <lattice:attribute lattice:name="GroupDrag">true</lattice:attribute>
+                                    <lattice:attribute lattice:name="GroupHide">false</lattice:attribute>
+                                    <lattice:attribute lattice:name="GroupType">DCUCHANNEL</lattice:attribute>
+                                </lattice:attributes>
+                                <lattice:elementref>Lane0</lattice:elementref>
+                            </lattice:group>
+                        </lattice:groups>
+                    </spirit:vendorExtensions>
+                </spirit:componentRef>
+            </spirit:componentInstance>
+        </spirit:componentInstances>
+        <spirit:adHocConnections>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_ctc_del_s</spirit:name>
+                <spirit:displayName>sgmii_ecp5_ctc_del_s</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="ctc_del_s" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_ctc_del_s"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_ctc_ins_s</spirit:name>
+                <spirit:displayName>sgmii_ecp5_ctc_ins_s</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="ctc_ins_s" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_ctc_ins_s"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_ctc_orun_s</spirit:name>
+                <spirit:displayName>sgmii_ecp5_ctc_orun_s</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="ctc_orun_s" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_ctc_orun_s"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_ctc_urun_s</spirit:name>
+                <spirit:displayName>sgmii_ecp5_ctc_urun_s</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="ctc_urun_s" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_ctc_urun_s"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_cyawstn</spirit:name>
+                <spirit:displayName>sgmii_ecp5_cyawstn</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="cyawstn" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_cyawstn"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_hdinn</spirit:name>
+                <spirit:displayName>sgmii_ecp5_hdinn</spirit:displayName>
+                <spirit:vendorExtensions>
+                    <lattice:attributes>
+                        <lattice:attribute lattice:name="export">sys_yes</lattice:attribute>
+                    </lattice:attributes>
+                </spirit:vendorExtensions>
+                <spirit:internalPortReference spirit:portRef="hdinn" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_hdinn"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_hdinp</spirit:name>
+                <spirit:displayName>sgmii_ecp5_hdinp</spirit:displayName>
+                <spirit:vendorExtensions>
+                    <lattice:attributes>
+                        <lattice:attribute lattice:name="export">sys_yes</lattice:attribute>
+                    </lattice:attributes>
+                </spirit:vendorExtensions>
+                <spirit:internalPortReference spirit:portRef="hdinp" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_hdinp"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_hdoutn</spirit:name>
+                <spirit:displayName>sgmii_ecp5_hdoutn</spirit:displayName>
+                <spirit:vendorExtensions>
+                    <lattice:attributes>
+                        <lattice:attribute lattice:name="export">sys_yes</lattice:attribute>
+                    </lattice:attributes>
+                </spirit:vendorExtensions>
+                <spirit:internalPortReference spirit:portRef="hdoutn" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_hdoutn"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_hdoutp</spirit:name>
+                <spirit:displayName>sgmii_ecp5_hdoutp</spirit:displayName>
+                <spirit:vendorExtensions>
+                    <lattice:attributes>
+                        <lattice:attribute lattice:name="export">sys_yes</lattice:attribute>
+                    </lattice:attributes>
+                </spirit:vendorExtensions>
+                <spirit:internalPortReference spirit:portRef="hdoutp" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_hdoutp"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_lsm_status_s</spirit:name>
+                <spirit:displayName>sgmii_ecp5_lsm_status_s</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="lsm_status_s" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_lsm_status_s"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_pll_lol</spirit:name>
+                <spirit:displayName>sgmii_ecp5_pll_lol</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="pll_lol" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_pll_lol"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_pll_refclki</spirit:name>
+                <spirit:displayName>sgmii_ecp5_pll_refclki</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="pll_refclki" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_pll_refclki"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rsl_disable</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rsl_disable</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rsl_disable" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rsl_disable"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rsl_rst</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rsl_rst</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rsl_rst" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rsl_rst"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rsl_rx_rdy</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rsl_rx_rdy</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rsl_rx_rdy" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rsl_rx_rdy"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rsl_tx_rdy</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rsl_tx_rdy</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rsl_tx_rdy" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rsl_tx_rdy"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rst_dual_c</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rst_dual_c</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rst_dual_c" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rst_dual_c"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rx_cdr_lol_s</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rx_cdr_lol_s</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rx_cdr_lol_s" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rx_cdr_lol_s"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rx_los_low_s</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rx_los_low_s</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rx_los_low_s" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rx_los_low_s"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rx_pcs_rst_c</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rx_pcs_rst_c</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rx_pcs_rst_c" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rx_pcs_rst_c"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rx_pwrup_c</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rx_pwrup_c</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rx_pwrup_c" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rx_pwrup_c"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rx_serdes_rst_c</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rx_serdes_rst_c</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rx_serdes_rst_c" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rx_serdes_rst_c"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rxrefclk</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rxrefclk</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rxrefclk" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rxrefclk"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_en</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_en</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_en" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_en"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_en_dual</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_en_dual</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_en_dual" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_en_dual"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_int</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_int</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_int" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_int"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_rd</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_rd</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_rd" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_rd"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_sel</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_sel</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_sel" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_sel"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_sel_dual</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_sel_dual</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_sel_dual" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_sel_dual"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_wrn</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_wrn</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_wrn" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_wrn"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_serdes_pdb</spirit:name>
+                <spirit:displayName>sgmii_ecp5_serdes_pdb</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="serdes_pdb" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_serdes_pdb"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_serdes_rst_dual_c</spirit:name>
+                <spirit:displayName>sgmii_ecp5_serdes_rst_dual_c</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="serdes_rst_dual_c" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_serdes_rst_dual_c"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_signal_detect_c</spirit:name>
+                <spirit:displayName>sgmii_ecp5_signal_detect_c</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="signal_detect_c" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_signal_detect_c"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_tx_pclk</spirit:name>
+                <spirit:displayName>sgmii_ecp5_tx_pclk</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="tx_pclk" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_tx_pclk"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_tx_pcs_rst_c</spirit:name>
+                <spirit:displayName>sgmii_ecp5_tx_pcs_rst_c</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="tx_pcs_rst_c" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_tx_pcs_rst_c"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_tx_pwrup_c</spirit:name>
+                <spirit:displayName>sgmii_ecp5_tx_pwrup_c</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="tx_pwrup_c" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_tx_pwrup_c"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_tx_serdes_rst_c</spirit:name>
+                <spirit:displayName>sgmii_ecp5_tx_serdes_rst_c</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="tx_serdes_rst_c" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_tx_serdes_rst_c"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_txi_clk</spirit:name>
+                <spirit:displayName>sgmii_ecp5_txi_clk</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="txi_clk" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_txi_clk"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rx_cv_err</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rx_cv_err</spirit:displayName>
+                <spirit:internalPortReference spirit:right="0" spirit:portRef="rx_cv_err" spirit:componentRef="sgmii_ecp5" spirit:left="0"/>
+                <spirit:externalPortReference spirit:right="0" spirit:portRef="sgmii_ecp5_rx_cv_err" spirit:left="0"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rx_cv_err[0]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rx_cv_err[0]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rx_cv_err[0]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rx_cv_err[0]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rx_disp_err</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rx_disp_err</spirit:displayName>
+                <spirit:internalPortReference spirit:right="0" spirit:portRef="rx_disp_err" spirit:componentRef="sgmii_ecp5" spirit:left="0"/>
+                <spirit:externalPortReference spirit:right="0" spirit:portRef="sgmii_ecp5_rx_disp_err" spirit:left="0"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rx_disp_err[0]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rx_disp_err[0]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rx_disp_err[0]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rx_disp_err[0]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rx_k</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rx_k</spirit:displayName>
+                <spirit:internalPortReference spirit:right="0" spirit:portRef="rx_k" spirit:componentRef="sgmii_ecp5" spirit:left="0"/>
+                <spirit:externalPortReference spirit:right="0" spirit:portRef="sgmii_ecp5_rx_k" spirit:left="0"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rx_k[0]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rx_k[0]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rx_k[0]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rx_k[0]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rxdata</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rxdata</spirit:displayName>
+                <spirit:internalPortReference spirit:right="0" spirit:portRef="rxdata" spirit:componentRef="sgmii_ecp5" spirit:left="7"/>
+                <spirit:externalPortReference spirit:right="0" spirit:portRef="sgmii_ecp5_rxdata" spirit:left="7"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rxdata[0]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rxdata[0]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rxdata[0]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rxdata[0]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rxdata[1]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rxdata[1]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rxdata[1]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rxdata[1]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rxdata[2]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rxdata[2]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rxdata[2]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rxdata[2]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rxdata[3]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rxdata[3]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rxdata[3]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rxdata[3]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rxdata[4]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rxdata[4]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rxdata[4]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rxdata[4]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rxdata[5]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rxdata[5]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rxdata[5]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rxdata[5]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rxdata[6]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rxdata[6]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rxdata[6]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rxdata[6]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_rxdata[7]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_rxdata[7]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rxdata[7]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_rxdata[7]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_addr</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_addr</spirit:displayName>
+                <spirit:internalPortReference spirit:right="0" spirit:portRef="sci_addr" spirit:componentRef="sgmii_ecp5" spirit:left="5"/>
+                <spirit:externalPortReference spirit:right="0" spirit:portRef="sgmii_ecp5_sci_addr" spirit:left="5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_addr[0]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_addr[0]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_addr[0]"/>
+                <spirit:internalPortReference spirit:portRef="sci_addr[0]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_addr[1]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_addr[1]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_addr[1]"/>
+                <spirit:internalPortReference spirit:portRef="sci_addr[1]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_addr[2]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_addr[2]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_addr[2]"/>
+                <spirit:internalPortReference spirit:portRef="sci_addr[2]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_addr[3]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_addr[3]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_addr[3]"/>
+                <spirit:internalPortReference spirit:portRef="sci_addr[3]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_addr[4]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_addr[4]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_addr[4]"/>
+                <spirit:internalPortReference spirit:portRef="sci_addr[4]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_addr[5]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_addr[5]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_addr[5]"/>
+                <spirit:internalPortReference spirit:portRef="sci_addr[5]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_rddata</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_rddata</spirit:displayName>
+                <spirit:internalPortReference spirit:right="0" spirit:portRef="sci_rddata" spirit:componentRef="sgmii_ecp5" spirit:left="7"/>
+                <spirit:externalPortReference spirit:right="0" spirit:portRef="sgmii_ecp5_sci_rddata" spirit:left="7"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_rddata[0]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_rddata[0]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_rddata[0]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_rddata[0]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_rddata[1]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_rddata[1]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_rddata[1]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_rddata[1]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_rddata[2]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_rddata[2]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_rddata[2]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_rddata[2]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_rddata[3]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_rddata[3]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_rddata[3]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_rddata[3]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_rddata[4]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_rddata[4]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_rddata[4]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_rddata[4]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_rddata[5]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_rddata[5]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_rddata[5]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_rddata[5]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_rddata[6]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_rddata[6]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_rddata[6]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_rddata[6]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_rddata[7]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_rddata[7]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_rddata[7]" spirit:componentRef="sgmii_ecp5"/>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_rddata[7]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_wrdata</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_wrdata</spirit:displayName>
+                <spirit:internalPortReference spirit:right="0" spirit:portRef="sci_wrdata" spirit:componentRef="sgmii_ecp5" spirit:left="7"/>
+                <spirit:externalPortReference spirit:right="0" spirit:portRef="sgmii_ecp5_sci_wrdata" spirit:left="7"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_wrdata[0]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_wrdata[0]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_wrdata[0]"/>
+                <spirit:internalPortReference spirit:portRef="sci_wrdata[0]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_wrdata[1]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_wrdata[1]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_wrdata[1]"/>
+                <spirit:internalPortReference spirit:portRef="sci_wrdata[1]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_wrdata[2]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_wrdata[2]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_wrdata[2]"/>
+                <spirit:internalPortReference spirit:portRef="sci_wrdata[2]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_wrdata[3]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_wrdata[3]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_wrdata[3]"/>
+                <spirit:internalPortReference spirit:portRef="sci_wrdata[3]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_wrdata[4]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_wrdata[4]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_wrdata[4]"/>
+                <spirit:internalPortReference spirit:portRef="sci_wrdata[4]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_wrdata[5]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_wrdata[5]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_wrdata[5]"/>
+                <spirit:internalPortReference spirit:portRef="sci_wrdata[5]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_wrdata[6]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_wrdata[6]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_wrdata[6]"/>
+                <spirit:internalPortReference spirit:portRef="sci_wrdata[6]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_sci_wrdata[7]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_sci_wrdata[7]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_sci_wrdata[7]"/>
+                <spirit:internalPortReference spirit:portRef="sci_wrdata[7]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_tx_disp_correct</spirit:name>
+                <spirit:displayName>sgmii_ecp5_tx_disp_correct</spirit:displayName>
+                <spirit:internalPortReference spirit:right="0" spirit:portRef="tx_disp_correct" spirit:componentRef="sgmii_ecp5" spirit:left="0"/>
+                <spirit:externalPortReference spirit:right="0" spirit:portRef="sgmii_ecp5_tx_disp_correct" spirit:left="0"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_tx_disp_correct[0]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_tx_disp_correct[0]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_tx_disp_correct[0]"/>
+                <spirit:internalPortReference spirit:portRef="tx_disp_correct[0]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_tx_k</spirit:name>
+                <spirit:displayName>sgmii_ecp5_tx_k</spirit:displayName>
+                <spirit:internalPortReference spirit:right="0" spirit:portRef="tx_k" spirit:componentRef="sgmii_ecp5" spirit:left="0"/>
+                <spirit:externalPortReference spirit:right="0" spirit:portRef="sgmii_ecp5_tx_k" spirit:left="0"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_tx_k[0]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_tx_k[0]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_tx_k[0]"/>
+                <spirit:internalPortReference spirit:portRef="tx_k[0]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_txdata</spirit:name>
+                <spirit:displayName>sgmii_ecp5_txdata</spirit:displayName>
+                <spirit:internalPortReference spirit:right="0" spirit:portRef="txdata" spirit:componentRef="sgmii_ecp5" spirit:left="7"/>
+                <spirit:externalPortReference spirit:right="0" spirit:portRef="sgmii_ecp5_txdata" spirit:left="7"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_txdata[0]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_txdata[0]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_txdata[0]"/>
+                <spirit:internalPortReference spirit:portRef="txdata[0]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_txdata[1]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_txdata[1]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_txdata[1]"/>
+                <spirit:internalPortReference spirit:portRef="txdata[1]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_txdata[2]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_txdata[2]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_txdata[2]"/>
+                <spirit:internalPortReference spirit:portRef="txdata[2]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_txdata[3]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_txdata[3]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_txdata[3]"/>
+                <spirit:internalPortReference spirit:portRef="txdata[3]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_txdata[4]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_txdata[4]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_txdata[4]"/>
+                <spirit:internalPortReference spirit:portRef="txdata[4]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_txdata[5]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_txdata[5]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_txdata[5]"/>
+                <spirit:internalPortReference spirit:portRef="txdata[5]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_txdata[6]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_txdata[6]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_txdata[6]"/>
+                <spirit:internalPortReference spirit:portRef="txdata[6]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_txdata[7]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_txdata[7]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_txdata[7]"/>
+                <spirit:internalPortReference spirit:portRef="txdata[7]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_xmit</spirit:name>
+                <spirit:displayName>sgmii_ecp5_xmit</spirit:displayName>
+                <spirit:internalPortReference spirit:right="0" spirit:portRef="xmit" spirit:componentRef="sgmii_ecp5" spirit:left="0"/>
+                <spirit:externalPortReference spirit:right="0" spirit:portRef="sgmii_ecp5_xmit" spirit:left="0"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>sgmii_ecp5_xmit[0]</spirit:name>
+                <spirit:displayName>sgmii_ecp5_xmit[0]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="sgmii_ecp5_xmit[0]"/>
+                <spirit:internalPortReference spirit:portRef="xmit[0]" spirit:componentRef="sgmii_ecp5"/>
+            </spirit:adHocConnection>
+        </spirit:adHocConnections>
+    </spirit:design>
+</lattice:project>

diff --git a/gbe/cores/test_gbepcs/test_gbepcs.vhd b/gbe/cores/test_gbepcs/test_gbepcs.vhd
new file mode 100644 (file)
index 0000000..6f75c97
--- /dev/null
+++ b/gbe/cores/test_gbepcs/test_gbepcs.vhd
@@ -0,0 +1,167 @@
+
+
+--
+-- Verific VHDL Description of module test_gbepcs
+--
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+entity test_gbepcs is
+    port (sgmii_ecp5_rx_cv_err: out std_logic_vector(0 downto 0);
+        sgmii_ecp5_rx_disp_err: out std_logic_vector(0 downto 0);
+        sgmii_ecp5_rx_k: out std_logic_vector(0 downto 0);
+        sgmii_ecp5_rxdata: out std_logic_vector(7 downto 0);
+        sgmii_ecp5_sci_addr: in std_logic_vector(5 downto 0);
+        sgmii_ecp5_sci_rddata: out std_logic_vector(7 downto 0);
+        sgmii_ecp5_sci_wrdata: in std_logic_vector(7 downto 0);
+        sgmii_ecp5_tx_disp_correct: in std_logic_vector(0 downto 0);
+        sgmii_ecp5_tx_k: in std_logic_vector(0 downto 0);
+        sgmii_ecp5_txdata: in std_logic_vector(7 downto 0);
+        sgmii_ecp5_xmit: in std_logic_vector(0 downto 0);
+        sgmii_ecp5_ctc_del_s: out std_logic;
+        sgmii_ecp5_ctc_ins_s: out std_logic;
+        sgmii_ecp5_ctc_orun_s: out std_logic;
+        sgmii_ecp5_ctc_urun_s: out std_logic;
+        sgmii_ecp5_cyawstn: in std_logic;
+        sgmii_ecp5_hdinn: in std_logic;
+        sgmii_ecp5_hdinp: in std_logic;
+        sgmii_ecp5_hdoutn: out std_logic;
+        sgmii_ecp5_hdoutp: out std_logic;
+        sgmii_ecp5_lsm_status_s: out std_logic;
+        sgmii_ecp5_pll_lol: out std_logic;
+        sgmii_ecp5_pll_refclki: in std_logic;
+        sgmii_ecp5_rsl_disable: in std_logic;
+        sgmii_ecp5_rsl_rst: in std_logic;
+        sgmii_ecp5_rsl_rx_rdy: out std_logic;
+        sgmii_ecp5_rsl_tx_rdy: out std_logic;
+        sgmii_ecp5_rst_dual_c: in std_logic;
+        sgmii_ecp5_rx_cdr_lol_s: out std_logic;
+        sgmii_ecp5_rx_los_low_s: out std_logic;
+        sgmii_ecp5_rx_pcs_rst_c: in std_logic;
+        sgmii_ecp5_rx_pwrup_c: in std_logic;
+        sgmii_ecp5_rx_serdes_rst_c: in std_logic;
+        sgmii_ecp5_rxrefclk: in std_logic;
+        sgmii_ecp5_sci_en: in std_logic;
+        sgmii_ecp5_sci_en_dual: in std_logic;
+        sgmii_ecp5_sci_int: out std_logic;
+        sgmii_ecp5_sci_rd: in std_logic;
+        sgmii_ecp5_sci_sel: in std_logic;
+        sgmii_ecp5_sci_sel_dual: in std_logic;
+        sgmii_ecp5_sci_wrn: in std_logic;
+        sgmii_ecp5_serdes_pdb: in std_logic;
+        sgmii_ecp5_serdes_rst_dual_c: in std_logic;
+        sgmii_ecp5_signal_detect_c: in std_logic;
+        sgmii_ecp5_tx_pclk: out std_logic;
+        sgmii_ecp5_tx_pcs_rst_c: in std_logic;
+        sgmii_ecp5_tx_pwrup_c: in std_logic;
+        sgmii_ecp5_tx_serdes_rst_c: in std_logic;
+        sgmii_ecp5_txi_clk: in std_logic
+    );
+    
+end entity test_gbepcs; -- sbp_module=true 
+
+architecture test_gbepcs of test_gbepcs is 
+    component sgmii_ecp5 is
+        port (rx_cv_err: out std_logic_vector(0 downto 0);
+            rx_disp_err: out std_logic_vector(0 downto 0);
+            rx_k: out std_logic_vector(0 downto 0);
+            rxdata: out std_logic_vector(7 downto 0);
+            sci_addr: in std_logic_vector(5 downto 0);
+            sci_rddata: out std_logic_vector(7 downto 0);
+            sci_wrdata: in std_logic_vector(7 downto 0);
+            tx_disp_correct: in std_logic_vector(0 downto 0);
+            tx_k: in std_logic_vector(0 downto 0);
+            txdata: in std_logic_vector(7 downto 0);
+            xmit: in std_logic_vector(0 downto 0);
+            ctc_del_s: out std_logic;
+            ctc_ins_s: out std_logic;
+            ctc_orun_s: out std_logic;
+            ctc_urun_s: out std_logic;
+            cyawstn: in std_logic;
+            hdinn: in std_logic;
+            hdinp: in std_logic;
+            hdoutn: out std_logic;
+            hdoutp: out std_logic;
+            lsm_status_s: out std_logic;
+            pll_lol: out std_logic;
+            pll_refclki: in std_logic;
+            rsl_disable: in std_logic;
+            rsl_rst: in std_logic;
+            rsl_rx_rdy: out std_logic;
+            rsl_tx_rdy: out std_logic;
+            rst_dual_c: in std_logic;
+            rx_cdr_lol_s: out std_logic;
+            rx_los_low_s: out std_logic;
+            rx_pcs_rst_c: in std_logic;
+            rx_pwrup_c: in std_logic;
+            rx_serdes_rst_c: in std_logic;
+            rxrefclk: in std_logic;
+            sci_en: in std_logic;
+            sci_en_dual: in std_logic;
+            sci_int: out std_logic;
+            sci_rd: in std_logic;
+            sci_sel: in std_logic;
+            sci_sel_dual: in std_logic;
+            sci_wrn: in std_logic;
+            serdes_pdb: in std_logic;
+            serdes_rst_dual_c: in std_logic;
+            signal_detect_c: in std_logic;
+            sli_rst: in std_logic;
+            tx_pclk: out std_logic;
+            tx_pcs_rst_c: in std_logic;
+            tx_pwrup_c: in std_logic;
+            tx_serdes_rst_c: in std_logic;
+            txi_clk: in std_logic
+        );
+        
+    end component sgmii_ecp5; -- not_need_bbox=true 
+    
+    
+    signal sli_rst_wire0,gnd : std_logic; 
+begin
+    sli_rst_wire0 <= sgmii_ecp5_serdes_rst_dual_c OR  sgmii_ecp5_tx_serdes_rst_c OR  (NOT sgmii_ecp5_serdes_pdb) OR  (NOT sgmii_ecp5_tx_pwrup_c);
+    sgmii_ecp5_inst: component sgmii_ecp5 port map (rx_cv_err(0)=>sgmii_ecp5_rx_cv_err(0),
+            rx_disp_err(0)=>sgmii_ecp5_rx_disp_err(0),rx_k(0)=>sgmii_ecp5_rx_k(0),
+            rxdata(7)=>sgmii_ecp5_rxdata(7),rxdata(6)=>sgmii_ecp5_rxdata(6),
+            rxdata(5)=>sgmii_ecp5_rxdata(5),rxdata(4)=>sgmii_ecp5_rxdata(4),
+            rxdata(3)=>sgmii_ecp5_rxdata(3),rxdata(2)=>sgmii_ecp5_rxdata(2),
+            rxdata(1)=>sgmii_ecp5_rxdata(1),rxdata(0)=>sgmii_ecp5_rxdata(0),
+            sci_addr(5)=>sgmii_ecp5_sci_addr(5),sci_addr(4)=>sgmii_ecp5_sci_addr(4),
+            sci_addr(3)=>sgmii_ecp5_sci_addr(3),sci_addr(2)=>sgmii_ecp5_sci_addr(2),
+            sci_addr(1)=>sgmii_ecp5_sci_addr(1),sci_addr(0)=>sgmii_ecp5_sci_addr(0),
+            sci_rddata(7)=>sgmii_ecp5_sci_rddata(7),sci_rddata(6)=>sgmii_ecp5_sci_rddata(6),
+            sci_rddata(5)=>sgmii_ecp5_sci_rddata(5),sci_rddata(4)=>sgmii_ecp5_sci_rddata(4),
+            sci_rddata(3)=>sgmii_ecp5_sci_rddata(3),sci_rddata(2)=>sgmii_ecp5_sci_rddata(2),
+            sci_rddata(1)=>sgmii_ecp5_sci_rddata(1),sci_rddata(0)=>sgmii_ecp5_sci_rddata(0),
+            sci_wrdata(7)=>sgmii_ecp5_sci_wrdata(7),sci_wrdata(6)=>sgmii_ecp5_sci_wrdata(6),
+            sci_wrdata(5)=>sgmii_ecp5_sci_wrdata(5),sci_wrdata(4)=>sgmii_ecp5_sci_wrdata(4),
+            sci_wrdata(3)=>sgmii_ecp5_sci_wrdata(3),sci_wrdata(2)=>sgmii_ecp5_sci_wrdata(2),
+            sci_wrdata(1)=>sgmii_ecp5_sci_wrdata(1),sci_wrdata(0)=>sgmii_ecp5_sci_wrdata(0),
+            tx_disp_correct(0)=>sgmii_ecp5_tx_disp_correct(0),tx_k(0)=>sgmii_ecp5_tx_k(0),
+            txdata(7)=>sgmii_ecp5_txdata(7),txdata(6)=>sgmii_ecp5_txdata(6),
+            txdata(5)=>sgmii_ecp5_txdata(5),txdata(4)=>sgmii_ecp5_txdata(4),
+            txdata(3)=>sgmii_ecp5_txdata(3),txdata(2)=>sgmii_ecp5_txdata(2),
+            txdata(1)=>sgmii_ecp5_txdata(1),txdata(0)=>sgmii_ecp5_txdata(0),
+            xmit(0)=>sgmii_ecp5_xmit(0),ctc_del_s=>sgmii_ecp5_ctc_del_s,ctc_ins_s=>sgmii_ecp5_ctc_ins_s,
+            ctc_orun_s=>sgmii_ecp5_ctc_orun_s,ctc_urun_s=>sgmii_ecp5_ctc_urun_s,
+            cyawstn=>sgmii_ecp5_cyawstn,hdinn=>sgmii_ecp5_hdinn,hdinp=>sgmii_ecp5_hdinp,
+            hdoutn=>sgmii_ecp5_hdoutn,hdoutp=>sgmii_ecp5_hdoutp,lsm_status_s=>sgmii_ecp5_lsm_status_s,
+            pll_lol=>sgmii_ecp5_pll_lol,pll_refclki=>sgmii_ecp5_pll_refclki,
+            rsl_disable=>sgmii_ecp5_rsl_disable,rsl_rst=>sgmii_ecp5_rsl_rst,
+            rsl_rx_rdy=>sgmii_ecp5_rsl_rx_rdy,rsl_tx_rdy=>sgmii_ecp5_rsl_tx_rdy,
+            rst_dual_c=>sgmii_ecp5_rst_dual_c,rx_cdr_lol_s=>sgmii_ecp5_rx_cdr_lol_s,
+            rx_los_low_s=>sgmii_ecp5_rx_los_low_s,rx_pcs_rst_c=>sgmii_ecp5_rx_pcs_rst_c,
+            rx_pwrup_c=>sgmii_ecp5_rx_pwrup_c,rx_serdes_rst_c=>sgmii_ecp5_rx_serdes_rst_c,
+            rxrefclk=>sgmii_ecp5_rxrefclk,sci_en=>sgmii_ecp5_sci_en,sci_en_dual=>sgmii_ecp5_sci_en_dual,
+            sci_int=>sgmii_ecp5_sci_int,sci_rd=>sgmii_ecp5_sci_rd,sci_sel=>sgmii_ecp5_sci_sel,
+            sci_sel_dual=>sgmii_ecp5_sci_sel_dual,sci_wrn=>sgmii_ecp5_sci_wrn,
+            serdes_pdb=>sgmii_ecp5_serdes_pdb,serdes_rst_dual_c=>sgmii_ecp5_serdes_rst_dual_c,
+            signal_detect_c=>sgmii_ecp5_signal_detect_c,sli_rst=>sli_rst_wire0,
+            tx_pclk=>sgmii_ecp5_tx_pclk,tx_pcs_rst_c=>sgmii_ecp5_tx_pcs_rst_c,
+            tx_pwrup_c=>sgmii_ecp5_tx_pwrup_c,tx_serdes_rst_c=>sgmii_ecp5_tx_serdes_rst_c,
+            txi_clk=>sgmii_ecp5_txi_clk);
+    gnd <= '0' ;
+    
+end architecture test_gbepcs; -- sbp_module=true 
+

diff --git a/gbe/cores/test_gbepcs/test_gbepcs_tmpl.v b/gbe/cores/test_gbepcs/test_gbepcs_tmpl.v
new file mode 100644 (file)
index 0000000..89088e9
--- /dev/null
+++ b/gbe/cores/test_gbepcs/test_gbepcs_tmpl.v
@@ -0,0 +1,19 @@
+//Verilog instantiation template
+
+test_gbepcs _inst (.sgmii_ecp5_rx_cv_err(), .sgmii_ecp5_rx_disp_err(), .sgmii_ecp5_rx_k(), 
+            .sgmii_ecp5_rxdata(), .sgmii_ecp5_sci_addr(), .sgmii_ecp5_sci_rddata(), 
+            .sgmii_ecp5_sci_wrdata(), .sgmii_ecp5_tx_disp_correct(), .sgmii_ecp5_tx_k(), 
+            .sgmii_ecp5_txdata(), .sgmii_ecp5_xmit(), .sgmii_ecp5_ctc_del_s(), 
+            .sgmii_ecp5_ctc_ins_s(), .sgmii_ecp5_ctc_orun_s(), .sgmii_ecp5_ctc_urun_s(), 
+            .sgmii_ecp5_cyawstn(), .sgmii_ecp5_hdinn(), .sgmii_ecp5_hdinp(), 
+            .sgmii_ecp5_hdoutn(), .sgmii_ecp5_hdoutp(), .sgmii_ecp5_lsm_status_s(), 
+            .sgmii_ecp5_pll_lol(), .sgmii_ecp5_pll_refclki(), .sgmii_ecp5_rsl_disable(), 
+            .sgmii_ecp5_rsl_rst(), .sgmii_ecp5_rsl_rx_rdy(), .sgmii_ecp5_rsl_tx_rdy(), 
+            .sgmii_ecp5_rst_dual_c(), .sgmii_ecp5_rx_cdr_lol_s(), .sgmii_ecp5_rx_los_low_s(), 
+            .sgmii_ecp5_rx_pcs_rst_c(), .sgmii_ecp5_rx_pwrup_c(), .sgmii_ecp5_rx_serdes_rst_c(), 
+            .sgmii_ecp5_rxrefclk(), .sgmii_ecp5_sci_en(), .sgmii_ecp5_sci_en_dual(), 
+            .sgmii_ecp5_sci_int(), .sgmii_ecp5_sci_rd(), .sgmii_ecp5_sci_sel(), 
+            .sgmii_ecp5_sci_sel_dual(), .sgmii_ecp5_sci_wrn(), .sgmii_ecp5_serdes_pdb(), 
+            .sgmii_ecp5_serdes_rst_dual_c(), .sgmii_ecp5_signal_detect_c(), 
+            .sgmii_ecp5_tx_pclk(), .sgmii_ecp5_tx_pcs_rst_c(), .sgmii_ecp5_tx_pwrup_c(), 
+            .sgmii_ecp5_tx_serdes_rst_c(), .sgmii_ecp5_txi_clk());
\ No newline at end of file

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_0.sbx b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_0.sbx
new file mode 100644 (file)
index 0000000..8a2304e
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_0.sbx
@@ -0,0 +1,2096 @@
+<!DOCTYPE serdes_sync_0>
+<lattice:project>
+    <spirit:component>
+        <spirit:vendor>LATTICE</spirit:vendor>
+        <spirit:library>LOCAL</spirit:library>
+        <spirit:name>serdes_sync_0</spirit:name>
+        <spirit:version>1.0</spirit:version>
+        <spirit:fileSets>
+            <spirit:fileset>
+                <spirit:name>Diamond_Synthesis</spirit:name>
+                <spirit:group>synthesis</spirit:group>
+                <spirit:file>
+                    <spirit:name>./serdes_sync_0.vhd</spirit:name>
+                    <spirit:fileType>vhdlSource</spirit:fileType>
+                </spirit:file>
+            </spirit:fileset>
+            <spirit:fileset>
+                <spirit:name>Diamond_Simulation</spirit:name>
+                <spirit:group>simulation</spirit:group>
+                <spirit:file>
+                    <spirit:name>./serdes_sync_0.vhd</spirit:name>
+                    <spirit:fileType>vhdlSource</spirit:fileType>
+                </spirit:file>
+            </spirit:fileset>
+        </spirit:fileSets>
+        <spirit:componentGenerators/>
+        <spirit:model>
+            <spirit:views/>
+            <spirit:ports>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_cyawstn</spirit:name>
+                    <spirit:displayName>serdes_sync_1_cyawstn</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.cyawstn</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_hdinn</spirit:name>
+                    <spirit:displayName>serdes_sync_1_hdinn</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.hdinn</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_hdinp</spirit:name>
+                    <spirit:displayName>serdes_sync_1_hdinp</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.hdinp</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_hdoutn</spirit:name>
+                    <spirit:displayName>serdes_sync_1_hdoutn</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.hdoutn</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_hdoutp</spirit:name>
+                    <spirit:displayName>serdes_sync_1_hdoutp</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.hdoutp</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_lsm_status_s</spirit:name>
+                    <spirit:displayName>serdes_sync_1_lsm_status_s</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.lsm_status_s</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_pll_lol</spirit:name>
+                    <spirit:displayName>serdes_sync_1_pll_lol</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.pll_lol</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_pll_refclki</spirit:name>
+                    <spirit:displayName>serdes_sync_1_pll_refclki</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.pll_refclki</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_rsl_disable</spirit:name>
+                    <spirit:displayName>serdes_sync_1_rsl_disable</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.rsl_disable</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_rsl_rst</spirit:name>
+                    <spirit:displayName>serdes_sync_1_rsl_rst</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.rsl_rst</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_rsl_rx_rdy</spirit:name>
+                    <spirit:displayName>serdes_sync_1_rsl_rx_rdy</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.rsl_rx_rdy</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_rsl_tx_rdy</spirit:name>
+                    <spirit:displayName>serdes_sync_1_rsl_tx_rdy</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.rsl_tx_rdy</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_rst_dual_c</spirit:name>
+                    <spirit:displayName>serdes_sync_1_rst_dual_c</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.rst_dual_c</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_rx_cdr_lol_s</spirit:name>
+                    <spirit:displayName>serdes_sync_1_rx_cdr_lol_s</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.rx_cdr_lol_s</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_rx_los_low_s</spirit:name>
+                    <spirit:displayName>serdes_sync_1_rx_los_low_s</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.rx_los_low_s</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_rx_pclk</spirit:name>
+                    <spirit:displayName>serdes_sync_1_rx_pclk</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.rx_pclk</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_rx_pcs_rst_c</spirit:name>
+                    <spirit:displayName>serdes_sync_1_rx_pcs_rst_c</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.rx_pcs_rst_c</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_rx_pwrup_c</spirit:name>
+                    <spirit:displayName>serdes_sync_1_rx_pwrup_c</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.rx_pwrup_c</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_rx_serdes_rst_c</spirit:name>
+                    <spirit:displayName>serdes_sync_1_rx_serdes_rst_c</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.rx_serdes_rst_c</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_rxrefclk</spirit:name>
+                    <spirit:displayName>serdes_sync_1_rxrefclk</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.rxrefclk</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_sci_en</spirit:name>
+                    <spirit:displayName>serdes_sync_1_sci_en</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.sci_en</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_sci_en_dual</spirit:name>
+                    <spirit:displayName>serdes_sync_1_sci_en_dual</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.sci_en_dual</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_sci_int</spirit:name>
+                    <spirit:displayName>serdes_sync_1_sci_int</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.sci_int</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_sci_rd</spirit:name>
+                    <spirit:displayName>serdes_sync_1_sci_rd</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.sci_rd</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_sci_sel</spirit:name>
+                    <spirit:displayName>serdes_sync_1_sci_sel</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.sci_sel</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_sci_sel_dual</spirit:name>
+                    <spirit:displayName>serdes_sync_1_sci_sel_dual</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.sci_sel_dual</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_sci_wrn</spirit:name>
+                    <spirit:displayName>serdes_sync_1_sci_wrn</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.sci_wrn</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_serdes_pdb</spirit:name>
+                    <spirit:displayName>serdes_sync_1_serdes_pdb</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.serdes_pdb</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_serdes_rst_dual_c</spirit:name>
+                    <spirit:displayName>serdes_sync_1_serdes_rst_dual_c</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.serdes_rst_dual_c</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_signal_detect_c</spirit:name>
+                    <spirit:displayName>serdes_sync_1_signal_detect_c</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.signal_detect_c</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_tx_idle_c</spirit:name>
+                    <spirit:displayName>serdes_sync_1_tx_idle_c</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.tx_idle_c</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_tx_pclk</spirit:name>
+                    <spirit:displayName>serdes_sync_1_tx_pclk</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.tx_pclk</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_tx_pcs_rst_c</spirit:name>
+                    <spirit:displayName>serdes_sync_1_tx_pcs_rst_c</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.tx_pcs_rst_c</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_tx_pwrup_c</spirit:name>
+                    <spirit:displayName>serdes_sync_1_tx_pwrup_c</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.tx_pwrup_c</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_tx_serdes_rst_c</spirit:name>
+                    <spirit:displayName>serdes_sync_1_tx_serdes_rst_c</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.tx_serdes_rst_c</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_rx_cv_err</spirit:name>
+                    <spirit:displayName>serdes_sync_1_rx_cv_err</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                        <spirit:vector>
+                            <spirit:left>0</spirit:left>
+                            <spirit:right>0</spirit:right>
+                        </spirit:vector>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.rx_cv_err</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_rx_disp_err</spirit:name>
+                    <spirit:displayName>serdes_sync_1_rx_disp_err</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                        <spirit:vector>
+                            <spirit:left>0</spirit:left>
+                            <spirit:right>0</spirit:right>
+                        </spirit:vector>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.rx_disp_err</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_rx_k</spirit:name>
+                    <spirit:displayName>serdes_sync_1_rx_k</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                        <spirit:vector>
+                            <spirit:left>0</spirit:left>
+                            <spirit:right>0</spirit:right>
+                        </spirit:vector>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.rx_k</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_rxdata</spirit:name>
+                    <spirit:displayName>serdes_sync_1_rxdata</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                        <spirit:vector>
+                            <spirit:left>7</spirit:left>
+                            <spirit:right>0</spirit:right>
+                        </spirit:vector>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.rxdata</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_sci_addr</spirit:name>
+                    <spirit:displayName>serdes_sync_1_sci_addr</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                        <spirit:vector>
+                            <spirit:left>5</spirit:left>
+                            <spirit:right>0</spirit:right>
+                        </spirit:vector>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.sci_addr</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_sci_rddata</spirit:name>
+                    <spirit:displayName>serdes_sync_1_sci_rddata</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>out</spirit:direction>
+                        <spirit:vector>
+                            <spirit:left>7</spirit:left>
+                            <spirit:right>0</spirit:right>
+                        </spirit:vector>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.sci_rddata</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_sci_wrdata</spirit:name>
+                    <spirit:displayName>serdes_sync_1_sci_wrdata</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                        <spirit:vector>
+                            <spirit:left>7</spirit:left>
+                            <spirit:right>0</spirit:right>
+                        </spirit:vector>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.sci_wrdata</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_tx_disp_sel</spirit:name>
+                    <spirit:displayName>serdes_sync_1_tx_disp_sel</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                        <spirit:vector>
+                            <spirit:left>0</spirit:left>
+                            <spirit:right>0</spirit:right>
+                        </spirit:vector>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.tx_disp_sel</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_tx_force_disp</spirit:name>
+                    <spirit:displayName>serdes_sync_1_tx_force_disp</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                        <spirit:vector>
+                            <spirit:left>0</spirit:left>
+                            <spirit:right>0</spirit:right>
+                        </spirit:vector>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.tx_force_disp</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_tx_k</spirit:name>
+                    <spirit:displayName>serdes_sync_1_tx_k</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                        <spirit:vector>
+                            <spirit:left>0</spirit:left>
+                            <spirit:right>0</spirit:right>
+                        </spirit:vector>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.tx_k</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+                <spirit:port>
+                    <spirit:name>serdes_sync_1_txdata</spirit:name>
+                    <spirit:displayName>serdes_sync_1_txdata</spirit:displayName>
+                    <spirit:wire>
+                        <spirit:direction>in</spirit:direction>
+                        <spirit:vector>
+                            <spirit:left>7</spirit:left>
+                            <spirit:right>0</spirit:right>
+                        </spirit:vector>
+                    </spirit:wire>
+                    <spirit:vendorExtensions>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="exportFrom">serdes_sync_1.txdata</lattice:attribute>
+                        </lattice:attributes>
+                    </spirit:vendorExtensions>
+                </spirit:port>
+            </spirit:ports>
+        </spirit:model>
+        <spirit:vendorExtensions>
+            <lattice:device>LFE5UM-85F-8BG756C</lattice:device>
+            <lattice:synthesis>synplify</lattice:synthesis>
+            <lattice:date>2019-05-10.09:27:16 AM</lattice:date>
+            <lattice:modified>2019-05-10.11:03:41 AM</lattice:modified>
+            <lattice:diamond>3.10.3.144</lattice:diamond>
+            <lattice:language>VHDL</lattice:language>
+            <lattice:attributes>
+                <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+                <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+                <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+                <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+                <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+            </lattice:attributes>
+            <lattice:elements/>
+            <lattice:lpc/>
+            <lattice:groups/>
+        </spirit:vendorExtensions>
+    </spirit:component>
+    <spirit:design>
+        <spirit:vendor>LATTICE</spirit:vendor>
+        <spirit:library>LOCAL</spirit:library>
+        <spirit:name>serdes_sync_0</spirit:name>
+        <spirit:version>1.0</spirit:version>
+        <spirit:componentInstances>
+            <spirit:componentInstance>
+                <spirit:instanceName>serdes_sync_1</spirit:instanceName>
+                <spirit:componentRef>
+                    <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
+                    <spirit:library>LEGACY</spirit:library>
+                    <spirit:name>PCS</spirit:name>
+                    <spirit:version>8.2</spirit:version>
+                    <spirit:fileSets>
+                        <spirit:fileset>
+                            <spirit:name>Diamond_Simulation</spirit:name>
+                            <spirit:group>simulation</spirit:group>
+                            <spirit:file>
+                                <spirit:name>./serdes_sync_1/serdes_sync_1_softlogic.v</spirit:name>
+                                <spirit:fileType>verilogSource</spirit:fileType>
+                            </spirit:file>
+                            <spirit:file>
+                                <spirit:name>./serdes_sync_1/serdes_sync_1.vhd</spirit:name>
+                                <spirit:fileType>vhdlSource</spirit:fileType>
+                            </spirit:file>
+                        </spirit:fileset>
+                        <spirit:fileset>
+                            <spirit:name>Diamond_Synthesis</spirit:name>
+                            <spirit:group>synthesis</spirit:group>
+                            <spirit:file>
+                                <spirit:name>./serdes_sync_1/serdes_sync_1_softlogic.v</spirit:name>
+                                <spirit:fileType>verilogSource</spirit:fileType>
+                            </spirit:file>
+                            <spirit:file>
+                                <spirit:name>./serdes_sync_1/serdes_sync_1.vhd</spirit:name>
+                                <spirit:fileType>vhdlSource</spirit:fileType>
+                            </spirit:file>
+                        </spirit:fileset>
+                    </spirit:fileSets>
+                    <spirit:componentGenerators>
+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>Configuration</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
+                            <spirit:group>CONFIG</spirit:group>
+                        </spirit:componentGenerator>
+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>CreateNGD</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_ngd.tcl</spirit:generatorExe>
+                            <spirit:group>CONFIG</spirit:group>
+                        </spirit:componentGenerator>
+                        <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+                            <spirit:name>Generation</spirit:name>
+                            <spirit:apiType>none</spirit:apiType>
+                            <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
+                            <spirit:group>GENERATE</spirit:group>
+                        </spirit:componentGenerator>
+                    </spirit:componentGenerators>
+                    <spirit:model>
+                        <spirit:views/>
+                        <spirit:ports>
+                            <spirit:port>
+                                <spirit:name>cyawstn</spirit:name>
+                                <spirit:displayName>cyawstn</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>hdinn</spirit:name>
+                                <spirit:displayName>hdinn</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                                <spirit:vendorExtensions>
+                                    <lattice:attributes>
+                                        <lattice:attribute lattice:name="PadPin">true</lattice:attribute>
+                                    </lattice:attributes>
+                                </spirit:vendorExtensions>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>hdinp</spirit:name>
+                                <spirit:displayName>hdinp</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                                <spirit:vendorExtensions>
+                                    <lattice:attributes>
+                                        <lattice:attribute lattice:name="PadPin">true</lattice:attribute>
+                                    </lattice:attributes>
+                                </spirit:vendorExtensions>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>hdoutn</spirit:name>
+                                <spirit:displayName>hdoutn</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                                <spirit:vendorExtensions>
+                                    <lattice:attributes>
+                                        <lattice:attribute lattice:name="PadPin">true</lattice:attribute>
+                                    </lattice:attributes>
+                                </spirit:vendorExtensions>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>hdoutp</spirit:name>
+                                <spirit:displayName>hdoutp</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                                <spirit:vendorExtensions>
+                                    <lattice:attributes>
+                                        <lattice:attribute lattice:name="PadPin">true</lattice:attribute>
+                                    </lattice:attributes>
+                                </spirit:vendorExtensions>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>lsm_status_s</spirit:name>
+                                <spirit:displayName>lsm_status_s</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>pll_lol</spirit:name>
+                                <spirit:displayName>pll_lol</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>pll_refclki</spirit:name>
+                                <spirit:displayName>pll_refclki</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rsl_disable</spirit:name>
+                                <spirit:displayName>rsl_disable</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rsl_rst</spirit:name>
+                                <spirit:displayName>rsl_rst</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rsl_rx_rdy</spirit:name>
+                                <spirit:displayName>rsl_rx_rdy</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rsl_tx_rdy</spirit:name>
+                                <spirit:displayName>rsl_tx_rdy</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rst_dual_c</spirit:name>
+                                <spirit:displayName>rst_dual_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_cdr_lol_s</spirit:name>
+                                <spirit:displayName>rx_cdr_lol_s</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_los_low_s</spirit:name>
+                                <spirit:displayName>rx_los_low_s</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_pclk</spirit:name>
+                                <spirit:displayName>rx_pclk</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_pcs_rst_c</spirit:name>
+                                <spirit:displayName>rx_pcs_rst_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_pwrup_c</spirit:name>
+                                <spirit:displayName>rx_pwrup_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_serdes_rst_c</spirit:name>
+                                <spirit:displayName>rx_serdes_rst_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rxrefclk</spirit:name>
+                                <spirit:displayName>rxrefclk</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_en</spirit:name>
+                                <spirit:displayName>sci_en</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_en_dual</spirit:name>
+                                <spirit:displayName>sci_en_dual</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_int</spirit:name>
+                                <spirit:displayName>sci_int</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_rd</spirit:name>
+                                <spirit:displayName>sci_rd</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_sel</spirit:name>
+                                <spirit:displayName>sci_sel</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_sel_dual</spirit:name>
+                                <spirit:displayName>sci_sel_dual</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_wrn</spirit:name>
+                                <spirit:displayName>sci_wrn</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>serdes_pdb</spirit:name>
+                                <spirit:displayName>serdes_pdb</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>serdes_rst_dual_c</spirit:name>
+                                <spirit:displayName>serdes_rst_dual_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>signal_detect_c</spirit:name>
+                                <spirit:displayName>signal_detect_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sli_rst</spirit:name>
+                                <spirit:displayName>sli_rst</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                                <spirit:vendorExtensions>
+                                    <lattice:attributes>
+                                        <lattice:attribute lattice:name="Hide">true</lattice:attribute>
+                                    </lattice:attributes>
+                                </spirit:vendorExtensions>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_idle_c</spirit:name>
+                                <spirit:displayName>tx_idle_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_pclk</spirit:name>
+                                <spirit:displayName>tx_pclk</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_pcs_rst_c</spirit:name>
+                                <spirit:displayName>tx_pcs_rst_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_pwrup_c</spirit:name>
+                                <spirit:displayName>tx_pwrup_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_serdes_rst_c</spirit:name>
+                                <spirit:displayName>tx_serdes_rst_c</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_cv_err</spirit:name>
+                                <spirit:displayName>rx_cv_err</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>0</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_disp_err</spirit:name>
+                                <spirit:displayName>rx_disp_err</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>0</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rx_k</spirit:name>
+                                <spirit:displayName>rx_k</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>0</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>rxdata</spirit:name>
+                                <spirit:displayName>rxdata</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>7</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_addr</spirit:name>
+                                <spirit:displayName>sci_addr</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>5</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_rddata</spirit:name>
+                                <spirit:displayName>sci_rddata</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>out</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>7</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>sci_wrdata</spirit:name>
+                                <spirit:displayName>sci_wrdata</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>7</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_disp_sel</spirit:name>
+                                <spirit:displayName>tx_disp_sel</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>0</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_force_disp</spirit:name>
+                                <spirit:displayName>tx_force_disp</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>0</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>tx_k</spirit:name>
+                                <spirit:displayName>tx_k</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>0</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                            <spirit:port>
+                                <spirit:name>txdata</spirit:name>
+                                <spirit:displayName>txdata</spirit:displayName>
+                                <spirit:wire>
+                                    <spirit:direction>in</spirit:direction>
+                                    <spirit:vector>
+                                        <spirit:left>7</spirit:left>
+                                        <spirit:right>0</spirit:right>
+                                    </spirit:vector>
+                                </spirit:wire>
+                            </spirit:port>
+                        </spirit:ports>
+                    </spirit:model>
+                    <spirit:vendorExtensions>
+                        <lattice:synthesis>synplify</lattice:synthesis>
+                        <lattice:modified>2019-05-10.11:03:41 AM</lattice:modified>
+                        <lattice:attributes>
+                            <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+                            <lattice:attribute lattice:name="BBox">false</lattice:attribute>
+                            <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+                            <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+                            <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute>
+                            <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute>
+                            <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute>
+                            <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+                            <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+                        </lattice:attributes>
+                        <lattice:elements>
+                            <lattice:element>
+                                <lattice:name>Lane0</lattice:name>
+                                <lattice:type>DCUCHANNEL</lattice:type>
+                                <lattice:attributes>
+                                    <lattice:attribute lattice:name="ElementDrag">true</lattice:attribute>
+                                    <lattice:attribute lattice:name="ElementHide">false</lattice:attribute>
+                                    <lattice:attribute lattice:name="ElementType">DCUCHANNEL</lattice:attribute>
+                                    <lattice:attribute lattice:name="Locate">9</lattice:attribute>
+                                </lattice:attributes>
+                            </lattice:element>
+                        </lattice:elements>
+                        <lattice:lpc>
+                            <lattice:lpcsection lattice:name="Device"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Family</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">ecp5um</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>OperatingCondition</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Package</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">CABGA756</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PartName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F-8BG756C</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PartType</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SpeedGrade</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Status</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">P</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="IP"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">PCS</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreRevision</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">8.2</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreStatus</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CoreType</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Date</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">05/10/2019</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ModuleName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">serdes_sync_1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SourceFormat</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">VHDL</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Time</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">10:23:27</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>VendorName</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="Parameters"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>;ACHARA</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>;ACHARB</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>;ACHARM</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>;RXMCAENABLE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CDRLOLACTION</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Full Recalibration</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CDRLOLRANGE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">3</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CDR_MAX_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1.25</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CDR_MULT</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">10X</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CDR_REF_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">125.0000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>CH_MODE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Rx and Tx</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Destination</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>EDIF</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Expression</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">BusA(0 to 7)</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>IO</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>IO_TYPE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">G8B10B</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>LEQ</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>LOOPBACK</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>LOSPORT</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>NUM_CHS</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Order</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PPORT_RX_RDY</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PPORT_TX_RDY</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PROTOCOL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">G8B10B</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PWAIT_RX_RDY</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">3000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>PWAIT_TX_RDY</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">3000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RCSRC</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>REFCLK_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">125.0000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RSTSEQSEL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RX8B10B</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCOMMAA</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1100000100</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCOMMAB</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0011111000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCOMMAM</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1111111100</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCOUPLING</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">AC</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCTC</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCTCBYTEN</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCTCBYTEN1</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCTCBYTEN2</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCTCBYTEN3</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXCTCMATCHPATTERN</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">M4-S4</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXDIFFTERM</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">50 ohms</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXFIFO_ENABLE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXINVPOL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Non-invert</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXLDR</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Off</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXLOSTHRESHOLD</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">4</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXLSM</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXSC</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">K28P157</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RXWA</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Barrel Shift</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RX_DATA_WIDTH</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">8/10-Bit</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RX_FICLK_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">125.0000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RX_LINE_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1.2500</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>RX_RATE_DIV</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Full Rate</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SCIPORT</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>SOFTLOL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TX8B10B</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXAMPLITUDE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">800</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXDEPOST</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXDEPRE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXDIFFTERM</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">50 ohms</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXFIFO_ENABLE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXINVPOL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Non-invert</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXLDR</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Off</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXPLLLOLTHRESHOLD</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TXPLLMULT</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">10X</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TX_DATA_WIDTH</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">8/10-Bit</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TX_FICLK_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">125.0000</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TX_LINE_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1.2500</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TX_MAX_RATE</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1.25</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>TX_RATE_DIV</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">Full Rate</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>VHDL</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>Verilog</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcsection lattice:name="FilesGenerated"/>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>serdes_sync_1.pp</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">pp</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>serdes_sync_1.sym</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">sym</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>serdes_sync_1.tft</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">tft</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                            <lattice:lpcentry>
+                                <lattice:lpckey>serdes_sync_1.txt</lattice:lpckey>
+                                <lattice:lpcvalue lattice:resolve="constant">pcs_module</lattice:lpcvalue>
+                            </lattice:lpcentry>
+                        </lattice:lpc>
+                        <lattice:groups>
+                            <lattice:group>
+                                <lattice:name>DCUCHANNEL</lattice:name>
+                                <lattice:category>1</lattice:category>
+                                <lattice:attributes>
+                                    <lattice:attribute lattice:name="GroupDrag">true</lattice:attribute>
+                                    <lattice:attribute lattice:name="GroupHide">false</lattice:attribute>
+                                    <lattice:attribute lattice:name="GroupType">DCUCHANNEL</lattice:attribute>
+                                </lattice:attributes>
+                                <lattice:elementref>Lane0</lattice:elementref>
+                            </lattice:group>
+                        </lattice:groups>
+                    </spirit:vendorExtensions>
+                </spirit:componentRef>
+            </spirit:componentInstance>
+        </spirit:componentInstances>
+        <spirit:adHocConnections>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_cyawstn</spirit:name>
+                <spirit:displayName>serdes_sync_1_cyawstn</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="cyawstn" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_cyawstn"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_hdinn</spirit:name>
+                <spirit:displayName>serdes_sync_1_hdinn</spirit:displayName>
+                <spirit:vendorExtensions>
+                    <lattice:attributes>
+                        <lattice:attribute lattice:name="export">sys_yes</lattice:attribute>
+                    </lattice:attributes>
+                </spirit:vendorExtensions>
+                <spirit:internalPortReference spirit:portRef="hdinn" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_hdinn"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_hdinp</spirit:name>
+                <spirit:displayName>serdes_sync_1_hdinp</spirit:displayName>
+                <spirit:vendorExtensions>
+                    <lattice:attributes>
+                        <lattice:attribute lattice:name="export">sys_yes</lattice:attribute>
+                    </lattice:attributes>
+                </spirit:vendorExtensions>
+                <spirit:internalPortReference spirit:portRef="hdinp" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_hdinp"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_hdoutn</spirit:name>
+                <spirit:displayName>serdes_sync_1_hdoutn</spirit:displayName>
+                <spirit:vendorExtensions>
+                    <lattice:attributes>
+                        <lattice:attribute lattice:name="export">sys_yes</lattice:attribute>
+                    </lattice:attributes>
+                </spirit:vendorExtensions>
+                <spirit:internalPortReference spirit:portRef="hdoutn" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_hdoutn"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_hdoutp</spirit:name>
+                <spirit:displayName>serdes_sync_1_hdoutp</spirit:displayName>
+                <spirit:vendorExtensions>
+                    <lattice:attributes>
+                        <lattice:attribute lattice:name="export">sys_yes</lattice:attribute>
+                    </lattice:attributes>
+                </spirit:vendorExtensions>
+                <spirit:internalPortReference spirit:portRef="hdoutp" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_hdoutp"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_lsm_status_s</spirit:name>
+                <spirit:displayName>serdes_sync_1_lsm_status_s</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="lsm_status_s" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_lsm_status_s"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_pll_lol</spirit:name>
+                <spirit:displayName>serdes_sync_1_pll_lol</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="pll_lol" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_pll_lol"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_pll_refclki</spirit:name>
+                <spirit:displayName>serdes_sync_1_pll_refclki</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="pll_refclki" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_pll_refclki"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_rsl_disable</spirit:name>
+                <spirit:displayName>serdes_sync_1_rsl_disable</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rsl_disable" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_rsl_disable"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_rsl_rst</spirit:name>
+                <spirit:displayName>serdes_sync_1_rsl_rst</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rsl_rst" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_rsl_rst"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_rsl_rx_rdy</spirit:name>
+                <spirit:displayName>serdes_sync_1_rsl_rx_rdy</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rsl_rx_rdy" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_rsl_rx_rdy"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_rsl_tx_rdy</spirit:name>
+                <spirit:displayName>serdes_sync_1_rsl_tx_rdy</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rsl_tx_rdy" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_rsl_tx_rdy"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_rst_dual_c</spirit:name>
+                <spirit:displayName>serdes_sync_1_rst_dual_c</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rst_dual_c" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_rst_dual_c"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_rx_cdr_lol_s</spirit:name>
+                <spirit:displayName>serdes_sync_1_rx_cdr_lol_s</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rx_cdr_lol_s" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_rx_cdr_lol_s"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_rx_los_low_s</spirit:name>
+                <spirit:displayName>serdes_sync_1_rx_los_low_s</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rx_los_low_s" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_rx_los_low_s"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_rx_pclk</spirit:name>
+                <spirit:displayName>serdes_sync_1_rx_pclk</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rx_pclk" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_rx_pclk"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_rx_pcs_rst_c</spirit:name>
+                <spirit:displayName>serdes_sync_1_rx_pcs_rst_c</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rx_pcs_rst_c" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_rx_pcs_rst_c"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_rx_pwrup_c</spirit:name>
+                <spirit:displayName>serdes_sync_1_rx_pwrup_c</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rx_pwrup_c" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_rx_pwrup_c"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_rx_serdes_rst_c</spirit:name>
+                <spirit:displayName>serdes_sync_1_rx_serdes_rst_c</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rx_serdes_rst_c" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_rx_serdes_rst_c"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_rxrefclk</spirit:name>
+                <spirit:displayName>serdes_sync_1_rxrefclk</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rxrefclk" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_rxrefclk"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_sci_en</spirit:name>
+                <spirit:displayName>serdes_sync_1_sci_en</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_en" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_sci_en"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_sci_en_dual</spirit:name>
+                <spirit:displayName>serdes_sync_1_sci_en_dual</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_en_dual" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_sci_en_dual"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_sci_int</spirit:name>
+                <spirit:displayName>serdes_sync_1_sci_int</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_int" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_sci_int"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_sci_rd</spirit:name>
+                <spirit:displayName>serdes_sync_1_sci_rd</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_rd" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_sci_rd"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_sci_sel</spirit:name>
+                <spirit:displayName>serdes_sync_1_sci_sel</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_sel" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_sci_sel"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_sci_sel_dual</spirit:name>
+                <spirit:displayName>serdes_sync_1_sci_sel_dual</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_sel_dual" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_sci_sel_dual"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_sci_wrn</spirit:name>
+                <spirit:displayName>serdes_sync_1_sci_wrn</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_wrn" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_sci_wrn"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_serdes_pdb</spirit:name>
+                <spirit:displayName>serdes_sync_1_serdes_pdb</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="serdes_pdb" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_serdes_pdb"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_serdes_rst_dual_c</spirit:name>
+                <spirit:displayName>serdes_sync_1_serdes_rst_dual_c</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="serdes_rst_dual_c" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_serdes_rst_dual_c"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_signal_detect_c</spirit:name>
+                <spirit:displayName>serdes_sync_1_signal_detect_c</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="signal_detect_c" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_signal_detect_c"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_tx_idle_c</spirit:name>
+                <spirit:displayName>serdes_sync_1_tx_idle_c</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="tx_idle_c" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_tx_idle_c"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_tx_pclk</spirit:name>
+                <spirit:displayName>serdes_sync_1_tx_pclk</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="tx_pclk" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_tx_pclk"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_tx_pcs_rst_c</spirit:name>
+                <spirit:displayName>serdes_sync_1_tx_pcs_rst_c</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="tx_pcs_rst_c" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_tx_pcs_rst_c"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_tx_pwrup_c</spirit:name>
+                <spirit:displayName>serdes_sync_1_tx_pwrup_c</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="tx_pwrup_c" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_tx_pwrup_c"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_tx_serdes_rst_c</spirit:name>
+                <spirit:displayName>serdes_sync_1_tx_serdes_rst_c</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="tx_serdes_rst_c" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_tx_serdes_rst_c"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_rx_cv_err</spirit:name>
+                <spirit:displayName>serdes_sync_1_rx_cv_err</spirit:displayName>
+                <spirit:internalPortReference spirit:right="0" spirit:portRef="rx_cv_err" spirit:componentRef="serdes_sync_1" spirit:left="0"/>
+                <spirit:externalPortReference spirit:right="0" spirit:portRef="serdes_sync_1_rx_cv_err" spirit:left="0"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_rx_cv_err[0]</spirit:name>
+                <spirit:displayName>serdes_sync_1_rx_cv_err[0]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rx_cv_err[0]" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_rx_cv_err[0]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_rx_disp_err</spirit:name>
+                <spirit:displayName>serdes_sync_1_rx_disp_err</spirit:displayName>
+                <spirit:internalPortReference spirit:right="0" spirit:portRef="rx_disp_err" spirit:componentRef="serdes_sync_1" spirit:left="0"/>
+                <spirit:externalPortReference spirit:right="0" spirit:portRef="serdes_sync_1_rx_disp_err" spirit:left="0"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_rx_disp_err[0]</spirit:name>
+                <spirit:displayName>serdes_sync_1_rx_disp_err[0]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rx_disp_err[0]" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_rx_disp_err[0]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_rx_k</spirit:name>
+                <spirit:displayName>serdes_sync_1_rx_k</spirit:displayName>
+                <spirit:internalPortReference spirit:right="0" spirit:portRef="rx_k" spirit:componentRef="serdes_sync_1" spirit:left="0"/>
+                <spirit:externalPortReference spirit:right="0" spirit:portRef="serdes_sync_1_rx_k" spirit:left="0"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_rx_k[0]</spirit:name>
+                <spirit:displayName>serdes_sync_1_rx_k[0]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rx_k[0]" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_rx_k[0]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_rxdata</spirit:name>
+                <spirit:displayName>serdes_sync_1_rxdata</spirit:displayName>
+                <spirit:internalPortReference spirit:right="0" spirit:portRef="rxdata" spirit:componentRef="serdes_sync_1" spirit:left="7"/>
+                <spirit:externalPortReference spirit:right="0" spirit:portRef="serdes_sync_1_rxdata" spirit:left="7"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_rxdata[0]</spirit:name>
+                <spirit:displayName>serdes_sync_1_rxdata[0]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rxdata[0]" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_rxdata[0]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_rxdata[1]</spirit:name>
+                <spirit:displayName>serdes_sync_1_rxdata[1]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rxdata[1]" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_rxdata[1]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_rxdata[2]</spirit:name>
+                <spirit:displayName>serdes_sync_1_rxdata[2]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rxdata[2]" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_rxdata[2]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_rxdata[3]</spirit:name>
+                <spirit:displayName>serdes_sync_1_rxdata[3]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rxdata[3]" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_rxdata[3]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_rxdata[4]</spirit:name>
+                <spirit:displayName>serdes_sync_1_rxdata[4]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rxdata[4]" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_rxdata[4]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_rxdata[5]</spirit:name>
+                <spirit:displayName>serdes_sync_1_rxdata[5]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rxdata[5]" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_rxdata[5]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_rxdata[6]</spirit:name>
+                <spirit:displayName>serdes_sync_1_rxdata[6]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rxdata[6]" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_rxdata[6]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_rxdata[7]</spirit:name>
+                <spirit:displayName>serdes_sync_1_rxdata[7]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="rxdata[7]" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_rxdata[7]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_sci_addr</spirit:name>
+                <spirit:displayName>serdes_sync_1_sci_addr</spirit:displayName>
+                <spirit:internalPortReference spirit:right="0" spirit:portRef="sci_addr" spirit:componentRef="serdes_sync_1" spirit:left="5"/>
+                <spirit:externalPortReference spirit:right="0" spirit:portRef="serdes_sync_1_sci_addr" spirit:left="5"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_sci_addr[0]</spirit:name>
+                <spirit:displayName>serdes_sync_1_sci_addr[0]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_sci_addr[0]"/>
+                <spirit:internalPortReference spirit:portRef="sci_addr[0]" spirit:componentRef="serdes_sync_1"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_sci_addr[1]</spirit:name>
+                <spirit:displayName>serdes_sync_1_sci_addr[1]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_sci_addr[1]"/>
+                <spirit:internalPortReference spirit:portRef="sci_addr[1]" spirit:componentRef="serdes_sync_1"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_sci_addr[2]</spirit:name>
+                <spirit:displayName>serdes_sync_1_sci_addr[2]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_sci_addr[2]"/>
+                <spirit:internalPortReference spirit:portRef="sci_addr[2]" spirit:componentRef="serdes_sync_1"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_sci_addr[3]</spirit:name>
+                <spirit:displayName>serdes_sync_1_sci_addr[3]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_sci_addr[3]"/>
+                <spirit:internalPortReference spirit:portRef="sci_addr[3]" spirit:componentRef="serdes_sync_1"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_sci_addr[4]</spirit:name>
+                <spirit:displayName>serdes_sync_1_sci_addr[4]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_sci_addr[4]"/>
+                <spirit:internalPortReference spirit:portRef="sci_addr[4]" spirit:componentRef="serdes_sync_1"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_sci_addr[5]</spirit:name>
+                <spirit:displayName>serdes_sync_1_sci_addr[5]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_sci_addr[5]"/>
+                <spirit:internalPortReference spirit:portRef="sci_addr[5]" spirit:componentRef="serdes_sync_1"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_sci_rddata</spirit:name>
+                <spirit:displayName>serdes_sync_1_sci_rddata</spirit:displayName>
+                <spirit:internalPortReference spirit:right="0" spirit:portRef="sci_rddata" spirit:componentRef="serdes_sync_1" spirit:left="7"/>
+                <spirit:externalPortReference spirit:right="0" spirit:portRef="serdes_sync_1_sci_rddata" spirit:left="7"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_sci_rddata[0]</spirit:name>
+                <spirit:displayName>serdes_sync_1_sci_rddata[0]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_rddata[0]" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_sci_rddata[0]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_sci_rddata[1]</spirit:name>
+                <spirit:displayName>serdes_sync_1_sci_rddata[1]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_rddata[1]" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_sci_rddata[1]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_sci_rddata[2]</spirit:name>
+                <spirit:displayName>serdes_sync_1_sci_rddata[2]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_rddata[2]" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_sci_rddata[2]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_sci_rddata[3]</spirit:name>
+                <spirit:displayName>serdes_sync_1_sci_rddata[3]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_rddata[3]" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_sci_rddata[3]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_sci_rddata[4]</spirit:name>
+                <spirit:displayName>serdes_sync_1_sci_rddata[4]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_rddata[4]" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_sci_rddata[4]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_sci_rddata[5]</spirit:name>
+                <spirit:displayName>serdes_sync_1_sci_rddata[5]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_rddata[5]" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_sci_rddata[5]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_sci_rddata[6]</spirit:name>
+                <spirit:displayName>serdes_sync_1_sci_rddata[6]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_rddata[6]" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_sci_rddata[6]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_sci_rddata[7]</spirit:name>
+                <spirit:displayName>serdes_sync_1_sci_rddata[7]</spirit:displayName>
+                <spirit:internalPortReference spirit:portRef="sci_rddata[7]" spirit:componentRef="serdes_sync_1"/>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_sci_rddata[7]"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_sci_wrdata</spirit:name>
+                <spirit:displayName>serdes_sync_1_sci_wrdata</spirit:displayName>
+                <spirit:internalPortReference spirit:right="0" spirit:portRef="sci_wrdata" spirit:componentRef="serdes_sync_1" spirit:left="7"/>
+                <spirit:externalPortReference spirit:right="0" spirit:portRef="serdes_sync_1_sci_wrdata" spirit:left="7"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_sci_wrdata[0]</spirit:name>
+                <spirit:displayName>serdes_sync_1_sci_wrdata[0]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_sci_wrdata[0]"/>
+                <spirit:internalPortReference spirit:portRef="sci_wrdata[0]" spirit:componentRef="serdes_sync_1"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_sci_wrdata[1]</spirit:name>
+                <spirit:displayName>serdes_sync_1_sci_wrdata[1]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_sci_wrdata[1]"/>
+                <spirit:internalPortReference spirit:portRef="sci_wrdata[1]" spirit:componentRef="serdes_sync_1"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_sci_wrdata[2]</spirit:name>
+                <spirit:displayName>serdes_sync_1_sci_wrdata[2]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_sci_wrdata[2]"/>
+                <spirit:internalPortReference spirit:portRef="sci_wrdata[2]" spirit:componentRef="serdes_sync_1"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_sci_wrdata[3]</spirit:name>
+                <spirit:displayName>serdes_sync_1_sci_wrdata[3]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_sci_wrdata[3]"/>
+                <spirit:internalPortReference spirit:portRef="sci_wrdata[3]" spirit:componentRef="serdes_sync_1"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_sci_wrdata[4]</spirit:name>
+                <spirit:displayName>serdes_sync_1_sci_wrdata[4]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_sci_wrdata[4]"/>
+                <spirit:internalPortReference spirit:portRef="sci_wrdata[4]" spirit:componentRef="serdes_sync_1"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_sci_wrdata[5]</spirit:name>
+                <spirit:displayName>serdes_sync_1_sci_wrdata[5]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_sci_wrdata[5]"/>
+                <spirit:internalPortReference spirit:portRef="sci_wrdata[5]" spirit:componentRef="serdes_sync_1"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_sci_wrdata[6]</spirit:name>
+                <spirit:displayName>serdes_sync_1_sci_wrdata[6]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_sci_wrdata[6]"/>
+                <spirit:internalPortReference spirit:portRef="sci_wrdata[6]" spirit:componentRef="serdes_sync_1"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_sci_wrdata[7]</spirit:name>
+                <spirit:displayName>serdes_sync_1_sci_wrdata[7]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_sci_wrdata[7]"/>
+                <spirit:internalPortReference spirit:portRef="sci_wrdata[7]" spirit:componentRef="serdes_sync_1"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_tx_disp_sel</spirit:name>
+                <spirit:displayName>serdes_sync_1_tx_disp_sel</spirit:displayName>
+                <spirit:internalPortReference spirit:right="0" spirit:portRef="tx_disp_sel" spirit:componentRef="serdes_sync_1" spirit:left="0"/>
+                <spirit:externalPortReference spirit:right="0" spirit:portRef="serdes_sync_1_tx_disp_sel" spirit:left="0"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_tx_disp_sel[0]</spirit:name>
+                <spirit:displayName>serdes_sync_1_tx_disp_sel[0]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_tx_disp_sel[0]"/>
+                <spirit:internalPortReference spirit:portRef="tx_disp_sel[0]" spirit:componentRef="serdes_sync_1"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_tx_force_disp</spirit:name>
+                <spirit:displayName>serdes_sync_1_tx_force_disp</spirit:displayName>
+                <spirit:internalPortReference spirit:right="0" spirit:portRef="tx_force_disp" spirit:componentRef="serdes_sync_1" spirit:left="0"/>
+                <spirit:externalPortReference spirit:right="0" spirit:portRef="serdes_sync_1_tx_force_disp" spirit:left="0"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_tx_force_disp[0]</spirit:name>
+                <spirit:displayName>serdes_sync_1_tx_force_disp[0]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_tx_force_disp[0]"/>
+                <spirit:internalPortReference spirit:portRef="tx_force_disp[0]" spirit:componentRef="serdes_sync_1"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_tx_k</spirit:name>
+                <spirit:displayName>serdes_sync_1_tx_k</spirit:displayName>
+                <spirit:internalPortReference spirit:right="0" spirit:portRef="tx_k" spirit:componentRef="serdes_sync_1" spirit:left="0"/>
+                <spirit:externalPortReference spirit:right="0" spirit:portRef="serdes_sync_1_tx_k" spirit:left="0"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_tx_k[0]</spirit:name>
+                <spirit:displayName>serdes_sync_1_tx_k[0]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_tx_k[0]"/>
+                <spirit:internalPortReference spirit:portRef="tx_k[0]" spirit:componentRef="serdes_sync_1"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_txdata</spirit:name>
+                <spirit:displayName>serdes_sync_1_txdata</spirit:displayName>
+                <spirit:internalPortReference spirit:right="0" spirit:portRef="txdata" spirit:componentRef="serdes_sync_1" spirit:left="7"/>
+                <spirit:externalPortReference spirit:right="0" spirit:portRef="serdes_sync_1_txdata" spirit:left="7"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_txdata[0]</spirit:name>
+                <spirit:displayName>serdes_sync_1_txdata[0]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_txdata[0]"/>
+                <spirit:internalPortReference spirit:portRef="txdata[0]" spirit:componentRef="serdes_sync_1"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_txdata[1]</spirit:name>
+                <spirit:displayName>serdes_sync_1_txdata[1]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_txdata[1]"/>
+                <spirit:internalPortReference spirit:portRef="txdata[1]" spirit:componentRef="serdes_sync_1"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_txdata[2]</spirit:name>
+                <spirit:displayName>serdes_sync_1_txdata[2]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_txdata[2]"/>
+                <spirit:internalPortReference spirit:portRef="txdata[2]" spirit:componentRef="serdes_sync_1"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_txdata[3]</spirit:name>
+                <spirit:displayName>serdes_sync_1_txdata[3]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_txdata[3]"/>
+                <spirit:internalPortReference spirit:portRef="txdata[3]" spirit:componentRef="serdes_sync_1"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_txdata[4]</spirit:name>
+                <spirit:displayName>serdes_sync_1_txdata[4]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_txdata[4]"/>
+                <spirit:internalPortReference spirit:portRef="txdata[4]" spirit:componentRef="serdes_sync_1"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_txdata[5]</spirit:name>
+                <spirit:displayName>serdes_sync_1_txdata[5]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_txdata[5]"/>
+                <spirit:internalPortReference spirit:portRef="txdata[5]" spirit:componentRef="serdes_sync_1"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_txdata[6]</spirit:name>
+                <spirit:displayName>serdes_sync_1_txdata[6]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_txdata[6]"/>
+                <spirit:internalPortReference spirit:portRef="txdata[6]" spirit:componentRef="serdes_sync_1"/>
+            </spirit:adHocConnection>
+            <spirit:adHocConnection>
+                <spirit:name>serdes_sync_1_txdata[7]</spirit:name>
+                <spirit:displayName>serdes_sync_1_txdata[7]</spirit:displayName>
+                <spirit:externalPortReference spirit:portRef="serdes_sync_1_txdata[7]"/>
+                <spirit:internalPortReference spirit:portRef="txdata[7]" spirit:componentRef="serdes_sync_1"/>
+            </spirit:adHocConnection>
+        </spirit:adHocConnections>
+    </spirit:design>
+</lattice:project>

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_0.vhd b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_0.vhd
new file mode 100644 (file)
index 0000000..6228fec
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_0.vhd
@@ -0,0 +1,161 @@
+
+
+--
+-- Verific VHDL Description of module serdes_sync_0
+--
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+entity serdes_sync_0 is
+    port (serdes_sync_1_rx_cv_err: out std_logic_vector(0 downto 0);
+        serdes_sync_1_rx_disp_err: out std_logic_vector(0 downto 0);
+        serdes_sync_1_rx_k: out std_logic_vector(0 downto 0);
+        serdes_sync_1_rxdata: out std_logic_vector(7 downto 0);
+        serdes_sync_1_sci_addr: in std_logic_vector(5 downto 0);
+        serdes_sync_1_sci_rddata: out std_logic_vector(7 downto 0);
+        serdes_sync_1_sci_wrdata: in std_logic_vector(7 downto 0);
+        serdes_sync_1_tx_disp_sel: in std_logic_vector(0 downto 0);
+        serdes_sync_1_tx_force_disp: in std_logic_vector(0 downto 0);
+        serdes_sync_1_tx_k: in std_logic_vector(0 downto 0);
+        serdes_sync_1_txdata: in std_logic_vector(7 downto 0);
+        serdes_sync_1_cyawstn: in std_logic;
+        serdes_sync_1_hdinn: in std_logic;
+        serdes_sync_1_hdinp: in std_logic;
+        serdes_sync_1_hdoutn: out std_logic;
+        serdes_sync_1_hdoutp: out std_logic;
+        serdes_sync_1_lsm_status_s: out std_logic;
+        serdes_sync_1_pll_lol: out std_logic;
+        serdes_sync_1_pll_refclki: in std_logic;
+        serdes_sync_1_rsl_disable: in std_logic;
+        serdes_sync_1_rsl_rst: in std_logic;
+        serdes_sync_1_rsl_rx_rdy: out std_logic;
+        serdes_sync_1_rsl_tx_rdy: out std_logic;
+        serdes_sync_1_rst_dual_c: in std_logic;
+        serdes_sync_1_rx_cdr_lol_s: out std_logic;
+        serdes_sync_1_rx_los_low_s: out std_logic;
+        serdes_sync_1_rx_pclk: out std_logic;
+        serdes_sync_1_rx_pcs_rst_c: in std_logic;
+        serdes_sync_1_rx_pwrup_c: in std_logic;
+        serdes_sync_1_rx_serdes_rst_c: in std_logic;
+        serdes_sync_1_rxrefclk: in std_logic;
+        serdes_sync_1_sci_en: in std_logic;
+        serdes_sync_1_sci_en_dual: in std_logic;
+        serdes_sync_1_sci_int: out std_logic;
+        serdes_sync_1_sci_rd: in std_logic;
+        serdes_sync_1_sci_sel: in std_logic;
+        serdes_sync_1_sci_sel_dual: in std_logic;
+        serdes_sync_1_sci_wrn: in std_logic;
+        serdes_sync_1_serdes_pdb: in std_logic;
+        serdes_sync_1_serdes_rst_dual_c: in std_logic;
+        serdes_sync_1_signal_detect_c: in std_logic;
+        serdes_sync_1_tx_idle_c: in std_logic;
+        serdes_sync_1_tx_pclk: out std_logic;
+        serdes_sync_1_tx_pcs_rst_c: in std_logic;
+        serdes_sync_1_tx_pwrup_c: in std_logic;
+        serdes_sync_1_tx_serdes_rst_c: in std_logic
+    );
+    
+end entity serdes_sync_0; -- sbp_module=true 
+
+architecture serdes_sync_0 of serdes_sync_0 is 
+    component serdes_sync_1 is
+        port (rx_cv_err: out std_logic_vector(0 downto 0);
+            rx_disp_err: out std_logic_vector(0 downto 0);
+            rx_k: out std_logic_vector(0 downto 0);
+            rxdata: out std_logic_vector(7 downto 0);
+            sci_addr: in std_logic_vector(5 downto 0);
+            sci_rddata: out std_logic_vector(7 downto 0);
+            sci_wrdata: in std_logic_vector(7 downto 0);
+            tx_disp_sel: in std_logic_vector(0 downto 0);
+            tx_force_disp: in std_logic_vector(0 downto 0);
+            tx_k: in std_logic_vector(0 downto 0);
+            txdata: in std_logic_vector(7 downto 0);
+            cyawstn: in std_logic;
+            hdinn: in std_logic;
+            hdinp: in std_logic;
+            hdoutn: out std_logic;
+            hdoutp: out std_logic;
+            lsm_status_s: out std_logic;
+            pll_lol: out std_logic;
+            pll_refclki: in std_logic;
+            rsl_disable: in std_logic;
+            rsl_rst: in std_logic;
+            rsl_rx_rdy: out std_logic;
+            rsl_tx_rdy: out std_logic;
+            rst_dual_c: in std_logic;
+            rx_cdr_lol_s: out std_logic;
+            rx_los_low_s: out std_logic;
+            rx_pclk: out std_logic;
+            rx_pcs_rst_c: in std_logic;
+            rx_pwrup_c: in std_logic;
+            rx_serdes_rst_c: in std_logic;
+            rxrefclk: in std_logic;
+            sci_en: in std_logic;
+            sci_en_dual: in std_logic;
+            sci_int: out std_logic;
+            sci_rd: in std_logic;
+            sci_sel: in std_logic;
+            sci_sel_dual: in std_logic;
+            sci_wrn: in std_logic;
+            serdes_pdb: in std_logic;
+            serdes_rst_dual_c: in std_logic;
+            signal_detect_c: in std_logic;
+            sli_rst: in std_logic;
+            tx_idle_c: in std_logic;
+            tx_pclk: out std_logic;
+            tx_pcs_rst_c: in std_logic;
+            tx_pwrup_c: in std_logic;
+            tx_serdes_rst_c: in std_logic
+        );
+        
+    end component serdes_sync_1; -- not_need_bbox=true 
+    
+    
+    signal sli_rst_wire0,gnd : std_logic; 
+begin
+    sli_rst_wire0 <= serdes_sync_1_serdes_rst_dual_c OR  serdes_sync_1_tx_serdes_rst_c OR  (NOT serdes_sync_1_serdes_pdb) OR  (NOT serdes_sync_1_tx_pwrup_c);
+    serdes_sync_1_inst: component serdes_sync_1 port map (rx_cv_err(0)=>serdes_sync_1_rx_cv_err(0),
+            rx_disp_err(0)=>serdes_sync_1_rx_disp_err(0),rx_k(0)=>serdes_sync_1_rx_k(0),
+            rxdata(7)=>serdes_sync_1_rxdata(7),rxdata(6)=>serdes_sync_1_rxdata(6),
+            rxdata(5)=>serdes_sync_1_rxdata(5),rxdata(4)=>serdes_sync_1_rxdata(4),
+            rxdata(3)=>serdes_sync_1_rxdata(3),rxdata(2)=>serdes_sync_1_rxdata(2),
+            rxdata(1)=>serdes_sync_1_rxdata(1),rxdata(0)=>serdes_sync_1_rxdata(0),
+            sci_addr(5)=>serdes_sync_1_sci_addr(5),sci_addr(4)=>serdes_sync_1_sci_addr(4),
+            sci_addr(3)=>serdes_sync_1_sci_addr(3),sci_addr(2)=>serdes_sync_1_sci_addr(2),
+            sci_addr(1)=>serdes_sync_1_sci_addr(1),sci_addr(0)=>serdes_sync_1_sci_addr(0),
+            sci_rddata(7)=>serdes_sync_1_sci_rddata(7),sci_rddata(6)=>serdes_sync_1_sci_rddata(6),
+            sci_rddata(5)=>serdes_sync_1_sci_rddata(5),sci_rddata(4)=>serdes_sync_1_sci_rddata(4),
+            sci_rddata(3)=>serdes_sync_1_sci_rddata(3),sci_rddata(2)=>serdes_sync_1_sci_rddata(2),
+            sci_rddata(1)=>serdes_sync_1_sci_rddata(1),sci_rddata(0)=>serdes_sync_1_sci_rddata(0),
+            sci_wrdata(7)=>serdes_sync_1_sci_wrdata(7),sci_wrdata(6)=>serdes_sync_1_sci_wrdata(6),
+            sci_wrdata(5)=>serdes_sync_1_sci_wrdata(5),sci_wrdata(4)=>serdes_sync_1_sci_wrdata(4),
+            sci_wrdata(3)=>serdes_sync_1_sci_wrdata(3),sci_wrdata(2)=>serdes_sync_1_sci_wrdata(2),
+            sci_wrdata(1)=>serdes_sync_1_sci_wrdata(1),sci_wrdata(0)=>serdes_sync_1_sci_wrdata(0),
+            tx_disp_sel(0)=>serdes_sync_1_tx_disp_sel(0),tx_force_disp(0)=>serdes_sync_1_tx_force_disp(0),
+            tx_k(0)=>serdes_sync_1_tx_k(0),txdata(7)=>serdes_sync_1_txdata(7),
+            txdata(6)=>serdes_sync_1_txdata(6),txdata(5)=>serdes_sync_1_txdata(5),
+            txdata(4)=>serdes_sync_1_txdata(4),txdata(3)=>serdes_sync_1_txdata(3),
+            txdata(2)=>serdes_sync_1_txdata(2),txdata(1)=>serdes_sync_1_txdata(1),
+            txdata(0)=>serdes_sync_1_txdata(0),cyawstn=>serdes_sync_1_cyawstn,
+            hdinn=>serdes_sync_1_hdinn,hdinp=>serdes_sync_1_hdinp,hdoutn=>serdes_sync_1_hdoutn,
+            hdoutp=>serdes_sync_1_hdoutp,lsm_status_s=>serdes_sync_1_lsm_status_s,
+            pll_lol=>serdes_sync_1_pll_lol,pll_refclki=>serdes_sync_1_pll_refclki,
+            rsl_disable=>serdes_sync_1_rsl_disable,rsl_rst=>serdes_sync_1_rsl_rst,
+            rsl_rx_rdy=>serdes_sync_1_rsl_rx_rdy,rsl_tx_rdy=>serdes_sync_1_rsl_tx_rdy,
+            rst_dual_c=>serdes_sync_1_rst_dual_c,rx_cdr_lol_s=>serdes_sync_1_rx_cdr_lol_s,
+            rx_los_low_s=>serdes_sync_1_rx_los_low_s,rx_pclk=>serdes_sync_1_rx_pclk,
+            rx_pcs_rst_c=>serdes_sync_1_rx_pcs_rst_c,rx_pwrup_c=>serdes_sync_1_rx_pwrup_c,
+            rx_serdes_rst_c=>serdes_sync_1_rx_serdes_rst_c,rxrefclk=>serdes_sync_1_rxrefclk,
+            sci_en=>serdes_sync_1_sci_en,sci_en_dual=>serdes_sync_1_sci_en_dual,
+            sci_int=>serdes_sync_1_sci_int,sci_rd=>serdes_sync_1_sci_rd,sci_sel=>serdes_sync_1_sci_sel,
+            sci_sel_dual=>serdes_sync_1_sci_sel_dual,sci_wrn=>serdes_sync_1_sci_wrn,
+            serdes_pdb=>serdes_sync_1_serdes_pdb,serdes_rst_dual_c=>serdes_sync_1_serdes_rst_dual_c,
+            signal_detect_c=>serdes_sync_1_signal_detect_c,sli_rst=>sli_rst_wire0,
+            tx_idle_c=>serdes_sync_1_tx_idle_c,tx_pclk=>serdes_sync_1_tx_pclk,
+            tx_pcs_rst_c=>serdes_sync_1_tx_pcs_rst_c,tx_pwrup_c=>serdes_sync_1_tx_pwrup_c,
+            tx_serdes_rst_c=>serdes_sync_1_tx_serdes_rst_c);
+    gnd <= '0' ;
+    
+end architecture serdes_sync_0; -- sbp_module=true 
+

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_0_tmpl.v b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_0_tmpl.v
new file mode 100644 (file)
index 0000000..a6828ba
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_0_tmpl.v
@@ -0,0 +1,19 @@
+//Verilog instantiation template
+
+serdes_sync_0 _inst (.serdes_sync_1_rx_cv_err(), .serdes_sync_1_rx_disp_err(), 
+            .serdes_sync_1_rx_k(), .serdes_sync_1_rxdata(), .serdes_sync_1_sci_addr(), 
+            .serdes_sync_1_sci_rddata(), .serdes_sync_1_sci_wrdata(), .serdes_sync_1_tx_disp_sel(), 
+            .serdes_sync_1_tx_force_disp(), .serdes_sync_1_tx_k(), .serdes_sync_1_txdata(), 
+            .serdes_sync_1_cyawstn(), .serdes_sync_1_hdinn(), .serdes_sync_1_hdinp(), 
+            .serdes_sync_1_hdoutn(), .serdes_sync_1_hdoutp(), .serdes_sync_1_lsm_status_s(), 
+            .serdes_sync_1_pll_lol(), .serdes_sync_1_pll_refclki(), .serdes_sync_1_rsl_disable(), 
+            .serdes_sync_1_rsl_rst(), .serdes_sync_1_rsl_rx_rdy(), .serdes_sync_1_rsl_tx_rdy(), 
+            .serdes_sync_1_rst_dual_c(), .serdes_sync_1_rx_cdr_lol_s(), 
+            .serdes_sync_1_rx_los_low_s(), .serdes_sync_1_rx_pclk(), .serdes_sync_1_rx_pcs_rst_c(), 
+            .serdes_sync_1_rx_pwrup_c(), .serdes_sync_1_rx_serdes_rst_c(), 
+            .serdes_sync_1_rxrefclk(), .serdes_sync_1_sci_en(), .serdes_sync_1_sci_en_dual(), 
+            .serdes_sync_1_sci_int(), .serdes_sync_1_sci_rd(), .serdes_sync_1_sci_sel(), 
+            .serdes_sync_1_sci_sel_dual(), .serdes_sync_1_sci_wrn(), .serdes_sync_1_serdes_pdb(), 
+            .serdes_sync_1_serdes_rst_dual_c(), .serdes_sync_1_signal_detect_c(), 
+            .serdes_sync_1_tx_idle_c(), .serdes_sync_1_tx_pclk(), .serdes_sync_1_tx_pcs_rst_c(), 
+            .serdes_sync_1_tx_pwrup_c(), .serdes_sync_1_tx_serdes_rst_c());
\ No newline at end of file

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_0.lpc b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_0.lpc
new file mode 100644 (file)
index 0000000..b79efbe
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_0.lpc
@@ -0,0 +1,97 @@
+[Device]
+Family=ecp5um
+OperatingCondition=COM
+Package=CABGA756
+PartName=LFE5UM-85F-8BG756C
+PartType=LFE5UM-85F
+SpeedGrade=8
+Status=P
+[IP]
+CoreName=PCS
+CoreRevision=8.2
+CoreStatus=Demo
+CoreType=LPM
+Date=04/24/2019
+ModuleName=serdes_sync_0
+ParameterFileVersion=1.0
+SourceFormat=vhdl
+Time=16:52:37
+VendorName=Lattice Semiconductor Corporation
+[Parameters]
+;ACHARA=0 00H
+;ACHARB=0 00H
+;ACHARM=0 00H
+;RXMCAENABLE=Disabled
+CDRLOLACTION=Full Recalibration
+CDRLOLRANGE=3
+CDR_MAX_RATE=2
+CDR_MULT=10X
+CDR_REF_RATE=200.0000
+CH_MODE=Rx and Tx
+Destination=Synplicity
+EDIF=1
+Expression=BusA(0 to 7)
+IO=0
+IO_TYPE=G8B10B
+LEQ=0
+LOOPBACK=Disabled
+LOSPORT=Enabled
+NUM_CHS=1
+Order=Big Endian [MSB:LSB]
+PPORT_RX_RDY=Enabled
+PPORT_TX_RDY=Enabled
+PROTOCOL=G8B10B
+PWAIT_RX_RDY=3000
+PWAIT_TX_RDY=3000
+RCSRC=Disabled
+REFCLK_RATE=200.0000
+RSTSEQSEL=Enabled
+RX8B10B=Enabled
+RXCOMMAA=1100000100
+RXCOMMAB=0011111000
+RXCOMMAM=1111111100
+RXCOUPLING=AC
+RXCTC=Disabled
+RXCTCBYTEN=0 00H
+RXCTCBYTEN1=0 00H
+RXCTCBYTEN2=0 00H
+RXCTCBYTEN3=0 00H
+RXCTCMATCHPATTERN=M4-S4
+RXDIFFTERM=50 ohms
+RXFIFO_ENABLE=Enabled
+RXINVPOL=Non-invert
+RXLDR=Off
+RXLOSTHRESHOLD=4
+RXLSM=Enabled
+RXSC=K28P157
+RXWA=Barrel Shift
+RX_DATA_WIDTH=8/10-Bit
+RX_FICLK_RATE=200.0000
+RX_LINE_RATE=2.0000
+RX_RATE_DIV=Full Rate
+SCIPORT=Enabled
+SOFTLOL=Enabled
+TX8B10B=Enabled
+TXAMPLITUDE=800
+TXDEPOST=Disabled
+TXDEPRE=Disabled
+TXDIFFTERM=50 ohms
+TXFIFO_ENABLE=Enabled
+TXINVPOL=Non-invert
+TXLDR=Off
+TXPLLLOLTHRESHOLD=1
+TXPLLMULT=10X
+TX_DATA_WIDTH=8/10-Bit
+TX_FICLK_RATE=200.0000
+TX_LINE_RATE=2.0000
+TX_MAX_RATE=2
+TX_RATE_DIV=Full Rate
+VHDL=1
+Verilog=0
+[FilesGenerated]
+serdes_sync_0.pp=pp
+serdes_sync_0.sym=sym
+serdes_sync_0.tft=tft
+serdes_sync_0.txt=pcs_module
+[SYSTEMPNR]
+LN0=DCU0_CH0

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.cmd b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.cmd
new file mode 100644 (file)
index 0000000..a65388e
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.cmd
@@ -0,0 +1,18 @@
+PROJECT: serdes_sync_1
+               working_path: "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results"
+               module: serdes_sync_1
+               verilog_file_list: "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd" "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v"
+               vlog_std_v2001: true
+               constraint_file_name: "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc"
+               suffix_name: edn
+               output_file_name: serdes_sync_1
+               write_prf: true
+               disable_io_insertion: true
+               force_gsr: false
+               frequency: 100
+               fanout_limit: 50
+               retiming: false
+               pipe: false
+               part: LFE5UM-85F
+               speed_grade: 8
+               

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.cst b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.cst
new file mode 100644 (file)
index 0000000..0a83d53
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.cst
@@ -0,0 +1,3 @@
+Date=05/10/2019
+Time=10:23:27
+

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc
new file mode 100644 (file)
index 0000000..5424a21
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc
@@ -0,0 +1,3 @@
+###==== Start Generation
+
+define_attribute  {i:Lane0} {loc} {DCU1_CH1}

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.lpc b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.lpc
new file mode 100644 (file)
index 0000000..6149a02
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.lpc
@@ -0,0 +1,97 @@
+[Device]
+Family=ecp5um
+OperatingCondition=COM
+Package=CABGA756
+PartName=LFE5UM-85F-8BG756C
+PartType=LFE5UM-85F
+SpeedGrade=8
+Status=P
+[IP]
+CoreName=PCS
+CoreRevision=8.2
+CoreStatus=Demo
+CoreType=LPM
+Date=05/10/2019
+ModuleName=serdes_sync_1
+ParameterFileVersion=1.0
+SourceFormat=VHDL
+Time=10:23:27
+VendorName=Lattice Semiconductor Corporation
+[Parameters]
+;ACHARA=0 00H
+;ACHARB=0 00H
+;ACHARM=0 00H
+;RXMCAENABLE=Disabled
+CDRLOLACTION=Full Recalibration
+CDRLOLRANGE=3
+CDR_MAX_RATE=1.25
+CDR_MULT=10X
+CDR_REF_RATE=125.0000
+CH_MODE=Rx and Tx
+Destination=Synplicity
+EDIF=1
+Expression=BusA(0 to 7)
+IO=0
+IO_TYPE=G8B10B
+LEQ=0
+LOOPBACK=Disabled
+LOSPORT=Enabled
+NUM_CHS=1
+Order=Big Endian [MSB:LSB]
+PPORT_RX_RDY=Enabled
+PPORT_TX_RDY=Enabled
+PROTOCOL=G8B10B
+PWAIT_RX_RDY=3000
+PWAIT_TX_RDY=3000
+RCSRC=Disabled
+REFCLK_RATE=125.0000
+RSTSEQSEL=Enabled
+RX8B10B=Enabled
+RXCOMMAA=1100000100
+RXCOMMAB=0011111000
+RXCOMMAM=1111111100
+RXCOUPLING=AC
+RXCTC=Disabled
+RXCTCBYTEN=0 00H
+RXCTCBYTEN1=0 00H
+RXCTCBYTEN2=0 00H
+RXCTCBYTEN3=0 00H
+RXCTCMATCHPATTERN=M4-S4
+RXDIFFTERM=50 ohms
+RXFIFO_ENABLE=Enabled
+RXINVPOL=Non-invert
+RXLDR=Off
+RXLOSTHRESHOLD=4
+RXLSM=Enabled
+RXSC=K28P157
+RXWA=Barrel Shift
+RX_DATA_WIDTH=8/10-Bit
+RX_FICLK_RATE=125.0000
+RX_LINE_RATE=1.2500
+RX_RATE_DIV=Full Rate
+SCIPORT=Enabled
+SOFTLOL=Enabled
+TX8B10B=Enabled
+TXAMPLITUDE=800
+TXDEPOST=Disabled
+TXDEPRE=Disabled
+TXDIFFTERM=50 ohms
+TXFIFO_ENABLE=Enabled
+TXINVPOL=Non-invert
+TXLDR=Off
+TXPLLLOLTHRESHOLD=1
+TXPLLMULT=10X
+TX_DATA_WIDTH=8/10-Bit
+TX_FICLK_RATE=125.0000
+TX_LINE_RATE=1.2500
+TX_MAX_RATE=1.25
+TX_RATE_DIV=Full Rate
+VHDL=1
+Verilog=0
+[FilesGenerated]
+serdes_sync_1.pp=pp
+serdes_sync_1.sym=sym
+serdes_sync_1.tft=tft
+serdes_sync_1.txt=pcs_module
+[SYSTEMPNR]
+LN0=DCU1_CH1

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.ngd b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.ngd
new file mode 100644 (file)
index 0000000..8d07b12
Binary files /dev/null and b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.ngd differ

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.ngo b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.ngo
new file mode 100644 (file)
index 0000000..d20d049
Binary files /dev/null and b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.ngo differ

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd
new file mode 100644 (file)
index 0000000..e119a1a
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd
@@ -0,0 +1,436 @@
+
+--
+-- Verific VHDL Description of module DCUA
+--
+
+-- DCUA is a black-box. Cannot print a valid VHDL entity description for it
+
+--
+-- Verific VHDL Description of module serdes_sync_1rsl_core
+--
+
+-- serdes_sync_1rsl_core is a black-box. Cannot print a valid VHDL entity description for it
+
+--
+-- Verific VHDL Description of module serdes_sync_1sll_core
+--
+
+-- serdes_sync_1sll_core is a black-box. Cannot print a valid VHDL entity description for it
+
+--
+-- Verific VHDL Description of module serdes_sync_1
+--
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+library ecp5um ;
+use ecp5um.components.all ;
+
+entity serdes_sync_1 is
+    port (hdoutp: out std_logic;
+        hdoutn: out std_logic;
+        hdinp: in std_logic;
+        hdinn: in std_logic;
+        rxrefclk: in std_logic;
+        rx_pclk: out std_logic;
+        tx_pclk: out std_logic;
+        txdata: in std_logic_vector(7 downto 0);
+        tx_k: in std_logic_vector(0 downto 0);
+        tx_force_disp: in std_logic_vector(0 downto 0);
+        tx_disp_sel: in std_logic_vector(0 downto 0);
+        rxdata: out std_logic_vector(7 downto 0);
+        rx_k: out std_logic_vector(0 downto 0);
+        rx_disp_err: out std_logic_vector(0 downto 0);
+        rx_cv_err: out std_logic_vector(0 downto 0);
+        tx_idle_c: in std_logic;
+        signal_detect_c: in std_logic;
+        rx_los_low_s: out std_logic;
+        lsm_status_s: out std_logic;
+        rx_cdr_lol_s: out std_logic;
+        sli_rst: in std_logic;
+        tx_pwrup_c: in std_logic;
+        rx_pwrup_c: in std_logic;
+        sci_wrdata: in std_logic_vector(7 downto 0);
+        sci_addr: in std_logic_vector(5 downto 0);
+        sci_rddata: out std_logic_vector(7 downto 0);
+        sci_en_dual: in std_logic;
+        sci_sel_dual: in std_logic;
+        sci_en: in std_logic;
+        sci_sel: in std_logic;
+        sci_rd: in std_logic;
+        sci_wrn: in std_logic;
+        sci_int: out std_logic;
+        cyawstn: in std_logic;
+        serdes_pdb: in std_logic;
+        pll_refclki: in std_logic;
+        rsl_disable: in std_logic;
+        rsl_rst: in std_logic;
+        serdes_rst_dual_c: in std_logic;
+        rst_dual_c: in std_logic;
+        tx_serdes_rst_c: in std_logic;
+        tx_pcs_rst_c: in std_logic;
+        pll_lol: out std_logic;
+        rsl_tx_rdy: out std_logic;
+        rx_serdes_rst_c: in std_logic;
+        rx_pcs_rst_c: in std_logic;
+        rsl_rx_rdy: out std_logic
+    );
+    
+end entity serdes_sync_1;
+
+architecture v1 of serdes_sync_1 is 
+    component serdes_sync_1rsl_core is
+        generic (pnum_channels: integer := 1;
+            pprotocol: string := "G8B10B";
+            pserdes_mode: string := "RX AND TX";
+            pport_tx_rdy: string := "ENABLED";
+            pwait_tx_rdy: integer := 3000;
+            pport_rx_rdy: string := "ENABLED";
+            pwait_rx_rdy: integer := 3000);
+        port (rui_rst: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(132)
+            rui_serdes_rst_dual_c: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(133)
+            rui_rst_dual_c: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(134)
+            rui_rsl_disable: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(135)
+            rui_tx_ref_clk: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(137)
+            rui_tx_serdes_rst_c: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(138)
+            rui_tx_pcs_rst_c: in std_logic_vector(3 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(139)
+            rdi_pll_lol: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(140)
+            rui_rx_ref_clk: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(142)
+            rui_rx_serdes_rst_c: in std_logic_vector(3 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(143)
+            rui_rx_pcs_rst_c: in std_logic_vector(3 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(144)
+            rdi_rx_los_low_s: in std_logic_vector(3 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(145)
+            rdi_rx_cdr_lol_s: in std_logic_vector(3 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(146)
+            rdo_serdes_rst_dual_c: out std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(149)
+            rdo_rst_dual_c: out std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(150)
+            ruo_tx_rdy: out std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(152)
+            rdo_tx_serdes_rst_c: out std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(153)
+            rdo_tx_pcs_rst_c: out std_logic_vector(3 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(154)
+            ruo_rx_rdy: out std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(156)
+            rdo_rx_serdes_rst_c: out std_logic_vector(3 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(157)
+            rdo_rx_pcs_rst_c: out std_logic_vector(3 downto 0)   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(158)
+        );
+        
+    end component serdes_sync_1rsl_core; -- syn_black_box=1    -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(88)
+    component serdes_sync_1sll_core is
+        generic (PPROTOCOL: string := "G8B10B";
+            PLOL_SETTING: integer := 1;
+            PDYN_RATE_CTRL: string := "DISABLED";
+            PPCIE_MAX_RATE: string := "2.5";
+            PDIFF_VAL_LOCK: integer := 39;
+            PDIFF_VAL_UNLOCK: integer := 262;
+            PPCLK_TC: integer := 131072;
+            PDIFF_DIV11_VAL_LOCK: integer := 0;
+            PDIFF_DIV11_VAL_UNLOCK: integer := 0;
+            PPCLK_DIV11_TC: integer := 0);
+        port (sli_rst: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(125)
+            sli_refclk: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(126)
+            sli_pclk: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(127)
+            sli_div2_rate: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(128)
+            sli_div11_rate: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(129)
+            sli_gear_mode: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(130)
+            sli_cpri_mode: in std_logic_vector(2 downto 0);   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(131)
+            sli_pcie_mode: in std_logic;   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(132)
+            slo_plol: out std_logic   -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(135)
+        );
+        
+    end component serdes_sync_1sll_core; -- syn_black_box=1    -- /home/soft/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(107)
+    signal n48,n47,n1,n2,n3,n4,rx_pclk_c,tx_pclk_c,n5,n6,n7,n8,n9,
+        n10,n11,n12,rx_los_low_s_c,n13,n14,n15,n16,rx_cdr_lol_s_c,n17,
+        n18,rsl_tx_pcs_rst_c,rsl_rx_pcs_rst_c,rsl_rx_serdes_rst_c,rsl_rst_dual_c,
+        rsl_serdes_rst_dual_c,rsl_tx_serdes_rst_c,n19,n20,n21,n22,n23,
+        n24,n25,n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37,
+        n38,n39,n40,n41,n42,n43,n44,n45,n46,n49,n106,n105,n50,n51,
+        n52,n53,n54,n55,n56,n57,n58,n59,n60,n61,n62,n63,n64,n65,
+        n66,n67,n68,n69,n70,n71,n72,n73,n74,n75,n76,n77,n78,n79,
+        n80,n81,n82,n83,n84,n85,n86,n87,n88,n89,n90,n91,n92,n93,
+        n94,n95,n96,n97,n98,n99,n100,n101,n102,n103,n104,n115,n114,
+        n113,pll_lol_c,n125,n124,n116,n117,n118,n119,n120,n121,n122,
+        n123,\_Z\,n127,n126,gnd,pwr : std_logic; 
+    attribute LOC : string;
+    attribute LOC of DCU1_inst : label is "DCU1";
+    attribute CHAN : string;
+    attribute CHAN of DCU1_inst : label is "CH1";
+begin
+    rx_pclk <= rx_pclk_c;
+    tx_pclk <= tx_pclk_c;
+    rx_los_low_s <= rx_los_low_s_c;
+    rx_cdr_lol_s <= rx_cdr_lol_s_c;
+    pll_lol <= pll_lol_c;
+    DCU1_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1",
+        D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0",
+        D_CDR_LOL_SET=>"0b11",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1",
+        D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1",
+        D_SYNC_ND_EN=>"0b0",CH1_UC_MODE=>"0b1",CH1_PCIE_MODE=>"0b0",CH1_RIO_MODE=>"0b0",
+        CH1_WA_MODE=>"0b0",CH1_INVERT_RX=>"0b0",CH1_INVERT_TX=>"0b0",CH1_PRBS_SELECTION=>"0b0",
+        CH1_GE_AN_ENABLE=>"0b0",CH1_PRBS_LOCK=>"0b0",CH1_PRBS_ENABLE=>"0b0",
+        CH1_ENABLE_CG_ALIGN=>"0b1",CH1_TX_GEAR_MODE=>"0b0",CH1_RX_GEAR_MODE=>"0b0",
+        CH1_PCS_DET_TIME_SEL=>"0b00",CH1_PCIE_EI_EN=>"0b0",CH1_TX_GEAR_BYPASS=>"0b0",
+        CH1_ENC_BYPASS=>"0b0",CH1_SB_BYPASS=>"0b0",CH1_RX_SB_BYPASS=>"0b0",
+        CH1_WA_BYPASS=>"0b0",CH1_DEC_BYPASS=>"0b0",CH1_CTC_BYPASS=>"0b1",
+        CH1_RX_GEAR_BYPASS=>"0b0",CH1_LSM_DISABLE=>"0b0",CH1_MATCH_2_ENABLE=>"0b0",
+        CH1_MATCH_4_ENABLE=>"0b1",CH1_MIN_IPG_CNT=>"0b11",CH1_CC_MATCH_1=>"0x1BC",
+        CH1_CC_MATCH_2=>"0x11C",CH1_CC_MATCH_3=>"0x11C",CH1_CC_MATCH_4=>"0x11C",
+        CH1_UDF_COMMA_MASK=>"0x0ff",CH1_UDF_COMMA_A=>"0x083",CH1_UDF_COMMA_B=>"0x07C",
+        CH1_RX_DCO_CK_DIV=>"0b010",CH1_RCV_DCC_EN=>"0b0",CH1_TPWDNB=>"0b1",
+        CH1_RATE_MODE_TX=>"0b0",CH1_RTERM_TX=>"0d19",CH1_TX_CM_SEL=>"0b00",
+        CH1_TDRV_PRE_EN=>"0b0",CH1_TDRV_SLICE0_SEL=>"0b00",CH1_TDRV_SLICE1_SEL=>"0b00",
+        CH1_TDRV_SLICE2_SEL=>"0b01",CH1_TDRV_SLICE3_SEL=>"0b01",CH1_TDRV_SLICE4_SEL=>"0b01",
+        CH1_TDRV_SLICE5_SEL=>"0b00",CH1_TDRV_SLICE0_CUR=>"0b000",CH1_TDRV_SLICE1_CUR=>"0b000",
+        CH1_TDRV_SLICE2_CUR=>"0b11",CH1_TDRV_SLICE3_CUR=>"0b11",CH1_TDRV_SLICE4_CUR=>"0b01",
+        CH1_TDRV_SLICE5_CUR=>"0b00",CH1_TDRV_DAT_SEL=>"0b00",CH1_TX_DIV11_SEL=>"0b0",
+        CH1_RPWDNB=>"0b1",CH1_RATE_MODE_RX=>"0b0",CH1_RX_DIV11_SEL=>"0b0",
+        CH1_SEL_SD_RX_CLK=>"0b1",CH1_FF_RX_H_CLK_EN=>"0b0",CH1_FF_RX_F_CLK_DIS=>"0b0",
+        CH1_FF_TX_H_CLK_EN=>"0b0",CH1_FF_TX_F_CLK_DIS=>"0b0",CH1_TDRV_POST_EN=>"0b0",
+        CH1_TX_POST_SIGN=>"0b0",CH1_TX_PRE_SIGN=>"0b0",CH1_REQ_LVL_SET=>"0b00",
+        CH1_REQ_EN=>"0b1",CH1_RTERM_RX=>"0d22",CH1_RXTERM_CM=>"0b11",CH1_PDEN_SEL=>"0b1",
+        CH1_RXIN_CM=>"0b11",CH1_LEQ_OFFSET_SEL=>"0b0",CH1_LEQ_OFFSET_TRIM=>"0b000",
+        CH1_RLOS_SEL=>"0b1",CH1_RX_LOS_LVL=>"0b100",CH1_RX_LOS_CEQ=>"0b11",
+        CH1_RX_LOS_HYST_EN=>"0b0",CH1_RX_LOS_EN=>"0b1",CH1_LDR_RX2CORE_SEL=>"0b0",
+        CH1_LDR_CORE2TX_SEL=>"0b0",D_TX_MAX_RATE=>"1.25",CH1_CDR_MAX_RATE=>"1.25",
+        CH1_TXAMPLITUDE=>"0d800",CH1_TXDEPRE=>"DISABLED",CH1_TXDEPOST=>"DISABLED",
+        CH1_PROTOCOL=>"G8B10B",D_ISETLOS=>"0d0",D_SETIRPOLY_AUX=>"0b00",D_SETICONST_AUX=>"0b00",
+        D_SETIRPOLY_CH=>"0b00",D_SETICONST_CH=>"0b00",D_REQ_ISET=>"0b000",
+        D_PD_ISET=>"0b00",D_DCO_CALIB_TIME_SEL=>"0b00",CH1_CDR_CNT4SEL=>"0b00",
+        CH1_CDR_CNT8SEL=>"0b00",CH1_DCOATDCFG=>"0b00",CH1_DCOATDDLY=>"0b00",
+        CH1_DCOBYPSATD=>"0b1",CH1_DCOCALDIV=>"0b001",CH1_DCOCTLGI=>"0b010",
+        CH1_DCODISBDAVOID=>"0b0",CH1_DCOFLTDAC=>"0b01",CH1_DCOFTNRG=>"0b110",
+        CH1_DCOIOSTUNE=>"0b000",CH1_DCOITUNE=>"0b00",CH1_DCOITUNE4LSB=>"0b111",
+        CH1_DCOIUPDNX2=>"0b1",CH1_DCONUOFLSB=>"0b101",CH1_DCOSCALEI=>"0b00",
+        CH1_DCOSTARTVAL=>"0b000",CH1_DCOSTEP=>"0b00",CH1_BAND_THRESHOLD=>"0d0",
+        CH1_AUTO_FACQ_EN=>"0b1",CH1_AUTO_CALIB_EN=>"0b1",CH1_CALIB_CK_MODE=>"0b0",
+        CH1_REG_BAND_OFFSET=>"0d0",CH1_REG_BAND_SEL=>"0d0",CH1_REG_IDAC_SEL=>"0d0",
+        CH1_REG_IDAC_EN=>"0b0",D_CMUSETISCL4VCO=>"0b000",D_CMUSETI4VCO=>"0b00",
+        D_CMUSETINITVCT=>"0b00",D_CMUSETZGM=>"0b000",D_CMUSETP2AGM=>"0b000",
+        D_CMUSETP1GM=>"0b000",D_CMUSETI4CPZ=>"0d0",D_CMUSETI4CPP=>"0d0",D_CMUSETICP4Z=>"0b101",
+        D_CMUSETICP4P=>"0b11",D_CMUSETBIASI=>"0b00",D_SETPLLRC=>"0d1",CH1_RX_RATE_SEL=>"0d10",
+        D_REFCK_MODE=>"0b001",D_TX_VCO_CK_DIV=>"0b010",D_PLL_LOL_SET=>"0b01",
+        D_RG_EN=>"0b0",D_RG_SET=>"0b00")
+     port map (CH0_HDINP=>n106,CH1_HDINP=>hdinp,CH0_HDINN=>n106,CH1_HDINN=>hdinn,
+    D_TXBIT_CLKP_FROM_ND=>n47,D_TXBIT_CLKN_FROM_ND=>n47,D_SYNC_ND=>n47,D_TXPLL_LOL_FROM_ND=>n47,
+    CH0_RX_REFCLK=>n106,CH1_RX_REFCLK=>rxrefclk,CH0_FF_RXI_CLK=>n105,CH1_FF_RXI_CLK=>rx_pclk_c,
+    CH0_FF_TXI_CLK=>n105,CH1_FF_TXI_CLK=>tx_pclk_c,CH0_FF_EBRD_CLK=>n105,
+    CH1_FF_EBRD_CLK=>n48,CH0_FF_TX_D_0=>n106,CH1_FF_TX_D_0=>txdata(0),CH0_FF_TX_D_1=>n106,
+    CH1_FF_TX_D_1=>txdata(1),CH0_FF_TX_D_2=>n106,CH1_FF_TX_D_2=>txdata(2),
+    CH0_FF_TX_D_3=>n106,CH1_FF_TX_D_3=>txdata(3),CH0_FF_TX_D_4=>n106,CH1_FF_TX_D_4=>txdata(4),
+    CH0_FF_TX_D_5=>n106,CH1_FF_TX_D_5=>txdata(5),CH0_FF_TX_D_6=>n106,CH1_FF_TX_D_6=>txdata(6),
+    CH0_FF_TX_D_7=>n106,CH1_FF_TX_D_7=>txdata(7),CH0_FF_TX_D_8=>n106,CH1_FF_TX_D_8=>tx_k(0),
+    CH0_FF_TX_D_9=>n106,CH1_FF_TX_D_9=>tx_force_disp(0),CH0_FF_TX_D_10=>n106,
+    CH1_FF_TX_D_10=>tx_disp_sel(0),CH0_FF_TX_D_11=>n106,CH1_FF_TX_D_11=>n47,
+    CH0_FF_TX_D_12=>n106,CH1_FF_TX_D_12=>n106,CH0_FF_TX_D_13=>n106,CH1_FF_TX_D_13=>n106,
+    CH0_FF_TX_D_14=>n106,CH1_FF_TX_D_14=>n106,CH0_FF_TX_D_15=>n106,CH1_FF_TX_D_15=>n106,
+    CH0_FF_TX_D_16=>n106,CH1_FF_TX_D_16=>n106,CH0_FF_TX_D_17=>n106,CH1_FF_TX_D_17=>n106,
+    CH0_FF_TX_D_18=>n106,CH1_FF_TX_D_18=>n106,CH0_FF_TX_D_19=>n106,CH1_FF_TX_D_19=>n106,
+    CH0_FF_TX_D_20=>n106,CH1_FF_TX_D_20=>n106,CH0_FF_TX_D_21=>n106,CH1_FF_TX_D_21=>n106,
+    CH0_FF_TX_D_22=>n106,CH1_FF_TX_D_22=>n106,CH0_FF_TX_D_23=>n106,CH1_FF_TX_D_23=>n47,
+    CH0_FFC_EI_EN=>n106,CH1_FFC_EI_EN=>tx_idle_c,CH0_FFC_PCIE_DET_EN=>n106,
+    CH1_FFC_PCIE_DET_EN=>n47,CH0_FFC_PCIE_CT=>n106,CH1_FFC_PCIE_CT=>n47,CH0_FFC_SB_INV_RX=>n106,
+    CH1_FFC_SB_INV_RX=>n106,CH0_FFC_ENABLE_CGALIGN=>n106,CH1_FFC_ENABLE_CGALIGN=>n106,
+    CH0_FFC_SIGNAL_DETECT=>n106,CH1_FFC_SIGNAL_DETECT=>signal_detect_c,CH0_FFC_FB_LOOPBACK=>n106,
+    CH1_FFC_FB_LOOPBACK=>n47,CH0_FFC_SB_PFIFO_LP=>n106,CH1_FFC_SB_PFIFO_LP=>n47,
+    CH0_FFC_PFIFO_CLR=>n106,CH1_FFC_PFIFO_CLR=>n47,CH0_FFC_RATE_MODE_RX=>n106,
+    CH1_FFC_RATE_MODE_RX=>n106,CH0_FFC_RATE_MODE_TX=>n106,CH1_FFC_RATE_MODE_TX=>n106,
+    CH0_FFC_DIV11_MODE_RX=>n106,CH1_FFC_DIV11_MODE_RX=>n47,CH0_FFC_DIV11_MODE_TX=>n106,
+    CH1_FFC_DIV11_MODE_TX=>n47,CH0_FFC_RX_GEAR_MODE=>n106,CH1_FFC_RX_GEAR_MODE=>n47,
+    CH0_FFC_TX_GEAR_MODE=>n106,CH1_FFC_TX_GEAR_MODE=>n47,CH0_FFC_LDR_CORE2TX_EN=>n106,
+    CH1_FFC_LDR_CORE2TX_EN=>n106,CH0_FFC_LANE_TX_RST=>n106,CH1_FFC_LANE_TX_RST=>rsl_tx_pcs_rst_c,
+    CH0_FFC_LANE_RX_RST=>n106,CH1_FFC_LANE_RX_RST=>rsl_rx_pcs_rst_c,CH0_FFC_RRST=>n106,
+    CH1_FFC_RRST=>rsl_rx_serdes_rst_c,CH0_FFC_TXPWDNB=>n106,CH1_FFC_TXPWDNB=>tx_pwrup_c,
+    CH0_FFC_RXPWDNB=>n106,CH1_FFC_RXPWDNB=>rx_pwrup_c,CH0_LDR_CORE2TX=>n106,
+    CH1_LDR_CORE2TX=>n106,D_SCIWDATA0=>sci_wrdata(0),D_SCIWDATA1=>sci_wrdata(1),
+    D_SCIWDATA2=>sci_wrdata(2),D_SCIWDATA3=>sci_wrdata(3),D_SCIWDATA4=>sci_wrdata(4),
+    D_SCIWDATA5=>sci_wrdata(5),D_SCIWDATA6=>sci_wrdata(6),D_SCIWDATA7=>sci_wrdata(7),
+    D_SCIADDR0=>sci_addr(0),D_SCIADDR1=>sci_addr(1),D_SCIADDR2=>sci_addr(2),
+    D_SCIADDR3=>sci_addr(3),D_SCIADDR4=>sci_addr(4),D_SCIADDR5=>sci_addr(5),
+    D_SCIENAUX=>sci_en_dual,D_SCISELAUX=>sci_sel_dual,CH0_SCIEN=>n106,CH1_SCIEN=>sci_en,
+    CH0_SCISEL=>n106,CH1_SCISEL=>sci_sel,D_SCIRD=>sci_rd,D_SCIWSTN=>sci_wrn,
+    D_CYAWSTN=>cyawstn,D_FFC_SYNC_TOGGLE=>n106,D_FFC_DUAL_RST=>rsl_rst_dual_c,
+    D_FFC_MACRO_RST=>rsl_serdes_rst_dual_c,D_FFC_MACROPDB=>serdes_pdb,D_FFC_TRST=>rsl_tx_serdes_rst_c,
+    CH0_FFC_CDR_EN_BITSLIP=>n106,CH1_FFC_CDR_EN_BITSLIP=>n47,D_SCAN_ENABLE=>n47,
+    D_SCAN_IN_0=>n47,D_SCAN_IN_1=>n47,D_SCAN_IN_2=>n47,D_SCAN_IN_3=>n47,
+    D_SCAN_IN_4=>n47,D_SCAN_IN_5=>n47,D_SCAN_IN_6=>n47,D_SCAN_IN_7=>n47,
+    D_SCAN_MODE=>n47,D_SCAN_RESET=>n47,D_CIN0=>n47,D_CIN1=>n47,D_CIN2=>n47,
+    D_CIN3=>n47,D_CIN4=>n47,D_CIN5=>n47,D_CIN6=>n47,D_CIN7=>n47,D_CIN8=>n47,
+    D_CIN9=>n47,D_CIN10=>n47,D_CIN11=>n47,CH0_HDOUTP=>n50,CH1_HDOUTP=>hdoutp,
+    CH0_HDOUTN=>n51,CH1_HDOUTN=>hdoutn,D_TXBIT_CLKP_TO_ND=>n1,D_TXBIT_CLKN_TO_ND=>n2,
+    D_SYNC_PULSE2ND=>n3,D_TXPLL_LOL_TO_ND=>n4,CH0_FF_RX_F_CLK=>n52,CH1_FF_RX_F_CLK=>n5,
+    CH0_FF_RX_H_CLK=>n53,CH1_FF_RX_H_CLK=>n6,CH0_FF_TX_F_CLK=>n54,CH1_FF_TX_F_CLK=>n7,
+    CH0_FF_TX_H_CLK=>n55,CH1_FF_TX_H_CLK=>n8,CH0_FF_RX_PCLK=>n56,CH1_FF_RX_PCLK=>rx_pclk_c,
+    CH0_FF_TX_PCLK=>n57,CH1_FF_TX_PCLK=>tx_pclk_c,CH0_FF_RX_D_0=>n58,CH1_FF_RX_D_0=>rxdata(0),
+    CH0_FF_RX_D_1=>n59,CH1_FF_RX_D_1=>rxdata(1),CH0_FF_RX_D_2=>n60,CH1_FF_RX_D_2=>rxdata(2),
+    CH0_FF_RX_D_3=>n61,CH1_FF_RX_D_3=>rxdata(3),CH0_FF_RX_D_4=>n62,CH1_FF_RX_D_4=>rxdata(4),
+    CH0_FF_RX_D_5=>n63,CH1_FF_RX_D_5=>rxdata(5),CH0_FF_RX_D_6=>n64,CH1_FF_RX_D_6=>rxdata(6),
+    CH0_FF_RX_D_7=>n65,CH1_FF_RX_D_7=>rxdata(7),CH0_FF_RX_D_8=>n66,CH1_FF_RX_D_8=>rx_k(0),
+    CH0_FF_RX_D_9=>n67,CH1_FF_RX_D_9=>rx_disp_err(0),CH0_FF_RX_D_10=>n68,
+    CH1_FF_RX_D_10=>rx_cv_err(0),CH0_FF_RX_D_11=>n69,CH1_FF_RX_D_11=>n9,CH0_FF_RX_D_12=>n70,
+    CH1_FF_RX_D_12=>n71,CH0_FF_RX_D_13=>n72,CH1_FF_RX_D_13=>n73,CH0_FF_RX_D_14=>n74,
+    CH1_FF_RX_D_14=>n75,CH0_FF_RX_D_15=>n76,CH1_FF_RX_D_15=>n77,CH0_FF_RX_D_16=>n78,
+    CH1_FF_RX_D_16=>n79,CH0_FF_RX_D_17=>n80,CH1_FF_RX_D_17=>n81,CH0_FF_RX_D_18=>n82,
+    CH1_FF_RX_D_18=>n83,CH0_FF_RX_D_19=>n84,CH1_FF_RX_D_19=>n85,CH0_FF_RX_D_20=>n86,
+    CH1_FF_RX_D_20=>n87,CH0_FF_RX_D_21=>n88,CH1_FF_RX_D_21=>n89,CH0_FF_RX_D_22=>n90,
+    CH1_FF_RX_D_22=>n91,CH0_FF_RX_D_23=>n92,CH1_FF_RX_D_23=>n10,CH0_FFS_PCIE_DONE=>n93,
+    CH1_FFS_PCIE_DONE=>n11,CH0_FFS_PCIE_CON=>n94,CH1_FFS_PCIE_CON=>n12,CH0_FFS_RLOS=>n95,
+    CH1_FFS_RLOS=>rx_los_low_s_c,CH0_FFS_LS_SYNC_STATUS=>n96,CH1_FFS_LS_SYNC_STATUS=>lsm_status_s,
+    CH0_FFS_CC_UNDERRUN=>n97,CH1_FFS_CC_UNDERRUN=>n13,CH0_FFS_CC_OVERRUN=>n98,
+    CH1_FFS_CC_OVERRUN=>n14,CH0_FFS_RXFBFIFO_ERROR=>n99,CH1_FFS_RXFBFIFO_ERROR=>n15,
+    CH0_FFS_TXFBFIFO_ERROR=>n100,CH1_FFS_TXFBFIFO_ERROR=>n16,CH0_FFS_RLOL=>n101,
+    CH1_FFS_RLOL=>rx_cdr_lol_s_c,CH0_FFS_SKP_ADDED=>n102,CH1_FFS_SKP_ADDED=>n17,
+    CH0_FFS_SKP_DELETED=>n103,CH1_FFS_SKP_DELETED=>n18,CH0_LDR_RX2CORE=>n104,
+    CH1_LDR_RX2CORE=>n115,D_SCIRDATA0=>sci_rddata(0),D_SCIRDATA1=>sci_rddata(1),
+    D_SCIRDATA2=>sci_rddata(2),D_SCIRDATA3=>sci_rddata(3),D_SCIRDATA4=>sci_rddata(4),
+    D_SCIRDATA5=>sci_rddata(5),D_SCIRDATA6=>sci_rddata(6),D_SCIRDATA7=>sci_rddata(7),
+    D_SCIINT=>sci_int,D_SCAN_OUT_0=>n19,D_SCAN_OUT_1=>n20,D_SCAN_OUT_2=>n21,
+    D_SCAN_OUT_3=>n22,D_SCAN_OUT_4=>n23,D_SCAN_OUT_5=>n24,D_SCAN_OUT_6=>n25,
+    D_SCAN_OUT_7=>n26,D_COUT0=>n27,D_COUT1=>n28,D_COUT2=>n29,D_COUT3=>n30,
+    D_COUT4=>n31,D_COUT5=>n32,D_COUT6=>n33,D_COUT7=>n34,D_COUT8=>n35,D_COUT9=>n36,
+    D_COUT10=>n37,D_COUT11=>n38,D_COUT12=>n39,D_COUT13=>n40,D_COUT14=>n41,
+    D_COUT15=>n42,D_COUT16=>n43,D_COUT17=>n44,D_COUT18=>n45,D_COUT19=>n46,
+    D_REFCLKI=>pll_refclki,D_FFS_PLOL=>n49);
+    n48 <= '1' ;
+    n47 <= '0' ;
+    n1 <= 'Z' ;
+    n2 <= 'Z' ;
+    n3 <= 'Z' ;
+    n4 <= 'Z' ;
+    n5 <= 'Z' ;
+    n6 <= 'Z' ;
+    n7 <= 'Z' ;
+    n8 <= 'Z' ;
+    n9 <= 'Z' ;
+    n10 <= 'Z' ;
+    n11 <= 'Z' ;
+    n12 <= 'Z' ;
+    n13 <= 'Z' ;
+    n14 <= 'Z' ;
+    n15 <= 'Z' ;
+    n16 <= 'Z' ;
+    n17 <= 'Z' ;
+    n18 <= 'Z' ;
+    n19 <= 'Z' ;
+    n20 <= 'Z' ;
+    n21 <= 'Z' ;
+    n22 <= 'Z' ;
+    n23 <= 'Z' ;
+    n24 <= 'Z' ;
+    n25 <= 'Z' ;
+    n26 <= 'Z' ;
+    n27 <= 'Z' ;
+    n28 <= 'Z' ;
+    n29 <= 'Z' ;
+    n30 <= 'Z' ;
+    n31 <= 'Z' ;
+    n32 <= 'Z' ;
+    n33 <= 'Z' ;
+    n34 <= 'Z' ;
+    n35 <= 'Z' ;
+    n36 <= 'Z' ;
+    n37 <= 'Z' ;
+    n38 <= 'Z' ;
+    n39 <= 'Z' ;
+    n40 <= 'Z' ;
+    n41 <= 'Z' ;
+    n42 <= 'Z' ;
+    n43 <= 'Z' ;
+    n44 <= 'Z' ;
+    n45 <= 'Z' ;
+    n46 <= 'Z' ;
+    n49 <= 'Z' ;
+    n106 <= '0' ;
+    n105 <= '1' ;
+    n50 <= 'Z' ;
+    n51 <= 'Z' ;
+    n52 <= 'Z' ;
+    n53 <= 'Z' ;
+    n54 <= 'Z' ;
+    n55 <= 'Z' ;
+    n56 <= 'Z' ;
+    n57 <= 'Z' ;
+    n58 <= 'Z' ;
+    n59 <= 'Z' ;
+    n60 <= 'Z' ;
+    n61 <= 'Z' ;
+    n62 <= 'Z' ;
+    n63 <= 'Z' ;
+    n64 <= 'Z' ;
+    n65 <= 'Z' ;
+    n66 <= 'Z' ;
+    n67 <= 'Z' ;
+    n68 <= 'Z' ;
+    n69 <= 'Z' ;
+    n70 <= 'Z' ;
+    n71 <= 'Z' ;
+    n72 <= 'Z' ;
+    n73 <= 'Z' ;
+    n74 <= 'Z' ;
+    n75 <= 'Z' ;
+    n76 <= 'Z' ;
+    n77 <= 'Z' ;
+    n78 <= 'Z' ;
+    n79 <= 'Z' ;
+    n80 <= 'Z' ;
+    n81 <= 'Z' ;
+    n82 <= 'Z' ;
+    n83 <= 'Z' ;
+    n84 <= 'Z' ;
+    n85 <= 'Z' ;
+    n86 <= 'Z' ;
+    n87 <= 'Z' ;
+    n88 <= 'Z' ;
+    n89 <= 'Z' ;
+    n90 <= 'Z' ;
+    n91 <= 'Z' ;
+    n92 <= 'Z' ;
+    n93 <= 'Z' ;
+    n94 <= 'Z' ;
+    n95 <= 'Z' ;
+    n96 <= 'Z' ;
+    n97 <= 'Z' ;
+    n98 <= 'Z' ;
+    n99 <= 'Z' ;
+    n100 <= 'Z' ;
+    n101 <= 'Z' ;
+    n102 <= 'Z' ;
+    n103 <= 'Z' ;
+    n104 <= 'Z' ;
+    n115 <= 'Z' ;
+    rsl_inst: component serdes_sync_1rsl_core port map (rui_rst=>rsl_rst,rui_serdes_rst_dual_c=>serdes_rst_dual_c,
+            rui_rst_dual_c=>rst_dual_c,rui_rsl_disable=>rsl_disable,rui_tx_ref_clk=>pll_refclki,
+            rui_tx_serdes_rst_c=>tx_serdes_rst_c,rui_tx_pcs_rst_c(3)=>n125,
+            rui_tx_pcs_rst_c(2)=>n125,rui_tx_pcs_rst_c(1)=>n125,rui_tx_pcs_rst_c(0)=>tx_pcs_rst_c,
+            rdi_pll_lol=>pll_lol_c,rui_rx_ref_clk=>rxrefclk,rui_rx_serdes_rst_c(3)=>n125,
+            rui_rx_serdes_rst_c(2)=>n125,rui_rx_serdes_rst_c(1)=>n125,rui_rx_serdes_rst_c(0)=>rx_serdes_rst_c,
+            rui_rx_pcs_rst_c(3)=>n125,rui_rx_pcs_rst_c(2)=>n125,rui_rx_pcs_rst_c(1)=>n125,
+            rui_rx_pcs_rst_c(0)=>rx_pcs_rst_c,rdi_rx_los_low_s(3)=>n125,rdi_rx_los_low_s(2)=>n125,
+            rdi_rx_los_low_s(1)=>n125,rdi_rx_los_low_s(0)=>rx_los_low_s_c,
+            rdi_rx_cdr_lol_s(3)=>n125,rdi_rx_cdr_lol_s(2)=>n125,rdi_rx_cdr_lol_s(1)=>n125,
+            rdi_rx_cdr_lol_s(0)=>rx_cdr_lol_s_c,rdo_serdes_rst_dual_c=>rsl_serdes_rst_dual_c,
+            rdo_rst_dual_c=>rsl_rst_dual_c,ruo_tx_rdy=>rsl_tx_rdy,rdo_tx_serdes_rst_c=>rsl_tx_serdes_rst_c,
+            rdo_tx_pcs_rst_c(3)=>n116,rdo_tx_pcs_rst_c(2)=>n117,rdo_tx_pcs_rst_c(1)=>n118,
+            rdo_tx_pcs_rst_c(0)=>rsl_tx_pcs_rst_c,ruo_rx_rdy=>rsl_rx_rdy,rdo_rx_serdes_rst_c(3)=>n119,
+            rdo_rx_serdes_rst_c(2)=>n120,rdo_rx_serdes_rst_c(1)=>n121,rdo_rx_serdes_rst_c(0)=>rsl_rx_serdes_rst_c,
+            rdo_rx_pcs_rst_c(3)=>n122,rdo_rx_pcs_rst_c(2)=>n123,rdo_rx_pcs_rst_c(1)=>\_Z\,
+            rdo_rx_pcs_rst_c(0)=>rsl_rx_pcs_rst_c);
+    n114 <= '1' ;
+    n113 <= '0' ;
+    n125 <= '0' ;
+    n124 <= '1' ;
+    n116 <= 'Z' ;
+    n117 <= 'Z' ;
+    n118 <= 'Z' ;
+    n119 <= 'Z' ;
+    n120 <= 'Z' ;
+    n121 <= 'Z' ;
+    n122 <= 'Z' ;
+    n123 <= 'Z' ;
+    \_Z\ <= 'Z' ;
+    sll_inst: component serdes_sync_1sll_core port map (sli_rst=>sli_rst,sli_refclk=>pll_refclki,
+            sli_pclk=>tx_pclk_c,sli_div2_rate=>gnd,sli_div11_rate=>gnd,sli_gear_mode=>gnd,
+            sli_cpri_mode(2)=>gnd,sli_cpri_mode(1)=>gnd,sli_cpri_mode(0)=>gnd,
+            sli_pcie_mode=>gnd,slo_plol=>pll_lol_c);
+    n127 <= '1' ;
+    n126 <= '0' ;
+    gnd <= '0' ;
+    pwr <= '1' ;
+    
+end architecture v1;
+

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_ngd.asd b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_ngd.asd
new file mode 100644 (file)
index 0000000..c265c78
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_ngd.asd
@@ -0,0 +1 @@
+[ActiveSupport NGD]

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v
new file mode 100644 (file)
index 0000000..ec34b40
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v
@@ -0,0 +1,2003 @@
+
+
+//   ===========================================================================
+//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
+//   ---------------------------------------------------------------------------
+//   Copyright (c) 2016 by Lattice Semiconductor Corporation
+//   ALL RIGHTS RESERVED
+//   ------------------------------------------------------------------
+//
+//   Permission:
+//
+//      Lattice SG Pte. Ltd. grants permission to use this code
+//      pursuant to the terms of the Lattice Reference Design License Agreement.
+//
+//
+//   Disclaimer:
+//
+//      This VHDL or Verilog source code is intended as a design reference
+//      which illustrates how these types of functions can be implemented.
+//      It is the user's responsibility to verify their design for
+//      consistency and functionality through the use of formal
+//      verification methods.  Lattice provides no warranty
+//      regarding the use or functionality of this code.
+//
+//   ---------------------------------------------------------------------------
+//
+//                  Lattice SG Pte. Ltd.
+//                  101 Thomson Road, United Square #07-02
+//                  Singapore 307591
+//
+//
+//                  TEL: 1-800-Lattice (USA and Canada)
+//                       +65-6631-2000 (Singapore)
+//                       +1-503-268-8001 (other locations)
+//
+//                  web: http://www.latticesemi.com/
+//                  email: techsupport@latticesemi.com
+//
+//   ---------------------------------------------------------------------------
+//
+// =============================================================================
+//                         FILE DETAILS
+// Project               : RSL- Reset Sequence Logic
+// File                  : rsl_core.v
+// Title                 : Top-level file for RSL
+// Dependencies          : 1.
+//                       : 2.
+// Description           :
+// =============================================================================
+//                        REVISION HISTORY
+// Version               : 1.0
+// Author(s)             : BM
+// Mod. Date             : October 28, 2013
+// Changes Made          : Initial Creation
+// -----------------------------------------------------------------------------
+// Version               : 1.1
+// Author(s)             : BM
+// Mod. Date             : November 06, 2013
+// Changes Made          : Tx/Rx separation, ready port code exclusion
+// -----------------------------------------------------------------------------
+// Version               : 1.2
+// Author(s)             : BM
+// Mod. Date             : June 13, 2014
+// Changes Made          : Updated Rx PCS reset method
+// -----------------------------------------------------------------------------
+// -----------------------------------------------------------------------------
+// Version               : 1.3
+// Author(s)             : UA
+// Mod. Date             : Dec 19, 2014
+// Changes Made          : Added new parameter fro PCIE
+// -----------------------------------------------------------------------------
+// Version               : 1.31
+// Author(s)             : BM/UM
+// Mod. Date             : Feb 23, 2016
+// Changes Made          : Behavior of rx_rdy output modified. The output rx_rdy
+//                         and the rx_rdy wait counter are reset to zero on
+//                         LOL or LOS. Reverted back the counter value change for PCIE.
+// -----------------------------------------------------------------------------
+// Version               : 1.4
+// Author(s)             : EB
+// Mod. Date:            : March 21, 2017
+// Changes Made          :
+// -----------------------------------------------------------------------------
+// Version               : 1.5
+// Author(s)             : ES
+// Mod. Date:            : May 8, 2017
+// Changes Made          : Implemented common RSL behaviour as proposed by BM.
+// =============================================================================
+
+`timescale 1ns/10ps
+
+module serdes_sync_1rsl_core (
+      // ------------ Inputs
+      // Common
+      rui_rst,               // Active high reset for the RSL module
+      rui_serdes_rst_dual_c, // SERDES macro reset user command
+      rui_rst_dual_c,        // PCS dual reset user command
+      rui_rsl_disable,       // Active high signal that disables all reset outputs of RSL
+      // Tx
+      rui_tx_ref_clk,        // Tx reference clock
+      rui_tx_serdes_rst_c,   // Tx SERDES reset user command
+      rui_tx_pcs_rst_c,      // Tx lane reset user command
+      rdi_pll_lol,           // Tx PLL Loss of Lock status input from the SERDES
+      // Rx
+      rui_rx_ref_clk,        // Rx reference clock
+      rui_rx_serdes_rst_c,   // SERDES Receive channel reset user command
+      rui_rx_pcs_rst_c,      // Rx lane reset user command
+      rdi_rx_los_low_s,      // Receive loss of signal status input from SERDES
+      rdi_rx_cdr_lol_s,      // Receive CDR loss of lock status input from SERDES
+
+      // ------------ Outputs
+      // Common
+      rdo_serdes_rst_dual_c, // SERDES macro reset command output
+      rdo_rst_dual_c,        // PCS dual reset command output
+      // Tx
+      ruo_tx_rdy,            // Tx lane ready status output
+      rdo_tx_serdes_rst_c,   // SERDES Tx reset command output
+      rdo_tx_pcs_rst_c,      // PCS Tx lane reset command output
+      // Rx
+      ruo_rx_rdy,            // Rx lane ready status output
+      rdo_rx_serdes_rst_c,   // SERDES Rx channel reset command output
+      rdo_rx_pcs_rst_c       // PCS Rx lane reset command output
+      );
+
+// ------------ Module parameters
+`ifdef NUM_CHANNELS
+   parameter pnum_channels = `NUM_CHANNELS;    // 1,2,4
+`else
+   parameter pnum_channels = 1;
+`endif
+
+`ifdef PCIE
+   parameter pprotocol    = "PCIE";
+`else
+   parameter pprotocol    = "";
+`endif
+
+`ifdef RX_ONLY
+   parameter pserdes_mode    = "RX ONLY";
+`else
+   `ifdef TX_ONLY
+      parameter pserdes_mode = "TX ONLY";
+   `else
+      parameter pserdes_mode = "RX AND TX";
+   `endif
+`endif
+
+`ifdef PORT_TX_RDY
+   parameter pport_tx_rdy = "ENABLED";
+`else
+   parameter pport_tx_rdy = "DISABLED";
+`endif
+
+`ifdef WAIT_TX_RDY
+   parameter pwait_tx_rdy = `WAIT_TX_RDY;
+`else
+   parameter pwait_tx_rdy = 3000;
+`endif
+
+`ifdef PORT_RX_RDY
+   parameter pport_rx_rdy = "ENABLED";
+`else
+   parameter pport_rx_rdy = "DISABLED";
+`endif
+
+`ifdef WAIT_RX_RDY
+   parameter pwait_rx_rdy = `WAIT_RX_RDY;
+`else
+   parameter pwait_rx_rdy = 3000;
+`endif
+
+// ------------ Local parameters
+   localparam wa_num_cycles      = 1024;
+   localparam dac_num_cycles     = 3;
+   localparam lreset_pwidth      = 3;      // reset pulse width-1, default=4-1=3
+   localparam lwait_b4_trst      = 781250; // 5ms wait with worst-case Fmax=156 MHz
+   localparam lwait_b4_trst_s    = 781;    // for simulation
+   localparam lplol_cnt_width    = 20;     // width for lwait_b4_trst
+   localparam lwait_after_plol0  = 4;
+   localparam lwait_b4_rrst      = 180224; // total calibration time
+   localparam lrrst_wait_width   = 20;
+   localparam lwait_after_rrst   = 800000; // For CPRI- unused
+   localparam lwait_b4_rrst_s    = 460;    // wait cycles provided by design team
+   localparam lrlol_cnt_width    = 19;     // width for lwait_b4_rrst
+   localparam lwait_after_lols   = (16384 * dac_num_cycles) + wa_num_cycles;  // 16384 cycles * dac_num_cycles + 1024 cycles
+   localparam lwait_after_lols_s = 150;    // wait cycles provided by design team
+   localparam llols_cnt_width    = 18;     // lols count width
+   localparam lrdb_max           = 15;     // maximum debounce count
+   localparam ltxr_wait_width    = 12;     // width of tx ready wait counter
+   localparam lrxr_wait_width    = 12;     // width of tx ready wait counter
+
+// ------------ input ports
+   input                         rui_rst;
+   input                         rui_serdes_rst_dual_c;
+   input                         rui_rst_dual_c;
+   input                         rui_rsl_disable;
+
+   input                         rui_tx_ref_clk;
+   input                         rui_tx_serdes_rst_c;
+   input  [3:0]                  rui_tx_pcs_rst_c;
+   input                         rdi_pll_lol;
+
+   input                         rui_rx_ref_clk;
+   input  [3:0]                  rui_rx_serdes_rst_c;
+   input  [3:0]                  rui_rx_pcs_rst_c;
+   input  [3:0]                  rdi_rx_los_low_s;
+   input  [3:0]                  rdi_rx_cdr_lol_s;
+
+// ------------ output ports
+   output                        rdo_serdes_rst_dual_c;
+   output                        rdo_rst_dual_c;
+
+   output                        ruo_tx_rdy;
+   output                        rdo_tx_serdes_rst_c;
+   output [3:0]                  rdo_tx_pcs_rst_c;
+
+   output                        ruo_rx_rdy;
+   output [3:0]                  rdo_rx_serdes_rst_c;
+   output [3:0]                  rdo_rx_pcs_rst_c;
+
+// ------------ Internal registers and wires
+   // inputs
+   wire                          rui_rst;
+   wire                          rui_serdes_rst_dual_c;
+   wire                          rui_rst_dual_c;
+   wire                          rui_rsl_disable;
+   wire                          rui_tx_ref_clk;
+   wire                          rui_tx_serdes_rst_c;
+   wire   [3:0]                  rui_tx_pcs_rst_c;
+   wire                          rdi_pll_lol;
+   wire                          rui_rx_ref_clk;
+   wire   [3:0]                  rui_rx_serdes_rst_c;
+   wire   [3:0]                  rui_rx_pcs_rst_c;
+   wire   [3:0]                  rdi_rx_los_low_s;
+   wire   [3:0]                  rdi_rx_cdr_lol_s;
+
+   // outputs
+   wire                          rdo_serdes_rst_dual_c;
+   wire                          rdo_rst_dual_c;
+   wire                          ruo_tx_rdy;
+   wire                          rdo_tx_serdes_rst_c;
+   wire   [3:0]                  rdo_tx_pcs_rst_c;
+   wire                          ruo_rx_rdy;
+   wire   [3:0]                  rdo_rx_serdes_rst_c;
+   wire   [3:0]                  rdo_rx_pcs_rst_c;
+
+   // internal signals
+   // common
+   wire                          rsl_enable;
+   wire   [lplol_cnt_width-1:0]  wait_b4_trst;
+   wire   [lrlol_cnt_width-1:0]  wait_b4_rrst;
+   wire   [llols_cnt_width-1:0]  wait_after_lols;
+   reg                           pll_lol_p1;
+   reg                           pll_lol_p2;
+   reg                           pll_lol_p3;
+   // ------------ Tx
+   // rdo_tx_serdes_rst_c
+   reg    [lplol_cnt_width-1:0]  plol_cnt;
+   wire                          plol_cnt_tc;
+
+   reg    [2:0]                  txs_cnt;
+   reg                           txs_rst;
+   wire                          txs_cnt_tc;
+   // rdo_tx_pcs_rst_c
+   wire                          plol_fedge;
+   wire                          plol_redge;
+   reg                           waita_plol0;
+   reg    [2:0]                  plol0_cnt;
+   wire                          plol0_cnt_tc;
+   reg    [2:0]                  txp_cnt;
+   reg                           txp_rst;
+   wire                          txp_cnt_tc;
+   // ruo_tx_rdy
+   wire                          dual_or_serd_rst;
+   wire                          tx_any_pcs_rst;
+   wire                          tx_any_rst;
+   reg                           txsr_appd /* synthesis syn_keep=1 */;
+   reg                           txdpr_appd;
+   reg    [pnum_channels-1:0]    txpr_appd;
+   reg                           txr_wt_en;
+   reg    [ltxr_wait_width-1:0]  txr_wt_cnt;
+   wire                          txr_wt_tc;
+   reg                           ruo_tx_rdyr;
+
+   // ------------ Rx
+   wire                          comb_rlos;
+   wire                          comb_rlol;
+   //wire                          rlols;
+   wire                          rx_all_well;
+
+   //reg                           rlols_p1;
+   //reg                           rlols_p2;
+   //reg                           rlols_p3;
+
+   reg                           rlol_p1;
+   reg                           rlol_p2;
+   reg                           rlol_p3;
+   reg                           rlos_p1;
+   reg                           rlos_p2;
+   reg                           rlos_p3;
+
+   //reg    [3:0]                  rdb_cnt;
+   //wire                          rdb_cnt_max;
+   //wire                          rdb_cnt_zero;
+   //reg                           rlols_db;
+   //reg                           rlols_db_p1;
+
+   reg    [3:0]                  rlol_db_cnt;
+   wire                          rlol_db_cnt_max;
+   wire                          rlol_db_cnt_zero;
+   reg                           rlol_db;
+   reg                                  rlol_db_p1;
+
+   reg    [3:0]                  rlos_db_cnt;
+   wire                          rlos_db_cnt_max;
+   wire                          rlos_db_cnt_zero;
+   reg                           rlos_db;
+   reg                                  rlos_db_p1;
+
+   // rdo_rx_serdes_rst_c
+   reg    [lrlol_cnt_width-1:0]  rlol1_cnt;
+   wire                          rlol1_cnt_tc;
+   reg    [2:0]                  rxs_cnt;
+   reg                           rxs_rst;
+   wire                          rxs_cnt_tc;
+   reg    [lrrst_wait_width-1:0] rrst_cnt;
+   wire                          rrst_cnt_tc;
+   reg                           rrst_wait;
+   // rdo_rx_pcs_rst_c
+   //wire                          rlols_fedge;
+   //wire                          rlols_redge;
+   wire                          rlol_fedge;
+   wire                          rlol_redge;
+   wire                          rlos_fedge;
+   wire                          rlos_redge;
+
+   reg                           wait_calib;
+   reg                           waita_rlols0;
+   reg    [llols_cnt_width-1:0]  rlols0_cnt;
+   wire                          rlols0_cnt_tc;
+   reg    [2:0]                  rxp_cnt;
+   reg                           rxp_rst;
+   wire                          rxp_cnt_tc;
+
+   wire                          rx_any_serd_rst;
+   reg    [llols_cnt_width-1:0]  rlolsz_cnt;
+   wire                          rlolsz_cnt_tc;
+   reg [2:0]                    rxp_cnt2;
+   reg                           rxp_rst2;
+   wire                          rxp_cnt2_tc;
+   reg [15:0]                    data_loop_b_cnt;
+   reg                           data_loop_b;
+   wire                          data_loop_b_tc;
+
+   // ruo_rx_rdy
+   reg    [pnum_channels-1:0]    rxsr_appd;
+   reg    [pnum_channels-1:0]    rxpr_appd;
+   reg                           rxsdr_appd /* synthesis syn_keep=1 */;
+   reg                           rxdpr_appd;
+   wire                          rxsdr_or_sr_appd;
+   wire                          dual_or_rserd_rst;
+   wire                          rx_any_pcs_rst;
+   wire                          rx_any_rst;
+   reg                           rxr_wt_en;
+   reg    [lrxr_wait_width-1:0]  rxr_wt_cnt;
+   wire                          rxr_wt_tc;
+   reg                           ruo_rx_rdyr;
+
+// ==================================================================
+//                          Start of code
+// ==================================================================
+   assign rsl_enable = ~rui_rsl_disable;
+
+// ------------ rdo_serdes_rst_dual_c
+   assign rdo_serdes_rst_dual_c = (rui_rst&rsl_enable) | rui_serdes_rst_dual_c;
+
+// ------------ rdo_rst_dual_c
+   assign rdo_rst_dual_c = rui_rst_dual_c;
+
+// ------------ Setting counter values for RSL_SIM_MODE
+   `ifdef RSL_SIM_MODE
+      assign wait_b4_trst    = lwait_b4_trst_s;
+      assign wait_b4_rrst    = lwait_b4_rrst_s;
+      assign wait_after_lols = lwait_after_lols_s;
+   `else
+      assign wait_b4_trst    = lwait_b4_trst;
+      assign wait_b4_rrst    = lwait_b4_rrst;
+      assign wait_after_lols = lwait_after_lols;
+   `endif
+
+// ==================================================================
+//                                 Tx
+// ==================================================================
+   generate
+   if((pserdes_mode=="RX AND TX")||(pserdes_mode=="TX ONLY")) begin
+
+// ------------ Synchronizing pll_lol to the tx clock
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) begin
+         pll_lol_p1 <= 1'd0;
+         pll_lol_p2 <= 1'd0;
+         pll_lol_p3 <= 1'd0;
+      end
+      else begin
+         pll_lol_p1 <= rdi_pll_lol;
+         pll_lol_p2 <= pll_lol_p1;
+         pll_lol_p3 <= pll_lol_p2;
+      end
+   end
+
+// ------------ rdo_tx_serdes_rst_c
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         plol_cnt    <= 'd0;
+      else if((pll_lol_p2==0)||(plol_cnt_tc==1)||(rdo_tx_serdes_rst_c==1))
+         plol_cnt    <= 'd0;
+      else
+         plol_cnt    <= plol_cnt+1;
+   end
+   assign plol_cnt_tc = (plol_cnt==wait_b4_trst)?1'b1:1'b0;
+
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) begin
+         txs_cnt  <= 'd0;   // tx serdes reset pulse count
+         txs_rst  <= 1'b0;  // tx serdes reset
+      end
+      else if(plol_cnt_tc==1)
+         txs_rst  <= 1'b1;
+      else if(txs_cnt_tc==1) begin
+         txs_cnt  <= 'd0;
+         txs_rst  <= 1'b0;
+      end
+      else if(txs_rst==1)
+         txs_cnt  <= txs_cnt+1;
+   end
+   assign txs_cnt_tc = (txs_cnt==lreset_pwidth)?1'b1:1'b0;
+
+   assign rdo_tx_serdes_rst_c = (rsl_enable&txs_rst)| rui_tx_serdes_rst_c;
+
+// ------------ rdo_tx_pcs_rst_c
+   assign plol_fedge = ~pll_lol_p2 & pll_lol_p3;
+   assign plol_redge = pll_lol_p2 & ~pll_lol_p3;
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         waita_plol0  <= 1'd0;
+      else if(plol_fedge==1'b1)
+         waita_plol0  <= 1'b1;
+      else if((plol0_cnt_tc==1)||(plol_redge==1))
+         waita_plol0  <= 1'd0;
+   end
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         plol0_cnt    <= 'd0;
+      else if((pll_lol_p2==1)||(plol0_cnt_tc==1))
+         plol0_cnt    <= 'd0;
+      else if(waita_plol0==1'b1)
+         plol0_cnt    <= plol0_cnt+1;
+   end
+   assign plol0_cnt_tc = (plol0_cnt==lwait_after_plol0)?1'b1:1'b0;
+
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) begin
+         txp_cnt  <= 'd0;   // tx serdes reset pulse count
+         txp_rst  <= 1'b0;  // tx serdes reset
+      end
+      else if(plol0_cnt_tc==1)
+         txp_rst  <= 1'b1;
+      else if(txp_cnt_tc==1) begin
+         txp_cnt  <= 'd0;
+         txp_rst  <= 1'b0;
+      end
+      else if(txp_rst==1)
+         txp_cnt  <= txp_cnt+1;
+   end
+   assign txp_cnt_tc = (txp_cnt==lreset_pwidth)?1'b1:1'b0;
+
+   genvar i;
+   for(i=0;i<pnum_channels;i=i+1) begin : ifor
+      assign rdo_tx_pcs_rst_c[i] = (rsl_enable&txp_rst)| rui_tx_pcs_rst_c[i];
+   end
+   if(pnum_channels==1)
+      assign rdo_tx_pcs_rst_c[3:1] = 3'b000;
+   else if(pnum_channels==2)
+      assign rdo_tx_pcs_rst_c[3:2] = 2'b00;
+
+   // ------------ ruo_tx_rdy
+   if(pport_tx_rdy=="ENABLED") begin
+   assign dual_or_serd_rst = rdo_serdes_rst_dual_c|rdo_tx_serdes_rst_c;
+   assign tx_any_pcs_rst = rdo_rst_dual_c|(|rdo_tx_pcs_rst_c[pnum_channels-1:0]);
+   assign tx_any_rst = dual_or_serd_rst | tx_any_pcs_rst;
+
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         txsr_appd <= 1'b1; // tx serdes reset applied
+      else if(dual_or_serd_rst==1)
+         txsr_appd <= 1'b1;
+   end
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         txdpr_appd <= 1'b0; // tx dual (pcs) reset applied
+      else if(pll_lol_p2|rdo_serdes_rst_dual_c|rdo_tx_serdes_rst_c)
+         txdpr_appd <= 1'b0;
+      else if(rdo_rst_dual_c==1)
+         txdpr_appd <= 1'b1;
+   end
+
+   genvar m;
+   for(m=0;m<pnum_channels;m=m+1) begin :mfor
+      always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         txpr_appd[m] <= 1'b0; // tx pcs reset applied
+      else if(pll_lol_p2|rdo_serdes_rst_dual_c|rdo_tx_serdes_rst_c)
+         txpr_appd[m] <= 1'b0;
+      else if(txsr_appd&(rdo_tx_pcs_rst_c[m]|txdpr_appd))
+         txpr_appd[m] <= 1'b1;
+      end
+   end
+
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         txr_wt_en  <= 0;  // tx ready wait counter enable
+      else if((txr_wt_tc==1)||(dual_or_serd_rst==1))
+         txr_wt_en  <= 0;
+      else if((~ruo_tx_rdyr)&(~pll_lol_p2)&(&txpr_appd))
+         txr_wt_en  <= 1;
+   end
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         txr_wt_cnt  <= 'd0;  // tx ready wait count
+      else if((txr_wt_tc==1)||(tx_any_rst==1))
+         txr_wt_cnt  <= 'd0;
+      else if(txr_wt_en==1)
+         txr_wt_cnt  <= txr_wt_cnt+1;
+   end
+   assign txr_wt_tc = (txr_wt_cnt==pwait_tx_rdy)?1'b1:1'b0;
+
+   always @(posedge rui_tx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         ruo_tx_rdyr <= 1'b0; // tx serdes reset applied
+      else if((tx_any_rst==1)||(pll_lol_p2==1))
+         ruo_tx_rdyr <= 1'b0;
+      else if(txr_wt_tc==1)
+         ruo_tx_rdyr <= 1'b1;
+   end
+   assign ruo_tx_rdy = ruo_tx_rdyr;
+   end         // if pport_tx_rdy
+   else
+      assign ruo_tx_rdy = 1'b0;
+   end         // generate if(Rx and Tx) or (Tx only)
+   else begin  // generate else (Rx only)
+      assign rdo_tx_serdes_rst_c = 1'b0;
+      assign rdo_tx_pcs_rst_c = 4'd0;
+      assign ruo_tx_rdy = 1'b0;
+   end
+   endgenerate
+
+// ==================================================================
+//                                 Rx
+// ==================================================================
+   generate
+   if((pserdes_mode=="RX AND TX")||(pserdes_mode=="RX ONLY")) begin
+   assign comb_rlos = |rdi_rx_los_low_s[pnum_channels-1:0];
+   assign comb_rlol = |rdi_rx_cdr_lol_s[pnum_channels-1:0];
+   //assign rlols     = comb_rlos|comb_rlol;
+
+   // ------------ Synchronizing rlols to the rx ref clock
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) begin
+        //rlols_p1    <= 1'd0;
+        //rlols_p2    <= 1'd0;
+        //rlols_p3    <= 1'd0;
+        //rlols_db_p1 <= 1'd1;
+
+        rlol_p1     <= 1'd0;
+        rlol_p2     <= 1'd0;
+        rlol_p3     <= 1'd0;
+        rlol_db_p1  <= 1'd1;
+
+        rlos_p1    <= 1'd0;
+        rlos_p2    <= 1'd0;
+        rlos_p3    <= 1'd0;
+        rlos_db_p1 <= 1'd1;
+      end
+      else begin
+        //rlols_p1    <= rlols;
+        //rlols_p2    <= rlols_p1;
+        //rlols_p3    <= rlols_p2;
+        //rlols_db_p1 <= rlols_db;
+
+        rlol_p1     <= comb_rlol;
+        rlol_p2     <= rlol_p1;
+        rlol_p3     <= rlol_p2;
+       rlol_db_p1  <= rlol_db;
+
+        rlos_p1    <= comb_rlos;
+        rlos_p2    <= rlos_p1;
+        rlos_p3    <= rlos_p2;
+        rlos_db_p1 <= rlos_db;
+      end
+   end
+   assign rx_all_well = ~rlol_db && ~rlos_db;
+
+//******************************************************************************
+// [ES:05.03.17] Unused registers for clean-up
+//------------------------------------------------------------------------------
+// ------------ Debouncing rlols
+//   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+//      if(rui_rst==1'b1) rdb_cnt  <= lrdb_max;
+//      else if(rlols_p2==1) begin
+//         if(!rdb_cnt_max) rdb_cnt <= rdb_cnt+1;
+//      end
+//      else if(!rdb_cnt_zero) rdb_cnt <= rdb_cnt-1;
+//   end
+//   assign rdb_cnt_max  = (rdb_cnt==lrdb_max);
+//   assign rdb_cnt_zero = (rdb_cnt==0);
+//   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+//      if(rui_rst==1'b1) rlols_db <= 1;
+//      else if(rdb_cnt_max)  rlols_db <= 1;
+//      else if(rdb_cnt_zero) rlols_db <= 0;
+//   end
+//******************************************************************************
+
+// ------------ Debouncing rlol
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) rlol_db_cnt  <= lrdb_max;
+      else if(rlol_p2==1) begin
+         if(!rlol_db_cnt_max) rlol_db_cnt <= rlol_db_cnt+1;
+      end
+      else if(!rlol_db_cnt_zero) rlol_db_cnt <= rlol_db_cnt-1;
+   end
+   assign rlol_db_cnt_max  = (rlol_db_cnt==lrdb_max);
+   assign rlol_db_cnt_zero = (rlol_db_cnt==0);
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) rlol_db <= 1;
+      else if(rlol_db_cnt_max)  rlol_db <= 1;
+      else if(rlol_db_cnt_zero) rlol_db <= 0;
+   end
+
+// ------------ Debouncing rlos
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) rlos_db_cnt  <= lrdb_max;
+      else if(rlos_p2==1) begin
+         if(!rlos_db_cnt_max) rlos_db_cnt <= rlos_db_cnt+1;
+      end
+      else if(!rlos_db_cnt_zero) rlos_db_cnt <= rlos_db_cnt-1;
+   end
+   assign rlos_db_cnt_max  = (rlos_db_cnt==lrdb_max);
+   assign rlos_db_cnt_zero = (rlos_db_cnt==0);
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1) rlos_db <= 1;
+      else if(rlos_db_cnt_max)  rlos_db <= 1;
+      else if(rlos_db_cnt_zero) rlos_db <= 0;
+   end
+
+// ------------ Calib time trigger
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+     if (rui_rst==1'b1) begin
+       wait_calib <= 1'd1;
+     end
+     else begin
+       if (rlol1_cnt_tc) begin
+         if (rlol_db)
+           wait_calib <= 1'd1;
+         else
+           wait_calib <= 1'd0;
+       end
+       else if (rlos_redge)
+         wait_calib <= 1'd0;
+       else if (rlos_fedge) begin
+         wait_calib <= 1'd1;
+       end
+     end
+   end
+
+   //***************************************************************************
+   // Total calibration time counter
+   // - this covers the band calibration time (256 cycles * 64) and
+   //   DAC calibration time (16384 cycles * 10 bits)
+   //---------------------------------------------------------------------------
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+     if (rui_rst==1'b1) begin
+       rlol1_cnt  <= 'd0;  // Counting when Rx LOL is 1 and Rx LOS is 0
+     end
+     else begin
+       if(rxs_rst || rlol1_cnt_tc || rlos_redge)
+         rlol1_cnt  <= 'd0;
+       else if (wait_calib)
+         rlol1_cnt <= rlol1_cnt+1;
+     end
+   end
+   assign rlol1_cnt_tc = (rlol1_cnt==wait_b4_rrst);
+
+// ------------ rdo_rx_serdes_rst_c
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+     if (rui_rst==1'b1) begin
+       rxs_cnt  <= 'd0;   // rx serdes reset pulse count
+       rxs_rst  <= 1'b0;  // rx serdes reset
+     end
+     else begin
+       if (rlos_db)
+         rxs_rst <= 1'b0;
+       else if (rlol1_cnt_tc && rlol_db)
+         rxs_rst <= 1'b1;
+       else if (rxs_cnt_tc==1) begin
+         rxs_rst  <= 1'b0;
+       end
+
+       if (rxs_cnt_tc)
+         rxs_cnt <= 'd0;
+       else
+         if (rxs_rst==1)
+           rxs_cnt <= rxs_cnt+1;
+     end
+   end
+   assign rxs_cnt_tc  = (rxs_cnt==lreset_pwidth)?1'b1:1'b0;
+
+   //***************************************************************************
+   // [ES:05.03.17] Unused logic from CPRI rrst_wait
+   //---------------------------------------------------------------------------
+   // always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+   //    if(rui_rst==1'b1)
+   //       rrst_cnt    <= 'd0;
+   //    else if(rlol1_cnt_tc)
+   //       rrst_cnt    <= 'd0;
+   //    else if(rrst_wait)
+   //       rrst_cnt    <= rrst_cnt+1;
+   // end
+   // assign rrst_cnt_tc = (rrst_cnt==lwait_after_rrst) ? 1'b1 : 1'b0;
+   // always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+   //    if(rui_rst==1'b1)
+   //       rrst_wait    <= 0;
+   //    else if(pprotocol != "CPRI")
+   //       rrst_wait    <= 0;
+   //    else if(rlol1_cnt_tc)
+   //       rrst_wait    <= 1;
+   //    else if(rrst_cnt_tc==1)
+   //       rrst_wait    <= 0;
+   // end
+   //***************************************************************************
+
+   genvar j;
+   for(j=0;j<pnum_channels;j=j+1) begin :jfor
+      assign rdo_rx_serdes_rst_c[j] = (rsl_enable&rxs_rst)| rui_rx_serdes_rst_c[j];
+   end
+   if(pnum_channels==1)
+      assign rdo_rx_serdes_rst_c[3:1] = 3'b000;
+   else if(pnum_channels==2)
+      assign rdo_rx_serdes_rst_c[3:2] = 2'b00;
+
+// ------------ rdo_rx_pcs_rst_c
+   //assign rlols_fedge = ~rlols_db & rlols_db_p1;
+   //assign rlols_redge = rlols_db & ~rlols_db_p1;
+
+   assign rlol_fedge  = ~rlol_db & rlol_db_p1;
+   assign rlol_redge  = rlol_db & ~rlol_db_p1;
+   assign rlos_fedge  = ~rlos_db & rlos_db_p1;
+   assign rlos_redge  = rlos_db & ~rlos_db_p1;
+
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if (rui_rst==1'b1) begin
+        waita_rlols0 <= 1'd0;
+      end
+      else begin
+        if ((rlos_fedge && ~rlol_db) || (rlol_fedge && ~rlos_db))
+          waita_rlols0 <= 1'b1;
+        else if (rlos_redge || rlol_redge)
+          waita_rlols0 <= 1'd0;
+        else if (rlols0_cnt_tc==1)
+          waita_rlols0 <= 1'd0;
+      end
+   end
+
+   //***************************************************************************
+   // Post RLOL check before pcs_rst deassertion
+   // - allowance of 2-4 DAC calibration cycles + 1024 cycles for WA module
+   //   (word alignment).
+   //---------------------------------------------------------------------------
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+     if (rui_rst==1'b1) begin
+       rlols0_cnt <= 'd0;
+     end
+     else begin
+       if (rlol_redge || rlos_redge || rlols0_cnt_tc)
+         rlols0_cnt <= 'd0;
+       else if (waita_rlols0==1)
+         rlols0_cnt <= rlols0_cnt+1;
+     end
+   end
+   assign rlols0_cnt_tc   = (rlols0_cnt == wait_after_lols);
+   assign rx_any_serd_rst = rdo_serdes_rst_dual_c|(|rdo_rx_serdes_rst_c);
+
+   //***************************************************************************
+   // [ES:05.03.17] Unused registers for clean-up
+   //---------------------------------------------------------------------------
+   // always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+   //    if(rui_rst==1'b1)
+   //       rlolsz_cnt  <= 'd0;  // Counting when both Rx LOL is 0 and Rx LOS is 0
+   //    else if((rlol_db|rx_any_serd_rst)||(rlolsz_cnt_tc==1))
+   //       rlolsz_cnt  <= 'd0;
+   //    else if((rlolsz_cnt_tc==0)&&(rlol_db==0))
+   //       rlolsz_cnt  <= rlolsz_cnt+1;
+   // end
+   // assign rlolsz_cnt_tc = (rlolsz_cnt==wait_after_lols);
+   //***************************************************************************
+
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+     if (rui_rst==1'b1) begin
+       rxp_cnt2  <= 'd0;   // pcs serdes reset pulse count
+       rxp_rst2  <= 1'b1;  // rx pcs reset
+     end
+     else begin
+       if (rx_any_serd_rst || rlos_redge) begin
+         rxp_rst2 <= 1'b1;
+       end
+       else if (rlols0_cnt_tc) begin
+         rxp_rst2 <= 1'b0;
+       end
+       //***********************************************************************
+       // [ES:05.03.17] No need for pulse width
+       //-----------------------------------------------------------------------
+       // else if(rxp_cnt2_tc==1) begin
+       //   rxp_cnt2  <= 'd0;
+       //   rxp_rst2  <= 1'b0;
+       // end
+       //***********************************************************************
+       // [ES:05.03.17] No need for pulse width
+       //-----------------------------------------------------------------------
+       // else if (rxp_rst2==1)
+       //   rxp_cnt2 <= rxp_cnt2+1;
+       //***********************************************************************
+     end // else: !if(rui_rst==1'b1)
+   end // always @ (posedge rui_rx_ref_clk or posedge rui_rst)
+   //assign rxp_cnt2_tc = (rxp_cnt2==lreset_pwidth)?1'b1:1'b0;
+
+   //***************************************************************************
+   // [ES:05.03.17] No need for pulse width
+   //---------------------------------------------------------------------------
+   //else begin
+   //   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+   //      if(rui_rst==1'b1)
+   //         rxp_rst2  <= 1'b1;  // rx pcs reset
+   //      else if(rx_any_serd_rst)
+   //         rxp_rst2  <= 1'b1;
+   //      else if(rlolsz_cnt_tc==1)
+   //         rxp_rst2  <= 1'b0;
+   //   end
+   //end
+   //***************************************************************************
+
+   genvar k;
+   for(k=0;k<pnum_channels;k=k+1) begin: kfor
+      assign rdo_rx_pcs_rst_c[k] = (rsl_enable&rxp_rst2)| rui_rx_pcs_rst_c[k];
+   end
+   if(pnum_channels==1)
+      assign rdo_rx_pcs_rst_c[3:1] = 3'b000;
+   else if(pnum_channels==2)
+      assign rdo_rx_pcs_rst_c[3:2] = 2'b00;
+
+// ------------ ruo_rx_rdy
+   if(pport_rx_rdy=="ENABLED") begin
+   assign dual_or_rserd_rst = rdo_serdes_rst_dual_c|(|rdo_rx_serdes_rst_c[pnum_channels-1:0]);
+   assign rx_any_pcs_rst = rdo_rst_dual_c|(|rdo_rx_pcs_rst_c[pnum_channels-1:0]);
+   assign rx_any_rst = dual_or_rserd_rst | rx_any_pcs_rst;
+
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         rxsdr_appd <= 1'b1;  // Serdes dual reset (macro reset) applied
+      else if(rdo_serdes_rst_dual_c==1)
+         rxsdr_appd <= 1'b1;
+   end
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         rxdpr_appd <= 1'b0;  // Rx dual PCS reset (dual reset) applied
+      else if(~rx_all_well|dual_or_rserd_rst)
+         rxdpr_appd <= 1'b0;
+      else if(rdo_rst_dual_c==1)
+         rxdpr_appd <= 1'b1;
+   end
+
+   genvar l;
+   for(l=0;l<pnum_channels;l=l+1) begin : lfor
+      always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+         if(rui_rst==1'b1)
+            rxsr_appd[l] <= 1'b0; // rx serdes reset applied
+         else if(rdo_rx_serdes_rst_c[l]==1)
+            rxsr_appd[l] <= 1'b1;
+      end
+      always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         rxpr_appd[l] <= 1'b0; // rx pcs reset applied
+      else if(rdi_rx_los_low_s[l]|rdi_rx_cdr_lol_s[l]|rdo_serdes_rst_dual_c|rdo_rx_serdes_rst_c[l])
+         rxpr_appd[l] <= 1'b0;
+      else if(rxsdr_or_sr_appd&(~rx_all_well)&rdo_rx_pcs_rst_c[l])
+         rxpr_appd[l] <= 1'b1;
+      end
+   end
+
+   assign rxsdr_or_sr_appd = rxsdr_appd|(&rxsr_appd);
+
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         rxr_wt_en  <= 0;  // rx ready wait counter enable
+      //else if((rxr_wt_tc==1)||(dual_or_rserd_rst==1))
+      else if((rxr_wt_tc==1)||(dual_or_rserd_rst==1)||(rx_all_well==0)) // BM, 2/4/16
+         rxr_wt_en  <= 0;
+      else if(~ruo_rx_rdyr&rx_all_well&((&rxpr_appd)|rxdpr_appd))
+         rxr_wt_en  <= 1;
+   end
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         rxr_wt_cnt  <= 'd0;  // rx ready wait count
+      //else if((rxr_wt_tc==1)||(rx_any_rst==1))
+      else if((rxr_wt_tc==1)||(rx_any_rst==1)||(rx_all_well==0)) // BM, 2/4/16
+         rxr_wt_cnt  <= 'd0;
+      else if(rxr_wt_en==1)
+         rxr_wt_cnt  <= rxr_wt_cnt+1;
+   end
+   assign rxr_wt_tc = (rxr_wt_cnt==pwait_rx_rdy)?1'b1:1'b0;
+
+   always @(posedge rui_rx_ref_clk or posedge rui_rst) begin
+      if(rui_rst==1'b1)
+         ruo_rx_rdyr <= 1'b0; // rx serdes reset applied
+      else if((rx_any_rst==1)||(rx_all_well==0))
+         ruo_rx_rdyr <= 1'b0;
+      else if(rxr_wt_tc==1)
+         ruo_rx_rdyr <= 1'b1;
+   end
+   assign ruo_rx_rdy = ruo_rx_rdyr;
+   end         // if pport_rx_rdy
+   else
+      assign ruo_rx_rdy = 1'b0;
+   end // if ((pserdes_mode=="RX AND TX")||(pserdes_mode=="RX ONLY"))
+
+   else begin  // generate else (Tx only)
+      assign rdo_rx_serdes_rst_c = 4'd0;
+      assign rdo_rx_pcs_rst_c = 4'd0;
+      assign ruo_rx_rdy = 1'b0;
+   end // else: !if((pserdes_mode=="RX AND TX")||(pserdes_mode=="RX ONLY"))
+
+   endgenerate
+
+endmodule
+
+
+//   ===========================================================================
+//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
+//   ---------------------------------------------------------------------------
+//   Copyright (c) 2015 by Lattice Semiconductor Corporation
+//   ALL RIGHTS RESERVED 
+//   ------------------------------------------------------------------
+//
+//   Permission:
+//
+//      Lattice SG Pte. Ltd. grants permission to use this code
+//      pursuant to the terms of the Lattice Reference Design License Agreement. 
+//
+//
+//   Disclaimer:
+//
+//      This VHDL or Verilog source code is intended as a design reference
+//      which illustrates how these types of functions can be implemented.
+//      It is the user's responsibility to verify their design for
+//      consistency and functionality through the use of formal
+//      verification methods.  Lattice provides no warranty
+//      regarding the use or functionality of this code.
+//
+//   ---------------------------------------------------------------------------
+//
+//                  Lattice SG Pte. Ltd.
+//                  101 Thomson Road, United Square #07-02 
+//                  Singapore 307591
+//
+//
+//                  TEL: 1-800-Lattice (USA and Canada)
+//                       +65-6631-2000 (Singapore)
+//                       +1-503-268-8001 (other locations)
+//
+//                  web: http://www.latticesemi.com/
+//                  email: techsupport@latticesemi.com
+//
+//   ---------------------------------------------------------------------------
+//
+// =============================================================================
+//                         FILE DETAILS         
+// Project               : SLL - Soft Loss Of Lock(LOL) Logic
+// File                  : sll_core.v
+// Title                 : Top-level file for SLL 
+// Dependencies          : 1.
+//                       : 2.
+// Description           : 
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.0
+// Author(s)             : AV
+// Mod. Date             : March 2, 2015
+// Changes Made          : Initial Creation
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.1
+// Author(s)             : AV
+// Mod. Date             : June 8, 2015
+// Changes Made          : Following updates were made 
+//                       : 1. Changed all the PLOL status logic and FSM to run
+//                       :    on sli_refclk. 
+//                       : 2. Added the HB logic for presence of tx_pclk 
+//                       : 3. Changed the lparam assignment scheme for 
+//                       :    simulation purposes. 
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.2
+// Author(s)             : AV
+// Mod. Date             : June 24, 2015
+// Changes Made          : Updated the gearing logic for SDI dynamic rate change
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.3
+// Author(s)             : AV
+// Mod. Date             : July 14, 2015
+// Changes Made          : Added the logic for dynamic rate change in CPRI
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.4
+// Author(s)             : AV
+// Mod. Date             : August 21, 2015
+// Changes Made          : Added the logic for dynamic rate change of 5G CPRI & 
+//                         PCIe.
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.5
+// Author(s)             : ES/EB
+// Mod. Date             : March 21, 2017
+// Changes Made          : 1. Added pdiff_sync signal to syncrhonize pcount_diff 
+//                       :    to sli_refclk.
+//                       : 2. Updated terminal count logic for PCIe 5G
+//                       : 3. Modified checking of pcount_diff in SLL state
+//                       :    machine to cover actual count
+//                       :    (from 16-bits to 22-bits)
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.6
+// Author(s)             : ES
+// Mod. Date             : April 19, 2017
+// Changes Made          : 1. Added registered lock and unlock signal from
+//                            pdiff_sync to totally decouple pcount_diff from
+//                            SLL state machine.
+//                       : 2. Modified LPCLK_TC_4 to 1:1 clock ratio when CPRI
+//                            is operating @ 4.9125Gbps data rate.
+// =============================================================================
+`timescale 1ns/10ps
+
+module serdes_sync_1sll_core ( 
+  //Reset and Clock inputs
+  sli_rst,         //Active high asynchronous reset input
+  sli_refclk,      //Refclk input to the Tx PLL
+  sli_pclk,        //Tx pclk output from the PCS
+  
+  //Control inputs
+  sli_div2_rate,   //Divide by 2 control; 0 - Full rate; 1 - Half rate
+  sli_div11_rate,  //Divide by 11 control; 0 - Full rate; 1 - Div by 11
+  sli_gear_mode,   //Gear mode control for PCS; 0 - 8/10; 1- 16/20
+  sli_cpri_mode,   //Mode of operation specific to CPRI protocol
+  sli_pcie_mode,   //Mode of operation specific to PCIe mode (2.5G or 5G)
+  
+  //LOL Output
+  slo_plol         //Tx PLL Loss of Lock output to the user logic
+  );
+  
+// Inputs
+input       sli_rst;
+input       sli_refclk;
+input       sli_pclk;
+input       sli_div2_rate;
+input       sli_div11_rate;
+input       sli_gear_mode;
+input [2:0] sli_cpri_mode;
+input       sli_pcie_mode;
+
+// Outputs
+output      slo_plol;
+
+
+// Parameters
+parameter PPROTOCOL              = "PCIE";     //Protocol selected by the User
+parameter PLOL_SETTING           = 0;          //PLL LOL setting. Possible values are 0,1,2,3
+parameter PDYN_RATE_CTRL         = "DISABLED"; //PCS Dynamic Rate control
+parameter PPCIE_MAX_RATE         = "2.5";      //PCIe max data rate
+parameter PDIFF_VAL_LOCK         = 20;         //Differential count value for Lock
+parameter PDIFF_VAL_UNLOCK       = 39;         //Differential count value for Unlock
+parameter PPCLK_TC               = 65535;      //Terminal count value for counter running on sli_pclk
+parameter PDIFF_DIV11_VAL_LOCK   = 3;          //Differential count value for Lock for SDI Div11
+parameter PDIFF_DIV11_VAL_UNLOCK = 3;          //Differential count value for Unlock for SDI Div11
+parameter PPCLK_DIV11_TC         = 2383;       //Terminal count value (SDI Div11) for counter running on sli_pclk
+
+
+// Local Parameters
+localparam [1:0]  LPLL_LOSS_ST         = 2'b00;       //PLL Loss state
+localparam [1:0]  LPLL_PRELOSS_ST      = 2'b01;       //PLL Pre-Loss state
+localparam [1:0]  LPLL_PRELOCK_ST      = 2'b10;       //PLL Pre-Lock state
+localparam [1:0]  LPLL_LOCK_ST         = 2'b11;       //PLL Lock state
+`ifdef RSL_SIM_MODE
+localparam [15:0] LRCLK_TC             = 16'd63;   //Terminal count value for counter running on sli_refclk
+`else
+localparam [15:0] LRCLK_TC             = 16'd65535;   //Terminal count value for counter running on sli_refclk
+`endif
+localparam [15:0] LRCLK_TC_PUL_WIDTH   = 16'd50;      //Pulse width for the Refclk terminal count pulse
+localparam [7:0]  LHB_WAIT_CNT         = 8'd255;      //Wait count for the Heartbeat signal
+
+// Local Parameters related to the CPRI dynamic modes
+// Terminal count values for the four CPRI modes
+localparam LPCLK_TC_0 = 32768;
+localparam LPCLK_TC_1 = 65536;
+localparam LPCLK_TC_2 = 131072;
+localparam LPCLK_TC_3 = 163840;
+localparam LPCLK_TC_4 = 65536;
+
+// Lock values count values for the four CPRI modes and four PLOL settings (4x5)
+// CPRI rate mode 0                CPRI rate mode 1                   CPRI rate mode 2                    CPRI rate mode 3                     CPRI rate mode 4
+localparam LPDIFF_LOCK_00 = 9;     localparam LPDIFF_LOCK_10 = 19;    localparam LPDIFF_LOCK_20 = 39;     localparam LPDIFF_LOCK_30 = 49;      localparam LPDIFF_LOCK_40 = 19;
+localparam LPDIFF_LOCK_01 = 9;     localparam LPDIFF_LOCK_11 = 19;    localparam LPDIFF_LOCK_21 = 39;     localparam LPDIFF_LOCK_31 = 49;      localparam LPDIFF_LOCK_41 = 19;
+localparam LPDIFF_LOCK_02 = 49;    localparam LPDIFF_LOCK_12 = 98;    localparam LPDIFF_LOCK_22 = 196;    localparam LPDIFF_LOCK_32 = 245;     localparam LPDIFF_LOCK_42 = 98;
+localparam LPDIFF_LOCK_03 = 131;   localparam LPDIFF_LOCK_13 = 262;   localparam LPDIFF_LOCK_23 = 524;    localparam LPDIFF_LOCK_33 = 655;     localparam LPDIFF_LOCK_43 = 262;
+
+// Unlock values count values for the four CPRI modes and four PLOL settings (4x5)
+// CPRI rate mode 0                  CPRI rate mode 1                      CPRI rate mode 2                       CPRI rate mode 3                         CPRI rate mode 4
+localparam LPDIFF_UNLOCK_00 = 19;    localparam LPDIFF_UNLOCK_10 = 39;     localparam LPDIFF_UNLOCK_20 = 78;      localparam LPDIFF_UNLOCK_30 = 98;        localparam LPDIFF_UNLOCK_40 = 39;
+localparam LPDIFF_UNLOCK_01 = 65;    localparam LPDIFF_UNLOCK_11 = 131;    localparam LPDIFF_UNLOCK_21 = 262;     localparam LPDIFF_UNLOCK_31 = 327;       localparam LPDIFF_UNLOCK_41 = 131;
+localparam LPDIFF_UNLOCK_02 = 72;    localparam LPDIFF_UNLOCK_12 = 144;    localparam LPDIFF_UNLOCK_22 = 288;     localparam LPDIFF_UNLOCK_32 = 360;       localparam LPDIFF_UNLOCK_42 = 144;
+localparam LPDIFF_UNLOCK_03 = 196;   localparam LPDIFF_UNLOCK_13 = 393;    localparam LPDIFF_UNLOCK_23 = 786;     localparam LPDIFF_UNLOCK_33 = 983;       localparam LPDIFF_UNLOCK_43 = 393;
+
+// Input and Output reg and wire declarations
+wire       sli_rst;
+wire       sli_refclk;
+wire       sli_pclk;
+wire       sli_div2_rate;
+wire       sli_div11_rate;
+wire       sli_gear_mode;
+wire [2:0] sli_cpri_mode;
+wire       sli_pcie_mode;
+wire       slo_plol;
+
+//-------------- Internal signals reg and wire declarations --------------------
+
+//Signals running on sli_refclk
+reg  [15:0] rcount;           //16-bit Counter
+reg         rtc_pul;          //Terminal count pulse
+reg         rtc_pul_p1;       //Terminal count pulse pipeline
+reg         rtc_ctrl;         //Terminal count pulse control
+
+reg  [7:0]  rhb_wait_cnt;     //Heartbeat wait counter
+
+//Heatbeat synchronization and pipeline registers
+wire        rhb_sync;
+reg         rhb_sync_p2;
+reg         rhb_sync_p1;
+
+//Pipeling registers for dynamic control mode
+wire        rgear;
+wire        rdiv2;
+wire        rdiv11;
+reg         rgear_p1;
+reg         rdiv2_p1;
+reg         rdiv11_p1;
+
+reg         rstat_pclk;        //Pclk presence/absence status
+
+reg  [21:0] rcount_tc;         //Tx_pclk terminal count register
+reg  [15:0] rdiff_comp_lock;   //Differential comparison value for Lock
+reg  [15:0] rdiff_comp_unlock; //Differential compariosn value for Unlock
+
+wire        rpcie_mode;        //PCIe mode signal synchronized to refclk
+reg         rpcie_mode_p1;     //PCIe mode pipeline register
+
+wire        rcpri_mod_ch_sync; //CPRI mode change synchronized to refclk
+reg         rcpri_mod_ch_p1;   //CPRI mode change pipeline register
+reg         rcpri_mod_ch_p2;   //CPRI mode change pipeline register
+reg         rcpri_mod_ch_st;   //CPRI mode change status
+
+reg  [1:0]  sll_state;         //Current-state register for LOL FSM
+
+reg         pll_lock;          //PLL Lock signal
+
+//Signals running on sli_pclk
+//Synchronization and pipeline registers
+wire        ppul_sync;
+reg         ppul_sync_p1;
+reg         ppul_sync_p2;
+reg         ppul_sync_p3;
+
+wire        pdiff_sync;
+reg         pdiff_sync_p1;
+   
+reg  [21:0] pcount;            //22-bit counter
+reg  [21:0] pcount_diff;       //Differential value between Tx_pclk counter and theoritical value
+
+//Heartbeat counter and heartbeat signal running on pclk
+reg  [2:0]  phb_cnt;
+reg         phb;
+
+//CPRI dynamic mode releated signals
+reg  [2:0]  pcpri_mode;
+reg         pcpri_mod_ch;
+
+//Assignment scheme changed mainly for simulation purpose
+wire [15:0] LRCLK_TC_w;
+assign LRCLK_TC_w = LRCLK_TC;
+
+reg         unlock;
+reg         lock;
+
+//Heartbeat synchronization
+sync # (.PDATA_RST_VAL(0)) phb_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (phb),
+  .data_out(rhb_sync)
+  );
+  
+  
+//Terminal count pulse synchronization
+sync # (.PDATA_RST_VAL(0)) rtc_sync_inst ( 
+  .clk     (sli_pclk),
+  .rst     (sli_rst),
+  .data_in (rtc_pul),
+  .data_out(ppul_sync)
+  );
+
+//Differential value logic update synchronization
+sync # (.PDATA_RST_VAL(0)) pdiff_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (ppul_sync),
+  .data_out(pdiff_sync)
+  );
+
+//Gear mode synchronization
+sync # (.PDATA_RST_VAL(0)) gear_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (sli_gear_mode),
+  .data_out(rgear)
+  );
+  
+//Div2 synchronization
+sync # (.PDATA_RST_VAL(0)) div2_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (sli_div2_rate),
+  .data_out(rdiv2)
+  );
+  
+//Div11 synchronization
+sync # (.PDATA_RST_VAL(0)) div11_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (sli_div11_rate),
+  .data_out(rdiv11)
+  );
+  
+//CPRI mode change synchronization
+sync # (.PDATA_RST_VAL(0)) cpri_mod_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (pcpri_mod_ch),
+  .data_out(rcpri_mod_ch_sync)
+  );
+  
+//PCIe mode change synchronization
+sync # (.PDATA_RST_VAL(0)) pcie_mod_sync_inst ( 
+  .clk     (sli_refclk),
+  .rst     (sli_rst),
+  .data_in (sli_pcie_mode),
+  .data_out(rpcie_mode)
+  );  
+
+// =============================================================================
+// Synchronized Lock/Unlock signals
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    unlock        <= 1'b0;
+    lock          <= 1'b0;
+    pdiff_sync_p1 <= 1'b0;
+  end
+  else begin
+    pdiff_sync_p1 <= pdiff_sync;
+    if (unlock) begin
+      unlock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : unlock;
+    end
+    else begin
+      unlock <= pdiff_sync ? (pcount_diff[21:0] > {6'd0, rdiff_comp_unlock}) : 1'b0;
+    end
+    if (lock) begin
+      lock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : lock;
+    end
+    else begin
+      lock <= pdiff_sync ? (pcount_diff[21:0] <= {6'd0, rdiff_comp_lock}) : 1'b0;
+    end
+  end
+end
+
+// =============================================================================
+// Refclk Counter, pulse generation logic and Heartbeat monitor logic
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rcount     <= 16'd0;
+    rtc_pul    <= 1'b0;
+    rtc_ctrl   <= 1'b0;
+    rtc_pul_p1 <= 1'b0;
+  end
+  else begin
+    //Counter logic
+    if ((rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin
+      if (rtc_ctrl == 1'b1) begin
+        rcount <= LRCLK_TC_PUL_WIDTH;
+      end  
+    end
+    else begin
+      if (rcount != LRCLK_TC_w) begin
+        rcount <= rcount + 1;
+      end
+      else begin
+        rcount <= 16'd0;   
+      end
+    end
+    
+    //Pulse control logic
+    if (rcount == LRCLK_TC_w - 1) begin
+      rtc_ctrl <= 1'b1;
+    end
+    
+    //Pulse Generation logic
+    if (rtc_ctrl == 1'b1) begin
+      if ((rcount == LRCLK_TC_w) || (rcount < LRCLK_TC_PUL_WIDTH)) begin
+        rtc_pul <= 1'b1;
+    end  
+      else begin
+        rtc_pul <= 1'b0;  
+      end
+    end
+    
+    rtc_pul_p1 <= rtc_pul;  
+  end  
+end
+
+
+// =============================================================================
+// Heartbeat synchronization & monitor logic and Dynamic mode pipeline logic 
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rhb_sync_p1     <= 1'b0;
+    rhb_sync_p2     <= 1'b0;
+    rhb_wait_cnt    <= 8'd0;
+    rstat_pclk      <= 1'b0;
+    rgear_p1        <= 1'b0;
+    rdiv2_p1        <= 1'b0;
+    rdiv11_p1       <= 1'b0;
+    rcpri_mod_ch_p1 <= 1'b0;
+    rcpri_mod_ch_p2 <= 1'b0;
+    rcpri_mod_ch_st <= 1'b0;
+    rpcie_mode_p1   <= 1'b0;
+    
+  end
+  else begin
+    //Pipeline stages for the Heartbeat
+    rhb_sync_p1 <= rhb_sync;
+    rhb_sync_p2 <= rhb_sync_p1;
+    
+    //Pipeline stages of the Dynamic rate control signals
+    rgear_p1  <= rgear;
+    rdiv2_p1  <= rdiv2;
+    rdiv11_p1 <= rdiv11;
+    
+    //Pipeline stage for PCIe mode
+    rpcie_mode_p1 <= rpcie_mode;
+    
+    //Pipeline stage for CPRI mode change
+    rcpri_mod_ch_p1 <= rcpri_mod_ch_sync;
+    rcpri_mod_ch_p2 <= rcpri_mod_ch_p1;
+    
+    //CPRI mode change status logic
+    if (rcpri_mod_ch_p1^rcpri_mod_ch_sync == 1'b1) begin
+      rcpri_mod_ch_st <= 1'b1;
+    end 
+    
+    //Heartbeat wait counter and monitor logic
+    if (rtc_ctrl == 1'b1) begin
+      if (rhb_sync_p1 == 1'b1 && rhb_sync_p2 == 1'b0) begin
+        rhb_wait_cnt <= 8'd0;
+        rstat_pclk   <= 1'b1;
+      end
+      else if (rhb_wait_cnt == LHB_WAIT_CNT) begin
+        rhb_wait_cnt <= 8'd0;
+        rstat_pclk   <= 1'b0;
+      end
+      else begin
+        rhb_wait_cnt <= rhb_wait_cnt + 1;
+      end
+    end
+  end  
+end
+
+
+// =============================================================================
+// Pipleline registers for the TC pulse and CPRI mode change logic
+// =============================================================================
+always @(posedge sli_pclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    ppul_sync_p1 <= 1'b0;
+    ppul_sync_p2 <= 1'b0;
+    ppul_sync_p3 <= 1'b0;
+    pcpri_mode   <= 3'b0;
+    pcpri_mod_ch <= 1'b0;
+  end
+  else begin
+    ppul_sync_p1 <= ppul_sync;
+    ppul_sync_p2 <= ppul_sync_p1;
+    ppul_sync_p3 <= ppul_sync_p2;
+    
+    //CPRI mode change logic
+    pcpri_mode <= sli_cpri_mode;
+    
+    if (pcpri_mode != sli_cpri_mode) begin
+      pcpri_mod_ch <= ~pcpri_mod_ch;
+    end 
+  end  
+end
+   
+
+// =============================================================================
+// Terminal count logic
+// =============================================================================
+
+//For SDI protocol with Dynamic rate control enabled
+generate
+if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "SDI")) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rcount_tc         <= 22'd0;
+    rdiff_comp_lock   <= 16'd0;
+    rdiff_comp_unlock <= 16'd0;
+  end
+  else begin
+    //Terminal count logic
+    //Div by 11 is enabled
+    if (rdiv11 == 1'b1) begin
+      //Gear mode is 16/20
+      if (rgear == 1'b1) begin
+        rcount_tc         <= PPCLK_DIV11_TC;
+        rdiff_comp_lock   <= PDIFF_DIV11_VAL_LOCK;
+        rdiff_comp_unlock <= PDIFF_DIV11_VAL_UNLOCK;
+      end
+      else begin
+        rcount_tc         <= {PPCLK_DIV11_TC[20:0], 1'b0};
+        rdiff_comp_lock   <= {PDIFF_DIV11_VAL_LOCK[14:0], 1'b0};
+        rdiff_comp_unlock <= {PDIFF_DIV11_VAL_UNLOCK[14:0], 1'b0};
+      end
+    end
+    //Div by 2 is enabled
+    else if (rdiv2 == 1'b1) begin
+      //Gear mode is 16/20
+      if (rgear == 1'b1) begin
+        rcount_tc         <= {1'b0,PPCLK_TC[21:1]};
+        rdiff_comp_lock   <= {1'b0,PDIFF_VAL_LOCK[15:1]};
+        rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]};
+      end
+      else begin
+        rcount_tc         <= PPCLK_TC;
+        rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+        rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+      end
+    end
+    //Both div by 11 and div by 2 are disabled
+    else begin
+      //Gear mode is 16/20
+      if (rgear == 1'b1) begin
+        rcount_tc         <= PPCLK_TC;
+        rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+        rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+      end
+      else begin
+        rcount_tc         <= {PPCLK_TC[20:0],1'b0};
+        rdiff_comp_lock   <= {PDIFF_VAL_LOCK[14:0],1'b0};
+        rdiff_comp_unlock <= {PDIFF_VAL_UNLOCK[14:0],1'b0};
+      end
+    end
+  end  
+end
+end
+endgenerate
+
+//For G8B10B protocol with Dynamic rate control enabled
+generate
+if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "G8B10B")) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rcount_tc         <= 22'd0;
+    rdiff_comp_lock   <= 16'd0;
+    rdiff_comp_unlock <= 16'd0;
+  end
+  else begin
+    //Terminal count logic
+    //Div by 2 is enabled
+    if (rdiv2 == 1'b1) begin
+      rcount_tc         <= {1'b0,PPCLK_TC[21:1]};
+      rdiff_comp_lock   <= {1'b0,PDIFF_VAL_LOCK[15:1]};
+      rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]};
+    end
+    else begin
+      rcount_tc         <= PPCLK_TC;
+      rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+      rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+    end
+  end  
+end
+end
+endgenerate
+
+
+//For CPRI protocol with Dynamic rate control is disabled
+generate
+if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "CPRI")) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rcount_tc         <= 22'd0;
+    rdiff_comp_lock   <= 16'd0;
+    rdiff_comp_unlock <= 16'd0;
+  end
+  else begin
+    //Terminal count logic for CPRI protocol
+    //Only if there is a change in the rate mode from the default
+    if (rcpri_mod_ch_st == 1'b1) begin
+      if (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) begin
+        case(sli_cpri_mode)
+          3'd0 : begin //For 0.6Gbps
+            rcount_tc         <= LPCLK_TC_0;
+            case(PLOL_SETTING)
+              'd0 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_00;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_00;
+              end
+              
+              'd1 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_01;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_01;
+              end
+              
+              'd2 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_02;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_02;
+              end
+              
+              'd3 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_03;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_03;
+              end
+              
+              default : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_00;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_00;
+              end
+            endcase
+          end
+          
+          3'd1 : begin //For 1.2Gbps
+            rcount_tc         <= LPCLK_TC_1;
+            case(PLOL_SETTING)
+              'd0 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_10;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_10;
+              end
+              
+              'd1 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_11;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_11;
+              end
+              
+              'd2 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_12;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_12;
+              end
+              
+              'd3 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_13;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_13;
+              end
+              
+              default : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_10;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_10;
+              end
+            endcase
+          end
+          
+          3'd2 : begin //For 2.4Gbps
+            rcount_tc         <= LPCLK_TC_2;
+            case(PLOL_SETTING)
+              'd0 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_20;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_20;
+              end
+              
+              'd1 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_21;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_21;
+              end
+              
+              'd2 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_22;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_22;
+              end
+              
+              'd3 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_23;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_23;
+              end
+              
+              default : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_20;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_20;
+              end
+            endcase
+          end
+          
+          3'd3 : begin //For 3.07Gbps
+            rcount_tc         <= LPCLK_TC_3;
+            case(PLOL_SETTING)
+              'd0 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_30;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_30;
+              end
+              
+              'd1 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_31;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_31;
+              end
+              
+              'd2 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_32;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_32;
+              end
+              
+              'd3 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_33;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_33;
+              end
+            endcase
+          end    
+              
+          3'd4 : begin //For 4.9125bps
+            rcount_tc         <= LPCLK_TC_4;
+            case(PLOL_SETTING)
+              'd0 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_40;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_40;
+              end
+              
+              'd1 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_41;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_41;
+              end
+              
+              'd2 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_42;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_42;
+              end
+              
+              'd3 : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_43;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_43;
+              end  
+            
+              default : begin
+                rdiff_comp_lock   <= LPDIFF_LOCK_40;
+                rdiff_comp_unlock <= LPDIFF_UNLOCK_40;
+              end
+            endcase
+          end
+        
+          default : begin
+            rcount_tc         <= LPCLK_TC_0;
+            rdiff_comp_lock   <= LPDIFF_LOCK_00;
+            rdiff_comp_unlock <= LPDIFF_UNLOCK_00;
+          end
+        endcase
+      end
+    end
+    else begin
+      //If there is no change in the CPRI rate mode from default
+      rcount_tc         <= PPCLK_TC;
+      rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+      rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+    end  
+  end  
+end
+end
+endgenerate
+
+//For PCIe protocol with Dynamic rate control disabled
+generate
+if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "PCIE")) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rcount_tc         <= 22'd0;
+    rdiff_comp_lock   <= 16'd0;
+    rdiff_comp_unlock <= 16'd0;
+  end
+  else begin
+    //Terminal count logic
+    if (PPCIE_MAX_RATE == "2.5") begin
+      //2.5G mode is enabled
+      rcount_tc         <= PPCLK_TC;
+      rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+      rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+    end
+    else begin
+      //5G mode is enabled
+      if (rpcie_mode == 1'b1) begin
+        rcount_tc         <= PPCLK_TC;
+        rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+        rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+      end
+      else begin
+        //2.5G mode is enabled
+        rcount_tc         <= {1'b0,PPCLK_TC[21:1]};
+        rdiff_comp_lock   <= {1'b0,PDIFF_VAL_LOCK[15:1]};
+        rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]};
+      end 
+    end          
+  end  
+end
+end
+endgenerate
+
+//For all protocols other than CPRI & PCIe
+generate
+if ((PDYN_RATE_CTRL == "DISABLED") && ((PPROTOCOL != "CPRI") && (PPROTOCOL != "PCIE"))) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    rcount_tc         <= 22'd0;
+    rdiff_comp_lock   <= 16'd0;
+    rdiff_comp_unlock <= 16'd0;
+  end
+  else begin
+    //Terminal count logic for all protocols other than CPRI & PCIe
+    rcount_tc         <= PPCLK_TC;
+    rdiff_comp_lock   <= PDIFF_VAL_LOCK;
+    rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+  end  
+end
+end
+endgenerate
+
+
+// =============================================================================
+// Tx_pclk counter, Heartbeat and Differential value logic
+// =============================================================================
+always @(posedge sli_pclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    pcount      <= 22'd0;
+    pcount_diff <= 22'd65535;
+    phb_cnt     <= 3'd0;
+    phb         <= 1'b0;
+  end
+  else begin
+    //Counter logic
+    if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin
+      pcount <= 22'd0;
+    end
+    else begin
+      pcount <= pcount + 1;
+    end
+    
+    //Heartbeat logic
+    phb_cnt <= phb_cnt + 1;
+    
+    if ((phb_cnt < 3'd4) && (phb_cnt >= 3'd0)) begin
+      phb <= 1'b1;
+    end  
+    else begin
+      phb <= 1'b0;  
+    end 
+    
+    //Differential value logic
+    if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin
+      pcount_diff <= rcount_tc + ~(pcount) + 1;
+    end  
+    else if (ppul_sync_p2 == 1'b1 && ppul_sync_p3 == 1'b0) begin
+      if (pcount_diff[21] == 1'b1) begin
+        pcount_diff <= ~(pcount_diff) + 1;
+      end
+    end
+  end  
+end
+
+
+// =============================================================================
+// State transition logic for SLL FSM
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    sll_state <= LPLL_LOSS_ST; 
+  end
+  else begin
+    //Reasons to declare an immediate loss - Absence of Tx_pclk, Dynamic rate change for SDI or CPRI
+    if ((rstat_pclk == 1'b0) || (rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || 
+    (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin
+      sll_state <= LPLL_LOSS_ST;
+    end
+    else begin  
+      case(sll_state)
+        LPLL_LOSS_ST : begin
+          if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin
+            if (unlock) begin
+              sll_state <= LPLL_LOSS_ST;
+            end
+            else if (lock) begin
+              if (PLOL_SETTING == 2'd0) begin
+                sll_state <= LPLL_PRELOCK_ST;
+              end
+              else begin
+                sll_state <= LPLL_LOCK_ST;
+              end
+            end
+          end
+        end
+        
+        LPLL_LOCK_ST : begin
+          if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin
+            if (lock) begin
+              sll_state <= LPLL_LOCK_ST;
+            end
+            else begin
+              if (PLOL_SETTING == 2'd0) begin
+                sll_state <= LPLL_LOSS_ST;
+              end
+              else begin
+                sll_state <= LPLL_PRELOSS_ST;
+              end
+            end
+          end
+        end
+        
+        LPLL_PRELOCK_ST : begin
+          if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin
+            if (lock) begin
+              sll_state <= LPLL_LOCK_ST;
+            end
+            else begin
+              sll_state <= LPLL_PRELOSS_ST;
+            end
+          end
+        end
+        
+        LPLL_PRELOSS_ST : begin
+          if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin
+            if (unlock) begin
+              sll_state <= LPLL_PRELOSS_ST;
+            end
+            else if (lock) begin
+              sll_state <= LPLL_LOCK_ST;
+            end
+          end
+        end
+        
+        default: begin
+          sll_state <= LPLL_LOSS_ST;
+        end
+      endcase
+    end  
+  end  
+end
+
+
+// =============================================================================
+// Logic for Tx PLL Lock
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+  if (sli_rst == 1'b1) begin
+    pll_lock <= 1'b0; 
+  end
+  else begin
+    case(sll_state)
+      LPLL_LOSS_ST : begin
+        pll_lock <= 1'b0;
+      end
+      
+      LPLL_LOCK_ST : begin
+        pll_lock <= 1'b1;
+      end
+      
+      LPLL_PRELOSS_ST : begin
+        pll_lock <= 1'b0;
+      end
+      
+      default: begin
+        pll_lock <= 1'b0;
+      end
+    endcase
+  end  
+end
+
+assign slo_plol = ~(pll_lock);
+
+endmodule  
+
+
+//   ===========================================================================
+//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
+//   ---------------------------------------------------------------------------
+//   Copyright (c) 2015 by Lattice Semiconductor Corporation
+//   ALL RIGHTS RESERVED 
+//   ------------------------------------------------------------------
+//
+//   Permission:
+//
+//      Lattice SG Pte. Ltd. grants permission to use this code
+//      pursuant to the terms of the Lattice Reference Design License Agreement. 
+//
+//
+//   Disclaimer:
+//
+//      This VHDL or Verilog source code is intended as a design reference
+//      which illustrates how these types of functions can be implemented.
+//      It is the user's responsibility to verify their design for
+//      consistency and functionality through the use of formal
+//      verification methods.  Lattice provides no warranty
+//      regarding the use or functionality of this code.
+//
+//   ---------------------------------------------------------------------------
+//
+//                  Lattice SG Pte. Ltd.
+//                  101 Thomson Road, United Square #07-02 
+//                  Singapore 307591
+//
+//
+//                  TEL: 1-800-Lattice (USA and Canada)
+//                       +65-6631-2000 (Singapore)
+//                       +1-503-268-8001 (other locations)
+//
+//                  web: http://www.latticesemi.com/
+//                  email: techsupport@latticesemi.com
+//
+//   ---------------------------------------------------------------------------
+//
+// =============================================================================
+//                         FILE DETAILS
+// Project               : Synchronizer Logic
+// File                  : sync.v
+// Title                 : Synchronizer module
+// Description           : 
+// =============================================================================
+//                         REVISION HISTORY
+// Version               : 1.0
+// Author(s)             : AV
+// Mod. Date             : July 7, 2015
+// Changes Made          : Initial Creation
+// -----------------------------------------------------------------------------
+// Version               : 1.1
+// Author(s)             : EB
+// Mod. Date             : March 21, 2017
+// Changes Made          : 
+// =============================================================================
+
+`ifndef PCS_SYNC_MODULE
+`define PCS_SYNC_MODULE
+module sync ( 
+  clk,
+  rst,
+  data_in,
+  data_out
+  );
+  
+input  clk;                  //Clock in which the async data needs to be synchronized to
+input  rst;                  //Active high reset
+input  data_in;              //Asynchronous data
+output data_out;             //Synchronized data
+
+parameter PDATA_RST_VAL = 0; //Reset value for the registers
+
+reg data_p1;
+reg data_p2;
+
+// =============================================================================
+// Synchronization logic
+// =============================================================================
+always @(posedge clk or posedge rst) begin
+  if (rst == 1'b1) begin
+    data_p1 <= PDATA_RST_VAL;
+    data_p2 <= PDATA_RST_VAL; 
+  end
+  else begin
+    data_p1 <= data_in;
+    data_p2 <= data_p1;
+  end  
+end
+
+assign data_out = data_p2; 
+
+endmodule    
+`endif
+

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/.recordref b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/.recordref
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/_CMD_.CML b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/_CMD_.CML
new file mode 100644 (file)
index 0000000..4fa0e06
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/_CMD_.CML
@@ -0,0 +1 @@
+ -osyn  /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.srs  -top  serdes_sync_1  -hdllog  /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_compiler.srr  -encrypt  -mp  4  -verification_mode 0  -vhdl  -prodtype  synplify_pro  -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver  -encrypt  -pro  -dmgen  /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/dm  -lite -ui -fid2 -ram -sharing on -ll 2000 -autosm  -ignore_undefined_lib  -lib work /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd  -verilog  -prodtype  synplify_pro  -dspmac -fixsmult -infer_seqShift -nram -sdff_counter -divnmod -nostructver   -I /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/  -I /home/soft/lattice/diamond/3.10_x64/synpbase/lib   -v2001  -devicelib  /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v  -devicelib  /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v  -encrypt  -pro  -dmgen  /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/dm  -ui -fid2 -ram -sharing on -ll 2000 -autosm  -lib work /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v  -jobname  "compiler" 
\ No newline at end of file

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/_cmd._cml b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/_cmd._cml
new file mode 100644 (file)
index 0000000..20bb359
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/_cmd._cml
@@ -0,0 +1 @@
+-link    -encrypt        -top serdes_sync_1 -osyn /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.srs /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer0.srs /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.srs   
\ No newline at end of file

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/backup/serdes_sync_1.srr b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/backup/serdes_sync_1.srr
new file mode 100644 (file)
index 0000000..5a66bb2
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/backup/serdes_sync_1.srr
@@ -0,0 +1,1145 @@
+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
+#install: /home/soft/lattice/diamond/3.10_x64/synpbase
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Fri May 10 09:32:32 2019
+
+#Implementation: syn_results
+
+Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Top entity is set to serdes_sync_1.
+VHDL syntax check successful!
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Fri May 10 09:32:33 2019
+
+###########################################################]
+Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v" (library work)
+Verilog syntax check successful!
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Fri May 10 09:32:33 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Top entity is set to serdes_sync_1.
+VHDL syntax check successful!
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Synthesizing work.serdes_sync_1.v1.
+Post processing for work.serdes_sync_1.v1
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB)
+
+
+Process completed successfully.
+# Fri May 10 09:32:33 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v" (library work)
+Verilog syntax check successful!
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work.
+
+       PDATA_RST_VAL=32'b00000000000000000000000000000000
+   Generated name = sync_0s
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1051:7:1051:27|Synthesizing module serdes_sync_1sll_core in library work.
+
+       PPROTOCOL=48'b010001110011100001000010001100010011000001000010
+       PLOL_SETTING=32'b00000000000000000000000000000001
+       PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100
+       PPCIE_MAX_RATE=24'b001100100010111000110101
+       PDIFF_VAL_LOCK=32'b00000000000000000000000000010011
+       PDIFF_VAL_UNLOCK=32'b00000000000000000000000010000011
+       PPCLK_TC=32'b00000000000000010000000000000000
+       PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000
+       PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000
+       PPCLK_DIV11_TC=32'b00000000000000000000000000000000
+       LPLL_LOSS_ST=2'b00
+       LPLL_PRELOSS_ST=2'b01
+       LPLL_PRELOCK_ST=2'b10
+       LPLL_LOCK_ST=2'b11
+       LRCLK_TC=16'b1111111111111111
+       LRCLK_TC_PUL_WIDTH=16'b0000000000110010
+       LHB_WAIT_CNT=8'b11111111
+       LPCLK_TC_0=32'b00000000000000001000000000000000
+       LPCLK_TC_1=32'b00000000000000010000000000000000
+       LPCLK_TC_2=32'b00000000000000100000000000000000
+       LPCLK_TC_3=32'b00000000000000101000000000000000
+       LPCLK_TC_4=32'b00000000000000010000000000000000
+       LPDIFF_LOCK_00=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_10=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_20=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_30=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_40=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_01=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_11=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_21=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_31=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_41=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_02=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_12=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_22=32'b00000000000000000000000011000100
+       LPDIFF_LOCK_32=32'b00000000000000000000000011110101
+       LPDIFF_LOCK_42=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_03=32'b00000000000000000000000010000011
+       LPDIFF_LOCK_13=32'b00000000000000000000000100000110
+       LPDIFF_LOCK_23=32'b00000000000000000000001000001100
+       LPDIFF_LOCK_33=32'b00000000000000000000001010001111
+       LPDIFF_LOCK_43=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011
+       LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110
+       LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010
+       LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001
+       LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111
+       LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000
+       LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000
+       LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000
+       LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100
+       LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001
+       LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010
+       LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111
+       LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001
+   Generated name = serdes_sync_1sll_core_Z1_layer1
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1287:54:1287:59|Removing redundant assignment.
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1293:52:1293:55|Removing redundant assignment.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL177 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Sharing sequential element genblk5.rdiff_comp_lock. Add a syn_preserve attribute to the element to prevent sharing.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 17 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":92:7:92:27|Synthesizing module serdes_sync_1rsl_core in library work.
+
+       pnum_channels=32'b00000000000000000000000000000001
+       pprotocol=48'b010001110011100001000010001100010011000001000010
+       pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
+       pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_tx_rdy=32'b00000000000000000000101110111000
+       pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_rx_rdy=32'b00000000000000000000101110111000
+       wa_num_cycles=32'b00000000000000000000010000000000
+       dac_num_cycles=32'b00000000000000000000000000000011
+       lreset_pwidth=32'b00000000000000000000000000000011
+       lwait_b4_trst=32'b00000000000010111110101111000010
+       lwait_b4_trst_s=32'b00000000000000000000001100001101
+       lplol_cnt_width=32'b00000000000000000000000000010100
+       lwait_after_plol0=32'b00000000000000000000000000000100
+       lwait_b4_rrst=32'b00000000000000101100000000000000
+       lrrst_wait_width=32'b00000000000000000000000000010100
+       lwait_after_rrst=32'b00000000000011000011010100000000
+       lwait_b4_rrst_s=32'b00000000000000000000000111001100
+       lrlol_cnt_width=32'b00000000000000000000000000010011
+       lwait_after_lols=32'b00000000000000001100010000000000
+       lwait_after_lols_s=32'b00000000000000000000000010010110
+       llols_cnt_width=32'b00000000000000000000000000010010
+       lrdb_max=32'b00000000000000000000000000001111
+       ltxr_wait_width=32'b00000000000000000000000000001100
+       lrxr_wait_width=32'b00000000000000000000000000001100
+   Generated name = serdes_sync_1rsl_core_Z2_layer1
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning register bits 7 to 6 of genblk5.rdiff_comp_unlock[7:5]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[5]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[16]. Make sure that there are no unused intermediate registers.
+@N: CL201 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state.
+Extracted state machine for register sll_state
+State machine has 3 reachable states with original encodings of:
+   00
+   01
+   11
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB)
+
+
+Process completed successfully.
+# Fri May 10 09:32:34 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+
+=======================================================================================
+For a summary of linker messages for components that did not bind, please see log file:
+@L: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.linkerlog
+=======================================================================================
+
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 09:32:34 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 09:32:34 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 09:32:35 2019
+
+###########################################################]
+Pre-mapping Report
+
+# Fri May 10 09:32:35 2019
+
+Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc
+@L: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_scck.rpt 
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_scck.rpt" file 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 115MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 117MB)
+
+@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances.
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist serdes_sync_1
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
+
+
+
+Clock Summary
+******************
+
+          Start                                    Requested     Requested     Clock        Clock                   Clock
+Level     Clock                                    Frequency     Period        Type         Group                   Load 
+-------------------------------------------------------------------------------------------------------------------------
+0 -       System                                   100.0 MHz     10.000        system       system_clkgroup         0    
+                                                                                                                         
+0 -       serdes_sync_1|pll_refclki                100.0 MHz     10.000        inferred     Inferred_clkgroup_0     92   
+                                                                                                                         
+0 -       serdes_sync_1|rxrefclk                   100.0 MHz     10.000        inferred     Inferred_clkgroup_1     77   
+                                                                                                                         
+0 -       serdes_sync_1|tx_pclk_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_2     53   
+=========================================================================================================================
+
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Found inferred clock serdes_sync_1|pll_refclki which controls 92 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Found inferred clock serdes_sync_1|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Found inferred clock serdes_sync_1|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 145MB)
+
+Encoding state machine sll_state[2:0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   11 -> 10
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 59MB peak: 145MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Fri May 10 09:32:36 2019
+
+###########################################################]
+Map & Optimize Report
+
+# Fri May 10 09:32:36 2019
+
+Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[2:0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   11 -> 10
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1350:0:1350:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1304:0:1304:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance rcount[15:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1759:0:1759:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance pcount[21:0] 
+@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1801:0:1801:5|Removing sequential instance sll_state[0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":412:3:412:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":909:3:909:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":527:3:527:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":778:3:778:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":680:3:680:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] 
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
+
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+   1           0h:00m:01s                   5.35ns              151 /       220
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+3 non-gated/non-generated clock tree(s) driving 220 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+============================================= Non-Gated/Non-Generated Clocks =============================================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                                   
+--------------------------------------------------------------------------------------------------------------------------
+@K:CKID0001       pll_refclki         port                   90         rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]
+@K:CKID0002       rxrefclk            port                   77         rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]
+@K:CKID0003       DCU0_inst           DCUA                   53         sll_inst.pcount_diff[21]                          
+==========================================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 148MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 148MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.edn
+M-2017.03L-SP1-1
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 152MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 152MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB)
+
+@W: MT246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":160:4:160:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+@W: MT420 |Found inferred clock serdes_sync_1|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"
+@W: MT420 |Found inferred clock serdes_sync_1|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"
+@W: MT420 |Found inferred clock serdes_sync_1|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk"
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Fri May 10 09:32:39 2019
+#
+
+
+Top view:               serdes_sync_1
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 4.079
+
+@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
+                                         Requested     Estimated     Requested     Estimated               Clock        Clock              
+Starting Clock                           Frequency     Frequency     Period        Period        Slack     Type         Group              
+-------------------------------------------------------------------------------------------------------------------------------------------
+serdes_sync_1|pll_refclki                100.0 MHz     168.9 MHz     10.000        5.921         4.079     inferred     Inferred_clkgroup_0
+serdes_sync_1|rxrefclk                   100.0 MHz     170.5 MHz     10.000        5.864         4.136     inferred     Inferred_clkgroup_1
+serdes_sync_1|tx_pclk_inferred_clock     100.0 MHz     237.5 MHz     10.000        4.211         5.789     inferred     Inferred_clkgroup_2
+System                                   100.0 MHz     840.7 MHz     10.000        1.190         8.810     system       system_clkgroup    
+===========================================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                                                                      |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Starting                              Ending                                |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+System                                System                                |  10.000      10.000  |  No paths    -      |  No paths    -      |  No paths    -    
+System                                serdes_sync_1|rxrefclk                |  10.000      8.811   |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|pll_refclki             System                                |  10.000      8.307   |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|pll_refclki             serdes_sync_1|pll_refclki             |  10.000      4.079   |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|pll_refclki             serdes_sync_1|tx_pclk_inferred_clock  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|rxrefclk                System                                |  10.000      8.193   |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|rxrefclk                serdes_sync_1|rxrefclk                |  10.000      4.136   |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|tx_pclk_inferred_clock  serdes_sync_1|pll_refclki             |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|tx_pclk_inferred_clock  serdes_sync_1|tx_pclk_inferred_clock  |  10.000      5.789   |  No paths    -      |  No paths    -      |  No paths    -    
+===================================================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: serdes_sync_1|pll_refclki
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                   Starting                                                           Arrival          
+Instance                           Reference                     Type        Pin     Net              Time        Slack
+                                   Clock                                                                               
+-----------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[1]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[1]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[6]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[6]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[7]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[7]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[12]     serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[12]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[2]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[2]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[3]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[3]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[4]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[4]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[5]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[5]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[8]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[8]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[9]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[9]      0.907       4.684
+=======================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                   Starting                                                             Required          
+Instance                           Reference                     Type        Pin     Net                Time         Slack
+                                   Clock                                                                                  
+--------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[19]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[19]     9.946        4.079
+rsl_inst.genblk1\.plol_cnt[17]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[17]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[18]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[18]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[15]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[15]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[16]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[16]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[13]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[13]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[14]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[14]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[11]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[11]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[12]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[12]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[9]      serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[9]      9.946        4.383
+==========================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.867
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     4.079
+
+    Number of logic level(s):                15
+    Starting point:                          rsl_inst.genblk1\.plol_cnt[1] / Q
+    Ending point:                            rsl_inst.genblk1\.plol_cnt[19] / D
+    The start point is clocked by            serdes_sync_1|pll_refclki [rising] on pin CK
+    The end   point is clocked by            serdes_sync_1|pll_refclki [rising] on pin CK
+
+Instance / Net                                        Pin      Pin               Arrival     No. of    
+Name                                     Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[1]            FD1S3DX      Q        Out     0.907     0.907       -         
+plol_cnt[1]                              Net          -        -       -         -           2         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     Z        Out     0.606     1.513       -         
+un1_plol_cnt_tc_10                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     Z        Out     0.606     2.119       -         
+un1_plol_cnt_tc_14                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     Z        Out     0.762     2.881       -         
+un1_plol_cnt_tc                          Net          -        -       -         -           5         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     B        In      0.000     2.881       -         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     Z        Out     0.840     3.721       -         
+plol_cnt                                 Net          -        -       -         -           21        
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.721       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.621       -         
+plol_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.621       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.682       -         
+plol_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.682       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.743       -         
+plol_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.743       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.804       -         
+plol_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.804       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.865       -         
+plol_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.865       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.926       -         
+plol_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.926       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.987       -         
+plol_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.987       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.048       -         
+plol_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.048       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.109       -         
+plol_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.109       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        COUT     Out     0.061     5.170       -         
+plol_cnt_cry[18]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        CIN      In      0.000     5.170       -         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        S0       Out     0.698     5.867       -         
+plol_cnt_s[19]                           Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt[19]           FD1S3DX      D        In      0.000     5.867       -         
+=======================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: serdes_sync_1|rxrefclk
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                     Starting                                                          Arrival          
+Instance                             Reference                  Type        Pin     Net                Time        Slack
+                                     Clock                                                                              
+------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[14]      serdes_sync_1|rxrefclk     FD1P3DX     Q       rlol1_cnt[14]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[15]      serdes_sync_1|rxrefclk     FD1P3DX     Q       rlol1_cnt[15]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[16]      serdes_sync_1|rxrefclk     FD1P3DX     Q       rlol1_cnt[16]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[17]      serdes_sync_1|rxrefclk     FD1P3DX     Q       rlol1_cnt[17]      0.907       4.136
+rsl_inst.genblk2\.rlols0_cnt[9]      serdes_sync_1|rxrefclk     FD1P3DX     Q       rlols0_cnt[9]      0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[11]     serdes_sync_1|rxrefclk     FD1P3DX     Q       rlols0_cnt[11]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[12]     serdes_sync_1|rxrefclk     FD1P3DX     Q       rlols0_cnt[12]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[13]     serdes_sync_1|rxrefclk     FD1P3DX     Q       rlols0_cnt[13]     0.907       4.170
+rsl_inst.genblk2\.rlol1_cnt[0]       serdes_sync_1|rxrefclk     FD1P3DX     Q       rlol1_cnt[0]       0.907       4.742
+rsl_inst.genblk2\.rlol1_cnt[1]       serdes_sync_1|rxrefclk     FD1P3DX     Q       rlol1_cnt[1]       0.907       4.742
+========================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                     Starting                                                            Required          
+Instance                             Reference                  Type        Pin     Net                  Time         Slack
+                                     Clock                                                                                 
+---------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[17]      serdes_sync_1|rxrefclk     FD1P3DX     D       rlol1_cnt_s[17]      9.946        4.136
+rsl_inst.genblk2\.rlol1_cnt[18]      serdes_sync_1|rxrefclk     FD1P3DX     D       rlol1_cnt_s[18]      9.946        4.136
+rsl_inst.genblk2\.rlols0_cnt[17]     serdes_sync_1|rxrefclk     FD1P3DX     D       rlols0_cnt_s[17]     9.946        4.170
+rsl_inst.genblk2\.rlol1_cnt[15]      serdes_sync_1|rxrefclk     FD1P3DX     D       rlol1_cnt_s[15]      9.946        4.197
+rsl_inst.genblk2\.rlol1_cnt[16]      serdes_sync_1|rxrefclk     FD1P3DX     D       rlol1_cnt_s[16]      9.946        4.197
+rsl_inst.genblk2\.rlols0_cnt[15]     serdes_sync_1|rxrefclk     FD1P3DX     D       rlols0_cnt_s[15]     9.946        4.231
+rsl_inst.genblk2\.rlols0_cnt[16]     serdes_sync_1|rxrefclk     FD1P3DX     D       rlols0_cnt_s[16]     9.946        4.231
+rsl_inst.genblk2\.rlol1_cnt[13]      serdes_sync_1|rxrefclk     FD1P3DX     D       rlol1_cnt_s[13]      9.946        4.258
+rsl_inst.genblk2\.rlol1_cnt[14]      serdes_sync_1|rxrefclk     FD1P3DX     D       rlol1_cnt_s[14]      9.946        4.258
+rsl_inst.genblk2\.rlols0_cnt[13]     serdes_sync_1|rxrefclk     FD1P3DX     D       rlols0_cnt_s[13]     9.946        4.292
+===========================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.809
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.136
+
+    Number of logic level(s):                14
+    Starting point:                          rsl_inst.genblk2\.rlol1_cnt[14] / Q
+    Ending point:                            rsl_inst.genblk2\.rlol1_cnt[18] / D
+    The start point is clocked by            serdes_sync_1|rxrefclk [rising] on pin CK
+    The end   point is clocked by            serdes_sync_1|rxrefclk [rising] on pin CK
+
+Instance / Net                                         Pin      Pin               Arrival     No. of    
+Name                                      Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[14]           FD1P3DX      Q        Out     0.907     0.907       -         
+rlol1_cnt[14]                             Net          -        -       -         -           2         
+rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     Z        Out     0.606     1.513       -         
+rlol1_cnt_tc_1_10                         Net          -        -       -         -           1         
+rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     Z        Out     0.606     2.119       -         
+rlol1_cnt_tc_1_14                         Net          -        -       -         -           1         
+rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     Z        Out     0.768     2.887       -         
+rlol1_cnt_tc_1                            Net          -        -       -         -           6         
+rsl_inst.genblk2\.rlos_db_p1_RNIS0OP      ORCALUT4     A        In      0.000     2.887       -         
+rsl_inst.genblk2\.rlos_db_p1_RNIS0OP      ORCALUT4     Z        Out     0.837     3.724       -         
+rlol1_cnt                                 Net          -        -       -         -           20        
+rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.724       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.624       -         
+rlol1_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.624       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.685       -         
+rlol1_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.685       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.746       -         
+rlol1_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.746       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.807       -         
+rlol1_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.807       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.868       -         
+rlol1_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.868       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.929       -         
+rlol1_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.929       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.990       -         
+rlol1_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.990       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.051       -         
+rlol1_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.051       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.112       -         
+rlol1_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.112       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        S1       Out     0.698     5.809       -         
+rlol1_cnt_s[18]                           Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt[18]           FD1P3DX      D        In      0.000     5.809       -         
+========================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: serdes_sync_1|tx_pclk_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                            Starting                                                                      Arrival          
+Instance                    Reference                                Type        Pin     Net              Time        Slack
+                            Clock                                                                                          
+---------------------------------------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1       serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p1     1.098       5.789
+sll_inst.ppul_sync_p2       serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p2     1.098       5.789
+sll_inst.pcount_diff[0]     serdes_sync_1|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_0      0.985       6.147
+sll_inst.pcount[0]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[0]        0.955       6.178
+sll_inst.pcount_diff[1]     serdes_sync_1|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_1      0.955       6.239
+sll_inst.pcount_diff[2]     serdes_sync_1|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_2      0.955       6.239
+sll_inst.pcount[1]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[1]        0.907       6.287
+sll_inst.pcount[2]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[2]        0.907       6.287
+sll_inst.pcount_diff[3]     serdes_sync_1|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_3      0.955       6.300
+sll_inst.pcount_diff[4]     serdes_sync_1|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_4      0.955       6.300
+===========================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                             Starting                                                                                     Required          
+Instance                     Reference                                Type        Pin     Net                             Time         Slack
+                             Clock                                                                                                          
+--------------------------------------------------------------------------------------------------------------------------------------------
+sll_inst.pcount[21]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[21]                    9.946        5.789
+sll_inst.pcount[19]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[19]                    9.946        5.850
+sll_inst.pcount[20]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[20]                    9.946        5.850
+sll_inst.pcount[17]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[17]                    9.946        5.911
+sll_inst.pcount[18]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[18]                    9.946        5.911
+sll_inst.pcount[15]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[15]                    9.946        5.972
+sll_inst.pcount[16]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[16]                    9.946        5.972
+sll_inst.pcount[13]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[13]                    9.946        6.033
+sll_inst.pcount[14]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[14]                    9.946        6.033
+sll_inst.pcount_diff[21]     serdes_sync_1|tx_pclk_inferred_clock     FD1P3DX     D       un1_pcount_diff_1_s_21_0_S0     9.946        6.034
+============================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      4.157
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 5.789
+
+    Number of logic level(s):                13
+    Starting point:                          sll_inst.ppul_sync_p1 / Q
+    Ending point:                            sll_inst.pcount[21] / D
+    The start point is clocked by            serdes_sync_1|tx_pclk_inferred_clock [rising] on pin CK
+    The end   point is clocked by            serdes_sync_1|tx_pclk_inferred_clock [rising] on pin CK
+
+Instance / Net                             Pin      Pin               Arrival     No. of    
+Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1         FD1S3DX      Q        Out     1.098     1.098       -         
+ppul_sync_p1                  Net          -        -       -         -           25        
+sll_inst.pcount10_0_o3        ORCALUT4     A        In      0.000     1.098       -         
+sll_inst.pcount10_0_o3        ORCALUT4     Z        Out     0.851     1.950       -         
+N_8                           Net          -        -       -         -           25        
+sll_inst.pcount_cry_0[0]      CCU2C        A1       In      0.000     1.950       -         
+sll_inst.pcount_cry_0[0]      CCU2C        COUT     Out     0.900     2.850       -         
+pcount_cry[0]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[1]      CCU2C        CIN      In      0.000     2.850       -         
+sll_inst.pcount_cry_0[1]      CCU2C        COUT     Out     0.061     2.911       -         
+pcount_cry[2]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[3]      CCU2C        CIN      In      0.000     2.911       -         
+sll_inst.pcount_cry_0[3]      CCU2C        COUT     Out     0.061     2.972       -         
+pcount_cry[4]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[5]      CCU2C        CIN      In      0.000     2.972       -         
+sll_inst.pcount_cry_0[5]      CCU2C        COUT     Out     0.061     3.033       -         
+pcount_cry[6]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[7]      CCU2C        CIN      In      0.000     3.033       -         
+sll_inst.pcount_cry_0[7]      CCU2C        COUT     Out     0.061     3.094       -         
+pcount_cry[8]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[9]      CCU2C        CIN      In      0.000     3.094       -         
+sll_inst.pcount_cry_0[9]      CCU2C        COUT     Out     0.061     3.155       -         
+pcount_cry[10]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[11]     CCU2C        CIN      In      0.000     3.155       -         
+sll_inst.pcount_cry_0[11]     CCU2C        COUT     Out     0.061     3.216       -         
+pcount_cry[12]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[13]     CCU2C        CIN      In      0.000     3.216       -         
+sll_inst.pcount_cry_0[13]     CCU2C        COUT     Out     0.061     3.277       -         
+pcount_cry[14]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[15]     CCU2C        CIN      In      0.000     3.277       -         
+sll_inst.pcount_cry_0[15]     CCU2C        COUT     Out     0.061     3.338       -         
+pcount_cry[16]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[17]     CCU2C        CIN      In      0.000     3.338       -         
+sll_inst.pcount_cry_0[17]     CCU2C        COUT     Out     0.061     3.399       -         
+pcount_cry[18]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[19]     CCU2C        CIN      In      0.000     3.399       -         
+sll_inst.pcount_cry_0[19]     CCU2C        COUT     Out     0.061     3.460       -         
+pcount_cry[20]                Net          -        -       -         -           1         
+sll_inst.pcount_s_0[21]       CCU2C        CIN      In      0.000     3.460       -         
+sll_inst.pcount_s_0[21]       CCU2C        S0       Out     0.698     4.157       -         
+pcount_s[21]                  Net          -        -       -         -           1         
+sll_inst.pcount[21]           FD1S3DX      D        In      0.000     4.157       -         
+============================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                                   Arrival           
+Instance      Reference     Type     Pin                Net              Time        Slack 
+              Clock                                                                        
+-------------------------------------------------------------------------------------------
+DCU0_inst     System        DCUA     CH0_FFS_RLOL       rx_cdr_lol_s     0.000       8.810 
+DCU0_inst     System        DCUA     CH0_FFS_RLOS       rx_los_low_s     0.000       8.810 
+DCU0_inst     System        DCUA     CH0_FF_RX_PCLK     rx_pclk          0.000       10.000
+===========================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                       Starting                                                                       Required           
+Instance                                               Reference     Type        Pin                Net                               Time         Slack 
+                                                       Clock                                                                                             
+---------------------------------------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     SP                 un2_rdo_serdes_rst_dual_c_2_i     9.806        8.810 
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     D                  un2_rdo_serdes_rst_dual_c_1       9.946        9.556 
+rsl_inst.genblk2\.rlol_p1                              System        FD1S3DX     D                  rx_cdr_lol_s                      9.946        9.946 
+rsl_inst.genblk2\.rlos_p1                              System        FD1S3DX     D                  rx_los_low_s                      9.946        9.946 
+DCU0_inst                                              System        DCUA        CH0_FF_RXI_CLK     rx_pclk                           10.000       10.000
+=========================================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.194
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.806
+
+    - Propagation time:                      0.996
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 8.810
+
+    Number of logic level(s):                2
+    Starting point:                          DCU0_inst / CH0_FFS_RLOL
+    Ending point:                            rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            serdes_sync_1|rxrefclk [rising] on pin CK
+
+Instance / Net                                                          Pin              Pin               Arrival     No. of    
+Name                                                       Type         Name             Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------------------------------------------------
+DCU0_inst                                                  DCUA         CH0_FFS_RLOL     Out     0.000     0.000       -         
+rx_cdr_lol_s                                               Net          -                -       -         -           4         
+rsl_inst.un2_rdo_serdes_rst_dual_c_2_0                     ORCALUT4     B                In      0.000     0.000       -         
+rsl_inst.un2_rdo_serdes_rst_dual_c_2_0                     ORCALUT4     Z                Out     0.606     0.606       -         
+un2_rdo_serdes_rst_dual_c_2_0                              Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO[0]     ORCALUT4     B                In      0.000     0.606       -         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO[0]     ORCALUT4     Z                Out     0.390     0.996       -         
+un2_rdo_serdes_rst_dual_c_2_i                              Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]         FD1P3DX      SP               In      0.000     0.996       -         
+=================================================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 220 of 24288 (1%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+CCU2C:          113
+DCUA:           1
+FD1P3BX:        20
+FD1P3DX:        92
+FD1S3BX:        12
+FD1S3DX:        96
+GSR:            1
+INV:            3
+ORCALUT4:       150
+PFUMX:          2
+PUR:            1
+VHI:            6
+VLO:            6
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 152MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Fri May 10 09:32:40 2019
+
+###########################################################]

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/dm/layer0.xdm b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/dm/layer0.xdm
new file mode 100644 (file)
index 0000000..9cf4948
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/dm/layer0.xdm
@@ -0,0 +1,542 @@
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index 0000000..33af778
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diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/run_options.txt b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/run_options.txt
new file mode 100644 (file)
index 0000000..4af0c5d
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/run_options.txt
@@ -0,0 +1,76 @@
+#--  Synopsys, Inc.
+#--  Version M-2017.03L-SP1-1
+#--  Project file /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/run_options.txt
+#--  Written on Fri May 10 10:23:30 2019
+
+
+#project files
+add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd"
+add_file -verilog "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v"
+add_file -fpga_constraint "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc"
+
+
+
+#implementation: "syn_results"
+impl -add syn_results -type fpga
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+
+#device options
+set_option -technology ecp5um
+set_option -part LFE5UM_25F
+set_option -package MG285C
+set_option -speed_grade -6
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -top_module "serdes_sync_1"
+
+# hdl_compiler_options
+set_option -distributed_compile 0
+
+# mapper_without_write_options
+set_option -frequency 100
+set_option -srs_instrumentation 1
+
+# mapper_options
+set_option -write_verilog 1
+set_option -write_vhdl 1
+
+# Lattice XP
+set_option -maxfan 50
+set_option -disable_io_insertion 1
+set_option -retiming 0
+set_option -pipe 0
+set_option -forcegsr false
+set_option -fix_gated_and_generated_clocks 1
+set_option -rw_check_on_ram 1
+set_option -update_models_cp 0
+set_option -syn_edif_array_rename 1
+set_option -Write_declared_clocks_only 1
+
+# NFilter
+set_option -no_sequential_opt 0
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "./serdes_sync_1.edn"
+
+#set log file 
+set_option log_file "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srf" 
+impl -active "syn_results"

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/scemi_cfg.txt b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/scemi_cfg.txt
new file mode 100644 (file)
index 0000000..868d437
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/scemi_cfg.txt
@@ -0,0 +1,3 @@
+## UMR3 MESSAGE PORT CONFIGURATION FILE
+## ************************************
+XTOR_DPI_MSG_PORT_UMR_ADDR_VERSION=0

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/scratchproject.prs b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/scratchproject.prs
new file mode 100644 (file)
index 0000000..27162ad
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/scratchproject.prs
@@ -0,0 +1,74 @@
+#--  Synopsys, Inc.
+#--  Version M-2017.03L-SP1-1
+#--  Project file /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/scratchproject.prs
+
+#project files
+add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd"
+add_file -verilog "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v"
+add_file -fpga_constraint "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc"
+
+
+
+#implementation: "syn_results"
+impl -add /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results -type fpga
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+
+#device options
+set_option -technology ecp5um
+set_option -part LFE5UM_25F
+set_option -package MG285C
+set_option -speed_grade -6
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -top_module "serdes_sync_1"
+
+# hdl_compiler_options
+set_option -distributed_compile 0
+
+# mapper_without_write_options
+set_option -frequency 100
+set_option -srs_instrumentation 1
+
+# mapper_options
+set_option -write_verilog 1
+set_option -write_vhdl 1
+
+# Lattice XP
+set_option -maxfan 50
+set_option -disable_io_insertion 1
+set_option -retiming 0
+set_option -pipe 0
+set_option -forcegsr false
+set_option -fix_gated_and_generated_clocks 1
+set_option -rw_check_on_ram 1
+set_option -update_models_cp 0
+set_option -syn_edif_array_rename 1
+set_option -Write_declared_clocks_only 1
+
+# NFilter
+set_option -no_sequential_opt 0
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.edn"
+
+#set log file 
+set_option log_file "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srf" 
+impl -active "syn_results"

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.areasrr b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.areasrr
new file mode 100644 (file)
index 0000000..0e55e08
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.areasrr
@@ -0,0 +1,97 @@
+----------------------------------------------------------------------
+Report for cell serdes_sync_1.v1
+
+Register bits: 220 of 24288 (1%)
+PIC Latch:       0
+I/O cells:       0
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                              CCU2C      113       100.0
+                               DCUA        1       100.0
+                            FD1P3BX       20       100.0
+                            FD1P3DX       92       100.0
+                            FD1S3BX       12       100.0
+                            FD1S3DX       96       100.0
+                                GSR        1       100.0
+                                INV        3       100.0
+                           ORCALUT4      150       100.0
+                              PFUMX        2       100.0
+                                PUR        1       100.0
+                                VHI        6       100.0
+                                VLO        6       100.0
+SUB MODULES 
+          serdes_sync_1rsl_core_Z2_layer1        1       100.0
+          serdes_sync_1sll_core_Z1_layer1        1       100.0
+                            sync_0s        1       100.0
+                          sync_0s_0        1       100.0
+                          sync_0s_6        1       100.0
+                            
+                         TOTAL           508           
+----------------------------------------------------------------------
+Report for cell serdes_sync_1rsl_core_Z2_layer1.netlist
+     Instance path:  rsl_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                              CCU2C       51        45.1
+                            FD1P3BX        4        20.0
+                            FD1P3DX       74        80.4
+                            FD1S3BX       12       100.0
+                            FD1S3DX       37        38.5
+                           ORCALUT4       99        66.0
+                              PFUMX        2       100.0
+                                VHI        1        16.7
+                                VLO        1        16.7
+                            
+                         TOTAL           281           
+----------------------------------------------------------------------
+Report for cell serdes_sync_1sll_core_Z1_layer1.netlist
+     Instance path:  sll_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                              CCU2C       62        54.9
+                            FD1P3BX       16        80.0
+                            FD1P3DX       18        19.6
+                            FD1S3DX       59        61.5
+                                INV        3       100.0
+                           ORCALUT4       51        34.0
+                                VHI        4        66.7
+                                VLO        4        66.7
+SUB MODULES 
+                            sync_0s        1       100.0
+                          sync_0s_0        1       100.0
+                          sync_0s_6        1       100.0
+                            
+                         TOTAL           220           
+----------------------------------------------------------------------
+Report for cell sync_0s_0.netlist
+  Original Cell name sync_0s
+     Instance path:  sll_inst.pdiff_sync_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                            FD1S3DX        2         2.1
+                                VHI        1        16.7
+                                VLO        1        16.7
+                            
+                         TOTAL             4           
+----------------------------------------------------------------------
+Report for cell sync_0s_6.netlist
+  Original Cell name sync_0s
+     Instance path:  sll_inst.rtc_sync_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                            FD1S3DX        2         2.1
+                                VHI        1        16.7
+                                VLO        1        16.7
+                            
+                         TOTAL             4           
+----------------------------------------------------------------------
+Report for cell sync_0s.netlist
+  Original Cell name sync_0s
+     Instance path:  sll_inst.phb_sync_inst
+                                          Cell usage:
+                               cell       count    Res Usage(%)
+                            FD1S3DX        2         2.1
+                                VHI        1        16.7
+                                VLO        1        16.7
+                            
+                         TOTAL             4           

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.fse b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.fse
new file mode 100644 (file)
index 0000000..f4aa273
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.fse
@@ -0,0 +1,10 @@
+
+fsm_encoding {61801018011} sequential
+
+fsm_state_encoding {61801018011} LPLL_LOSS_ST {00}
+
+fsm_state_encoding {61801018011} LPLL_PRELOSS_ST {01}
+
+fsm_state_encoding {61801018011} LPLL_LOCK_ST {10}
+
+fsm_registers {61801018011} {sll_state[1]}  {sll_state[0]} 

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.htm b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.htm
new file mode 100644 (file)
index 0000000..757e0e6
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.htm
@@ -0,0 +1,9 @@
+<html>
+ <head>
+ <title>syntmp/serdes_sync_1_srr.htm log file</title>
+ </head>
+ <frameset cols="20%, 80%">
+ <frame src="syntmp/serdes_sync_1_toc.htm" name="tocFrame" />
+                                <frame src="syntmp/serdes_sync_1_srr.htm" name="srrFrame"/>
+</frameset>
+ </html>

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.prj b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.prj
new file mode 100644 (file)
index 0000000..e8c4120
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.prj
@@ -0,0 +1,47 @@
+#-- Lattice Semiconductor Corporation Ltd.
+#-- Synplify OEM project file /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.prj
+#-- Written on Fri May 10 10:23:30 2019
+
+
+#device options
+set_option -technology ecp5um
+set_option -part LFE5UM-85F
+set_option -speed_grade 8
+
+#use verilog 2001 standard option
+set_option -vlog_std v2001
+
+#map options
+set_option -frequency 100
+set_option -fanout_limit 50
+set_option -disable_io_insertion true
+set_option -retiming false
+set_option -pipe false
+set_option -pipe false
+set_option -force_gsr false
+
+#simulation options
+set_option -write_verilog true
+set_option -write_vhdl true
+
+#timing analysis options
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#-- add_file options
+add_file -vhdl -lib work "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd"
+add_file -verilog -lib work "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v"
+add_file -constraint {"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc"}
+
+#-- top module name
+set_option -top_module serdes_sync_1
+
+#-- set result format/file last
+project -result_file "serdes_sync_1.edn"
+
+#-- error message log file
+project -log_file serdes_sync_1.srf
+
+#-- run Synplify with 'arrange VHDL file'
+project -run

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srd b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srd
new file mode 100644 (file)
index 0000000..6e49b64
Binary files /dev/null and b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srd differ

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srf b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srf
new file mode 100644 (file)
index 0000000..6dd20a1
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srf
@@ -0,0 +1,1147 @@
+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
+#install: /home/soft/lattice/diamond/3.10_x64/synpbase
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Fri May 10 10:23:30 2019
+
+#Implementation: syn_results
+
+Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Top entity is set to serdes_sync_1.
+VHDL syntax check successful!
+File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd changed - recompiling
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Fri May 10 10:23:30 2019
+
+###########################################################]
+Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v" (library work)
+Verilog syntax check successful!
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Fri May 10 10:23:31 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Top entity is set to serdes_sync_1.
+File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd changed - recompiling
+File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling
+VHDL syntax check successful!
+File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd changed - recompiling
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Synthesizing work.serdes_sync_1.v1.
+Post processing for work.serdes_sync_1.v1
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB)
+
+
+Process completed successfully.
+# Fri May 10 10:23:31 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v" (library work)
+Verilog syntax check successful!
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work.
+
+       PDATA_RST_VAL=32'b00000000000000000000000000000000
+   Generated name = sync_0s
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1051:7:1051:27|Synthesizing module serdes_sync_1sll_core in library work.
+
+       PPROTOCOL=48'b010001110011100001000010001100010011000001000010
+       PLOL_SETTING=32'b00000000000000000000000000000001
+       PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100
+       PPCIE_MAX_RATE=24'b001100100010111000110101
+       PDIFF_VAL_LOCK=32'b00000000000000000000000000100111
+       PDIFF_VAL_UNLOCK=32'b00000000000000000000000100000110
+       PPCLK_TC=32'b00000000000000100000000000000000
+       PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000
+       PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000
+       PPCLK_DIV11_TC=32'b00000000000000000000000000000000
+       LPLL_LOSS_ST=2'b00
+       LPLL_PRELOSS_ST=2'b01
+       LPLL_PRELOCK_ST=2'b10
+       LPLL_LOCK_ST=2'b11
+       LRCLK_TC=16'b1111111111111111
+       LRCLK_TC_PUL_WIDTH=16'b0000000000110010
+       LHB_WAIT_CNT=8'b11111111
+       LPCLK_TC_0=32'b00000000000000001000000000000000
+       LPCLK_TC_1=32'b00000000000000010000000000000000
+       LPCLK_TC_2=32'b00000000000000100000000000000000
+       LPCLK_TC_3=32'b00000000000000101000000000000000
+       LPCLK_TC_4=32'b00000000000000010000000000000000
+       LPDIFF_LOCK_00=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_10=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_20=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_30=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_40=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_01=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_11=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_21=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_31=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_41=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_02=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_12=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_22=32'b00000000000000000000000011000100
+       LPDIFF_LOCK_32=32'b00000000000000000000000011110101
+       LPDIFF_LOCK_42=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_03=32'b00000000000000000000000010000011
+       LPDIFF_LOCK_13=32'b00000000000000000000000100000110
+       LPDIFF_LOCK_23=32'b00000000000000000000001000001100
+       LPDIFF_LOCK_33=32'b00000000000000000000001010001111
+       LPDIFF_LOCK_43=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011
+       LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110
+       LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010
+       LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001
+       LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111
+       LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000
+       LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000
+       LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000
+       LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100
+       LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001
+       LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010
+       LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111
+       LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001
+   Generated name = serdes_sync_1sll_core_Z1_layer1
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1287:54:1287:59|Removing redundant assignment.
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1293:52:1293:55|Removing redundant assignment.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":92:7:92:27|Synthesizing module serdes_sync_1rsl_core in library work.
+
+       pnum_channels=32'b00000000000000000000000000000001
+       pprotocol=48'b010001110011100001000010001100010011000001000010
+       pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
+       pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_tx_rdy=32'b00000000000000000000101110111000
+       pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_rx_rdy=32'b00000000000000000000101110111000
+       wa_num_cycles=32'b00000000000000000000010000000000
+       dac_num_cycles=32'b00000000000000000000000000000011
+       lreset_pwidth=32'b00000000000000000000000000000011
+       lwait_b4_trst=32'b00000000000010111110101111000010
+       lwait_b4_trst_s=32'b00000000000000000000001100001101
+       lplol_cnt_width=32'b00000000000000000000000000010100
+       lwait_after_plol0=32'b00000000000000000000000000000100
+       lwait_b4_rrst=32'b00000000000000101100000000000000
+       lrrst_wait_width=32'b00000000000000000000000000010100
+       lwait_after_rrst=32'b00000000000011000011010100000000
+       lwait_b4_rrst_s=32'b00000000000000000000000111001100
+       lrlol_cnt_width=32'b00000000000000000000000000010011
+       lwait_after_lols=32'b00000000000000001100010000000000
+       lwait_after_lols_s=32'b00000000000000000000000010010110
+       llols_cnt_width=32'b00000000000000000000000000010010
+       lrdb_max=32'b00000000000000000000000000001111
+       ltxr_wait_width=32'b00000000000000000000000000001100
+       lrxr_wait_width=32'b00000000000000000000000000001100
+   Generated name = serdes_sync_1rsl_core_Z2_layer1
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning register bits 8 to 7 of genblk5.rdiff_comp_unlock[8:6]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[6]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers.
+@N: CL201 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state.
+Extracted state machine for register sll_state
+State machine has 3 reachable states with original encodings of:
+   00
+   01
+   11
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB)
+
+
+Process completed successfully.
+# Fri May 10 10:23:32 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer0.srs changed - recompiling
+File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.srs changed - recompiling
+
+=======================================================================================
+For a summary of linker messages for components that did not bind, please see log file:
+@L: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.linkerlog
+=======================================================================================
+
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 10:23:32 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 10:23:32 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 10:23:33 2019
+
+###########################################################]
+# Fri May 10 10:23:33 2019
+
+Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc
+@L: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_scck.rpt 
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_scck.rpt" file 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 115MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 117MB)
+
+@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances.
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist serdes_sync_1
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
+
+
+
+Clock Summary
+******************
+
+          Start                                    Requested     Requested     Clock        Clock                   Clock
+Level     Clock                                    Frequency     Period        Type         Group                   Load 
+-------------------------------------------------------------------------------------------------------------------------
+0 -       System                                   100.0 MHz     10.000        system       system_clkgroup         0    
+                                                                                                                         
+0 -       serdes_sync_1|pll_refclki                100.0 MHz     10.000        inferred     Inferred_clkgroup_0     92   
+                                                                                                                         
+0 -       serdes_sync_1|rxrefclk                   100.0 MHz     10.000        inferred     Inferred_clkgroup_1     77   
+                                                                                                                         
+0 -       serdes_sync_1|tx_pclk_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_2     53   
+=========================================================================================================================
+
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Found inferred clock serdes_sync_1|pll_refclki which controls 92 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Found inferred clock serdes_sync_1|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Found inferred clock serdes_sync_1|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 145MB)
+
+Encoding state machine sll_state[2:0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   11 -> 10
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 59MB peak: 145MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Fri May 10 10:23:34 2019
+
+###########################################################]
+# Fri May 10 10:23:34 2019
+
+Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[2:0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   11 -> 10
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1350:0:1350:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1304:0:1304:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance rcount[15:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1759:0:1759:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance pcount[21:0] 
+@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1801:0:1801:5|Removing sequential instance sll_state[0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":412:3:412:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":909:3:909:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":527:3:527:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":778:3:778:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":680:3:680:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] 
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+   1           0h:00m:01s                   5.35ns              151 /       220
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+3 non-gated/non-generated clock tree(s) driving 220 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+============================================= Non-Gated/Non-Generated Clocks =============================================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                                   
+--------------------------------------------------------------------------------------------------------------------------
+@K:CKID0001       pll_refclki         port                   90         rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]
+@K:CKID0002       rxrefclk            port                   77         rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]
+@K:CKID0003       DCU0_inst           DCUA                   53         sll_inst.pcount_diff[21]                          
+==========================================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 148MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.edn
+M-2017.03L-SP1-1
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 152MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 152MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB)
+
+@W: MT246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":160:4:160:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+@W: MT420 |Found inferred clock serdes_sync_1|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"
+@W: MT420 |Found inferred clock serdes_sync_1|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"
+@W: MT420 |Found inferred clock serdes_sync_1|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk"
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Fri May 10 10:23:38 2019
+#
+
+
+Top view:               serdes_sync_1
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 4.079
+
+@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
+                                         Requested     Estimated     Requested     Estimated               Clock        Clock              
+Starting Clock                           Frequency     Frequency     Period        Period        Slack     Type         Group              
+-------------------------------------------------------------------------------------------------------------------------------------------
+serdes_sync_1|pll_refclki                100.0 MHz     168.9 MHz     10.000        5.921         4.079     inferred     Inferred_clkgroup_0
+serdes_sync_1|rxrefclk                   100.0 MHz     170.5 MHz     10.000        5.864         4.136     inferred     Inferred_clkgroup_1
+serdes_sync_1|tx_pclk_inferred_clock     100.0 MHz     237.5 MHz     10.000        4.211         5.789     inferred     Inferred_clkgroup_2
+System                                   100.0 MHz     840.7 MHz     10.000        1.190         8.810     system       system_clkgroup    
+===========================================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                                                                      |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Starting                              Ending                                |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+System                                System                                |  10.000      10.000  |  No paths    -      |  No paths    -      |  No paths    -    
+System                                serdes_sync_1|rxrefclk                |  10.000      8.811   |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|pll_refclki             System                                |  10.000      8.307   |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|pll_refclki             serdes_sync_1|pll_refclki             |  10.000      4.079   |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|pll_refclki             serdes_sync_1|tx_pclk_inferred_clock  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|rxrefclk                System                                |  10.000      8.193   |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|rxrefclk                serdes_sync_1|rxrefclk                |  10.000      4.136   |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|tx_pclk_inferred_clock  serdes_sync_1|pll_refclki             |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|tx_pclk_inferred_clock  serdes_sync_1|tx_pclk_inferred_clock  |  10.000      5.789   |  No paths    -      |  No paths    -      |  No paths    -    
+===================================================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: serdes_sync_1|pll_refclki
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                   Starting                                                           Arrival          
+Instance                           Reference                     Type        Pin     Net              Time        Slack
+                                   Clock                                                                               
+-----------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[1]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[1]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[6]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[6]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[7]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[7]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[12]     serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[12]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[2]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[2]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[3]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[3]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[4]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[4]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[5]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[5]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[8]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[8]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[9]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[9]      0.907       4.684
+=======================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                   Starting                                                             Required          
+Instance                           Reference                     Type        Pin     Net                Time         Slack
+                                   Clock                                                                                  
+--------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[19]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[19]     9.946        4.079
+rsl_inst.genblk1\.plol_cnt[17]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[17]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[18]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[18]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[15]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[15]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[16]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[16]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[13]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[13]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[14]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[14]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[11]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[11]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[12]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[12]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[9]      serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[9]      9.946        4.383
+==========================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.867
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     4.079
+
+    Number of logic level(s):                15
+    Starting point:                          rsl_inst.genblk1\.plol_cnt[1] / Q
+    Ending point:                            rsl_inst.genblk1\.plol_cnt[19] / D
+    The start point is clocked by            serdes_sync_1|pll_refclki [rising] on pin CK
+    The end   point is clocked by            serdes_sync_1|pll_refclki [rising] on pin CK
+
+Instance / Net                                        Pin      Pin               Arrival     No. of    
+Name                                     Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[1]            FD1S3DX      Q        Out     0.907     0.907       -         
+plol_cnt[1]                              Net          -        -       -         -           2         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     Z        Out     0.606     1.513       -         
+un1_plol_cnt_tc_10                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     Z        Out     0.606     2.119       -         
+un1_plol_cnt_tc_14                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     Z        Out     0.762     2.881       -         
+un1_plol_cnt_tc                          Net          -        -       -         -           5         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     B        In      0.000     2.881       -         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     Z        Out     0.840     3.721       -         
+plol_cnt                                 Net          -        -       -         -           21        
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.721       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.621       -         
+plol_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.621       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.682       -         
+plol_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.682       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.743       -         
+plol_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.743       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.804       -         
+plol_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.804       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.865       -         
+plol_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.865       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.926       -         
+plol_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.926       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.987       -         
+plol_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.987       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.048       -         
+plol_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.048       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.109       -         
+plol_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.109       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        COUT     Out     0.061     5.170       -         
+plol_cnt_cry[18]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        CIN      In      0.000     5.170       -         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        S0       Out     0.698     5.867       -         
+plol_cnt_s[19]                           Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt[19]           FD1S3DX      D        In      0.000     5.867       -         
+=======================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: serdes_sync_1|rxrefclk
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                     Starting                                                          Arrival          
+Instance                             Reference                  Type        Pin     Net                Time        Slack
+                                     Clock                                                                              
+------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[14]      serdes_sync_1|rxrefclk     FD1P3DX     Q       rlol1_cnt[14]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[15]      serdes_sync_1|rxrefclk     FD1P3DX     Q       rlol1_cnt[15]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[16]      serdes_sync_1|rxrefclk     FD1P3DX     Q       rlol1_cnt[16]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[17]      serdes_sync_1|rxrefclk     FD1P3DX     Q       rlol1_cnt[17]      0.907       4.136
+rsl_inst.genblk2\.rlols0_cnt[9]      serdes_sync_1|rxrefclk     FD1P3DX     Q       rlols0_cnt[9]      0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[11]     serdes_sync_1|rxrefclk     FD1P3DX     Q       rlols0_cnt[11]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[12]     serdes_sync_1|rxrefclk     FD1P3DX     Q       rlols0_cnt[12]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[13]     serdes_sync_1|rxrefclk     FD1P3DX     Q       rlols0_cnt[13]     0.907       4.170
+rsl_inst.genblk2\.rlol1_cnt[0]       serdes_sync_1|rxrefclk     FD1P3DX     Q       rlol1_cnt[0]       0.907       4.742
+rsl_inst.genblk2\.rlol1_cnt[1]       serdes_sync_1|rxrefclk     FD1P3DX     Q       rlol1_cnt[1]       0.907       4.742
+========================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                     Starting                                                            Required          
+Instance                             Reference                  Type        Pin     Net                  Time         Slack
+                                     Clock                                                                                 
+---------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[17]      serdes_sync_1|rxrefclk     FD1P3DX     D       rlol1_cnt_s[17]      9.946        4.136
+rsl_inst.genblk2\.rlol1_cnt[18]      serdes_sync_1|rxrefclk     FD1P3DX     D       rlol1_cnt_s[18]      9.946        4.136
+rsl_inst.genblk2\.rlols0_cnt[17]     serdes_sync_1|rxrefclk     FD1P3DX     D       rlols0_cnt_s[17]     9.946        4.170
+rsl_inst.genblk2\.rlol1_cnt[15]      serdes_sync_1|rxrefclk     FD1P3DX     D       rlol1_cnt_s[15]      9.946        4.197
+rsl_inst.genblk2\.rlol1_cnt[16]      serdes_sync_1|rxrefclk     FD1P3DX     D       rlol1_cnt_s[16]      9.946        4.197
+rsl_inst.genblk2\.rlols0_cnt[15]     serdes_sync_1|rxrefclk     FD1P3DX     D       rlols0_cnt_s[15]     9.946        4.231
+rsl_inst.genblk2\.rlols0_cnt[16]     serdes_sync_1|rxrefclk     FD1P3DX     D       rlols0_cnt_s[16]     9.946        4.231
+rsl_inst.genblk2\.rlol1_cnt[13]      serdes_sync_1|rxrefclk     FD1P3DX     D       rlol1_cnt_s[13]      9.946        4.258
+rsl_inst.genblk2\.rlol1_cnt[14]      serdes_sync_1|rxrefclk     FD1P3DX     D       rlol1_cnt_s[14]      9.946        4.258
+rsl_inst.genblk2\.rlols0_cnt[13]     serdes_sync_1|rxrefclk     FD1P3DX     D       rlols0_cnt_s[13]     9.946        4.292
+===========================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.809
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.136
+
+    Number of logic level(s):                14
+    Starting point:                          rsl_inst.genblk2\.rlol1_cnt[14] / Q
+    Ending point:                            rsl_inst.genblk2\.rlol1_cnt[18] / D
+    The start point is clocked by            serdes_sync_1|rxrefclk [rising] on pin CK
+    The end   point is clocked by            serdes_sync_1|rxrefclk [rising] on pin CK
+
+Instance / Net                                         Pin      Pin               Arrival     No. of    
+Name                                      Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[14]           FD1P3DX      Q        Out     0.907     0.907       -         
+rlol1_cnt[14]                             Net          -        -       -         -           2         
+rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     Z        Out     0.606     1.513       -         
+rlol1_cnt_tc_1_10                         Net          -        -       -         -           1         
+rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     Z        Out     0.606     2.119       -         
+rlol1_cnt_tc_1_14                         Net          -        -       -         -           1         
+rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     Z        Out     0.768     2.887       -         
+rlol1_cnt_tc_1                            Net          -        -       -         -           6         
+rsl_inst.genblk2\.rlos_db_p1_RNIS0OP      ORCALUT4     A        In      0.000     2.887       -         
+rsl_inst.genblk2\.rlos_db_p1_RNIS0OP      ORCALUT4     Z        Out     0.837     3.724       -         
+rlol1_cnt                                 Net          -        -       -         -           20        
+rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.724       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.624       -         
+rlol1_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.624       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.685       -         
+rlol1_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.685       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.746       -         
+rlol1_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.746       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.807       -         
+rlol1_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.807       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.868       -         
+rlol1_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.868       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.929       -         
+rlol1_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.929       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.990       -         
+rlol1_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.990       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.051       -         
+rlol1_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.051       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.112       -         
+rlol1_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.112       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        S1       Out     0.698     5.809       -         
+rlol1_cnt_s[18]                           Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt[18]           FD1P3DX      D        In      0.000     5.809       -         
+========================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: serdes_sync_1|tx_pclk_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                            Starting                                                                      Arrival          
+Instance                    Reference                                Type        Pin     Net              Time        Slack
+                            Clock                                                                                          
+---------------------------------------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1       serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p1     1.098       5.789
+sll_inst.ppul_sync_p2       serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p2     1.098       5.789
+sll_inst.pcount_diff[0]     serdes_sync_1|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_0      0.985       6.147
+sll_inst.pcount[0]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[0]        0.955       6.178
+sll_inst.pcount_diff[1]     serdes_sync_1|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_1      0.955       6.239
+sll_inst.pcount_diff[2]     serdes_sync_1|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_2      0.955       6.239
+sll_inst.pcount[1]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[1]        0.907       6.287
+sll_inst.pcount[2]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[2]        0.907       6.287
+sll_inst.pcount_diff[3]     serdes_sync_1|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_3      0.955       6.300
+sll_inst.pcount_diff[4]     serdes_sync_1|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_4      0.955       6.300
+===========================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                             Starting                                                                                     Required          
+Instance                     Reference                                Type        Pin     Net                             Time         Slack
+                             Clock                                                                                                          
+--------------------------------------------------------------------------------------------------------------------------------------------
+sll_inst.pcount[21]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[21]                    9.946        5.789
+sll_inst.pcount[19]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[19]                    9.946        5.850
+sll_inst.pcount[20]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[20]                    9.946        5.850
+sll_inst.pcount[17]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[17]                    9.946        5.911
+sll_inst.pcount[18]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[18]                    9.946        5.911
+sll_inst.pcount[15]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[15]                    9.946        5.972
+sll_inst.pcount[16]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[16]                    9.946        5.972
+sll_inst.pcount[13]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[13]                    9.946        6.033
+sll_inst.pcount[14]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[14]                    9.946        6.033
+sll_inst.pcount_diff[21]     serdes_sync_1|tx_pclk_inferred_clock     FD1P3DX     D       un1_pcount_diff_1_s_21_0_S0     9.946        6.034
+============================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      4.157
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 5.789
+
+    Number of logic level(s):                13
+    Starting point:                          sll_inst.ppul_sync_p1 / Q
+    Ending point:                            sll_inst.pcount[21] / D
+    The start point is clocked by            serdes_sync_1|tx_pclk_inferred_clock [rising] on pin CK
+    The end   point is clocked by            serdes_sync_1|tx_pclk_inferred_clock [rising] on pin CK
+
+Instance / Net                             Pin      Pin               Arrival     No. of    
+Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1         FD1S3DX      Q        Out     1.098     1.098       -         
+ppul_sync_p1                  Net          -        -       -         -           25        
+sll_inst.pcount10_0_o3        ORCALUT4     A        In      0.000     1.098       -         
+sll_inst.pcount10_0_o3        ORCALUT4     Z        Out     0.851     1.950       -         
+N_8                           Net          -        -       -         -           25        
+sll_inst.pcount_cry_0[0]      CCU2C        A1       In      0.000     1.950       -         
+sll_inst.pcount_cry_0[0]      CCU2C        COUT     Out     0.900     2.850       -         
+pcount_cry[0]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[1]      CCU2C        CIN      In      0.000     2.850       -         
+sll_inst.pcount_cry_0[1]      CCU2C        COUT     Out     0.061     2.911       -         
+pcount_cry[2]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[3]      CCU2C        CIN      In      0.000     2.911       -         
+sll_inst.pcount_cry_0[3]      CCU2C        COUT     Out     0.061     2.972       -         
+pcount_cry[4]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[5]      CCU2C        CIN      In      0.000     2.972       -         
+sll_inst.pcount_cry_0[5]      CCU2C        COUT     Out     0.061     3.033       -         
+pcount_cry[6]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[7]      CCU2C        CIN      In      0.000     3.033       -         
+sll_inst.pcount_cry_0[7]      CCU2C        COUT     Out     0.061     3.094       -         
+pcount_cry[8]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[9]      CCU2C        CIN      In      0.000     3.094       -         
+sll_inst.pcount_cry_0[9]      CCU2C        COUT     Out     0.061     3.155       -         
+pcount_cry[10]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[11]     CCU2C        CIN      In      0.000     3.155       -         
+sll_inst.pcount_cry_0[11]     CCU2C        COUT     Out     0.061     3.216       -         
+pcount_cry[12]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[13]     CCU2C        CIN      In      0.000     3.216       -         
+sll_inst.pcount_cry_0[13]     CCU2C        COUT     Out     0.061     3.277       -         
+pcount_cry[14]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[15]     CCU2C        CIN      In      0.000     3.277       -         
+sll_inst.pcount_cry_0[15]     CCU2C        COUT     Out     0.061     3.338       -         
+pcount_cry[16]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[17]     CCU2C        CIN      In      0.000     3.338       -         
+sll_inst.pcount_cry_0[17]     CCU2C        COUT     Out     0.061     3.399       -         
+pcount_cry[18]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[19]     CCU2C        CIN      In      0.000     3.399       -         
+sll_inst.pcount_cry_0[19]     CCU2C        COUT     Out     0.061     3.460       -         
+pcount_cry[20]                Net          -        -       -         -           1         
+sll_inst.pcount_s_0[21]       CCU2C        CIN      In      0.000     3.460       -         
+sll_inst.pcount_s_0[21]       CCU2C        S0       Out     0.698     4.157       -         
+pcount_s[21]                  Net          -        -       -         -           1         
+sll_inst.pcount[21]           FD1S3DX      D        In      0.000     4.157       -         
+============================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                                   Arrival           
+Instance      Reference     Type     Pin                Net              Time        Slack 
+              Clock                                                                        
+-------------------------------------------------------------------------------------------
+DCU0_inst     System        DCUA     CH0_FFS_RLOL       rx_cdr_lol_s     0.000       8.810 
+DCU0_inst     System        DCUA     CH0_FFS_RLOS       rx_los_low_s     0.000       8.810 
+DCU0_inst     System        DCUA     CH0_FF_RX_PCLK     rx_pclk          0.000       10.000
+===========================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                       Starting                                                                       Required           
+Instance                                               Reference     Type        Pin                Net                               Time         Slack 
+                                                       Clock                                                                                             
+---------------------------------------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     SP                 un2_rdo_serdes_rst_dual_c_2_i     9.806        8.810 
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     D                  un2_rdo_serdes_rst_dual_c_1       9.946        9.556 
+rsl_inst.genblk2\.rlol_p1                              System        FD1S3DX     D                  rx_cdr_lol_s                      9.946        9.946 
+rsl_inst.genblk2\.rlos_p1                              System        FD1S3DX     D                  rx_los_low_s                      9.946        9.946 
+DCU0_inst                                              System        DCUA        CH0_FF_RXI_CLK     rx_pclk                           10.000       10.000
+=========================================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.194
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.806
+
+    - Propagation time:                      0.996
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 8.810
+
+    Number of logic level(s):                2
+    Starting point:                          DCU0_inst / CH0_FFS_RLOL
+    Ending point:                            rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            serdes_sync_1|rxrefclk [rising] on pin CK
+
+Instance / Net                                                          Pin              Pin               Arrival     No. of    
+Name                                                       Type         Name             Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------------------------------------------------
+DCU0_inst                                                  DCUA         CH0_FFS_RLOL     Out     0.000     0.000       -         
+rx_cdr_lol_s                                               Net          -                -       -         -           4         
+rsl_inst.un2_rdo_serdes_rst_dual_c_2_0                     ORCALUT4     B                In      0.000     0.000       -         
+rsl_inst.un2_rdo_serdes_rst_dual_c_2_0                     ORCALUT4     Z                Out     0.606     0.606       -         
+un2_rdo_serdes_rst_dual_c_2_0                              Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO[0]     ORCALUT4     B                In      0.000     0.606       -         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO[0]     ORCALUT4     Z                Out     0.390     0.996       -         
+un2_rdo_serdes_rst_dual_c_2_i                              Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]         FD1P3DX      SP               In      0.000     0.996       -         
+=================================================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 220 of 24288 (1%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+CCU2C:          113
+DCUA:           1
+FD1P3BX:        20
+FD1P3DX:        92
+FD1S3BX:        12
+FD1S3DX:        96
+GSR:            1
+INV:            3
+ORCALUT4:       150
+PFUMX:          2
+PUR:            1
+VHI:            6
+VLO:            6
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 152MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Fri May 10 10:23:38 2019
+
+###########################################################]

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srm b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srm
new file mode 100644 (file)
index 0000000..75dd84e
Binary files /dev/null and b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srm differ

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srr b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srr
new file mode 100644 (file)
index 0000000..6dd20a1
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srr
@@ -0,0 +1,1147 @@
+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
+#install: /home/soft/lattice/diamond/3.10_x64/synpbase
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Fri May 10 10:23:30 2019
+
+#Implementation: syn_results
+
+Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Top entity is set to serdes_sync_1.
+VHDL syntax check successful!
+File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd changed - recompiling
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Fri May 10 10:23:30 2019
+
+###########################################################]
+Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v" (library work)
+Verilog syntax check successful!
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Fri May 10 10:23:31 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Top entity is set to serdes_sync_1.
+File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd changed - recompiling
+File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling
+VHDL syntax check successful!
+File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd changed - recompiling
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Synthesizing work.serdes_sync_1.v1.
+Post processing for work.serdes_sync_1.v1
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB)
+
+
+Process completed successfully.
+# Fri May 10 10:23:31 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v" (library work)
+Verilog syntax check successful!
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work.
+
+       PDATA_RST_VAL=32'b00000000000000000000000000000000
+   Generated name = sync_0s
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1051:7:1051:27|Synthesizing module serdes_sync_1sll_core in library work.
+
+       PPROTOCOL=48'b010001110011100001000010001100010011000001000010
+       PLOL_SETTING=32'b00000000000000000000000000000001
+       PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100
+       PPCIE_MAX_RATE=24'b001100100010111000110101
+       PDIFF_VAL_LOCK=32'b00000000000000000000000000100111
+       PDIFF_VAL_UNLOCK=32'b00000000000000000000000100000110
+       PPCLK_TC=32'b00000000000000100000000000000000
+       PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000
+       PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000
+       PPCLK_DIV11_TC=32'b00000000000000000000000000000000
+       LPLL_LOSS_ST=2'b00
+       LPLL_PRELOSS_ST=2'b01
+       LPLL_PRELOCK_ST=2'b10
+       LPLL_LOCK_ST=2'b11
+       LRCLK_TC=16'b1111111111111111
+       LRCLK_TC_PUL_WIDTH=16'b0000000000110010
+       LHB_WAIT_CNT=8'b11111111
+       LPCLK_TC_0=32'b00000000000000001000000000000000
+       LPCLK_TC_1=32'b00000000000000010000000000000000
+       LPCLK_TC_2=32'b00000000000000100000000000000000
+       LPCLK_TC_3=32'b00000000000000101000000000000000
+       LPCLK_TC_4=32'b00000000000000010000000000000000
+       LPDIFF_LOCK_00=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_10=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_20=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_30=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_40=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_01=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_11=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_21=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_31=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_41=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_02=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_12=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_22=32'b00000000000000000000000011000100
+       LPDIFF_LOCK_32=32'b00000000000000000000000011110101
+       LPDIFF_LOCK_42=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_03=32'b00000000000000000000000010000011
+       LPDIFF_LOCK_13=32'b00000000000000000000000100000110
+       LPDIFF_LOCK_23=32'b00000000000000000000001000001100
+       LPDIFF_LOCK_33=32'b00000000000000000000001010001111
+       LPDIFF_LOCK_43=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011
+       LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110
+       LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010
+       LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001
+       LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111
+       LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000
+       LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000
+       LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000
+       LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100
+       LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001
+       LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010
+       LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111
+       LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001
+   Generated name = serdes_sync_1sll_core_Z1_layer1
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1287:54:1287:59|Removing redundant assignment.
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1293:52:1293:55|Removing redundant assignment.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":92:7:92:27|Synthesizing module serdes_sync_1rsl_core in library work.
+
+       pnum_channels=32'b00000000000000000000000000000001
+       pprotocol=48'b010001110011100001000010001100010011000001000010
+       pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
+       pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_tx_rdy=32'b00000000000000000000101110111000
+       pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_rx_rdy=32'b00000000000000000000101110111000
+       wa_num_cycles=32'b00000000000000000000010000000000
+       dac_num_cycles=32'b00000000000000000000000000000011
+       lreset_pwidth=32'b00000000000000000000000000000011
+       lwait_b4_trst=32'b00000000000010111110101111000010
+       lwait_b4_trst_s=32'b00000000000000000000001100001101
+       lplol_cnt_width=32'b00000000000000000000000000010100
+       lwait_after_plol0=32'b00000000000000000000000000000100
+       lwait_b4_rrst=32'b00000000000000101100000000000000
+       lrrst_wait_width=32'b00000000000000000000000000010100
+       lwait_after_rrst=32'b00000000000011000011010100000000
+       lwait_b4_rrst_s=32'b00000000000000000000000111001100
+       lrlol_cnt_width=32'b00000000000000000000000000010011
+       lwait_after_lols=32'b00000000000000001100010000000000
+       lwait_after_lols_s=32'b00000000000000000000000010010110
+       llols_cnt_width=32'b00000000000000000000000000010010
+       lrdb_max=32'b00000000000000000000000000001111
+       ltxr_wait_width=32'b00000000000000000000000000001100
+       lrxr_wait_width=32'b00000000000000000000000000001100
+   Generated name = serdes_sync_1rsl_core_Z2_layer1
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning register bits 8 to 7 of genblk5.rdiff_comp_unlock[8:6]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[6]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers.
+@N: CL201 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state.
+Extracted state machine for register sll_state
+State machine has 3 reachable states with original encodings of:
+   00
+   01
+   11
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB)
+
+
+Process completed successfully.
+# Fri May 10 10:23:32 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer0.srs changed - recompiling
+File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.srs changed - recompiling
+
+=======================================================================================
+For a summary of linker messages for components that did not bind, please see log file:
+@L: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.linkerlog
+=======================================================================================
+
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 10:23:32 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 10:23:32 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 10:23:33 2019
+
+###########################################################]
+# Fri May 10 10:23:33 2019
+
+Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc
+@L: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_scck.rpt 
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_scck.rpt" file 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 115MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 117MB)
+
+@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances.
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist serdes_sync_1
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
+
+
+
+Clock Summary
+******************
+
+          Start                                    Requested     Requested     Clock        Clock                   Clock
+Level     Clock                                    Frequency     Period        Type         Group                   Load 
+-------------------------------------------------------------------------------------------------------------------------
+0 -       System                                   100.0 MHz     10.000        system       system_clkgroup         0    
+                                                                                                                         
+0 -       serdes_sync_1|pll_refclki                100.0 MHz     10.000        inferred     Inferred_clkgroup_0     92   
+                                                                                                                         
+0 -       serdes_sync_1|rxrefclk                   100.0 MHz     10.000        inferred     Inferred_clkgroup_1     77   
+                                                                                                                         
+0 -       serdes_sync_1|tx_pclk_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_2     53   
+=========================================================================================================================
+
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Found inferred clock serdes_sync_1|pll_refclki which controls 92 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Found inferred clock serdes_sync_1|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Found inferred clock serdes_sync_1|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 145MB)
+
+Encoding state machine sll_state[2:0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   11 -> 10
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 59MB peak: 145MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Fri May 10 10:23:34 2019
+
+###########################################################]
+# Fri May 10 10:23:34 2019
+
+Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[2:0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   11 -> 10
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1350:0:1350:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1304:0:1304:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance rcount[15:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1759:0:1759:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance pcount[21:0] 
+@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1801:0:1801:5|Removing sequential instance sll_state[0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":412:3:412:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":909:3:909:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":527:3:527:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":778:3:778:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":680:3:680:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] 
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+   1           0h:00m:01s                   5.35ns              151 /       220
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+3 non-gated/non-generated clock tree(s) driving 220 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+============================================= Non-Gated/Non-Generated Clocks =============================================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                                   
+--------------------------------------------------------------------------------------------------------------------------
+@K:CKID0001       pll_refclki         port                   90         rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]
+@K:CKID0002       rxrefclk            port                   77         rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]
+@K:CKID0003       DCU0_inst           DCUA                   53         sll_inst.pcount_diff[21]                          
+==========================================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 148MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.edn
+M-2017.03L-SP1-1
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 152MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 152MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB)
+
+@W: MT246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":160:4:160:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+@W: MT420 |Found inferred clock serdes_sync_1|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"
+@W: MT420 |Found inferred clock serdes_sync_1|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"
+@W: MT420 |Found inferred clock serdes_sync_1|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk"
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Fri May 10 10:23:38 2019
+#
+
+
+Top view:               serdes_sync_1
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 4.079
+
+@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
+                                         Requested     Estimated     Requested     Estimated               Clock        Clock              
+Starting Clock                           Frequency     Frequency     Period        Period        Slack     Type         Group              
+-------------------------------------------------------------------------------------------------------------------------------------------
+serdes_sync_1|pll_refclki                100.0 MHz     168.9 MHz     10.000        5.921         4.079     inferred     Inferred_clkgroup_0
+serdes_sync_1|rxrefclk                   100.0 MHz     170.5 MHz     10.000        5.864         4.136     inferred     Inferred_clkgroup_1
+serdes_sync_1|tx_pclk_inferred_clock     100.0 MHz     237.5 MHz     10.000        4.211         5.789     inferred     Inferred_clkgroup_2
+System                                   100.0 MHz     840.7 MHz     10.000        1.190         8.810     system       system_clkgroup    
+===========================================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                                                                      |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Starting                              Ending                                |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+System                                System                                |  10.000      10.000  |  No paths    -      |  No paths    -      |  No paths    -    
+System                                serdes_sync_1|rxrefclk                |  10.000      8.811   |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|pll_refclki             System                                |  10.000      8.307   |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|pll_refclki             serdes_sync_1|pll_refclki             |  10.000      4.079   |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|pll_refclki             serdes_sync_1|tx_pclk_inferred_clock  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|rxrefclk                System                                |  10.000      8.193   |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|rxrefclk                serdes_sync_1|rxrefclk                |  10.000      4.136   |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|tx_pclk_inferred_clock  serdes_sync_1|pll_refclki             |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|tx_pclk_inferred_clock  serdes_sync_1|tx_pclk_inferred_clock  |  10.000      5.789   |  No paths    -      |  No paths    -      |  No paths    -    
+===================================================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: serdes_sync_1|pll_refclki
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                   Starting                                                           Arrival          
+Instance                           Reference                     Type        Pin     Net              Time        Slack
+                                   Clock                                                                               
+-----------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[1]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[1]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[6]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[6]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[7]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[7]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[12]     serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[12]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[2]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[2]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[3]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[3]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[4]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[4]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[5]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[5]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[8]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[8]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[9]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[9]      0.907       4.684
+=======================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                   Starting                                                             Required          
+Instance                           Reference                     Type        Pin     Net                Time         Slack
+                                   Clock                                                                                  
+--------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[19]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[19]     9.946        4.079
+rsl_inst.genblk1\.plol_cnt[17]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[17]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[18]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[18]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[15]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[15]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[16]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[16]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[13]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[13]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[14]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[14]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[11]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[11]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[12]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[12]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[9]      serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[9]      9.946        4.383
+==========================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.867
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     4.079
+
+    Number of logic level(s):                15
+    Starting point:                          rsl_inst.genblk1\.plol_cnt[1] / Q
+    Ending point:                            rsl_inst.genblk1\.plol_cnt[19] / D
+    The start point is clocked by            serdes_sync_1|pll_refclki [rising] on pin CK
+    The end   point is clocked by            serdes_sync_1|pll_refclki [rising] on pin CK
+
+Instance / Net                                        Pin      Pin               Arrival     No. of    
+Name                                     Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[1]            FD1S3DX      Q        Out     0.907     0.907       -         
+plol_cnt[1]                              Net          -        -       -         -           2         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     Z        Out     0.606     1.513       -         
+un1_plol_cnt_tc_10                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     Z        Out     0.606     2.119       -         
+un1_plol_cnt_tc_14                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     Z        Out     0.762     2.881       -         
+un1_plol_cnt_tc                          Net          -        -       -         -           5         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     B        In      0.000     2.881       -         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     Z        Out     0.840     3.721       -         
+plol_cnt                                 Net          -        -       -         -           21        
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.721       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.621       -         
+plol_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.621       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.682       -         
+plol_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.682       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.743       -         
+plol_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.743       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.804       -         
+plol_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.804       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.865       -         
+plol_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.865       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.926       -         
+plol_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.926       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.987       -         
+plol_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.987       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.048       -         
+plol_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.048       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.109       -         
+plol_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.109       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        COUT     Out     0.061     5.170       -         
+plol_cnt_cry[18]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        CIN      In      0.000     5.170       -         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        S0       Out     0.698     5.867       -         
+plol_cnt_s[19]                           Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt[19]           FD1S3DX      D        In      0.000     5.867       -         
+=======================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: serdes_sync_1|rxrefclk
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                     Starting                                                          Arrival          
+Instance                             Reference                  Type        Pin     Net                Time        Slack
+                                     Clock                                                                              
+------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[14]      serdes_sync_1|rxrefclk     FD1P3DX     Q       rlol1_cnt[14]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[15]      serdes_sync_1|rxrefclk     FD1P3DX     Q       rlol1_cnt[15]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[16]      serdes_sync_1|rxrefclk     FD1P3DX     Q       rlol1_cnt[16]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[17]      serdes_sync_1|rxrefclk     FD1P3DX     Q       rlol1_cnt[17]      0.907       4.136
+rsl_inst.genblk2\.rlols0_cnt[9]      serdes_sync_1|rxrefclk     FD1P3DX     Q       rlols0_cnt[9]      0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[11]     serdes_sync_1|rxrefclk     FD1P3DX     Q       rlols0_cnt[11]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[12]     serdes_sync_1|rxrefclk     FD1P3DX     Q       rlols0_cnt[12]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[13]     serdes_sync_1|rxrefclk     FD1P3DX     Q       rlols0_cnt[13]     0.907       4.170
+rsl_inst.genblk2\.rlol1_cnt[0]       serdes_sync_1|rxrefclk     FD1P3DX     Q       rlol1_cnt[0]       0.907       4.742
+rsl_inst.genblk2\.rlol1_cnt[1]       serdes_sync_1|rxrefclk     FD1P3DX     Q       rlol1_cnt[1]       0.907       4.742
+========================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                     Starting                                                            Required          
+Instance                             Reference                  Type        Pin     Net                  Time         Slack
+                                     Clock                                                                                 
+---------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[17]      serdes_sync_1|rxrefclk     FD1P3DX     D       rlol1_cnt_s[17]      9.946        4.136
+rsl_inst.genblk2\.rlol1_cnt[18]      serdes_sync_1|rxrefclk     FD1P3DX     D       rlol1_cnt_s[18]      9.946        4.136
+rsl_inst.genblk2\.rlols0_cnt[17]     serdes_sync_1|rxrefclk     FD1P3DX     D       rlols0_cnt_s[17]     9.946        4.170
+rsl_inst.genblk2\.rlol1_cnt[15]      serdes_sync_1|rxrefclk     FD1P3DX     D       rlol1_cnt_s[15]      9.946        4.197
+rsl_inst.genblk2\.rlol1_cnt[16]      serdes_sync_1|rxrefclk     FD1P3DX     D       rlol1_cnt_s[16]      9.946        4.197
+rsl_inst.genblk2\.rlols0_cnt[15]     serdes_sync_1|rxrefclk     FD1P3DX     D       rlols0_cnt_s[15]     9.946        4.231
+rsl_inst.genblk2\.rlols0_cnt[16]     serdes_sync_1|rxrefclk     FD1P3DX     D       rlols0_cnt_s[16]     9.946        4.231
+rsl_inst.genblk2\.rlol1_cnt[13]      serdes_sync_1|rxrefclk     FD1P3DX     D       rlol1_cnt_s[13]      9.946        4.258
+rsl_inst.genblk2\.rlol1_cnt[14]      serdes_sync_1|rxrefclk     FD1P3DX     D       rlol1_cnt_s[14]      9.946        4.258
+rsl_inst.genblk2\.rlols0_cnt[13]     serdes_sync_1|rxrefclk     FD1P3DX     D       rlols0_cnt_s[13]     9.946        4.292
+===========================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.809
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.136
+
+    Number of logic level(s):                14
+    Starting point:                          rsl_inst.genblk2\.rlol1_cnt[14] / Q
+    Ending point:                            rsl_inst.genblk2\.rlol1_cnt[18] / D
+    The start point is clocked by            serdes_sync_1|rxrefclk [rising] on pin CK
+    The end   point is clocked by            serdes_sync_1|rxrefclk [rising] on pin CK
+
+Instance / Net                                         Pin      Pin               Arrival     No. of    
+Name                                      Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[14]           FD1P3DX      Q        Out     0.907     0.907       -         
+rlol1_cnt[14]                             Net          -        -       -         -           2         
+rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     Z        Out     0.606     1.513       -         
+rlol1_cnt_tc_1_10                         Net          -        -       -         -           1         
+rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     Z        Out     0.606     2.119       -         
+rlol1_cnt_tc_1_14                         Net          -        -       -         -           1         
+rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     Z        Out     0.768     2.887       -         
+rlol1_cnt_tc_1                            Net          -        -       -         -           6         
+rsl_inst.genblk2\.rlos_db_p1_RNIS0OP      ORCALUT4     A        In      0.000     2.887       -         
+rsl_inst.genblk2\.rlos_db_p1_RNIS0OP      ORCALUT4     Z        Out     0.837     3.724       -         
+rlol1_cnt                                 Net          -        -       -         -           20        
+rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.724       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.624       -         
+rlol1_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.624       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.685       -         
+rlol1_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.685       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.746       -         
+rlol1_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.746       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.807       -         
+rlol1_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.807       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.868       -         
+rlol1_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.868       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.929       -         
+rlol1_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.929       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.990       -         
+rlol1_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.990       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.051       -         
+rlol1_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.051       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.112       -         
+rlol1_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.112       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        S1       Out     0.698     5.809       -         
+rlol1_cnt_s[18]                           Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt[18]           FD1P3DX      D        In      0.000     5.809       -         
+========================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: serdes_sync_1|tx_pclk_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                            Starting                                                                      Arrival          
+Instance                    Reference                                Type        Pin     Net              Time        Slack
+                            Clock                                                                                          
+---------------------------------------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1       serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p1     1.098       5.789
+sll_inst.ppul_sync_p2       serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p2     1.098       5.789
+sll_inst.pcount_diff[0]     serdes_sync_1|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_0      0.985       6.147
+sll_inst.pcount[0]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[0]        0.955       6.178
+sll_inst.pcount_diff[1]     serdes_sync_1|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_1      0.955       6.239
+sll_inst.pcount_diff[2]     serdes_sync_1|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_2      0.955       6.239
+sll_inst.pcount[1]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[1]        0.907       6.287
+sll_inst.pcount[2]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[2]        0.907       6.287
+sll_inst.pcount_diff[3]     serdes_sync_1|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_3      0.955       6.300
+sll_inst.pcount_diff[4]     serdes_sync_1|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_4      0.955       6.300
+===========================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                             Starting                                                                                     Required          
+Instance                     Reference                                Type        Pin     Net                             Time         Slack
+                             Clock                                                                                                          
+--------------------------------------------------------------------------------------------------------------------------------------------
+sll_inst.pcount[21]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[21]                    9.946        5.789
+sll_inst.pcount[19]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[19]                    9.946        5.850
+sll_inst.pcount[20]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[20]                    9.946        5.850
+sll_inst.pcount[17]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[17]                    9.946        5.911
+sll_inst.pcount[18]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[18]                    9.946        5.911
+sll_inst.pcount[15]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[15]                    9.946        5.972
+sll_inst.pcount[16]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[16]                    9.946        5.972
+sll_inst.pcount[13]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[13]                    9.946        6.033
+sll_inst.pcount[14]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[14]                    9.946        6.033
+sll_inst.pcount_diff[21]     serdes_sync_1|tx_pclk_inferred_clock     FD1P3DX     D       un1_pcount_diff_1_s_21_0_S0     9.946        6.034
+============================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      4.157
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 5.789
+
+    Number of logic level(s):                13
+    Starting point:                          sll_inst.ppul_sync_p1 / Q
+    Ending point:                            sll_inst.pcount[21] / D
+    The start point is clocked by            serdes_sync_1|tx_pclk_inferred_clock [rising] on pin CK
+    The end   point is clocked by            serdes_sync_1|tx_pclk_inferred_clock [rising] on pin CK
+
+Instance / Net                             Pin      Pin               Arrival     No. of    
+Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1         FD1S3DX      Q        Out     1.098     1.098       -         
+ppul_sync_p1                  Net          -        -       -         -           25        
+sll_inst.pcount10_0_o3        ORCALUT4     A        In      0.000     1.098       -         
+sll_inst.pcount10_0_o3        ORCALUT4     Z        Out     0.851     1.950       -         
+N_8                           Net          -        -       -         -           25        
+sll_inst.pcount_cry_0[0]      CCU2C        A1       In      0.000     1.950       -         
+sll_inst.pcount_cry_0[0]      CCU2C        COUT     Out     0.900     2.850       -         
+pcount_cry[0]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[1]      CCU2C        CIN      In      0.000     2.850       -         
+sll_inst.pcount_cry_0[1]      CCU2C        COUT     Out     0.061     2.911       -         
+pcount_cry[2]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[3]      CCU2C        CIN      In      0.000     2.911       -         
+sll_inst.pcount_cry_0[3]      CCU2C        COUT     Out     0.061     2.972       -         
+pcount_cry[4]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[5]      CCU2C        CIN      In      0.000     2.972       -         
+sll_inst.pcount_cry_0[5]      CCU2C        COUT     Out     0.061     3.033       -         
+pcount_cry[6]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[7]      CCU2C        CIN      In      0.000     3.033       -         
+sll_inst.pcount_cry_0[7]      CCU2C        COUT     Out     0.061     3.094       -         
+pcount_cry[8]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[9]      CCU2C        CIN      In      0.000     3.094       -         
+sll_inst.pcount_cry_0[9]      CCU2C        COUT     Out     0.061     3.155       -         
+pcount_cry[10]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[11]     CCU2C        CIN      In      0.000     3.155       -         
+sll_inst.pcount_cry_0[11]     CCU2C        COUT     Out     0.061     3.216       -         
+pcount_cry[12]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[13]     CCU2C        CIN      In      0.000     3.216       -         
+sll_inst.pcount_cry_0[13]     CCU2C        COUT     Out     0.061     3.277       -         
+pcount_cry[14]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[15]     CCU2C        CIN      In      0.000     3.277       -         
+sll_inst.pcount_cry_0[15]     CCU2C        COUT     Out     0.061     3.338       -         
+pcount_cry[16]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[17]     CCU2C        CIN      In      0.000     3.338       -         
+sll_inst.pcount_cry_0[17]     CCU2C        COUT     Out     0.061     3.399       -         
+pcount_cry[18]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[19]     CCU2C        CIN      In      0.000     3.399       -         
+sll_inst.pcount_cry_0[19]     CCU2C        COUT     Out     0.061     3.460       -         
+pcount_cry[20]                Net          -        -       -         -           1         
+sll_inst.pcount_s_0[21]       CCU2C        CIN      In      0.000     3.460       -         
+sll_inst.pcount_s_0[21]       CCU2C        S0       Out     0.698     4.157       -         
+pcount_s[21]                  Net          -        -       -         -           1         
+sll_inst.pcount[21]           FD1S3DX      D        In      0.000     4.157       -         
+============================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                                   Arrival           
+Instance      Reference     Type     Pin                Net              Time        Slack 
+              Clock                                                                        
+-------------------------------------------------------------------------------------------
+DCU0_inst     System        DCUA     CH0_FFS_RLOL       rx_cdr_lol_s     0.000       8.810 
+DCU0_inst     System        DCUA     CH0_FFS_RLOS       rx_los_low_s     0.000       8.810 
+DCU0_inst     System        DCUA     CH0_FF_RX_PCLK     rx_pclk          0.000       10.000
+===========================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                       Starting                                                                       Required           
+Instance                                               Reference     Type        Pin                Net                               Time         Slack 
+                                                       Clock                                                                                             
+---------------------------------------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     SP                 un2_rdo_serdes_rst_dual_c_2_i     9.806        8.810 
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     D                  un2_rdo_serdes_rst_dual_c_1       9.946        9.556 
+rsl_inst.genblk2\.rlol_p1                              System        FD1S3DX     D                  rx_cdr_lol_s                      9.946        9.946 
+rsl_inst.genblk2\.rlos_p1                              System        FD1S3DX     D                  rx_los_low_s                      9.946        9.946 
+DCU0_inst                                              System        DCUA        CH0_FF_RXI_CLK     rx_pclk                           10.000       10.000
+=========================================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.194
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.806
+
+    - Propagation time:                      0.996
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 8.810
+
+    Number of logic level(s):                2
+    Starting point:                          DCU0_inst / CH0_FFS_RLOL
+    Ending point:                            rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            serdes_sync_1|rxrefclk [rising] on pin CK
+
+Instance / Net                                                          Pin              Pin               Arrival     No. of    
+Name                                                       Type         Name             Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------------------------------------------------
+DCU0_inst                                                  DCUA         CH0_FFS_RLOL     Out     0.000     0.000       -         
+rx_cdr_lol_s                                               Net          -                -       -         -           4         
+rsl_inst.un2_rdo_serdes_rst_dual_c_2_0                     ORCALUT4     B                In      0.000     0.000       -         
+rsl_inst.un2_rdo_serdes_rst_dual_c_2_0                     ORCALUT4     Z                Out     0.606     0.606       -         
+un2_rdo_serdes_rst_dual_c_2_0                              Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO[0]     ORCALUT4     B                In      0.000     0.606       -         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO[0]     ORCALUT4     Z                Out     0.390     0.996       -         
+un2_rdo_serdes_rst_dual_c_2_i                              Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]         FD1P3DX      SP               In      0.000     0.996       -         
+=================================================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 220 of 24288 (1%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+CCU2C:          113
+DCUA:           1
+FD1P3BX:        20
+FD1P3DX:        92
+FD1S3BX:        12
+FD1S3DX:        96
+GSR:            1
+INV:            3
+ORCALUT4:       150
+PFUMX:          2
+PUR:            1
+VHI:            6
+VLO:            6
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 152MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Fri May 10 10:23:38 2019
+
+###########################################################]

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srr.db b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srr.db
new file mode 100644 (file)
index 0000000..ba0ed54
Binary files /dev/null and b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srr.db differ

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srs b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srs
new file mode 100644 (file)
index 0000000..4da2ca9
Binary files /dev/null and b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srs differ

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.vhm b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.vhm
new file mode 100644 (file)
index 0000000..cc3fb94
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.vhm
@@ -0,0 +1,6398 @@
+--
+-- Written by Synplicity
+-- Product Version "M-2017.03L-SP1-1"
+-- Program "Synplify Pro", Mapper "maplat, Build 1796R"
+-- Fri May 10 10:23:37 2019
+--
+
+--
+-- Written by Synplify Pro version Build 1796R
+-- Fri May 10 10:23:37 2019
+--
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library synplify;
+use synplify.components.all;
+library pmi;
+use pmi.pmi_components.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity sync_0s_0 is
+port(
+  ppul_sync :  in std_logic;
+  pdiff_sync :  out std_logic;
+  sli_rst :  in std_logic;
+  pll_refclki :  in std_logic);
+end sync_0s_0;
+
+architecture beh of sync_0s_0 is
+  signal DATA_P1 : std_logic ;
+  signal DATA_P2_QN_1 : std_logic ;
+  signal VCC : std_logic ;
+  signal DATA_P1_QN_1 : std_logic ;
+  signal GND : std_logic ;
+begin
+DATA_P2_REG_Z10: FD1S3DX port map (
+    D => DATA_P1,
+    CK => pll_refclki,
+    CD => sli_rst,
+    Q => pdiff_sync);
+DATA_P1_REG_Z12: FD1S3DX port map (
+    D => ppul_sync,
+    CK => pll_refclki,
+    CD => sli_rst,
+    Q => DATA_P1);
+VCC_0: VHI port map (
+    Z => VCC);
+II_GND: VLO port map (
+    Z => GND);
+end beh;
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library synplify;
+use synplify.components.all;
+library pmi;
+use pmi.pmi_components.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity sync_0s_6 is
+port(
+rtc_pul :  in std_logic;
+ppul_sync :  out std_logic;
+sli_rst :  in std_logic;
+tx_pclk :  in std_logic);
+end sync_0s_6;
+
+architecture beh of sync_0s_6 is
+signal DATA_P1 : std_logic ;
+signal DATA_P2_QN : std_logic ;
+signal VCC : std_logic ;
+signal DATA_P1_QN : std_logic ;
+signal GND : std_logic ;
+begin
+DATA_P2_REG_Z10: FD1S3DX port map (
+  D => DATA_P1,
+  CK => tx_pclk,
+  CD => sli_rst,
+  Q => ppul_sync);
+DATA_P1_REG_Z12: FD1S3DX port map (
+  D => rtc_pul,
+  CK => tx_pclk,
+  CD => sli_rst,
+  Q => DATA_P1);
+VCC_0: VHI port map (
+  Z => VCC);
+II_GND: VLO port map (
+  Z => GND);
+end beh;
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library synplify;
+use synplify.components.all;
+library pmi;
+use pmi.pmi_components.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity sync_0s is
+port(
+phb :  in std_logic;
+rhb_sync :  out std_logic;
+sli_rst :  in std_logic;
+pll_refclki :  in std_logic);
+end sync_0s;
+
+architecture beh of sync_0s is
+signal DATA_P1 : std_logic ;
+signal DATA_P2_QN_0 : std_logic ;
+signal VCC : std_logic ;
+signal DATA_P1_QN_0 : std_logic ;
+signal GND : std_logic ;
+begin
+DATA_P2_REG_Z10: FD1S3DX port map (
+D => DATA_P1,
+CK => pll_refclki,
+CD => sli_rst,
+Q => rhb_sync);
+DATA_P1_REG_Z12: FD1S3DX port map (
+D => phb,
+CK => pll_refclki,
+CD => sli_rst,
+Q => DATA_P1);
+VCC_0: VHI port map (
+Z => VCC);
+II_GND: VLO port map (
+Z => GND);
+end beh;
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library synplify;
+use synplify.components.all;
+library pmi;
+use pmi.pmi_components.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity serdes_sync_1rsl_core_Z2_layer1 is
+port(
+rx_pcs_rst_c :  in std_logic;
+serdes_rst_dual_c :  in std_logic;
+tx_serdes_rst_c :  in std_logic;
+rsl_tx_pcs_rst_c :  out std_logic;
+rst_dual_c :  in std_logic;
+rsl_rx_pcs_rst_c :  out std_logic;
+rsl_tx_serdes_rst_c :  out std_logic;
+rsl_tx_rdy :  out std_logic;
+pll_lock_i :  in std_logic;
+pll_refclki :  in std_logic;
+rsl_rx_rdy :  out std_logic;
+rx_cdr_lol_s :  in std_logic;
+rx_los_low_s :  in std_logic;
+rsl_rst :  in std_logic;
+rxrefclk :  in std_logic;
+rx_serdes_rst_c :  in std_logic;
+rsl_rx_serdes_rst_c :  out std_logic;
+rsl_serdes_rst_dual_c :  out std_logic;
+rsl_disable :  in std_logic;
+tx_pcs_rst_c :  in std_logic);
+end serdes_sync_1rsl_core_Z2_layer1;
+
+architecture beh of serdes_sync_1rsl_core_Z2_layer1 is
+signal PLOL0_CNT : std_logic_vector(2 downto 0);
+signal PLOL0_CNT_3 : std_logic_vector(2 downto 0);
+signal RXSR_APPD : std_logic_vector(0 to 0);
+signal RXS_CNT_3 : std_logic_vector(1 downto 0);
+signal RXS_CNT : std_logic_vector(1 downto 0);
+signal RXS_CNT_QN : std_logic_vector(1 downto 0);
+signal RLOS_DB_CNT : std_logic_vector(3 downto 0);
+signal RLOS_DB_CNT_QN : std_logic_vector(3 downto 0);
+signal RLOLS0_CNT_S : std_logic_vector(17 downto 0);
+signal RLOLS0_CNT : std_logic_vector(17 downto 0);
+signal RLOLS0_CNT_QN : std_logic_vector(17 downto 0);
+signal RLOL_DB_CNT : std_logic_vector(3 downto 0);
+signal RLOL_DB_CNT_QN : std_logic_vector(3 downto 0);
+signal RLOL1_CNT_S : std_logic_vector(18 downto 0);
+signal RLOL1_CNT : std_logic_vector(18 downto 0);
+signal RLOL1_CNT_QN : std_logic_vector(18 downto 0);
+signal RXR_WT_CNT_S : std_logic_vector(11 downto 0);
+signal RXR_WT_CNT : std_logic_vector(11 downto 0);
+signal RXR_WT_CNT_QN : std_logic_vector(11 downto 0);
+signal RXSR_APPD_QN : std_logic_vector(0 to 0);
+signal RXPR_APPD : std_logic_vector(0 to 0);
+signal RXPR_APPD_QN : std_logic_vector(0 to 0);
+signal TXS_CNT : std_logic_vector(1 downto 0);
+signal TXS_CNT_QN : std_logic_vector(1 downto 0);
+signal TXS_CNT_RNO : std_logic_vector(1 to 1);
+signal TXP_CNT : std_logic_vector(1 downto 0);
+signal TXP_CNT_QN : std_logic_vector(1 downto 0);
+signal TXP_CNT_RNO : std_logic_vector(1 to 1);
+signal PLOL_CNT_S : std_logic_vector(19 downto 0);
+signal PLOL_CNT : std_logic_vector(19 downto 0);
+signal PLOL_CNT_QN : std_logic_vector(19 downto 0);
+signal PLOL0_CNT_QN : std_logic_vector(2 downto 0);
+signal TXR_WT_CNT_S : std_logic_vector(11 downto 0);
+signal TXR_WT_CNT : std_logic_vector(11 downto 0);
+signal TXR_WT_CNT_QN : std_logic_vector(11 downto 0);
+signal TXPR_APPD : std_logic_vector(0 to 0);
+signal TXPR_APPD_QN : std_logic_vector(0 to 0);
+signal UN1_RLOL_DB_CNT_ZERO : std_logic_vector(0 to 0);
+signal UN1_RLOS_DB_CNT_ZERO : std_logic_vector(0 to 0);
+signal UN1_RLOL_DB_CNT_ZERO_BM : std_logic_vector(0 to 0);
+signal UN1_RLOL_DB_CNT_ZERO_AM : std_logic_vector(0 to 0);
+signal UN1_RLOS_DB_CNT_ZERO_BM : std_logic_vector(0 to 0);
+signal UN1_RLOS_DB_CNT_ZERO_AM : std_logic_vector(0 to 0);
+signal RLOL1_CNT_CRY : std_logic_vector(16 downto 0);
+signal RLOL1_CNT_CRY_0_S0 : std_logic_vector(0 to 0);
+signal RLOL1_CNT_CRY_0_COUT : std_logic_vector(17 to 17);
+signal RLOLS0_CNT_CRY : std_logic_vector(16 downto 0);
+signal RLOLS0_CNT_CRY_0_S0 : std_logic_vector(0 to 0);
+signal RLOLS0_CNT_S_0_COUT : std_logic_vector(17 to 17);
+signal RLOLS0_CNT_S_0_S1 : std_logic_vector(17 to 17);
+signal TXR_WT_CNT_CRY : std_logic_vector(10 downto 0);
+signal TXR_WT_CNT_CRY_0_S0 : std_logic_vector(0 to 0);
+signal TXR_WT_CNT_S_0_COUT : std_logic_vector(11 to 11);
+signal TXR_WT_CNT_S_0_S1 : std_logic_vector(11 to 11);
+signal RXR_WT_CNT_CRY : std_logic_vector(10 downto 0);
+signal RXR_WT_CNT_CRY_0_S0 : std_logic_vector(0 to 0);
+signal RXR_WT_CNT_S_0_COUT : std_logic_vector(11 to 11);
+signal RXR_WT_CNT_S_0_S1 : std_logic_vector(11 to 11);
+signal PLOL_CNT_CRY : std_logic_vector(18 downto 0);
+signal PLOL_CNT_CRY_0_S0 : std_logic_vector(0 to 0);
+signal PLOL_CNT_S_0_COUT : std_logic_vector(19 to 19);
+signal PLOL_CNT_S_0_S1 : std_logic_vector(19 to 19);
+signal TXDPR_APPD : std_logic ;
+signal TXP_RST : std_logic ;
+signal UN2_RDO_TX_PCS_RST_C : std_logic ;
+signal RSL_SERDES_RST_DUAL_C_10 : std_logic ;
+signal RSL_RX_SERDES_RST_C_9 : std_logic ;
+signal RLOS_DB_P1 : std_logic ;
+signal RLOS_DB : std_logic ;
+signal RXP_RST25 : std_logic ;
+signal PLOL0_CNT9 : std_logic ;
+signal WAITA_PLOL0 : std_logic ;
+signal DUAL_OR_SERD_RST : std_logic ;
+signal UN18_TXR_WT_TC_8 : std_logic ;
+signal UN18_TXR_WT_TC_7 : std_logic ;
+signal UN18_TXR_WT_TC_6 : std_logic ;
+signal UN1_DUAL_OR_SERD_RST_1_1 : std_logic ;
+signal UN1_RUI_RST_DUAL_C_1_1 : std_logic ;
+signal UN17_RXR_WT_TC_8 : std_logic ;
+signal UN17_RXR_WT_TC_7 : std_logic ;
+signal UN17_RXR_WT_TC_6 : std_logic ;
+signal UN3_RX_ALL_WELL_1 : std_logic ;
+signal RLOL1_CNT_TC_1 : std_logic ;
+signal RXS_RST : std_logic ;
+signal \RLOL1_CNT_\ : std_logic ;
+signal UN2_PLOL_FEDGE_5_1 : std_logic ;
+signal UN2_PLOL_FEDGE_5_I : std_logic ;
+signal N_2175_0 : std_logic ;
+signal WAITA_RLOLS06 : std_logic ;
+signal UN1_RLOLS0_CNT_TC : std_logic ;
+signal WAITA_RLOLS0 : std_logic ;
+signal WAITA_RLOLS0_QN : std_logic ;
+signal VCC : std_logic ;
+signal WAIT_CALIB_RNO : std_logic ;
+signal UN1_RLOS_FEDGE_1 : std_logic ;
+signal WAIT_CALIB : std_logic ;
+signal WAIT_CALIB_QN : std_logic ;
+signal RXS_RST6 : std_logic ;
+signal UN1_RXS_CNT_TC : std_logic ;
+signal RXS_RST_QN : std_logic ;
+signal UN2_RLOS_REDGE_1_I : std_logic ;
+signal RXP_RST2 : std_logic ;
+signal RXP_RST2_QN : std_logic ;
+signal RLOS_P1 : std_logic ;
+signal RLOS_P2 : std_logic ;
+signal RLOS_P2_QN : std_logic ;
+signal RLOS_P1_QN : std_logic ;
+signal RLOS_DB_P1_QN : std_logic ;
+signal RLOS_DB_CNT_AXB_0 : std_logic ;
+signal RLOS_DB_CNT_CRY_1_0_S0 : std_logic ;
+signal RLOS_DB_CNT_CRY_1_0_S1 : std_logic ;
+signal RLOS_DB_CNT_S_3_0_S0 : std_logic ;
+signal UN1_RLOS_DB_CNT_MAX : std_logic ;
+signal RLOS_DB_QN : std_logic ;
+signal RLOLS0_CNTE : std_logic ;
+signal RLOL_P1 : std_logic ;
+signal RLOL_P2 : std_logic ;
+signal RLOL_P2_QN : std_logic ;
+signal RLOL_P1_QN : std_logic ;
+signal RLOL_DB : std_logic ;
+signal RLOL_DB_P1 : std_logic ;
+signal RLOL_DB_P1_QN : std_logic ;
+signal RLOL_DB_CNT_AXB_0 : std_logic ;
+signal RLOL_DB_CNT_CRY_1_0_S0 : std_logic ;
+signal RLOL_DB_CNT_CRY_1_0_S1 : std_logic ;
+signal RLOL_DB_CNT_S_3_0_S0 : std_logic ;
+signal UN1_RLOL_DB_CNT_MAX : std_logic ;
+signal RLOL_DB_QN : std_logic ;
+signal RLOL1_CNTE : std_logic ;
+signal RXSDR_APPD_2 : std_logic ;
+signal RXSDR_APPD : std_logic ;
+signal RXSDR_APPD_QN : std_logic ;
+signal UN1_DUAL_OR_RSERD_RST_2_I : std_logic ;
+signal RXR_WT_EN : std_logic ;
+signal RXR_WT_EN_QN : std_logic ;
+signal RXR_WT_CNTE : std_logic ;
+signal UN1_RUI_RST_DUAL_C_1_I : std_logic ;
+signal RXDPR_APPD : std_logic ;
+signal RXDPR_APPD_QN : std_logic ;
+signal UN3_RX_ALL_WELL_2 : std_logic ;
+signal RXR_WT_CNT9 : std_logic ;
+signal RSL_RX_RDY_8 : std_logic ;
+signal RUO_RX_RDYR_QN : std_logic ;
+signal UN2_RDO_SERDES_RST_DUAL_C_1 : std_logic ;
+signal UN2_RDO_SERDES_RST_DUAL_C_2_I : std_logic ;
+signal PLOL_FEDGE : std_logic ;
+signal UN1_PLOL0_CNT_TC_1_I : std_logic ;
+signal WAITA_PLOL0_QN : std_logic ;
+signal UN1_PLOL_CNT_TC : std_logic ;
+signal UN2_PLOL_CNT_TC : std_logic ;
+signal TXS_RST : std_logic ;
+signal TXS_RST_QN : std_logic ;
+signal N_10_I : std_logic ;
+signal UN9_PLOL0_CNT_TC : std_logic ;
+signal UN1_PLOL0_CNT_TC_1 : std_logic ;
+signal TXP_RST_QN : std_logic ;
+signal N_11_I : std_logic ;
+signal PLL_LOL_P2 : std_logic ;
+signal PLL_LOL_P3 : std_logic ;
+signal PLL_LOL_P3_QN : std_logic ;
+signal PLL_LOL_P1 : std_logic ;
+signal PLL_LOL_P2_QN : std_logic ;
+signal PLL_LOL_P1_QN : std_logic ;
+signal TXSR_APPD_2 : std_logic ;
+signal TXSR_APPD : std_logic ;
+signal TXSR_APPD_QN : std_logic ;
+signal UN1_DUAL_OR_SERD_RST_1_I : std_logic ;
+signal TXR_WT_EN : std_logic ;
+signal TXR_WT_EN_QN : std_logic ;
+signal TXR_WT_CNTE : std_logic ;
+signal UN2_PLOL_FEDGE_2 : std_logic ;
+signal UN2_PLOL_FEDGE_3_I : std_logic ;
+signal TXDPR_APPD_QN : std_logic ;
+signal RSL_TX_RDY_7 : std_logic ;
+signal RUO_TX_RDYR_QN : std_logic ;
+signal UN2_PLOL_FEDGE_8_I : std_logic ;
+signal RLOLS0_CNT_TC_1 : std_logic ;
+signal RLOS_REDGE : std_logic ;
+signal RLOLS0_CNT11_0 : std_logic ;
+signal RSL_TX_SERDES_RST_C_6 : std_logic ;
+signal \PLOL_CNT_\ : std_logic ;
+signal \RLOLS0_CNT_\ : std_logic ;
+signal UN8_RXS_CNT_TC : std_logic ;
+signal TXSR_APPD_4 : std_logic ;
+signal UN17_RXR_WT_TC : std_logic ;
+signal UN1_DUAL_OR_RSERD_RST_2_0 : std_logic ;
+signal UN1_RXSDR_OR_SR_APPD_0 : std_logic ;
+signal UN2_RDO_SERDES_RST_DUAL_C_2_0 : std_logic ;
+signal RSL_RX_PCS_RST_C_5 : std_logic ;
+signal TXR_WT_CNT9 : std_logic ;
+signal RX_ANY_RST : std_logic ;
+signal UN18_TXR_WT_TC : std_logic ;
+signal RSL_TX_PCS_RST_C_4 : std_logic ;
+signal RLOLS0_CNT_TC_1_10 : std_logic ;
+signal RLOLS0_CNT_TC_1_11 : std_logic ;
+signal RLOLS0_CNT_TC_1_12 : std_logic ;
+signal RLOLS0_CNT_TC_1_13 : std_logic ;
+signal RLOL1_CNT_TC_1_11 : std_logic ;
+signal RLOL1_CNT_TC_1_12 : std_logic ;
+signal RLOL1_CNT_TC_1_13 : std_logic ;
+signal RLOL1_CNT_TC_1_14 : std_logic ;
+signal UN1_PLOL_CNT_TC_11 : std_logic ;
+signal UN1_PLOL_CNT_TC_12 : std_logic ;
+signal UN1_PLOL_CNT_TC_13 : std_logic ;
+signal UN1_PLOL_CNT_TC_14 : std_logic ;
+signal CO0_2 : std_logic ;
+signal RLOLS0_CNT_TC_1_9 : std_logic ;
+signal UN1_PLOL_CNT_TC_10 : std_logic ;
+signal RLOL1_CNT_TC_1_10 : std_logic ;
+signal UN3_RX_ALL_WELL_2_1 : std_logic ;
+signal RXSDR_APPD_4 : std_logic ;
+signal RLOS_DB_CNT_CRY_0 : std_logic ;
+signal RLOS_DB_CNT_CRY_0_0_S0 : std_logic ;
+signal RLOS_DB_CNT_CRY_0_0_S1 : std_logic ;
+signal RLOS_DB_CNT_CRY_2 : std_logic ;
+signal RLOS_DB_CNT_S_3_0_COUT : std_logic ;
+signal RLOS_DB_CNT_S_3_0_S1 : std_logic ;
+signal RLOL_DB_CNT_CRY_0 : std_logic ;
+signal RLOL_DB_CNT_CRY_0_0_S0 : std_logic ;
+signal RLOL_DB_CNT_CRY_0_0_S1 : std_logic ;
+signal RLOL_DB_CNT_CRY_2 : std_logic ;
+signal RLOL_DB_CNT_S_3_0_COUT : std_logic ;
+signal RLOL_DB_CNT_S_3_0_S1 : std_logic ;
+signal GND : std_logic ;
+signal N_1 : std_logic ;
+signal N_2 : std_logic ;
+signal N_3 : std_logic ;
+signal N_4 : std_logic ;
+signal N_5 : std_logic ;
+signal N_6 : std_logic ;
+signal N_7 : std_logic ;
+begin
+\GENBLK1.GENBLK2.MFOR[0].TXPR_APPD_RNO_0[0]\: LUT4 
+generic map(
+  init => X"EEFE"
+)
+port map (
+A => TXDPR_APPD,
+B => tx_pcs_rst_c,
+C => TXP_RST,
+D => rsl_disable,
+Z => UN2_RDO_TX_PCS_RST_C);
+\GENBLK2.RXP_RST2_RNO\: LUT4 
+generic map(
+  init => X"EFEE"
+)
+port map (
+A => RSL_SERDES_RST_DUAL_C_10,
+B => RSL_RX_SERDES_RST_C_9,
+C => RLOS_DB_P1,
+D => RLOS_DB,
+Z => RXP_RST25);
+\GENBLK1.PLOL0_CNT_RNO[1]\: LUT4 
+generic map(
+  init => X"1222"
+)
+port map (
+A => PLOL0_CNT(1),
+B => PLOL0_CNT9,
+C => WAITA_PLOL0,
+D => PLOL0_CNT(0),
+Z => PLOL0_CNT_3(1));
+\GENBLK1.GENBLK2.UN18_TXR_WT_TC_6_RNI7IS21\: LUT4 
+generic map(
+  init => X"1555"
+)
+port map (
+A => DUAL_OR_SERD_RST,
+B => UN18_TXR_WT_TC_8,
+C => UN18_TXR_WT_TC_7,
+D => UN18_TXR_WT_TC_6,
+Z => UN1_DUAL_OR_SERD_RST_1_1);
+\GENBLK2.GENBLK3.RXR_WT_EN_RNO\: LUT4 
+generic map(
+  init => X"2AAA"
+)
+port map (
+A => UN1_RUI_RST_DUAL_C_1_1,
+B => UN17_RXR_WT_TC_8,
+C => UN17_RXR_WT_TC_7,
+D => UN17_RXR_WT_TC_6,
+Z => UN3_RX_ALL_WELL_1);
+\GENBLK2.RLOS_DB_P1_RNIS0OP\: LUT4 
+generic map(
+  init => X"1011"
+)
+port map (
+A => RLOL1_CNT_TC_1,
+B => RXS_RST,
+C => RLOS_DB_P1,
+D => RLOS_DB,
+Z => \RLOL1_CNT_\);
+\GENBLK1.GENBLK2.RUO_TX_RDYR_RNO\: LUT4 
+generic map(
+  init => X"D555"
+)
+port map (
+A => UN2_PLOL_FEDGE_5_1,
+B => UN18_TXR_WT_TC_8,
+C => UN18_TXR_WT_TC_7,
+D => UN18_TXR_WT_TC_6,
+Z => UN2_PLOL_FEDGE_5_I);
+\GENBLK2.GENBLK3.LFOR[0].RXSR_APPD_RNO[0]\: LUT4 
+generic map(
+  init => X"EEFE"
+)
+port map (
+A => RXSR_APPD(0),
+B => rx_serdes_rst_c,
+C => RXS_RST,
+D => rsl_disable,
+Z => N_2175_0);
+\GENBLK2.WAITA_RLOLS0_REG_Z610\: FD1P3DX port map (
+D => WAITA_RLOLS06,
+SP => UN1_RLOLS0_CNT_TC,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => WAITA_RLOLS0);
+\GENBLK2.WAIT_CALIB_REG_Z612\: FD1P3BX port map (
+D => WAIT_CALIB_RNO,
+SP => UN1_RLOS_FEDGE_1,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => WAIT_CALIB);
+\GENBLK2.RXS_RST_REG_Z614\: FD1P3DX port map (
+D => RXS_RST6,
+SP => UN1_RXS_CNT_TC,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXS_RST);
+\GENBLK2.RXS_CNT[0]_REG_Z616\: FD1S3DX port map (
+D => RXS_CNT_3(0),
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXS_CNT(0));
+\GENBLK2.RXS_CNT[1]_REG_Z618\: FD1S3DX port map (
+D => RXS_CNT_3(1),
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXS_CNT(1));
+\GENBLK2.RXP_RST2_REG_Z620\: FD1P3BX port map (
+D => RXP_RST25,
+SP => UN2_RLOS_REDGE_1_I,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RXP_RST2);
+\GENBLK2.RLOS_P2_REG_Z622\: FD1S3DX port map (
+D => RLOS_P1,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOS_P2);
+\GENBLK2.RLOS_P1_REG_Z624\: FD1S3DX port map (
+D => rx_los_low_s,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOS_P1);
+\GENBLK2.RLOS_DB_P1_REG_Z626\: FD1S3BX port map (
+D => RLOS_DB,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOS_DB_P1);
+\GENBLK2.RLOS_DB_CNT[0]_REG_Z628\: FD1S3BX port map (
+D => RLOS_DB_CNT_AXB_0,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOS_DB_CNT(0));
+\GENBLK2.RLOS_DB_CNT[1]_REG_Z630\: FD1S3BX port map (
+D => RLOS_DB_CNT_CRY_1_0_S0,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOS_DB_CNT(1));
+\GENBLK2.RLOS_DB_CNT[2]_REG_Z632\: FD1S3BX port map (
+D => RLOS_DB_CNT_CRY_1_0_S1,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOS_DB_CNT(2));
+\GENBLK2.RLOS_DB_CNT[3]_REG_Z634\: FD1S3BX port map (
+D => RLOS_DB_CNT_S_3_0_S0,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOS_DB_CNT(3));
+\GENBLK2.RLOS_DB_REG_Z636\: FD1P3BX port map (
+D => RLOS_DB_CNT(1),
+SP => UN1_RLOS_DB_CNT_MAX,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOS_DB);
+\GENBLK2.RLOLS0_CNT[0]_REG_Z638\: FD1P3DX port map (
+D => RLOLS0_CNT_S(0),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(0));
+\GENBLK2.RLOLS0_CNT[1]_REG_Z640\: FD1P3DX port map (
+D => RLOLS0_CNT_S(1),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(1));
+\GENBLK2.RLOLS0_CNT[2]_REG_Z642\: FD1P3DX port map (
+D => RLOLS0_CNT_S(2),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(2));
+\GENBLK2.RLOLS0_CNT[3]_REG_Z644\: FD1P3DX port map (
+D => RLOLS0_CNT_S(3),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(3));
+\GENBLK2.RLOLS0_CNT[4]_REG_Z646\: FD1P3DX port map (
+D => RLOLS0_CNT_S(4),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(4));
+\GENBLK2.RLOLS0_CNT[5]_REG_Z648\: FD1P3DX port map (
+D => RLOLS0_CNT_S(5),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(5));
+\GENBLK2.RLOLS0_CNT[6]_REG_Z650\: FD1P3DX port map (
+D => RLOLS0_CNT_S(6),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(6));
+\GENBLK2.RLOLS0_CNT[7]_REG_Z652\: FD1P3DX port map (
+D => RLOLS0_CNT_S(7),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(7));
+\GENBLK2.RLOLS0_CNT[8]_REG_Z654\: FD1P3DX port map (
+D => RLOLS0_CNT_S(8),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(8));
+\GENBLK2.RLOLS0_CNT[9]_REG_Z656\: FD1P3DX port map (
+D => RLOLS0_CNT_S(9),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(9));
+\GENBLK2.RLOLS0_CNT[10]_REG_Z658\: FD1P3DX port map (
+D => RLOLS0_CNT_S(10),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(10));
+\GENBLK2.RLOLS0_CNT[11]_REG_Z660\: FD1P3DX port map (
+D => RLOLS0_CNT_S(11),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(11));
+\GENBLK2.RLOLS0_CNT[12]_REG_Z662\: FD1P3DX port map (
+D => RLOLS0_CNT_S(12),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(12));
+\GENBLK2.RLOLS0_CNT[13]_REG_Z664\: FD1P3DX port map (
+D => RLOLS0_CNT_S(13),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(13));
+\GENBLK2.RLOLS0_CNT[14]_REG_Z666\: FD1P3DX port map (
+D => RLOLS0_CNT_S(14),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(14));
+\GENBLK2.RLOLS0_CNT[15]_REG_Z668\: FD1P3DX port map (
+D => RLOLS0_CNT_S(15),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(15));
+\GENBLK2.RLOLS0_CNT[16]_REG_Z670\: FD1P3DX port map (
+D => RLOLS0_CNT_S(16),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(16));
+\GENBLK2.RLOLS0_CNT[17]_REG_Z672\: FD1P3DX port map (
+D => RLOLS0_CNT_S(17),
+SP => RLOLS0_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOLS0_CNT(17));
+\GENBLK2.RLOL_P2_REG_Z674\: FD1S3DX port map (
+D => RLOL_P1,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL_P2);
+\GENBLK2.RLOL_P1_REG_Z676\: FD1S3DX port map (
+D => rx_cdr_lol_s,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL_P1);
+\GENBLK2.RLOL_DB_P1_REG_Z678\: FD1S3BX port map (
+D => RLOL_DB,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOL_DB_P1);
+\GENBLK2.RLOL_DB_CNT[0]_REG_Z680\: FD1S3BX port map (
+D => RLOL_DB_CNT_AXB_0,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOL_DB_CNT(0));
+\GENBLK2.RLOL_DB_CNT[1]_REG_Z682\: FD1S3BX port map (
+D => RLOL_DB_CNT_CRY_1_0_S0,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOL_DB_CNT(1));
+\GENBLK2.RLOL_DB_CNT[2]_REG_Z684\: FD1S3BX port map (
+D => RLOL_DB_CNT_CRY_1_0_S1,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOL_DB_CNT(2));
+\GENBLK2.RLOL_DB_CNT[3]_REG_Z686\: FD1S3BX port map (
+D => RLOL_DB_CNT_S_3_0_S0,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOL_DB_CNT(3));
+\GENBLK2.RLOL_DB_REG_Z688\: FD1P3BX port map (
+D => RLOL_DB_CNT(1),
+SP => UN1_RLOL_DB_CNT_MAX,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RLOL_DB);
+\GENBLK2.RLOL1_CNT[0]_REG_Z690\: FD1P3DX port map (
+D => RLOL1_CNT_S(0),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(0));
+\GENBLK2.RLOL1_CNT[1]_REG_Z692\: FD1P3DX port map (
+D => RLOL1_CNT_S(1),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(1));
+\GENBLK2.RLOL1_CNT[2]_REG_Z694\: FD1P3DX port map (
+D => RLOL1_CNT_S(2),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(2));
+\GENBLK2.RLOL1_CNT[3]_REG_Z696\: FD1P3DX port map (
+D => RLOL1_CNT_S(3),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(3));
+\GENBLK2.RLOL1_CNT[4]_REG_Z698\: FD1P3DX port map (
+D => RLOL1_CNT_S(4),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(4));
+\GENBLK2.RLOL1_CNT[5]_REG_Z700\: FD1P3DX port map (
+D => RLOL1_CNT_S(5),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(5));
+\GENBLK2.RLOL1_CNT[6]_REG_Z702\: FD1P3DX port map (
+D => RLOL1_CNT_S(6),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(6));
+\GENBLK2.RLOL1_CNT[7]_REG_Z704\: FD1P3DX port map (
+D => RLOL1_CNT_S(7),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(7));
+\GENBLK2.RLOL1_CNT[8]_REG_Z706\: FD1P3DX port map (
+D => RLOL1_CNT_S(8),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(8));
+\GENBLK2.RLOL1_CNT[9]_REG_Z708\: FD1P3DX port map (
+D => RLOL1_CNT_S(9),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(9));
+\GENBLK2.RLOL1_CNT[10]_REG_Z710\: FD1P3DX port map (
+D => RLOL1_CNT_S(10),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(10));
+\GENBLK2.RLOL1_CNT[11]_REG_Z712\: FD1P3DX port map (
+D => RLOL1_CNT_S(11),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(11));
+\GENBLK2.RLOL1_CNT[12]_REG_Z714\: FD1P3DX port map (
+D => RLOL1_CNT_S(12),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(12));
+\GENBLK2.RLOL1_CNT[13]_REG_Z716\: FD1P3DX port map (
+D => RLOL1_CNT_S(13),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(13));
+\GENBLK2.RLOL1_CNT[14]_REG_Z718\: FD1P3DX port map (
+D => RLOL1_CNT_S(14),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(14));
+\GENBLK2.RLOL1_CNT[15]_REG_Z720\: FD1P3DX port map (
+D => RLOL1_CNT_S(15),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(15));
+\GENBLK2.RLOL1_CNT[16]_REG_Z722\: FD1P3DX port map (
+D => RLOL1_CNT_S(16),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(16));
+\GENBLK2.RLOL1_CNT[17]_REG_Z724\: FD1P3DX port map (
+D => RLOL1_CNT_S(17),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(17));
+\GENBLK2.RLOL1_CNT[18]_REG_Z726\: FD1P3DX port map (
+D => RLOL1_CNT_S(18),
+SP => RLOL1_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RLOL1_CNT(18));
+\GENBLK2.GENBLK3.RXSDR_APPD_REG_Z728\: FD1S3BX port map (
+D => RXSDR_APPD_2,
+CK => rxrefclk,
+PD => rsl_rst,
+Q => RXSDR_APPD);
+\GENBLK2.GENBLK3.RXR_WT_EN_REG_Z730\: FD1P3DX port map (
+D => UN3_RX_ALL_WELL_1,
+SP => UN1_DUAL_OR_RSERD_RST_2_I,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_EN);
+\GENBLK2.GENBLK3.RXR_WT_CNT[0]_REG_Z732\: FD1P3DX port map (
+D => RXR_WT_CNT_S(0),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(0));
+\GENBLK2.GENBLK3.RXR_WT_CNT[1]_REG_Z734\: FD1P3DX port map (
+D => RXR_WT_CNT_S(1),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(1));
+\GENBLK2.GENBLK3.RXR_WT_CNT[2]_REG_Z736\: FD1P3DX port map (
+D => RXR_WT_CNT_S(2),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(2));
+\GENBLK2.GENBLK3.RXR_WT_CNT[3]_REG_Z738\: FD1P3DX port map (
+D => RXR_WT_CNT_S(3),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(3));
+\GENBLK2.GENBLK3.RXR_WT_CNT[4]_REG_Z740\: FD1P3DX port map (
+D => RXR_WT_CNT_S(4),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(4));
+\GENBLK2.GENBLK3.RXR_WT_CNT[5]_REG_Z742\: FD1P3DX port map (
+D => RXR_WT_CNT_S(5),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(5));
+\GENBLK2.GENBLK3.RXR_WT_CNT[6]_REG_Z744\: FD1P3DX port map (
+D => RXR_WT_CNT_S(6),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(6));
+\GENBLK2.GENBLK3.RXR_WT_CNT[7]_REG_Z746\: FD1P3DX port map (
+D => RXR_WT_CNT_S(7),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(7));
+\GENBLK2.GENBLK3.RXR_WT_CNT[8]_REG_Z748\: FD1P3DX port map (
+D => RXR_WT_CNT_S(8),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(8));
+\GENBLK2.GENBLK3.RXR_WT_CNT[9]_REG_Z750\: FD1P3DX port map (
+D => RXR_WT_CNT_S(9),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(9));
+\GENBLK2.GENBLK3.RXR_WT_CNT[10]_REG_Z752\: FD1P3DX port map (
+D => RXR_WT_CNT_S(10),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(10));
+\GENBLK2.GENBLK3.RXR_WT_CNT[11]_REG_Z754\: FD1P3DX port map (
+D => RXR_WT_CNT_S(11),
+SP => RXR_WT_CNTE,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXR_WT_CNT(11));
+\GENBLK2.GENBLK3.RXDPR_APPD_REG_Z756\: FD1P3DX port map (
+D => UN1_RUI_RST_DUAL_C_1_1,
+SP => UN1_RUI_RST_DUAL_C_1_I,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXDPR_APPD);
+\GENBLK2.GENBLK3.RUO_RX_RDYR_REG_Z758\: FD1P3DX port map (
+D => UN3_RX_ALL_WELL_2,
+SP => RXR_WT_CNT9,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RSL_RX_RDY_8);
+\GENBLK2.GENBLK3.LFOR[0].RXSR_APPD[0]_REG_Z760\: FD1S3DX port map (
+D => N_2175_0,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXSR_APPD(0));
+\GENBLK2.GENBLK3.LFOR[0].RXPR_APPD[0]_REG_Z762\: FD1P3DX port map (
+D => UN2_RDO_SERDES_RST_DUAL_C_1,
+SP => UN2_RDO_SERDES_RST_DUAL_C_2_I,
+CK => rxrefclk,
+CD => rsl_rst,
+Q => RXPR_APPD(0));
+\GENBLK1.WAITA_PLOL0_REG_Z764\: FD1P3DX port map (
+D => PLOL_FEDGE,
+SP => UN1_PLOL0_CNT_TC_1_I,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => WAITA_PLOL0);
+\GENBLK1.TXS_RST_REG_Z766\: FD1P3DX port map (
+D => UN1_PLOL_CNT_TC,
+SP => UN2_PLOL_CNT_TC,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXS_RST);
+\GENBLK1.TXS_CNT[0]_REG_Z768\: FD1S3DX port map (
+D => N_10_I,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXS_CNT(0));
+\GENBLK1.TXS_CNT[1]_REG_Z770\: FD1S3DX port map (
+D => TXS_CNT_RNO(1),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXS_CNT(1));
+\GENBLK1.TXP_RST_REG_Z772\: FD1P3DX port map (
+D => UN9_PLOL0_CNT_TC,
+SP => UN1_PLOL0_CNT_TC_1,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXP_RST);
+\GENBLK1.TXP_CNT[0]_REG_Z774\: FD1S3DX port map (
+D => N_11_I,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXP_CNT(0));
+\GENBLK1.TXP_CNT[1]_REG_Z776\: FD1S3DX port map (
+D => TXP_CNT_RNO(1),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXP_CNT(1));
+\GENBLK1.PLOL_CNT[0]_REG_Z778\: FD1S3DX port map (
+D => PLOL_CNT_S(0),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(0));
+\GENBLK1.PLOL_CNT[1]_REG_Z780\: FD1S3DX port map (
+D => PLOL_CNT_S(1),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(1));
+\GENBLK1.PLOL_CNT[2]_REG_Z782\: FD1S3DX port map (
+D => PLOL_CNT_S(2),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(2));
+\GENBLK1.PLOL_CNT[3]_REG_Z784\: FD1S3DX port map (
+D => PLOL_CNT_S(3),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(3));
+\GENBLK1.PLOL_CNT[4]_REG_Z786\: FD1S3DX port map (
+D => PLOL_CNT_S(4),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(4));
+\GENBLK1.PLOL_CNT[5]_REG_Z788\: FD1S3DX port map (
+D => PLOL_CNT_S(5),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(5));
+\GENBLK1.PLOL_CNT[6]_REG_Z790\: FD1S3DX port map (
+D => PLOL_CNT_S(6),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(6));
+\GENBLK1.PLOL_CNT[7]_REG_Z792\: FD1S3DX port map (
+D => PLOL_CNT_S(7),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(7));
+\GENBLK1.PLOL_CNT[8]_REG_Z794\: FD1S3DX port map (
+D => PLOL_CNT_S(8),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(8));
+\GENBLK1.PLOL_CNT[9]_REG_Z796\: FD1S3DX port map (
+D => PLOL_CNT_S(9),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(9));
+\GENBLK1.PLOL_CNT[10]_REG_Z798\: FD1S3DX port map (
+D => PLOL_CNT_S(10),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(10));
+\GENBLK1.PLOL_CNT[11]_REG_Z800\: FD1S3DX port map (
+D => PLOL_CNT_S(11),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(11));
+\GENBLK1.PLOL_CNT[12]_REG_Z802\: FD1S3DX port map (
+D => PLOL_CNT_S(12),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(12));
+\GENBLK1.PLOL_CNT[13]_REG_Z804\: FD1S3DX port map (
+D => PLOL_CNT_S(13),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(13));
+\GENBLK1.PLOL_CNT[14]_REG_Z806\: FD1S3DX port map (
+D => PLOL_CNT_S(14),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(14));
+\GENBLK1.PLOL_CNT[15]_REG_Z808\: FD1S3DX port map (
+D => PLOL_CNT_S(15),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(15));
+\GENBLK1.PLOL_CNT[16]_REG_Z810\: FD1S3DX port map (
+D => PLOL_CNT_S(16),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(16));
+\GENBLK1.PLOL_CNT[17]_REG_Z812\: FD1S3DX port map (
+D => PLOL_CNT_S(17),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(17));
+\GENBLK1.PLOL_CNT[18]_REG_Z814\: FD1S3DX port map (
+D => PLOL_CNT_S(18),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(18));
+\GENBLK1.PLOL_CNT[19]_REG_Z816\: FD1S3DX port map (
+D => PLOL_CNT_S(19),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL_CNT(19));
+\GENBLK1.PLOL0_CNT[0]_REG_Z818\: FD1S3DX port map (
+D => PLOL0_CNT_3(0),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL0_CNT(0));
+\GENBLK1.PLOL0_CNT[1]_REG_Z820\: FD1S3DX port map (
+D => PLOL0_CNT_3(1),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL0_CNT(1));
+\GENBLK1.PLOL0_CNT[2]_REG_Z822\: FD1S3DX port map (
+D => PLOL0_CNT_3(2),
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLOL0_CNT(2));
+\GENBLK1.PLL_LOL_P3_REG_Z824\: FD1S3DX port map (
+D => PLL_LOL_P2,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLL_LOL_P3);
+\GENBLK1.PLL_LOL_P2_REG_Z826\: FD1S3DX port map (
+D => PLL_LOL_P1,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLL_LOL_P2);
+\GENBLK1.PLL_LOL_P1_REG_Z828\: FD1S3DX port map (
+D => pll_lock_i,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => PLL_LOL_P1);
+\GENBLK1.GENBLK2.TXSR_APPD_REG_Z830\: FD1S3BX port map (
+D => TXSR_APPD_2,
+CK => pll_refclki,
+PD => rsl_rst,
+Q => TXSR_APPD);
+\GENBLK1.GENBLK2.TXR_WT_EN_REG_Z832\: FD1P3DX port map (
+D => UN1_DUAL_OR_SERD_RST_1_1,
+SP => UN1_DUAL_OR_SERD_RST_1_I,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_EN);
+\GENBLK1.GENBLK2.TXR_WT_CNT[0]_REG_Z834\: FD1P3DX port map (
+D => TXR_WT_CNT_S(0),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(0));
+\GENBLK1.GENBLK2.TXR_WT_CNT[1]_REG_Z836\: FD1P3DX port map (
+D => TXR_WT_CNT_S(1),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(1));
+\GENBLK1.GENBLK2.TXR_WT_CNT[2]_REG_Z838\: FD1P3DX port map (
+D => TXR_WT_CNT_S(2),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(2));
+\GENBLK1.GENBLK2.TXR_WT_CNT[3]_REG_Z840\: FD1P3DX port map (
+D => TXR_WT_CNT_S(3),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(3));
+\GENBLK1.GENBLK2.TXR_WT_CNT[4]_REG_Z842\: FD1P3DX port map (
+D => TXR_WT_CNT_S(4),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(4));
+\GENBLK1.GENBLK2.TXR_WT_CNT[5]_REG_Z844\: FD1P3DX port map (
+D => TXR_WT_CNT_S(5),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(5));
+\GENBLK1.GENBLK2.TXR_WT_CNT[6]_REG_Z846\: FD1P3DX port map (
+D => TXR_WT_CNT_S(6),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(6));
+\GENBLK1.GENBLK2.TXR_WT_CNT[7]_REG_Z848\: FD1P3DX port map (
+D => TXR_WT_CNT_S(7),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(7));
+\GENBLK1.GENBLK2.TXR_WT_CNT[8]_REG_Z850\: FD1P3DX port map (
+D => TXR_WT_CNT_S(8),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(8));
+\GENBLK1.GENBLK2.TXR_WT_CNT[9]_REG_Z852\: FD1P3DX port map (
+D => TXR_WT_CNT_S(9),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(9));
+\GENBLK1.GENBLK2.TXR_WT_CNT[10]_REG_Z854\: FD1P3DX port map (
+D => TXR_WT_CNT_S(10),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(10));
+\GENBLK1.GENBLK2.TXR_WT_CNT[11]_REG_Z856\: FD1P3DX port map (
+D => TXR_WT_CNT_S(11),
+SP => TXR_WT_CNTE,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXR_WT_CNT(11));
+\GENBLK1.GENBLK2.TXDPR_APPD_REG_Z858\: FD1P3DX port map (
+D => UN2_PLOL_FEDGE_2,
+SP => UN2_PLOL_FEDGE_3_I,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXDPR_APPD);
+\GENBLK1.GENBLK2.RUO_TX_RDYR_REG_Z860\: FD1P3DX port map (
+D => UN2_PLOL_FEDGE_5_1,
+SP => UN2_PLOL_FEDGE_5_I,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => RSL_TX_RDY_7);
+\GENBLK1.GENBLK2.MFOR[0].TXPR_APPD[0]_REG_Z862\: FD1P3DX port map (
+D => UN2_PLOL_FEDGE_2,
+SP => UN2_PLOL_FEDGE_8_I,
+CK => pll_refclki,
+CD => rsl_rst,
+Q => TXPR_APPD(0));
+\GENBLK1.TXS_CNT_RNO[0]\: LUT4 
+generic map(
+  init => X"A6A6"
+)
+port map (
+A => TXS_CNT(0),
+B => TXS_RST,
+C => UN1_PLOL_CNT_TC,
+D => VCC,
+Z => N_10_I);
+\GENBLK1.TXS_CNT_RNO[1]\: LUT4 
+generic map(
+  init => X"CC6C"
+)
+port map (
+A => TXS_CNT(0),
+B => TXS_CNT(1),
+C => TXS_RST,
+D => UN1_PLOL_CNT_TC,
+Z => TXS_CNT_RNO(1));
+\GENBLK2.RXP_RST2_RNO_0\: LUT4 
+generic map(
+  init => X"FFFE"
+)
+port map (
+A => RLOLS0_CNT_TC_1,
+B => RLOS_REDGE,
+C => RSL_RX_SERDES_RST_C_9,
+D => RSL_SERDES_RST_DUAL_C_10,
+Z => UN2_RLOS_REDGE_1_I);
+\GENBLK1.GENBLK2.TXR_WT_EN_RNO\: LUT4 
+generic map(
+  init => X"0F2F"
+)
+port map (
+A => TXPR_APPD(0),
+B => PLL_LOL_P2,
+C => UN1_DUAL_OR_SERD_RST_1_1,
+D => RSL_TX_RDY_7,
+Z => UN1_DUAL_OR_SERD_RST_1_I);
+\GENBLK2.WAIT_CALIB_RNIKRP81\: LUT4 
+generic map(
+  init => X"FFFE"
+)
+port map (
+A => RXS_RST,
+B => WAIT_CALIB,
+C => RLOL1_CNT_TC_1,
+D => RLOS_REDGE,
+Z => RLOL1_CNTE);
+\GENBLK2.RXS_RST6\: LUT4 
+generic map(
+  init => X"2020"
+)
+port map (
+A => RLOL_DB,
+B => RLOS_DB,
+C => RLOL1_CNT_TC_1,
+D => VCC,
+Z => RXS_RST6);
+\GENBLK2.WAITA_RLOLS0_RNI266C\: LUT4 
+generic map(
+  init => X"FEFE"
+)
+port map (
+A => RLOLS0_CNT11_0,
+B => WAITA_RLOLS0,
+C => RLOLS0_CNT_TC_1,
+D => VCC,
+Z => RLOLS0_CNTE);
+\GENBLK2.GENBLK3.RXR_WT_EN_RNI1B6E\: LUT4 
+generic map(
+  init => X"EEEE"
+)
+port map (
+A => RXR_WT_CNT9,
+B => RXR_WT_EN,
+C => VCC,
+D => VCC,
+Z => RXR_WT_CNTE);
+\GENBLK1.PLOL_CNT11_I\: LUT4 
+generic map(
+  init => X"0202"
+)
+port map (
+A => PLL_LOL_P2,
+B => UN1_PLOL_CNT_TC,
+C => RSL_TX_SERDES_RST_C_6,
+D => VCC,
+Z => \PLOL_CNT_\);
+\GENBLK2.RLOLS0_CNT11_I\: LUT4 
+generic map(
+  init => X"1111"
+)
+port map (
+A => RLOLS0_CNT11_0,
+B => RLOLS0_CNT_TC_1,
+C => VCC,
+D => VCC,
+Z => \RLOLS0_CNT_\);
+\GENBLK2.UN1_RXS_CNT_TC\: LUT4 
+generic map(
+  init => X"FEFC"
+)
+port map (
+A => RLOL_DB,
+B => RLOS_DB,
+C => UN8_RXS_CNT_TC,
+D => RLOL1_CNT_TC_1,
+Z => UN1_RXS_CNT_TC);
+\GENBLK2.WAIT_CALIB_RNO\: LUT4 
+generic map(
+  init => X"A3A3"
+)
+port map (
+A => RLOL_DB,
+B => RLOS_DB,
+C => RLOL1_CNT_TC_1,
+D => VCC,
+Z => WAIT_CALIB_RNO);
+\GENBLK1.GENBLK2.MFOR[0].TXPR_APPD_RNO[0]\: LUT4 
+generic map(
+  init => X"FEFA"
+)
+port map (
+A => DUAL_OR_SERD_RST,
+B => UN2_RDO_TX_PCS_RST_C,
+C => PLL_LOL_P2,
+D => TXSR_APPD_4,
+Z => UN2_PLOL_FEDGE_8_I);
+\GENBLK2.GENBLK3.RXR_WT_EN_RNO_0\: LUT4 
+generic map(
+  init => X"FFFB"
+)
+port map (
+A => UN17_RXR_WT_TC,
+B => UN1_DUAL_OR_RSERD_RST_2_0,
+C => RSL_RX_SERDES_RST_C_9,
+D => RSL_SERDES_RST_DUAL_C_10,
+Z => UN1_DUAL_OR_RSERD_RST_2_I);
+\GENBLK2.GENBLK3.LFOR[0].RXPR_APPD_RNO[0]\: LUT4 
+generic map(
+  init => X"FFB3"
+)
+port map (
+A => UN1_RXSDR_OR_SR_APPD_0,
+B => UN2_RDO_SERDES_RST_DUAL_C_2_0,
+C => RSL_RX_PCS_RST_C_5,
+D => RSL_RX_SERDES_RST_C_9,
+Z => UN2_RDO_SERDES_RST_DUAL_C_2_I);
+\GENBLK2.GENBLK3.RXDPR_APPD_RNO\: LUT4 
+generic map(
+  init => X"DDDD"
+)
+port map (
+A => UN1_RUI_RST_DUAL_C_1_1,
+B => rst_dual_c,
+C => VCC,
+D => VCC,
+Z => UN1_RUI_RST_DUAL_C_1_I);
+\GENBLK1.UN2_PLOL_CNT_TC\: LUT4 
+generic map(
+  init => X"F8F8"
+)
+port map (
+A => TXS_CNT(0),
+B => TXS_CNT(1),
+C => UN1_PLOL_CNT_TC,
+D => VCC,
+Z => UN2_PLOL_CNT_TC);
+\GENBLK1.GENBLK2.TXR_WT_EN_RNI1JHS\: LUT4 
+generic map(
+  init => X"EEEE"
+)
+port map (
+A => TXR_WT_CNT9,
+B => TXR_WT_EN,
+C => VCC,
+D => VCC,
+Z => TXR_WT_CNTE);
+\GENBLK2.GENBLK3.RXR_WT_CNT9\: LUT4 
+generic map(
+  init => X"FFFE"
+)
+port map (
+A => UN17_RXR_WT_TC,
+B => RLOL_DB,
+C => RLOS_DB,
+D => RX_ANY_RST,
+Z => RXR_WT_CNT9);
+\GENBLK2.UN1_RLOLS0_CNT_TC\: LUT4 
+generic map(
+  init => X"FEFE"
+)
+port map (
+A => RLOLS0_CNT11_0,
+B => WAITA_RLOLS06,
+C => RLOLS0_CNT_TC_1,
+D => VCC,
+Z => UN1_RLOLS0_CNT_TC);
+\GENBLK2.UN1_RLOS_FEDGE_1\: LUT4 
+generic map(
+  init => X"F6F6"
+)
+port map (
+A => RLOS_DB,
+B => RLOS_DB_P1,
+C => RLOL1_CNT_TC_1,
+D => VCC,
+Z => UN1_RLOS_FEDGE_1);
+\GENBLK1.GENBLK2.TXDPR_APPD_RNO\: LUT4 
+generic map(
+  init => X"FEFE"
+)
+port map (
+A => DUAL_OR_SERD_RST,
+B => PLL_LOL_P2,
+C => rst_dual_c,
+D => VCC,
+Z => UN2_PLOL_FEDGE_3_I);
+\GENBLK1.TXP_CNT_RNO[0]\: LUT4 
+generic map(
+  init => X"A6A6"
+)
+port map (
+A => TXP_CNT(0),
+B => TXP_RST,
+C => UN9_PLOL0_CNT_TC,
+D => VCC,
+Z => N_11_I);
+\GENBLK1.TXP_CNT_RNO[1]\: LUT4 
+generic map(
+  init => X"CC6C"
+)
+port map (
+A => TXP_CNT(0),
+B => TXP_CNT(1),
+C => TXP_RST,
+D => UN9_PLOL0_CNT_TC,
+Z => TXP_CNT_RNO(1));
+UN3_RX_ALL_WELL_2_Z887: LUT4 
+generic map(
+  init => X"0101"
+)
+port map (
+A => RLOL_DB,
+B => RLOS_DB,
+C => RX_ANY_RST,
+D => VCC,
+Z => UN3_RX_ALL_WELL_2);
+\GENBLK1.GENBLK2.TXR_WT_CNT9\: LUT4 
+generic map(
+  init => X"FFFE"
+)
+port map (
+A => DUAL_OR_SERD_RST,
+B => UN18_TXR_WT_TC,
+C => RSL_TX_PCS_RST_C_4,
+D => rst_dual_c,
+Z => TXR_WT_CNT9);
+UN2_PLOL_FEDGE_5_1_Z889: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => DUAL_OR_SERD_RST,
+B => PLL_LOL_P2,
+C => RSL_TX_PCS_RST_C_4,
+D => rst_dual_c,
+Z => UN2_PLOL_FEDGE_5_1);
+RLOLS0_CNT_TC_1_Z890: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RLOLS0_CNT_TC_1_10,
+B => RLOLS0_CNT_TC_1_11,
+C => RLOLS0_CNT_TC_1_12,
+D => RLOLS0_CNT_TC_1_13,
+Z => RLOLS0_CNT_TC_1);
+RLOL1_CNT_TC_1_Z891: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RLOL1_CNT_TC_1_11,
+B => RLOL1_CNT_TC_1_12,
+C => RLOL1_CNT_TC_1_13,
+D => RLOL1_CNT_TC_1_14,
+Z => RLOL1_CNT_TC_1);
+\GENBLK1.UN1_PLOL_CNT_TC\: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => UN1_PLOL_CNT_TC_11,
+B => UN1_PLOL_CNT_TC_12,
+C => UN1_PLOL_CNT_TC_13,
+D => UN1_PLOL_CNT_TC_14,
+Z => UN1_PLOL_CNT_TC);
+\UN1_GENBLK2.RLOL_DB_CNT_AXB_0\: LUT4 
+generic map(
+  init => X"9999"
+)
+port map (
+A => RLOL_DB_CNT(0),
+B => UN1_RLOL_DB_CNT_ZERO(0),
+C => VCC,
+D => VCC,
+Z => RLOL_DB_CNT_AXB_0);
+\UN1_GENBLK2.RLOS_DB_CNT_AXB_0\: LUT4 
+generic map(
+  init => X"9999"
+)
+port map (
+A => RLOS_DB_CNT(0),
+B => UN1_RLOS_DB_CNT_ZERO(0),
+C => VCC,
+D => VCC,
+Z => RLOS_DB_CNT_AXB_0);
+\GENBLK1.WAITA_PLOL0_RNO\: LUT4 
+generic map(
+  init => X"F6F6"
+)
+port map (
+A => PLL_LOL_P2,
+B => PLL_LOL_P3,
+C => UN9_PLOL0_CNT_TC,
+D => VCC,
+Z => UN1_PLOL0_CNT_TC_1_I);
+\GENBLK1.PLOL0_CNT_3[2]\: LUT4 
+generic map(
+  init => X"1320"
+)
+port map (
+A => CO0_2,
+B => PLOL0_CNT9,
+C => PLOL0_CNT(1),
+D => PLOL0_CNT(2),
+Z => PLOL0_CNT_3(2));
+\GENBLK1.PLOL0_CNT_3[0]\: LUT4 
+generic map(
+  init => X"1414"
+)
+port map (
+A => PLOL0_CNT9,
+B => PLOL0_CNT(0),
+C => WAITA_PLOL0,
+D => VCC,
+Z => PLOL0_CNT_3(0));
+UN1_RUI_RST_DUAL_C_1_1_Z898: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RLOL_DB,
+B => RLOS_DB,
+C => RSL_RX_SERDES_RST_C_9,
+D => RSL_SERDES_RST_DUAL_C_10,
+Z => UN1_RUI_RST_DUAL_C_1_1);
+UN2_RDO_SERDES_RST_DUAL_C_1_Z899: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RSL_RX_SERDES_RST_C_9,
+B => RSL_SERDES_RST_DUAL_C_10,
+C => rx_cdr_lol_s,
+D => rx_los_low_s,
+Z => UN2_RDO_SERDES_RST_DUAL_C_1);
+\GENBLK1.GENBLK2.TXSR_APPD_2\: LUT4 
+generic map(
+  init => X"EEEE"
+)
+port map (
+A => DUAL_OR_SERD_RST,
+B => TXSR_APPD_4,
+C => VCC,
+D => VCC,
+Z => TXSR_APPD_2);
+\GENBLK1.GENBLK2.UN18_TXR_WT_TC\: LUT4 
+generic map(
+  init => X"8080"
+)
+port map (
+A => UN18_TXR_WT_TC_6,
+B => UN18_TXR_WT_TC_7,
+C => UN18_TXR_WT_TC_8,
+D => VCC,
+Z => UN18_TXR_WT_TC);
+UN2_PLOL_FEDGE_2_Z902: LUT4 
+generic map(
+  init => X"0101"
+)
+port map (
+A => PLL_LOL_P2,
+B => RSL_SERDES_RST_DUAL_C_10,
+C => RSL_TX_SERDES_RST_C_6,
+D => VCC,
+Z => UN2_PLOL_FEDGE_2);
+RX_ANY_RST_Z903: LUT4 
+generic map(
+  init => X"FFFE"
+)
+port map (
+A => RSL_RX_PCS_RST_C_5,
+B => RSL_RX_SERDES_RST_C_9,
+C => RSL_SERDES_RST_DUAL_C_10,
+D => rst_dual_c,
+Z => RX_ANY_RST);
+\GENBLK2.GENBLK3.UN17_RXR_WT_TC\: LUT4 
+generic map(
+  init => X"8080"
+)
+port map (
+A => UN17_RXR_WT_TC_6,
+B => UN17_RXR_WT_TC_7,
+C => UN17_RXR_WT_TC_8,
+D => VCC,
+Z => UN17_RXR_WT_TC);
+\UN1_RLOL_DB_CNT_ZERO_BM[0]_Z905\: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RLOL_DB_CNT(0),
+B => RLOL_DB_CNT(1),
+C => RLOL_DB_CNT(2),
+D => RLOL_DB_CNT(3),
+Z => UN1_RLOL_DB_CNT_ZERO_BM(0));
+\UN1_RLOL_DB_CNT_ZERO[0]_Z906\: PFUMX port map (
+ALUT => UN1_RLOL_DB_CNT_ZERO_BM(0),
+BLUT => UN1_RLOL_DB_CNT_ZERO_AM(0),
+C0 => RLOL_P2,
+Z => UN1_RLOL_DB_CNT_ZERO(0));
+\UN1_RLOS_DB_CNT_ZERO_BM[0]_Z907\: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RLOS_DB_CNT(0),
+B => RLOS_DB_CNT(1),
+C => RLOS_DB_CNT(2),
+D => RLOS_DB_CNT(3),
+Z => UN1_RLOS_DB_CNT_ZERO_BM(0));
+\UN1_RLOS_DB_CNT_ZERO[0]_Z908\: PFUMX port map (
+ALUT => UN1_RLOS_DB_CNT_ZERO_BM(0),
+BLUT => UN1_RLOS_DB_CNT_ZERO_AM(0),
+C0 => RLOS_P2,
+Z => UN1_RLOS_DB_CNT_ZERO(0));
+\RXS_CNT_3[1]_Z909\: LUT4 
+generic map(
+  init => X"6464"
+)
+port map (
+A => RXS_CNT(0),
+B => RXS_CNT(1),
+C => RXS_RST,
+D => VCC,
+Z => RXS_CNT_3(1));
+\GENBLK1.UN1_PLOL0_CNT_TC_1\: LUT4 
+generic map(
+  init => X"F8F8"
+)
+port map (
+A => TXP_CNT(0),
+B => TXP_CNT(1),
+C => UN9_PLOL0_CNT_TC,
+D => VCC,
+Z => UN1_PLOL0_CNT_TC_1);
+\GENBLK2.UN1_RLOL_DB_CNT_MAX\: LUT4 
+generic map(
+  init => X"8001"
+)
+port map (
+A => RLOL_DB_CNT(0),
+B => RLOL_DB_CNT(1),
+C => RLOL_DB_CNT(2),
+D => RLOL_DB_CNT(3),
+Z => UN1_RLOL_DB_CNT_MAX);
+\GENBLK2.UN1_RLOS_DB_CNT_MAX\: LUT4 
+generic map(
+  init => X"8001"
+)
+port map (
+A => RLOS_DB_CNT(0),
+B => RLOS_DB_CNT(1),
+C => RLOS_DB_CNT(2),
+D => RLOS_DB_CNT(3),
+Z => UN1_RLOS_DB_CNT_MAX);
+\GENBLK2.WAITA_RLOLS06\: LUT4 
+generic map(
+  init => X"0504"
+)
+port map (
+A => RLOL_DB,
+B => RLOL_DB_P1,
+C => RLOS_DB,
+D => RLOS_DB_P1,
+Z => WAITA_RLOLS06);
+RLOLS0_CNT_TC_1_13_Z914: LUT4 
+generic map(
+  init => X"1010"
+)
+port map (
+A => RLOLS0_CNT(16),
+B => RLOLS0_CNT(17),
+C => RLOLS0_CNT_TC_1_9,
+D => VCC,
+Z => RLOLS0_CNT_TC_1_13);
+\GENBLK1.UN1_PLOL_CNT_TC_14\: LUT4 
+generic map(
+  init => X"0100"
+)
+port map (
+A => PLOL_CNT(5),
+B => PLOL_CNT(10),
+C => PLOL_CNT(18),
+D => UN1_PLOL_CNT_TC_10,
+Z => UN1_PLOL_CNT_TC_14);
+RLOL1_CNT_TC_1_14_Z916: LUT4 
+generic map(
+  init => X"0100"
+)
+port map (
+A => RLOL1_CNT(12),
+B => RLOL1_CNT(13),
+C => RLOL1_CNT(18),
+D => RLOL1_CNT_TC_1_10,
+Z => RLOL1_CNT_TC_1_14);
+UN2_RDO_SERDES_RST_DUAL_C_2_0_Z917: LUT4 
+generic map(
+  init => X"0101"
+)
+port map (
+A => RSL_SERDES_RST_DUAL_C_10,
+B => rx_cdr_lol_s,
+C => rx_los_low_s,
+D => VCC,
+Z => UN2_RDO_SERDES_RST_DUAL_C_2_0);
+UN1_DUAL_OR_RSERD_RST_2_0_Z918: LUT4 
+generic map(
+  init => X"0101"
+)
+port map (
+A => UN3_RX_ALL_WELL_2_1,
+B => RLOL_DB,
+C => RLOS_DB,
+D => VCC,
+Z => UN1_DUAL_OR_RSERD_RST_2_0);
+\RXS_CNT_3[0]_Z919\: LUT4 
+generic map(
+  init => X"5252"
+)
+port map (
+A => RXS_CNT(0),
+B => RXS_CNT(1),
+C => RXS_RST,
+D => VCC,
+Z => RXS_CNT_3(0));
+\RDO_RX_SERDES_RST_C_1[0]\: LUT4 
+generic map(
+  init => X"F4F4"
+)
+port map (
+A => rsl_disable,
+B => RXS_RST,
+C => rx_serdes_rst_c,
+D => VCC,
+Z => RSL_RX_SERDES_RST_C_9);
+\RDO_TX_PCS_RST_C_1[0]\: LUT4 
+generic map(
+  init => X"F4F4"
+)
+port map (
+A => rsl_disable,
+B => TXP_RST,
+C => tx_pcs_rst_c,
+D => VCC,
+Z => RSL_TX_PCS_RST_C_4);
+RDO_TX_SERDES_RST_C: LUT4 
+generic map(
+  init => X"F4F4"
+)
+port map (
+A => rsl_disable,
+B => TXS_RST,
+C => tx_serdes_rst_c,
+D => VCC,
+Z => RSL_TX_SERDES_RST_C_6);
+RDO_SERDES_RST_DUAL_C: LUT4 
+generic map(
+  init => X"F4F4"
+)
+port map (
+A => rsl_disable,
+B => rsl_rst,
+C => serdes_rst_dual_c,
+D => VCC,
+Z => RSL_SERDES_RST_DUAL_C_10);
+\GENBLK2.GENBLK3.UN3_RX_ALL_WELL_2_1\: LUT4 
+generic map(
+  init => X"0E0E"
+)
+port map (
+A => RXPR_APPD(0),
+B => RXDPR_APPD,
+C => RSL_RX_RDY_8,
+D => VCC,
+Z => UN3_RX_ALL_WELL_2_1);
+\RDO_RX_PCS_RST_C_1[0]\: LUT4 
+generic map(
+  init => X"F4F4"
+)
+port map (
+A => rsl_disable,
+B => RXP_RST2,
+C => rx_pcs_rst_c,
+D => VCC,
+Z => RSL_RX_PCS_RST_C_5);
+\GENBLK1.UN9_PLOL0_CNT_TC\: LUT4 
+generic map(
+  init => X"1010"
+)
+port map (
+A => PLOL0_CNT(0),
+B => PLOL0_CNT(1),
+C => PLOL0_CNT(2),
+D => VCC,
+Z => UN9_PLOL0_CNT_TC);
+\GENBLK2.GENBLK3.LFOR[0].UN1_RXSDR_OR_SR_APPD_0\: LUT4 
+generic map(
+  init => X"FCA8"
+)
+port map (
+A => RXSR_APPD(0),
+B => RLOL_DB,
+C => RLOS_DB,
+D => RXSDR_APPD_4,
+Z => UN1_RXSDR_OR_SR_APPD_0);
+\GENBLK1.GENBLK2.UN18_TXR_WT_TC_6\: LUT4 
+generic map(
+  init => X"4000"
+)
+port map (
+A => TXR_WT_CNT(0),
+B => TXR_WT_CNT(8),
+C => TXR_WT_CNT(9),
+D => TXR_WT_CNT(11),
+Z => UN18_TXR_WT_TC_6);
+\GENBLK1.GENBLK2.UN18_TXR_WT_TC_7\: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => TXR_WT_CNT(3),
+B => TXR_WT_CNT(4),
+C => TXR_WT_CNT(5),
+D => TXR_WT_CNT(7),
+Z => UN18_TXR_WT_TC_7);
+\GENBLK1.GENBLK2.UN18_TXR_WT_TC_8\: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => TXR_WT_CNT(1),
+B => TXR_WT_CNT(2),
+C => TXR_WT_CNT(6),
+D => TXR_WT_CNT(10),
+Z => UN18_TXR_WT_TC_8);
+\GENBLK2.GENBLK3.UN17_RXR_WT_TC_6\: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RXR_WT_CNT(3),
+B => RXR_WT_CNT(4),
+C => RXR_WT_CNT(5),
+D => RXR_WT_CNT(7),
+Z => UN17_RXR_WT_TC_6);
+\GENBLK2.GENBLK3.UN17_RXR_WT_TC_7\: LUT4 
+generic map(
+  init => X"4000"
+)
+port map (
+A => RXR_WT_CNT(0),
+B => RXR_WT_CNT(8),
+C => RXR_WT_CNT(9),
+D => RXR_WT_CNT(11),
+Z => UN17_RXR_WT_TC_7);
+\GENBLK2.GENBLK3.UN17_RXR_WT_TC_8\: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RXR_WT_CNT(1),
+B => RXR_WT_CNT(2),
+C => RXR_WT_CNT(6),
+D => RXR_WT_CNT(10),
+Z => UN17_RXR_WT_TC_8);
+RLOLS0_CNT_TC_1_9_Z934: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RLOLS0_CNT(9),
+B => RLOLS0_CNT(11),
+C => RLOLS0_CNT(12),
+D => RLOLS0_CNT(13),
+Z => RLOLS0_CNT_TC_1_9);
+RLOLS0_CNT_TC_1_10_Z935: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RLOLS0_CNT(5),
+B => RLOLS0_CNT(6),
+C => RLOLS0_CNT(7),
+D => RLOLS0_CNT(8),
+Z => RLOLS0_CNT_TC_1_10);
+RLOLS0_CNT_TC_1_11_Z936: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RLOLS0_CNT(1),
+B => RLOLS0_CNT(2),
+C => RLOLS0_CNT(3),
+D => RLOLS0_CNT(4),
+Z => RLOLS0_CNT_TC_1_11);
+RLOLS0_CNT_TC_1_12_Z937: LUT4 
+generic map(
+  init => X"4000"
+)
+port map (
+A => RLOLS0_CNT(0),
+B => RLOLS0_CNT(10),
+C => RLOLS0_CNT(14),
+D => RLOLS0_CNT(15),
+Z => RLOLS0_CNT_TC_1_12);
+\GENBLK1.UN1_PLOL_CNT_TC_10\: LUT4 
+generic map(
+  init => X"0080"
+)
+port map (
+A => PLOL_CNT(1),
+B => PLOL_CNT(6),
+C => PLOL_CNT(7),
+D => PLOL_CNT(12),
+Z => UN1_PLOL_CNT_TC_10);
+\GENBLK1.UN1_PLOL_CNT_TC_11\: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => PLOL_CNT(8),
+B => PLOL_CNT(9),
+C => PLOL_CNT(11),
+D => PLOL_CNT(13),
+Z => UN1_PLOL_CNT_TC_11);
+\GENBLK1.UN1_PLOL_CNT_TC_12\: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => PLOL_CNT(14),
+B => PLOL_CNT(15),
+C => PLOL_CNT(16),
+D => PLOL_CNT(17),
+Z => UN1_PLOL_CNT_TC_12);
+\GENBLK1.UN1_PLOL_CNT_TC_13\: LUT4 
+generic map(
+  init => X"0100"
+)
+port map (
+A => PLOL_CNT(2),
+B => PLOL_CNT(3),
+C => PLOL_CNT(4),
+D => PLOL_CNT(19),
+Z => UN1_PLOL_CNT_TC_13);
+RLOL1_CNT_TC_1_10_Z942: LUT4 
+generic map(
+  init => X"0800"
+)
+port map (
+A => RLOL1_CNT(14),
+B => RLOL1_CNT(15),
+C => RLOL1_CNT(16),
+D => RLOL1_CNT(17),
+Z => RLOL1_CNT_TC_1_10);
+RLOL1_CNT_TC_1_11_Z943: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RLOL1_CNT(0),
+B => RLOL1_CNT(1),
+C => RLOL1_CNT(2),
+D => RLOL1_CNT(3),
+Z => RLOL1_CNT_TC_1_11);
+RLOL1_CNT_TC_1_12_Z944: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RLOL1_CNT(4),
+B => RLOL1_CNT(5),
+C => RLOL1_CNT(6),
+D => RLOL1_CNT(7),
+Z => RLOL1_CNT_TC_1_12);
+RLOL1_CNT_TC_1_13_Z945: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RLOL1_CNT(8),
+B => RLOL1_CNT(9),
+C => RLOL1_CNT(10),
+D => RLOL1_CNT(11),
+Z => RLOL1_CNT_TC_1_13);
+\GENBLK1.PLOL0_CNT_3_RNO[2]\: LUT4 
+generic map(
+  init => X"8888"
+)
+port map (
+A => PLOL0_CNT(0),
+B => WAITA_PLOL0,
+C => VCC,
+D => VCC,
+Z => CO0_2);
+PLOL_FEDGE_Z947: LUT4 
+generic map(
+  init => X"4444"
+)
+port map (
+A => PLL_LOL_P2,
+B => PLL_LOL_P3,
+C => VCC,
+D => VCC,
+Z => PLOL_FEDGE);
+\GENBLK2.UN8_RXS_CNT_TC\: LUT4 
+generic map(
+  init => X"8888"
+)
+port map (
+A => RXS_CNT(0),
+B => RXS_CNT(1),
+C => VCC,
+D => VCC,
+Z => UN8_RXS_CNT_TC);
+RLOS_REDGE_Z949: LUT4 
+generic map(
+  init => X"2222"
+)
+port map (
+A => RLOS_DB,
+B => RLOS_DB_P1,
+C => VCC,
+D => VCC,
+Z => RLOS_REDGE);
+\GENBLK2.GENBLK3.RXSDR_APPD_2\: LUT4 
+generic map(
+  init => X"EEEE"
+)
+port map (
+A => RXSDR_APPD_4,
+B => serdes_rst_dual_c,
+C => VCC,
+D => VCC,
+Z => RXSDR_APPD_2);
+\UN1_RLOS_DB_CNT_ZERO_AM[0]_Z951\: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RLOS_DB_CNT(0),
+B => RLOS_DB_CNT(1),
+C => RLOS_DB_CNT(2),
+D => RLOS_DB_CNT(3),
+Z => UN1_RLOS_DB_CNT_ZERO_AM(0));
+\UN1_RLOL_DB_CNT_ZERO_AM[0]_Z952\: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RLOL_DB_CNT(0),
+B => RLOL_DB_CNT(1),
+C => RLOL_DB_CNT(2),
+D => RLOL_DB_CNT(3),
+Z => UN1_RLOL_DB_CNT_ZERO_AM(0));
+DUAL_OR_SERD_RST_Z953: LUT4 
+generic map(
+  init => X"EEFE"
+)
+port map (
+A => RSL_SERDES_RST_DUAL_C_10,
+B => tx_serdes_rst_c,
+C => TXS_RST,
+D => rsl_disable,
+Z => DUAL_OR_SERD_RST);
+\GENBLK1.PLOL0_CNT9\: LUT4 
+generic map(
+  init => X"AAAE"
+)
+port map (
+A => PLL_LOL_P2,
+B => PLOL0_CNT(2),
+C => PLOL0_CNT(1),
+D => PLOL0_CNT(0),
+Z => PLOL0_CNT9);
+\GENBLK2.RLOLS0_CNT11_0\: LUT4 
+generic map(
+  init => X"4F44"
+)
+port map (
+A => RLOL_DB_P1,
+B => RLOL_DB,
+C => RLOS_DB_P1,
+D => RLOS_DB,
+Z => RLOLS0_CNT11_0);
+\GENBLK2.RLOL1_CNT_CRY_0[0]\: CCU2C 
+generic map(
+  INIT0 => X"500c",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => \RLOL1_CNT_\,
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_7,
+COUT => RLOL1_CNT_CRY(0),
+S0 => RLOL1_CNT_CRY_0_S0(0),
+S1 => RLOL1_CNT_S(0));
+\GENBLK2.RLOL1_CNT_CRY_0[1]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOL1_CNT_\,
+B0 => RLOL1_CNT(1),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(2),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL1_CNT_CRY(0),
+COUT => RLOL1_CNT_CRY(2),
+S0 => RLOL1_CNT_S(1),
+S1 => RLOL1_CNT_S(2));
+\GENBLK2.RLOL1_CNT_CRY_0[3]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOL1_CNT_\,
+B0 => RLOL1_CNT(3),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(4),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL1_CNT_CRY(2),
+COUT => RLOL1_CNT_CRY(4),
+S0 => RLOL1_CNT_S(3),
+S1 => RLOL1_CNT_S(4));
+\GENBLK2.RLOL1_CNT_CRY_0[5]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOL1_CNT_\,
+B0 => RLOL1_CNT(5),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(6),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL1_CNT_CRY(4),
+COUT => RLOL1_CNT_CRY(6),
+S0 => RLOL1_CNT_S(5),
+S1 => RLOL1_CNT_S(6));
+\GENBLK2.RLOL1_CNT_CRY_0[7]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOL1_CNT_\,
+B0 => RLOL1_CNT(7),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(8),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL1_CNT_CRY(6),
+COUT => RLOL1_CNT_CRY(8),
+S0 => RLOL1_CNT_S(7),
+S1 => RLOL1_CNT_S(8));
+\GENBLK2.RLOL1_CNT_CRY_0[9]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOL1_CNT_\,
+B0 => RLOL1_CNT(9),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(10),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL1_CNT_CRY(8),
+COUT => RLOL1_CNT_CRY(10),
+S0 => RLOL1_CNT_S(9),
+S1 => RLOL1_CNT_S(10));
+\GENBLK2.RLOL1_CNT_CRY_0[11]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOL1_CNT_\,
+B0 => RLOL1_CNT(11),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(12),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL1_CNT_CRY(10),
+COUT => RLOL1_CNT_CRY(12),
+S0 => RLOL1_CNT_S(11),
+S1 => RLOL1_CNT_S(12));
+\GENBLK2.RLOL1_CNT_CRY_0[13]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOL1_CNT_\,
+B0 => RLOL1_CNT(13),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(14),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL1_CNT_CRY(12),
+COUT => RLOL1_CNT_CRY(14),
+S0 => RLOL1_CNT_S(13),
+S1 => RLOL1_CNT_S(14));
+\GENBLK2.RLOL1_CNT_CRY_0[15]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOL1_CNT_\,
+B0 => RLOL1_CNT(15),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(16),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL1_CNT_CRY(14),
+COUT => RLOL1_CNT_CRY(16),
+S0 => RLOL1_CNT_S(15),
+S1 => RLOL1_CNT_S(16));
+\GENBLK2.RLOL1_CNT_CRY_0[17]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"800a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOL1_CNT_\,
+B0 => RLOL1_CNT(17),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOL1_CNT_\,
+B1 => RLOL1_CNT(18),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL1_CNT_CRY(16),
+COUT => RLOL1_CNT_CRY_0_COUT(17),
+S0 => RLOL1_CNT_S(17),
+S1 => RLOL1_CNT_S(18));
+\GENBLK2.RLOLS0_CNT_CRY_0[0]\: CCU2C 
+generic map(
+  INIT0 => X"500c",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => \RLOLS0_CNT_\,
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOLS0_CNT_\,
+B1 => RLOLS0_CNT(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_6,
+COUT => RLOLS0_CNT_CRY(0),
+S0 => RLOLS0_CNT_CRY_0_S0(0),
+S1 => RLOLS0_CNT_S(0));
+\GENBLK2.RLOLS0_CNT_CRY_0[1]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOLS0_CNT_\,
+B0 => RLOLS0_CNT(1),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOLS0_CNT_\,
+B1 => RLOLS0_CNT(2),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOLS0_CNT_CRY(0),
+COUT => RLOLS0_CNT_CRY(2),
+S0 => RLOLS0_CNT_S(1),
+S1 => RLOLS0_CNT_S(2));
+\GENBLK2.RLOLS0_CNT_CRY_0[3]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOLS0_CNT_\,
+B0 => RLOLS0_CNT(3),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOLS0_CNT_\,
+B1 => RLOLS0_CNT(4),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOLS0_CNT_CRY(2),
+COUT => RLOLS0_CNT_CRY(4),
+S0 => RLOLS0_CNT_S(3),
+S1 => RLOLS0_CNT_S(4));
+\GENBLK2.RLOLS0_CNT_CRY_0[5]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOLS0_CNT_\,
+B0 => RLOLS0_CNT(5),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOLS0_CNT_\,
+B1 => RLOLS0_CNT(6),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOLS0_CNT_CRY(4),
+COUT => RLOLS0_CNT_CRY(6),
+S0 => RLOLS0_CNT_S(5),
+S1 => RLOLS0_CNT_S(6));
+\GENBLK2.RLOLS0_CNT_CRY_0[7]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOLS0_CNT_\,
+B0 => RLOLS0_CNT(7),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOLS0_CNT_\,
+B1 => RLOLS0_CNT(8),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOLS0_CNT_CRY(6),
+COUT => RLOLS0_CNT_CRY(8),
+S0 => RLOLS0_CNT_S(7),
+S1 => RLOLS0_CNT_S(8));
+\GENBLK2.RLOLS0_CNT_CRY_0[9]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOLS0_CNT_\,
+B0 => RLOLS0_CNT(9),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOLS0_CNT_\,
+B1 => RLOLS0_CNT(10),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOLS0_CNT_CRY(8),
+COUT => RLOLS0_CNT_CRY(10),
+S0 => RLOLS0_CNT_S(9),
+S1 => RLOLS0_CNT_S(10));
+\GENBLK2.RLOLS0_CNT_CRY_0[11]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOLS0_CNT_\,
+B0 => RLOLS0_CNT(11),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOLS0_CNT_\,
+B1 => RLOLS0_CNT(12),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOLS0_CNT_CRY(10),
+COUT => RLOLS0_CNT_CRY(12),
+S0 => RLOLS0_CNT_S(11),
+S1 => RLOLS0_CNT_S(12));
+\GENBLK2.RLOLS0_CNT_CRY_0[13]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOLS0_CNT_\,
+B0 => RLOLS0_CNT(13),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOLS0_CNT_\,
+B1 => RLOLS0_CNT(14),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOLS0_CNT_CRY(12),
+COUT => RLOLS0_CNT_CRY(14),
+S0 => RLOLS0_CNT_S(13),
+S1 => RLOLS0_CNT_S(14));
+\GENBLK2.RLOLS0_CNT_CRY_0[15]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOLS0_CNT_\,
+B0 => RLOLS0_CNT(15),
+C0 => VCC,
+D0 => VCC,
+A1 => \RLOLS0_CNT_\,
+B1 => RLOLS0_CNT(16),
+C1 => VCC,
+D1 => VCC,
+CIN => RLOLS0_CNT_CRY(14),
+COUT => RLOLS0_CNT_CRY(16),
+S0 => RLOLS0_CNT_S(15),
+S1 => RLOLS0_CNT_S(16));
+\GENBLK2.RLOLS0_CNT_S_0[17]\: CCU2C 
+generic map(
+  INIT0 => X"800a",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \RLOLS0_CNT_\,
+B0 => RLOLS0_CNT(17),
+C0 => VCC,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => RLOLS0_CNT_CRY(16),
+COUT => RLOLS0_CNT_S_0_COUT(17),
+S0 => RLOLS0_CNT_S(17),
+S1 => RLOLS0_CNT_S_0_S1(17));
+\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[0]\: CCU2C 
+generic map(
+  INIT0 => X"5003",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => TXR_WT_CNT9,
+C0 => VCC,
+D0 => VCC,
+A1 => TXR_WT_CNT9,
+B1 => TXR_WT_CNT(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_5,
+COUT => TXR_WT_CNT_CRY(0),
+S0 => TXR_WT_CNT_CRY_0_S0(0),
+S1 => TXR_WT_CNT_S(0));
+\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[1]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => TXR_WT_CNT9,
+B0 => TXR_WT_CNT(1),
+C0 => VCC,
+D0 => VCC,
+A1 => TXR_WT_CNT9,
+B1 => TXR_WT_CNT(2),
+C1 => VCC,
+D1 => VCC,
+CIN => TXR_WT_CNT_CRY(0),
+COUT => TXR_WT_CNT_CRY(2),
+S0 => TXR_WT_CNT_S(1),
+S1 => TXR_WT_CNT_S(2));
+\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[3]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => TXR_WT_CNT9,
+B0 => TXR_WT_CNT(3),
+C0 => VCC,
+D0 => VCC,
+A1 => TXR_WT_CNT9,
+B1 => TXR_WT_CNT(4),
+C1 => VCC,
+D1 => VCC,
+CIN => TXR_WT_CNT_CRY(2),
+COUT => TXR_WT_CNT_CRY(4),
+S0 => TXR_WT_CNT_S(3),
+S1 => TXR_WT_CNT_S(4));
+\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[5]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => TXR_WT_CNT9,
+B0 => TXR_WT_CNT(5),
+C0 => VCC,
+D0 => VCC,
+A1 => TXR_WT_CNT9,
+B1 => TXR_WT_CNT(6),
+C1 => VCC,
+D1 => VCC,
+CIN => TXR_WT_CNT_CRY(4),
+COUT => TXR_WT_CNT_CRY(6),
+S0 => TXR_WT_CNT_S(5),
+S1 => TXR_WT_CNT_S(6));
+\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[7]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => TXR_WT_CNT9,
+B0 => TXR_WT_CNT(7),
+C0 => VCC,
+D0 => VCC,
+A1 => TXR_WT_CNT9,
+B1 => TXR_WT_CNT(8),
+C1 => VCC,
+D1 => VCC,
+CIN => TXR_WT_CNT_CRY(6),
+COUT => TXR_WT_CNT_CRY(8),
+S0 => TXR_WT_CNT_S(7),
+S1 => TXR_WT_CNT_S(8));
+\GENBLK1.GENBLK2.TXR_WT_CNT_CRY_0[9]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => TXR_WT_CNT9,
+B0 => TXR_WT_CNT(9),
+C0 => VCC,
+D0 => VCC,
+A1 => TXR_WT_CNT9,
+B1 => TXR_WT_CNT(10),
+C1 => VCC,
+D1 => VCC,
+CIN => TXR_WT_CNT_CRY(8),
+COUT => TXR_WT_CNT_CRY(10),
+S0 => TXR_WT_CNT_S(9),
+S1 => TXR_WT_CNT_S(10));
+\GENBLK1.GENBLK2.TXR_WT_CNT_S_0[11]\: CCU2C 
+generic map(
+  INIT0 => X"4005",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => TXR_WT_CNT9,
+B0 => TXR_WT_CNT(11),
+C0 => VCC,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => TXR_WT_CNT_CRY(10),
+COUT => TXR_WT_CNT_S_0_COUT(11),
+S0 => TXR_WT_CNT_S(11),
+S1 => TXR_WT_CNT_S_0_S1(11));
+\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[0]\: CCU2C 
+generic map(
+  INIT0 => X"5003",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => RXR_WT_CNT9,
+C0 => VCC,
+D0 => VCC,
+A1 => RXR_WT_CNT9,
+B1 => RXR_WT_CNT(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_4,
+COUT => RXR_WT_CNT_CRY(0),
+S0 => RXR_WT_CNT_CRY_0_S0(0),
+S1 => RXR_WT_CNT_S(0));
+\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[1]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => RXR_WT_CNT9,
+B0 => RXR_WT_CNT(1),
+C0 => VCC,
+D0 => VCC,
+A1 => RXR_WT_CNT9,
+B1 => RXR_WT_CNT(2),
+C1 => VCC,
+D1 => VCC,
+CIN => RXR_WT_CNT_CRY(0),
+COUT => RXR_WT_CNT_CRY(2),
+S0 => RXR_WT_CNT_S(1),
+S1 => RXR_WT_CNT_S(2));
+\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[3]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => RXR_WT_CNT9,
+B0 => RXR_WT_CNT(3),
+C0 => VCC,
+D0 => VCC,
+A1 => RXR_WT_CNT9,
+B1 => RXR_WT_CNT(4),
+C1 => VCC,
+D1 => VCC,
+CIN => RXR_WT_CNT_CRY(2),
+COUT => RXR_WT_CNT_CRY(4),
+S0 => RXR_WT_CNT_S(3),
+S1 => RXR_WT_CNT_S(4));
+\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[5]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => RXR_WT_CNT9,
+B0 => RXR_WT_CNT(5),
+C0 => VCC,
+D0 => VCC,
+A1 => RXR_WT_CNT9,
+B1 => RXR_WT_CNT(6),
+C1 => VCC,
+D1 => VCC,
+CIN => RXR_WT_CNT_CRY(4),
+COUT => RXR_WT_CNT_CRY(6),
+S0 => RXR_WT_CNT_S(5),
+S1 => RXR_WT_CNT_S(6));
+\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[7]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => RXR_WT_CNT9,
+B0 => RXR_WT_CNT(7),
+C0 => VCC,
+D0 => VCC,
+A1 => RXR_WT_CNT9,
+B1 => RXR_WT_CNT(8),
+C1 => VCC,
+D1 => VCC,
+CIN => RXR_WT_CNT_CRY(6),
+COUT => RXR_WT_CNT_CRY(8),
+S0 => RXR_WT_CNT_S(7),
+S1 => RXR_WT_CNT_S(8));
+\GENBLK2.GENBLK3.RXR_WT_CNT_CRY_0[9]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => RXR_WT_CNT9,
+B0 => RXR_WT_CNT(9),
+C0 => VCC,
+D0 => VCC,
+A1 => RXR_WT_CNT9,
+B1 => RXR_WT_CNT(10),
+C1 => VCC,
+D1 => VCC,
+CIN => RXR_WT_CNT_CRY(8),
+COUT => RXR_WT_CNT_CRY(10),
+S0 => RXR_WT_CNT_S(9),
+S1 => RXR_WT_CNT_S(10));
+\GENBLK2.GENBLK3.RXR_WT_CNT_S_0[11]\: CCU2C 
+generic map(
+  INIT0 => X"4005",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => RXR_WT_CNT9,
+B0 => RXR_WT_CNT(11),
+C0 => VCC,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => RXR_WT_CNT_CRY(10),
+COUT => RXR_WT_CNT_S_0_COUT(11),
+S0 => RXR_WT_CNT_S(11),
+S1 => RXR_WT_CNT_S_0_S1(11));
+\GENBLK1.PLOL_CNT_CRY_0[0]\: CCU2C 
+generic map(
+  INIT0 => X"500c",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => \PLOL_CNT_\,
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_3,
+COUT => PLOL_CNT_CRY(0),
+S0 => PLOL_CNT_CRY_0_S0(0),
+S1 => PLOL_CNT_S(0));
+\GENBLK1.PLOL_CNT_CRY_0[1]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(1),
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(2),
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(0),
+COUT => PLOL_CNT_CRY(2),
+S0 => PLOL_CNT_S(1),
+S1 => PLOL_CNT_S(2));
+\GENBLK1.PLOL_CNT_CRY_0[3]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(3),
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(4),
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(2),
+COUT => PLOL_CNT_CRY(4),
+S0 => PLOL_CNT_S(3),
+S1 => PLOL_CNT_S(4));
+\GENBLK1.PLOL_CNT_CRY_0[5]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(5),
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(6),
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(4),
+COUT => PLOL_CNT_CRY(6),
+S0 => PLOL_CNT_S(5),
+S1 => PLOL_CNT_S(6));
+\GENBLK1.PLOL_CNT_CRY_0[7]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(7),
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(8),
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(6),
+COUT => PLOL_CNT_CRY(8),
+S0 => PLOL_CNT_S(7),
+S1 => PLOL_CNT_S(8));
+\GENBLK1.PLOL_CNT_CRY_0[9]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(9),
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(10),
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(8),
+COUT => PLOL_CNT_CRY(10),
+S0 => PLOL_CNT_S(9),
+S1 => PLOL_CNT_S(10));
+\GENBLK1.PLOL_CNT_CRY_0[11]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(11),
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(12),
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(10),
+COUT => PLOL_CNT_CRY(12),
+S0 => PLOL_CNT_S(11),
+S1 => PLOL_CNT_S(12));
+\GENBLK1.PLOL_CNT_CRY_0[13]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(13),
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(14),
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(12),
+COUT => PLOL_CNT_CRY(14),
+S0 => PLOL_CNT_S(13),
+S1 => PLOL_CNT_S(14));
+\GENBLK1.PLOL_CNT_CRY_0[15]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(15),
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(16),
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(14),
+COUT => PLOL_CNT_CRY(16),
+S0 => PLOL_CNT_S(15),
+S1 => PLOL_CNT_S(16));
+\GENBLK1.PLOL_CNT_CRY_0[17]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(17),
+C0 => VCC,
+D0 => VCC,
+A1 => \PLOL_CNT_\,
+B1 => PLOL_CNT(18),
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(16),
+COUT => PLOL_CNT_CRY(18),
+S0 => PLOL_CNT_S(17),
+S1 => PLOL_CNT_S(18));
+\GENBLK1.PLOL_CNT_S_0[19]\: CCU2C 
+generic map(
+  INIT0 => X"800a",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => \PLOL_CNT_\,
+B0 => PLOL_CNT(19),
+C0 => VCC,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => PLOL_CNT_CRY(18),
+COUT => PLOL_CNT_S_0_COUT(19),
+S0 => PLOL_CNT_S(19),
+S1 => PLOL_CNT_S_0_S1(19));
+\UN1_GENBLK2.RLOS_DB_CNT_CRY_0_0\: CCU2C 
+generic map(
+  INIT0 => X"5003",
+  INIT1 => X"900a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => RLOS_DB_CNT(0),
+B1 => UN1_RLOS_DB_CNT_ZERO(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_2,
+COUT => RLOS_DB_CNT_CRY_0,
+S0 => RLOS_DB_CNT_CRY_0_0_S0,
+S1 => RLOS_DB_CNT_CRY_0_0_S1);
+\UN1_GENBLK2.RLOS_DB_CNT_CRY_1_0\: CCU2C 
+generic map(
+  INIT0 => X"e101",
+  INIT1 => X"e101",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RLOS_DB_CNT_ZERO(0),
+B0 => RLOS_P2,
+C0 => RLOS_DB_CNT(1),
+D0 => VCC,
+A1 => UN1_RLOS_DB_CNT_ZERO(0),
+B1 => RLOS_P2,
+C1 => RLOS_DB_CNT(2),
+D1 => VCC,
+CIN => RLOS_DB_CNT_CRY_0,
+COUT => RLOS_DB_CNT_CRY_2,
+S0 => RLOS_DB_CNT_CRY_1_0_S0,
+S1 => RLOS_DB_CNT_CRY_1_0_S1);
+\UN1_GENBLK2.RLOS_DB_CNT_S_3_0\: CCU2C 
+generic map(
+  INIT0 => X"a90a",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => RLOS_DB_CNT(3),
+B0 => RLOS_P2,
+C0 => UN1_RLOS_DB_CNT_ZERO(0),
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => RLOS_DB_CNT_CRY_2,
+COUT => RLOS_DB_CNT_S_3_0_COUT,
+S0 => RLOS_DB_CNT_S_3_0_S0,
+S1 => RLOS_DB_CNT_S_3_0_S1);
+\UN1_GENBLK2.RLOL_DB_CNT_CRY_0_0\: CCU2C 
+generic map(
+  INIT0 => X"5003",
+  INIT1 => X"900a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => RLOL_DB_CNT(0),
+B1 => UN1_RLOL_DB_CNT_ZERO(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_1,
+COUT => RLOL_DB_CNT_CRY_0,
+S0 => RLOL_DB_CNT_CRY_0_0_S0,
+S1 => RLOL_DB_CNT_CRY_0_0_S1);
+\UN1_GENBLK2.RLOL_DB_CNT_CRY_1_0\: CCU2C 
+generic map(
+  INIT0 => X"e101",
+  INIT1 => X"e101",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RLOL_DB_CNT_ZERO(0),
+B0 => RLOL_P2,
+C0 => RLOL_DB_CNT(1),
+D0 => VCC,
+A1 => UN1_RLOL_DB_CNT_ZERO(0),
+B1 => RLOL_P2,
+C1 => RLOL_DB_CNT(2),
+D1 => VCC,
+CIN => RLOL_DB_CNT_CRY_0,
+COUT => RLOL_DB_CNT_CRY_2,
+S0 => RLOL_DB_CNT_CRY_1_0_S0,
+S1 => RLOL_DB_CNT_CRY_1_0_S1);
+\UN1_GENBLK2.RLOL_DB_CNT_S_3_0\: CCU2C 
+generic map(
+  INIT0 => X"a90a",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => RLOL_DB_CNT(3),
+B0 => RLOL_P2,
+C0 => UN1_RLOL_DB_CNT_ZERO(0),
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => RLOL_DB_CNT_CRY_2,
+COUT => RLOL_DB_CNT_S_3_0_COUT,
+S0 => RLOL_DB_CNT_S_3_0_S0,
+S1 => RLOL_DB_CNT_S_3_0_S1);
+RXSDR_APPD_4 <= RXSDR_APPD;
+TXSR_APPD_4 <= TXSR_APPD;
+VCC_0: VHI port map (
+Z => VCC);
+II_GND: VLO port map (
+Z => GND);
+rsl_tx_pcs_rst_c <= RSL_TX_PCS_RST_C_4;
+rsl_rx_pcs_rst_c <= RSL_RX_PCS_RST_C_5;
+rsl_tx_serdes_rst_c <= RSL_TX_SERDES_RST_C_6;
+rsl_tx_rdy <= RSL_TX_RDY_7;
+rsl_rx_rdy <= RSL_RX_RDY_8;
+rsl_rx_serdes_rst_c <= RSL_RX_SERDES_RST_C_9;
+rsl_serdes_rst_dual_c <= RSL_SERDES_RST_DUAL_C_10;
+end beh;
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library synplify;
+use synplify.components.all;
+library pmi;
+use pmi.pmi_components.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity serdes_sync_1sll_core_Z1_layer1 is
+port(
+tx_pclk :  in std_logic;
+sli_rst :  in std_logic;
+pll_refclki :  in std_logic;
+pll_lock_i :  out std_logic);
+end serdes_sync_1sll_core_Z1_layer1;
+
+architecture beh of serdes_sync_1sll_core_Z1_layer1 is
+signal PHB_CNT : std_logic_vector(2 downto 0);
+signal PHB_CNT_I : std_logic_vector(2 downto 0);
+signal RCOUNT : std_logic_vector(15 downto 0);
+signal PCOUNT : std_logic_vector(21 downto 0);
+signal UN1_PCOUNT_DIFF_I : std_logic_vector(0 to 0);
+signal SLL_STATE : std_logic_vector(1 to 1);
+signal SLL_STATE_QN : std_logic_vector(1 to 1);
+signal RHB_WAIT_CNT_S : std_logic_vector(7 downto 0);
+signal RHB_WAIT_CNT : std_logic_vector(7 downto 0);
+signal RHB_WAIT_CNT_QN : std_logic_vector(7 downto 0);
+signal RCOUNT_S : std_logic_vector(15 downto 0);
+signal RCOUNT_QN : std_logic_vector(15 downto 0);
+signal PHB_CNT_QN : std_logic_vector(2 downto 0);
+signal PHB_CNT_RNO : std_logic_vector(2 downto 1);
+signal PCOUNT_DIFF_QN : std_logic_vector(21 downto 0);
+signal PCOUNT_S : std_logic_vector(21 downto 0);
+signal PCOUNT_QN : std_logic_vector(21 downto 0);
+signal RDIFF_COMP_LOCK : std_logic_vector(2 to 2);
+signal RDIFF_COMP_LOCK_QN : std_logic_vector(2 to 2);
+signal SLL_STATE_NS_I_0_M3 : std_logic_vector(1 to 1);
+signal UN1_PCOUNT_DIFF : std_logic_vector(0 to 0);
+signal PCOUNT_CRY : std_logic_vector(20 downto 0);
+signal PCOUNT_CRY_0_S0 : std_logic_vector(0 to 0);
+signal PCOUNT_S_0_COUT : std_logic_vector(21 to 21);
+signal PCOUNT_S_0_S1 : std_logic_vector(21 to 21);
+signal RCOUNT_CRY : std_logic_vector(14 downto 0);
+signal RCOUNT_CRY_0_S0 : std_logic_vector(0 to 0);
+signal RCOUNT_S_0_COUT : std_logic_vector(15 to 15);
+signal RCOUNT_S_0_S1 : std_logic_vector(15 to 15);
+signal RHB_WAIT_CNT_CRY : std_logic_vector(6 downto 0);
+signal RHB_WAIT_CNT_CRY_0_S0 : std_logic_vector(0 to 0);
+signal RHB_WAIT_CNT_S_0_COUT : std_logic_vector(7 to 7);
+signal RHB_WAIT_CNT_S_0_S1 : std_logic_vector(7 to 7);
+signal PLL_LOCK : std_logic ;
+signal RTC_CTRL4_0_A3_1 : std_logic ;
+signal UN13_LOCK_20 : std_logic ;
+signal PPUL_SYNC_P2 : std_logic ;
+signal PPUL_SYNC_P1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_20 : std_logic ;
+signal UN13_LOCK_19 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_19 : std_logic ;
+signal UN13_LOCK_18 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_18 : std_logic ;
+signal UN13_LOCK_17 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_17_0_RNO : std_logic ;
+signal UN13_LOCK_16 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_16 : std_logic ;
+signal UN13_LOCK_15 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_15 : std_logic ;
+signal UN13_LOCK_14 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_14 : std_logic ;
+signal UN13_LOCK_13 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_13 : std_logic ;
+signal UN13_LOCK_12 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_12 : std_logic ;
+signal UN13_LOCK_11 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_11 : std_logic ;
+signal UN13_LOCK_10 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_10 : std_logic ;
+signal UN13_LOCK_9 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_9 : std_logic ;
+signal UN13_LOCK_8 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_8 : std_logic ;
+signal UN13_LOCK_7 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_7 : std_logic ;
+signal UN13_LOCK_6 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_6 : std_logic ;
+signal UN13_LOCK_5 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_5 : std_logic ;
+signal UN13_LOCK_4 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_4 : std_logic ;
+signal UN13_LOCK_3 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_3 : std_logic ;
+signal UN13_LOCK_2 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_2 : std_logic ;
+signal UN13_LOCK_1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_AXB_1 : std_logic ;
+signal UN13_LOCK_21 : std_logic ;
+signal PPUL_SYNC_P3 : std_logic ;
+signal N_7 : std_logic ;
+signal UN13_LOCK_0 : std_logic ;
+signal RTC_CTRL4 : std_logic ;
+signal RTC_CTRL : std_logic ;
+signal VCC : std_logic ;
+signal N_2136_0 : std_logic ;
+signal UNLOCK_5 : std_logic ;
+signal UNLOCK_1_SQMUXA_I_0 : std_logic ;
+signal UNLOCK : std_logic ;
+signal UNLOCK_QN : std_logic ;
+signal N_89_I : std_logic ;
+signal RTC_PUL : std_logic ;
+signal RTC_PUL_P1 : std_logic ;
+signal RTC_PUL_P1_QN : std_logic ;
+signal RTC_PUL5 : std_logic ;
+signal RTC_PUL_QN : std_logic ;
+signal RTC_CTRL_QN : std_logic ;
+signal RSTAT_PCLK_2 : std_logic ;
+signal RSTAT_PCLK : std_logic ;
+signal RSTAT_PCLK_QN : std_logic ;
+signal RHB_SYNC_P1 : std_logic ;
+signal RHB_SYNC_P2 : std_logic ;
+signal RHB_SYNC_P2_QN : std_logic ;
+signal RHB_SYNC : std_logic ;
+signal RHB_SYNC_P1_QN : std_logic ;
+signal PPUL_SYNC_P3_QN : std_logic ;
+signal PPUL_SYNC_P2_QN : std_logic ;
+signal PPUL_SYNC : std_logic ;
+signal PPUL_SYNC_P1_QN : std_logic ;
+signal PLL_LOCK_QN : std_logic ;
+signal PHB : std_logic ;
+signal PHB_QN : std_logic ;
+signal PDIFF_SYNC : std_logic ;
+signal PDIFF_SYNC_P1 : std_logic ;
+signal PDIFF_SYNC_P1_QN : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_1_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_1_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_3_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_3_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_5_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_5_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_7_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_7_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_9_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_9_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_11_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_11_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_13_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_13_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_15_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_15_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_17_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_17_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_19_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_19_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_S_21_0_S0 : std_logic ;
+signal LOCK_5 : std_logic ;
+signal LOCK_1_SQMUXA_I_0 : std_logic ;
+signal LOCK : std_logic ;
+signal LOCK_QN : std_logic ;
+signal RTC_PUL5_0_O3 : std_logic ;
+signal RTC_PUL5_0_A3_6 : std_logic ;
+signal RTC_PUL5_0_A3_7 : std_logic ;
+signal UN1_RCOUNT_1_0_A3 : std_logic ;
+signal UN1_RHB_WAIT_CNT : std_logic ;
+signal N_12 : std_logic ;
+signal RTC_CTRL4_0_A3_12_4 : std_logic ;
+signal RTC_CTRL4_0_A3_12_5 : std_logic ;
+signal RTC_CTRL4_10 : std_logic ;
+signal UN1_RCOUNT_1_0_A3_1 : std_logic ;
+signal N_6 : std_logic ;
+signal UN1_RHB_WAIT_CNT_3 : std_logic ;
+signal UN1_RHB_WAIT_CNT_4 : std_logic ;
+signal RTC_PUL5_0_A3_5 : std_logic ;
+signal UN13_LOCK_CRY_21_I : std_logic ;
+signal UN13_UNLOCK_CRY_21 : std_logic ;
+signal N_8 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_0_0_S0 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_0_0_S1 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_2 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_4 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_6 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_8 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_10 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_12 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_14 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_16 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_18 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_CRY_20 : std_logic ;
+signal UN1_PCOUNT_DIFF_1_S_21_0_COUT : std_logic ;
+signal UN1_PCOUNT_DIFF_1_S_21_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_0 : std_logic ;
+signal UN13_LOCK_CRY_0_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_0_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_2 : std_logic ;
+signal UN13_LOCK_CRY_1_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_1_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_4 : std_logic ;
+signal UN13_LOCK_CRY_3_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_3_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_6 : std_logic ;
+signal UN13_LOCK_CRY_5_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_5_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_8 : std_logic ;
+signal UN13_LOCK_CRY_7_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_7_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_10 : std_logic ;
+signal UN13_LOCK_CRY_9_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_9_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_12 : std_logic ;
+signal UN13_LOCK_CRY_11_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_11_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_14 : std_logic ;
+signal UN13_LOCK_CRY_13_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_13_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_16 : std_logic ;
+signal UN13_LOCK_CRY_15_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_15_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_18 : std_logic ;
+signal UN13_LOCK_CRY_17_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_17_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_20 : std_logic ;
+signal UN13_LOCK_CRY_19_0_S0 : std_logic ;
+signal UN13_LOCK_CRY_19_0_S1 : std_logic ;
+signal UN13_LOCK_CRY_21_0_COUT : std_logic ;
+signal UN13_LOCK_CRY_21_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_0 : std_logic ;
+signal UN13_UNLOCK_CRY_0_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_0_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_2 : std_logic ;
+signal UN13_UNLOCK_CRY_1_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_1_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_4 : std_logic ;
+signal UN13_UNLOCK_CRY_3_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_3_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_6 : std_logic ;
+signal UN13_UNLOCK_CRY_5_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_5_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_8 : std_logic ;
+signal UN13_UNLOCK_CRY_7_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_7_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_10 : std_logic ;
+signal UN13_UNLOCK_CRY_9_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_9_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_12 : std_logic ;
+signal UN13_UNLOCK_CRY_11_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_11_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_14 : std_logic ;
+signal UN13_UNLOCK_CRY_13_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_13_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_16 : std_logic ;
+signal UN13_UNLOCK_CRY_15_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_15_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_18 : std_logic ;
+signal UN13_UNLOCK_CRY_17_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_17_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_20 : std_logic ;
+signal UN13_UNLOCK_CRY_19_0_S0 : std_logic ;
+signal UN13_UNLOCK_CRY_19_0_S1 : std_logic ;
+signal UN13_UNLOCK_CRY_21_0_COUT : std_logic ;
+signal UN13_UNLOCK_CRY_21_0_S0 : std_logic ;
+signal N_96 : std_logic ;
+signal N_20 : std_logic ;
+signal N_19 : std_logic ;
+signal N_18 : std_logic ;
+signal N_14 : std_logic ;
+signal GND : std_logic ;
+signal N_1 : std_logic ;
+signal N_2 : std_logic ;
+signal N_3 : std_logic ;
+signal N_4 : std_logic ;
+signal N_5 : std_logic ;
+signal N_9 : std_logic ;
+component sync_0s
+port(
+phb :  in std_logic;
+rhb_sync :  out std_logic;
+sli_rst :  in std_logic;
+pll_refclki :  in std_logic  );
+end component;
+component sync_0s_6
+port(
+rtc_pul :  in std_logic;
+ppul_sync :  out std_logic;
+sli_rst :  in std_logic;
+tx_pclk :  in std_logic  );
+end component;
+component sync_0s_0
+port(
+ppul_sync :  in std_logic;
+pdiff_sync :  out std_logic;
+sli_rst :  in std_logic;
+pll_refclki :  in std_logic  );
+end component;
+begin
+PHB_RNO: INV port map (
+A => PHB_CNT(2),
+Z => PHB_CNT_I(2));
+\PHB_CNT_RNO[0]\: INV port map (
+A => PHB_CNT(0),
+Z => PHB_CNT_I(0));
+PLL_LOCK_RNI6JK9: INV port map (
+A => PLL_LOCK,
+Z => pll_lock_i);
+RTC_CTRL4_0_A3_RNO: LUT4 
+generic map(
+  init => X"2000"
+)
+port map (
+A => RCOUNT(2),
+B => RCOUNT(0),
+C => RCOUNT(5),
+D => RCOUNT(4),
+Z => RTC_CTRL4_0_A3_1);
+UN1_PCOUNT_DIFF_1_CRY_19_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_20,
+B => PCOUNT(20),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_20);
+UN1_PCOUNT_DIFF_1_CRY_19_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_19,
+B => PCOUNT(19),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_19);
+UN1_PCOUNT_DIFF_1_CRY_17_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_18,
+B => PCOUNT(18),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_18);
+UN1_PCOUNT_DIFF_1_CRY_17_0_RNO_Z473: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_17,
+B => PCOUNT(17),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_CRY_17_0_RNO);
+UN1_PCOUNT_DIFF_1_CRY_15_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_16,
+B => PCOUNT(16),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_16);
+UN1_PCOUNT_DIFF_1_CRY_15_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_15,
+B => PCOUNT(15),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_15);
+UN1_PCOUNT_DIFF_1_CRY_13_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_14,
+B => PCOUNT(14),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_14);
+UN1_PCOUNT_DIFF_1_CRY_13_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_13,
+B => PCOUNT(13),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_13);
+UN1_PCOUNT_DIFF_1_CRY_11_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_12,
+B => PCOUNT(12),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_12);
+UN1_PCOUNT_DIFF_1_CRY_11_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_11,
+B => PCOUNT(11),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_11);
+UN1_PCOUNT_DIFF_1_CRY_9_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_10,
+B => PCOUNT(10),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_10);
+UN1_PCOUNT_DIFF_1_CRY_9_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_9,
+B => PCOUNT(9),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_9);
+UN1_PCOUNT_DIFF_1_CRY_7_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_8,
+B => PCOUNT(8),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_8);
+UN1_PCOUNT_DIFF_1_CRY_7_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_7,
+B => PCOUNT(7),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_7);
+UN1_PCOUNT_DIFF_1_CRY_5_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_6,
+B => PCOUNT(6),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_6);
+UN1_PCOUNT_DIFF_1_CRY_5_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_5,
+B => PCOUNT(5),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_5);
+UN1_PCOUNT_DIFF_1_CRY_3_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_4,
+B => PCOUNT(4),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_4);
+UN1_PCOUNT_DIFF_1_CRY_3_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_3,
+B => PCOUNT(3),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_3);
+UN1_PCOUNT_DIFF_1_CRY_1_0_RNO_0: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_2,
+B => PCOUNT(2),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_2);
+UN1_PCOUNT_DIFF_1_CRY_1_0_RNO: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_1,
+B => PCOUNT(1),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF_1_AXB_1);
+PPUL_SYNC_P3_RNIU65C: LUT4 
+generic map(
+  init => X"2F20"
+)
+port map (
+A => UN13_LOCK_21,
+B => PPUL_SYNC_P3,
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => N_7);
+\PCOUNT_DIFF_RNO[0]\: LUT4 
+generic map(
+  init => X"FD20"
+)
+port map (
+A => PPUL_SYNC_P1,
+B => PPUL_SYNC_P2,
+C => PCOUNT(0),
+D => UN13_LOCK_0,
+Z => UN1_PCOUNT_DIFF_I(0));
+RTC_CTRL_0: LUT4 
+generic map(
+  init => X"EEEE"
+)
+port map (
+A => RTC_CTRL4,
+B => RTC_CTRL,
+C => VCC,
+D => VCC,
+Z => N_2136_0);
+UNLOCK_REG_Z494: FD1P3DX port map (
+D => UNLOCK_5,
+SP => UNLOCK_1_SQMUXA_I_0,
+CK => pll_refclki,
+CD => sli_rst,
+Q => UNLOCK);
+\SLL_STATE[1]_REG_Z496\: FD1S3DX port map (
+D => N_89_I,
+CK => pll_refclki,
+CD => sli_rst,
+Q => SLL_STATE(1));
+RTC_PUL_P1_REG_Z498: FD1S3DX port map (
+D => RTC_PUL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RTC_PUL_P1);
+RTC_PUL_REG_Z500: FD1P3DX port map (
+D => RTC_PUL5,
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RTC_PUL);
+RTC_CTRL_REG_Z502: FD1S3DX port map (
+D => N_2136_0,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RTC_CTRL);
+RSTAT_PCLK_REG_Z504: FD1P3DX port map (
+D => RSTAT_PCLK_2,
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RSTAT_PCLK);
+\RHB_WAIT_CNT[0]_REG_Z506\: FD1P3DX port map (
+D => RHB_WAIT_CNT_S(0),
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_WAIT_CNT(0));
+\RHB_WAIT_CNT[1]_REG_Z508\: FD1P3DX port map (
+D => RHB_WAIT_CNT_S(1),
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_WAIT_CNT(1));
+\RHB_WAIT_CNT[2]_REG_Z510\: FD1P3DX port map (
+D => RHB_WAIT_CNT_S(2),
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_WAIT_CNT(2));
+\RHB_WAIT_CNT[3]_REG_Z512\: FD1P3DX port map (
+D => RHB_WAIT_CNT_S(3),
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_WAIT_CNT(3));
+\RHB_WAIT_CNT[4]_REG_Z514\: FD1P3DX port map (
+D => RHB_WAIT_CNT_S(4),
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_WAIT_CNT(4));
+\RHB_WAIT_CNT[5]_REG_Z516\: FD1P3DX port map (
+D => RHB_WAIT_CNT_S(5),
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_WAIT_CNT(5));
+\RHB_WAIT_CNT[6]_REG_Z518\: FD1P3DX port map (
+D => RHB_WAIT_CNT_S(6),
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_WAIT_CNT(6));
+\RHB_WAIT_CNT[7]_REG_Z520\: FD1P3DX port map (
+D => RHB_WAIT_CNT_S(7),
+SP => RTC_CTRL,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_WAIT_CNT(7));
+RHB_SYNC_P2_REG_Z522: FD1S3DX port map (
+D => RHB_SYNC_P1,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_SYNC_P2);
+RHB_SYNC_P1_REG_Z524: FD1S3DX port map (
+D => RHB_SYNC,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RHB_SYNC_P1);
+\RCOUNT[0]_REG_Z526\: FD1S3DX port map (
+D => RCOUNT_S(0),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(0));
+\RCOUNT[1]_REG_Z528\: FD1S3DX port map (
+D => RCOUNT_S(1),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(1));
+\RCOUNT[2]_REG_Z530\: FD1S3DX port map (
+D => RCOUNT_S(2),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(2));
+\RCOUNT[3]_REG_Z532\: FD1S3DX port map (
+D => RCOUNT_S(3),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(3));
+\RCOUNT[4]_REG_Z534\: FD1S3DX port map (
+D => RCOUNT_S(4),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(4));
+\RCOUNT[5]_REG_Z536\: FD1S3DX port map (
+D => RCOUNT_S(5),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(5));
+\RCOUNT[6]_REG_Z538\: FD1S3DX port map (
+D => RCOUNT_S(6),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(6));
+\RCOUNT[7]_REG_Z540\: FD1S3DX port map (
+D => RCOUNT_S(7),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(7));
+\RCOUNT[8]_REG_Z542\: FD1S3DX port map (
+D => RCOUNT_S(8),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(8));
+\RCOUNT[9]_REG_Z544\: FD1S3DX port map (
+D => RCOUNT_S(9),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(9));
+\RCOUNT[10]_REG_Z546\: FD1S3DX port map (
+D => RCOUNT_S(10),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(10));
+\RCOUNT[11]_REG_Z548\: FD1S3DX port map (
+D => RCOUNT_S(11),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(11));
+\RCOUNT[12]_REG_Z550\: FD1S3DX port map (
+D => RCOUNT_S(12),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(12));
+\RCOUNT[13]_REG_Z552\: FD1S3DX port map (
+D => RCOUNT_S(13),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(13));
+\RCOUNT[14]_REG_Z554\: FD1S3DX port map (
+D => RCOUNT_S(14),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(14));
+\RCOUNT[15]_REG_Z556\: FD1S3DX port map (
+D => RCOUNT_S(15),
+CK => pll_refclki,
+CD => sli_rst,
+Q => RCOUNT(15));
+PPUL_SYNC_P3_REG_Z558: FD1S3DX port map (
+D => PPUL_SYNC_P2,
+CK => tx_pclk,
+CD => sli_rst,
+Q => PPUL_SYNC_P3);
+PPUL_SYNC_P2_REG_Z560: FD1S3DX port map (
+D => PPUL_SYNC_P1,
+CK => tx_pclk,
+CD => sli_rst,
+Q => PPUL_SYNC_P2);
+PPUL_SYNC_P1_REG_Z562: FD1S3DX port map (
+D => PPUL_SYNC,
+CK => tx_pclk,
+CD => sli_rst,
+Q => PPUL_SYNC_P1);
+PLL_LOCK_REG_Z564: FD1S3DX port map (
+D => SLL_STATE(1),
+CK => pll_refclki,
+CD => sli_rst,
+Q => PLL_LOCK);
+\PHB_CNT[0]_REG_Z566\: FD1S3DX port map (
+D => PHB_CNT_I(0),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PHB_CNT(0));
+\PHB_CNT[1]_REG_Z568\: FD1S3DX port map (
+D => PHB_CNT_RNO(1),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PHB_CNT(1));
+\PHB_CNT[2]_REG_Z570\: FD1S3DX port map (
+D => PHB_CNT_RNO(2),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PHB_CNT(2));
+PHB_REG_Z572: FD1S3DX port map (
+D => PHB_CNT_I(2),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PHB);
+PDIFF_SYNC_P1_REG_Z574: FD1S3DX port map (
+D => PDIFF_SYNC,
+CK => pll_refclki,
+CD => sli_rst,
+Q => PDIFF_SYNC_P1);
+\PCOUNT_DIFF[0]_REG_Z576\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_I(0),
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_0);
+\PCOUNT[0]_REG_Z578\: FD1S3DX port map (
+D => PCOUNT_S(0),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(0));
+\PCOUNT[1]_REG_Z580\: FD1S3DX port map (
+D => PCOUNT_S(1),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(1));
+\PCOUNT_DIFF[1]_REG_Z582\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_1_0_S0,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_1);
+\PCOUNT_DIFF[2]_REG_Z584\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_1_0_S1,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_2);
+\PCOUNT[2]_REG_Z586\: FD1S3DX port map (
+D => PCOUNT_S(2),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(2));
+\PCOUNT[3]_REG_Z588\: FD1S3DX port map (
+D => PCOUNT_S(3),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(3));
+\PCOUNT_DIFF[3]_REG_Z590\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_3_0_S0,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_3);
+\PCOUNT_DIFF[4]_REG_Z592\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_3_0_S1,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_4);
+\PCOUNT[4]_REG_Z594\: FD1S3DX port map (
+D => PCOUNT_S(4),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(4));
+\PCOUNT[5]_REG_Z596\: FD1S3DX port map (
+D => PCOUNT_S(5),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(5));
+\PCOUNT_DIFF[5]_REG_Z598\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_5_0_S0,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_5);
+\PCOUNT_DIFF[6]_REG_Z600\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_5_0_S1,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_6);
+\PCOUNT[6]_REG_Z602\: FD1S3DX port map (
+D => PCOUNT_S(6),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(6));
+\PCOUNT_DIFF[7]_REG_Z604\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_7_0_S0,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_7);
+\PCOUNT[7]_REG_Z606\: FD1S3DX port map (
+D => PCOUNT_S(7),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(7));
+\PCOUNT[8]_REG_Z608\: FD1S3DX port map (
+D => PCOUNT_S(8),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(8));
+\PCOUNT_DIFF[8]_REG_Z610\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_7_0_S1,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_8);
+\PCOUNT_DIFF[9]_REG_Z612\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_9_0_S0,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_9);
+\PCOUNT[9]_REG_Z614\: FD1S3DX port map (
+D => PCOUNT_S(9),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(9));
+\PCOUNT[10]_REG_Z616\: FD1S3DX port map (
+D => PCOUNT_S(10),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(10));
+\PCOUNT_DIFF[10]_REG_Z618\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_9_0_S1,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_10);
+\PCOUNT_DIFF[11]_REG_Z620\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_11_0_S0,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_11);
+\PCOUNT[11]_REG_Z622\: FD1S3DX port map (
+D => PCOUNT_S(11),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(11));
+\PCOUNT[12]_REG_Z624\: FD1S3DX port map (
+D => PCOUNT_S(12),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(12));
+\PCOUNT_DIFF[12]_REG_Z626\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_11_0_S1,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_12);
+\PCOUNT[13]_REG_Z628\: FD1S3DX port map (
+D => PCOUNT_S(13),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(13));
+\PCOUNT_DIFF[13]_REG_Z630\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_13_0_S0,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_13);
+\PCOUNT_DIFF[14]_REG_Z632\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_13_0_S1,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_14);
+\PCOUNT[14]_REG_Z634\: FD1S3DX port map (
+D => PCOUNT_S(14),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(14));
+\PCOUNT_DIFF[15]_REG_Z636\: FD1P3BX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_15_0_S0,
+SP => N_7,
+CK => tx_pclk,
+PD => sli_rst,
+Q => UN13_LOCK_15);
+\PCOUNT[15]_REG_Z638\: FD1S3DX port map (
+D => PCOUNT_S(15),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(15));
+\PCOUNT[16]_REG_Z640\: FD1S3DX port map (
+D => PCOUNT_S(16),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(16));
+\PCOUNT_DIFF[16]_REG_Z642\: FD1P3DX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_15_0_S1,
+SP => N_7,
+CK => tx_pclk,
+CD => sli_rst,
+Q => UN13_LOCK_16);
+\PCOUNT_DIFF[17]_REG_Z644\: FD1P3DX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_17_0_S0,
+SP => N_7,
+CK => tx_pclk,
+CD => sli_rst,
+Q => UN13_LOCK_17);
+\PCOUNT[17]_REG_Z646\: FD1S3DX port map (
+D => PCOUNT_S(17),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(17));
+\PCOUNT[18]_REG_Z648\: FD1S3DX port map (
+D => PCOUNT_S(18),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(18));
+\PCOUNT_DIFF[18]_REG_Z650\: FD1P3DX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_17_0_S1,
+SP => N_7,
+CK => tx_pclk,
+CD => sli_rst,
+Q => UN13_LOCK_18);
+\PCOUNT[19]_REG_Z652\: FD1S3DX port map (
+D => PCOUNT_S(19),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(19));
+\PCOUNT_DIFF[19]_REG_Z654\: FD1P3DX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_19_0_S0,
+SP => N_7,
+CK => tx_pclk,
+CD => sli_rst,
+Q => UN13_LOCK_19);
+\PCOUNT_DIFF[20]_REG_Z656\: FD1P3DX port map (
+D => UN1_PCOUNT_DIFF_1_CRY_19_0_S1,
+SP => N_7,
+CK => tx_pclk,
+CD => sli_rst,
+Q => UN13_LOCK_20);
+\PCOUNT[20]_REG_Z658\: FD1S3DX port map (
+D => PCOUNT_S(20),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(20));
+\PCOUNT[21]_REG_Z660\: FD1S3DX port map (
+D => PCOUNT_S(21),
+CK => tx_pclk,
+CD => sli_rst,
+Q => PCOUNT(21));
+\PCOUNT_DIFF[21]_REG_Z662\: FD1P3DX port map (
+D => UN1_PCOUNT_DIFF_1_S_21_0_S0,
+SP => N_7,
+CK => tx_pclk,
+CD => sli_rst,
+Q => UN13_LOCK_21);
+LOCK_REG_Z664: FD1P3DX port map (
+D => LOCK_5,
+SP => LOCK_1_SQMUXA_I_0,
+CK => pll_refclki,
+CD => sli_rst,
+Q => LOCK);
+\GENBLK5.RDIFF_COMP_LOCK[2]_REG_Z666\: FD1S3DX port map (
+D => VCC,
+CK => pll_refclki,
+CD => sli_rst,
+Q => RDIFF_COMP_LOCK(2));
+RTC_PUL5_0_0: LUT4 
+generic map(
+  init => X"FF80"
+)
+port map (
+A => RTC_PUL5_0_O3,
+B => RTC_PUL5_0_A3_6,
+C => RTC_PUL5_0_A3_7,
+D => UN1_RCOUNT_1_0_A3,
+Z => RTC_PUL5);
+RSTAT_PCLK_2_IV_0_0: LUT4 
+generic map(
+  init => X"5D0C"
+)
+port map (
+A => UN1_RHB_WAIT_CNT,
+B => RHB_SYNC_P1,
+C => RHB_SYNC_P2,
+D => RSTAT_PCLK,
+Z => RSTAT_PCLK_2);
+\SLL_STATE_RNO[1]\: LUT4 
+generic map(
+  init => X"4044"
+)
+port map (
+A => SLL_STATE_NS_I_0_M3(1),
+B => RSTAT_PCLK,
+C => SLL_STATE(1),
+D => UNLOCK,
+Z => N_89_I);
+UN1_RHB_WAIT_CNT12_1_I_0_A3: LUT4 
+generic map(
+  init => X"5151"
+)
+port map (
+A => UN1_RHB_WAIT_CNT,
+B => RHB_SYNC_P1,
+C => RHB_SYNC_P2,
+D => VCC,
+Z => N_12);
+RTC_CTRL4_0_A3: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RTC_CTRL4_0_A3_1,
+B => RTC_CTRL4_0_A3_12_4,
+C => RTC_CTRL4_0_A3_12_5,
+D => RTC_CTRL4_10,
+Z => RTC_CTRL4);
+UN1_RCOUNT_1_0_A3_Z672: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RTC_CTRL4_0_A3_12_4,
+B => RTC_CTRL4_0_A3_12_5,
+C => RTC_CTRL4_10,
+D => UN1_RCOUNT_1_0_A3_1,
+Z => UN1_RCOUNT_1_0_A3);
+RTC_PUL5_0_O3_Z673: LUT4 
+generic map(
+  init => X"AAAB"
+)
+port map (
+A => N_6,
+B => RCOUNT(1),
+C => RCOUNT(2),
+D => RCOUNT(3),
+Z => RTC_PUL5_0_O3);
+UN1_RHB_WAIT_CNT_Z674: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RHB_WAIT_CNT(4),
+B => RHB_WAIT_CNT(5),
+C => UN1_RHB_WAIT_CNT_3,
+D => UN1_RHB_WAIT_CNT_4,
+Z => UN1_RHB_WAIT_CNT);
+RTC_PUL5_0_A3_7_Z675: LUT4 
+generic map(
+  init => X"1010"
+)
+port map (
+A => RCOUNT(7),
+B => RCOUNT(8),
+C => RTC_PUL5_0_A3_5,
+D => VCC,
+Z => RTC_PUL5_0_A3_7);
+\SLL_STATE_NS_I_0_M3[1]_Z676\: LUT4 
+generic map(
+  init => X"10DF"
+)
+port map (
+A => LOCK,
+B => RTC_PUL,
+C => RTC_PUL_P1,
+D => SLL_STATE(1),
+Z => SLL_STATE_NS_I_0_M3(1));
+\PHB_CNT_RNO[2]_Z677\: LUT4 
+generic map(
+  init => X"7878"
+)
+port map (
+A => PHB_CNT(0),
+B => PHB_CNT(1),
+C => PHB_CNT(2),
+D => VCC,
+Z => PHB_CNT_RNO(2));
+UNLOCK_1_SQMUXA_I_0_Z678: LUT4 
+generic map(
+  init => X"4F4F"
+)
+port map (
+A => PDIFF_SYNC,
+B => PDIFF_SYNC_P1,
+C => UNLOCK,
+D => VCC,
+Z => UNLOCK_1_SQMUXA_I_0);
+LOCK_1_SQMUXA_I_0_Z679: LUT4 
+generic map(
+  init => X"7575"
+)
+port map (
+A => LOCK,
+B => PDIFF_SYNC,
+C => PDIFF_SYNC_P1,
+D => VCC,
+Z => LOCK_1_SQMUXA_I_0);
+RTC_CTRL4_0_A3_10: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RCOUNT(1),
+B => RCOUNT(3),
+C => RCOUNT(6),
+D => RCOUNT(15),
+Z => RTC_CTRL4_10);
+UN1_RHB_WAIT_CNT_4_Z681: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RHB_WAIT_CNT(0),
+B => RHB_WAIT_CNT(1),
+C => RHB_WAIT_CNT(2),
+D => RHB_WAIT_CNT(3),
+Z => UN1_RHB_WAIT_CNT_4);
+RTC_CTRL4_0_A3_12_4_Z682: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RCOUNT(11),
+B => RCOUNT(12),
+C => RCOUNT(13),
+D => RCOUNT(14),
+Z => RTC_CTRL4_0_A3_12_4);
+RTC_CTRL4_0_A3_12_5_Z683: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RCOUNT(7),
+B => RCOUNT(8),
+C => RCOUNT(9),
+D => RCOUNT(10),
+Z => RTC_CTRL4_0_A3_12_5);
+RTC_PUL5_0_A3_5_Z684: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RCOUNT(6),
+B => RCOUNT(13),
+C => RCOUNT(14),
+D => RCOUNT(15),
+Z => RTC_PUL5_0_A3_5);
+RTC_PUL5_0_A3_6_Z685: LUT4 
+generic map(
+  init => X"0001"
+)
+port map (
+A => RCOUNT(9),
+B => RCOUNT(10),
+C => RCOUNT(11),
+D => RCOUNT(12),
+Z => RTC_PUL5_0_A3_6);
+LOCK_5_Z686: LUT4 
+generic map(
+  init => X"8888"
+)
+port map (
+A => PDIFF_SYNC,
+B => UN13_LOCK_CRY_21_I,
+C => VCC,
+D => VCC,
+Z => LOCK_5);
+UNLOCK_5_Z687: LUT4 
+generic map(
+  init => X"8888"
+)
+port map (
+A => PDIFF_SYNC,
+B => UN13_UNLOCK_CRY_21,
+C => VCC,
+D => VCC,
+Z => UNLOCK_5);
+PCOUNT10_0_O3: LUT4 
+generic map(
+  init => X"DDDD"
+)
+port map (
+A => PPUL_SYNC_P1,
+B => PPUL_SYNC_P2,
+C => VCC,
+D => VCC,
+Z => N_8);
+\PHB_CNT_RNO[1]_Z689\: LUT4 
+generic map(
+  init => X"6666"
+)
+port map (
+A => PHB_CNT(0),
+B => PHB_CNT(1),
+C => VCC,
+D => VCC,
+Z => PHB_CNT_RNO(1));
+RTC_CTRL4_0_O3: LUT4 
+generic map(
+  init => X"7777"
+)
+port map (
+A => RCOUNT(4),
+B => RCOUNT(5),
+C => VCC,
+D => VCC,
+Z => N_6);
+UN1_RHB_WAIT_CNT_3_Z691: LUT4 
+generic map(
+  init => X"8888"
+)
+port map (
+A => RHB_WAIT_CNT(6),
+B => RHB_WAIT_CNT(7),
+C => VCC,
+D => VCC,
+Z => UN1_RHB_WAIT_CNT_3);
+\UN1_PCOUNT_DIFF[0]_Z692\: LUT4 
+generic map(
+  init => X"5355"
+)
+port map (
+A => UN13_LOCK_0,
+B => PCOUNT(0),
+C => PPUL_SYNC_P2,
+D => PPUL_SYNC_P1,
+Z => UN1_PCOUNT_DIFF(0));
+UN1_RCOUNT_1_0_A3_1_Z693: LUT4 
+generic map(
+  init => X"8000"
+)
+port map (
+A => RCOUNT(2),
+B => RCOUNT(0),
+C => RCOUNT(5),
+D => RCOUNT(4),
+Z => UN1_RCOUNT_1_0_A3_1);
+\PCOUNT_CRY_0[0]\: CCU2C 
+generic map(
+  INIT0 => X"500c",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => N_8,
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_9,
+COUT => PCOUNT_CRY(0),
+S0 => PCOUNT_CRY_0_S0(0),
+S1 => PCOUNT_S(0));
+\PCOUNT_CRY_0[1]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(1),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(2),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(0),
+COUT => PCOUNT_CRY(2),
+S0 => PCOUNT_S(1),
+S1 => PCOUNT_S(2));
+\PCOUNT_CRY_0[3]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(3),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(4),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(2),
+COUT => PCOUNT_CRY(4),
+S0 => PCOUNT_S(3),
+S1 => PCOUNT_S(4));
+\PCOUNT_CRY_0[5]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(5),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(6),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(4),
+COUT => PCOUNT_CRY(6),
+S0 => PCOUNT_S(5),
+S1 => PCOUNT_S(6));
+\PCOUNT_CRY_0[7]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(7),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(8),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(6),
+COUT => PCOUNT_CRY(8),
+S0 => PCOUNT_S(7),
+S1 => PCOUNT_S(8));
+\PCOUNT_CRY_0[9]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(9),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(10),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(8),
+COUT => PCOUNT_CRY(10),
+S0 => PCOUNT_S(9),
+S1 => PCOUNT_S(10));
+\PCOUNT_CRY_0[11]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(11),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(12),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(10),
+COUT => PCOUNT_CRY(12),
+S0 => PCOUNT_S(11),
+S1 => PCOUNT_S(12));
+\PCOUNT_CRY_0[13]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(13),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(14),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(12),
+COUT => PCOUNT_CRY(14),
+S0 => PCOUNT_S(13),
+S1 => PCOUNT_S(14));
+\PCOUNT_CRY_0[15]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(15),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(16),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(14),
+COUT => PCOUNT_CRY(16),
+S0 => PCOUNT_S(15),
+S1 => PCOUNT_S(16));
+\PCOUNT_CRY_0[17]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(17),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(18),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(16),
+COUT => PCOUNT_CRY(18),
+S0 => PCOUNT_S(17),
+S1 => PCOUNT_S(18));
+\PCOUNT_CRY_0[19]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(19),
+C0 => VCC,
+D0 => VCC,
+A1 => N_8,
+B1 => PCOUNT(20),
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(18),
+COUT => PCOUNT_CRY(20),
+S0 => PCOUNT_S(19),
+S1 => PCOUNT_S(20));
+\PCOUNT_S_0[21]\: CCU2C 
+generic map(
+  INIT0 => X"800a",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => PCOUNT(21),
+C0 => VCC,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => PCOUNT_CRY(20),
+COUT => PCOUNT_S_0_COUT(21),
+S0 => PCOUNT_S(21),
+S1 => PCOUNT_S_0_S1(21));
+\RCOUNT_CRY_0[0]\: CCU2C 
+generic map(
+  INIT0 => X"5003",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => UN1_RCOUNT_1_0_A3,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_RCOUNT_1_0_A3,
+B1 => RCOUNT(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_5,
+COUT => RCOUNT_CRY(0),
+S0 => RCOUNT_CRY_0_S0(0),
+S1 => RCOUNT_S(0));
+\RCOUNT_CRY_0[1]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RCOUNT_1_0_A3,
+B0 => RCOUNT(1),
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_RCOUNT_1_0_A3,
+B1 => RCOUNT(2),
+C1 => VCC,
+D1 => VCC,
+CIN => RCOUNT_CRY(0),
+COUT => RCOUNT_CRY(2),
+S0 => RCOUNT_S(1),
+S1 => RCOUNT_S(2));
+\RCOUNT_CRY_0[3]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RCOUNT_1_0_A3,
+B0 => RCOUNT(3),
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_RCOUNT_1_0_A3,
+B1 => RCOUNT(4),
+C1 => VCC,
+D1 => VCC,
+CIN => RCOUNT_CRY(2),
+COUT => RCOUNT_CRY(4),
+S0 => RCOUNT_S(3),
+S1 => RCOUNT_S(4));
+\RCOUNT_CRY_0[5]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RCOUNT_1_0_A3,
+B0 => RCOUNT(5),
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_RCOUNT_1_0_A3,
+B1 => RCOUNT(6),
+C1 => VCC,
+D1 => VCC,
+CIN => RCOUNT_CRY(4),
+COUT => RCOUNT_CRY(6),
+S0 => RCOUNT_S(5),
+S1 => RCOUNT_S(6));
+\RCOUNT_CRY_0[7]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RCOUNT_1_0_A3,
+B0 => RCOUNT(7),
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_RCOUNT_1_0_A3,
+B1 => RCOUNT(8),
+C1 => VCC,
+D1 => VCC,
+CIN => RCOUNT_CRY(6),
+COUT => RCOUNT_CRY(8),
+S0 => RCOUNT_S(7),
+S1 => RCOUNT_S(8));
+\RCOUNT_CRY_0[9]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RCOUNT_1_0_A3,
+B0 => RCOUNT(9),
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_RCOUNT_1_0_A3,
+B1 => RCOUNT(10),
+C1 => VCC,
+D1 => VCC,
+CIN => RCOUNT_CRY(8),
+COUT => RCOUNT_CRY(10),
+S0 => RCOUNT_S(9),
+S1 => RCOUNT_S(10));
+\RCOUNT_CRY_0[11]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RCOUNT_1_0_A3,
+B0 => RCOUNT(11),
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_RCOUNT_1_0_A3,
+B1 => RCOUNT(12),
+C1 => VCC,
+D1 => VCC,
+CIN => RCOUNT_CRY(10),
+COUT => RCOUNT_CRY(12),
+S0 => RCOUNT_S(11),
+S1 => RCOUNT_S(12));
+\RCOUNT_CRY_0[13]\: CCU2C 
+generic map(
+  INIT0 => X"4000",
+  INIT1 => X"4000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RCOUNT_1_0_A3,
+B0 => RCOUNT(13),
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_RCOUNT_1_0_A3,
+B1 => RCOUNT(14),
+C1 => VCC,
+D1 => VCC,
+CIN => RCOUNT_CRY(12),
+COUT => RCOUNT_CRY(14),
+S0 => RCOUNT_S(13),
+S1 => RCOUNT_S(14));
+\RCOUNT_S_0[15]\: CCU2C 
+generic map(
+  INIT0 => X"4005",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_RCOUNT_1_0_A3,
+B0 => RCOUNT(15),
+C0 => VCC,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => RCOUNT_CRY(14),
+COUT => RCOUNT_S_0_COUT(15),
+S0 => RCOUNT_S(15),
+S1 => RCOUNT_S_0_S1(15));
+\RHB_WAIT_CNT_CRY_0[0]\: CCU2C 
+generic map(
+  INIT0 => X"500c",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => N_12,
+C0 => VCC,
+D0 => VCC,
+A1 => N_12,
+B1 => RHB_WAIT_CNT(0),
+C1 => VCC,
+D1 => VCC,
+CIN => N_4,
+COUT => RHB_WAIT_CNT_CRY(0),
+S0 => RHB_WAIT_CNT_CRY_0_S0(0),
+S1 => RHB_WAIT_CNT_S(0));
+\RHB_WAIT_CNT_CRY_0[1]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_12,
+B0 => RHB_WAIT_CNT(1),
+C0 => VCC,
+D0 => VCC,
+A1 => N_12,
+B1 => RHB_WAIT_CNT(2),
+C1 => VCC,
+D1 => VCC,
+CIN => RHB_WAIT_CNT_CRY(0),
+COUT => RHB_WAIT_CNT_CRY(2),
+S0 => RHB_WAIT_CNT_S(1),
+S1 => RHB_WAIT_CNT_S(2));
+\RHB_WAIT_CNT_CRY_0[3]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_12,
+B0 => RHB_WAIT_CNT(3),
+C0 => VCC,
+D0 => VCC,
+A1 => N_12,
+B1 => RHB_WAIT_CNT(4),
+C1 => VCC,
+D1 => VCC,
+CIN => RHB_WAIT_CNT_CRY(2),
+COUT => RHB_WAIT_CNT_CRY(4),
+S0 => RHB_WAIT_CNT_S(3),
+S1 => RHB_WAIT_CNT_S(4));
+\RHB_WAIT_CNT_CRY_0[5]\: CCU2C 
+generic map(
+  INIT0 => X"8000",
+  INIT1 => X"8000",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_12,
+B0 => RHB_WAIT_CNT(5),
+C0 => VCC,
+D0 => VCC,
+A1 => N_12,
+B1 => RHB_WAIT_CNT(6),
+C1 => VCC,
+D1 => VCC,
+CIN => RHB_WAIT_CNT_CRY(4),
+COUT => RHB_WAIT_CNT_CRY(6),
+S0 => RHB_WAIT_CNT_S(5),
+S1 => RHB_WAIT_CNT_S(6));
+\RHB_WAIT_CNT_S_0[7]\: CCU2C 
+generic map(
+  INIT0 => X"800a",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_12,
+B0 => RHB_WAIT_CNT(7),
+C0 => VCC,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => RHB_WAIT_CNT_CRY(6),
+COUT => RHB_WAIT_CNT_S_0_COUT(7),
+S0 => RHB_WAIT_CNT_S(7),
+S1 => RHB_WAIT_CNT_S_0_S1(7));
+UN1_PCOUNT_DIFF_1_CRY_0_0: CCU2C 
+generic map(
+  INIT0 => X"5003",
+  INIT1 => X"500f",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF(0),
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => N_3,
+COUT => UN1_PCOUNT_DIFF_1_CRY_0,
+S0 => UN1_PCOUNT_DIFF_1_CRY_0_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_0_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_1_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_1,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_2,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_0,
+COUT => UN1_PCOUNT_DIFF_1_CRY_2,
+S0 => UN1_PCOUNT_DIFF_1_CRY_1_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_1_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_3_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_3,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_4,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_2,
+COUT => UN1_PCOUNT_DIFF_1_CRY_4,
+S0 => UN1_PCOUNT_DIFF_1_CRY_3_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_3_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_5_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_5,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_6,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_4,
+COUT => UN1_PCOUNT_DIFF_1_CRY_6,
+S0 => UN1_PCOUNT_DIFF_1_CRY_5_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_5_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_7_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_7,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_8,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_6,
+COUT => UN1_PCOUNT_DIFF_1_CRY_8,
+S0 => UN1_PCOUNT_DIFF_1_CRY_7_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_7_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_9_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_9,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_10,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_8,
+COUT => UN1_PCOUNT_DIFF_1_CRY_10,
+S0 => UN1_PCOUNT_DIFF_1_CRY_9_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_9_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_11_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_11,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_12,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_10,
+COUT => UN1_PCOUNT_DIFF_1_CRY_12,
+S0 => UN1_PCOUNT_DIFF_1_CRY_11_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_11_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_13_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_13,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_14,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_12,
+COUT => UN1_PCOUNT_DIFF_1_CRY_14,
+S0 => UN1_PCOUNT_DIFF_1_CRY_13_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_13_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_15_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_15,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_16,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_14,
+COUT => UN1_PCOUNT_DIFF_1_CRY_16,
+S0 => UN1_PCOUNT_DIFF_1_CRY_15_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_15_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_17_0: CCU2C 
+generic map(
+  INIT0 => X"b404",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => N_8,
+B0 => RDIFF_COMP_LOCK(2),
+C0 => UN1_PCOUNT_DIFF_1_CRY_17_0_RNO,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_18,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_16,
+COUT => UN1_PCOUNT_DIFF_1_CRY_18,
+S0 => UN1_PCOUNT_DIFF_1_CRY_17_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_17_0_S1);
+UN1_PCOUNT_DIFF_1_CRY_19_0: CCU2C 
+generic map(
+  INIT0 => X"a003",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN1_PCOUNT_DIFF_1_AXB_19,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN1_PCOUNT_DIFF_1_AXB_20,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_18,
+COUT => UN1_PCOUNT_DIFF_1_CRY_20,
+S0 => UN1_PCOUNT_DIFF_1_CRY_19_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_CRY_19_0_S1);
+UN1_PCOUNT_DIFF_1_S_21_0: CCU2C 
+generic map(
+  INIT0 => X"350a",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => PCOUNT(21),
+B0 => UN13_LOCK_21,
+C0 => N_8,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN1_PCOUNT_DIFF_1_CRY_20,
+COUT => UN1_PCOUNT_DIFF_1_S_21_0_COUT,
+S0 => UN1_PCOUNT_DIFF_1_S_21_0_S0,
+S1 => UN1_PCOUNT_DIFF_1_S_21_0_S1);
+UN13_LOCK_CRY_0_0: CCU2C 
+generic map(
+  INIT0 => X"5003",
+  INIT1 => X"900a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_0,
+B1 => RDIFF_COMP_LOCK(2),
+C1 => VCC,
+D1 => VCC,
+CIN => N_2,
+COUT => UN13_LOCK_CRY_0,
+S0 => UN13_LOCK_CRY_0_0_S0,
+S1 => UN13_LOCK_CRY_0_0_S1);
+UN13_LOCK_CRY_1_0: CCU2C 
+generic map(
+  INIT0 => X"900a",
+  INIT1 => X"900a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_1,
+B0 => RDIFF_COMP_LOCK(2),
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_2,
+B1 => RDIFF_COMP_LOCK(2),
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_0,
+COUT => UN13_LOCK_CRY_2,
+S0 => UN13_LOCK_CRY_1_0_S0,
+S1 => UN13_LOCK_CRY_1_0_S1);
+UN13_LOCK_CRY_3_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_3,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_4,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_2,
+COUT => UN13_LOCK_CRY_4,
+S0 => UN13_LOCK_CRY_3_0_S0,
+S1 => UN13_LOCK_CRY_3_0_S1);
+UN13_LOCK_CRY_5_0: CCU2C 
+generic map(
+  INIT0 => X"900a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_5,
+B0 => RDIFF_COMP_LOCK(2),
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_6,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_4,
+COUT => UN13_LOCK_CRY_6,
+S0 => UN13_LOCK_CRY_5_0_S0,
+S1 => UN13_LOCK_CRY_5_0_S1);
+UN13_LOCK_CRY_7_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_7,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_8,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_6,
+COUT => UN13_LOCK_CRY_8,
+S0 => UN13_LOCK_CRY_7_0_S0,
+S1 => UN13_LOCK_CRY_7_0_S1);
+UN13_LOCK_CRY_9_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_9,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_10,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_8,
+COUT => UN13_LOCK_CRY_10,
+S0 => UN13_LOCK_CRY_9_0_S0,
+S1 => UN13_LOCK_CRY_9_0_S1);
+UN13_LOCK_CRY_11_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_11,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_12,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_10,
+COUT => UN13_LOCK_CRY_12,
+S0 => UN13_LOCK_CRY_11_0_S0,
+S1 => UN13_LOCK_CRY_11_0_S1);
+UN13_LOCK_CRY_13_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_13,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_14,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_12,
+COUT => UN13_LOCK_CRY_14,
+S0 => UN13_LOCK_CRY_13_0_S0,
+S1 => UN13_LOCK_CRY_13_0_S1);
+UN13_LOCK_CRY_15_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_15,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_16,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_14,
+COUT => UN13_LOCK_CRY_16,
+S0 => UN13_LOCK_CRY_15_0_S0,
+S1 => UN13_LOCK_CRY_15_0_S1);
+UN13_LOCK_CRY_17_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_17,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_18,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_16,
+COUT => UN13_LOCK_CRY_18,
+S0 => UN13_LOCK_CRY_17_0_S0,
+S1 => UN13_LOCK_CRY_17_0_S1);
+UN13_LOCK_CRY_19_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_19,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_20,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_18,
+COUT => UN13_LOCK_CRY_20,
+S0 => UN13_LOCK_CRY_19_0_S0,
+S1 => UN13_LOCK_CRY_19_0_S1);
+UN13_LOCK_CRY_21_0: CCU2C 
+generic map(
+  INIT0 => X"500f",
+  INIT1 => X"a003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_21,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_LOCK_CRY_20,
+COUT => UN13_LOCK_CRY_21_0_COUT,
+S0 => UN13_LOCK_CRY_21_0_S0,
+S1 => UN13_LOCK_CRY_21_I);
+UN13_UNLOCK_CRY_0_0: CCU2C 
+generic map(
+  INIT0 => X"5003",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => VCC,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_0,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => N_1,
+COUT => UN13_UNLOCK_CRY_0,
+S0 => UN13_UNLOCK_CRY_0_0_S0,
+S1 => UN13_UNLOCK_CRY_0_0_S1);
+UN13_UNLOCK_CRY_1_0: CCU2C 
+generic map(
+  INIT0 => X"900a",
+  INIT1 => X"900a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_1,
+B0 => RDIFF_COMP_LOCK(2),
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_2,
+B1 => RDIFF_COMP_LOCK(2),
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_0,
+COUT => UN13_UNLOCK_CRY_2,
+S0 => UN13_UNLOCK_CRY_1_0_S0,
+S1 => UN13_UNLOCK_CRY_1_0_S1);
+UN13_UNLOCK_CRY_3_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_3,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_4,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_2,
+COUT => UN13_UNLOCK_CRY_4,
+S0 => UN13_UNLOCK_CRY_3_0_S0,
+S1 => UN13_UNLOCK_CRY_3_0_S1);
+UN13_UNLOCK_CRY_5_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_5,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_6,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_4,
+COUT => UN13_UNLOCK_CRY_6,
+S0 => UN13_UNLOCK_CRY_5_0_S0,
+S1 => UN13_UNLOCK_CRY_5_0_S1);
+UN13_UNLOCK_CRY_7_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"900a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_7,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_8,
+B1 => RDIFF_COMP_LOCK(2),
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_6,
+COUT => UN13_UNLOCK_CRY_8,
+S0 => UN13_UNLOCK_CRY_7_0_S0,
+S1 => UN13_UNLOCK_CRY_7_0_S1);
+UN13_UNLOCK_CRY_9_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_9,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_10,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_8,
+COUT => UN13_UNLOCK_CRY_10,
+S0 => UN13_UNLOCK_CRY_9_0_S0,
+S1 => UN13_UNLOCK_CRY_9_0_S1);
+UN13_UNLOCK_CRY_11_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_11,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_12,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_10,
+COUT => UN13_UNLOCK_CRY_12,
+S0 => UN13_UNLOCK_CRY_11_0_S0,
+S1 => UN13_UNLOCK_CRY_11_0_S1);
+UN13_UNLOCK_CRY_13_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_13,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_14,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_12,
+COUT => UN13_UNLOCK_CRY_14,
+S0 => UN13_UNLOCK_CRY_13_0_S0,
+S1 => UN13_UNLOCK_CRY_13_0_S1);
+UN13_UNLOCK_CRY_15_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_15,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_16,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_14,
+COUT => UN13_UNLOCK_CRY_16,
+S0 => UN13_UNLOCK_CRY_15_0_S0,
+S1 => UN13_UNLOCK_CRY_15_0_S1);
+UN13_UNLOCK_CRY_17_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_17,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_18,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_16,
+COUT => UN13_UNLOCK_CRY_18,
+S0 => UN13_UNLOCK_CRY_17_0_S0,
+S1 => UN13_UNLOCK_CRY_17_0_S1);
+UN13_UNLOCK_CRY_19_0: CCU2C 
+generic map(
+  INIT0 => X"500a",
+  INIT1 => X"500a",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_19,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => UN13_LOCK_20,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_18,
+COUT => UN13_UNLOCK_CRY_20,
+S0 => UN13_UNLOCK_CRY_19_0_S0,
+S1 => UN13_UNLOCK_CRY_19_0_S1);
+UN13_UNLOCK_CRY_21_0: CCU2C 
+generic map(
+  INIT0 => X"500f",
+  INIT1 => X"5003",
+  INJECT1_0 => "NO",
+  INJECT1_1 => "NO"
+)
+port map (
+A0 => UN13_LOCK_21,
+B0 => VCC,
+C0 => VCC,
+D0 => VCC,
+A1 => VCC,
+B1 => VCC,
+C1 => VCC,
+D1 => VCC,
+CIN => UN13_UNLOCK_CRY_20,
+COUT => UN13_UNLOCK_CRY_21_0_COUT,
+S0 => UN13_UNLOCK_CRY_21_0_S0,
+S1 => UN13_UNLOCK_CRY_21);
+PHB_SYNC_INST: sync_0s port map (
+phb => PHB,
+rhb_sync => RHB_SYNC,
+sli_rst => sli_rst,
+pll_refclki => pll_refclki);
+RTC_SYNC_INST: sync_0s_6 port map (
+rtc_pul => RTC_PUL,
+ppul_sync => PPUL_SYNC,
+sli_rst => sli_rst,
+tx_pclk => tx_pclk);
+PDIFF_SYNC_INST: sync_0s_0 port map (
+ppul_sync => PPUL_SYNC,
+pdiff_sync => PDIFF_SYNC,
+sli_rst => sli_rst,
+pll_refclki => pll_refclki);
+VCC_0: VHI port map (
+Z => VCC);
+II_GND: VLO port map (
+Z => GND);
+end beh;
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library synplify;
+use synplify.components.all;
+library pmi;
+use pmi.pmi_components.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity serdes_sync_1 is
+port(
+hdoutp :  out std_logic;
+hdoutn :  out std_logic;
+hdinp :  in std_logic;
+hdinn :  in std_logic;
+rxrefclk :  in std_logic;
+rx_pclk :  out std_logic;
+tx_pclk :  out std_logic;
+txdata : in std_logic_vector(7 downto 0);
+tx_k : in std_logic_vector(0 downto 0);
+tx_force_disp : in std_logic_vector(0 downto 0);
+tx_disp_sel : in std_logic_vector(0 downto 0);
+rxdata : out std_logic_vector(7 downto 0);
+rx_k : out std_logic_vector(0 downto 0);
+rx_disp_err : out std_logic_vector(0 downto 0);
+rx_cv_err : out std_logic_vector(0 downto 0);
+tx_idle_c :  in std_logic;
+signal_detect_c :  in std_logic;
+rx_los_low_s :  out std_logic;
+lsm_status_s :  out std_logic;
+rx_cdr_lol_s :  out std_logic;
+sli_rst :  in std_logic;
+tx_pwrup_c :  in std_logic;
+rx_pwrup_c :  in std_logic;
+sci_wrdata : in std_logic_vector(7 downto 0);
+sci_addr : in std_logic_vector(5 downto 0);
+sci_rddata : out std_logic_vector(7 downto 0);
+sci_en_dual :  in std_logic;
+sci_sel_dual :  in std_logic;
+sci_en :  in std_logic;
+sci_sel :  in std_logic;
+sci_rd :  in std_logic;
+sci_wrn :  in std_logic;
+sci_int :  out std_logic;
+cyawstn :  in std_logic;
+serdes_pdb :  in std_logic;
+pll_refclki :  in std_logic;
+rsl_disable :  in std_logic;
+rsl_rst :  in std_logic;
+serdes_rst_dual_c :  in std_logic;
+rst_dual_c :  in std_logic;
+tx_serdes_rst_c :  in std_logic;
+tx_pcs_rst_c :  in std_logic;
+pll_lol :  out std_logic;
+rsl_tx_rdy :  out std_logic;
+rx_serdes_rst_c :  in std_logic;
+rx_pcs_rst_c :  in std_logic;
+rsl_rx_rdy :  out std_logic);
+end serdes_sync_1;
+
+architecture beh of serdes_sync_1 is
+signal RX_PCLK_11 : std_logic ;
+signal TX_PCLK_12 : std_logic ;
+signal RX_LOS_LOW_S_13 : std_logic ;
+signal RX_CDR_LOL_S_14 : std_logic ;
+signal RSL_TX_PCS_RST_C : std_logic ;
+signal RSL_RX_PCS_RST_C : std_logic ;
+signal RSL_RX_SERDES_RST_C : std_logic ;
+signal RSL_SERDES_RST_DUAL_C : std_logic ;
+signal RSL_TX_SERDES_RST_C : std_logic ;
+signal N50_1 : std_logic ;
+signal N51_1 : std_logic ;
+signal N1_1 : std_logic ;
+signal N2_1 : std_logic ;
+signal N3_1 : std_logic ;
+signal N4_1 : std_logic ;
+signal N5_1 : std_logic ;
+signal N52_1 : std_logic ;
+signal N6_1 : std_logic ;
+signal N53_1 : std_logic ;
+signal N7_1 : std_logic ;
+signal N54_1 : std_logic ;
+signal N8_1 : std_logic ;
+signal N55_1 : std_logic ;
+signal N56_1 : std_logic ;
+signal N57_1 : std_logic ;
+signal N58_1 : std_logic ;
+signal N59_1 : std_logic ;
+signal N60_1 : std_logic ;
+signal N61_1 : std_logic ;
+signal N62_1 : std_logic ;
+signal N63_1 : std_logic ;
+signal N64_1 : std_logic ;
+signal N65_1 : std_logic ;
+signal N66_1 : std_logic ;
+signal N67_1 : std_logic ;
+signal N68_1 : std_logic ;
+signal N9_1 : std_logic ;
+signal N69_1 : std_logic ;
+signal N70_1 : std_logic ;
+signal N71_1 : std_logic ;
+signal N72_1 : std_logic ;
+signal N73_1 : std_logic ;
+signal N74_1 : std_logic ;
+signal N75_1 : std_logic ;
+signal N76_1 : std_logic ;
+signal N77_1 : std_logic ;
+signal N78_1 : std_logic ;
+signal N79_1 : std_logic ;
+signal N80_1 : std_logic ;
+signal N81_1 : std_logic ;
+signal N82_1 : std_logic ;
+signal N83_1 : std_logic ;
+signal N84_1 : std_logic ;
+signal N85_1 : std_logic ;
+signal N86_1 : std_logic ;
+signal N87_1 : std_logic ;
+signal N88_1 : std_logic ;
+signal N89_1 : std_logic ;
+signal N90_1 : std_logic ;
+signal N91_1 : std_logic ;
+signal N10_1 : std_logic ;
+signal N92_1 : std_logic ;
+signal N11_1 : std_logic ;
+signal N93_1 : std_logic ;
+signal N12_1 : std_logic ;
+signal N94_1 : std_logic ;
+signal N95_1 : std_logic ;
+signal N96_1 : std_logic ;
+signal N13_1 : std_logic ;
+signal N97_1 : std_logic ;
+signal N14_1 : std_logic ;
+signal N98_1 : std_logic ;
+signal N15_1 : std_logic ;
+signal N99_1 : std_logic ;
+signal N16_1 : std_logic ;
+signal N100_1 : std_logic ;
+signal N101_1 : std_logic ;
+signal N17_1 : std_logic ;
+signal N102_1 : std_logic ;
+signal N18_1 : std_logic ;
+signal N103_1 : std_logic ;
+signal N104_1 : std_logic ;
+signal N115_1 : std_logic ;
+signal N19_1 : std_logic ;
+signal N20_1 : std_logic ;
+signal N21_1 : std_logic ;
+signal N22_1 : std_logic ;
+signal N23_1 : std_logic ;
+signal N24_1 : std_logic ;
+signal N25_1 : std_logic ;
+signal N26_1 : std_logic ;
+signal N27_1 : std_logic ;
+signal N28_1 : std_logic ;
+signal N29_1 : std_logic ;
+signal N30_1 : std_logic ;
+signal N31_1 : std_logic ;
+signal N32_1 : std_logic ;
+signal N33_1 : std_logic ;
+signal N34_1 : std_logic ;
+signal N35_1 : std_logic ;
+signal N36_1 : std_logic ;
+signal N37_1 : std_logic ;
+signal N38_1 : std_logic ;
+signal N39_1 : std_logic ;
+signal N40_1 : std_logic ;
+signal N41_1 : std_logic ;
+signal N42_1 : std_logic ;
+signal N43_1 : std_logic ;
+signal N44_1 : std_logic ;
+signal N45_1 : std_logic ;
+signal N46_1 : std_logic ;
+signal N49_1 : std_logic ;
+signal TX_PCLK_I : std_logic ;
+signal GND : std_logic ;
+signal VCC : std_logic ;
+signal \SLL_INST.PLL_LOCK_I_15\ : std_logic ;
+component serdes_sync_1sll_core_Z1_layer1
+port(
+tx_pclk :  in std_logic;
+sli_rst :  in std_logic;
+pll_refclki :  in std_logic;
+pll_lock_i :  out std_logic  );
+end component;
+component serdes_sync_1rsl_core_Z2_layer1
+port(
+rx_pcs_rst_c :  in std_logic;
+serdes_rst_dual_c :  in std_logic;
+tx_serdes_rst_c :  in std_logic;
+rsl_tx_pcs_rst_c :  out std_logic;
+rst_dual_c :  in std_logic;
+rsl_rx_pcs_rst_c :  out std_logic;
+rsl_tx_serdes_rst_c :  out std_logic;
+rsl_tx_rdy :  out std_logic;
+pll_lock_i :  in std_logic;
+pll_refclki :  in std_logic;
+rsl_rx_rdy :  out std_logic;
+rx_cdr_lol_s :  in std_logic;
+rx_los_low_s :  in std_logic;
+rsl_rst :  in std_logic;
+rxrefclk :  in std_logic;
+rx_serdes_rst_c :  in std_logic;
+rsl_rx_serdes_rst_c :  out std_logic;
+rsl_serdes_rst_dual_c :  out std_logic;
+rsl_disable :  in std_logic;
+tx_pcs_rst_c :  in std_logic  );
+end component;
+begin
+GND_0: VLO port map (
+Z => GND);
+VCC_0: VHI port map (
+Z => VCC);
+PUR_INST: PUR port map (
+PUR => VCC);
+GSR_INST: GSR port map (
+GSR => VCC);
+TX_PCLK_12 <= TX_PCLK_I;
+DCU0_INST: DCUA 
+generic map( 
+  D_MACROPDB => "0b1", 
+  D_IB_PWDNB => "0b1", 
+  D_XGE_MODE => "0b0", 
+  D_LOW_MARK => "0d4", 
+  D_HIGH_MARK => "0d12", 
+  D_BUS8BIT_SEL => "0b0", 
+  D_CDR_LOL_SET => "0b11", 
+  D_BITCLK_LOCAL_EN => "0b1", 
+  D_BITCLK_ND_EN => "0b0", 
+  D_BITCLK_FROM_ND_EN => "0b0", 
+  D_SYNC_LOCAL_EN => "0b1", 
+  D_SYNC_ND_EN => "0b0", 
+  CH0_UC_MODE => "0b1", 
+  CH0_PCIE_MODE => "0b0", 
+  CH0_RIO_MODE => "0b0", 
+  CH0_WA_MODE => "0b0", 
+  CH0_INVERT_RX => "0b0", 
+  CH0_INVERT_TX => "0b0", 
+  CH0_PRBS_SELECTION => "0b0", 
+  CH0_GE_AN_ENABLE => "0b0", 
+  CH0_PRBS_LOCK => "0b0", 
+  CH0_PRBS_ENABLE => "0b0", 
+  CH0_ENABLE_CG_ALIGN => "0b1", 
+  CH0_TX_GEAR_MODE => "0b0", 
+  CH0_RX_GEAR_MODE => "0b0", 
+  CH0_PCS_DET_TIME_SEL => "0b00", 
+  CH0_PCIE_EI_EN => "0b0", 
+  CH0_TX_GEAR_BYPASS => "0b0", 
+  CH0_ENC_BYPASS => "0b0", 
+  CH0_SB_BYPASS => "0b0", 
+  CH0_RX_SB_BYPASS => "0b0", 
+  CH0_WA_BYPASS => "0b0", 
+  CH0_DEC_BYPASS => "0b0", 
+  CH0_CTC_BYPASS => "0b1", 
+  CH0_RX_GEAR_BYPASS => "0b0", 
+  CH0_LSM_DISABLE => "0b0", 
+  CH0_MATCH_2_ENABLE => "0b0", 
+  CH0_MATCH_4_ENABLE => "0b1", 
+  CH0_MIN_IPG_CNT => "0b11", 
+  CH0_CC_MATCH_1 => "0x1BC", 
+  CH0_CC_MATCH_2 => "0x11C", 
+  CH0_CC_MATCH_3 => "0x11C", 
+  CH0_CC_MATCH_4 => "0x11C", 
+  CH0_UDF_COMMA_MASK => "0x0ff", 
+  CH0_UDF_COMMA_A => "0x083", 
+  CH0_UDF_COMMA_B => "0x07C", 
+  CH0_RX_DCO_CK_DIV => "0b010", 
+  CH0_RCV_DCC_EN => "0b0", 
+  CH0_REQ_LVL_SET => "0b00", 
+  CH0_REQ_EN => "0b1", 
+  CH0_RTERM_RX => "0d22", 
+  CH0_PDEN_SEL => "0b1", 
+  CH0_LDR_RX2CORE_SEL => "0b0", 
+  CH0_LDR_CORE2TX_SEL => "0b0", 
+  CH0_TPWDNB => "0b1", 
+  CH0_RATE_MODE_TX => "0b0", 
+  CH0_RTERM_TX => "0d19", 
+  CH0_TX_CM_SEL => "0b00", 
+  CH0_TDRV_PRE_EN => "0b0", 
+  CH0_TDRV_SLICE0_SEL => "0b00", 
+  CH0_TDRV_SLICE1_SEL => "0b00", 
+  CH0_TDRV_SLICE2_SEL => "0b01", 
+  CH0_TDRV_SLICE3_SEL => "0b01", 
+  CH0_TDRV_SLICE4_SEL => "0b01", 
+  CH0_TDRV_SLICE5_SEL => "0b00", 
+  CH0_TDRV_SLICE0_CUR => "0b000", 
+  CH0_TDRV_SLICE1_CUR => "0b000", 
+  CH0_TDRV_SLICE2_CUR => "0b11", 
+  CH0_TDRV_SLICE3_CUR => "0b11", 
+  CH0_TDRV_SLICE4_CUR => "0b01", 
+  CH0_TDRV_SLICE5_CUR => "0b00", 
+  CH0_TDRV_DAT_SEL => "0b00", 
+  CH0_TX_DIV11_SEL => "0b0", 
+  CH0_RPWDNB => "0b1", 
+  CH0_RATE_MODE_RX => "0b0", 
+  CH0_RLOS_SEL => "0b1", 
+  CH0_RX_LOS_LVL => "0b100", 
+  CH0_RX_LOS_CEQ => "0b11", 
+  CH0_RX_LOS_HYST_EN => "0b0", 
+  CH0_RX_LOS_EN => "0b1", 
+  CH0_RX_DIV11_SEL => "0b0", 
+  CH0_SEL_SD_RX_CLK => "0b1", 
+  CH0_FF_RX_H_CLK_EN => "0b0", 
+  CH0_FF_RX_F_CLK_DIS => "0b0", 
+  CH0_FF_TX_H_CLK_EN => "0b0", 
+  CH0_FF_TX_F_CLK_DIS => "0b0", 
+  CH0_RX_RATE_SEL => "0d10", 
+  CH0_TDRV_POST_EN => "0b0", 
+  CH0_TX_POST_SIGN => "0b0", 
+  CH0_TX_PRE_SIGN => "0b0", 
+  CH0_RXTERM_CM => "0b11", 
+  CH0_RXIN_CM => "0b11", 
+  CH0_LEQ_OFFSET_SEL => "0b0", 
+  CH0_LEQ_OFFSET_TRIM => "0b000", 
+  D_TX_MAX_RATE => "1.25", 
+  CH0_CDR_MAX_RATE => "1.25", 
+  CH0_TXAMPLITUDE => "0d800", 
+  CH0_TXDEPRE => "DISABLED", 
+  CH0_TXDEPOST => "DISABLED", 
+  CH0_PROTOCOL => "G8B10B", 
+  D_ISETLOS => "0d0", 
+  D_SETIRPOLY_AUX => "0b00", 
+  D_SETICONST_AUX => "0b00", 
+  D_SETIRPOLY_CH => "0b00", 
+  D_SETICONST_CH => "0b00", 
+  D_REQ_ISET => "0b000", 
+  D_PD_ISET => "0b00", 
+  D_DCO_CALIB_TIME_SEL => "0b00", 
+  CH0_DCOCTLGI => "0b010", 
+  CH0_DCOATDDLY => "0b00", 
+  CH0_DCOATDCFG => "0b00", 
+  CH0_DCOBYPSATD => "0b1", 
+  CH0_DCOSCALEI => "0b00", 
+  CH0_DCOITUNE4LSB => "0b111", 
+  CH0_DCOIOSTUNE => "0b000", 
+  CH0_DCODISBDAVOID => "0b0", 
+  CH0_DCOCALDIV => "0b001", 
+  CH0_DCONUOFLSB => "0b101", 
+  CH0_DCOIUPDNX2 => "0b1", 
+  CH0_DCOSTEP => "0b00", 
+  CH0_DCOSTARTVAL => "0b000", 
+  CH0_DCOFLTDAC => "0b01", 
+  CH0_DCOITUNE => "0b00", 
+  CH0_DCOFTNRG => "0b110", 
+  CH0_CDR_CNT4SEL => "0b00", 
+  CH0_CDR_CNT8SEL => "0b00", 
+  CH0_BAND_THRESHOLD => "0d0", 
+  CH0_AUTO_FACQ_EN => "0b1", 
+  CH0_AUTO_CALIB_EN => "0b1", 
+  CH0_CALIB_CK_MODE => "0b0", 
+  CH0_REG_BAND_OFFSET => "0d0", 
+  CH0_REG_BAND_SEL => "0d0", 
+  CH0_REG_IDAC_SEL => "0d0", 
+  CH0_REG_IDAC_EN => "0b0", 
+  D_TXPLL_PWDNB => "0b1", 
+  D_SETPLLRC => "0d1", 
+  D_REFCK_MODE => "0b001", 
+  D_TX_VCO_CK_DIV => "0b010", 
+  D_PLL_LOL_SET => "0b01", 
+  D_RG_EN => "0b0", 
+  D_RG_SET => "0b00", 
+  D_CMUSETISCL4VCO => "0b000", 
+  D_CMUSETI4VCO => "0b00", 
+  D_CMUSETINITVCT => "0b00", 
+  D_CMUSETZGM => "0b000", 
+  D_CMUSETP2AGM => "0b000", 
+  D_CMUSETP1GM => "0b000", 
+  D_CMUSETI4CPZ => "0d0", 
+  D_CMUSETI4CPP => "0d0", 
+  D_CMUSETICP4Z => "0b101", 
+  D_CMUSETICP4P => "0b11", 
+  D_CMUSETBIASI => "0b00"
+) 
+port map (
+CH0_HDINP => hdinp,
+CH1_HDINP => GND,
+CH0_HDINN => hdinn,
+CH1_HDINN => GND,
+D_TXBIT_CLKP_FROM_ND => GND,
+D_TXBIT_CLKN_FROM_ND => GND,
+D_SYNC_ND => GND,
+D_TXPLL_LOL_FROM_ND => GND,
+CH0_RX_REFCLK => rxrefclk,
+CH1_RX_REFCLK => GND,
+CH0_FF_RXI_CLK => RX_PCLK_11,
+CH1_FF_RXI_CLK => VCC,
+CH0_FF_TXI_CLK => TX_PCLK_12,
+CH1_FF_TXI_CLK => VCC,
+CH0_FF_EBRD_CLK => VCC,
+CH1_FF_EBRD_CLK => VCC,
+CH0_FF_TX_D_0 => txdata(0),
+CH1_FF_TX_D_0 => GND,
+CH0_FF_TX_D_1 => txdata(1),
+CH1_FF_TX_D_1 => GND,
+CH0_FF_TX_D_2 => txdata(2),
+CH1_FF_TX_D_2 => GND,
+CH0_FF_TX_D_3 => txdata(3),
+CH1_FF_TX_D_3 => GND,
+CH0_FF_TX_D_4 => txdata(4),
+CH1_FF_TX_D_4 => GND,
+CH0_FF_TX_D_5 => txdata(5),
+CH1_FF_TX_D_5 => GND,
+CH0_FF_TX_D_6 => txdata(6),
+CH1_FF_TX_D_6 => GND,
+CH0_FF_TX_D_7 => txdata(7),
+CH1_FF_TX_D_7 => GND,
+CH0_FF_TX_D_8 => tx_k(0),
+CH1_FF_TX_D_8 => GND,
+CH0_FF_TX_D_9 => tx_force_disp(0),
+CH1_FF_TX_D_9 => GND,
+CH0_FF_TX_D_10 => tx_disp_sel(0),
+CH1_FF_TX_D_10 => GND,
+CH0_FF_TX_D_11 => GND,
+CH1_FF_TX_D_11 => GND,
+CH0_FF_TX_D_12 => GND,
+CH1_FF_TX_D_12 => GND,
+CH0_FF_TX_D_13 => GND,
+CH1_FF_TX_D_13 => GND,
+CH0_FF_TX_D_14 => GND,
+CH1_FF_TX_D_14 => GND,
+CH0_FF_TX_D_15 => GND,
+CH1_FF_TX_D_15 => GND,
+CH0_FF_TX_D_16 => GND,
+CH1_FF_TX_D_16 => GND,
+CH0_FF_TX_D_17 => GND,
+CH1_FF_TX_D_17 => GND,
+CH0_FF_TX_D_18 => GND,
+CH1_FF_TX_D_18 => GND,
+CH0_FF_TX_D_19 => GND,
+CH1_FF_TX_D_19 => GND,
+CH0_FF_TX_D_20 => GND,
+CH1_FF_TX_D_20 => GND,
+CH0_FF_TX_D_21 => GND,
+CH1_FF_TX_D_21 => GND,
+CH0_FF_TX_D_22 => GND,
+CH1_FF_TX_D_22 => GND,
+CH0_FF_TX_D_23 => GND,
+CH1_FF_TX_D_23 => GND,
+CH0_FFC_EI_EN => tx_idle_c,
+CH1_FFC_EI_EN => GND,
+CH0_FFC_PCIE_DET_EN => GND,
+CH1_FFC_PCIE_DET_EN => GND,
+CH0_FFC_PCIE_CT => GND,
+CH1_FFC_PCIE_CT => GND,
+CH0_FFC_SB_INV_RX => GND,
+CH1_FFC_SB_INV_RX => GND,
+CH0_FFC_ENABLE_CGALIGN => GND,
+CH1_FFC_ENABLE_CGALIGN => GND,
+CH0_FFC_SIGNAL_DETECT => signal_detect_c,
+CH1_FFC_SIGNAL_DETECT => GND,
+CH0_FFC_FB_LOOPBACK => GND,
+CH1_FFC_FB_LOOPBACK => GND,
+CH0_FFC_SB_PFIFO_LP => GND,
+CH1_FFC_SB_PFIFO_LP => GND,
+CH0_FFC_PFIFO_CLR => GND,
+CH1_FFC_PFIFO_CLR => GND,
+CH0_FFC_RATE_MODE_RX => GND,
+CH1_FFC_RATE_MODE_RX => GND,
+CH0_FFC_RATE_MODE_TX => GND,
+CH1_FFC_RATE_MODE_TX => GND,
+CH0_FFC_DIV11_MODE_RX => GND,
+CH1_FFC_DIV11_MODE_RX => GND,
+CH0_FFC_RX_GEAR_MODE => GND,
+CH1_FFC_RX_GEAR_MODE => GND,
+CH0_FFC_TX_GEAR_MODE => GND,
+CH1_FFC_TX_GEAR_MODE => GND,
+CH0_FFC_DIV11_MODE_TX => GND,
+CH1_FFC_DIV11_MODE_TX => GND,
+CH0_FFC_LDR_CORE2TX_EN => GND,
+CH1_FFC_LDR_CORE2TX_EN => GND,
+CH0_FFC_LANE_TX_RST => RSL_TX_PCS_RST_C,
+CH1_FFC_LANE_TX_RST => GND,
+CH0_FFC_LANE_RX_RST => RSL_RX_PCS_RST_C,
+CH1_FFC_LANE_RX_RST => GND,
+CH0_FFC_RRST => RSL_RX_SERDES_RST_C,
+CH1_FFC_RRST => GND,
+CH0_FFC_TXPWDNB => tx_pwrup_c,
+CH1_FFC_TXPWDNB => GND,
+CH0_FFC_RXPWDNB => rx_pwrup_c,
+CH1_FFC_RXPWDNB => GND,
+CH0_LDR_CORE2TX => GND,
+CH1_LDR_CORE2TX => GND,
+D_SCIWDATA0 => sci_wrdata(0),
+D_SCIWDATA1 => sci_wrdata(1),
+D_SCIWDATA2 => sci_wrdata(2),
+D_SCIWDATA3 => sci_wrdata(3),
+D_SCIWDATA4 => sci_wrdata(4),
+D_SCIWDATA5 => sci_wrdata(5),
+D_SCIWDATA6 => sci_wrdata(6),
+D_SCIWDATA7 => sci_wrdata(7),
+D_SCIADDR0 => sci_addr(0),
+D_SCIADDR1 => sci_addr(1),
+D_SCIADDR2 => sci_addr(2),
+D_SCIADDR3 => sci_addr(3),
+D_SCIADDR4 => sci_addr(4),
+D_SCIADDR5 => sci_addr(5),
+D_SCIENAUX => sci_en_dual,
+D_SCISELAUX => sci_sel_dual,
+CH0_SCIEN => sci_en,
+CH1_SCIEN => GND,
+CH0_SCISEL => sci_sel,
+CH1_SCISEL => GND,
+D_SCIRD => sci_rd,
+D_SCIWSTN => sci_wrn,
+D_CYAWSTN => cyawstn,
+D_FFC_SYNC_TOGGLE => GND,
+D_FFC_DUAL_RST => rst_dual_c,
+D_FFC_MACRO_RST => RSL_SERDES_RST_DUAL_C,
+D_FFC_MACROPDB => serdes_pdb,
+D_FFC_TRST => RSL_TX_SERDES_RST_C,
+CH0_FFC_CDR_EN_BITSLIP => GND,
+CH1_FFC_CDR_EN_BITSLIP => GND,
+D_SCAN_ENABLE => GND,
+D_SCAN_IN_0 => GND,
+D_SCAN_IN_1 => GND,
+D_SCAN_IN_2 => GND,
+D_SCAN_IN_3 => GND,
+D_SCAN_IN_4 => GND,
+D_SCAN_IN_5 => GND,
+D_SCAN_IN_6 => GND,
+D_SCAN_IN_7 => GND,
+D_SCAN_MODE => GND,
+D_SCAN_RESET => GND,
+D_CIN0 => GND,
+D_CIN1 => GND,
+D_CIN2 => GND,
+D_CIN3 => GND,
+D_CIN4 => GND,
+D_CIN5 => GND,
+D_CIN6 => GND,
+D_CIN7 => GND,
+D_CIN8 => GND,
+D_CIN9 => GND,
+D_CIN10 => GND,
+D_CIN11 => GND,
+CH0_HDOUTP => hdoutp,
+CH1_HDOUTP => N50_1,
+CH0_HDOUTN => hdoutn,
+CH1_HDOUTN => N51_1,
+D_TXBIT_CLKP_TO_ND => N1_1,
+D_TXBIT_CLKN_TO_ND => N2_1,
+D_SYNC_PULSE2ND => N3_1,
+D_TXPLL_LOL_TO_ND => N4_1,
+CH0_FF_RX_F_CLK => N5_1,
+CH1_FF_RX_F_CLK => N52_1,
+CH0_FF_RX_H_CLK => N6_1,
+CH1_FF_RX_H_CLK => N53_1,
+CH0_FF_TX_F_CLK => N7_1,
+CH1_FF_TX_F_CLK => N54_1,
+CH0_FF_TX_H_CLK => N8_1,
+CH1_FF_TX_H_CLK => N55_1,
+CH0_FF_RX_PCLK => RX_PCLK_11,
+CH1_FF_RX_PCLK => N56_1,
+CH0_FF_TX_PCLK => TX_PCLK_I,
+CH1_FF_TX_PCLK => N57_1,
+CH0_FF_RX_D_0 => rxdata(0),
+CH1_FF_RX_D_0 => N58_1,
+CH0_FF_RX_D_1 => rxdata(1),
+CH1_FF_RX_D_1 => N59_1,
+CH0_FF_RX_D_2 => rxdata(2),
+CH1_FF_RX_D_2 => N60_1,
+CH0_FF_RX_D_3 => rxdata(3),
+CH1_FF_RX_D_3 => N61_1,
+CH0_FF_RX_D_4 => rxdata(4),
+CH1_FF_RX_D_4 => N62_1,
+CH0_FF_RX_D_5 => rxdata(5),
+CH1_FF_RX_D_5 => N63_1,
+CH0_FF_RX_D_6 => rxdata(6),
+CH1_FF_RX_D_6 => N64_1,
+CH0_FF_RX_D_7 => rxdata(7),
+CH1_FF_RX_D_7 => N65_1,
+CH0_FF_RX_D_8 => rx_k(0),
+CH1_FF_RX_D_8 => N66_1,
+CH0_FF_RX_D_9 => rx_disp_err(0),
+CH1_FF_RX_D_9 => N67_1,
+CH0_FF_RX_D_10 => rx_cv_err(0),
+CH1_FF_RX_D_10 => N68_1,
+CH0_FF_RX_D_11 => N9_1,
+CH1_FF_RX_D_11 => N69_1,
+CH0_FF_RX_D_12 => N70_1,
+CH1_FF_RX_D_12 => N71_1,
+CH0_FF_RX_D_13 => N72_1,
+CH1_FF_RX_D_13 => N73_1,
+CH0_FF_RX_D_14 => N74_1,
+CH1_FF_RX_D_14 => N75_1,
+CH0_FF_RX_D_15 => N76_1,
+CH1_FF_RX_D_15 => N77_1,
+CH0_FF_RX_D_16 => N78_1,
+CH1_FF_RX_D_16 => N79_1,
+CH0_FF_RX_D_17 => N80_1,
+CH1_FF_RX_D_17 => N81_1,
+CH0_FF_RX_D_18 => N82_1,
+CH1_FF_RX_D_18 => N83_1,
+CH0_FF_RX_D_19 => N84_1,
+CH1_FF_RX_D_19 => N85_1,
+CH0_FF_RX_D_20 => N86_1,
+CH1_FF_RX_D_20 => N87_1,
+CH0_FF_RX_D_21 => N88_1,
+CH1_FF_RX_D_21 => N89_1,
+CH0_FF_RX_D_22 => N90_1,
+CH1_FF_RX_D_22 => N91_1,
+CH0_FF_RX_D_23 => N10_1,
+CH1_FF_RX_D_23 => N92_1,
+CH0_FFS_PCIE_DONE => N11_1,
+CH1_FFS_PCIE_DONE => N93_1,
+CH0_FFS_PCIE_CON => N12_1,
+CH1_FFS_PCIE_CON => N94_1,
+CH0_FFS_RLOS => RX_LOS_LOW_S_13,
+CH1_FFS_RLOS => N95_1,
+CH0_FFS_LS_SYNC_STATUS => lsm_status_s,
+CH1_FFS_LS_SYNC_STATUS => N96_1,
+CH0_FFS_CC_UNDERRUN => N13_1,
+CH1_FFS_CC_UNDERRUN => N97_1,
+CH0_FFS_CC_OVERRUN => N14_1,
+CH1_FFS_CC_OVERRUN => N98_1,
+CH0_FFS_RXFBFIFO_ERROR => N15_1,
+CH1_FFS_RXFBFIFO_ERROR => N99_1,
+CH0_FFS_TXFBFIFO_ERROR => N16_1,
+CH1_FFS_TXFBFIFO_ERROR => N100_1,
+CH0_FFS_RLOL => RX_CDR_LOL_S_14,
+CH1_FFS_RLOL => N101_1,
+CH0_FFS_SKP_ADDED => N17_1,
+CH1_FFS_SKP_ADDED => N102_1,
+CH0_FFS_SKP_DELETED => N18_1,
+CH1_FFS_SKP_DELETED => N103_1,
+CH0_LDR_RX2CORE => N104_1,
+CH1_LDR_RX2CORE => N115_1,
+D_SCIRDATA0 => sci_rddata(0),
+D_SCIRDATA1 => sci_rddata(1),
+D_SCIRDATA2 => sci_rddata(2),
+D_SCIRDATA3 => sci_rddata(3),
+D_SCIRDATA4 => sci_rddata(4),
+D_SCIRDATA5 => sci_rddata(5),
+D_SCIRDATA6 => sci_rddata(6),
+D_SCIRDATA7 => sci_rddata(7),
+D_SCIINT => sci_int,
+D_SCAN_OUT_0 => N19_1,
+D_SCAN_OUT_1 => N20_1,
+D_SCAN_OUT_2 => N21_1,
+D_SCAN_OUT_3 => N22_1,
+D_SCAN_OUT_4 => N23_1,
+D_SCAN_OUT_5 => N24_1,
+D_SCAN_OUT_6 => N25_1,
+D_SCAN_OUT_7 => N26_1,
+D_COUT0 => N27_1,
+D_COUT1 => N28_1,
+D_COUT2 => N29_1,
+D_COUT3 => N30_1,
+D_COUT4 => N31_1,
+D_COUT5 => N32_1,
+D_COUT6 => N33_1,
+D_COUT7 => N34_1,
+D_COUT8 => N35_1,
+D_COUT9 => N36_1,
+D_COUT10 => N37_1,
+D_COUT11 => N38_1,
+D_COUT12 => N39_1,
+D_COUT13 => N40_1,
+D_COUT14 => N41_1,
+D_COUT15 => N42_1,
+D_COUT16 => N43_1,
+D_COUT17 => N44_1,
+D_COUT18 => N45_1,
+D_COUT19 => N46_1,
+D_REFCLKI => pll_refclki,
+D_FFS_PLOL => N49_1);
+SLL_INST: serdes_sync_1sll_core_Z1_layer1 port map (
+tx_pclk => TX_PCLK_12,
+sli_rst => sli_rst,
+pll_refclki => pll_refclki,
+pll_lock_i => \SLL_INST.PLL_LOCK_I_15\);
+RSL_INST: serdes_sync_1rsl_core_Z2_layer1 port map (
+rx_pcs_rst_c => rx_pcs_rst_c,
+serdes_rst_dual_c => serdes_rst_dual_c,
+tx_serdes_rst_c => tx_serdes_rst_c,
+rsl_tx_pcs_rst_c => RSL_TX_PCS_RST_C,
+rst_dual_c => rst_dual_c,
+rsl_rx_pcs_rst_c => RSL_RX_PCS_RST_C,
+rsl_tx_serdes_rst_c => RSL_TX_SERDES_RST_C,
+rsl_tx_rdy => rsl_tx_rdy,
+pll_lock_i => \SLL_INST.PLL_LOCK_I_15\,
+pll_refclki => pll_refclki,
+rsl_rx_rdy => rsl_rx_rdy,
+rx_cdr_lol_s => RX_CDR_LOL_S_14,
+rx_los_low_s => RX_LOS_LOW_S_13,
+rsl_rst => rsl_rst,
+rxrefclk => rxrefclk,
+rx_serdes_rst_c => rx_serdes_rst_c,
+rsl_rx_serdes_rst_c => RSL_RX_SERDES_RST_C,
+rsl_serdes_rst_dual_c => RSL_SERDES_RST_DUAL_C,
+rsl_disable => rsl_disable,
+tx_pcs_rst_c => tx_pcs_rst_c);
+rx_pclk <= RX_PCLK_11;
+tx_pclk <= TX_PCLK_12;
+rx_los_low_s <= RX_LOS_LOW_S_13;
+rx_cdr_lol_s <= RX_CDR_LOL_S_14;
+pll_lol <= \SLL_INST.PLL_LOCK_I_15\;
+end beh;
+

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.vm b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.vm
new file mode 100644 (file)
index 0000000..8c03aad
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.vm
@@ -0,0 +1,6580 @@
+//
+// Written by Synplify Pro 
+// Product Version "M-2017.03L-SP1-1"
+// Program "Synplify Pro", Mapper "maplat, Build 1796R"
+// Fri May 10 10:23:37 2019
+//
+// Source file index table:
+// Object locations will have the form <file>:<line>
+// file 0 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd "
+// file 1 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd "
+// file 2 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd "
+// file 3 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd "
+// file 4 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd "
+// file 5 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd "
+// file 6 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd "
+// file 7 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd "
+// file 8 "\/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd "
+// file 9 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd "
+// file 10 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v "
+// file 11 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v "
+// file 12 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v "
+// file 13 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v "
+// file 14 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v "
+// file 15 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh "
+// file 16 "\/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v "
+// file 17 "\/home/soft/lattice/diamond/3.10_x64/synpbase/lib/nlconst.dat "
+// file 18 "\/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc "
+
+`timescale 100 ps/100 ps
+module sync_0s (
+  phb,
+  rhb_sync,
+  sli_rst,
+  pll_refclki
+)
+;
+input phb ;
+output rhb_sync ;
+input sli_rst ;
+input pll_refclki ;
+wire phb ;
+wire rhb_sync ;
+wire sli_rst ;
+wire pll_refclki ;
+wire data_p1 ;
+wire data_p2_QN_0 ;
+wire VCC ;
+wire data_p1_QN_0 ;
+wire GND ;
+// @16:1988
+  FD1S3DX data_p2 (
+       .D(data_p1),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_sync)
+);
+// @16:1988
+  FD1S3DX data_p1_reg (
+       .D(phb),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(data_p1)
+);
+  VHI VCC_0 (
+       .Z(VCC)
+);
+// @16:865
+  VLO GND_cZ (
+       .Z(GND)
+);
+endmodule /* sync_0s */
+
+module sync_0s_6 (
+  rtc_pul,
+  ppul_sync,
+  sli_rst,
+  tx_pclk
+)
+;
+input rtc_pul ;
+output ppul_sync ;
+input sli_rst ;
+input tx_pclk ;
+wire rtc_pul ;
+wire ppul_sync ;
+wire sli_rst ;
+wire tx_pclk ;
+wire data_p1 ;
+wire data_p2_QN ;
+wire VCC ;
+wire data_p1_QN ;
+wire GND ;
+// @16:1988
+  FD1S3DX data_p2 (
+       .D(data_p1),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(ppul_sync)
+);
+// @16:1988
+  FD1S3DX data_p1_reg (
+       .D(rtc_pul),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(data_p1)
+);
+  VHI VCC_0 (
+       .Z(VCC)
+);
+// @16:865
+  VLO GND_cZ (
+       .Z(GND)
+);
+endmodule /* sync_0s_6 */
+
+module sync_0s_0 (
+  ppul_sync,
+  pdiff_sync,
+  sli_rst,
+  pll_refclki
+)
+;
+input ppul_sync ;
+output pdiff_sync ;
+input sli_rst ;
+input pll_refclki ;
+wire ppul_sync ;
+wire pdiff_sync ;
+wire sli_rst ;
+wire pll_refclki ;
+wire data_p1 ;
+wire data_p2_QN_1 ;
+wire VCC ;
+wire data_p1_QN_1 ;
+wire GND ;
+// @16:1988
+  FD1S3DX data_p2 (
+       .D(data_p1),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(pdiff_sync)
+);
+// @16:1988
+  FD1S3DX data_p1_reg (
+       .D(ppul_sync),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(data_p1)
+);
+  VHI VCC_0 (
+       .Z(VCC)
+);
+// @16:865
+  VLO GND_cZ (
+       .Z(GND)
+);
+endmodule /* sync_0s_0 */
+
+module serdes_sync_1sll_core_Z1_layer1 (
+  tx_pclk,
+  sli_rst,
+  pll_refclki,
+  pll_lock_i
+)
+;
+input tx_pclk ;
+input sli_rst ;
+input pll_refclki ;
+output pll_lock_i ;
+wire tx_pclk ;
+wire sli_rst ;
+wire pll_refclki ;
+wire pll_lock_i ;
+wire [2:0] phb_cnt;
+wire [2:0] phb_cnt_i;
+wire [15:0] rcount;
+wire [21:0] pcount;
+wire [0:0] un1_pcount_diff_i;
+wire [1:1] sll_state;
+wire [1:1] sll_state_QN;
+wire [7:0] rhb_wait_cnt_s;
+wire [7:0] rhb_wait_cnt;
+wire [7:0] rhb_wait_cnt_QN;
+wire [15:0] rcount_s;
+wire [15:0] rcount_QN;
+wire [2:0] phb_cnt_QN;
+wire [2:1] phb_cnt_RNO;
+wire [21:0] pcount_diff_QN;
+wire [21:0] pcount_s;
+wire [21:0] pcount_QN;
+wire [2:2] rdiff_comp_lock;
+wire [2:2] rdiff_comp_lock_QN;
+wire [1:1] sll_state_ns_i_0_m3;
+wire [0:0] un1_pcount_diff;
+wire [20:0] pcount_cry;
+wire [0:0] pcount_cry_0_S0;
+wire [21:21] pcount_s_0_COUT;
+wire [21:21] pcount_s_0_S1;
+wire [14:0] rcount_cry;
+wire [0:0] rcount_cry_0_S0;
+wire [15:15] rcount_s_0_COUT;
+wire [15:15] rcount_s_0_S1;
+wire [6:0] rhb_wait_cnt_cry;
+wire [0:0] rhb_wait_cnt_cry_0_S0;
+wire [7:7] rhb_wait_cnt_s_0_COUT;
+wire [7:7] rhb_wait_cnt_s_0_S1;
+wire pll_lock ;
+wire rtc_ctrl4_0_a3_1 ;
+wire un13_lock_20 ;
+wire ppul_sync_p2 ;
+wire ppul_sync_p1 ;
+wire un1_pcount_diff_1_axb_20 ;
+wire un13_lock_19 ;
+wire un1_pcount_diff_1_axb_19 ;
+wire un13_lock_18 ;
+wire un1_pcount_diff_1_axb_18 ;
+wire un13_lock_17 ;
+wire un1_pcount_diff_1_cry_17_0_RNO ;
+wire un13_lock_16 ;
+wire un1_pcount_diff_1_axb_16 ;
+wire un13_lock_15 ;
+wire un1_pcount_diff_1_axb_15 ;
+wire un13_lock_14 ;
+wire un1_pcount_diff_1_axb_14 ;
+wire un13_lock_13 ;
+wire un1_pcount_diff_1_axb_13 ;
+wire un13_lock_12 ;
+wire un1_pcount_diff_1_axb_12 ;
+wire un13_lock_11 ;
+wire un1_pcount_diff_1_axb_11 ;
+wire un13_lock_10 ;
+wire un1_pcount_diff_1_axb_10 ;
+wire un13_lock_9 ;
+wire un1_pcount_diff_1_axb_9 ;
+wire un13_lock_8 ;
+wire un1_pcount_diff_1_axb_8 ;
+wire un13_lock_7 ;
+wire un1_pcount_diff_1_axb_7 ;
+wire un13_lock_6 ;
+wire un1_pcount_diff_1_axb_6 ;
+wire un13_lock_5 ;
+wire un1_pcount_diff_1_axb_5 ;
+wire un13_lock_4 ;
+wire un1_pcount_diff_1_axb_4 ;
+wire un13_lock_3 ;
+wire un1_pcount_diff_1_axb_3 ;
+wire un13_lock_2 ;
+wire un1_pcount_diff_1_axb_2 ;
+wire un13_lock_1 ;
+wire un1_pcount_diff_1_axb_1 ;
+wire un13_lock_21 ;
+wire ppul_sync_p3 ;
+wire N_7 ;
+wire un13_lock_0 ;
+wire rtc_ctrl4 ;
+wire rtc_ctrl ;
+wire VCC ;
+wire N_2136_0 ;
+wire unlock_5 ;
+wire unlock_1_sqmuxa_i_0 ;
+wire unlock ;
+wire unlock_QN ;
+wire N_89_i ;
+wire rtc_pul ;
+wire rtc_pul_p1 ;
+wire rtc_pul_p1_QN ;
+wire rtc_pul5 ;
+wire rtc_pul_QN ;
+wire rtc_ctrl_QN ;
+wire rstat_pclk_2 ;
+wire rstat_pclk ;
+wire rstat_pclk_QN ;
+wire rhb_sync_p1 ;
+wire rhb_sync_p2 ;
+wire rhb_sync_p2_QN ;
+wire rhb_sync ;
+wire rhb_sync_p1_QN ;
+wire ppul_sync_p3_QN ;
+wire ppul_sync_p2_QN ;
+wire ppul_sync ;
+wire ppul_sync_p1_QN ;
+wire pll_lock_QN ;
+wire phb ;
+wire phb_QN ;
+wire pdiff_sync ;
+wire pdiff_sync_p1 ;
+wire pdiff_sync_p1_QN ;
+wire un1_pcount_diff_1_cry_1_0_S0 ;
+wire un1_pcount_diff_1_cry_1_0_S1 ;
+wire un1_pcount_diff_1_cry_3_0_S0 ;
+wire un1_pcount_diff_1_cry_3_0_S1 ;
+wire un1_pcount_diff_1_cry_5_0_S0 ;
+wire un1_pcount_diff_1_cry_5_0_S1 ;
+wire un1_pcount_diff_1_cry_7_0_S0 ;
+wire un1_pcount_diff_1_cry_7_0_S1 ;
+wire un1_pcount_diff_1_cry_9_0_S0 ;
+wire un1_pcount_diff_1_cry_9_0_S1 ;
+wire un1_pcount_diff_1_cry_11_0_S0 ;
+wire un1_pcount_diff_1_cry_11_0_S1 ;
+wire un1_pcount_diff_1_cry_13_0_S0 ;
+wire un1_pcount_diff_1_cry_13_0_S1 ;
+wire un1_pcount_diff_1_cry_15_0_S0 ;
+wire un1_pcount_diff_1_cry_15_0_S1 ;
+wire un1_pcount_diff_1_cry_17_0_S0 ;
+wire un1_pcount_diff_1_cry_17_0_S1 ;
+wire un1_pcount_diff_1_cry_19_0_S0 ;
+wire un1_pcount_diff_1_cry_19_0_S1 ;
+wire un1_pcount_diff_1_s_21_0_S0 ;
+wire lock_5 ;
+wire lock_1_sqmuxa_i_0 ;
+wire lock ;
+wire lock_QN ;
+wire rtc_pul5_0_o3 ;
+wire rtc_pul5_0_a3_6 ;
+wire rtc_pul5_0_a3_7 ;
+wire un1_rcount_1_0_a3 ;
+wire un1_rhb_wait_cnt ;
+wire N_12 ;
+wire rtc_ctrl4_0_a3_12_4 ;
+wire rtc_ctrl4_0_a3_12_5 ;
+wire rtc_ctrl4_10 ;
+wire un1_rcount_1_0_a3_1 ;
+wire N_6 ;
+wire un1_rhb_wait_cnt_3 ;
+wire un1_rhb_wait_cnt_4 ;
+wire rtc_pul5_0_a3_5 ;
+wire un13_lock_cry_21_i ;
+wire un13_unlock_cry_21 ;
+wire N_8 ;
+wire un1_pcount_diff_1_cry_0 ;
+wire un1_pcount_diff_1_cry_0_0_S0 ;
+wire un1_pcount_diff_1_cry_0_0_S1 ;
+wire un1_pcount_diff_1_cry_2 ;
+wire un1_pcount_diff_1_cry_4 ;
+wire un1_pcount_diff_1_cry_6 ;
+wire un1_pcount_diff_1_cry_8 ;
+wire un1_pcount_diff_1_cry_10 ;
+wire un1_pcount_diff_1_cry_12 ;
+wire un1_pcount_diff_1_cry_14 ;
+wire un1_pcount_diff_1_cry_16 ;
+wire un1_pcount_diff_1_cry_18 ;
+wire un1_pcount_diff_1_cry_20 ;
+wire un1_pcount_diff_1_s_21_0_COUT ;
+wire un1_pcount_diff_1_s_21_0_S1 ;
+wire un13_lock_cry_0 ;
+wire un13_lock_cry_0_0_S0 ;
+wire un13_lock_cry_0_0_S1 ;
+wire un13_lock_cry_2 ;
+wire un13_lock_cry_1_0_S0 ;
+wire un13_lock_cry_1_0_S1 ;
+wire un13_lock_cry_4 ;
+wire un13_lock_cry_3_0_S0 ;
+wire un13_lock_cry_3_0_S1 ;
+wire un13_lock_cry_6 ;
+wire un13_lock_cry_5_0_S0 ;
+wire un13_lock_cry_5_0_S1 ;
+wire un13_lock_cry_8 ;
+wire un13_lock_cry_7_0_S0 ;
+wire un13_lock_cry_7_0_S1 ;
+wire un13_lock_cry_10 ;
+wire un13_lock_cry_9_0_S0 ;
+wire un13_lock_cry_9_0_S1 ;
+wire un13_lock_cry_12 ;
+wire un13_lock_cry_11_0_S0 ;
+wire un13_lock_cry_11_0_S1 ;
+wire un13_lock_cry_14 ;
+wire un13_lock_cry_13_0_S0 ;
+wire un13_lock_cry_13_0_S1 ;
+wire un13_lock_cry_16 ;
+wire un13_lock_cry_15_0_S0 ;
+wire un13_lock_cry_15_0_S1 ;
+wire un13_lock_cry_18 ;
+wire un13_lock_cry_17_0_S0 ;
+wire un13_lock_cry_17_0_S1 ;
+wire un13_lock_cry_20 ;
+wire un13_lock_cry_19_0_S0 ;
+wire un13_lock_cry_19_0_S1 ;
+wire un13_lock_cry_21_0_COUT ;
+wire un13_lock_cry_21_0_S0 ;
+wire un13_unlock_cry_0 ;
+wire un13_unlock_cry_0_0_S0 ;
+wire un13_unlock_cry_0_0_S1 ;
+wire un13_unlock_cry_2 ;
+wire un13_unlock_cry_1_0_S0 ;
+wire un13_unlock_cry_1_0_S1 ;
+wire un13_unlock_cry_4 ;
+wire un13_unlock_cry_3_0_S0 ;
+wire un13_unlock_cry_3_0_S1 ;
+wire un13_unlock_cry_6 ;
+wire un13_unlock_cry_5_0_S0 ;
+wire un13_unlock_cry_5_0_S1 ;
+wire un13_unlock_cry_8 ;
+wire un13_unlock_cry_7_0_S0 ;
+wire un13_unlock_cry_7_0_S1 ;
+wire un13_unlock_cry_10 ;
+wire un13_unlock_cry_9_0_S0 ;
+wire un13_unlock_cry_9_0_S1 ;
+wire un13_unlock_cry_12 ;
+wire un13_unlock_cry_11_0_S0 ;
+wire un13_unlock_cry_11_0_S1 ;
+wire un13_unlock_cry_14 ;
+wire un13_unlock_cry_13_0_S0 ;
+wire un13_unlock_cry_13_0_S1 ;
+wire un13_unlock_cry_16 ;
+wire un13_unlock_cry_15_0_S0 ;
+wire un13_unlock_cry_15_0_S1 ;
+wire un13_unlock_cry_18 ;
+wire un13_unlock_cry_17_0_S0 ;
+wire un13_unlock_cry_17_0_S1 ;
+wire un13_unlock_cry_20 ;
+wire un13_unlock_cry_19_0_S0 ;
+wire un13_unlock_cry_19_0_S1 ;
+wire un13_unlock_cry_21_0_COUT ;
+wire un13_unlock_cry_21_0_S0 ;
+wire N_96 ;
+wire N_20 ;
+wire N_19 ;
+wire N_18 ;
+wire N_14 ;
+wire GND ;
+wire N_1 ;
+wire N_2 ;
+wire N_3 ;
+wire N_4 ;
+wire N_5 ;
+wire N_9 ;
+  INV phb_RNO (
+       .A(phb_cnt[2]),
+       .Z(phb_cnt_i[2])
+);
+  INV \phb_cnt_RNO[0]  (
+       .A(phb_cnt[0]),
+       .Z(phb_cnt_i[0])
+);
+  INV pll_lock_RNI6JK9 (
+       .A(pll_lock),
+       .Z(pll_lock_i)
+);
+  LUT4 rtc_ctrl4_0_a3_RNO (
+       .A(rcount[2]),
+       .B(rcount[0]),
+       .C(rcount[5]),
+       .D(rcount[4]),
+       .Z(rtc_ctrl4_0_a3_1)
+);
+defparam rtc_ctrl4_0_a3_RNO.init=16'h2000;
+  LUT4 un1_pcount_diff_1_cry_19_0_RNO_0 (
+       .A(un13_lock_20),
+       .B(pcount[20]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_20)
+);
+defparam un1_pcount_diff_1_cry_19_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_19_0_RNO (
+       .A(un13_lock_19),
+       .B(pcount[19]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_19)
+);
+defparam un1_pcount_diff_1_cry_19_0_RNO.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_17_0_RNO_0 (
+       .A(un13_lock_18),
+       .B(pcount[18]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_18)
+);
+defparam un1_pcount_diff_1_cry_17_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_17_0_RNO_cZ (
+       .A(un13_lock_17),
+       .B(pcount[17]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_cry_17_0_RNO)
+);
+defparam un1_pcount_diff_1_cry_17_0_RNO_cZ.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_15_0_RNO_0 (
+       .A(un13_lock_16),
+       .B(pcount[16]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_16)
+);
+defparam un1_pcount_diff_1_cry_15_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_15_0_RNO (
+       .A(un13_lock_15),
+       .B(pcount[15]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_15)
+);
+defparam un1_pcount_diff_1_cry_15_0_RNO.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_13_0_RNO_0 (
+       .A(un13_lock_14),
+       .B(pcount[14]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_14)
+);
+defparam un1_pcount_diff_1_cry_13_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_13_0_RNO (
+       .A(un13_lock_13),
+       .B(pcount[13]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_13)
+);
+defparam un1_pcount_diff_1_cry_13_0_RNO.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_11_0_RNO_0 (
+       .A(un13_lock_12),
+       .B(pcount[12]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_12)
+);
+defparam un1_pcount_diff_1_cry_11_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_11_0_RNO (
+       .A(un13_lock_11),
+       .B(pcount[11]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_11)
+);
+defparam un1_pcount_diff_1_cry_11_0_RNO.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_9_0_RNO_0 (
+       .A(un13_lock_10),
+       .B(pcount[10]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_10)
+);
+defparam un1_pcount_diff_1_cry_9_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_9_0_RNO (
+       .A(un13_lock_9),
+       .B(pcount[9]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_9)
+);
+defparam un1_pcount_diff_1_cry_9_0_RNO.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_7_0_RNO_0 (
+       .A(un13_lock_8),
+       .B(pcount[8]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_8)
+);
+defparam un1_pcount_diff_1_cry_7_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_7_0_RNO (
+       .A(un13_lock_7),
+       .B(pcount[7]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_7)
+);
+defparam un1_pcount_diff_1_cry_7_0_RNO.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_5_0_RNO_0 (
+       .A(un13_lock_6),
+       .B(pcount[6]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_6)
+);
+defparam un1_pcount_diff_1_cry_5_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_5_0_RNO (
+       .A(un13_lock_5),
+       .B(pcount[5]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_5)
+);
+defparam un1_pcount_diff_1_cry_5_0_RNO.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_3_0_RNO_0 (
+       .A(un13_lock_4),
+       .B(pcount[4]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_4)
+);
+defparam un1_pcount_diff_1_cry_3_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_3_0_RNO (
+       .A(un13_lock_3),
+       .B(pcount[3]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_3)
+);
+defparam un1_pcount_diff_1_cry_3_0_RNO.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_1_0_RNO_0 (
+       .A(un13_lock_2),
+       .B(pcount[2]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_2)
+);
+defparam un1_pcount_diff_1_cry_1_0_RNO_0.init=16'h5355;
+  LUT4 un1_pcount_diff_1_cry_1_0_RNO (
+       .A(un13_lock_1),
+       .B(pcount[1]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff_1_axb_1)
+);
+defparam un1_pcount_diff_1_cry_1_0_RNO.init=16'h5355;
+  LUT4 ppul_sync_p3_RNIU65C (
+       .A(un13_lock_21),
+       .B(ppul_sync_p3),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(N_7)
+);
+defparam ppul_sync_p3_RNIU65C.init=16'h2F20;
+  LUT4 \pcount_diff_RNO[0]  (
+       .A(ppul_sync_p1),
+       .B(ppul_sync_p2),
+       .C(pcount[0]),
+       .D(un13_lock_0),
+       .Z(un1_pcount_diff_i[0])
+);
+defparam \pcount_diff_RNO[0] .init=16'hFD20;
+// @16:1304
+  LUT4 rtc_ctrl_0 (
+       .A(rtc_ctrl4),
+       .B(rtc_ctrl),
+       .C(VCC),
+       .D(VCC),
+       .Z(N_2136_0)
+);
+defparam rtc_ctrl_0.init=16'hEEEE;
+// @16:1278
+  FD1P3DX unlock_reg (
+       .D(unlock_5),
+       .SP(unlock_1_sqmuxa_i_0),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(unlock)
+);
+// @16:1801
+  FD1S3DX \sll_state_reg[1]  (
+       .D(N_89_i),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(sll_state[1])
+);
+// @16:1304
+  FD1S3DX rtc_pul_p1_reg (
+       .D(rtc_pul),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rtc_pul_p1)
+);
+// @16:1304
+  FD1P3DX rtc_pul_reg (
+       .D(rtc_pul5),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rtc_pul)
+);
+// @16:1304
+  FD1S3DX rtc_ctrl_reg (
+       .D(N_2136_0),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rtc_ctrl)
+);
+// @16:1350
+  FD1P3DX rstat_pclk_reg (
+       .D(rstat_pclk_2),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rstat_pclk)
+);
+// @16:1350
+  FD1P3DX \rhb_wait_cnt_reg[0]  (
+       .D(rhb_wait_cnt_s[0]),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_wait_cnt[0])
+);
+// @16:1350
+  FD1P3DX \rhb_wait_cnt_reg[1]  (
+       .D(rhb_wait_cnt_s[1]),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_wait_cnt[1])
+);
+// @16:1350
+  FD1P3DX \rhb_wait_cnt_reg[2]  (
+       .D(rhb_wait_cnt_s[2]),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_wait_cnt[2])
+);
+// @16:1350
+  FD1P3DX \rhb_wait_cnt_reg[3]  (
+       .D(rhb_wait_cnt_s[3]),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_wait_cnt[3])
+);
+// @16:1350
+  FD1P3DX \rhb_wait_cnt_reg[4]  (
+       .D(rhb_wait_cnt_s[4]),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_wait_cnt[4])
+);
+// @16:1350
+  FD1P3DX \rhb_wait_cnt_reg[5]  (
+       .D(rhb_wait_cnt_s[5]),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_wait_cnt[5])
+);
+// @16:1350
+  FD1P3DX \rhb_wait_cnt_reg[6]  (
+       .D(rhb_wait_cnt_s[6]),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_wait_cnt[6])
+);
+// @16:1350
+  FD1P3DX \rhb_wait_cnt_reg[7]  (
+       .D(rhb_wait_cnt_s[7]),
+       .SP(rtc_ctrl),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_wait_cnt[7])
+);
+// @16:1350
+  FD1S3DX rhb_sync_p2_reg (
+       .D(rhb_sync_p1),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_sync_p2)
+);
+// @16:1350
+  FD1S3DX rhb_sync_p1_reg (
+       .D(rhb_sync),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rhb_sync_p1)
+);
+// @16:1304
+  FD1S3DX \rcount_reg[0]  (
+       .D(rcount_s[0]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[0])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[1]  (
+       .D(rcount_s[1]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[1])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[2]  (
+       .D(rcount_s[2]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[2])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[3]  (
+       .D(rcount_s[3]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[3])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[4]  (
+       .D(rcount_s[4]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[4])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[5]  (
+       .D(rcount_s[5]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[5])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[6]  (
+       .D(rcount_s[6]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[6])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[7]  (
+       .D(rcount_s[7]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[7])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[8]  (
+       .D(rcount_s[8]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[8])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[9]  (
+       .D(rcount_s[9]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[9])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[10]  (
+       .D(rcount_s[10]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[10])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[11]  (
+       .D(rcount_s[11]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[11])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[12]  (
+       .D(rcount_s[12]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[12])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[13]  (
+       .D(rcount_s[13]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[13])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[14]  (
+       .D(rcount_s[14]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[14])
+);
+// @16:1304
+  FD1S3DX \rcount_reg[15]  (
+       .D(rcount_s[15]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rcount[15])
+);
+// @16:1408
+  FD1S3DX ppul_sync_p3_reg (
+       .D(ppul_sync_p2),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(ppul_sync_p3)
+);
+// @16:1408
+  FD1S3DX ppul_sync_p2_reg (
+       .D(ppul_sync_p1),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(ppul_sync_p2)
+);
+// @16:1408
+  FD1S3DX ppul_sync_p1_reg (
+       .D(ppul_sync),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(ppul_sync_p1)
+);
+// @16:1879
+  FD1S3DX pll_lock_reg (
+       .D(sll_state[1]),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(pll_lock)
+);
+// @16:1759
+  FD1S3DX \phb_cnt_reg[0]  (
+       .D(phb_cnt_i[0]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(phb_cnt[0])
+);
+// @16:1759
+  FD1S3DX \phb_cnt_reg[1]  (
+       .D(phb_cnt_RNO[1]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(phb_cnt[1])
+);
+// @16:1759
+  FD1S3DX \phb_cnt_reg[2]  (
+       .D(phb_cnt_RNO[2]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(phb_cnt[2])
+);
+// @16:1759
+  FD1S3DX phb_reg (
+       .D(phb_cnt_i[2]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(phb)
+);
+// @16:1278
+  FD1S3DX pdiff_sync_p1_reg (
+       .D(pdiff_sync),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(pdiff_sync_p1)
+);
+// @16:1759
+  FD1P3BX \pcount_diff[0]  (
+       .D(un1_pcount_diff_i[0]),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_0)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[0]  (
+       .D(pcount_s[0]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[0])
+);
+// @16:1759
+  FD1S3DX \pcount_reg[1]  (
+       .D(pcount_s[1]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[1])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[1]  (
+       .D(un1_pcount_diff_1_cry_1_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_1)
+);
+// @16:1759
+  FD1P3BX \pcount_diff[2]  (
+       .D(un1_pcount_diff_1_cry_1_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_2)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[2]  (
+       .D(pcount_s[2]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[2])
+);
+// @16:1759
+  FD1S3DX \pcount_reg[3]  (
+       .D(pcount_s[3]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[3])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[3]  (
+       .D(un1_pcount_diff_1_cry_3_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_3)
+);
+// @16:1759
+  FD1P3BX \pcount_diff[4]  (
+       .D(un1_pcount_diff_1_cry_3_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_4)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[4]  (
+       .D(pcount_s[4]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[4])
+);
+// @16:1759
+  FD1S3DX \pcount_reg[5]  (
+       .D(pcount_s[5]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[5])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[5]  (
+       .D(un1_pcount_diff_1_cry_5_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_5)
+);
+// @16:1759
+  FD1P3BX \pcount_diff[6]  (
+       .D(un1_pcount_diff_1_cry_5_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_6)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[6]  (
+       .D(pcount_s[6]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[6])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[7]  (
+       .D(un1_pcount_diff_1_cry_7_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_7)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[7]  (
+       .D(pcount_s[7]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[7])
+);
+// @16:1759
+  FD1S3DX \pcount_reg[8]  (
+       .D(pcount_s[8]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[8])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[8]  (
+       .D(un1_pcount_diff_1_cry_7_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_8)
+);
+// @16:1759
+  FD1P3BX \pcount_diff[9]  (
+       .D(un1_pcount_diff_1_cry_9_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_9)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[9]  (
+       .D(pcount_s[9]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[9])
+);
+// @16:1759
+  FD1S3DX \pcount_reg[10]  (
+       .D(pcount_s[10]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[10])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[10]  (
+       .D(un1_pcount_diff_1_cry_9_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_10)
+);
+// @16:1759
+  FD1P3BX \pcount_diff[11]  (
+       .D(un1_pcount_diff_1_cry_11_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_11)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[11]  (
+       .D(pcount_s[11]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[11])
+);
+// @16:1759
+  FD1S3DX \pcount_reg[12]  (
+       .D(pcount_s[12]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[12])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[12]  (
+       .D(un1_pcount_diff_1_cry_11_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_12)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[13]  (
+       .D(pcount_s[13]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[13])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[13]  (
+       .D(un1_pcount_diff_1_cry_13_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_13)
+);
+// @16:1759
+  FD1P3BX \pcount_diff[14]  (
+       .D(un1_pcount_diff_1_cry_13_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_14)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[14]  (
+       .D(pcount_s[14]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[14])
+);
+// @16:1759
+  FD1P3BX \pcount_diff[15]  (
+       .D(un1_pcount_diff_1_cry_15_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .PD(sli_rst),
+       .Q(un13_lock_15)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[15]  (
+       .D(pcount_s[15]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[15])
+);
+// @16:1759
+  FD1S3DX \pcount_reg[16]  (
+       .D(pcount_s[16]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[16])
+);
+// @16:1759
+  FD1P3DX \pcount_diff[16]  (
+       .D(un1_pcount_diff_1_cry_15_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(un13_lock_16)
+);
+// @16:1759
+  FD1P3DX \pcount_diff[17]  (
+       .D(un1_pcount_diff_1_cry_17_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(un13_lock_17)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[17]  (
+       .D(pcount_s[17]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[17])
+);
+// @16:1759
+  FD1S3DX \pcount_reg[18]  (
+       .D(pcount_s[18]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[18])
+);
+// @16:1759
+  FD1P3DX \pcount_diff[18]  (
+       .D(un1_pcount_diff_1_cry_17_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(un13_lock_18)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[19]  (
+       .D(pcount_s[19]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[19])
+);
+// @16:1759
+  FD1P3DX \pcount_diff[19]  (
+       .D(un1_pcount_diff_1_cry_19_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(un13_lock_19)
+);
+// @16:1759
+  FD1P3DX \pcount_diff[20]  (
+       .D(un1_pcount_diff_1_cry_19_0_S1),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(un13_lock_20)
+);
+// @16:1759
+  FD1S3DX \pcount_reg[20]  (
+       .D(pcount_s[20]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[20])
+);
+// @16:1759
+  FD1S3DX \pcount_reg[21]  (
+       .D(pcount_s[21]),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(pcount[21])
+);
+// @16:1759
+  FD1P3DX \pcount_diff[21]  (
+       .D(un1_pcount_diff_1_s_21_0_S0),
+       .SP(N_7),
+       .CK(tx_pclk),
+       .CD(sli_rst),
+       .Q(un13_lock_21)
+);
+// @16:1278
+  FD1P3DX lock_reg (
+       .D(lock_5),
+       .SP(lock_1_sqmuxa_i_0),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(lock)
+);
+// @16:1739
+  FD1S3DX \genblk5.rdiff_comp_lock[2]  (
+       .D(VCC),
+       .CK(pll_refclki),
+       .CD(sli_rst),
+       .Q(rdiff_comp_lock[2])
+);
+// @16:1334
+  LUT4 rtc_pul5_0_0 (
+       .A(rtc_pul5_0_o3),
+       .B(rtc_pul5_0_a3_6),
+       .C(rtc_pul5_0_a3_7),
+       .D(un1_rcount_1_0_a3),
+       .Z(rtc_pul5)
+);
+defparam rtc_pul5_0_0.init=16'hFF80;
+// @16:1389
+  LUT4 rstat_pclk_2_iv_0_0 (
+       .A(un1_rhb_wait_cnt),
+       .B(rhb_sync_p1),
+       .C(rhb_sync_p2),
+       .D(rstat_pclk),
+       .Z(rstat_pclk_2)
+);
+defparam rstat_pclk_2_iv_0_0.init=16'h5D0C;
+// @16:1801
+  LUT4 \sll_state_RNO[1]  (
+       .A(sll_state_ns_i_0_m3[1]),
+       .B(rstat_pclk),
+       .C(sll_state[1]),
+       .D(unlock),
+       .Z(N_89_i)
+);
+defparam \sll_state_RNO[1] .init=16'h4044;
+// @16:1389
+  LUT4 un1_rhb_wait_cnt12_1_i_0_a3 (
+       .A(un1_rhb_wait_cnt),
+       .B(rhb_sync_p1),
+       .C(rhb_sync_p2),
+       .D(VCC),
+       .Z(N_12)
+);
+defparam un1_rhb_wait_cnt12_1_i_0_a3.init=16'h5151;
+// @16:1328
+  LUT4 rtc_ctrl4_0_a3 (
+       .A(rtc_ctrl4_0_a3_1),
+       .B(rtc_ctrl4_0_a3_12_4),
+       .C(rtc_ctrl4_0_a3_12_5),
+       .D(rtc_ctrl4_10),
+       .Z(rtc_ctrl4)
+);
+defparam rtc_ctrl4_0_a3.init=16'h8000;
+// @16:1319
+  LUT4 un1_rcount_1_0_a3_cZ (
+       .A(rtc_ctrl4_0_a3_12_4),
+       .B(rtc_ctrl4_0_a3_12_5),
+       .C(rtc_ctrl4_10),
+       .D(un1_rcount_1_0_a3_1),
+       .Z(un1_rcount_1_0_a3)
+);
+defparam un1_rcount_1_0_a3_cZ.init=16'h8000;
+// @16:1334
+  LUT4 rtc_pul5_0_o3_cZ (
+       .A(N_6),
+       .B(rcount[1]),
+       .C(rcount[2]),
+       .D(rcount[3]),
+       .Z(rtc_pul5_0_o3)
+);
+defparam rtc_pul5_0_o3_cZ.init=16'hAAAB;
+// @16:1393
+  LUT4 un1_rhb_wait_cnt_cZ (
+       .A(rhb_wait_cnt[4]),
+       .B(rhb_wait_cnt[5]),
+       .C(un1_rhb_wait_cnt_3),
+       .D(un1_rhb_wait_cnt_4),
+       .Z(un1_rhb_wait_cnt)
+);
+defparam un1_rhb_wait_cnt_cZ.init=16'h8000;
+// @16:1334
+  LUT4 rtc_pul5_0_a3_7_cZ (
+       .A(rcount[7]),
+       .B(rcount[8]),
+       .C(rtc_pul5_0_a3_5),
+       .D(VCC),
+       .Z(rtc_pul5_0_a3_7)
+);
+defparam rtc_pul5_0_a3_7_cZ.init=16'h1010;
+// @16:1801
+  LUT4 \sll_state_ns_i_0_m3_cZ[1]  (
+       .A(lock),
+       .B(rtc_pul),
+       .C(rtc_pul_p1),
+       .D(sll_state[1]),
+       .Z(sll_state_ns_i_0_m3[1])
+);
+defparam \sll_state_ns_i_0_m3_cZ[1] .init=16'h10DF;
+// @16:1776
+  LUT4 \phb_cnt_RNO_cZ[2]  (
+       .A(phb_cnt[0]),
+       .B(phb_cnt[1]),
+       .C(phb_cnt[2]),
+       .D(VCC),
+       .Z(phb_cnt_RNO[2])
+);
+defparam \phb_cnt_RNO_cZ[2] .init=16'h7878;
+// @16:1287
+  LUT4 unlock_1_sqmuxa_i_0_cZ (
+       .A(pdiff_sync),
+       .B(pdiff_sync_p1),
+       .C(unlock),
+       .D(VCC),
+       .Z(unlock_1_sqmuxa_i_0)
+);
+defparam unlock_1_sqmuxa_i_0_cZ.init=16'h4F4F;
+// @16:1287
+  LUT4 lock_1_sqmuxa_i_0_cZ (
+       .A(lock),
+       .B(pdiff_sync),
+       .C(pdiff_sync_p1),
+       .D(VCC),
+       .Z(lock_1_sqmuxa_i_0)
+);
+defparam lock_1_sqmuxa_i_0_cZ.init=16'h7575;
+// @16:1328
+  LUT4 rtc_ctrl4_0_a3_10 (
+       .A(rcount[1]),
+       .B(rcount[3]),
+       .C(rcount[6]),
+       .D(rcount[15]),
+       .Z(rtc_ctrl4_10)
+);
+defparam rtc_ctrl4_0_a3_10.init=16'h8000;
+// @16:1393
+  LUT4 un1_rhb_wait_cnt_4_cZ (
+       .A(rhb_wait_cnt[0]),
+       .B(rhb_wait_cnt[1]),
+       .C(rhb_wait_cnt[2]),
+       .D(rhb_wait_cnt[3]),
+       .Z(un1_rhb_wait_cnt_4)
+);
+defparam un1_rhb_wait_cnt_4_cZ.init=16'h8000;
+// @16:1328
+  LUT4 rtc_ctrl4_0_a3_12_4_cZ (
+       .A(rcount[11]),
+       .B(rcount[12]),
+       .C(rcount[13]),
+       .D(rcount[14]),
+       .Z(rtc_ctrl4_0_a3_12_4)
+);
+defparam rtc_ctrl4_0_a3_12_4_cZ.init=16'h8000;
+// @16:1328
+  LUT4 rtc_ctrl4_0_a3_12_5_cZ (
+       .A(rcount[7]),
+       .B(rcount[8]),
+       .C(rcount[9]),
+       .D(rcount[10]),
+       .Z(rtc_ctrl4_0_a3_12_5)
+);
+defparam rtc_ctrl4_0_a3_12_5_cZ.init=16'h8000;
+// @16:1334
+  LUT4 rtc_pul5_0_a3_5_cZ (
+       .A(rcount[6]),
+       .B(rcount[13]),
+       .C(rcount[14]),
+       .D(rcount[15]),
+       .Z(rtc_pul5_0_a3_5)
+);
+defparam rtc_pul5_0_a3_5_cZ.init=16'h0001;
+// @16:1334
+  LUT4 rtc_pul5_0_a3_6_cZ (
+       .A(rcount[9]),
+       .B(rcount[10]),
+       .C(rcount[11]),
+       .D(rcount[12]),
+       .Z(rtc_pul5_0_a3_6)
+);
+defparam rtc_pul5_0_a3_6_cZ.init=16'h0001;
+// @16:1292
+  LUT4 lock_5_cZ (
+       .A(pdiff_sync),
+       .B(un13_lock_cry_21_i),
+       .C(VCC),
+       .D(VCC),
+       .Z(lock_5)
+);
+defparam lock_5_cZ.init=16'h8888;
+// @16:1286
+  LUT4 unlock_5_cZ (
+       .A(pdiff_sync),
+       .B(un13_unlock_cry_21),
+       .C(VCC),
+       .D(VCC),
+       .Z(unlock_5)
+);
+defparam unlock_5_cZ.init=16'h8888;
+// @16:1768
+  LUT4 pcount10_0_o3 (
+       .A(ppul_sync_p1),
+       .B(ppul_sync_p2),
+       .C(VCC),
+       .D(VCC),
+       .Z(N_8)
+);
+defparam pcount10_0_o3.init=16'hDDDD;
+// @16:1776
+  LUT4 \phb_cnt_RNO_cZ[1]  (
+       .A(phb_cnt[0]),
+       .B(phb_cnt[1]),
+       .C(VCC),
+       .D(VCC),
+       .Z(phb_cnt_RNO[1])
+);
+defparam \phb_cnt_RNO_cZ[1] .init=16'h6666;
+// @16:1328
+  LUT4 rtc_ctrl4_0_o3 (
+       .A(rcount[4]),
+       .B(rcount[5]),
+       .C(VCC),
+       .D(VCC),
+       .Z(N_6)
+);
+defparam rtc_ctrl4_0_o3.init=16'h7777;
+// @16:1393
+  LUT4 un1_rhb_wait_cnt_3_cZ (
+       .A(rhb_wait_cnt[6]),
+       .B(rhb_wait_cnt[7]),
+       .C(VCC),
+       .D(VCC),
+       .Z(un1_rhb_wait_cnt_3)
+);
+defparam un1_rhb_wait_cnt_3_cZ.init=16'h8888;
+// @16:1786
+  LUT4 \un1_pcount_diff_cZ[0]  (
+       .A(un13_lock_0),
+       .B(pcount[0]),
+       .C(ppul_sync_p2),
+       .D(ppul_sync_p1),
+       .Z(un1_pcount_diff[0])
+);
+defparam \un1_pcount_diff_cZ[0] .init=16'h5355;
+// @16:1319
+  LUT4 un1_rcount_1_0_a3_1_cZ (
+       .A(rcount[2]),
+       .B(rcount[0]),
+       .C(rcount[5]),
+       .D(rcount[4]),
+       .Z(un1_rcount_1_0_a3_1)
+);
+defparam un1_rcount_1_0_a3_1_cZ.init=16'h8000;
+  CCU2C \pcount_cry_0[0]  (
+       .A0(VCC),
+       .B0(N_8),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_9),
+       .COUT(pcount_cry[0]),
+       .S0(pcount_cry_0_S0[0]),
+       .S1(pcount_s[0])
+);
+defparam \pcount_cry_0[0] .INIT0=16'h500c;
+defparam \pcount_cry_0[0] .INIT1=16'h8000;
+defparam \pcount_cry_0[0] .INJECT1_0="NO";
+defparam \pcount_cry_0[0] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[1]  (
+       .A0(N_8),
+       .B0(pcount[1]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[0]),
+       .COUT(pcount_cry[2]),
+       .S0(pcount_s[1]),
+       .S1(pcount_s[2])
+);
+defparam \pcount_cry_0[1] .INIT0=16'h8000;
+defparam \pcount_cry_0[1] .INIT1=16'h8000;
+defparam \pcount_cry_0[1] .INJECT1_0="NO";
+defparam \pcount_cry_0[1] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[3]  (
+       .A0(N_8),
+       .B0(pcount[3]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[4]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[2]),
+       .COUT(pcount_cry[4]),
+       .S0(pcount_s[3]),
+       .S1(pcount_s[4])
+);
+defparam \pcount_cry_0[3] .INIT0=16'h8000;
+defparam \pcount_cry_0[3] .INIT1=16'h8000;
+defparam \pcount_cry_0[3] .INJECT1_0="NO";
+defparam \pcount_cry_0[3] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[5]  (
+       .A0(N_8),
+       .B0(pcount[5]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[6]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[4]),
+       .COUT(pcount_cry[6]),
+       .S0(pcount_s[5]),
+       .S1(pcount_s[6])
+);
+defparam \pcount_cry_0[5] .INIT0=16'h8000;
+defparam \pcount_cry_0[5] .INIT1=16'h8000;
+defparam \pcount_cry_0[5] .INJECT1_0="NO";
+defparam \pcount_cry_0[5] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[7]  (
+       .A0(N_8),
+       .B0(pcount[7]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[8]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[6]),
+       .COUT(pcount_cry[8]),
+       .S0(pcount_s[7]),
+       .S1(pcount_s[8])
+);
+defparam \pcount_cry_0[7] .INIT0=16'h8000;
+defparam \pcount_cry_0[7] .INIT1=16'h8000;
+defparam \pcount_cry_0[7] .INJECT1_0="NO";
+defparam \pcount_cry_0[7] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[9]  (
+       .A0(N_8),
+       .B0(pcount[9]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[10]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[8]),
+       .COUT(pcount_cry[10]),
+       .S0(pcount_s[9]),
+       .S1(pcount_s[10])
+);
+defparam \pcount_cry_0[9] .INIT0=16'h8000;
+defparam \pcount_cry_0[9] .INIT1=16'h8000;
+defparam \pcount_cry_0[9] .INJECT1_0="NO";
+defparam \pcount_cry_0[9] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[11]  (
+       .A0(N_8),
+       .B0(pcount[11]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[12]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[10]),
+       .COUT(pcount_cry[12]),
+       .S0(pcount_s[11]),
+       .S1(pcount_s[12])
+);
+defparam \pcount_cry_0[11] .INIT0=16'h8000;
+defparam \pcount_cry_0[11] .INIT1=16'h8000;
+defparam \pcount_cry_0[11] .INJECT1_0="NO";
+defparam \pcount_cry_0[11] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[13]  (
+       .A0(N_8),
+       .B0(pcount[13]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[14]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[12]),
+       .COUT(pcount_cry[14]),
+       .S0(pcount_s[13]),
+       .S1(pcount_s[14])
+);
+defparam \pcount_cry_0[13] .INIT0=16'h8000;
+defparam \pcount_cry_0[13] .INIT1=16'h8000;
+defparam \pcount_cry_0[13] .INJECT1_0="NO";
+defparam \pcount_cry_0[13] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[15]  (
+       .A0(N_8),
+       .B0(pcount[15]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[16]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[14]),
+       .COUT(pcount_cry[16]),
+       .S0(pcount_s[15]),
+       .S1(pcount_s[16])
+);
+defparam \pcount_cry_0[15] .INIT0=16'h8000;
+defparam \pcount_cry_0[15] .INIT1=16'h8000;
+defparam \pcount_cry_0[15] .INJECT1_0="NO";
+defparam \pcount_cry_0[15] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[17]  (
+       .A0(N_8),
+       .B0(pcount[17]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[18]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[16]),
+       .COUT(pcount_cry[18]),
+       .S0(pcount_s[17]),
+       .S1(pcount_s[18])
+);
+defparam \pcount_cry_0[17] .INIT0=16'h8000;
+defparam \pcount_cry_0[17] .INIT1=16'h8000;
+defparam \pcount_cry_0[17] .INJECT1_0="NO";
+defparam \pcount_cry_0[17] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_cry_0[19]  (
+       .A0(N_8),
+       .B0(pcount[19]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_8),
+       .B1(pcount[20]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[18]),
+       .COUT(pcount_cry[20]),
+       .S0(pcount_s[19]),
+       .S1(pcount_s[20])
+);
+defparam \pcount_cry_0[19] .INIT0=16'h8000;
+defparam \pcount_cry_0[19] .INIT1=16'h8000;
+defparam \pcount_cry_0[19] .INJECT1_0="NO";
+defparam \pcount_cry_0[19] .INJECT1_1="NO";
+// @16:1759
+  CCU2C \pcount_s_0[21]  (
+       .A0(N_8),
+       .B0(pcount[21]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(pcount_cry[20]),
+       .COUT(pcount_s_0_COUT[21]),
+       .S0(pcount_s[21]),
+       .S1(pcount_s_0_S1[21])
+);
+defparam \pcount_s_0[21] .INIT0=16'h800a;
+defparam \pcount_s_0[21] .INIT1=16'h5003;
+defparam \pcount_s_0[21] .INJECT1_0="NO";
+defparam \pcount_s_0[21] .INJECT1_1="NO";
+  CCU2C \rcount_cry_0[0]  (
+       .A0(VCC),
+       .B0(un1_rcount_1_0_a3),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_rcount_1_0_a3),
+       .B1(rcount[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_5),
+       .COUT(rcount_cry[0]),
+       .S0(rcount_cry_0_S0[0]),
+       .S1(rcount_s[0])
+);
+defparam \rcount_cry_0[0] .INIT0=16'h5003;
+defparam \rcount_cry_0[0] .INIT1=16'h4000;
+defparam \rcount_cry_0[0] .INJECT1_0="NO";
+defparam \rcount_cry_0[0] .INJECT1_1="NO";
+// @16:1304
+  CCU2C \rcount_cry_0[1]  (
+       .A0(un1_rcount_1_0_a3),
+       .B0(rcount[1]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_rcount_1_0_a3),
+       .B1(rcount[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rcount_cry[0]),
+       .COUT(rcount_cry[2]),
+       .S0(rcount_s[1]),
+       .S1(rcount_s[2])
+);
+defparam \rcount_cry_0[1] .INIT0=16'h4000;
+defparam \rcount_cry_0[1] .INIT1=16'h4000;
+defparam \rcount_cry_0[1] .INJECT1_0="NO";
+defparam \rcount_cry_0[1] .INJECT1_1="NO";
+// @16:1304
+  CCU2C \rcount_cry_0[3]  (
+       .A0(un1_rcount_1_0_a3),
+       .B0(rcount[3]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_rcount_1_0_a3),
+       .B1(rcount[4]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rcount_cry[2]),
+       .COUT(rcount_cry[4]),
+       .S0(rcount_s[3]),
+       .S1(rcount_s[4])
+);
+defparam \rcount_cry_0[3] .INIT0=16'h4000;
+defparam \rcount_cry_0[3] .INIT1=16'h4000;
+defparam \rcount_cry_0[3] .INJECT1_0="NO";
+defparam \rcount_cry_0[3] .INJECT1_1="NO";
+// @16:1304
+  CCU2C \rcount_cry_0[5]  (
+       .A0(un1_rcount_1_0_a3),
+       .B0(rcount[5]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_rcount_1_0_a3),
+       .B1(rcount[6]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rcount_cry[4]),
+       .COUT(rcount_cry[6]),
+       .S0(rcount_s[5]),
+       .S1(rcount_s[6])
+);
+defparam \rcount_cry_0[5] .INIT0=16'h4000;
+defparam \rcount_cry_0[5] .INIT1=16'h4000;
+defparam \rcount_cry_0[5] .INJECT1_0="NO";
+defparam \rcount_cry_0[5] .INJECT1_1="NO";
+// @16:1304
+  CCU2C \rcount_cry_0[7]  (
+       .A0(un1_rcount_1_0_a3),
+       .B0(rcount[7]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_rcount_1_0_a3),
+       .B1(rcount[8]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rcount_cry[6]),
+       .COUT(rcount_cry[8]),
+       .S0(rcount_s[7]),
+       .S1(rcount_s[8])
+);
+defparam \rcount_cry_0[7] .INIT0=16'h4000;
+defparam \rcount_cry_0[7] .INIT1=16'h4000;
+defparam \rcount_cry_0[7] .INJECT1_0="NO";
+defparam \rcount_cry_0[7] .INJECT1_1="NO";
+// @16:1304
+  CCU2C \rcount_cry_0[9]  (
+       .A0(un1_rcount_1_0_a3),
+       .B0(rcount[9]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_rcount_1_0_a3),
+       .B1(rcount[10]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rcount_cry[8]),
+       .COUT(rcount_cry[10]),
+       .S0(rcount_s[9]),
+       .S1(rcount_s[10])
+);
+defparam \rcount_cry_0[9] .INIT0=16'h4000;
+defparam \rcount_cry_0[9] .INIT1=16'h4000;
+defparam \rcount_cry_0[9] .INJECT1_0="NO";
+defparam \rcount_cry_0[9] .INJECT1_1="NO";
+// @16:1304
+  CCU2C \rcount_cry_0[11]  (
+       .A0(un1_rcount_1_0_a3),
+       .B0(rcount[11]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_rcount_1_0_a3),
+       .B1(rcount[12]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rcount_cry[10]),
+       .COUT(rcount_cry[12]),
+       .S0(rcount_s[11]),
+       .S1(rcount_s[12])
+);
+defparam \rcount_cry_0[11] .INIT0=16'h4000;
+defparam \rcount_cry_0[11] .INIT1=16'h4000;
+defparam \rcount_cry_0[11] .INJECT1_0="NO";
+defparam \rcount_cry_0[11] .INJECT1_1="NO";
+// @16:1304
+  CCU2C \rcount_cry_0[13]  (
+       .A0(un1_rcount_1_0_a3),
+       .B0(rcount[13]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_rcount_1_0_a3),
+       .B1(rcount[14]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rcount_cry[12]),
+       .COUT(rcount_cry[14]),
+       .S0(rcount_s[13]),
+       .S1(rcount_s[14])
+);
+defparam \rcount_cry_0[13] .INIT0=16'h4000;
+defparam \rcount_cry_0[13] .INIT1=16'h4000;
+defparam \rcount_cry_0[13] .INJECT1_0="NO";
+defparam \rcount_cry_0[13] .INJECT1_1="NO";
+// @16:1304
+  CCU2C \rcount_s_0[15]  (
+       .A0(un1_rcount_1_0_a3),
+       .B0(rcount[15]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rcount_cry[14]),
+       .COUT(rcount_s_0_COUT[15]),
+       .S0(rcount_s[15]),
+       .S1(rcount_s_0_S1[15])
+);
+defparam \rcount_s_0[15] .INIT0=16'h4005;
+defparam \rcount_s_0[15] .INIT1=16'h5003;
+defparam \rcount_s_0[15] .INJECT1_0="NO";
+defparam \rcount_s_0[15] .INJECT1_1="NO";
+  CCU2C \rhb_wait_cnt_cry_0[0]  (
+       .A0(VCC),
+       .B0(N_12),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_12),
+       .B1(rhb_wait_cnt[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_4),
+       .COUT(rhb_wait_cnt_cry[0]),
+       .S0(rhb_wait_cnt_cry_0_S0[0]),
+       .S1(rhb_wait_cnt_s[0])
+);
+defparam \rhb_wait_cnt_cry_0[0] .INIT0=16'h500c;
+defparam \rhb_wait_cnt_cry_0[0] .INIT1=16'h8000;
+defparam \rhb_wait_cnt_cry_0[0] .INJECT1_0="NO";
+defparam \rhb_wait_cnt_cry_0[0] .INJECT1_1="NO";
+// @16:1350
+  CCU2C \rhb_wait_cnt_cry_0[1]  (
+       .A0(N_12),
+       .B0(rhb_wait_cnt[1]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_12),
+       .B1(rhb_wait_cnt[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rhb_wait_cnt_cry[0]),
+       .COUT(rhb_wait_cnt_cry[2]),
+       .S0(rhb_wait_cnt_s[1]),
+       .S1(rhb_wait_cnt_s[2])
+);
+defparam \rhb_wait_cnt_cry_0[1] .INIT0=16'h8000;
+defparam \rhb_wait_cnt_cry_0[1] .INIT1=16'h8000;
+defparam \rhb_wait_cnt_cry_0[1] .INJECT1_0="NO";
+defparam \rhb_wait_cnt_cry_0[1] .INJECT1_1="NO";
+// @16:1350
+  CCU2C \rhb_wait_cnt_cry_0[3]  (
+       .A0(N_12),
+       .B0(rhb_wait_cnt[3]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_12),
+       .B1(rhb_wait_cnt[4]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rhb_wait_cnt_cry[2]),
+       .COUT(rhb_wait_cnt_cry[4]),
+       .S0(rhb_wait_cnt_s[3]),
+       .S1(rhb_wait_cnt_s[4])
+);
+defparam \rhb_wait_cnt_cry_0[3] .INIT0=16'h8000;
+defparam \rhb_wait_cnt_cry_0[3] .INIT1=16'h8000;
+defparam \rhb_wait_cnt_cry_0[3] .INJECT1_0="NO";
+defparam \rhb_wait_cnt_cry_0[3] .INJECT1_1="NO";
+// @16:1350
+  CCU2C \rhb_wait_cnt_cry_0[5]  (
+       .A0(N_12),
+       .B0(rhb_wait_cnt[5]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(N_12),
+       .B1(rhb_wait_cnt[6]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rhb_wait_cnt_cry[4]),
+       .COUT(rhb_wait_cnt_cry[6]),
+       .S0(rhb_wait_cnt_s[5]),
+       .S1(rhb_wait_cnt_s[6])
+);
+defparam \rhb_wait_cnt_cry_0[5] .INIT0=16'h8000;
+defparam \rhb_wait_cnt_cry_0[5] .INIT1=16'h8000;
+defparam \rhb_wait_cnt_cry_0[5] .INJECT1_0="NO";
+defparam \rhb_wait_cnt_cry_0[5] .INJECT1_1="NO";
+// @16:1350
+  CCU2C \rhb_wait_cnt_s_0[7]  (
+       .A0(N_12),
+       .B0(rhb_wait_cnt[7]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rhb_wait_cnt_cry[6]),
+       .COUT(rhb_wait_cnt_s_0_COUT[7]),
+       .S0(rhb_wait_cnt_s[7]),
+       .S1(rhb_wait_cnt_s_0_S1[7])
+);
+defparam \rhb_wait_cnt_s_0[7] .INIT0=16'h800a;
+defparam \rhb_wait_cnt_s_0[7] .INIT1=16'h5003;
+defparam \rhb_wait_cnt_s_0[7] .INJECT1_0="NO";
+defparam \rhb_wait_cnt_s_0[7] .INJECT1_1="NO";
+  CCU2C un1_pcount_diff_1_cry_0_0 (
+       .A0(VCC),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff[0]),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_3),
+       .COUT(un1_pcount_diff_1_cry_0),
+       .S0(un1_pcount_diff_1_cry_0_0_S0),
+       .S1(un1_pcount_diff_1_cry_0_0_S1)
+);
+defparam un1_pcount_diff_1_cry_0_0.INIT0=16'h5003;
+defparam un1_pcount_diff_1_cry_0_0.INIT1=16'h500f;
+defparam un1_pcount_diff_1_cry_0_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_0_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_1_0 (
+       .A0(un1_pcount_diff_1_axb_1),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_2),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_0),
+       .COUT(un1_pcount_diff_1_cry_2),
+       .S0(un1_pcount_diff_1_cry_1_0_S0),
+       .S1(un1_pcount_diff_1_cry_1_0_S1)
+);
+defparam un1_pcount_diff_1_cry_1_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_1_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_1_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_1_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_3_0 (
+       .A0(un1_pcount_diff_1_axb_3),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_4),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_2),
+       .COUT(un1_pcount_diff_1_cry_4),
+       .S0(un1_pcount_diff_1_cry_3_0_S0),
+       .S1(un1_pcount_diff_1_cry_3_0_S1)
+);
+defparam un1_pcount_diff_1_cry_3_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_3_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_3_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_3_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_5_0 (
+       .A0(un1_pcount_diff_1_axb_5),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_6),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_4),
+       .COUT(un1_pcount_diff_1_cry_6),
+       .S0(un1_pcount_diff_1_cry_5_0_S0),
+       .S1(un1_pcount_diff_1_cry_5_0_S1)
+);
+defparam un1_pcount_diff_1_cry_5_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_5_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_5_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_5_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_7_0 (
+       .A0(un1_pcount_diff_1_axb_7),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_8),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_6),
+       .COUT(un1_pcount_diff_1_cry_8),
+       .S0(un1_pcount_diff_1_cry_7_0_S0),
+       .S1(un1_pcount_diff_1_cry_7_0_S1)
+);
+defparam un1_pcount_diff_1_cry_7_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_7_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_7_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_7_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_9_0 (
+       .A0(un1_pcount_diff_1_axb_9),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_10),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_8),
+       .COUT(un1_pcount_diff_1_cry_10),
+       .S0(un1_pcount_diff_1_cry_9_0_S0),
+       .S1(un1_pcount_diff_1_cry_9_0_S1)
+);
+defparam un1_pcount_diff_1_cry_9_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_9_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_9_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_9_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_11_0 (
+       .A0(un1_pcount_diff_1_axb_11),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_12),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_10),
+       .COUT(un1_pcount_diff_1_cry_12),
+       .S0(un1_pcount_diff_1_cry_11_0_S0),
+       .S1(un1_pcount_diff_1_cry_11_0_S1)
+);
+defparam un1_pcount_diff_1_cry_11_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_11_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_11_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_11_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_13_0 (
+       .A0(un1_pcount_diff_1_axb_13),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_14),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_12),
+       .COUT(un1_pcount_diff_1_cry_14),
+       .S0(un1_pcount_diff_1_cry_13_0_S0),
+       .S1(un1_pcount_diff_1_cry_13_0_S1)
+);
+defparam un1_pcount_diff_1_cry_13_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_13_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_13_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_13_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_15_0 (
+       .A0(un1_pcount_diff_1_axb_15),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_16),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_14),
+       .COUT(un1_pcount_diff_1_cry_16),
+       .S0(un1_pcount_diff_1_cry_15_0_S0),
+       .S1(un1_pcount_diff_1_cry_15_0_S1)
+);
+defparam un1_pcount_diff_1_cry_15_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_15_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_15_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_15_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_17_0 (
+       .A0(N_8),
+       .B0(rdiff_comp_lock[2]),
+       .C0(un1_pcount_diff_1_cry_17_0_RNO),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_18),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_16),
+       .COUT(un1_pcount_diff_1_cry_18),
+       .S0(un1_pcount_diff_1_cry_17_0_S0),
+       .S1(un1_pcount_diff_1_cry_17_0_S1)
+);
+defparam un1_pcount_diff_1_cry_17_0.INIT0=16'hb404;
+defparam un1_pcount_diff_1_cry_17_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_17_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_17_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_cry_19_0 (
+       .A0(un1_pcount_diff_1_axb_19),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un1_pcount_diff_1_axb_20),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_18),
+       .COUT(un1_pcount_diff_1_cry_20),
+       .S0(un1_pcount_diff_1_cry_19_0_S0),
+       .S1(un1_pcount_diff_1_cry_19_0_S1)
+);
+defparam un1_pcount_diff_1_cry_19_0.INIT0=16'ha003;
+defparam un1_pcount_diff_1_cry_19_0.INIT1=16'ha003;
+defparam un1_pcount_diff_1_cry_19_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_cry_19_0.INJECT1_1="NO";
+// @16:1786
+  CCU2C un1_pcount_diff_1_s_21_0 (
+       .A0(pcount[21]),
+       .B0(un13_lock_21),
+       .C0(N_8),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un1_pcount_diff_1_cry_20),
+       .COUT(un1_pcount_diff_1_s_21_0_COUT),
+       .S0(un1_pcount_diff_1_s_21_0_S0),
+       .S1(un1_pcount_diff_1_s_21_0_S1)
+);
+defparam un1_pcount_diff_1_s_21_0.INIT0=16'h350a;
+defparam un1_pcount_diff_1_s_21_0.INIT1=16'h5003;
+defparam un1_pcount_diff_1_s_21_0.INJECT1_0="NO";
+defparam un1_pcount_diff_1_s_21_0.INJECT1_1="NO";
+  CCU2C un13_lock_cry_0_0 (
+       .A0(VCC),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_0),
+       .B1(rdiff_comp_lock[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_2),
+       .COUT(un13_lock_cry_0),
+       .S0(un13_lock_cry_0_0_S0),
+       .S1(un13_lock_cry_0_0_S1)
+);
+defparam un13_lock_cry_0_0.INIT0=16'h5003;
+defparam un13_lock_cry_0_0.INIT1=16'h900a;
+defparam un13_lock_cry_0_0.INJECT1_0="NO";
+defparam un13_lock_cry_0_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_1_0 (
+       .A0(un13_lock_1),
+       .B0(rdiff_comp_lock[2]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_2),
+       .B1(rdiff_comp_lock[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_0),
+       .COUT(un13_lock_cry_2),
+       .S0(un13_lock_cry_1_0_S0),
+       .S1(un13_lock_cry_1_0_S1)
+);
+defparam un13_lock_cry_1_0.INIT0=16'h900a;
+defparam un13_lock_cry_1_0.INIT1=16'h900a;
+defparam un13_lock_cry_1_0.INJECT1_0="NO";
+defparam un13_lock_cry_1_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_3_0 (
+       .A0(un13_lock_3),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_4),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_2),
+       .COUT(un13_lock_cry_4),
+       .S0(un13_lock_cry_3_0_S0),
+       .S1(un13_lock_cry_3_0_S1)
+);
+defparam un13_lock_cry_3_0.INIT0=16'h500a;
+defparam un13_lock_cry_3_0.INIT1=16'h500a;
+defparam un13_lock_cry_3_0.INJECT1_0="NO";
+defparam un13_lock_cry_3_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_5_0 (
+       .A0(un13_lock_5),
+       .B0(rdiff_comp_lock[2]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_6),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_4),
+       .COUT(un13_lock_cry_6),
+       .S0(un13_lock_cry_5_0_S0),
+       .S1(un13_lock_cry_5_0_S1)
+);
+defparam un13_lock_cry_5_0.INIT0=16'h900a;
+defparam un13_lock_cry_5_0.INIT1=16'h500a;
+defparam un13_lock_cry_5_0.INJECT1_0="NO";
+defparam un13_lock_cry_5_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_7_0 (
+       .A0(un13_lock_7),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_8),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_6),
+       .COUT(un13_lock_cry_8),
+       .S0(un13_lock_cry_7_0_S0),
+       .S1(un13_lock_cry_7_0_S1)
+);
+defparam un13_lock_cry_7_0.INIT0=16'h500a;
+defparam un13_lock_cry_7_0.INIT1=16'h500a;
+defparam un13_lock_cry_7_0.INJECT1_0="NO";
+defparam un13_lock_cry_7_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_9_0 (
+       .A0(un13_lock_9),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_10),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_8),
+       .COUT(un13_lock_cry_10),
+       .S0(un13_lock_cry_9_0_S0),
+       .S1(un13_lock_cry_9_0_S1)
+);
+defparam un13_lock_cry_9_0.INIT0=16'h500a;
+defparam un13_lock_cry_9_0.INIT1=16'h500a;
+defparam un13_lock_cry_9_0.INJECT1_0="NO";
+defparam un13_lock_cry_9_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_11_0 (
+       .A0(un13_lock_11),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_12),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_10),
+       .COUT(un13_lock_cry_12),
+       .S0(un13_lock_cry_11_0_S0),
+       .S1(un13_lock_cry_11_0_S1)
+);
+defparam un13_lock_cry_11_0.INIT0=16'h500a;
+defparam un13_lock_cry_11_0.INIT1=16'h500a;
+defparam un13_lock_cry_11_0.INJECT1_0="NO";
+defparam un13_lock_cry_11_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_13_0 (
+       .A0(un13_lock_13),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_14),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_12),
+       .COUT(un13_lock_cry_14),
+       .S0(un13_lock_cry_13_0_S0),
+       .S1(un13_lock_cry_13_0_S1)
+);
+defparam un13_lock_cry_13_0.INIT0=16'h500a;
+defparam un13_lock_cry_13_0.INIT1=16'h500a;
+defparam un13_lock_cry_13_0.INJECT1_0="NO";
+defparam un13_lock_cry_13_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_15_0 (
+       .A0(un13_lock_15),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_16),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_14),
+       .COUT(un13_lock_cry_16),
+       .S0(un13_lock_cry_15_0_S0),
+       .S1(un13_lock_cry_15_0_S1)
+);
+defparam un13_lock_cry_15_0.INIT0=16'h500a;
+defparam un13_lock_cry_15_0.INIT1=16'h500a;
+defparam un13_lock_cry_15_0.INJECT1_0="NO";
+defparam un13_lock_cry_15_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_17_0 (
+       .A0(un13_lock_17),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_18),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_16),
+       .COUT(un13_lock_cry_18),
+       .S0(un13_lock_cry_17_0_S0),
+       .S1(un13_lock_cry_17_0_S1)
+);
+defparam un13_lock_cry_17_0.INIT0=16'h500a;
+defparam un13_lock_cry_17_0.INIT1=16'h500a;
+defparam un13_lock_cry_17_0.INJECT1_0="NO";
+defparam un13_lock_cry_17_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_19_0 (
+       .A0(un13_lock_19),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_20),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_18),
+       .COUT(un13_lock_cry_20),
+       .S0(un13_lock_cry_19_0_S0),
+       .S1(un13_lock_cry_19_0_S1)
+);
+defparam un13_lock_cry_19_0.INIT0=16'h500a;
+defparam un13_lock_cry_19_0.INIT1=16'h500a;
+defparam un13_lock_cry_19_0.INJECT1_0="NO";
+defparam un13_lock_cry_19_0.INJECT1_1="NO";
+// @16:1296
+  CCU2C un13_lock_cry_21_0 (
+       .A0(un13_lock_21),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_lock_cry_20),
+       .COUT(un13_lock_cry_21_0_COUT),
+       .S0(un13_lock_cry_21_0_S0),
+       .S1(un13_lock_cry_21_i)
+);
+defparam un13_lock_cry_21_0.INIT0=16'h500f;
+defparam un13_lock_cry_21_0.INIT1=16'ha003;
+defparam un13_lock_cry_21_0.INJECT1_0="NO";
+defparam un13_lock_cry_21_0.INJECT1_1="NO";
+  CCU2C un13_unlock_cry_0_0 (
+       .A0(VCC),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_0),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_1),
+       .COUT(un13_unlock_cry_0),
+       .S0(un13_unlock_cry_0_0_S0),
+       .S1(un13_unlock_cry_0_0_S1)
+);
+defparam un13_unlock_cry_0_0.INIT0=16'h5003;
+defparam un13_unlock_cry_0_0.INIT1=16'h500a;
+defparam un13_unlock_cry_0_0.INJECT1_0="NO";
+defparam un13_unlock_cry_0_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_1_0 (
+       .A0(un13_lock_1),
+       .B0(rdiff_comp_lock[2]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_2),
+       .B1(rdiff_comp_lock[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_0),
+       .COUT(un13_unlock_cry_2),
+       .S0(un13_unlock_cry_1_0_S0),
+       .S1(un13_unlock_cry_1_0_S1)
+);
+defparam un13_unlock_cry_1_0.INIT0=16'h900a;
+defparam un13_unlock_cry_1_0.INIT1=16'h900a;
+defparam un13_unlock_cry_1_0.INJECT1_0="NO";
+defparam un13_unlock_cry_1_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_3_0 (
+       .A0(un13_lock_3),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_4),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_2),
+       .COUT(un13_unlock_cry_4),
+       .S0(un13_unlock_cry_3_0_S0),
+       .S1(un13_unlock_cry_3_0_S1)
+);
+defparam un13_unlock_cry_3_0.INIT0=16'h500a;
+defparam un13_unlock_cry_3_0.INIT1=16'h500a;
+defparam un13_unlock_cry_3_0.INJECT1_0="NO";
+defparam un13_unlock_cry_3_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_5_0 (
+       .A0(un13_lock_5),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_6),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_4),
+       .COUT(un13_unlock_cry_6),
+       .S0(un13_unlock_cry_5_0_S0),
+       .S1(un13_unlock_cry_5_0_S1)
+);
+defparam un13_unlock_cry_5_0.INIT0=16'h500a;
+defparam un13_unlock_cry_5_0.INIT1=16'h500a;
+defparam un13_unlock_cry_5_0.INJECT1_0="NO";
+defparam un13_unlock_cry_5_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_7_0 (
+       .A0(un13_lock_7),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_8),
+       .B1(rdiff_comp_lock[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_6),
+       .COUT(un13_unlock_cry_8),
+       .S0(un13_unlock_cry_7_0_S0),
+       .S1(un13_unlock_cry_7_0_S1)
+);
+defparam un13_unlock_cry_7_0.INIT0=16'h500a;
+defparam un13_unlock_cry_7_0.INIT1=16'h900a;
+defparam un13_unlock_cry_7_0.INJECT1_0="NO";
+defparam un13_unlock_cry_7_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_9_0 (
+       .A0(un13_lock_9),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_10),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_8),
+       .COUT(un13_unlock_cry_10),
+       .S0(un13_unlock_cry_9_0_S0),
+       .S1(un13_unlock_cry_9_0_S1)
+);
+defparam un13_unlock_cry_9_0.INIT0=16'h500a;
+defparam un13_unlock_cry_9_0.INIT1=16'h500a;
+defparam un13_unlock_cry_9_0.INJECT1_0="NO";
+defparam un13_unlock_cry_9_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_11_0 (
+       .A0(un13_lock_11),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_12),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_10),
+       .COUT(un13_unlock_cry_12),
+       .S0(un13_unlock_cry_11_0_S0),
+       .S1(un13_unlock_cry_11_0_S1)
+);
+defparam un13_unlock_cry_11_0.INIT0=16'h500a;
+defparam un13_unlock_cry_11_0.INIT1=16'h500a;
+defparam un13_unlock_cry_11_0.INJECT1_0="NO";
+defparam un13_unlock_cry_11_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_13_0 (
+       .A0(un13_lock_13),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_14),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_12),
+       .COUT(un13_unlock_cry_14),
+       .S0(un13_unlock_cry_13_0_S0),
+       .S1(un13_unlock_cry_13_0_S1)
+);
+defparam un13_unlock_cry_13_0.INIT0=16'h500a;
+defparam un13_unlock_cry_13_0.INIT1=16'h500a;
+defparam un13_unlock_cry_13_0.INJECT1_0="NO";
+defparam un13_unlock_cry_13_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_15_0 (
+       .A0(un13_lock_15),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_16),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_14),
+       .COUT(un13_unlock_cry_16),
+       .S0(un13_unlock_cry_15_0_S0),
+       .S1(un13_unlock_cry_15_0_S1)
+);
+defparam un13_unlock_cry_15_0.INIT0=16'h500a;
+defparam un13_unlock_cry_15_0.INIT1=16'h500a;
+defparam un13_unlock_cry_15_0.INJECT1_0="NO";
+defparam un13_unlock_cry_15_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_17_0 (
+       .A0(un13_lock_17),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_18),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_16),
+       .COUT(un13_unlock_cry_18),
+       .S0(un13_unlock_cry_17_0_S0),
+       .S1(un13_unlock_cry_17_0_S1)
+);
+defparam un13_unlock_cry_17_0.INIT0=16'h500a;
+defparam un13_unlock_cry_17_0.INIT1=16'h500a;
+defparam un13_unlock_cry_17_0.INJECT1_0="NO";
+defparam un13_unlock_cry_17_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_19_0 (
+       .A0(un13_lock_19),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(un13_lock_20),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_18),
+       .COUT(un13_unlock_cry_20),
+       .S0(un13_unlock_cry_19_0_S0),
+       .S1(un13_unlock_cry_19_0_S1)
+);
+defparam un13_unlock_cry_19_0.INIT0=16'h500a;
+defparam un13_unlock_cry_19_0.INIT1=16'h500a;
+defparam un13_unlock_cry_19_0.INJECT1_0="NO";
+defparam un13_unlock_cry_19_0.INJECT1_1="NO";
+// @16:1290
+  CCU2C un13_unlock_cry_21_0 (
+       .A0(un13_lock_21),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(un13_unlock_cry_20),
+       .COUT(un13_unlock_cry_21_0_COUT),
+       .S0(un13_unlock_cry_21_0_S0),
+       .S1(un13_unlock_cry_21)
+);
+defparam un13_unlock_cry_21_0.INIT0=16'h500f;
+defparam un13_unlock_cry_21_0.INIT1=16'h5003;
+defparam un13_unlock_cry_21_0.INJECT1_0="NO";
+defparam un13_unlock_cry_21_0.INJECT1_1="NO";
+//@8:425
+//@16:1801
+//@8:425
+// @16:1211
+  sync_0s phb_sync_inst (
+       .phb(phb),
+       .rhb_sync(rhb_sync),
+       .sli_rst(sli_rst),
+       .pll_refclki(pll_refclki)
+);
+// @16:1220
+  sync_0s_6 rtc_sync_inst (
+       .rtc_pul(rtc_pul),
+       .ppul_sync(ppul_sync),
+       .sli_rst(sli_rst),
+       .tx_pclk(tx_pclk)
+);
+// @16:1228
+  sync_0s_0 pdiff_sync_inst (
+       .ppul_sync(ppul_sync),
+       .pdiff_sync(pdiff_sync),
+       .sli_rst(sli_rst),
+       .pll_refclki(pll_refclki)
+);
+  VHI VCC_0 (
+       .Z(VCC)
+);
+// @16:865
+  VLO GND_cZ (
+       .Z(GND)
+);
+endmodule /* serdes_sync_1sll_core_Z1_layer1 */
+
+module serdes_sync_1rsl_core_Z2_layer1 (
+  rx_pcs_rst_c,
+  serdes_rst_dual_c,
+  tx_serdes_rst_c,
+  rsl_tx_pcs_rst_c,
+  rst_dual_c,
+  rsl_rx_pcs_rst_c,
+  rsl_tx_serdes_rst_c,
+  rsl_tx_rdy,
+  pll_lock_i,
+  pll_refclki,
+  rsl_rx_rdy,
+  rx_cdr_lol_s,
+  rx_los_low_s,
+  rsl_rst,
+  rxrefclk,
+  rx_serdes_rst_c,
+  rsl_rx_serdes_rst_c,
+  rsl_serdes_rst_dual_c,
+  rsl_disable,
+  tx_pcs_rst_c
+)
+;
+input rx_pcs_rst_c ;
+input serdes_rst_dual_c ;
+input tx_serdes_rst_c ;
+output rsl_tx_pcs_rst_c ;
+input rst_dual_c ;
+output rsl_rx_pcs_rst_c ;
+output rsl_tx_serdes_rst_c ;
+output rsl_tx_rdy ;
+input pll_lock_i ;
+input pll_refclki ;
+output rsl_rx_rdy ;
+input rx_cdr_lol_s ;
+input rx_los_low_s ;
+input rsl_rst ;
+input rxrefclk ;
+input rx_serdes_rst_c ;
+output rsl_rx_serdes_rst_c ;
+output rsl_serdes_rst_dual_c ;
+input rsl_disable ;
+input tx_pcs_rst_c ;
+wire rx_pcs_rst_c ;
+wire serdes_rst_dual_c ;
+wire tx_serdes_rst_c ;
+wire rsl_tx_pcs_rst_c ;
+wire rst_dual_c ;
+wire rsl_rx_pcs_rst_c ;
+wire rsl_tx_serdes_rst_c ;
+wire rsl_tx_rdy ;
+wire pll_lock_i ;
+wire pll_refclki ;
+wire rsl_rx_rdy ;
+wire rx_cdr_lol_s ;
+wire rx_los_low_s ;
+wire rsl_rst ;
+wire rxrefclk ;
+wire rx_serdes_rst_c ;
+wire rsl_rx_serdes_rst_c ;
+wire rsl_serdes_rst_dual_c ;
+wire rsl_disable ;
+wire tx_pcs_rst_c ;
+wire [2:0] plol0_cnt;
+wire [2:0] plol0_cnt_3;
+wire [0:0] rxsr_appd;
+wire [1:0] rxs_cnt_3;
+wire [1:0] rxs_cnt;
+wire [1:0] rxs_cnt_QN;
+wire [3:0] rlos_db_cnt;
+wire [3:0] rlos_db_cnt_QN;
+wire [17:0] rlols0_cnt_s;
+wire [17:0] rlols0_cnt;
+wire [17:0] rlols0_cnt_QN;
+wire [3:0] rlol_db_cnt;
+wire [3:0] rlol_db_cnt_QN;
+wire [18:0] rlol1_cnt_s;
+wire [18:0] rlol1_cnt;
+wire [18:0] rlol1_cnt_QN;
+wire [11:0] rxr_wt_cnt_s;
+wire [11:0] rxr_wt_cnt;
+wire [11:0] rxr_wt_cnt_QN;
+wire [0:0] rxsr_appd_QN;
+wire [0:0] rxpr_appd;
+wire [0:0] rxpr_appd_QN;
+wire [1:0] txs_cnt;
+wire [1:0] txs_cnt_QN;
+wire [1:1] txs_cnt_RNO;
+wire [1:0] txp_cnt;
+wire [1:0] txp_cnt_QN;
+wire [1:1] txp_cnt_RNO;
+wire [19:0] plol_cnt_s;
+wire [19:0] plol_cnt;
+wire [19:0] plol_cnt_QN;
+wire [2:0] plol0_cnt_QN;
+wire [11:0] txr_wt_cnt_s;
+wire [11:0] txr_wt_cnt;
+wire [11:0] txr_wt_cnt_QN;
+wire [0:0] txpr_appd;
+wire [0:0] txpr_appd_QN;
+wire [0:0] un1_rlol_db_cnt_zero;
+wire [0:0] un1_rlos_db_cnt_zero;
+wire [0:0] un1_rlol_db_cnt_zero_bm;
+wire [0:0] un1_rlol_db_cnt_zero_am;
+wire [0:0] un1_rlos_db_cnt_zero_bm;
+wire [0:0] un1_rlos_db_cnt_zero_am;
+wire [16:0] rlol1_cnt_cry;
+wire [0:0] rlol1_cnt_cry_0_S0;
+wire [17:17] rlol1_cnt_cry_0_COUT;
+wire [16:0] rlols0_cnt_cry;
+wire [0:0] rlols0_cnt_cry_0_S0;
+wire [17:17] rlols0_cnt_s_0_COUT;
+wire [17:17] rlols0_cnt_s_0_S1;
+wire [10:0] txr_wt_cnt_cry;
+wire [0:0] txr_wt_cnt_cry_0_S0;
+wire [11:11] txr_wt_cnt_s_0_COUT;
+wire [11:11] txr_wt_cnt_s_0_S1;
+wire [10:0] rxr_wt_cnt_cry;
+wire [0:0] rxr_wt_cnt_cry_0_S0;
+wire [11:11] rxr_wt_cnt_s_0_COUT;
+wire [11:11] rxr_wt_cnt_s_0_S1;
+wire [18:0] plol_cnt_cry;
+wire [0:0] plol_cnt_cry_0_S0;
+wire [19:19] plol_cnt_s_0_COUT;
+wire [19:19] plol_cnt_s_0_S1;
+wire txdpr_appd ;
+wire txp_rst ;
+wire un2_rdo_tx_pcs_rst_c ;
+wire rlos_db_p1 ;
+wire rlos_db ;
+wire rxp_rst25 ;
+wire plol0_cnt9 ;
+wire waita_plol0 ;
+wire dual_or_serd_rst ;
+wire un18_txr_wt_tc_8 ;
+wire un18_txr_wt_tc_7 ;
+wire un18_txr_wt_tc_6 ;
+wire un1_dual_or_serd_rst_1_1 ;
+wire un1_rui_rst_dual_c_1_1 ;
+wire un17_rxr_wt_tc_8 ;
+wire un17_rxr_wt_tc_7 ;
+wire un17_rxr_wt_tc_6 ;
+wire un3_rx_all_well_1 ;
+wire rlol1_cnt_tc_1 ;
+wire rxs_rst ;
+wire rlol1_cnt_scalar ;
+wire un2_plol_fedge_5_1 ;
+wire un2_plol_fedge_5_i ;
+wire N_2175_0 ;
+wire waita_rlols06 ;
+wire un1_rlols0_cnt_tc ;
+wire waita_rlols0 ;
+wire waita_rlols0_QN ;
+wire VCC ;
+wire wait_calib_RNO ;
+wire un1_rlos_fedge_1 ;
+wire wait_calib ;
+wire wait_calib_QN ;
+wire rxs_rst6 ;
+wire un1_rxs_cnt_tc ;
+wire rxs_rst_QN ;
+wire un2_rlos_redge_1_i ;
+wire rxp_rst2 ;
+wire rxp_rst2_QN ;
+wire rlos_p1 ;
+wire rlos_p2 ;
+wire rlos_p2_QN ;
+wire rlos_p1_QN ;
+wire rlos_db_p1_QN ;
+wire rlos_db_cnt_axb_0 ;
+wire rlos_db_cnt_cry_1_0_S0 ;
+wire rlos_db_cnt_cry_1_0_S1 ;
+wire rlos_db_cnt_s_3_0_S0 ;
+wire un1_rlos_db_cnt_max ;
+wire rlos_db_QN ;
+wire rlols0_cnte ;
+wire rlol_p1 ;
+wire rlol_p2 ;
+wire rlol_p2_QN ;
+wire rlol_p1_QN ;
+wire rlol_db ;
+wire rlol_db_p1 ;
+wire rlol_db_p1_QN ;
+wire rlol_db_cnt_axb_0 ;
+wire rlol_db_cnt_cry_1_0_S0 ;
+wire rlol_db_cnt_cry_1_0_S1 ;
+wire rlol_db_cnt_s_3_0_S0 ;
+wire un1_rlol_db_cnt_max ;
+wire rlol_db_QN ;
+wire rlol1_cnte ;
+wire rxsdr_appd_2 ;
+wire rxsdr_appd_4 ;
+wire rxsdr_appd_QN ;
+wire un1_dual_or_rserd_rst_2_i ;
+wire rxr_wt_en ;
+wire rxr_wt_en_QN ;
+wire rxr_wt_cnte ;
+wire un1_rui_rst_dual_c_1_i ;
+wire rxdpr_appd ;
+wire rxdpr_appd_QN ;
+wire un3_rx_all_well_2 ;
+wire rxr_wt_cnt9 ;
+wire ruo_rx_rdyr_QN ;
+wire un2_rdo_serdes_rst_dual_c_1 ;
+wire un2_rdo_serdes_rst_dual_c_2_i ;
+wire plol_fedge ;
+wire un1_plol0_cnt_tc_1_i ;
+wire waita_plol0_QN ;
+wire un1_plol_cnt_tc ;
+wire un2_plol_cnt_tc ;
+wire txs_rst ;
+wire txs_rst_QN ;
+wire N_10_i ;
+wire un9_plol0_cnt_tc ;
+wire un1_plol0_cnt_tc_1 ;
+wire txp_rst_QN ;
+wire N_11_i ;
+wire pll_lol_p2 ;
+wire pll_lol_p3 ;
+wire pll_lol_p3_QN ;
+wire pll_lol_p1 ;
+wire pll_lol_p2_QN ;
+wire pll_lol_p1_QN ;
+wire txsr_appd_2 ;
+wire txsr_appd_4 ;
+wire txsr_appd_QN ;
+wire un1_dual_or_serd_rst_1_i ;
+wire txr_wt_en ;
+wire txr_wt_en_QN ;
+wire txr_wt_cnte ;
+wire un2_plol_fedge_2 ;
+wire un2_plol_fedge_3_i ;
+wire txdpr_appd_QN ;
+wire ruo_tx_rdyr_QN ;
+wire un2_plol_fedge_8_i ;
+wire rlols0_cnt_tc_1 ;
+wire rlos_redge ;
+wire rlols0_cnt11_0 ;
+wire plol_cnt_scalar ;
+wire rlols0_cnt_scalar ;
+wire un8_rxs_cnt_tc ;
+wire un17_rxr_wt_tc ;
+wire un1_dual_or_rserd_rst_2_0 ;
+wire un1_rxsdr_or_sr_appd_0 ;
+wire un2_rdo_serdes_rst_dual_c_2_0 ;
+wire txr_wt_cnt9 ;
+wire rx_any_rst ;
+wire un18_txr_wt_tc ;
+wire rlols0_cnt_tc_1_10 ;
+wire rlols0_cnt_tc_1_11 ;
+wire rlols0_cnt_tc_1_12 ;
+wire rlols0_cnt_tc_1_13 ;
+wire rlol1_cnt_tc_1_11 ;
+wire rlol1_cnt_tc_1_12 ;
+wire rlol1_cnt_tc_1_13 ;
+wire rlol1_cnt_tc_1_14 ;
+wire un1_plol_cnt_tc_11 ;
+wire un1_plol_cnt_tc_12 ;
+wire un1_plol_cnt_tc_13 ;
+wire un1_plol_cnt_tc_14 ;
+wire CO0_2 ;
+wire rlols0_cnt_tc_1_9 ;
+wire un1_plol_cnt_tc_10 ;
+wire rlol1_cnt_tc_1_10 ;
+wire un3_rx_all_well_2_1 ;
+wire rlos_db_cnt_cry_0 ;
+wire rlos_db_cnt_cry_0_0_S0 ;
+wire rlos_db_cnt_cry_0_0_S1 ;
+wire rlos_db_cnt_cry_2 ;
+wire rlos_db_cnt_s_3_0_COUT ;
+wire rlos_db_cnt_s_3_0_S1 ;
+wire rlol_db_cnt_cry_0 ;
+wire rlol_db_cnt_cry_0_0_S0 ;
+wire rlol_db_cnt_cry_0_0_S1 ;
+wire rlol_db_cnt_cry_2 ;
+wire rlol_db_cnt_s_3_0_COUT ;
+wire rlol_db_cnt_s_3_0_S1 ;
+wire GND ;
+wire N_1 ;
+wire N_2 ;
+wire N_3 ;
+wire N_4 ;
+wire N_5 ;
+wire N_6 ;
+wire N_7 ;
+  LUT4 \genblk1.genblk2.mfor[0].txpr_appd_RNO_0[0]  (
+       .A(txdpr_appd),
+       .B(tx_pcs_rst_c),
+       .C(txp_rst),
+       .D(rsl_disable),
+       .Z(un2_rdo_tx_pcs_rst_c)
+);
+defparam \genblk1.genblk2.mfor[0].txpr_appd_RNO_0[0] .init=16'hEEFE;
+  LUT4 \genblk2.rxp_rst2_RNO  (
+       .A(rsl_serdes_rst_dual_c),
+       .B(rsl_rx_serdes_rst_c),
+       .C(rlos_db_p1),
+       .D(rlos_db),
+       .Z(rxp_rst25)
+);
+defparam \genblk2.rxp_rst2_RNO .init=16'hEFEE;
+  LUT4 \genblk1.plol0_cnt_RNO[1]  (
+       .A(plol0_cnt[1]),
+       .B(plol0_cnt9),
+       .C(waita_plol0),
+       .D(plol0_cnt[0]),
+       .Z(plol0_cnt_3[1])
+);
+defparam \genblk1.plol0_cnt_RNO[1] .init=16'h1222;
+  LUT4 \genblk1.genblk2.un18_txr_wt_tc_6_RNI7IS21  (
+       .A(dual_or_serd_rst),
+       .B(un18_txr_wt_tc_8),
+       .C(un18_txr_wt_tc_7),
+       .D(un18_txr_wt_tc_6),
+       .Z(un1_dual_or_serd_rst_1_1)
+);
+defparam \genblk1.genblk2.un18_txr_wt_tc_6_RNI7IS21 .init=16'h1555;
+  LUT4 \genblk2.genblk3.rxr_wt_en_RNO  (
+       .A(un1_rui_rst_dual_c_1_1),
+       .B(un17_rxr_wt_tc_8),
+       .C(un17_rxr_wt_tc_7),
+       .D(un17_rxr_wt_tc_6),
+       .Z(un3_rx_all_well_1)
+);
+defparam \genblk2.genblk3.rxr_wt_en_RNO .init=16'h2AAA;
+  LUT4 \genblk2.rlos_db_p1_RNIS0OP  (
+       .A(rlol1_cnt_tc_1),
+       .B(rxs_rst),
+       .C(rlos_db_p1),
+       .D(rlos_db),
+       .Z(rlol1_cnt_scalar)
+);
+defparam \genblk2.rlos_db_p1_RNIS0OP .init=16'h1011;
+  LUT4 \genblk1.genblk2.ruo_tx_rdyr_RNO  (
+       .A(un2_plol_fedge_5_1),
+       .B(un18_txr_wt_tc_8),
+       .C(un18_txr_wt_tc_7),
+       .D(un18_txr_wt_tc_6),
+       .Z(un2_plol_fedge_5_i)
+);
+defparam \genblk1.genblk2.ruo_tx_rdyr_RNO .init=16'hD555;
+  LUT4 \genblk2.genblk3.lfor[0].rxsr_appd_RNO[0]  (
+       .A(rxsr_appd[0]),
+       .B(rx_serdes_rst_c),
+       .C(rxs_rst),
+       .D(rsl_disable),
+       .Z(N_2175_0)
+);
+defparam \genblk2.genblk3.lfor[0].rxsr_appd_RNO[0] .init=16'hEEFE;
+// @16:759
+  FD1P3DX \genblk2.waita_rlols0  (
+       .D(waita_rlols06),
+       .SP(un1_rlols0_cnt_tc),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(waita_rlols0)
+);
+// @16:656
+  FD1P3BX \genblk2.wait_calib  (
+       .D(wait_calib_RNO),
+       .SP(un1_rlos_fedge_1),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(wait_calib)
+);
+// @16:694
+  FD1P3DX \genblk2.rxs_rst  (
+       .D(rxs_rst6),
+       .SP(un1_rxs_cnt_tc),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxs_rst)
+);
+// @16:694
+  FD1S3DX \genblk2.rxs_cnt[0]  (
+       .D(rxs_cnt_3[0]),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxs_cnt[0])
+);
+// @16:694
+  FD1S3DX \genblk2.rxs_cnt[1]  (
+       .D(rxs_cnt_3[1]),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxs_cnt[1])
+);
+// @16:806
+  FD1P3BX \genblk2.rxp_rst2  (
+       .D(rxp_rst25),
+       .SP(un2_rlos_redge_1_i),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rxp_rst2)
+);
+// @16:567
+  FD1S3DX \genblk2.rlos_p2  (
+       .D(rlos_p1),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlos_p2)
+);
+// @16:567
+  FD1S3DX \genblk2.rlos_p1  (
+       .D(rx_los_low_s),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlos_p1)
+);
+// @16:567
+  FD1S3BX \genblk2.rlos_db_p1  (
+       .D(rlos_db),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlos_db_p1)
+);
+// @16:640
+  FD1S3BX \genblk2.rlos_db_cnt[0]  (
+       .D(rlos_db_cnt_axb_0),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlos_db_cnt[0])
+);
+// @16:640
+  FD1S3BX \genblk2.rlos_db_cnt[1]  (
+       .D(rlos_db_cnt_cry_1_0_S0),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlos_db_cnt[1])
+);
+// @16:640
+  FD1S3BX \genblk2.rlos_db_cnt[2]  (
+       .D(rlos_db_cnt_cry_1_0_S1),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlos_db_cnt[2])
+);
+// @16:640
+  FD1S3BX \genblk2.rlos_db_cnt[3]  (
+       .D(rlos_db_cnt_s_3_0_S0),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlos_db_cnt[3])
+);
+// @16:649
+  FD1P3BX \genblk2.rlos_db  (
+       .D(rlos_db_cnt[1]),
+       .SP(un1_rlos_db_cnt_max),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlos_db)
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[0]  (
+       .D(rlols0_cnt_s[0]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[0])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[1]  (
+       .D(rlols0_cnt_s[1]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[1])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[2]  (
+       .D(rlols0_cnt_s[2]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[2])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[3]  (
+       .D(rlols0_cnt_s[3]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[3])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[4]  (
+       .D(rlols0_cnt_s[4]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[4])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[5]  (
+       .D(rlols0_cnt_s[5]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[5])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[6]  (
+       .D(rlols0_cnt_s[6]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[6])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[7]  (
+       .D(rlols0_cnt_s[7]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[7])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[8]  (
+       .D(rlols0_cnt_s[8]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[8])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[9]  (
+       .D(rlols0_cnt_s[9]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[9])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[10]  (
+       .D(rlols0_cnt_s[10]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[10])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[11]  (
+       .D(rlols0_cnt_s[11]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[11])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[12]  (
+       .D(rlols0_cnt_s[12]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[12])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[13]  (
+       .D(rlols0_cnt_s[13]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[13])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[14]  (
+       .D(rlols0_cnt_s[14]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[14])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[15]  (
+       .D(rlols0_cnt_s[15]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[15])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[16]  (
+       .D(rlols0_cnt_s[16]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[16])
+);
+// @16:778
+  FD1P3DX \genblk2.rlols0_cnt[17]  (
+       .D(rlols0_cnt_s[17]),
+       .SP(rlols0_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlols0_cnt[17])
+);
+// @16:567
+  FD1S3DX \genblk2.rlol_p2  (
+       .D(rlol_p1),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol_p2)
+);
+// @16:567
+  FD1S3DX \genblk2.rlol_p1  (
+       .D(rx_cdr_lol_s),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol_p1)
+);
+// @16:567
+  FD1S3BX \genblk2.rlol_db_p1  (
+       .D(rlol_db),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlol_db_p1)
+);
+// @16:624
+  FD1S3BX \genblk2.rlol_db_cnt[0]  (
+       .D(rlol_db_cnt_axb_0),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlol_db_cnt[0])
+);
+// @16:624
+  FD1S3BX \genblk2.rlol_db_cnt[1]  (
+       .D(rlol_db_cnt_cry_1_0_S0),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlol_db_cnt[1])
+);
+// @16:624
+  FD1S3BX \genblk2.rlol_db_cnt[2]  (
+       .D(rlol_db_cnt_cry_1_0_S1),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlol_db_cnt[2])
+);
+// @16:624
+  FD1S3BX \genblk2.rlol_db_cnt[3]  (
+       .D(rlol_db_cnt_s_3_0_S0),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlol_db_cnt[3])
+);
+// @16:633
+  FD1P3BX \genblk2.rlol_db  (
+       .D(rlol_db_cnt[1]),
+       .SP(un1_rlol_db_cnt_max),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rlol_db)
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[0]  (
+       .D(rlol1_cnt_s[0]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[0])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[1]  (
+       .D(rlol1_cnt_s[1]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[1])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[2]  (
+       .D(rlol1_cnt_s[2]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[2])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[3]  (
+       .D(rlol1_cnt_s[3]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[3])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[4]  (
+       .D(rlol1_cnt_s[4]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[4])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[5]  (
+       .D(rlol1_cnt_s[5]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[5])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[6]  (
+       .D(rlol1_cnt_s[6]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[6])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[7]  (
+       .D(rlol1_cnt_s[7]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[7])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[8]  (
+       .D(rlol1_cnt_s[8]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[8])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[9]  (
+       .D(rlol1_cnt_s[9]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[9])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[10]  (
+       .D(rlol1_cnt_s[10]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[10])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[11]  (
+       .D(rlol1_cnt_s[11]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[11])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[12]  (
+       .D(rlol1_cnt_s[12]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[12])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[13]  (
+       .D(rlol1_cnt_s[13]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[13])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[14]  (
+       .D(rlol1_cnt_s[14]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[14])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[15]  (
+       .D(rlol1_cnt_s[15]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[15])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[16]  (
+       .D(rlol1_cnt_s[16]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[16])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[17]  (
+       .D(rlol1_cnt_s[17]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[17])
+);
+// @16:680
+  FD1P3DX \genblk2.rlol1_cnt[18]  (
+       .D(rlol1_cnt_s[18]),
+       .SP(rlol1_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rlol1_cnt[18])
+);
+// @16:865
+  FD1S3BX \genblk2.genblk3.rxsdr_appd  (
+       .D(rxsdr_appd_2),
+       .CK(rxrefclk),
+       .PD(rsl_rst),
+       .Q(rxsdr_appd_4)
+);
+// @16:900
+  FD1P3DX \genblk2.genblk3.rxr_wt_en  (
+       .D(un3_rx_all_well_1),
+       .SP(un1_dual_or_rserd_rst_2_i),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_en)
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[0]  (
+       .D(rxr_wt_cnt_s[0]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[0])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[1]  (
+       .D(rxr_wt_cnt_s[1]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[1])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[2]  (
+       .D(rxr_wt_cnt_s[2]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[2])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[3]  (
+       .D(rxr_wt_cnt_s[3]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[3])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[4]  (
+       .D(rxr_wt_cnt_s[4]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[4])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[5]  (
+       .D(rxr_wt_cnt_s[5]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[5])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[6]  (
+       .D(rxr_wt_cnt_s[6]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[6])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[7]  (
+       .D(rxr_wt_cnt_s[7]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[7])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[8]  (
+       .D(rxr_wt_cnt_s[8]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[8])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[9]  (
+       .D(rxr_wt_cnt_s[9]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[9])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[10]  (
+       .D(rxr_wt_cnt_s[10]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[10])
+);
+// @16:909
+  FD1P3DX \genblk2.genblk3.rxr_wt_cnt[11]  (
+       .D(rxr_wt_cnt_s[11]),
+       .SP(rxr_wt_cnte),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxr_wt_cnt[11])
+);
+// @16:871
+  FD1P3DX \genblk2.genblk3.rxdpr_appd  (
+       .D(un1_rui_rst_dual_c_1_1),
+       .SP(un1_rui_rst_dual_c_1_i),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxdpr_appd)
+);
+// @16:920
+  FD1P3DX \genblk2.genblk3.ruo_rx_rdyr  (
+       .D(un3_rx_all_well_2),
+       .SP(rxr_wt_cnt9),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rsl_rx_rdy)
+);
+// @16:882
+  FD1S3DX \genblk2.genblk3.lfor[0].rxsr_appd[0]  (
+       .D(N_2175_0),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxsr_appd[0])
+);
+// @16:888
+  FD1P3DX \genblk2.genblk3.lfor[0].rxpr_appd[0]  (
+       .D(un2_rdo_serdes_rst_dual_c_1),
+       .SP(un2_rdo_serdes_rst_dual_c_2_i),
+       .CK(rxrefclk),
+       .CD(rsl_rst),
+       .Q(rxpr_appd[0])
+);
+// @16:443
+  FD1P3DX \genblk1.waita_plol0  (
+       .D(plol_fedge),
+       .SP(un1_plol0_cnt_tc_1_i),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(waita_plol0)
+);
+// @16:422
+  FD1P3DX \genblk1.txs_rst  (
+       .D(un1_plol_cnt_tc),
+       .SP(un2_plol_cnt_tc),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txs_rst)
+);
+// @16:422
+  FD1S3DX \genblk1.txs_cnt[0]  (
+       .D(N_10_i),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txs_cnt[0])
+);
+// @16:422
+  FD1S3DX \genblk1.txs_cnt[1]  (
+       .D(txs_cnt_RNO[1]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txs_cnt[1])
+);
+// @16:461
+  FD1P3DX \genblk1.txp_rst  (
+       .D(un9_plol0_cnt_tc),
+       .SP(un1_plol0_cnt_tc_1),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txp_rst)
+);
+// @16:461
+  FD1S3DX \genblk1.txp_cnt[0]  (
+       .D(N_11_i),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txp_cnt[0])
+);
+// @16:461
+  FD1S3DX \genblk1.txp_cnt[1]  (
+       .D(txp_cnt_RNO[1]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txp_cnt[1])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[0]  (
+       .D(plol_cnt_s[0]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[0])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[1]  (
+       .D(plol_cnt_s[1]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[1])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[2]  (
+       .D(plol_cnt_s[2]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[2])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[3]  (
+       .D(plol_cnt_s[3]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[3])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[4]  (
+       .D(plol_cnt_s[4]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[4])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[5]  (
+       .D(plol_cnt_s[5]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[5])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[6]  (
+       .D(plol_cnt_s[6]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[6])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[7]  (
+       .D(plol_cnt_s[7]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[7])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[8]  (
+       .D(plol_cnt_s[8]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[8])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[9]  (
+       .D(plol_cnt_s[9]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[9])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[10]  (
+       .D(plol_cnt_s[10]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[10])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[11]  (
+       .D(plol_cnt_s[11]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[11])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[12]  (
+       .D(plol_cnt_s[12]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[12])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[13]  (
+       .D(plol_cnt_s[13]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[13])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[14]  (
+       .D(plol_cnt_s[14]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[14])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[15]  (
+       .D(plol_cnt_s[15]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[15])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[16]  (
+       .D(plol_cnt_s[16]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[16])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[17]  (
+       .D(plol_cnt_s[17]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[17])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[18]  (
+       .D(plol_cnt_s[18]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[18])
+);
+// @16:412
+  FD1S3DX \genblk1.plol_cnt[19]  (
+       .D(plol_cnt_s[19]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol_cnt[19])
+);
+// @16:451
+  FD1S3DX \genblk1.plol0_cnt[0]  (
+       .D(plol0_cnt_3[0]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol0_cnt[0])
+);
+// @16:451
+  FD1S3DX \genblk1.plol0_cnt[1]  (
+       .D(plol0_cnt_3[1]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol0_cnt[1])
+);
+// @16:451
+  FD1S3DX \genblk1.plol0_cnt[2]  (
+       .D(plol0_cnt_3[2]),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(plol0_cnt[2])
+);
+// @16:398
+  FD1S3DX \genblk1.pll_lol_p3  (
+       .D(pll_lol_p2),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(pll_lol_p3)
+);
+// @16:398
+  FD1S3DX \genblk1.pll_lol_p2  (
+       .D(pll_lol_p1),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(pll_lol_p2)
+);
+// @16:398
+  FD1S3DX \genblk1.pll_lol_p1  (
+       .D(pll_lock_i),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(pll_lol_p1)
+);
+// @16:492
+  FD1S3BX \genblk1.genblk2.txsr_appd  (
+       .D(txsr_appd_2),
+       .CK(pll_refclki),
+       .PD(rsl_rst),
+       .Q(txsr_appd_4)
+);
+// @16:519
+  FD1P3DX \genblk1.genblk2.txr_wt_en  (
+       .D(un1_dual_or_serd_rst_1_1),
+       .SP(un1_dual_or_serd_rst_1_i),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_en)
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[0]  (
+       .D(txr_wt_cnt_s[0]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[0])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[1]  (
+       .D(txr_wt_cnt_s[1]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[1])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[2]  (
+       .D(txr_wt_cnt_s[2]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[2])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[3]  (
+       .D(txr_wt_cnt_s[3]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[3])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[4]  (
+       .D(txr_wt_cnt_s[4]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[4])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[5]  (
+       .D(txr_wt_cnt_s[5]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[5])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[6]  (
+       .D(txr_wt_cnt_s[6]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[6])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[7]  (
+       .D(txr_wt_cnt_s[7]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[7])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[8]  (
+       .D(txr_wt_cnt_s[8]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[8])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[9]  (
+       .D(txr_wt_cnt_s[9]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[9])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[10]  (
+       .D(txr_wt_cnt_s[10]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[10])
+);
+// @16:527
+  FD1P3DX \genblk1.genblk2.txr_wt_cnt[11]  (
+       .D(txr_wt_cnt_s[11]),
+       .SP(txr_wt_cnte),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txr_wt_cnt[11])
+);
+// @16:498
+  FD1P3DX \genblk1.genblk2.txdpr_appd  (
+       .D(un2_plol_fedge_2),
+       .SP(un2_plol_fedge_3_i),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txdpr_appd)
+);
+// @16:537
+  FD1P3DX \genblk1.genblk2.ruo_tx_rdyr  (
+       .D(un2_plol_fedge_5_1),
+       .SP(un2_plol_fedge_5_i),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(rsl_tx_rdy)
+);
+// @16:509
+  FD1P3DX \genblk1.genblk2.mfor[0].txpr_appd[0]  (
+       .D(un2_plol_fedge_2),
+       .SP(un2_plol_fedge_8_i),
+       .CK(pll_refclki),
+       .CD(rsl_rst),
+       .Q(txpr_appd[0])
+);
+// @16:422
+  LUT4 \genblk1.txs_cnt_RNO[0]  (
+       .A(txs_cnt[0]),
+       .B(txs_rst),
+       .C(un1_plol_cnt_tc),
+       .D(VCC),
+       .Z(N_10_i)
+);
+defparam \genblk1.txs_cnt_RNO[0] .init=16'hA6A6;
+// @16:434
+  LUT4 \genblk1.txs_cnt_RNO[1]  (
+       .A(txs_cnt[0]),
+       .B(txs_cnt[1]),
+       .C(txs_rst),
+       .D(un1_plol_cnt_tc),
+       .Z(txs_cnt_RNO[1])
+);
+defparam \genblk1.txs_cnt_RNO[1] .init=16'hCC6C;
+// @16:806
+  LUT4 \genblk2.rxp_rst2_RNO_0  (
+       .A(rlols0_cnt_tc_1),
+       .B(rlos_redge),
+       .C(rsl_rx_serdes_rst_c),
+       .D(rsl_serdes_rst_dual_c),
+       .Z(un2_rlos_redge_1_i)
+);
+defparam \genblk2.rxp_rst2_RNO_0 .init=16'hFFFE;
+// @16:519
+  LUT4 \genblk1.genblk2.txr_wt_en_RNO  (
+       .A(txpr_appd[0]),
+       .B(pll_lol_p2),
+       .C(un1_dual_or_serd_rst_1_1),
+       .D(rsl_tx_rdy),
+       .Z(un1_dual_or_serd_rst_1_i)
+);
+defparam \genblk1.genblk2.txr_wt_en_RNO .init=16'h0F2F;
+// @8:395
+  LUT4 \genblk2.wait_calib_RNIKRP81  (
+       .A(rxs_rst),
+       .B(wait_calib),
+       .C(rlol1_cnt_tc_1),
+       .D(rlos_redge),
+       .Z(rlol1_cnte)
+);
+defparam \genblk2.wait_calib_RNIKRP81 .init=16'hFFFE;
+// @16:317
+  LUT4 \genblk2.rxs_rst6  (
+       .A(rlol_db),
+       .B(rlos_db),
+       .C(rlol1_cnt_tc_1),
+       .D(VCC),
+       .Z(rxs_rst6)
+);
+defparam \genblk2.rxs_rst6 .init=16'h2020;
+// @8:395
+  LUT4 \genblk2.waita_rlols0_RNI266C  (
+       .A(rlols0_cnt11_0),
+       .B(waita_rlols0),
+       .C(rlols0_cnt_tc_1),
+       .D(VCC),
+       .Z(rlols0_cnte)
+);
+defparam \genblk2.waita_rlols0_RNI266C .init=16'hFEFE;
+// @8:395
+  LUT4 \genblk2.genblk3.rxr_wt_en_RNI1B6E  (
+       .A(rxr_wt_cnt9),
+       .B(rxr_wt_en),
+       .C(VCC),
+       .D(VCC),
+       .Z(rxr_wt_cnte)
+);
+defparam \genblk2.genblk3.rxr_wt_en_RNI1B6E .init=16'hEEEE;
+// @16:412
+  LUT4 \genblk1.plol_cnt11_i  (
+       .A(pll_lol_p2),
+       .B(un1_plol_cnt_tc),
+       .C(rsl_tx_serdes_rst_c),
+       .D(VCC),
+       .Z(plol_cnt_scalar)
+);
+defparam \genblk1.plol_cnt11_i .init=16'h0202;
+// @16:778
+  LUT4 \genblk2.rlols0_cnt11_i  (
+       .A(rlols0_cnt11_0),
+       .B(rlols0_cnt_tc_1),
+       .C(VCC),
+       .D(VCC),
+       .Z(rlols0_cnt_scalar)
+);
+defparam \genblk2.rlols0_cnt11_i .init=16'h1111;
+// @16:317
+  LUT4 \genblk2.un1_rxs_cnt_tc  (
+       .A(rlol_db),
+       .B(rlos_db),
+       .C(un8_rxs_cnt_tc),
+       .D(rlol1_cnt_tc_1),
+       .Z(un1_rxs_cnt_tc)
+);
+defparam \genblk2.un1_rxs_cnt_tc .init=16'hFEFC;
+// @8:395
+  LUT4 \genblk2.wait_calib_RNO  (
+       .A(rlol_db),
+       .B(rlos_db),
+       .C(rlol1_cnt_tc_1),
+       .D(VCC),
+       .Z(wait_calib_RNO)
+);
+defparam \genblk2.wait_calib_RNO .init=16'hA3A3;
+// @16:509
+  LUT4 \genblk1.genblk2.mfor[0].txpr_appd_RNO[0]  (
+       .A(dual_or_serd_rst),
+       .B(un2_rdo_tx_pcs_rst_c),
+       .C(pll_lol_p2),
+       .D(txsr_appd_4),
+       .Z(un2_plol_fedge_8_i)
+);
+defparam \genblk1.genblk2.mfor[0].txpr_appd_RNO[0] .init=16'hFEFA;
+// @16:900
+  LUT4 \genblk2.genblk3.rxr_wt_en_RNO_0  (
+       .A(un17_rxr_wt_tc),
+       .B(un1_dual_or_rserd_rst_2_0),
+       .C(rsl_rx_serdes_rst_c),
+       .D(rsl_serdes_rst_dual_c),
+       .Z(un1_dual_or_rserd_rst_2_i)
+);
+defparam \genblk2.genblk3.rxr_wt_en_RNO_0 .init=16'hFFFB;
+// @16:888
+  LUT4 \genblk2.genblk3.lfor[0].rxpr_appd_RNO[0]  (
+       .A(un1_rxsdr_or_sr_appd_0),
+       .B(un2_rdo_serdes_rst_dual_c_2_0),
+       .C(rsl_rx_pcs_rst_c),
+       .D(rsl_rx_serdes_rst_c),
+       .Z(un2_rdo_serdes_rst_dual_c_2_i)
+);
+defparam \genblk2.genblk3.lfor[0].rxpr_appd_RNO[0] .init=16'hFFB3;
+// @16:871
+  LUT4 \genblk2.genblk3.rxdpr_appd_RNO  (
+       .A(un1_rui_rst_dual_c_1_1),
+       .B(rst_dual_c),
+       .C(VCC),
+       .D(VCC),
+       .Z(un1_rui_rst_dual_c_1_i)
+);
+defparam \genblk2.genblk3.rxdpr_appd_RNO .init=16'hDDDD;
+// @16:259
+  LUT4 \genblk1.un2_plol_cnt_tc  (
+       .A(txs_cnt[0]),
+       .B(txs_cnt[1]),
+       .C(un1_plol_cnt_tc),
+       .D(VCC),
+       .Z(un2_plol_cnt_tc)
+);
+defparam \genblk1.un2_plol_cnt_tc .init=16'hF8F8;
+// @8:395
+  LUT4 \genblk1.genblk2.txr_wt_en_RNI1JHS  (
+       .A(txr_wt_cnt9),
+       .B(txr_wt_en),
+       .C(VCC),
+       .D(VCC),
+       .Z(txr_wt_cnte)
+);
+defparam \genblk1.genblk2.txr_wt_en_RNI1JHS .init=16'hEEEE;
+// @16:913
+  LUT4 \genblk2.genblk3.rxr_wt_cnt9  (
+       .A(un17_rxr_wt_tc),
+       .B(rlol_db),
+       .C(rlos_db),
+       .D(rx_any_rst),
+       .Z(rxr_wt_cnt9)
+);
+defparam \genblk2.genblk3.rxr_wt_cnt9 .init=16'hFFFE;
+// @16:340
+  LUT4 \genblk2.un1_rlols0_cnt_tc  (
+       .A(rlols0_cnt11_0),
+       .B(waita_rlols06),
+       .C(rlols0_cnt_tc_1),
+       .D(VCC),
+       .Z(un1_rlols0_cnt_tc)
+);
+defparam \genblk2.un1_rlols0_cnt_tc .init=16'hFEFE;
+// @16:322
+  LUT4 \genblk2.un1_rlos_fedge_1  (
+       .A(rlos_db),
+       .B(rlos_db_p1),
+       .C(rlol1_cnt_tc_1),
+       .D(VCC),
+       .Z(un1_rlos_fedge_1)
+);
+defparam \genblk2.un1_rlos_fedge_1 .init=16'hF6F6;
+// @16:498
+  LUT4 \genblk1.genblk2.txdpr_appd_RNO  (
+       .A(dual_or_serd_rst),
+       .B(pll_lol_p2),
+       .C(rst_dual_c),
+       .D(VCC),
+       .Z(un2_plol_fedge_3_i)
+);
+defparam \genblk1.genblk2.txdpr_appd_RNO .init=16'hFEFE;
+// @16:461
+  LUT4 \genblk1.txp_cnt_RNO[0]  (
+       .A(txp_cnt[0]),
+       .B(txp_rst),
+       .C(un9_plol0_cnt_tc),
+       .D(VCC),
+       .Z(N_11_i)
+);
+defparam \genblk1.txp_cnt_RNO[0] .init=16'hA6A6;
+// @16:473
+  LUT4 \genblk1.txp_cnt_RNO[1]  (
+       .A(txp_cnt[0]),
+       .B(txp_cnt[1]),
+       .C(txp_rst),
+       .D(un9_plol0_cnt_tc),
+       .Z(txp_cnt_RNO[1])
+);
+defparam \genblk1.txp_cnt_RNO[1] .init=16'hCC6C;
+// @16:366
+  LUT4 un3_rx_all_well_2_cZ (
+       .A(rlol_db),
+       .B(rlos_db),
+       .C(rx_any_rst),
+       .D(VCC),
+       .Z(un3_rx_all_well_2)
+);
+defparam un3_rx_all_well_2_cZ.init=16'h0101;
+// @16:530
+  LUT4 \genblk1.genblk2.txr_wt_cnt9  (
+       .A(dual_or_serd_rst),
+       .B(un18_txr_wt_tc),
+       .C(rsl_tx_pcs_rst_c),
+       .D(rst_dual_c),
+       .Z(txr_wt_cnt9)
+);
+defparam \genblk1.genblk2.txr_wt_cnt9 .init=16'hFFFE;
+// @16:282
+  LUT4 un2_plol_fedge_5_1_cZ (
+       .A(dual_or_serd_rst),
+       .B(pll_lol_p2),
+       .C(rsl_tx_pcs_rst_c),
+       .D(rst_dual_c),
+       .Z(un2_plol_fedge_5_1)
+);
+defparam un2_plol_fedge_5_1_cZ.init=16'h0001;
+// @16:388
+  LUT4 rlols0_cnt_tc_1_cZ (
+       .A(rlols0_cnt_tc_1_10),
+       .B(rlols0_cnt_tc_1_11),
+       .C(rlols0_cnt_tc_1_12),
+       .D(rlols0_cnt_tc_1_13),
+       .Z(rlols0_cnt_tc_1)
+);
+defparam rlols0_cnt_tc_1_cZ.init=16'h8000;
+// @16:387
+  LUT4 rlol1_cnt_tc_1_cZ (
+       .A(rlol1_cnt_tc_1_11),
+       .B(rlol1_cnt_tc_1_12),
+       .C(rlol1_cnt_tc_1_13),
+       .D(rlol1_cnt_tc_1_14),
+       .Z(rlol1_cnt_tc_1)
+);
+defparam rlol1_cnt_tc_1_cZ.init=16'h8000;
+// @16:386
+  LUT4 \genblk1.un1_plol_cnt_tc  (
+       .A(un1_plol_cnt_tc_11),
+       .B(un1_plol_cnt_tc_12),
+       .C(un1_plol_cnt_tc_13),
+       .D(un1_plol_cnt_tc_14),
+       .Z(un1_plol_cnt_tc)
+);
+defparam \genblk1.un1_plol_cnt_tc .init=16'h8000;
+// @16:625
+  LUT4 \un1_genblk2.rlol_db_cnt_axb_0  (
+       .A(rlol_db_cnt[0]),
+       .B(un1_rlol_db_cnt_zero[0]),
+       .C(VCC),
+       .D(VCC),
+       .Z(rlol_db_cnt_axb_0)
+);
+defparam \un1_genblk2.rlol_db_cnt_axb_0 .init=16'h9999;
+// @16:641
+  LUT4 \un1_genblk2.rlos_db_cnt_axb_0  (
+       .A(rlos_db_cnt[0]),
+       .B(un1_rlos_db_cnt_zero[0]),
+       .C(VCC),
+       .D(VCC),
+       .Z(rlos_db_cnt_axb_0)
+);
+defparam \un1_genblk2.rlos_db_cnt_axb_0 .init=16'h9999;
+// @16:443
+  LUT4 \genblk1.waita_plol0_RNO  (
+       .A(pll_lol_p2),
+       .B(pll_lol_p3),
+       .C(un9_plol0_cnt_tc),
+       .D(VCC),
+       .Z(un1_plol0_cnt_tc_1_i)
+);
+defparam \genblk1.waita_plol0_RNO .init=16'hF6F6;
+// @16:452
+  LUT4 \genblk1.plol0_cnt_3[2]  (
+       .A(CO0_2),
+       .B(plol0_cnt9),
+       .C(plol0_cnt[1]),
+       .D(plol0_cnt[2]),
+       .Z(plol0_cnt_3[2])
+);
+defparam \genblk1.plol0_cnt_3[2] .init=16'h1320;
+// @16:452
+  LUT4 \genblk1.plol0_cnt_3[0]  (
+       .A(plol0_cnt9),
+       .B(plol0_cnt[0]),
+       .C(waita_plol0),
+       .D(VCC),
+       .Z(plol0_cnt_3[0])
+);
+defparam \genblk1.plol0_cnt_3[0] .init=16'h1414;
+// @16:211
+  LUT4 un1_rui_rst_dual_c_1_1_cZ (
+       .A(rlol_db),
+       .B(rlos_db),
+       .C(rsl_rx_serdes_rst_c),
+       .D(rsl_serdes_rst_dual_c),
+       .Z(un1_rui_rst_dual_c_1_1)
+);
+defparam un1_rui_rst_dual_c_1_1_cZ.init=16'h0001;
+// @16:891
+  LUT4 un2_rdo_serdes_rst_dual_c_1_cZ (
+       .A(rsl_rx_serdes_rst_c),
+       .B(rsl_serdes_rst_dual_c),
+       .C(rx_cdr_lol_s),
+       .D(rx_los_low_s),
+       .Z(un2_rdo_serdes_rst_dual_c_1)
+);
+defparam un2_rdo_serdes_rst_dual_c_1_cZ.init=16'h0001;
+// @16:493
+  LUT4 \genblk1.genblk2.txsr_appd_2  (
+       .A(dual_or_serd_rst),
+       .B(txsr_appd_4),
+       .C(VCC),
+       .D(VCC),
+       .Z(txsr_appd_2)
+);
+defparam \genblk1.genblk2.txsr_appd_2 .init=16'hEEEE;
+// @16:535
+  LUT4 \genblk1.genblk2.un18_txr_wt_tc  (
+       .A(un18_txr_wt_tc_6),
+       .B(un18_txr_wt_tc_7),
+       .C(un18_txr_wt_tc_8),
+       .D(VCC),
+       .Z(un18_txr_wt_tc)
+);
+defparam \genblk1.genblk2.un18_txr_wt_tc .init=16'h8080;
+// @16:211
+  LUT4 un2_plol_fedge_2_cZ (
+       .A(pll_lol_p2),
+       .B(rsl_serdes_rst_dual_c),
+       .C(rsl_tx_serdes_rst_c),
+       .D(VCC),
+       .Z(un2_plol_fedge_2)
+);
+defparam un2_plol_fedge_2_cZ.init=16'h0101;
+// @16:863
+  LUT4 rx_any_rst_cZ (
+       .A(rsl_rx_pcs_rst_c),
+       .B(rsl_rx_serdes_rst_c),
+       .C(rsl_serdes_rst_dual_c),
+       .D(rst_dual_c),
+       .Z(rx_any_rst)
+);
+defparam rx_any_rst_cZ.init=16'hFFFE;
+// @16:535
+  LUT4 \genblk2.genblk3.un17_rxr_wt_tc  (
+       .A(un17_rxr_wt_tc_6),
+       .B(un17_rxr_wt_tc_7),
+       .C(un17_rxr_wt_tc_8),
+       .D(VCC),
+       .Z(un17_rxr_wt_tc)
+);
+defparam \genblk2.genblk3.un17_rxr_wt_tc .init=16'h8080;
+// @16:219
+  LUT4 \un1_rlol_db_cnt_zero_bm_cZ[0]  (
+       .A(rlol_db_cnt[0]),
+       .B(rlol_db_cnt[1]),
+       .C(rlol_db_cnt[2]),
+       .D(rlol_db_cnt[3]),
+       .Z(un1_rlol_db_cnt_zero_bm[0])
+);
+defparam \un1_rlol_db_cnt_zero_bm_cZ[0] .init=16'h8000;
+// @16:219
+  PFUMX \un1_rlol_db_cnt_zero_cZ[0]  (
+       .ALUT(un1_rlol_db_cnt_zero_bm[0]),
+       .BLUT(un1_rlol_db_cnt_zero_am[0]),
+       .C0(rlol_p2),
+       .Z(un1_rlol_db_cnt_zero[0])
+);
+// @16:219
+  LUT4 \un1_rlos_db_cnt_zero_bm_cZ[0]  (
+       .A(rlos_db_cnt[0]),
+       .B(rlos_db_cnt[1]),
+       .C(rlos_db_cnt[2]),
+       .D(rlos_db_cnt[3]),
+       .Z(un1_rlos_db_cnt_zero_bm[0])
+);
+defparam \un1_rlos_db_cnt_zero_bm_cZ[0] .init=16'h8000;
+// @16:219
+  PFUMX \un1_rlos_db_cnt_zero_cZ[0]  (
+       .ALUT(un1_rlos_db_cnt_zero_bm[0]),
+       .BLUT(un1_rlos_db_cnt_zero_am[0]),
+       .C0(rlos_p2),
+       .Z(un1_rlos_db_cnt_zero[0])
+);
+// @16:708
+  LUT4 \rxs_cnt_3_cZ[1]  (
+       .A(rxs_cnt[0]),
+       .B(rxs_cnt[1]),
+       .C(rxs_rst),
+       .D(VCC),
+       .Z(rxs_cnt_3[1])
+);
+defparam \rxs_cnt_3_cZ[1] .init=16'h6464;
+// @16:269
+  LUT4 \genblk1.un1_plol0_cnt_tc_1  (
+       .A(txp_cnt[0]),
+       .B(txp_cnt[1]),
+       .C(un9_plol0_cnt_tc),
+       .D(VCC),
+       .Z(un1_plol0_cnt_tc_1)
+);
+defparam \genblk1.un1_plol0_cnt_tc_1 .init=16'hF8F8;
+// @16:309
+  LUT4 \genblk2.un1_rlol_db_cnt_max  (
+       .A(rlol_db_cnt[0]),
+       .B(rlol_db_cnt[1]),
+       .C(rlol_db_cnt[2]),
+       .D(rlol_db_cnt[3]),
+       .Z(un1_rlol_db_cnt_max)
+);
+defparam \genblk2.un1_rlol_db_cnt_max .init=16'h8001;
+// @16:315
+  LUT4 \genblk2.un1_rlos_db_cnt_max  (
+       .A(rlos_db_cnt[0]),
+       .B(rlos_db_cnt[1]),
+       .C(rlos_db_cnt[2]),
+       .D(rlos_db_cnt[3]),
+       .Z(un1_rlos_db_cnt_max)
+);
+defparam \genblk2.un1_rlos_db_cnt_max .init=16'h8001;
+// @16:764
+  LUT4 \genblk2.waita_rlols06  (
+       .A(rlol_db),
+       .B(rlol_db_p1),
+       .C(rlos_db),
+       .D(rlos_db_p1),
+       .Z(waita_rlols06)
+);
+defparam \genblk2.waita_rlols06 .init=16'h0504;
+// @16:388
+  LUT4 rlols0_cnt_tc_1_13_cZ (
+       .A(rlols0_cnt[16]),
+       .B(rlols0_cnt[17]),
+       .C(rlols0_cnt_tc_1_9),
+       .D(VCC),
+       .Z(rlols0_cnt_tc_1_13)
+);
+defparam rlols0_cnt_tc_1_13_cZ.init=16'h1010;
+// @16:386
+  LUT4 \genblk1.un1_plol_cnt_tc_14  (
+       .A(plol_cnt[5]),
+       .B(plol_cnt[10]),
+       .C(plol_cnt[18]),
+       .D(un1_plol_cnt_tc_10),
+       .Z(un1_plol_cnt_tc_14)
+);
+defparam \genblk1.un1_plol_cnt_tc_14 .init=16'h0100;
+// @16:387
+  LUT4 rlol1_cnt_tc_1_14_cZ (
+       .A(rlol1_cnt[12]),
+       .B(rlol1_cnt[13]),
+       .C(rlol1_cnt[18]),
+       .D(rlol1_cnt_tc_1_10),
+       .Z(rlol1_cnt_tc_1_14)
+);
+defparam rlol1_cnt_tc_1_14_cZ.init=16'h0100;
+// @16:891
+  LUT4 un2_rdo_serdes_rst_dual_c_2_0_cZ (
+       .A(rsl_serdes_rst_dual_c),
+       .B(rx_cdr_lol_s),
+       .C(rx_los_low_s),
+       .D(VCC),
+       .Z(un2_rdo_serdes_rst_dual_c_2_0)
+);
+defparam un2_rdo_serdes_rst_dual_c_2_0_cZ.init=16'h0101;
+// @16:904
+  LUT4 un1_dual_or_rserd_rst_2_0_cZ (
+       .A(un3_rx_all_well_2_1),
+       .B(rlol_db),
+       .C(rlos_db),
+       .D(VCC),
+       .Z(un1_dual_or_rserd_rst_2_0)
+);
+defparam un1_dual_or_rserd_rst_2_0_cZ.init=16'h0101;
+// @16:708
+  LUT4 \rxs_cnt_3_cZ[0]  (
+       .A(rxs_cnt[0]),
+       .B(rxs_cnt[1]),
+       .C(rxs_rst),
+       .D(VCC),
+       .Z(rxs_cnt_3[0])
+);
+defparam \rxs_cnt_3_cZ[0] .init=16'h5252;
+// @16:743
+  LUT4 \rdo_rx_serdes_rst_c_1[0]  (
+       .A(rsl_disable),
+       .B(rxs_rst),
+       .C(rx_serdes_rst_c),
+       .D(VCC),
+       .Z(rsl_rx_serdes_rst_c)
+);
+defparam \rdo_rx_serdes_rst_c_1[0] .init=16'hF4F4;
+// @16:479
+  LUT4 \rdo_tx_pcs_rst_c_1[0]  (
+       .A(rsl_disable),
+       .B(txp_rst),
+       .C(tx_pcs_rst_c),
+       .D(VCC),
+       .Z(rsl_tx_pcs_rst_c)
+);
+defparam \rdo_tx_pcs_rst_c_1[0] .init=16'hF4F4;
+// @16:438
+  LUT4 rdo_tx_serdes_rst_c (
+       .A(rsl_disable),
+       .B(txs_rst),
+       .C(tx_serdes_rst_c),
+       .D(VCC),
+       .Z(rsl_tx_serdes_rst_c)
+);
+defparam rdo_tx_serdes_rst_c.init=16'hF4F4;
+// @16:375
+  LUT4 rdo_serdes_rst_dual_c (
+       .A(rsl_disable),
+       .B(rsl_rst),
+       .C(serdes_rst_dual_c),
+       .D(VCC),
+       .Z(rsl_serdes_rst_dual_c)
+);
+defparam rdo_serdes_rst_dual_c.init=16'hF4F4;
+// @16:906
+  LUT4 \genblk2.genblk3.un3_rx_all_well_2_1  (
+       .A(rxpr_appd[0]),
+       .B(rxdpr_appd),
+       .C(rsl_rx_rdy),
+       .D(VCC),
+       .Z(un3_rx_all_well_2_1)
+);
+defparam \genblk2.genblk3.un3_rx_all_well_2_1 .init=16'h0E0E;
+// @16:852
+  LUT4 \rdo_rx_pcs_rst_c_1[0]  (
+       .A(rsl_disable),
+       .B(rxp_rst2),
+       .C(rx_pcs_rst_c),
+       .D(VCC),
+       .Z(rsl_rx_pcs_rst_c)
+);
+defparam \rdo_rx_pcs_rst_c_1[0] .init=16'hF4F4;
+// @16:459
+  LUT4 \genblk1.un9_plol0_cnt_tc  (
+       .A(plol0_cnt[0]),
+       .B(plol0_cnt[1]),
+       .C(plol0_cnt[2]),
+       .D(VCC),
+       .Z(un9_plol0_cnt_tc)
+);
+defparam \genblk1.un9_plol0_cnt_tc .init=16'h1010;
+// @16:893
+  LUT4 \genblk2.genblk3.lfor[0].un1_rxsdr_or_sr_appd_0  (
+       .A(rxsr_appd[0]),
+       .B(rlol_db),
+       .C(rlos_db),
+       .D(rxsdr_appd_4),
+       .Z(un1_rxsdr_or_sr_appd_0)
+);
+defparam \genblk2.genblk3.lfor[0].un1_rxsdr_or_sr_appd_0 .init=16'hFCA8;
+// @16:535
+  LUT4 \genblk1.genblk2.un18_txr_wt_tc_6  (
+       .A(txr_wt_cnt[0]),
+       .B(txr_wt_cnt[8]),
+       .C(txr_wt_cnt[9]),
+       .D(txr_wt_cnt[11]),
+       .Z(un18_txr_wt_tc_6)
+);
+defparam \genblk1.genblk2.un18_txr_wt_tc_6 .init=16'h4000;
+// @16:535
+  LUT4 \genblk1.genblk2.un18_txr_wt_tc_7  (
+       .A(txr_wt_cnt[3]),
+       .B(txr_wt_cnt[4]),
+       .C(txr_wt_cnt[5]),
+       .D(txr_wt_cnt[7]),
+       .Z(un18_txr_wt_tc_7)
+);
+defparam \genblk1.genblk2.un18_txr_wt_tc_7 .init=16'h8000;
+// @16:535
+  LUT4 \genblk1.genblk2.un18_txr_wt_tc_8  (
+       .A(txr_wt_cnt[1]),
+       .B(txr_wt_cnt[2]),
+       .C(txr_wt_cnt[6]),
+       .D(txr_wt_cnt[10]),
+       .Z(un18_txr_wt_tc_8)
+);
+defparam \genblk1.genblk2.un18_txr_wt_tc_8 .init=16'h0001;
+// @16:535
+  LUT4 \genblk2.genblk3.un17_rxr_wt_tc_6  (
+       .A(rxr_wt_cnt[3]),
+       .B(rxr_wt_cnt[4]),
+       .C(rxr_wt_cnt[5]),
+       .D(rxr_wt_cnt[7]),
+       .Z(un17_rxr_wt_tc_6)
+);
+defparam \genblk2.genblk3.un17_rxr_wt_tc_6 .init=16'h8000;
+// @16:535
+  LUT4 \genblk2.genblk3.un17_rxr_wt_tc_7  (
+       .A(rxr_wt_cnt[0]),
+       .B(rxr_wt_cnt[8]),
+       .C(rxr_wt_cnt[9]),
+       .D(rxr_wt_cnt[11]),
+       .Z(un17_rxr_wt_tc_7)
+);
+defparam \genblk2.genblk3.un17_rxr_wt_tc_7 .init=16'h4000;
+// @16:535
+  LUT4 \genblk2.genblk3.un17_rxr_wt_tc_8  (
+       .A(rxr_wt_cnt[1]),
+       .B(rxr_wt_cnt[2]),
+       .C(rxr_wt_cnt[6]),
+       .D(rxr_wt_cnt[10]),
+       .Z(un17_rxr_wt_tc_8)
+);
+defparam \genblk2.genblk3.un17_rxr_wt_tc_8 .init=16'h0001;
+// @16:388
+  LUT4 rlols0_cnt_tc_1_9_cZ (
+       .A(rlols0_cnt[9]),
+       .B(rlols0_cnt[11]),
+       .C(rlols0_cnt[12]),
+       .D(rlols0_cnt[13]),
+       .Z(rlols0_cnt_tc_1_9)
+);
+defparam rlols0_cnt_tc_1_9_cZ.init=16'h0001;
+// @16:388
+  LUT4 rlols0_cnt_tc_1_10_cZ (
+       .A(rlols0_cnt[5]),
+       .B(rlols0_cnt[6]),
+       .C(rlols0_cnt[7]),
+       .D(rlols0_cnt[8]),
+       .Z(rlols0_cnt_tc_1_10)
+);
+defparam rlols0_cnt_tc_1_10_cZ.init=16'h0001;
+// @16:388
+  LUT4 rlols0_cnt_tc_1_11_cZ (
+       .A(rlols0_cnt[1]),
+       .B(rlols0_cnt[2]),
+       .C(rlols0_cnt[3]),
+       .D(rlols0_cnt[4]),
+       .Z(rlols0_cnt_tc_1_11)
+);
+defparam rlols0_cnt_tc_1_11_cZ.init=16'h0001;
+// @16:388
+  LUT4 rlols0_cnt_tc_1_12_cZ (
+       .A(rlols0_cnt[0]),
+       .B(rlols0_cnt[10]),
+       .C(rlols0_cnt[14]),
+       .D(rlols0_cnt[15]),
+       .Z(rlols0_cnt_tc_1_12)
+);
+defparam rlols0_cnt_tc_1_12_cZ.init=16'h4000;
+// @16:386
+  LUT4 \genblk1.un1_plol_cnt_tc_10  (
+       .A(plol_cnt[1]),
+       .B(plol_cnt[6]),
+       .C(plol_cnt[7]),
+       .D(plol_cnt[12]),
+       .Z(un1_plol_cnt_tc_10)
+);
+defparam \genblk1.un1_plol_cnt_tc_10 .init=16'h0080;
+// @16:386
+  LUT4 \genblk1.un1_plol_cnt_tc_11  (
+       .A(plol_cnt[8]),
+       .B(plol_cnt[9]),
+       .C(plol_cnt[11]),
+       .D(plol_cnt[13]),
+       .Z(un1_plol_cnt_tc_11)
+);
+defparam \genblk1.un1_plol_cnt_tc_11 .init=16'h8000;
+// @16:386
+  LUT4 \genblk1.un1_plol_cnt_tc_12  (
+       .A(plol_cnt[14]),
+       .B(plol_cnt[15]),
+       .C(plol_cnt[16]),
+       .D(plol_cnt[17]),
+       .Z(un1_plol_cnt_tc_12)
+);
+defparam \genblk1.un1_plol_cnt_tc_12 .init=16'h8000;
+// @16:386
+  LUT4 \genblk1.un1_plol_cnt_tc_13  (
+       .A(plol_cnt[2]),
+       .B(plol_cnt[3]),
+       .C(plol_cnt[4]),
+       .D(plol_cnt[19]),
+       .Z(un1_plol_cnt_tc_13)
+);
+defparam \genblk1.un1_plol_cnt_tc_13 .init=16'h0100;
+// @16:387
+  LUT4 rlol1_cnt_tc_1_10_cZ (
+       .A(rlol1_cnt[14]),
+       .B(rlol1_cnt[15]),
+       .C(rlol1_cnt[16]),
+       .D(rlol1_cnt[17]),
+       .Z(rlol1_cnt_tc_1_10)
+);
+defparam rlol1_cnt_tc_1_10_cZ.init=16'h0800;
+// @16:387
+  LUT4 rlol1_cnt_tc_1_11_cZ (
+       .A(rlol1_cnt[0]),
+       .B(rlol1_cnt[1]),
+       .C(rlol1_cnt[2]),
+       .D(rlol1_cnt[3]),
+       .Z(rlol1_cnt_tc_1_11)
+);
+defparam rlol1_cnt_tc_1_11_cZ.init=16'h0001;
+// @16:387
+  LUT4 rlol1_cnt_tc_1_12_cZ (
+       .A(rlol1_cnt[4]),
+       .B(rlol1_cnt[5]),
+       .C(rlol1_cnt[6]),
+       .D(rlol1_cnt[7]),
+       .Z(rlol1_cnt_tc_1_12)
+);
+defparam rlol1_cnt_tc_1_12_cZ.init=16'h0001;
+// @16:387
+  LUT4 rlol1_cnt_tc_1_13_cZ (
+       .A(rlol1_cnt[8]),
+       .B(rlol1_cnt[9]),
+       .C(rlol1_cnt[10]),
+       .D(rlol1_cnt[11]),
+       .Z(rlol1_cnt_tc_1_13)
+);
+defparam rlol1_cnt_tc_1_13_cZ.init=16'h0001;
+// @16:457
+  LUT4 \genblk1.plol0_cnt_3_RNO[2]  (
+       .A(plol0_cnt[0]),
+       .B(waita_plol0),
+       .C(VCC),
+       .D(VCC),
+       .Z(CO0_2)
+);
+defparam \genblk1.plol0_cnt_3_RNO[2] .init=16'h8888;
+// @16:441
+  LUT4 plol_fedge_cZ (
+       .A(pll_lol_p2),
+       .B(pll_lol_p3),
+       .C(VCC),
+       .D(VCC),
+       .Z(plol_fedge)
+);
+defparam plol_fedge_cZ.init=16'h4444;
+// @16:436
+  LUT4 \genblk2.un8_rxs_cnt_tc  (
+       .A(rxs_cnt[0]),
+       .B(rxs_cnt[1]),
+       .C(VCC),
+       .D(VCC),
+       .Z(un8_rxs_cnt_tc)
+);
+defparam \genblk2.un8_rxs_cnt_tc .init=16'h8888;
+// @16:757
+  LUT4 rlos_redge_cZ (
+       .A(rlos_db),
+       .B(rlos_db_p1),
+       .C(VCC),
+       .D(VCC),
+       .Z(rlos_redge)
+);
+defparam rlos_redge_cZ.init=16'h2222;
+// @16:866
+  LUT4 \genblk2.genblk3.rxsdr_appd_2  (
+       .A(rxsdr_appd_4),
+       .B(serdes_rst_dual_c),
+       .C(VCC),
+       .D(VCC),
+       .Z(rxsdr_appd_2)
+);
+defparam \genblk2.genblk3.rxsdr_appd_2 .init=16'hEEEE;
+// @16:219
+  LUT4 \un1_rlos_db_cnt_zero_am_cZ[0]  (
+       .A(rlos_db_cnt[0]),
+       .B(rlos_db_cnt[1]),
+       .C(rlos_db_cnt[2]),
+       .D(rlos_db_cnt[3]),
+       .Z(un1_rlos_db_cnt_zero_am[0])
+);
+defparam \un1_rlos_db_cnt_zero_am_cZ[0] .init=16'h0001;
+// @16:219
+  LUT4 \un1_rlol_db_cnt_zero_am_cZ[0]  (
+       .A(rlol_db_cnt[0]),
+       .B(rlol_db_cnt[1]),
+       .C(rlol_db_cnt[2]),
+       .D(rlol_db_cnt[3]),
+       .Z(un1_rlol_db_cnt_zero_am[0])
+);
+defparam \un1_rlol_db_cnt_zero_am_cZ[0] .init=16'h0001;
+// @16:488
+  LUT4 dual_or_serd_rst_cZ (
+       .A(rsl_serdes_rst_dual_c),
+       .B(tx_serdes_rst_c),
+       .C(txs_rst),
+       .D(rsl_disable),
+       .Z(dual_or_serd_rst)
+);
+defparam dual_or_serd_rst_cZ.init=16'hEEFE;
+// @16:454
+  LUT4 \genblk1.plol0_cnt9  (
+       .A(pll_lol_p2),
+       .B(plol0_cnt[2]),
+       .C(plol0_cnt[1]),
+       .D(plol0_cnt[0]),
+       .Z(plol0_cnt9)
+);
+defparam \genblk1.plol0_cnt9 .init=16'hAAAE;
+// @16:783
+  LUT4 \genblk2.rlols0_cnt11_0  (
+       .A(rlol_db_p1),
+       .B(rlol_db),
+       .C(rlos_db_p1),
+       .D(rlos_db),
+       .Z(rlols0_cnt11_0)
+);
+defparam \genblk2.rlols0_cnt11_0 .init=16'h4F44;
+  CCU2C \genblk2.rlol1_cnt_cry_0[0]  (
+       .A0(VCC),
+       .B0(rlol1_cnt_scalar),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_7),
+       .COUT(rlol1_cnt_cry[0]),
+       .S0(rlol1_cnt_cry_0_S0[0]),
+       .S1(rlol1_cnt_s[0])
+);
+defparam \genblk2.rlol1_cnt_cry_0[0] .INIT0=16'h500c;
+defparam \genblk2.rlol1_cnt_cry_0[0] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[0] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[0] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[1]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[1]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[0]),
+       .COUT(rlol1_cnt_cry[2]),
+       .S0(rlol1_cnt_s[1]),
+       .S1(rlol1_cnt_s[2])
+);
+defparam \genblk2.rlol1_cnt_cry_0[1] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[1] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[1] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[1] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[3]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[3]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[4]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[2]),
+       .COUT(rlol1_cnt_cry[4]),
+       .S0(rlol1_cnt_s[3]),
+       .S1(rlol1_cnt_s[4])
+);
+defparam \genblk2.rlol1_cnt_cry_0[3] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[3] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[3] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[3] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[5]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[5]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[6]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[4]),
+       .COUT(rlol1_cnt_cry[6]),
+       .S0(rlol1_cnt_s[5]),
+       .S1(rlol1_cnt_s[6])
+);
+defparam \genblk2.rlol1_cnt_cry_0[5] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[5] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[5] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[5] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[7]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[7]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[8]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[6]),
+       .COUT(rlol1_cnt_cry[8]),
+       .S0(rlol1_cnt_s[7]),
+       .S1(rlol1_cnt_s[8])
+);
+defparam \genblk2.rlol1_cnt_cry_0[7] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[7] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[7] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[7] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[9]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[9]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[10]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[8]),
+       .COUT(rlol1_cnt_cry[10]),
+       .S0(rlol1_cnt_s[9]),
+       .S1(rlol1_cnt_s[10])
+);
+defparam \genblk2.rlol1_cnt_cry_0[9] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[9] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[9] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[9] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[11]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[11]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[12]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[10]),
+       .COUT(rlol1_cnt_cry[12]),
+       .S0(rlol1_cnt_s[11]),
+       .S1(rlol1_cnt_s[12])
+);
+defparam \genblk2.rlol1_cnt_cry_0[11] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[11] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[11] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[11] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[13]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[13]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[14]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[12]),
+       .COUT(rlol1_cnt_cry[14]),
+       .S0(rlol1_cnt_s[13]),
+       .S1(rlol1_cnt_s[14])
+);
+defparam \genblk2.rlol1_cnt_cry_0[13] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[13] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[13] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[13] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[15]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[15]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[16]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[14]),
+       .COUT(rlol1_cnt_cry[16]),
+       .S0(rlol1_cnt_s[15]),
+       .S1(rlol1_cnt_s[16])
+);
+defparam \genblk2.rlol1_cnt_cry_0[15] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[15] .INIT1=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[15] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[15] .INJECT1_1="NO";
+// @16:680
+  CCU2C \genblk2.rlol1_cnt_cry_0[17]  (
+       .A0(rlol1_cnt_scalar),
+       .B0(rlol1_cnt[17]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol1_cnt_scalar),
+       .B1(rlol1_cnt[18]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol1_cnt_cry[16]),
+       .COUT(rlol1_cnt_cry_0_COUT[17]),
+       .S0(rlol1_cnt_s[17]),
+       .S1(rlol1_cnt_s[18])
+);
+defparam \genblk2.rlol1_cnt_cry_0[17] .INIT0=16'h8000;
+defparam \genblk2.rlol1_cnt_cry_0[17] .INIT1=16'h800a;
+defparam \genblk2.rlol1_cnt_cry_0[17] .INJECT1_0="NO";
+defparam \genblk2.rlol1_cnt_cry_0[17] .INJECT1_1="NO";
+  CCU2C \genblk2.rlols0_cnt_cry_0[0]  (
+       .A0(VCC),
+       .B0(rlols0_cnt_scalar),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_6),
+       .COUT(rlols0_cnt_cry[0]),
+       .S0(rlols0_cnt_cry_0_S0[0]),
+       .S1(rlols0_cnt_s[0])
+);
+defparam \genblk2.rlols0_cnt_cry_0[0] .INIT0=16'h500c;
+defparam \genblk2.rlols0_cnt_cry_0[0] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[0] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[0] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[1]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[1]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[0]),
+       .COUT(rlols0_cnt_cry[2]),
+       .S0(rlols0_cnt_s[1]),
+       .S1(rlols0_cnt_s[2])
+);
+defparam \genblk2.rlols0_cnt_cry_0[1] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[1] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[1] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[1] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[3]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[3]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[4]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[2]),
+       .COUT(rlols0_cnt_cry[4]),
+       .S0(rlols0_cnt_s[3]),
+       .S1(rlols0_cnt_s[4])
+);
+defparam \genblk2.rlols0_cnt_cry_0[3] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[3] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[3] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[3] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[5]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[5]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[6]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[4]),
+       .COUT(rlols0_cnt_cry[6]),
+       .S0(rlols0_cnt_s[5]),
+       .S1(rlols0_cnt_s[6])
+);
+defparam \genblk2.rlols0_cnt_cry_0[5] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[5] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[5] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[5] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[7]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[7]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[8]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[6]),
+       .COUT(rlols0_cnt_cry[8]),
+       .S0(rlols0_cnt_s[7]),
+       .S1(rlols0_cnt_s[8])
+);
+defparam \genblk2.rlols0_cnt_cry_0[7] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[7] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[7] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[7] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[9]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[9]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[10]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[8]),
+       .COUT(rlols0_cnt_cry[10]),
+       .S0(rlols0_cnt_s[9]),
+       .S1(rlols0_cnt_s[10])
+);
+defparam \genblk2.rlols0_cnt_cry_0[9] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[9] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[9] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[9] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[11]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[11]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[12]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[10]),
+       .COUT(rlols0_cnt_cry[12]),
+       .S0(rlols0_cnt_s[11]),
+       .S1(rlols0_cnt_s[12])
+);
+defparam \genblk2.rlols0_cnt_cry_0[11] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[11] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[11] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[11] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[13]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[13]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[14]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[12]),
+       .COUT(rlols0_cnt_cry[14]),
+       .S0(rlols0_cnt_s[13]),
+       .S1(rlols0_cnt_s[14])
+);
+defparam \genblk2.rlols0_cnt_cry_0[13] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[13] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[13] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[13] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_cry_0[15]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[15]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlols0_cnt_scalar),
+       .B1(rlols0_cnt[16]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[14]),
+       .COUT(rlols0_cnt_cry[16]),
+       .S0(rlols0_cnt_s[15]),
+       .S1(rlols0_cnt_s[16])
+);
+defparam \genblk2.rlols0_cnt_cry_0[15] .INIT0=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[15] .INIT1=16'h8000;
+defparam \genblk2.rlols0_cnt_cry_0[15] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_cry_0[15] .INJECT1_1="NO";
+// @16:778
+  CCU2C \genblk2.rlols0_cnt_s_0[17]  (
+       .A0(rlols0_cnt_scalar),
+       .B0(rlols0_cnt[17]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlols0_cnt_cry[16]),
+       .COUT(rlols0_cnt_s_0_COUT[17]),
+       .S0(rlols0_cnt_s[17]),
+       .S1(rlols0_cnt_s_0_S1[17])
+);
+defparam \genblk2.rlols0_cnt_s_0[17] .INIT0=16'h800a;
+defparam \genblk2.rlols0_cnt_s_0[17] .INIT1=16'h5003;
+defparam \genblk2.rlols0_cnt_s_0[17] .INJECT1_0="NO";
+defparam \genblk2.rlols0_cnt_s_0[17] .INJECT1_1="NO";
+  CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[0]  (
+       .A0(VCC),
+       .B0(txr_wt_cnt9),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(txr_wt_cnt9),
+       .B1(txr_wt_cnt[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_5),
+       .COUT(txr_wt_cnt_cry[0]),
+       .S0(txr_wt_cnt_cry_0_S0[0]),
+       .S1(txr_wt_cnt_s[0])
+);
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[0] .INIT0=16'h5003;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[0] .INIT1=16'h4000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[0] .INJECT1_0="NO";
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[0] .INJECT1_1="NO";
+// @16:527
+  CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[1]  (
+       .A0(txr_wt_cnt9),
+       .B0(txr_wt_cnt[1]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(txr_wt_cnt9),
+       .B1(txr_wt_cnt[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(txr_wt_cnt_cry[0]),
+       .COUT(txr_wt_cnt_cry[2]),
+       .S0(txr_wt_cnt_s[1]),
+       .S1(txr_wt_cnt_s[2])
+);
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[1] .INIT0=16'h4000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[1] .INIT1=16'h4000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[1] .INJECT1_0="NO";
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[1] .INJECT1_1="NO";
+// @16:527
+  CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[3]  (
+       .A0(txr_wt_cnt9),
+       .B0(txr_wt_cnt[3]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(txr_wt_cnt9),
+       .B1(txr_wt_cnt[4]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(txr_wt_cnt_cry[2]),
+       .COUT(txr_wt_cnt_cry[4]),
+       .S0(txr_wt_cnt_s[3]),
+       .S1(txr_wt_cnt_s[4])
+);
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[3] .INIT0=16'h4000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[3] .INIT1=16'h4000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[3] .INJECT1_0="NO";
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[3] .INJECT1_1="NO";
+// @16:527
+  CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[5]  (
+       .A0(txr_wt_cnt9),
+       .B0(txr_wt_cnt[5]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(txr_wt_cnt9),
+       .B1(txr_wt_cnt[6]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(txr_wt_cnt_cry[4]),
+       .COUT(txr_wt_cnt_cry[6]),
+       .S0(txr_wt_cnt_s[5]),
+       .S1(txr_wt_cnt_s[6])
+);
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[5] .INIT0=16'h4000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[5] .INIT1=16'h4000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[5] .INJECT1_0="NO";
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[5] .INJECT1_1="NO";
+// @16:527
+  CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[7]  (
+       .A0(txr_wt_cnt9),
+       .B0(txr_wt_cnt[7]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(txr_wt_cnt9),
+       .B1(txr_wt_cnt[8]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(txr_wt_cnt_cry[6]),
+       .COUT(txr_wt_cnt_cry[8]),
+       .S0(txr_wt_cnt_s[7]),
+       .S1(txr_wt_cnt_s[8])
+);
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[7] .INIT0=16'h4000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[7] .INIT1=16'h4000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[7] .INJECT1_0="NO";
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[7] .INJECT1_1="NO";
+// @16:527
+  CCU2C \genblk1.genblk2.txr_wt_cnt_cry_0[9]  (
+       .A0(txr_wt_cnt9),
+       .B0(txr_wt_cnt[9]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(txr_wt_cnt9),
+       .B1(txr_wt_cnt[10]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(txr_wt_cnt_cry[8]),
+       .COUT(txr_wt_cnt_cry[10]),
+       .S0(txr_wt_cnt_s[9]),
+       .S1(txr_wt_cnt_s[10])
+);
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[9] .INIT0=16'h4000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[9] .INIT1=16'h4000;
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[9] .INJECT1_0="NO";
+defparam \genblk1.genblk2.txr_wt_cnt_cry_0[9] .INJECT1_1="NO";
+// @16:527
+  CCU2C \genblk1.genblk2.txr_wt_cnt_s_0[11]  (
+       .A0(txr_wt_cnt9),
+       .B0(txr_wt_cnt[11]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(txr_wt_cnt_cry[10]),
+       .COUT(txr_wt_cnt_s_0_COUT[11]),
+       .S0(txr_wt_cnt_s[11]),
+       .S1(txr_wt_cnt_s_0_S1[11])
+);
+defparam \genblk1.genblk2.txr_wt_cnt_s_0[11] .INIT0=16'h4005;
+defparam \genblk1.genblk2.txr_wt_cnt_s_0[11] .INIT1=16'h5003;
+defparam \genblk1.genblk2.txr_wt_cnt_s_0[11] .INJECT1_0="NO";
+defparam \genblk1.genblk2.txr_wt_cnt_s_0[11] .INJECT1_1="NO";
+  CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[0]  (
+       .A0(VCC),
+       .B0(rxr_wt_cnt9),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rxr_wt_cnt9),
+       .B1(rxr_wt_cnt[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_4),
+       .COUT(rxr_wt_cnt_cry[0]),
+       .S0(rxr_wt_cnt_cry_0_S0[0]),
+       .S1(rxr_wt_cnt_s[0])
+);
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[0] .INIT0=16'h5003;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[0] .INIT1=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[0] .INJECT1_0="NO";
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[0] .INJECT1_1="NO";
+// @16:909
+  CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[1]  (
+       .A0(rxr_wt_cnt9),
+       .B0(rxr_wt_cnt[1]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rxr_wt_cnt9),
+       .B1(rxr_wt_cnt[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rxr_wt_cnt_cry[0]),
+       .COUT(rxr_wt_cnt_cry[2]),
+       .S0(rxr_wt_cnt_s[1]),
+       .S1(rxr_wt_cnt_s[2])
+);
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[1] .INIT0=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[1] .INIT1=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[1] .INJECT1_0="NO";
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[1] .INJECT1_1="NO";
+// @16:909
+  CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[3]  (
+       .A0(rxr_wt_cnt9),
+       .B0(rxr_wt_cnt[3]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rxr_wt_cnt9),
+       .B1(rxr_wt_cnt[4]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rxr_wt_cnt_cry[2]),
+       .COUT(rxr_wt_cnt_cry[4]),
+       .S0(rxr_wt_cnt_s[3]),
+       .S1(rxr_wt_cnt_s[4])
+);
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[3] .INIT0=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[3] .INIT1=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[3] .INJECT1_0="NO";
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[3] .INJECT1_1="NO";
+// @16:909
+  CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[5]  (
+       .A0(rxr_wt_cnt9),
+       .B0(rxr_wt_cnt[5]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rxr_wt_cnt9),
+       .B1(rxr_wt_cnt[6]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rxr_wt_cnt_cry[4]),
+       .COUT(rxr_wt_cnt_cry[6]),
+       .S0(rxr_wt_cnt_s[5]),
+       .S1(rxr_wt_cnt_s[6])
+);
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[5] .INIT0=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[5] .INIT1=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[5] .INJECT1_0="NO";
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[5] .INJECT1_1="NO";
+// @16:909
+  CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[7]  (
+       .A0(rxr_wt_cnt9),
+       .B0(rxr_wt_cnt[7]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rxr_wt_cnt9),
+       .B1(rxr_wt_cnt[8]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rxr_wt_cnt_cry[6]),
+       .COUT(rxr_wt_cnt_cry[8]),
+       .S0(rxr_wt_cnt_s[7]),
+       .S1(rxr_wt_cnt_s[8])
+);
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[7] .INIT0=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[7] .INIT1=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[7] .INJECT1_0="NO";
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[7] .INJECT1_1="NO";
+// @16:909
+  CCU2C \genblk2.genblk3.rxr_wt_cnt_cry_0[9]  (
+       .A0(rxr_wt_cnt9),
+       .B0(rxr_wt_cnt[9]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rxr_wt_cnt9),
+       .B1(rxr_wt_cnt[10]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rxr_wt_cnt_cry[8]),
+       .COUT(rxr_wt_cnt_cry[10]),
+       .S0(rxr_wt_cnt_s[9]),
+       .S1(rxr_wt_cnt_s[10])
+);
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[9] .INIT0=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[9] .INIT1=16'h4000;
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[9] .INJECT1_0="NO";
+defparam \genblk2.genblk3.rxr_wt_cnt_cry_0[9] .INJECT1_1="NO";
+// @16:909
+  CCU2C \genblk2.genblk3.rxr_wt_cnt_s_0[11]  (
+       .A0(rxr_wt_cnt9),
+       .B0(rxr_wt_cnt[11]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rxr_wt_cnt_cry[10]),
+       .COUT(rxr_wt_cnt_s_0_COUT[11]),
+       .S0(rxr_wt_cnt_s[11]),
+       .S1(rxr_wt_cnt_s_0_S1[11])
+);
+defparam \genblk2.genblk3.rxr_wt_cnt_s_0[11] .INIT0=16'h4005;
+defparam \genblk2.genblk3.rxr_wt_cnt_s_0[11] .INIT1=16'h5003;
+defparam \genblk2.genblk3.rxr_wt_cnt_s_0[11] .INJECT1_0="NO";
+defparam \genblk2.genblk3.rxr_wt_cnt_s_0[11] .INJECT1_1="NO";
+  CCU2C \genblk1.plol_cnt_cry_0[0]  (
+       .A0(VCC),
+       .B0(plol_cnt_scalar),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_3),
+       .COUT(plol_cnt_cry[0]),
+       .S0(plol_cnt_cry_0_S0[0]),
+       .S1(plol_cnt_s[0])
+);
+defparam \genblk1.plol_cnt_cry_0[0] .INIT0=16'h500c;
+defparam \genblk1.plol_cnt_cry_0[0] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[0] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[0] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[1]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[1]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[2]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[0]),
+       .COUT(plol_cnt_cry[2]),
+       .S0(plol_cnt_s[1]),
+       .S1(plol_cnt_s[2])
+);
+defparam \genblk1.plol_cnt_cry_0[1] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[1] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[1] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[1] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[3]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[3]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[4]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[2]),
+       .COUT(plol_cnt_cry[4]),
+       .S0(plol_cnt_s[3]),
+       .S1(plol_cnt_s[4])
+);
+defparam \genblk1.plol_cnt_cry_0[3] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[3] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[3] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[3] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[5]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[5]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[6]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[4]),
+       .COUT(plol_cnt_cry[6]),
+       .S0(plol_cnt_s[5]),
+       .S1(plol_cnt_s[6])
+);
+defparam \genblk1.plol_cnt_cry_0[5] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[5] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[5] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[5] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[7]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[7]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[8]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[6]),
+       .COUT(plol_cnt_cry[8]),
+       .S0(plol_cnt_s[7]),
+       .S1(plol_cnt_s[8])
+);
+defparam \genblk1.plol_cnt_cry_0[7] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[7] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[7] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[7] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[9]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[9]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[10]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[8]),
+       .COUT(plol_cnt_cry[10]),
+       .S0(plol_cnt_s[9]),
+       .S1(plol_cnt_s[10])
+);
+defparam \genblk1.plol_cnt_cry_0[9] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[9] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[9] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[9] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[11]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[11]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[12]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[10]),
+       .COUT(plol_cnt_cry[12]),
+       .S0(plol_cnt_s[11]),
+       .S1(plol_cnt_s[12])
+);
+defparam \genblk1.plol_cnt_cry_0[11] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[11] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[11] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[11] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[13]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[13]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[14]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[12]),
+       .COUT(plol_cnt_cry[14]),
+       .S0(plol_cnt_s[13]),
+       .S1(plol_cnt_s[14])
+);
+defparam \genblk1.plol_cnt_cry_0[13] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[13] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[13] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[13] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[15]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[15]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[16]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[14]),
+       .COUT(plol_cnt_cry[16]),
+       .S0(plol_cnt_s[15]),
+       .S1(plol_cnt_s[16])
+);
+defparam \genblk1.plol_cnt_cry_0[15] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[15] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[15] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[15] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_cry_0[17]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[17]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(plol_cnt_scalar),
+       .B1(plol_cnt[18]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[16]),
+       .COUT(plol_cnt_cry[18]),
+       .S0(plol_cnt_s[17]),
+       .S1(plol_cnt_s[18])
+);
+defparam \genblk1.plol_cnt_cry_0[17] .INIT0=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[17] .INIT1=16'h8000;
+defparam \genblk1.plol_cnt_cry_0[17] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_cry_0[17] .INJECT1_1="NO";
+// @16:412
+  CCU2C \genblk1.plol_cnt_s_0[19]  (
+       .A0(plol_cnt_scalar),
+       .B0(plol_cnt[19]),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(plol_cnt_cry[18]),
+       .COUT(plol_cnt_s_0_COUT[19]),
+       .S0(plol_cnt_s[19]),
+       .S1(plol_cnt_s_0_S1[19])
+);
+defparam \genblk1.plol_cnt_s_0[19] .INIT0=16'h800a;
+defparam \genblk1.plol_cnt_s_0[19] .INIT1=16'h5003;
+defparam \genblk1.plol_cnt_s_0[19] .INJECT1_0="NO";
+defparam \genblk1.plol_cnt_s_0[19] .INJECT1_1="NO";
+  CCU2C \un1_genblk2.rlos_db_cnt_cry_0_0  (
+       .A0(VCC),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlos_db_cnt[0]),
+       .B1(un1_rlos_db_cnt_zero[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_2),
+       .COUT(rlos_db_cnt_cry_0),
+       .S0(rlos_db_cnt_cry_0_0_S0),
+       .S1(rlos_db_cnt_cry_0_0_S1)
+);
+defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INIT0=16'h5003;
+defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INIT1=16'h900a;
+defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INJECT1_0="NO";
+defparam \un1_genblk2.rlos_db_cnt_cry_0_0 .INJECT1_1="NO";
+// @16:641
+  CCU2C \un1_genblk2.rlos_db_cnt_cry_1_0  (
+       .A0(un1_rlos_db_cnt_zero[0]),
+       .B0(rlos_p2),
+       .C0(rlos_db_cnt[1]),
+       .D0(VCC),
+       .A1(un1_rlos_db_cnt_zero[0]),
+       .B1(rlos_p2),
+       .C1(rlos_db_cnt[2]),
+       .D1(VCC),
+       .CIN(rlos_db_cnt_cry_0),
+       .COUT(rlos_db_cnt_cry_2),
+       .S0(rlos_db_cnt_cry_1_0_S0),
+       .S1(rlos_db_cnt_cry_1_0_S1)
+);
+defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INIT0=16'he101;
+defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INIT1=16'he101;
+defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INJECT1_0="NO";
+defparam \un1_genblk2.rlos_db_cnt_cry_1_0 .INJECT1_1="NO";
+// @16:641
+  CCU2C \un1_genblk2.rlos_db_cnt_s_3_0  (
+       .A0(rlos_db_cnt[3]),
+       .B0(rlos_p2),
+       .C0(un1_rlos_db_cnt_zero[0]),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlos_db_cnt_cry_2),
+       .COUT(rlos_db_cnt_s_3_0_COUT),
+       .S0(rlos_db_cnt_s_3_0_S0),
+       .S1(rlos_db_cnt_s_3_0_S1)
+);
+defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INIT0=16'ha90a;
+defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INIT1=16'h5003;
+defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INJECT1_0="NO";
+defparam \un1_genblk2.rlos_db_cnt_s_3_0 .INJECT1_1="NO";
+  CCU2C \un1_genblk2.rlol_db_cnt_cry_0_0  (
+       .A0(VCC),
+       .B0(VCC),
+       .C0(VCC),
+       .D0(VCC),
+       .A1(rlol_db_cnt[0]),
+       .B1(un1_rlol_db_cnt_zero[0]),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(N_1),
+       .COUT(rlol_db_cnt_cry_0),
+       .S0(rlol_db_cnt_cry_0_0_S0),
+       .S1(rlol_db_cnt_cry_0_0_S1)
+);
+defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INIT0=16'h5003;
+defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INIT1=16'h900a;
+defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INJECT1_0="NO";
+defparam \un1_genblk2.rlol_db_cnt_cry_0_0 .INJECT1_1="NO";
+// @16:625
+  CCU2C \un1_genblk2.rlol_db_cnt_cry_1_0  (
+       .A0(un1_rlol_db_cnt_zero[0]),
+       .B0(rlol_p2),
+       .C0(rlol_db_cnt[1]),
+       .D0(VCC),
+       .A1(un1_rlol_db_cnt_zero[0]),
+       .B1(rlol_p2),
+       .C1(rlol_db_cnt[2]),
+       .D1(VCC),
+       .CIN(rlol_db_cnt_cry_0),
+       .COUT(rlol_db_cnt_cry_2),
+       .S0(rlol_db_cnt_cry_1_0_S0),
+       .S1(rlol_db_cnt_cry_1_0_S1)
+);
+defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INIT0=16'he101;
+defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INIT1=16'he101;
+defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INJECT1_0="NO";
+defparam \un1_genblk2.rlol_db_cnt_cry_1_0 .INJECT1_1="NO";
+// @16:625
+  CCU2C \un1_genblk2.rlol_db_cnt_s_3_0  (
+       .A0(rlol_db_cnt[3]),
+       .B0(rlol_p2),
+       .C0(un1_rlol_db_cnt_zero[0]),
+       .D0(VCC),
+       .A1(VCC),
+       .B1(VCC),
+       .C1(VCC),
+       .D1(VCC),
+       .CIN(rlol_db_cnt_cry_2),
+       .COUT(rlol_db_cnt_s_3_0_COUT),
+       .S0(rlol_db_cnt_s_3_0_S0),
+       .S1(rlol_db_cnt_s_3_0_S1)
+);
+defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INIT0=16'ha90a;
+defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INIT1=16'h5003;
+defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INJECT1_0="NO";
+defparam \un1_genblk2.rlol_db_cnt_s_3_0 .INJECT1_1="NO";
+//@16:865
+//@16:492
+  VHI VCC_0 (
+       .Z(VCC)
+);
+// @16:865
+  VLO GND_cZ (
+       .Z(GND)
+);
+endmodule /* serdes_sync_1rsl_core_Z2_layer1 */
+
+module serdes_sync_1 (
+  hdoutp,
+  hdoutn,
+  hdinp,
+  hdinn,
+  rxrefclk,
+  rx_pclk,
+  tx_pclk,
+  txdata,
+  tx_k,
+  tx_force_disp,
+  tx_disp_sel,
+  rxdata,
+  rx_k,
+  rx_disp_err,
+  rx_cv_err,
+  tx_idle_c,
+  signal_detect_c,
+  rx_los_low_s,
+  lsm_status_s,
+  rx_cdr_lol_s,
+  sli_rst,
+  tx_pwrup_c,
+  rx_pwrup_c,
+  sci_wrdata,
+  sci_addr,
+  sci_rddata,
+  sci_en_dual,
+  sci_sel_dual,
+  sci_en,
+  sci_sel,
+  sci_rd,
+  sci_wrn,
+  sci_int,
+  cyawstn,
+  serdes_pdb,
+  pll_refclki,
+  rsl_disable,
+  rsl_rst,
+  serdes_rst_dual_c,
+  rst_dual_c,
+  tx_serdes_rst_c,
+  tx_pcs_rst_c,
+  pll_lol,
+  rsl_tx_rdy,
+  rx_serdes_rst_c,
+  rx_pcs_rst_c,
+  rsl_rx_rdy
+)
+;
+output hdoutp ;
+output hdoutn ;
+input hdinp ;
+input hdinn ;
+input rxrefclk ;
+output rx_pclk ;
+output tx_pclk ;
+input [7:0] txdata ;
+input [0:0] tx_k ;
+input [0:0] tx_force_disp ;
+input [0:0] tx_disp_sel ;
+output [7:0] rxdata ;
+output [0:0] rx_k ;
+output [0:0] rx_disp_err ;
+output [0:0] rx_cv_err ;
+input tx_idle_c ;
+input signal_detect_c ;
+output rx_los_low_s ;
+output lsm_status_s ;
+output rx_cdr_lol_s ;
+input sli_rst ;
+input tx_pwrup_c ;
+input rx_pwrup_c ;
+input [7:0] sci_wrdata ;
+input [5:0] sci_addr ;
+output [7:0] sci_rddata ;
+input sci_en_dual ;
+input sci_sel_dual ;
+input sci_en ;
+input sci_sel ;
+input sci_rd ;
+input sci_wrn ;
+output sci_int ;
+input cyawstn ;
+input serdes_pdb ;
+input pll_refclki ;
+input rsl_disable ;
+input rsl_rst ;
+input serdes_rst_dual_c ;
+input rst_dual_c ;
+input tx_serdes_rst_c ;
+input tx_pcs_rst_c ;
+output pll_lol ;
+output rsl_tx_rdy ;
+input rx_serdes_rst_c ;
+input rx_pcs_rst_c ;
+output rsl_rx_rdy ;
+wire hdoutp ;
+wire hdoutn ;
+wire hdinp ;
+wire hdinn ;
+wire rxrefclk ;
+wire rx_pclk ;
+wire tx_pclk ;
+wire tx_idle_c ;
+wire signal_detect_c ;
+wire rx_los_low_s ;
+wire lsm_status_s ;
+wire rx_cdr_lol_s ;
+wire sli_rst ;
+wire tx_pwrup_c ;
+wire rx_pwrup_c ;
+wire sci_en_dual ;
+wire sci_sel_dual ;
+wire sci_en ;
+wire sci_sel ;
+wire sci_rd ;
+wire sci_wrn ;
+wire sci_int ;
+wire cyawstn ;
+wire serdes_pdb ;
+wire pll_refclki ;
+wire rsl_disable ;
+wire rsl_rst ;
+wire serdes_rst_dual_c ;
+wire rst_dual_c ;
+wire tx_serdes_rst_c ;
+wire tx_pcs_rst_c ;
+wire pll_lol ;
+wire rsl_tx_rdy ;
+wire rx_serdes_rst_c ;
+wire rx_pcs_rst_c ;
+wire rsl_rx_rdy ;
+wire rsl_tx_pcs_rst_c ;
+wire rsl_rx_pcs_rst_c ;
+wire rsl_rx_serdes_rst_c ;
+wire rsl_serdes_rst_dual_c ;
+wire rsl_tx_serdes_rst_c ;
+wire n50_1 ;
+wire n51_1 ;
+wire n1_1 ;
+wire n2_1 ;
+wire n3_1 ;
+wire n4_1 ;
+wire n5_1 ;
+wire n52_1 ;
+wire n6_1 ;
+wire n53_1 ;
+wire n7_1 ;
+wire n54_1 ;
+wire n8_1 ;
+wire n55_1 ;
+wire n56_1 ;
+wire n57_1 ;
+wire n58_1 ;
+wire n59_1 ;
+wire n60_1 ;
+wire n61_1 ;
+wire n62_1 ;
+wire n63_1 ;
+wire n64_1 ;
+wire n65_1 ;
+wire n66_1 ;
+wire n67_1 ;
+wire n68_1 ;
+wire n9_1 ;
+wire n69_1 ;
+wire n70_1 ;
+wire n71_1 ;
+wire n72_1 ;
+wire n73_1 ;
+wire n74_1 ;
+wire n75_1 ;
+wire n76_1 ;
+wire n77_1 ;
+wire n78_1 ;
+wire n79_1 ;
+wire n80_1 ;
+wire n81_1 ;
+wire n82_1 ;
+wire n83_1 ;
+wire n84_1 ;
+wire n85_1 ;
+wire n86_1 ;
+wire n87_1 ;
+wire n88_1 ;
+wire n89_1 ;
+wire n90_1 ;
+wire n91_1 ;
+wire n10_1 ;
+wire n92_1 ;
+wire n11_1 ;
+wire n93_1 ;
+wire n12_1 ;
+wire n94_1 ;
+wire n95_1 ;
+wire n96_1 ;
+wire n13_1 ;
+wire n97_1 ;
+wire n14_1 ;
+wire n98_1 ;
+wire n15_1 ;
+wire n99_1 ;
+wire n16_1 ;
+wire n100_1 ;
+wire n101_1 ;
+wire n17_1 ;
+wire n102_1 ;
+wire n18_1 ;
+wire n103_1 ;
+wire n104_1 ;
+wire n115_1 ;
+wire n19_1 ;
+wire n20_1 ;
+wire n21_1 ;
+wire n22_1 ;
+wire n23_1 ;
+wire n24_1 ;
+wire n25_1 ;
+wire n26_1 ;
+wire n27_1 ;
+wire n28_1 ;
+wire n29_1 ;
+wire n30_1 ;
+wire n31_1 ;
+wire n32_1 ;
+wire n33_1 ;
+wire n34_1 ;
+wire n35_1 ;
+wire n36_1 ;
+wire n37_1 ;
+wire n38_1 ;
+wire n39_1 ;
+wire n40_1 ;
+wire n41_1 ;
+wire n42_1 ;
+wire n43_1 ;
+wire n44_1 ;
+wire n45_1 ;
+wire n46_1 ;
+wire n49_1 ;
+wire GND ;
+wire VCC ;
+  VLO GND_0 (
+       .Z(GND)
+);
+  VHI VCC_0 (
+       .Z(VCC)
+);
+// @16:865
+  PUR PUR_INST (
+       .PUR(VCC)
+);
+// @16:865
+  GSR GSR_INST (
+       .GSR(VCC)
+);
+// @8:160
+(* CHAN="CH0" *)  DCUA DCU0_inst (
+       .CH0_HDINP(hdinp),
+       .CH1_HDINP(GND),
+       .CH0_HDINN(hdinn),
+       .CH1_HDINN(GND),
+       .D_TXBIT_CLKP_FROM_ND(GND),
+       .D_TXBIT_CLKN_FROM_ND(GND),
+       .D_SYNC_ND(GND),
+       .D_TXPLL_LOL_FROM_ND(GND),
+       .CH0_RX_REFCLK(rxrefclk),
+       .CH1_RX_REFCLK(GND),
+       .CH0_FF_RXI_CLK(rx_pclk),
+       .CH1_FF_RXI_CLK(VCC),
+       .CH0_FF_TXI_CLK(tx_pclk),
+       .CH1_FF_TXI_CLK(VCC),
+       .CH0_FF_EBRD_CLK(VCC),
+       .CH1_FF_EBRD_CLK(VCC),
+       .CH0_FF_TX_D_0(txdata[0]),
+       .CH1_FF_TX_D_0(GND),
+       .CH0_FF_TX_D_1(txdata[1]),
+       .CH1_FF_TX_D_1(GND),
+       .CH0_FF_TX_D_2(txdata[2]),
+       .CH1_FF_TX_D_2(GND),
+       .CH0_FF_TX_D_3(txdata[3]),
+       .CH1_FF_TX_D_3(GND),
+       .CH0_FF_TX_D_4(txdata[4]),
+       .CH1_FF_TX_D_4(GND),
+       .CH0_FF_TX_D_5(txdata[5]),
+       .CH1_FF_TX_D_5(GND),
+       .CH0_FF_TX_D_6(txdata[6]),
+       .CH1_FF_TX_D_6(GND),
+       .CH0_FF_TX_D_7(txdata[7]),
+       .CH1_FF_TX_D_7(GND),
+       .CH0_FF_TX_D_8(tx_k[0]),
+       .CH1_FF_TX_D_8(GND),
+       .CH0_FF_TX_D_9(tx_force_disp[0]),
+       .CH1_FF_TX_D_9(GND),
+       .CH0_FF_TX_D_10(tx_disp_sel[0]),
+       .CH1_FF_TX_D_10(GND),
+       .CH0_FF_TX_D_11(GND),
+       .CH1_FF_TX_D_11(GND),
+       .CH0_FF_TX_D_12(GND),
+       .CH1_FF_TX_D_12(GND),
+       .CH0_FF_TX_D_13(GND),
+       .CH1_FF_TX_D_13(GND),
+       .CH0_FF_TX_D_14(GND),
+       .CH1_FF_TX_D_14(GND),
+       .CH0_FF_TX_D_15(GND),
+       .CH1_FF_TX_D_15(GND),
+       .CH0_FF_TX_D_16(GND),
+       .CH1_FF_TX_D_16(GND),
+       .CH0_FF_TX_D_17(GND),
+       .CH1_FF_TX_D_17(GND),
+       .CH0_FF_TX_D_18(GND),
+       .CH1_FF_TX_D_18(GND),
+       .CH0_FF_TX_D_19(GND),
+       .CH1_FF_TX_D_19(GND),
+       .CH0_FF_TX_D_20(GND),
+       .CH1_FF_TX_D_20(GND),
+       .CH0_FF_TX_D_21(GND),
+       .CH1_FF_TX_D_21(GND),
+       .CH0_FF_TX_D_22(GND),
+       .CH1_FF_TX_D_22(GND),
+       .CH0_FF_TX_D_23(GND),
+       .CH1_FF_TX_D_23(GND),
+       .CH0_FFC_EI_EN(tx_idle_c),
+       .CH1_FFC_EI_EN(GND),
+       .CH0_FFC_PCIE_DET_EN(GND),
+       .CH1_FFC_PCIE_DET_EN(GND),
+       .CH0_FFC_PCIE_CT(GND),
+       .CH1_FFC_PCIE_CT(GND),
+       .CH0_FFC_SB_INV_RX(GND),
+       .CH1_FFC_SB_INV_RX(GND),
+       .CH0_FFC_ENABLE_CGALIGN(GND),
+       .CH1_FFC_ENABLE_CGALIGN(GND),
+       .CH0_FFC_SIGNAL_DETECT(signal_detect_c),
+       .CH1_FFC_SIGNAL_DETECT(GND),
+       .CH0_FFC_FB_LOOPBACK(GND),
+       .CH1_FFC_FB_LOOPBACK(GND),
+       .CH0_FFC_SB_PFIFO_LP(GND),
+       .CH1_FFC_SB_PFIFO_LP(GND),
+       .CH0_FFC_PFIFO_CLR(GND),
+       .CH1_FFC_PFIFO_CLR(GND),
+       .CH0_FFC_RATE_MODE_RX(GND),
+       .CH1_FFC_RATE_MODE_RX(GND),
+       .CH0_FFC_RATE_MODE_TX(GND),
+       .CH1_FFC_RATE_MODE_TX(GND),
+       .CH0_FFC_DIV11_MODE_RX(GND),
+       .CH1_FFC_DIV11_MODE_RX(GND),
+       .CH0_FFC_RX_GEAR_MODE(GND),
+       .CH1_FFC_RX_GEAR_MODE(GND),
+       .CH0_FFC_TX_GEAR_MODE(GND),
+       .CH1_FFC_TX_GEAR_MODE(GND),
+       .CH0_FFC_DIV11_MODE_TX(GND),
+       .CH1_FFC_DIV11_MODE_TX(GND),
+       .CH0_FFC_LDR_CORE2TX_EN(GND),
+       .CH1_FFC_LDR_CORE2TX_EN(GND),
+       .CH0_FFC_LANE_TX_RST(rsl_tx_pcs_rst_c),
+       .CH1_FFC_LANE_TX_RST(GND),
+       .CH0_FFC_LANE_RX_RST(rsl_rx_pcs_rst_c),
+       .CH1_FFC_LANE_RX_RST(GND),
+       .CH0_FFC_RRST(rsl_rx_serdes_rst_c),
+       .CH1_FFC_RRST(GND),
+       .CH0_FFC_TXPWDNB(tx_pwrup_c),
+       .CH1_FFC_TXPWDNB(GND),
+       .CH0_FFC_RXPWDNB(rx_pwrup_c),
+       .CH1_FFC_RXPWDNB(GND),
+       .CH0_LDR_CORE2TX(GND),
+       .CH1_LDR_CORE2TX(GND),
+       .D_SCIWDATA0(sci_wrdata[0]),
+       .D_SCIWDATA1(sci_wrdata[1]),
+       .D_SCIWDATA2(sci_wrdata[2]),
+       .D_SCIWDATA3(sci_wrdata[3]),
+       .D_SCIWDATA4(sci_wrdata[4]),
+       .D_SCIWDATA5(sci_wrdata[5]),
+       .D_SCIWDATA6(sci_wrdata[6]),
+       .D_SCIWDATA7(sci_wrdata[7]),
+       .D_SCIADDR0(sci_addr[0]),
+       .D_SCIADDR1(sci_addr[1]),
+       .D_SCIADDR2(sci_addr[2]),
+       .D_SCIADDR3(sci_addr[3]),
+       .D_SCIADDR4(sci_addr[4]),
+       .D_SCIADDR5(sci_addr[5]),
+       .D_SCIENAUX(sci_en_dual),
+       .D_SCISELAUX(sci_sel_dual),
+       .CH0_SCIEN(sci_en),
+       .CH1_SCIEN(GND),
+       .CH0_SCISEL(sci_sel),
+       .CH1_SCISEL(GND),
+       .D_SCIRD(sci_rd),
+       .D_SCIWSTN(sci_wrn),
+       .D_CYAWSTN(cyawstn),
+       .D_FFC_SYNC_TOGGLE(GND),
+       .D_FFC_DUAL_RST(rst_dual_c),
+       .D_FFC_MACRO_RST(rsl_serdes_rst_dual_c),
+       .D_FFC_MACROPDB(serdes_pdb),
+       .D_FFC_TRST(rsl_tx_serdes_rst_c),
+       .CH0_FFC_CDR_EN_BITSLIP(GND),
+       .CH1_FFC_CDR_EN_BITSLIP(GND),
+       .D_SCAN_ENABLE(GND),
+       .D_SCAN_IN_0(GND),
+       .D_SCAN_IN_1(GND),
+       .D_SCAN_IN_2(GND),
+       .D_SCAN_IN_3(GND),
+       .D_SCAN_IN_4(GND),
+       .D_SCAN_IN_5(GND),
+       .D_SCAN_IN_6(GND),
+       .D_SCAN_IN_7(GND),
+       .D_SCAN_MODE(GND),
+       .D_SCAN_RESET(GND),
+       .D_CIN0(GND),
+       .D_CIN1(GND),
+       .D_CIN2(GND),
+       .D_CIN3(GND),
+       .D_CIN4(GND),
+       .D_CIN5(GND),
+       .D_CIN6(GND),
+       .D_CIN7(GND),
+       .D_CIN8(GND),
+       .D_CIN9(GND),
+       .D_CIN10(GND),
+       .D_CIN11(GND),
+       .CH0_HDOUTP(hdoutp),
+       .CH1_HDOUTP(n50_1),
+       .CH0_HDOUTN(hdoutn),
+       .CH1_HDOUTN(n51_1),
+       .D_TXBIT_CLKP_TO_ND(n1_1),
+       .D_TXBIT_CLKN_TO_ND(n2_1),
+       .D_SYNC_PULSE2ND(n3_1),
+       .D_TXPLL_LOL_TO_ND(n4_1),
+       .CH0_FF_RX_F_CLK(n5_1),
+       .CH1_FF_RX_F_CLK(n52_1),
+       .CH0_FF_RX_H_CLK(n6_1),
+       .CH1_FF_RX_H_CLK(n53_1),
+       .CH0_FF_TX_F_CLK(n7_1),
+       .CH1_FF_TX_F_CLK(n54_1),
+       .CH0_FF_TX_H_CLK(n8_1),
+       .CH1_FF_TX_H_CLK(n55_1),
+       .CH0_FF_RX_PCLK(rx_pclk),
+       .CH1_FF_RX_PCLK(n56_1),
+       .CH0_FF_TX_PCLK(tx_pclk),
+       .CH1_FF_TX_PCLK(n57_1),
+       .CH0_FF_RX_D_0(rxdata[0]),
+       .CH1_FF_RX_D_0(n58_1),
+       .CH0_FF_RX_D_1(rxdata[1]),
+       .CH1_FF_RX_D_1(n59_1),
+       .CH0_FF_RX_D_2(rxdata[2]),
+       .CH1_FF_RX_D_2(n60_1),
+       .CH0_FF_RX_D_3(rxdata[3]),
+       .CH1_FF_RX_D_3(n61_1),
+       .CH0_FF_RX_D_4(rxdata[4]),
+       .CH1_FF_RX_D_4(n62_1),
+       .CH0_FF_RX_D_5(rxdata[5]),
+       .CH1_FF_RX_D_5(n63_1),
+       .CH0_FF_RX_D_6(rxdata[6]),
+       .CH1_FF_RX_D_6(n64_1),
+       .CH0_FF_RX_D_7(rxdata[7]),
+       .CH1_FF_RX_D_7(n65_1),
+       .CH0_FF_RX_D_8(rx_k[0]),
+       .CH1_FF_RX_D_8(n66_1),
+       .CH0_FF_RX_D_9(rx_disp_err[0]),
+       .CH1_FF_RX_D_9(n67_1),
+       .CH0_FF_RX_D_10(rx_cv_err[0]),
+       .CH1_FF_RX_D_10(n68_1),
+       .CH0_FF_RX_D_11(n9_1),
+       .CH1_FF_RX_D_11(n69_1),
+       .CH0_FF_RX_D_12(n70_1),
+       .CH1_FF_RX_D_12(n71_1),
+       .CH0_FF_RX_D_13(n72_1),
+       .CH1_FF_RX_D_13(n73_1),
+       .CH0_FF_RX_D_14(n74_1),
+       .CH1_FF_RX_D_14(n75_1),
+       .CH0_FF_RX_D_15(n76_1),
+       .CH1_FF_RX_D_15(n77_1),
+       .CH0_FF_RX_D_16(n78_1),
+       .CH1_FF_RX_D_16(n79_1),
+       .CH0_FF_RX_D_17(n80_1),
+       .CH1_FF_RX_D_17(n81_1),
+       .CH0_FF_RX_D_18(n82_1),
+       .CH1_FF_RX_D_18(n83_1),
+       .CH0_FF_RX_D_19(n84_1),
+       .CH1_FF_RX_D_19(n85_1),
+       .CH0_FF_RX_D_20(n86_1),
+       .CH1_FF_RX_D_20(n87_1),
+       .CH0_FF_RX_D_21(n88_1),
+       .CH1_FF_RX_D_21(n89_1),
+       .CH0_FF_RX_D_22(n90_1),
+       .CH1_FF_RX_D_22(n91_1),
+       .CH0_FF_RX_D_23(n10_1),
+       .CH1_FF_RX_D_23(n92_1),
+       .CH0_FFS_PCIE_DONE(n11_1),
+       .CH1_FFS_PCIE_DONE(n93_1),
+       .CH0_FFS_PCIE_CON(n12_1),
+       .CH1_FFS_PCIE_CON(n94_1),
+       .CH0_FFS_RLOS(rx_los_low_s),
+       .CH1_FFS_RLOS(n95_1),
+       .CH0_FFS_LS_SYNC_STATUS(lsm_status_s),
+       .CH1_FFS_LS_SYNC_STATUS(n96_1),
+       .CH0_FFS_CC_UNDERRUN(n13_1),
+       .CH1_FFS_CC_UNDERRUN(n97_1),
+       .CH0_FFS_CC_OVERRUN(n14_1),
+       .CH1_FFS_CC_OVERRUN(n98_1),
+       .CH0_FFS_RXFBFIFO_ERROR(n15_1),
+       .CH1_FFS_RXFBFIFO_ERROR(n99_1),
+       .CH0_FFS_TXFBFIFO_ERROR(n16_1),
+       .CH1_FFS_TXFBFIFO_ERROR(n100_1),
+       .CH0_FFS_RLOL(rx_cdr_lol_s),
+       .CH1_FFS_RLOL(n101_1),
+       .CH0_FFS_SKP_ADDED(n17_1),
+       .CH1_FFS_SKP_ADDED(n102_1),
+       .CH0_FFS_SKP_DELETED(n18_1),
+       .CH1_FFS_SKP_DELETED(n103_1),
+       .CH0_LDR_RX2CORE(n104_1),
+       .CH1_LDR_RX2CORE(n115_1),
+       .D_SCIRDATA0(sci_rddata[0]),
+       .D_SCIRDATA1(sci_rddata[1]),
+       .D_SCIRDATA2(sci_rddata[2]),
+       .D_SCIRDATA3(sci_rddata[3]),
+       .D_SCIRDATA4(sci_rddata[4]),
+       .D_SCIRDATA5(sci_rddata[5]),
+       .D_SCIRDATA6(sci_rddata[6]),
+       .D_SCIRDATA7(sci_rddata[7]),
+       .D_SCIINT(sci_int),
+       .D_SCAN_OUT_0(n19_1),
+       .D_SCAN_OUT_1(n20_1),
+       .D_SCAN_OUT_2(n21_1),
+       .D_SCAN_OUT_3(n22_1),
+       .D_SCAN_OUT_4(n23_1),
+       .D_SCAN_OUT_5(n24_1),
+       .D_SCAN_OUT_6(n25_1),
+       .D_SCAN_OUT_7(n26_1),
+       .D_COUT0(n27_1),
+       .D_COUT1(n28_1),
+       .D_COUT2(n29_1),
+       .D_COUT3(n30_1),
+       .D_COUT4(n31_1),
+       .D_COUT5(n32_1),
+       .D_COUT6(n33_1),
+       .D_COUT7(n34_1),
+       .D_COUT8(n35_1),
+       .D_COUT9(n36_1),
+       .D_COUT10(n37_1),
+       .D_COUT11(n38_1),
+       .D_COUT12(n39_1),
+       .D_COUT13(n40_1),
+       .D_COUT14(n41_1),
+       .D_COUT15(n42_1),
+       .D_COUT16(n43_1),
+       .D_COUT17(n44_1),
+       .D_COUT18(n45_1),
+       .D_COUT19(n46_1),
+       .D_REFCLKI(pll_refclki),
+       .D_FFS_PLOL(n49_1)
+);
+defparam DCU0_inst.D_MACROPDB = "0b1";
+defparam DCU0_inst.D_IB_PWDNB = "0b1";
+defparam DCU0_inst.D_XGE_MODE = "0b0";
+defparam DCU0_inst.D_LOW_MARK = "0d4";
+defparam DCU0_inst.D_HIGH_MARK = "0d12";
+defparam DCU0_inst.D_BUS8BIT_SEL = "0b0";
+defparam DCU0_inst.D_CDR_LOL_SET = "0b11";
+defparam DCU0_inst.D_BITCLK_LOCAL_EN = "0b1";
+defparam DCU0_inst.D_BITCLK_ND_EN = "0b0";
+defparam DCU0_inst.D_BITCLK_FROM_ND_EN = "0b0";
+defparam DCU0_inst.D_SYNC_LOCAL_EN = "0b1";
+defparam DCU0_inst.D_SYNC_ND_EN = "0b0";
+defparam DCU0_inst.CH0_UC_MODE = "0b1";
+defparam DCU0_inst.CH0_PCIE_MODE = "0b0";
+defparam DCU0_inst.CH0_RIO_MODE = "0b0";
+defparam DCU0_inst.CH0_WA_MODE = "0b0";
+defparam DCU0_inst.CH0_INVERT_RX = "0b0";
+defparam DCU0_inst.CH0_INVERT_TX = "0b0";
+defparam DCU0_inst.CH0_PRBS_SELECTION = "0b0";
+defparam DCU0_inst.CH0_GE_AN_ENABLE = "0b0";
+defparam DCU0_inst.CH0_PRBS_LOCK = "0b0";
+defparam DCU0_inst.CH0_PRBS_ENABLE = "0b0";
+defparam DCU0_inst.CH0_ENABLE_CG_ALIGN = "0b1";
+defparam DCU0_inst.CH0_TX_GEAR_MODE = "0b0";
+defparam DCU0_inst.CH0_RX_GEAR_MODE = "0b0";
+defparam DCU0_inst.CH0_PCS_DET_TIME_SEL = "0b00";
+defparam DCU0_inst.CH0_PCIE_EI_EN = "0b0";
+defparam DCU0_inst.CH0_TX_GEAR_BYPASS = "0b0";
+defparam DCU0_inst.CH0_ENC_BYPASS = "0b0";
+defparam DCU0_inst.CH0_SB_BYPASS = "0b0";
+defparam DCU0_inst.CH0_RX_SB_BYPASS = "0b0";
+defparam DCU0_inst.CH0_WA_BYPASS = "0b0";
+defparam DCU0_inst.CH0_DEC_BYPASS = "0b0";
+defparam DCU0_inst.CH0_CTC_BYPASS = "0b1";
+defparam DCU0_inst.CH0_RX_GEAR_BYPASS = "0b0";
+defparam DCU0_inst.CH0_LSM_DISABLE = "0b0";
+defparam DCU0_inst.CH0_MATCH_2_ENABLE = "0b0";
+defparam DCU0_inst.CH0_MATCH_4_ENABLE = "0b1";
+defparam DCU0_inst.CH0_MIN_IPG_CNT = "0b11";
+defparam DCU0_inst.CH0_CC_MATCH_1 = "0x1BC";
+defparam DCU0_inst.CH0_CC_MATCH_2 = "0x11C";
+defparam DCU0_inst.CH0_CC_MATCH_3 = "0x11C";
+defparam DCU0_inst.CH0_CC_MATCH_4 = "0x11C";
+defparam DCU0_inst.CH0_UDF_COMMA_MASK = "0x0ff";
+defparam DCU0_inst.CH0_UDF_COMMA_A = "0x083";
+defparam DCU0_inst.CH0_UDF_COMMA_B = "0x07C";
+defparam DCU0_inst.CH0_RX_DCO_CK_DIV = "0b010";
+defparam DCU0_inst.CH0_RCV_DCC_EN = "0b0";
+defparam DCU0_inst.CH0_REQ_LVL_SET = "0b00";
+defparam DCU0_inst.CH0_REQ_EN = "0b1";
+defparam DCU0_inst.CH0_RTERM_RX = "0d22";
+defparam DCU0_inst.CH0_PDEN_SEL = "0b1";
+defparam DCU0_inst.CH0_LDR_RX2CORE_SEL = "0b0";
+defparam DCU0_inst.CH0_LDR_CORE2TX_SEL = "0b0";
+defparam DCU0_inst.CH0_TPWDNB = "0b1";
+defparam DCU0_inst.CH0_RATE_MODE_TX = "0b0";
+defparam DCU0_inst.CH0_RTERM_TX = "0d19";
+defparam DCU0_inst.CH0_TX_CM_SEL = "0b00";
+defparam DCU0_inst.CH0_TDRV_PRE_EN = "0b0";
+defparam DCU0_inst.CH0_TDRV_SLICE0_SEL = "0b00";
+defparam DCU0_inst.CH0_TDRV_SLICE1_SEL = "0b00";
+defparam DCU0_inst.CH0_TDRV_SLICE2_SEL = "0b01";
+defparam DCU0_inst.CH0_TDRV_SLICE3_SEL = "0b01";
+defparam DCU0_inst.CH0_TDRV_SLICE4_SEL = "0b01";
+defparam DCU0_inst.CH0_TDRV_SLICE5_SEL = "0b00";
+defparam DCU0_inst.CH0_TDRV_SLICE0_CUR = "0b000";
+defparam DCU0_inst.CH0_TDRV_SLICE1_CUR = "0b000";
+defparam DCU0_inst.CH0_TDRV_SLICE2_CUR = "0b11";
+defparam DCU0_inst.CH0_TDRV_SLICE3_CUR = "0b11";
+defparam DCU0_inst.CH0_TDRV_SLICE4_CUR = "0b01";
+defparam DCU0_inst.CH0_TDRV_SLICE5_CUR = "0b00";
+defparam DCU0_inst.CH0_TDRV_DAT_SEL = "0b00";
+defparam DCU0_inst.CH0_TX_DIV11_SEL = "0b0";
+defparam DCU0_inst.CH0_RPWDNB = "0b1";
+defparam DCU0_inst.CH0_RATE_MODE_RX = "0b0";
+defparam DCU0_inst.CH0_RLOS_SEL = "0b1";
+defparam DCU0_inst.CH0_RX_LOS_LVL = "0b100";
+defparam DCU0_inst.CH0_RX_LOS_CEQ = "0b11";
+defparam DCU0_inst.CH0_RX_LOS_HYST_EN = "0b0";
+defparam DCU0_inst.CH0_RX_LOS_EN = "0b1";
+defparam DCU0_inst.CH0_RX_DIV11_SEL = "0b0";
+defparam DCU0_inst.CH0_SEL_SD_RX_CLK = "0b1";
+defparam DCU0_inst.CH0_FF_RX_H_CLK_EN = "0b0";
+defparam DCU0_inst.CH0_FF_RX_F_CLK_DIS = "0b0";
+defparam DCU0_inst.CH0_FF_TX_H_CLK_EN = "0b0";
+defparam DCU0_inst.CH0_FF_TX_F_CLK_DIS = "0b0";
+defparam DCU0_inst.CH0_RX_RATE_SEL = "0d10";
+defparam DCU0_inst.CH0_TDRV_POST_EN = "0b0";
+defparam DCU0_inst.CH0_TX_POST_SIGN = "0b0";
+defparam DCU0_inst.CH0_TX_PRE_SIGN = "0b0";
+defparam DCU0_inst.CH0_RXTERM_CM = "0b11";
+defparam DCU0_inst.CH0_RXIN_CM = "0b11";
+defparam DCU0_inst.CH0_LEQ_OFFSET_SEL = "0b0";
+defparam DCU0_inst.CH0_LEQ_OFFSET_TRIM = "0b000";
+defparam DCU0_inst.D_TX_MAX_RATE = "1.25";
+defparam DCU0_inst.CH0_CDR_MAX_RATE = "1.25";
+defparam DCU0_inst.CH0_TXAMPLITUDE = "0d800";
+defparam DCU0_inst.CH0_TXDEPRE = "DISABLED";
+defparam DCU0_inst.CH0_TXDEPOST = "DISABLED";
+defparam DCU0_inst.CH0_PROTOCOL = "G8B10B";
+defparam DCU0_inst.D_ISETLOS = "0d0";
+defparam DCU0_inst.D_SETIRPOLY_AUX = "0b00";
+defparam DCU0_inst.D_SETICONST_AUX = "0b00";
+defparam DCU0_inst.D_SETIRPOLY_CH = "0b00";
+defparam DCU0_inst.D_SETICONST_CH = "0b00";
+defparam DCU0_inst.D_REQ_ISET = "0b000";
+defparam DCU0_inst.D_PD_ISET = "0b00";
+defparam DCU0_inst.D_DCO_CALIB_TIME_SEL = "0b00";
+defparam DCU0_inst.CH0_DCOCTLGI = "0b010";
+defparam DCU0_inst.CH0_DCOATDDLY = "0b00";
+defparam DCU0_inst.CH0_DCOATDCFG = "0b00";
+defparam DCU0_inst.CH0_DCOBYPSATD = "0b1";
+defparam DCU0_inst.CH0_DCOSCALEI = "0b00";
+defparam DCU0_inst.CH0_DCOITUNE4LSB = "0b111";
+defparam DCU0_inst.CH0_DCOIOSTUNE = "0b000";
+defparam DCU0_inst.CH0_DCODISBDAVOID = "0b0";
+defparam DCU0_inst.CH0_DCOCALDIV = "0b001";
+defparam DCU0_inst.CH0_DCONUOFLSB = "0b101";
+defparam DCU0_inst.CH0_DCOIUPDNX2 = "0b1";
+defparam DCU0_inst.CH0_DCOSTEP = "0b00";
+defparam DCU0_inst.CH0_DCOSTARTVAL = "0b000";
+defparam DCU0_inst.CH0_DCOFLTDAC = "0b01";
+defparam DCU0_inst.CH0_DCOITUNE = "0b00";
+defparam DCU0_inst.CH0_DCOFTNRG = "0b110";
+defparam DCU0_inst.CH0_CDR_CNT4SEL = "0b00";
+defparam DCU0_inst.CH0_CDR_CNT8SEL = "0b00";
+defparam DCU0_inst.CH0_BAND_THRESHOLD = "0d0";
+defparam DCU0_inst.CH0_AUTO_FACQ_EN = "0b1";
+defparam DCU0_inst.CH0_AUTO_CALIB_EN = "0b1";
+defparam DCU0_inst.CH0_CALIB_CK_MODE = "0b0";
+defparam DCU0_inst.CH0_REG_BAND_OFFSET = "0d0";
+defparam DCU0_inst.CH0_REG_BAND_SEL = "0d0";
+defparam DCU0_inst.CH0_REG_IDAC_SEL = "0d0";
+defparam DCU0_inst.CH0_REG_IDAC_EN = "0b0";
+defparam DCU0_inst.D_TXPLL_PWDNB = "0b1";
+defparam DCU0_inst.D_SETPLLRC = "0d1";
+defparam DCU0_inst.D_REFCK_MODE = "0b001";
+defparam DCU0_inst.D_TX_VCO_CK_DIV = "0b010";
+defparam DCU0_inst.D_PLL_LOL_SET = "0b01";
+defparam DCU0_inst.D_RG_EN = "0b0";
+defparam DCU0_inst.D_RG_SET = "0b00";
+defparam DCU0_inst.D_CMUSETISCL4VCO = "0b000";
+defparam DCU0_inst.D_CMUSETI4VCO = "0b00";
+defparam DCU0_inst.D_CMUSETINITVCT = "0b00";
+defparam DCU0_inst.D_CMUSETZGM = "0b000";
+defparam DCU0_inst.D_CMUSETP2AGM = "0b000";
+defparam DCU0_inst.D_CMUSETP1GM = "0b000";
+defparam DCU0_inst.D_CMUSETI4CPZ = "0d0";
+defparam DCU0_inst.D_CMUSETI4CPP = "0d0";
+defparam DCU0_inst.D_CMUSETICP4Z = "0b101";
+defparam DCU0_inst.D_CMUSETICP4P = "0b11";
+defparam DCU0_inst.D_CMUSETBIASI = "0b00";
+// @8:425
+  serdes_sync_1sll_core_Z1_layer1 sll_inst (
+       .tx_pclk(tx_pclk),
+       .sli_rst(sli_rst),
+       .pll_refclki(pll_refclki),
+       .pll_lock_i(pll_lol)
+);
+// @8:395
+  serdes_sync_1rsl_core_Z2_layer1 rsl_inst (
+       .rx_pcs_rst_c(rx_pcs_rst_c),
+       .serdes_rst_dual_c(serdes_rst_dual_c),
+       .tx_serdes_rst_c(tx_serdes_rst_c),
+       .rsl_tx_pcs_rst_c(rsl_tx_pcs_rst_c),
+       .rst_dual_c(rst_dual_c),
+       .rsl_rx_pcs_rst_c(rsl_rx_pcs_rst_c),
+       .rsl_tx_serdes_rst_c(rsl_tx_serdes_rst_c),
+       .rsl_tx_rdy(rsl_tx_rdy),
+       .pll_lock_i(pll_lol),
+       .pll_refclki(pll_refclki),
+       .rsl_rx_rdy(rsl_rx_rdy),
+       .rx_cdr_lol_s(rx_cdr_lol_s),
+       .rx_los_low_s(rx_los_low_s),
+       .rsl_rst(rsl_rst),
+       .rxrefclk(rxrefclk),
+       .rx_serdes_rst_c(rx_serdes_rst_c),
+       .rsl_rx_serdes_rst_c(rsl_rx_serdes_rst_c),
+       .rsl_serdes_rst_dual_c(rsl_serdes_rst_dual_c),
+       .rsl_disable(rsl_disable),
+       .tx_pcs_rst_c(tx_pcs_rst_c)
+);
+endmodule /* serdes_sync_1 */
+

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_cck.rpt.db b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_cck.rpt.db
new file mode 100644 (file)
index 0000000..029fa7a
Binary files /dev/null and b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_cck.rpt.db differ

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_scck.rpt.db b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_scck.rpt.db
new file mode 100644 (file)
index 0000000..029fa7a
Binary files /dev/null and b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_scck.rpt.db differ

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_synplify.lpf b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_synplify.lpf
new file mode 100644 (file)
index 0000000..9cbac38
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_synplify.lpf
@@ -0,0 +1,29 @@
+#
+# Logical Preferences generated for Lattice by Synplify maplat, Build 1796R.
+#
+
+# Period Constraints 
+#FREQUENCY PORT "pll_refclki" 100.0 MHz;
+#FREQUENCY PORT "rxrefclk" 100.0 MHz;
+#FREQUENCY NET "tx_pclk" 100.0 MHz;
+
+
+# Output Constraints 
+
+# Input Constraints 
+
+# Point-to-point Delay Constraints 
+
+
+
+# Block Path Constraints 
+#BLOCK PATH FROM CLKNET "tx_pclk" TO CLKNET "rxrefclk";
+#BLOCK PATH FROM CLKNET "tx_pclk" TO CLKNET "pll_refclki";
+#BLOCK PATH FROM CLKNET "rxrefclk" TO CLKNET "tx_pclk";
+#BLOCK PATH FROM CLKNET "rxrefclk" TO CLKNET "pll_refclki";
+#BLOCK PATH FROM CLKNET "pll_refclki" TO CLKNET "tx_pclk";
+#BLOCK PATH FROM CLKNET "pll_refclki" TO CLKNET "rxrefclk";
+
+BLOCK ASYNCPATHS;
+
+# End of generated Logical Preferences.

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_synplify_tmp2.lpf b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_synplify_tmp2.lpf
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_synplify_tmp4.lpf b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_synplify_tmp4.lpf
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_synplify_tmp8.lpf b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_synplify_tmp8.lpf
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/layer0.tlg.rptmap b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/layer0.tlg.rptmap
new file mode 100644 (file)
index 0000000..3910cac
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/layer0.tlg.rptmap
@@ -0,0 +1 @@
+./synwork/layer0.tlg,layer0.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages.

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/layer1.tlg.rptmap b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/layer1.tlg.rptmap
new file mode 100644 (file)
index 0000000..af92e0b
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/layer1.tlg.rptmap
@@ -0,0 +1 @@
+./synwork/layer1.tlg,layer1.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages.

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/linker.rpt.rptmap b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/linker.rpt.rptmap
new file mode 100644 (file)
index 0000000..708d195
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/linker.rpt.rptmap
@@ -0,0 +1 @@
+./synwork/serdes_sync_1_comp.linkerlog,linker.rpt,Summary of linker messages for components that did not bind

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/metrics.db b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/metrics.db
new file mode 100644 (file)
index 0000000..3314034
Binary files /dev/null and b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/metrics.db differ

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_compiler_notes.txt b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_compiler_notes.txt
new file mode 100644 (file)
index 0000000..4814ec4
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_compiler_notes.txt
@@ -0,0 +1,16 @@
+@N|Running in 64-bit mode
+@N|Running in 64-bit mode
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Top entity is set to serdes_sync_1.
+@N|Running in 64-bit mode
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Top entity is set to serdes_sync_1.
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Synthesizing work.serdes_sync_1.v1.
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work.
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1051:7:1051:27|Synthesizing module serdes_sync_1sll_core in library work.
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1287:54:1287:59|Removing redundant assignment.
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1293:52:1293:55|Removing redundant assignment.
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":92:7:92:27|Synthesizing module serdes_sync_1rsl_core in library work.
+@N: CL201 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state.
+@N|Running in 64-bit mode
+

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_compiler_runstatus.xml b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_compiler_runstatus.xml
new file mode 100644 (file)
index 0000000..6d9d2c0
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_compiler_runstatus.xml
@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the job information from compiler to be displayed as part of the summary report.
+*******************************************************************************************-->
+
+<job_run_status name="compiler"> 
+  <report_link name="Detailed report">
+    <data>/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_compiler.srr</data>
+    <title>Synopsys HDL Compiler</title>
+  </report_link> 
+  <job_status>
+    <data>Completed    </data>
+  </job_status>
+<job_info> 
+                       <info name="Notes">
+  <data>15</data>
+  <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_compiler_notes.txt</data></report_link>
+  </info>
+                       <info name="Warnings">
+  <data>77</data>
+  <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_compiler_warnings.txt</data></report_link>
+  </info>
+                       <info name="Errors">
+  <data>0</data>
+  <report_link name="more"><data>/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_compiler_errors.txt</data></report_link>
+  </info>
+                       <info name="CPU Time">
+  <data>-</data>
+  </info>
+                       <info name="Real Time">
+  <data>00h:00m:02s</data>
+  </info>
+                       <info name="Peak Memory">
+  <data>-</data>
+  </info>
+                       <info name="Date &amp;Time">
+  <data type="timestamp">1557476612</data>
+  </info>
+                       </job_info>
+</job_run_status>
\ No newline at end of file

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_compiler_warnings.txt b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_compiler_warnings.txt
new file mode 100644 (file)
index 0000000..6622b46
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_compiler_warnings.txt
@@ -0,0 +1,78 @@
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning register bits 8 to 7 of genblk5.rdiff_comp_unlock[8:6]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[6]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers.
+

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_area_report.xml b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_area_report.xml
new file mode 100644 (file)
index 0000000..8fa1b06
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_area_report.xml
@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the area information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<report_table display_priority="1" name="Area Summary">
+<report_link name="Detailed report">
+<data>/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_resourceusage.rpt</data>
+<title>Resource Usage</title>
+</report_link>
+<parameter tooltip="Total Register bits used" name="Register bits">
+<data>220</data>
+</parameter>
+<parameter tooltip="Total I/O cells used" name="I/O cells">
+<data>0</data>
+</parameter>
+<parameter tcl_name="v_ram" tooltip="Total Block RAMs used" name="Block RAMs">
+<data>0</data>
+</parameter>
+<parameter tcl_name="dsp_used" tooltip="Total DSPs used" name="DSPs">
+<data>0</data>
+</parameter>
+<parameter tcl_name="total_luts" tooltip="Total ORCA LUTs used" name="ORCA LUTs">
+<data>150</data>
+</parameter>
+</report_table>

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_errors.txt b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_errors.txt
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_notes.txt b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_notes.txt
new file mode 100644 (file)
index 0000000..2d9eda0
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_notes.txt
@@ -0,0 +1,23 @@
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1350:0:1350:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1304:0:1304:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance rcount[15:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1759:0:1759:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance pcount[21:0] 
+@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1801:0:1801:5|Removing sequential instance sll_state[0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":412:3:412:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":909:3:909:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":527:3:527:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":778:3:778:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":680:3:680:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] 
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.edn
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_opt_report.xml b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_opt_report.xml
new file mode 100644 (file)
index 0000000..2137e39
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_opt_report.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the optimization information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<report_table display_priority="3" name="Optimizations Summary">
+<parameter tooltip="Non-gated/non-generated clock trees / Gated/generated clock trees" name="Combined Clock Conversion">
+<data>3 / 0</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_combined_clk.rpt</data>
+<title>START OF CLOCK OPTIMIZATION REPORT</title>
+</report_link>
+</parameter>
+</report_table>

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_runstatus.xml b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_runstatus.xml
new file mode 100644 (file)
index 0000000..dc0003e
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_runstatus.xml
@@ -0,0 +1,46 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the job information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<job_run_status name="Mapper">
+<report_link name="Detailed report">
+<data>/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_fpga_mapper.srr</data>
+<title>Synopsys Lattice Technology Mapper</title>
+</report_link>
+<job_status>
+<data>Completed</data>
+</job_status>
+<job_info>
+<info name="Notes">
+<data>23</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_notes.txt</data>
+</report_link>
+</info>
+<info name="Warnings">
+<data>4</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_warnings.txt</data>
+</report_link>
+</info>
+<info name="Errors">
+<data>0</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_errors.txt</data>
+</report_link>
+</info>
+<info name="CPU Time">
+<data>0h:00m:03s</data>
+</info>
+<info name="Real Time">
+<data>0h:00m:03s</data>
+</info>
+<info name="Peak Memory">
+<data>152MB</data>
+</info>
+<info name="Date &amp; Time">
+<data type="timestamp">1557476618</data>
+</info>
+</job_info>
+</job_run_status>

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_timing_report.xml b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_timing_report.xml
new file mode 100644 (file)
index 0000000..ae318a5
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_timing_report.xml
@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+Max Top 5 critical clocks will be reported. For rest user needs to refer to Detailed report
+*******************************************************************************************-->
+<report_table display_priority="2" name="Timing Summary">
+<report_link name="Detailed report">
+<data>/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_fpga_mapper.srr</data>
+<title>START OF TIMING REPORT</title>
+</report_link>
+<row>
+<data tcl_name="clock_name">Clock Name</data>
+<data tcl_name="req_freq">Req Freq</data>
+<data tcl_name="est_freq">Est Freq</data>
+<data tcl_name="slack">Slack</data>
+</row>
+<row>
+<data>serdes_sync_1|pll_refclki</data>
+<data>100.0 MHz</data>
+<data>168.9 MHz</data>
+<data>4.079</data>
+</row>
+<row>
+<data>serdes_sync_1|rxrefclk</data>
+<data>100.0 MHz</data>
+<data>170.5 MHz</data>
+<data>4.136</data>
+</row>
+<row>
+<data>serdes_sync_1|tx_pclk_inferred_clock</data>
+<data>100.0 MHz</data>
+<data>237.5 MHz</data>
+<data>5.789</data>
+</row>
+<row>
+<data>System</data>
+<data>100.0 MHz</data>
+<data>840.7 MHz</data>
+<data>8.810</data>
+</row>
+</report_table>

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_warnings.txt b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_warnings.txt
new file mode 100644 (file)
index 0000000..08dea66
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_fpga_mapper_warnings.txt
@@ -0,0 +1,4 @@
+@W: MT246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":160:4:160:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+@W: MT420 |Found inferred clock serdes_sync_1|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"
+@W: MT420 |Found inferred clock serdes_sync_1|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"
+@W: MT420 |Found inferred clock serdes_sync_1|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk"

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_errors.txt b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_errors.txt
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_notes.txt b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_notes.txt
new file mode 100644 (file)
index 0000000..ff38fdb
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_notes.txt
@@ -0,0 +1,8 @@
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances.

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_runstatus.xml b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_runstatus.xml
new file mode 100644 (file)
index 0000000..e63e0c3
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_runstatus.xml
@@ -0,0 +1,46 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!-- *************************************************************************************
+FILE DESCRIPTION
+The file contains the job information from mapper to be displayed as part of the summary report.
+*******************************************************************************************-->
+<job_run_status name="Mapper">
+<report_link name="Detailed report">
+<data>/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_premap.srr</data>
+<title>Synopsys Lattice Technology Pre-mapping</title>
+</report_link>
+<job_status>
+<data>Completed</data>
+</job_status>
+<job_info>
+<info name="Notes">
+<data>8</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_notes.txt</data>
+</report_link>
+</info>
+<info name="Warnings">
+<data>3</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_warnings.txt</data>
+</report_link>
+</info>
+<info name="Errors">
+<data>0</data>
+<report_link name="more">
+<data>/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_errors.txt</data>
+</report_link>
+</info>
+<info name="CPU Time">
+<data>0h:00m:00s</data>
+</info>
+<info name="Real Time">
+<data>0h:00m:00s</data>
+</info>
+<info name="Peak Memory">
+<data>145MB</data>
+</info>
+<info name="Date &amp; Time">
+<data type="timestamp">1557476614</data>
+</info>
+</job_info>
+</job_run_status>

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_warnings.txt b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_warnings.txt
new file mode 100644 (file)
index 0000000..b332633
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/report/serdes_sync_1_premap_warnings.txt
@@ -0,0 +1,3 @@
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Found inferred clock serdes_sync_1|pll_refclki which controls 92 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Found inferred clock serdes_sync_1|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Found inferred clock serdes_sync_1|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_compiler.srr b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_compiler.srr
new file mode 100644 (file)
index 0000000..471f88d
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_compiler.srr
@@ -0,0 +1,357 @@
+Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Top entity is set to serdes_sync_1.
+VHDL syntax check successful!
+File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd changed - recompiling
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Fri May 10 10:23:30 2019
+
+###########################################################]
+Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v" (library work)
+Verilog syntax check successful!
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Fri May 10 10:23:31 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@N: CD720 :"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ps
+@N:"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Top entity is set to serdes_sync_1.
+File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd changed - recompiling
+File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling
+VHDL syntax check successful!
+File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd changed - recompiling
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Synthesizing work.serdes_sync_1.v1.
+Post processing for work.serdes_sync_1.v1
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB)
+
+
+Process completed successfully.
+# Fri May 10 10:23:31 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v" (library work)
+Verilog syntax check successful!
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work.
+
+       PDATA_RST_VAL=32'b00000000000000000000000000000000
+   Generated name = sync_0s
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1051:7:1051:27|Synthesizing module serdes_sync_1sll_core in library work.
+
+       PPROTOCOL=48'b010001110011100001000010001100010011000001000010
+       PLOL_SETTING=32'b00000000000000000000000000000001
+       PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100
+       PPCIE_MAX_RATE=24'b001100100010111000110101
+       PDIFF_VAL_LOCK=32'b00000000000000000000000000100111
+       PDIFF_VAL_UNLOCK=32'b00000000000000000000000100000110
+       PPCLK_TC=32'b00000000000000100000000000000000
+       PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000
+       PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000
+       PPCLK_DIV11_TC=32'b00000000000000000000000000000000
+       LPLL_LOSS_ST=2'b00
+       LPLL_PRELOSS_ST=2'b01
+       LPLL_PRELOCK_ST=2'b10
+       LPLL_LOCK_ST=2'b11
+       LRCLK_TC=16'b1111111111111111
+       LRCLK_TC_PUL_WIDTH=16'b0000000000110010
+       LHB_WAIT_CNT=8'b11111111
+       LPCLK_TC_0=32'b00000000000000001000000000000000
+       LPCLK_TC_1=32'b00000000000000010000000000000000
+       LPCLK_TC_2=32'b00000000000000100000000000000000
+       LPCLK_TC_3=32'b00000000000000101000000000000000
+       LPCLK_TC_4=32'b00000000000000010000000000000000
+       LPDIFF_LOCK_00=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_10=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_20=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_30=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_40=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_01=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_11=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_21=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_31=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_41=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_02=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_12=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_22=32'b00000000000000000000000011000100
+       LPDIFF_LOCK_32=32'b00000000000000000000000011110101
+       LPDIFF_LOCK_42=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_03=32'b00000000000000000000000010000011
+       LPDIFF_LOCK_13=32'b00000000000000000000000100000110
+       LPDIFF_LOCK_23=32'b00000000000000000000001000001100
+       LPDIFF_LOCK_33=32'b00000000000000000000001010001111
+       LPDIFF_LOCK_43=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011
+       LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110
+       LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010
+       LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001
+       LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111
+       LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000
+       LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000
+       LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000
+       LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100
+       LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001
+       LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010
+       LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111
+       LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001
+   Generated name = serdes_sync_1sll_core_Z1_layer1
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1287:54:1287:59|Removing redundant assignment.
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1293:52:1293:55|Removing redundant assignment.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":92:7:92:27|Synthesizing module serdes_sync_1rsl_core in library work.
+
+       pnum_channels=32'b00000000000000000000000000000001
+       pprotocol=48'b010001110011100001000010001100010011000001000010
+       pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
+       pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_tx_rdy=32'b00000000000000000000101110111000
+       pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_rx_rdy=32'b00000000000000000000101110111000
+       wa_num_cycles=32'b00000000000000000000010000000000
+       dac_num_cycles=32'b00000000000000000000000000000011
+       lreset_pwidth=32'b00000000000000000000000000000011
+       lwait_b4_trst=32'b00000000000010111110101111000010
+       lwait_b4_trst_s=32'b00000000000000000000001100001101
+       lplol_cnt_width=32'b00000000000000000000000000010100
+       lwait_after_plol0=32'b00000000000000000000000000000100
+       lwait_b4_rrst=32'b00000000000000101100000000000000
+       lrrst_wait_width=32'b00000000000000000000000000010100
+       lwait_after_rrst=32'b00000000000011000011010100000000
+       lwait_b4_rrst_s=32'b00000000000000000000000111001100
+       lrlol_cnt_width=32'b00000000000000000000000000010011
+       lwait_after_lols=32'b00000000000000001100010000000000
+       lwait_after_lols_s=32'b00000000000000000000000010010110
+       llols_cnt_width=32'b00000000000000000000000000010010
+       lrdb_max=32'b00000000000000000000000000001111
+       ltxr_wait_width=32'b00000000000000000000000000001100
+       lrxr_wait_width=32'b00000000000000000000000000001100
+   Generated name = serdes_sync_1rsl_core_Z2_layer1
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning register bits 8 to 7 of genblk5.rdiff_comp_unlock[8:6]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[6]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers.
+@N: CL201 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state.
+Extracted state machine for register sll_state
+State machine has 3 reachable states with original encodings of:
+   00
+   01
+   11
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB)
+
+
+Process completed successfully.
+# Fri May 10 10:23:32 2019
+
+###########################################################]
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer0.srs changed - recompiling
+File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.srs changed - recompiling
+
+=======================================================================================
+For a summary of linker messages for components that did not bind, please see log file:
+@L: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.linkerlog
+=======================================================================================
+
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 10:23:32 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 10:23:32 2019
+
+###########################################################]

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_compiler.srr.db b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_compiler.srr.db
new file mode 100644 (file)
index 0000000..b41afd2
Binary files /dev/null and b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_compiler.srr.db differ

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_compiler.srr.rptmap b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_compiler.srr.rptmap
new file mode 100644 (file)
index 0000000..7e5b6f8
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_compiler.srr.rptmap
@@ -0,0 +1 @@
+./synlog/serdes_sync_1_compiler.srr,serdes_sync_1_compiler.srr,Compile Log

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_fpga_mapper.srr b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_fpga_mapper.srr
new file mode 100644 (file)
index 0000000..422efb8
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_fpga_mapper.srr
@@ -0,0 +1,685 @@
+# Fri May 10 10:23:34 2019
+
+Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[2:0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   11 -> 10
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1350:0:1350:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1304:0:1304:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance rcount[15:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1759:0:1759:5|Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance pcount[21:0] 
+@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1801:0:1801:5|Removing sequential instance sll_state[0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":412:3:412:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":909:3:909:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":527:3:527:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":778:3:778:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] 
+@N: MO231 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":680:3:680:8|Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] 
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+   1           0h:00m:01s                   5.35ns              151 /       220
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+@N: FX1019 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+#### START OF CLOCK OPTIMIZATION REPORT #####[
+
+3 non-gated/non-generated clock tree(s) driving 220 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+============================================= Non-Gated/Non-Generated Clocks =============================================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                                   
+--------------------------------------------------------------------------------------------------------------------------
+@K:CKID0001       pll_refclki         port                   90         rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]
+@K:CKID0002       rxrefclk            port                   77         rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]
+@K:CKID0003       DCU0_inst           DCUA                   53         sll_inst.pcount_diff[21]                          
+==========================================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 148MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.edn
+M-2017.03L-SP1-1
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 152MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 152MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB)
+
+@W: MT246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":160:4:160:12|Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
+@W: MT420 |Found inferred clock serdes_sync_1|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"
+@W: MT420 |Found inferred clock serdes_sync_1|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"
+@W: MT420 |Found inferred clock serdes_sync_1|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk"
+
+
+##### START OF TIMING REPORT #####[
+# Timing Report written on Fri May 10 10:23:38 2019
+#
+
+
+Top view:               serdes_sync_1
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 4.079
+
+@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
+                                         Requested     Estimated     Requested     Estimated               Clock        Clock              
+Starting Clock                           Frequency     Frequency     Period        Period        Slack     Type         Group              
+-------------------------------------------------------------------------------------------------------------------------------------------
+serdes_sync_1|pll_refclki                100.0 MHz     168.9 MHz     10.000        5.921         4.079     inferred     Inferred_clkgroup_0
+serdes_sync_1|rxrefclk                   100.0 MHz     170.5 MHz     10.000        5.864         4.136     inferred     Inferred_clkgroup_1
+serdes_sync_1|tx_pclk_inferred_clock     100.0 MHz     237.5 MHz     10.000        4.211         5.789     inferred     Inferred_clkgroup_2
+System                                   100.0 MHz     840.7 MHz     10.000        1.190         8.810     system       system_clkgroup    
+===========================================================================================================================================
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks                                                                      |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Starting                              Ending                                |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+System                                System                                |  10.000      10.000  |  No paths    -      |  No paths    -      |  No paths    -    
+System                                serdes_sync_1|rxrefclk                |  10.000      8.811   |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|pll_refclki             System                                |  10.000      8.307   |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|pll_refclki             serdes_sync_1|pll_refclki             |  10.000      4.079   |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|pll_refclki             serdes_sync_1|tx_pclk_inferred_clock  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|rxrefclk                System                                |  10.000      8.193   |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|rxrefclk                serdes_sync_1|rxrefclk                |  10.000      4.136   |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|tx_pclk_inferred_clock  serdes_sync_1|pll_refclki             |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|tx_pclk_inferred_clock  serdes_sync_1|tx_pclk_inferred_clock  |  10.000      5.789   |  No paths    -      |  No paths    -      |  No paths    -    
+===================================================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: serdes_sync_1|pll_refclki
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                   Starting                                                           Arrival          
+Instance                           Reference                     Type        Pin     Net              Time        Slack
+                                   Clock                                                                               
+-----------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[1]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[1]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[6]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[6]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[7]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[7]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[12]     serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[12]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[2]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[2]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[3]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[3]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[4]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[4]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[5]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[5]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[8]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[8]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[9]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[9]      0.907       4.684
+=======================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                   Starting                                                             Required          
+Instance                           Reference                     Type        Pin     Net                Time         Slack
+                                   Clock                                                                                  
+--------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[19]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[19]     9.946        4.079
+rsl_inst.genblk1\.plol_cnt[17]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[17]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[18]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[18]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[15]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[15]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[16]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[16]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[13]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[13]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[14]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[14]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[11]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[11]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[12]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[12]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[9]      serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[9]      9.946        4.383
+==========================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.867
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     4.079
+
+    Number of logic level(s):                15
+    Starting point:                          rsl_inst.genblk1\.plol_cnt[1] / Q
+    Ending point:                            rsl_inst.genblk1\.plol_cnt[19] / D
+    The start point is clocked by            serdes_sync_1|pll_refclki [rising] on pin CK
+    The end   point is clocked by            serdes_sync_1|pll_refclki [rising] on pin CK
+
+Instance / Net                                        Pin      Pin               Arrival     No. of    
+Name                                     Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[1]            FD1S3DX      Q        Out     0.907     0.907       -         
+plol_cnt[1]                              Net          -        -       -         -           2         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     Z        Out     0.606     1.513       -         
+un1_plol_cnt_tc_10                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     Z        Out     0.606     2.119       -         
+un1_plol_cnt_tc_14                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     Z        Out     0.762     2.881       -         
+un1_plol_cnt_tc                          Net          -        -       -         -           5         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     B        In      0.000     2.881       -         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     Z        Out     0.840     3.721       -         
+plol_cnt                                 Net          -        -       -         -           21        
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.721       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.621       -         
+plol_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.621       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.682       -         
+plol_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.682       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.743       -         
+plol_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.743       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.804       -         
+plol_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.804       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.865       -         
+plol_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.865       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.926       -         
+plol_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.926       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.987       -         
+plol_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.987       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.048       -         
+plol_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.048       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.109       -         
+plol_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.109       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        COUT     Out     0.061     5.170       -         
+plol_cnt_cry[18]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        CIN      In      0.000     5.170       -         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        S0       Out     0.698     5.867       -         
+plol_cnt_s[19]                           Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt[19]           FD1S3DX      D        In      0.000     5.867       -         
+=======================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: serdes_sync_1|rxrefclk
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                                     Starting                                                          Arrival          
+Instance                             Reference                  Type        Pin     Net                Time        Slack
+                                     Clock                                                                              
+------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[14]      serdes_sync_1|rxrefclk     FD1P3DX     Q       rlol1_cnt[14]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[15]      serdes_sync_1|rxrefclk     FD1P3DX     Q       rlol1_cnt[15]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[16]      serdes_sync_1|rxrefclk     FD1P3DX     Q       rlol1_cnt[16]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[17]      serdes_sync_1|rxrefclk     FD1P3DX     Q       rlol1_cnt[17]      0.907       4.136
+rsl_inst.genblk2\.rlols0_cnt[9]      serdes_sync_1|rxrefclk     FD1P3DX     Q       rlols0_cnt[9]      0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[11]     serdes_sync_1|rxrefclk     FD1P3DX     Q       rlols0_cnt[11]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[12]     serdes_sync_1|rxrefclk     FD1P3DX     Q       rlols0_cnt[12]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[13]     serdes_sync_1|rxrefclk     FD1P3DX     Q       rlols0_cnt[13]     0.907       4.170
+rsl_inst.genblk2\.rlol1_cnt[0]       serdes_sync_1|rxrefclk     FD1P3DX     Q       rlol1_cnt[0]       0.907       4.742
+rsl_inst.genblk2\.rlol1_cnt[1]       serdes_sync_1|rxrefclk     FD1P3DX     Q       rlol1_cnt[1]       0.907       4.742
+========================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                     Starting                                                            Required          
+Instance                             Reference                  Type        Pin     Net                  Time         Slack
+                                     Clock                                                                                 
+---------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[17]      serdes_sync_1|rxrefclk     FD1P3DX     D       rlol1_cnt_s[17]      9.946        4.136
+rsl_inst.genblk2\.rlol1_cnt[18]      serdes_sync_1|rxrefclk     FD1P3DX     D       rlol1_cnt_s[18]      9.946        4.136
+rsl_inst.genblk2\.rlols0_cnt[17]     serdes_sync_1|rxrefclk     FD1P3DX     D       rlols0_cnt_s[17]     9.946        4.170
+rsl_inst.genblk2\.rlol1_cnt[15]      serdes_sync_1|rxrefclk     FD1P3DX     D       rlol1_cnt_s[15]      9.946        4.197
+rsl_inst.genblk2\.rlol1_cnt[16]      serdes_sync_1|rxrefclk     FD1P3DX     D       rlol1_cnt_s[16]      9.946        4.197
+rsl_inst.genblk2\.rlols0_cnt[15]     serdes_sync_1|rxrefclk     FD1P3DX     D       rlols0_cnt_s[15]     9.946        4.231
+rsl_inst.genblk2\.rlols0_cnt[16]     serdes_sync_1|rxrefclk     FD1P3DX     D       rlols0_cnt_s[16]     9.946        4.231
+rsl_inst.genblk2\.rlol1_cnt[13]      serdes_sync_1|rxrefclk     FD1P3DX     D       rlol1_cnt_s[13]      9.946        4.258
+rsl_inst.genblk2\.rlol1_cnt[14]      serdes_sync_1|rxrefclk     FD1P3DX     D       rlol1_cnt_s[14]      9.946        4.258
+rsl_inst.genblk2\.rlols0_cnt[13]     serdes_sync_1|rxrefclk     FD1P3DX     D       rlols0_cnt_s[13]     9.946        4.292
+===========================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.809
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.136
+
+    Number of logic level(s):                14
+    Starting point:                          rsl_inst.genblk2\.rlol1_cnt[14] / Q
+    Ending point:                            rsl_inst.genblk2\.rlol1_cnt[18] / D
+    The start point is clocked by            serdes_sync_1|rxrefclk [rising] on pin CK
+    The end   point is clocked by            serdes_sync_1|rxrefclk [rising] on pin CK
+
+Instance / Net                                         Pin      Pin               Arrival     No. of    
+Name                                      Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[14]           FD1P3DX      Q        Out     0.907     0.907       -         
+rlol1_cnt[14]                             Net          -        -       -         -           2         
+rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     Z        Out     0.606     1.513       -         
+rlol1_cnt_tc_1_10                         Net          -        -       -         -           1         
+rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     Z        Out     0.606     2.119       -         
+rlol1_cnt_tc_1_14                         Net          -        -       -         -           1         
+rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     Z        Out     0.768     2.887       -         
+rlol1_cnt_tc_1                            Net          -        -       -         -           6         
+rsl_inst.genblk2\.rlos_db_p1_RNIS0OP      ORCALUT4     A        In      0.000     2.887       -         
+rsl_inst.genblk2\.rlos_db_p1_RNIS0OP      ORCALUT4     Z        Out     0.837     3.724       -         
+rlol1_cnt                                 Net          -        -       -         -           20        
+rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.724       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.624       -         
+rlol1_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.624       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.685       -         
+rlol1_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.685       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.746       -         
+rlol1_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.746       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.807       -         
+rlol1_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.807       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.868       -         
+rlol1_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.868       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.929       -         
+rlol1_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.929       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.990       -         
+rlol1_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.990       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.051       -         
+rlol1_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.051       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.112       -         
+rlol1_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.112       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        S1       Out     0.698     5.809       -         
+rlol1_cnt_s[18]                           Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt[18]           FD1P3DX      D        In      0.000     5.809       -         
+========================================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: serdes_sync_1|tx_pclk_inferred_clock
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                            Starting                                                                      Arrival          
+Instance                    Reference                                Type        Pin     Net              Time        Slack
+                            Clock                                                                                          
+---------------------------------------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1       serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p1     1.098       5.789
+sll_inst.ppul_sync_p2       serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p2     1.098       5.789
+sll_inst.pcount_diff[0]     serdes_sync_1|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_0      0.985       6.147
+sll_inst.pcount[0]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[0]        0.955       6.178
+sll_inst.pcount_diff[1]     serdes_sync_1|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_1      0.955       6.239
+sll_inst.pcount_diff[2]     serdes_sync_1|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_2      0.955       6.239
+sll_inst.pcount[1]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[1]        0.907       6.287
+sll_inst.pcount[2]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[2]        0.907       6.287
+sll_inst.pcount_diff[3]     serdes_sync_1|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_3      0.955       6.300
+sll_inst.pcount_diff[4]     serdes_sync_1|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_4      0.955       6.300
+===========================================================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                             Starting                                                                                     Required          
+Instance                     Reference                                Type        Pin     Net                             Time         Slack
+                             Clock                                                                                                          
+--------------------------------------------------------------------------------------------------------------------------------------------
+sll_inst.pcount[21]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[21]                    9.946        5.789
+sll_inst.pcount[19]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[19]                    9.946        5.850
+sll_inst.pcount[20]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[20]                    9.946        5.850
+sll_inst.pcount[17]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[17]                    9.946        5.911
+sll_inst.pcount[18]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[18]                    9.946        5.911
+sll_inst.pcount[15]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[15]                    9.946        5.972
+sll_inst.pcount[16]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[16]                    9.946        5.972
+sll_inst.pcount[13]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[13]                    9.946        6.033
+sll_inst.pcount[14]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[14]                    9.946        6.033
+sll_inst.pcount_diff[21]     serdes_sync_1|tx_pclk_inferred_clock     FD1P3DX     D       un1_pcount_diff_1_s_21_0_S0     9.946        6.034
+============================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      4.157
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 5.789
+
+    Number of logic level(s):                13
+    Starting point:                          sll_inst.ppul_sync_p1 / Q
+    Ending point:                            sll_inst.pcount[21] / D
+    The start point is clocked by            serdes_sync_1|tx_pclk_inferred_clock [rising] on pin CK
+    The end   point is clocked by            serdes_sync_1|tx_pclk_inferred_clock [rising] on pin CK
+
+Instance / Net                             Pin      Pin               Arrival     No. of    
+Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1         FD1S3DX      Q        Out     1.098     1.098       -         
+ppul_sync_p1                  Net          -        -       -         -           25        
+sll_inst.pcount10_0_o3        ORCALUT4     A        In      0.000     1.098       -         
+sll_inst.pcount10_0_o3        ORCALUT4     Z        Out     0.851     1.950       -         
+N_8                           Net          -        -       -         -           25        
+sll_inst.pcount_cry_0[0]      CCU2C        A1       In      0.000     1.950       -         
+sll_inst.pcount_cry_0[0]      CCU2C        COUT     Out     0.900     2.850       -         
+pcount_cry[0]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[1]      CCU2C        CIN      In      0.000     2.850       -         
+sll_inst.pcount_cry_0[1]      CCU2C        COUT     Out     0.061     2.911       -         
+pcount_cry[2]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[3]      CCU2C        CIN      In      0.000     2.911       -         
+sll_inst.pcount_cry_0[3]      CCU2C        COUT     Out     0.061     2.972       -         
+pcount_cry[4]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[5]      CCU2C        CIN      In      0.000     2.972       -         
+sll_inst.pcount_cry_0[5]      CCU2C        COUT     Out     0.061     3.033       -         
+pcount_cry[6]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[7]      CCU2C        CIN      In      0.000     3.033       -         
+sll_inst.pcount_cry_0[7]      CCU2C        COUT     Out     0.061     3.094       -         
+pcount_cry[8]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[9]      CCU2C        CIN      In      0.000     3.094       -         
+sll_inst.pcount_cry_0[9]      CCU2C        COUT     Out     0.061     3.155       -         
+pcount_cry[10]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[11]     CCU2C        CIN      In      0.000     3.155       -         
+sll_inst.pcount_cry_0[11]     CCU2C        COUT     Out     0.061     3.216       -         
+pcount_cry[12]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[13]     CCU2C        CIN      In      0.000     3.216       -         
+sll_inst.pcount_cry_0[13]     CCU2C        COUT     Out     0.061     3.277       -         
+pcount_cry[14]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[15]     CCU2C        CIN      In      0.000     3.277       -         
+sll_inst.pcount_cry_0[15]     CCU2C        COUT     Out     0.061     3.338       -         
+pcount_cry[16]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[17]     CCU2C        CIN      In      0.000     3.338       -         
+sll_inst.pcount_cry_0[17]     CCU2C        COUT     Out     0.061     3.399       -         
+pcount_cry[18]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[19]     CCU2C        CIN      In      0.000     3.399       -         
+sll_inst.pcount_cry_0[19]     CCU2C        COUT     Out     0.061     3.460       -         
+pcount_cry[20]                Net          -        -       -         -           1         
+sll_inst.pcount_s_0[21]       CCU2C        CIN      In      0.000     3.460       -         
+sll_inst.pcount_s_0[21]       CCU2C        S0       Out     0.698     4.157       -         
+pcount_s[21]                  Net          -        -       -         -           1         
+sll_inst.pcount[21]           FD1S3DX      D        In      0.000     4.157       -         
+============================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+              Starting                                                   Arrival           
+Instance      Reference     Type     Pin                Net              Time        Slack 
+              Clock                                                                        
+-------------------------------------------------------------------------------------------
+DCU0_inst     System        DCUA     CH0_FFS_RLOL       rx_cdr_lol_s     0.000       8.810 
+DCU0_inst     System        DCUA     CH0_FFS_RLOS       rx_los_low_s     0.000       8.810 
+DCU0_inst     System        DCUA     CH0_FF_RX_PCLK     rx_pclk          0.000       10.000
+===========================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                                                       Starting                                                                       Required           
+Instance                                               Reference     Type        Pin                Net                               Time         Slack 
+                                                       Clock                                                                                             
+---------------------------------------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     SP                 un2_rdo_serdes_rst_dual_c_2_i     9.806        8.810 
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     D                  un2_rdo_serdes_rst_dual_c_1       9.946        9.556 
+rsl_inst.genblk2\.rlol_p1                              System        FD1S3DX     D                  rx_cdr_lol_s                      9.946        9.946 
+rsl_inst.genblk2\.rlos_p1                              System        FD1S3DX     D                  rx_los_low_s                      9.946        9.946 
+DCU0_inst                                              System        DCUA        CH0_FF_RXI_CLK     rx_pclk                           10.000       10.000
+=========================================================================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.194
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.806
+
+    - Propagation time:                      0.996
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 8.810
+
+    Number of logic level(s):                2
+    Starting point:                          DCU0_inst / CH0_FFS_RLOL
+    Ending point:                            rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            serdes_sync_1|rxrefclk [rising] on pin CK
+
+Instance / Net                                                          Pin              Pin               Arrival     No. of    
+Name                                                       Type         Name             Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------------------------------------------------
+DCU0_inst                                                  DCUA         CH0_FFS_RLOL     Out     0.000     0.000       -         
+rx_cdr_lol_s                                               Net          -                -       -         -           4         
+rsl_inst.un2_rdo_serdes_rst_dual_c_2_0                     ORCALUT4     B                In      0.000     0.000       -         
+rsl_inst.un2_rdo_serdes_rst_dual_c_2_0                     ORCALUT4     Z                Out     0.606     0.606       -         
+un2_rdo_serdes_rst_dual_c_2_0                              Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO[0]     ORCALUT4     B                In      0.000     0.606       -         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO[0]     ORCALUT4     Z                Out     0.390     0.996       -         
+un2_rdo_serdes_rst_dual_c_2_i                              Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]         FD1P3DX      SP               In      0.000     0.996       -         
+=================================================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lfe5um_25f-6
+
+Register bits: 220 of 24288 (1%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+CCU2C:          113
+DCUA:           1
+FD1P3BX:        20
+FD1P3DX:        92
+FD1S3BX:        12
+FD1S3DX:        96
+GSR:            1
+INV:            3
+ORCALUT4:       150
+PFUMX:          2
+PUR:            1
+VHI:            6
+VLO:            6
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 152MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Fri May 10 10:23:38 2019
+
+###########################################################]

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_fpga_mapper.srr.db b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_fpga_mapper.srr.db
new file mode 100644 (file)
index 0000000..f91149b
Binary files /dev/null and b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_fpga_mapper.srr.db differ

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_fpga_mapper.szr b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_fpga_mapper.szr
new file mode 100644 (file)
index 0000000..d0b1a44
Binary files /dev/null and b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_fpga_mapper.szr differ

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_fpga_mapper.xck b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_fpga_mapper.xck
new file mode 100644 (file)
index 0000000..d68c9cb
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_fpga_mapper.xck
@@ -0,0 +1,3 @@
+CKID0001:@|S:pll_refclki@|E:rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001 
+CKID0002:@|S:rxrefclk@|E:rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]@|F:@syn_sample_clock_path==CKID0002@|M:ClockId0002 
+CKID0003:@|S:DCU0_inst@|E:sll_inst.pcount_diff[21]@|F:@syn_sample_clock_path==CKID0003@|M:ClockId0003 

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_multi_srs_gen.srr b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_multi_srs_gen.srr
new file mode 100644 (file)
index 0000000..8c7faa5
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_multi_srs_gen.srr
@@ -0,0 +1,12 @@
+Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017
+@N|Running in 64-bit mode
+File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 10:23:33 2019
+
+###########################################################]

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_multi_srs_gen.srr.db b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_multi_srs_gen.srr.db
new file mode 100644 (file)
index 0000000..029fa7a
Binary files /dev/null and b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_multi_srs_gen.srr.db differ

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_premap.srr b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_premap.srr
new file mode 100644 (file)
index 0000000..bee72ed
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_premap.srr
@@ -0,0 +1,84 @@
+# Fri May 10 10:23:33 2019
+
+Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc
+@L: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_scck.rpt 
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_scck.rpt" file 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 115MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 117MB)
+
+@N: BN362 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1408:0:1408:5|Removing sequential instance pcpri_mod_ch (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1244:27:1244:40|Removing instance div2_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1252:27:1252:41|Removing instance div11_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1236:27:1236:40|Removing instance gear_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1268:27:1268:44|Removing instance pcie_mod_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances.
+@N: BN115 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1260:27:1260:44|Removing instance cpri_mod_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances.
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist serdes_sync_1
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
+
+
+
+Clock Summary
+******************
+
+          Start                                    Requested     Requested     Clock        Clock                   Clock
+Level     Clock                                    Frequency     Period        Type         Group                   Load 
+-------------------------------------------------------------------------------------------------------------------------
+0 -       System                                   100.0 MHz     10.000        system       system_clkgroup         0    
+                                                                                                                         
+0 -       serdes_sync_1|pll_refclki                100.0 MHz     10.000        inferred     Inferred_clkgroup_0     92   
+                                                                                                                         
+0 -       serdes_sync_1|rxrefclk                   100.0 MHz     10.000        inferred     Inferred_clkgroup_1     77   
+                                                                                                                         
+0 -       serdes_sync_1|tx_pclk_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_2     53   
+=========================================================================================================================
+
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Found inferred clock serdes_sync_1|pll_refclki which controls 92 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Found inferred clock serdes_sync_1|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+@W: MT529 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1988:0:1988:5|Found inferred clock serdes_sync_1|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 145MB)
+
+Encoding state machine sll_state[2:0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   11 -> 10
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 59MB peak: 145MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Fri May 10 10:23:34 2019
+
+###########################################################]

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_premap.srr.db b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_premap.srr.db
new file mode 100644 (file)
index 0000000..1df1332
Binary files /dev/null and b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_premap.srr.db differ

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_premap.szr b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_premap.szr
new file mode 100644 (file)
index 0000000..d9730c2
Binary files /dev/null and b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/serdes_sync_1_premap.szr differ

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/syntax_constraint_check.rpt.rptmap b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/syntax_constraint_check.rpt.rptmap
new file mode 100644 (file)
index 0000000..6c6e0b6
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synlog/syntax_constraint_check.rpt.rptmap
@@ -0,0 +1 @@
+./serdes_sync_1_scck.rpt,syntax_constraint_check.rpt,Syntax Constraint Check Report

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/closed.png b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/closed.png
new file mode 100644 (file)
index 0000000..0d78634
Binary files /dev/null and b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/closed.png differ

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/open.png b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/open.png
new file mode 100644 (file)
index 0000000..a227005
Binary files /dev/null and b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/open.png differ

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/run_option.xml b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/run_option.xml
new file mode 100644 (file)
index 0000000..9bdba19
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/run_option.xml
@@ -0,0 +1,24 @@
+<?xml version="1.0" encoding="utf-8"?> 
+<!-- 
+  Synopsys, Inc.
+  Version M-2017.03L-SP1-1
+  Project file /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/run_option.xml
+  Written on Fri May 10 10:23:30 2019
+
+
+--> 
+<project_attribute_list name="Project Settings"> 
+     <option name="project_name" display_name="Project Name">serdes_sync_1</option>
+     <option name="device_name" display_name="Device Name">syn_results: Lattice ECP5UM : LFE5UM_25F</option>
+     <option name="impl_name" display_name="Implementation Name">syn_results</option>
+     <option name="top_module" display_name="Top Module">serdes_sync_1</option>
+     <option name="pipe" display_name="Pipelining">0</option>
+     <option name="retiming" display_name="Retiming">0</option>
+     <option name="resource_sharing" display_name="Resource Sharing">1</option>
+     <option name="maxfan" display_name="Fanout Guide">50</option>
+     <option name="disable_io_insertion" display_name="Disable I/O Insertion">1</option>
+     <option name="no_sequential_opt" display_name="Disable Sequential Optimizations">0</option>
+     <option name="fix_gated_and_generated_clocks" display_name="Clock Conversion">1</option>
+     <option name="symbolic_fsm_compiler" display_name="FSM Compiler">1</option>
+</project_attribute_list>
+

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1.plg b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1.plg
new file mode 100644 (file)
index 0000000..a777b88
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1.plg
@@ -0,0 +1,28 @@
+@P:  Worst Slack : 4.079
+@P:  serdes_sync_1|pll_refclki - Estimated Frequency : 168.9 MHz
+@P:  serdes_sync_1|pll_refclki - Requested Frequency : 100.0 MHz
+@P:  serdes_sync_1|pll_refclki - Estimated Period : 5.921
+@P:  serdes_sync_1|pll_refclki - Requested Period : 10.000
+@P:  serdes_sync_1|pll_refclki - Slack : 4.079
+@P:  serdes_sync_1|rxrefclk - Estimated Frequency : 170.5 MHz
+@P:  serdes_sync_1|rxrefclk - Requested Frequency : 100.0 MHz
+@P:  serdes_sync_1|rxrefclk - Estimated Period : 5.864
+@P:  serdes_sync_1|rxrefclk - Requested Period : 10.000
+@P:  serdes_sync_1|rxrefclk - Slack : 4.136
+@P:  serdes_sync_1|tx_pclk_inferred_clock - Estimated Frequency : 237.5 MHz
+@P:  serdes_sync_1|tx_pclk_inferred_clock - Requested Frequency : 100.0 MHz
+@P:  serdes_sync_1|tx_pclk_inferred_clock - Estimated Period : 4.211
+@P:  serdes_sync_1|tx_pclk_inferred_clock - Requested Period : 10.000
+@P:  serdes_sync_1|tx_pclk_inferred_clock - Slack : 5.789
+@P:  System - Estimated Frequency : 840.7 MHz
+@P:  System - Requested Frequency : 100.0 MHz
+@P:  System - Estimated Period : 1.190
+@P:  System - Requested Period : 10.000
+@P:  System - Slack : 8.810
+@P:  Total Area : 153.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  Total Area : 0.0
+@P:  CPU Time : 0h:00m:03s

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_srr.htm b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_srr.htm
new file mode 100644 (file)
index 0000000..e476d77
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_srr.htm
@@ -0,0 +1,1167 @@
+<html><body><samp><pre>
+<!@TC:1557476610>
+#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug  4 2017
+#install: /home/soft/lattice/diamond/3.10_x64/synpbase
+#OS: Linux 
+#Hostname: lxhadeb07
+
+# Fri May 10 10:23:30 2019
+
+#Implementation: syn_results
+
+<a name=compilerReport1></a>Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1557476612> | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+<a name=compilerReport2></a>Synopsys VHDL Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1557476612> | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1557476612> | Setting time resolution to ps
+@N: : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd:30:7:30:20:@N::@XP_MSG">serdes_sync_1.vhd(30)</a><!@TM:1557476612> | Top entity is set to serdes_sync_1.
+VHDL syntax check successful!
+File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd changed - recompiling
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Fri May 10 10:23:30 2019
+
+###########################################################]
+<a name=compilerReport3></a>Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1557476612> | Running in 64-bit mode 
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v" (library work)
+Verilog syntax check successful!
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+
+Process completed successfully.
+# Fri May 10 10:23:31 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1557476612> | Setting time resolution to ps
+@N: : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd:30:7:30:20:@N::@XP_MSG">serdes_sync_1.vhd(30)</a><!@TM:1557476612> | Top entity is set to serdes_sync_1.
+File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd changed - recompiling
+File /home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd changed - recompiling
+VHDL syntax check successful!
+File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd changed - recompiling
+@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd:30:7:30:20:@N:CD630:@XP_MSG">serdes_sync_1.vhd(30)</a><!@TM:1557476612> | Synthesizing work.serdes_sync_1.v1.
+Post processing for work.serdes_sync_1.v1
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB)
+
+
+Process completed successfully.
+# Fri May 10 10:23:31 2019
+
+###########################################################]
+Running on host :lxhadeb07
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v" (library work)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
+@I::"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
+@I::"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v" (library work)
+Verilog syntax check successful!
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1968:7:1968:11:@N:CG364:@XP_MSG">serdes_sync_1_softlogic.v(1968)</a><!@TM:1557476612> | Synthesizing module sync in library work.
+
+       PDATA_RST_VAL=32'b00000000000000000000000000000000
+   Generated name = sync_0s
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1051:7:1051:28:@N:CG364:@XP_MSG">serdes_sync_1_softlogic.v(1051)</a><!@TM:1557476612> | Synthesizing module serdes_sync_1sll_core in library work.
+
+       PPROTOCOL=48'b010001110011100001000010001100010011000001000010
+       PLOL_SETTING=32'b00000000000000000000000000000001
+       PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100
+       PPCIE_MAX_RATE=24'b001100100010111000110101
+       PDIFF_VAL_LOCK=32'b00000000000000000000000000100111
+       PDIFF_VAL_UNLOCK=32'b00000000000000000000000100000110
+       PPCLK_TC=32'b00000000000000100000000000000000
+       PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000
+       PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000
+       PPCLK_DIV11_TC=32'b00000000000000000000000000000000
+       LPLL_LOSS_ST=2'b00
+       LPLL_PRELOSS_ST=2'b01
+       LPLL_PRELOCK_ST=2'b10
+       LPLL_LOCK_ST=2'b11
+       LRCLK_TC=16'b1111111111111111
+       LRCLK_TC_PUL_WIDTH=16'b0000000000110010
+       LHB_WAIT_CNT=8'b11111111
+       LPCLK_TC_0=32'b00000000000000001000000000000000
+       LPCLK_TC_1=32'b00000000000000010000000000000000
+       LPCLK_TC_2=32'b00000000000000100000000000000000
+       LPCLK_TC_3=32'b00000000000000101000000000000000
+       LPCLK_TC_4=32'b00000000000000010000000000000000
+       LPDIFF_LOCK_00=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_10=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_20=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_30=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_40=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_01=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_11=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_21=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_31=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_41=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_02=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_12=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_22=32'b00000000000000000000000011000100
+       LPDIFF_LOCK_32=32'b00000000000000000000000011110101
+       LPDIFF_LOCK_42=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_03=32'b00000000000000000000000010000011
+       LPDIFF_LOCK_13=32'b00000000000000000000000100000110
+       LPDIFF_LOCK_23=32'b00000000000000000000001000001100
+       LPDIFF_LOCK_33=32'b00000000000000000000001010001111
+       LPDIFF_LOCK_43=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011
+       LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110
+       LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010
+       LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001
+       LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111
+       LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000
+       LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000
+       LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000
+       LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100
+       LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001
+       LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010
+       LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111
+       LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001
+   Generated name = serdes_sync_1sll_core_Z1_layer1
+@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1287:54:1287:60:@N:CG179:@XP_MSG">serdes_sync_1_softlogic.v(1287)</a><!@TM:1557476612> | Removing redundant assignment.
+@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1293:52:1293:56:@N:CG179:@XP_MSG">serdes_sync_1_softlogic.v(1293)</a><!@TM:1557476612> | Removing redundant assignment.
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1350:0:1350:6:@W:CL169:@XP_MSG">serdes_sync_1_softlogic.v(1350)</a><!@TM:1557476612> | Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 3 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 6 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+<font color=#A52A2A>@W:<a href="@W:CL208:@XP_HELP">CL208</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL208:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.</font>
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:92:7:92:28:@N:CG364:@XP_MSG">serdes_sync_1_softlogic.v(92)</a><!@TM:1557476612> | Synthesizing module serdes_sync_1rsl_core in library work.
+
+       pnum_channels=32'b00000000000000000000000000000001
+       pprotocol=48'b010001110011100001000010001100010011000001000010
+       pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
+       pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_tx_rdy=32'b00000000000000000000101110111000
+       pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_rx_rdy=32'b00000000000000000000101110111000
+       wa_num_cycles=32'b00000000000000000000010000000000
+       dac_num_cycles=32'b00000000000000000000000000000011
+       lreset_pwidth=32'b00000000000000000000000000000011
+       lwait_b4_trst=32'b00000000000010111110101111000010
+       lwait_b4_trst_s=32'b00000000000000000000001100001101
+       lplol_cnt_width=32'b00000000000000000000000000010100
+       lwait_after_plol0=32'b00000000000000000000000000000100
+       lwait_b4_rrst=32'b00000000000000101100000000000000
+       lrrst_wait_width=32'b00000000000000000000000000010100
+       lwait_after_rrst=32'b00000000000011000011010100000000
+       lwait_b4_rrst_s=32'b00000000000000000000000111001100
+       lrlol_cnt_width=32'b00000000000000000000000000010011
+       lwait_after_lols=32'b00000000000000001100010000000000
+       lwait_after_lols_s=32'b00000000000000000000000010010110
+       llols_cnt_width=32'b00000000000000000000000000010010
+       lrdb_max=32'b00000000000000000000000000001111
+       ltxr_wait_width=32'b00000000000000000000000000001100
+       lrxr_wait_width=32'b00000000000000000000000000001100
+   Generated name = serdes_sync_1rsl_core_Z2_layer1
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:326:33:326:41:@W:CG133:@XP_MSG">serdes_sync_1_softlogic.v(326)</a><!@TM:1557476612> | Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:327:33:327:44:@W:CG360:@XP_MSG">serdes_sync_1_softlogic.v(327)</a><!@TM:1557476612> | Removing wire rrst_cnt_tc, as there is no assignment to it.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:328:33:328:42:@W:CG133:@XP_MSG">serdes_sync_1_softlogic.v(328)</a><!@TM:1557476612> | Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:341:33:341:40:@W:CG133:@XP_MSG">serdes_sync_1_softlogic.v(341)</a><!@TM:1557476612> | Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:342:33:342:40:@W:CG133:@XP_MSG">serdes_sync_1_softlogic.v(342)</a><!@TM:1557476612> | Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:343:33:343:43:@W:CG360:@XP_MSG">serdes_sync_1_softlogic.v(343)</a><!@TM:1557476612> | Removing wire rxp_cnt_tc, as there is no assignment to it.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:346:33:346:43:@W:CG133:@XP_MSG">serdes_sync_1_softlogic.v(346)</a><!@TM:1557476612> | Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:347:33:347:46:@W:CG360:@XP_MSG">serdes_sync_1_softlogic.v(347)</a><!@TM:1557476612> | Removing wire rlolsz_cnt_tc, as there is no assignment to it.</font>
+<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:350:33:350:44:@W:CG360:@XP_MSG">serdes_sync_1_softlogic.v(350)</a><!@TM:1557476612> | Removing wire rxp_cnt2_tc, as there is no assignment to it.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:351:33:351:48:@W:CG133:@XP_MSG">serdes_sync_1_softlogic.v(351)</a><!@TM:1557476612> | Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG133:@XP_HELP">CG133</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:352:33:352:44:@W:CG133:@XP_MSG">serdes_sync_1_softlogic.v(352)</a><!@TM:1557476612> | Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.</font>
+<font color=#A52A2A>@W:<a href="@W:CG360:@XP_HELP">CG360</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:353:33:353:47:@W:CG360:@XP_MSG">serdes_sync_1_softlogic.v(353)</a><!@TM:1557476612> | Removing wire data_loop_b_tc, as there is no assignment to it.</font>
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:806:3:806:9:@W:CL169:@XP_MSG">serdes_sync_1_softlogic.v(806)</a><!@TM:1557476612> | Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.</font>
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:567:3:567:9:@W:CL169:@XP_MSG">serdes_sync_1_softlogic.v(567)</a><!@TM:1557476612> | Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.</font>
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:567:3:567:9:@W:CL169:@XP_MSG">serdes_sync_1_softlogic.v(567)</a><!@TM:1557476612> | Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.</font>
+<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:694:3:694:9:@W:CL190:@XP_MSG">serdes_sync_1_softlogic.v(694)</a><!@TM:1557476612> | Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
+<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:461:3:461:9:@W:CL190:@XP_MSG">serdes_sync_1_softlogic.v(461)</a><!@TM:1557476612> | Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
+<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:422:3:422:9:@W:CL190:@XP_MSG">serdes_sync_1_softlogic.v(422)</a><!@TM:1557476612> | Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
+<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:422:3:422:9:@W:CL260:@XP_MSG">serdes_sync_1_softlogic.v(422)</a><!@TM:1557476612> | Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
+<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:461:3:461:9:@W:CL260:@XP_MSG">serdes_sync_1_softlogic.v(461)</a><!@TM:1557476612> | Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
+<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:694:3:694:9:@W:CL260:@XP_MSG">serdes_sync_1_softlogic.v(694)</a><!@TM:1557476612> | Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
+<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:200:33:200:49:@W:CL246:@XP_MSG">serdes_sync_1_softlogic.v(200)</a><!@TM:1557476612> | Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.</font>
+<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:204:33:204:52:@W:CL246:@XP_MSG">serdes_sync_1_softlogic.v(204)</a><!@TM:1557476612> | Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.</font>
+<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:205:33:205:49:@W:CL246:@XP_MSG">serdes_sync_1_softlogic.v(205)</a><!@TM:1557476612> | Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.</font>
+<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:206:33:206:49:@W:CL246:@XP_MSG">serdes_sync_1_softlogic.v(206)</a><!@TM:1557476612> | Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.</font>
+<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:207:33:207:49:@W:CL246:@XP_MSG">serdes_sync_1_softlogic.v(207)</a><!@TM:1557476612> | Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.</font>
+<font color=#A52A2A>@W:<a href="@W:CL279:@XP_HELP">CL279</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL279:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | Pruning register bits 8 to 7 of genblk5.rdiff_comp_unlock[8:6]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.</font>
+<font color=#A52A2A>@W:<a href="@W:CL279:@XP_HELP">CL279</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL279:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.</font>
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL169:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | Pruning unused register genblk5.rdiff_comp_unlock[6]. Make sure that there are no unused intermediate registers.</font>
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1739:0:1739:6:@W:CL169:@XP_MSG">serdes_sync_1_softlogic.v(1739)</a><!@TM:1557476612> | Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers.</font>
+@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1801:0:1801:6:@N:CL201:@XP_MSG">serdes_sync_1_softlogic.v(1801)</a><!@TM:1557476612> | Trying to extract state machine for register sll_state.
+Extracted state machine for register sll_state
+State machine has 3 reachable states with original encodings of:
+   00
+   01
+   11
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 81MB)
+
+
+Process completed successfully.
+# Fri May 10 10:23:32 2019
+
+###########################################################]
+<a name=compilerReport4></a>Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1557476612> | Running in 64-bit mode 
+File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer0.srs changed - recompiling
+File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.srs changed - recompiling
+
+=======================================================================================
+For a summary of linker messages for components that did not bind, please see log file:
+Linked File: <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.linkerlog:@XP_FILE">serdes_sync_1_comp.linkerlog</a>
+=======================================================================================
+
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 10:23:32 2019
+
+###########################################################]
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 10:23:32 2019
+
+###########################################################]
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1557476610>
+<a name=compilerReport5></a>Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug  4 2017</a>
+@N: : <!@TM:1557476613> | Running in 64-bit mode 
+File /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Fri May 10 10:23:33 2019
+
+###########################################################]
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1557476610>
+# Fri May 10 10:23:33 2019
+
+<a name=mapperReport6></a>Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35</a>
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+Reading constraint file: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc
+Linked File: <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_scck.rpt:@XP_FILE">serdes_sync_1_scck.rpt</a>
+Printing clock  summary report in "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_scck.rpt" file 
+@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1557476614> | Running in 64-bit mode. 
+@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1557476614> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 115MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 117MB)
+
+@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1408:0:1408:6:@N:BN362:@XP_MSG">serdes_sync_1_softlogic.v(1408)</a><!@TM:1557476614> | Removing sequential instance pcpri_mod_ch (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
+@N:<a href="@N:BN115:@XP_HELP">BN115</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1244:27:1244:41:@N:BN115:@XP_MSG">serdes_sync_1_softlogic.v(1244)</a><!@TM:1557476614> | Removing instance div2_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_3(verilog) because it does not drive other instances.
+@N:<a href="@N:BN115:@XP_HELP">BN115</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1252:27:1252:42:@N:BN115:@XP_MSG">serdes_sync_1_softlogic.v(1252)</a><!@TM:1557476614> | Removing instance div11_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_2(verilog) because it does not drive other instances.
+@N:<a href="@N:BN115:@XP_HELP">BN115</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1236:27:1236:41:@N:BN115:@XP_MSG">serdes_sync_1_softlogic.v(1236)</a><!@TM:1557476614> | Removing instance gear_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_4(verilog) because it does not drive other instances.
+@N:<a href="@N:BN115:@XP_HELP">BN115</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1268:27:1268:45:@N:BN115:@XP_MSG">serdes_sync_1_softlogic.v(1268)</a><!@TM:1557476614> | Removing instance pcie_mod_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_0(verilog) because it does not drive other instances.
+@N:<a href="@N:BN115:@XP_HELP">BN115</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1260:27:1260:45:@N:BN115:@XP_MSG">serdes_sync_1_softlogic.v(1260)</a><!@TM:1557476614> | Removing instance cpri_mod_sync_inst (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:work.sync_0s_1(verilog) because it does not drive other instances.
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:     0
+syn_allowed_resources : blockrams=56  set on top level netlist serdes_sync_1
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
+
+
+
+<a name=mapperReport7></a>Clock Summary</a>
+******************
+
+          Start                                    Requested     Requested     Clock        Clock                   Clock
+Level     Clock                                    Frequency     Period        Type         Group                   Load 
+-------------------------------------------------------------------------------------------------------------------------
+0 -       System                                   100.0 MHz     10.000        system       system_clkgroup         0    
+                                                                                                                         
+0 -       serdes_sync_1|pll_refclki                100.0 MHz     10.000        inferred     Inferred_clkgroup_0     92   
+                                                                                                                         
+0 -       serdes_sync_1|rxrefclk                   100.0 MHz     10.000        inferred     Inferred_clkgroup_1     77   
+                                                                                                                         
+0 -       serdes_sync_1|tx_pclk_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_2     53   
+=========================================================================================================================
+
+<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1988:0:1988:6:@W:MT529:@XP_MSG">serdes_sync_1_softlogic.v(1988)</a><!@TM:1557476614> | Found inferred clock serdes_sync_1|pll_refclki which controls 92 sequential elements including sll_inst.phb_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
+<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:567:3:567:9:@W:MT529:@XP_MSG">serdes_sync_1_softlogic.v(567)</a><!@TM:1557476614> | Found inferred clock serdes_sync_1|rxrefclk which controls 77 sequential elements including rsl_inst.genblk2\.rlos_db_p1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
+<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1988:0:1988:6:@W:MT529:@XP_MSG">serdes_sync_1_softlogic.v(1988)</a><!@TM:1557476614> | Found inferred clock serdes_sync_1|tx_pclk_inferred_clock which controls 53 sequential elements including sll_inst.rtc_sync_inst.data_p2. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
+
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 145MB)
+
+Encoding state machine sll_state[2:0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   11 -> 10
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
+
+None
+None
+
+Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 59MB peak: 145MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Fri May 10 10:23:34 2019
+
+###########################################################]
+
+</pre></samp></body></html>
+<html><body><samp><pre>
+<!@TC:1557476610>
+# Fri May 10 10:23:34 2019
+
+<a name=mapperReport8></a>Synopsys Lattice Technology Mapper, Version maplat, Build 1796R, Built Aug  4 2017 09:36:35</a>
+Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
+Product Version M-2017.03L-SP1-1
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
+
+@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1557476618> | Running in 64-bit mode. 
+@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1557476618> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 113MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 144MB)
+
+
+Available hyper_sources - for debug and ip models
+       None Found
+
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+Encoding state machine sll_state[2:0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog))
+original code -> new code
+   00 -> 00
+   01 -> 01
+   11 -> 10
+@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1350:0:1350:6:@N:MO231:@XP_MSG">serdes_sync_1_softlogic.v(1350)</a><!@TM:1557476618> | Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance rhb_wait_cnt[7:0] 
+@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1304:0:1304:6:@N:MO231:@XP_MSG">serdes_sync_1_softlogic.v(1304)</a><!@TM:1557476618> | Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance rcount[15:0] 
+@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1759:0:1759:6:@N:MO231:@XP_MSG">serdes_sync_1_softlogic.v(1759)</a><!@TM:1557476618> | Found counter in view:work.serdes_sync_1sll_core_Z1_layer1(verilog) instance pcount[21:0] 
+@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1801:0:1801:6:@N:BN362:@XP_MSG">serdes_sync_1_softlogic.v(1801)</a><!@TM:1557476618> | Removing sequential instance sll_state[0] (in view: work.serdes_sync_1sll_core_Z1_layer1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
+@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:412:3:412:9:@N:MO231:@XP_MSG">serdes_sync_1_softlogic.v(412)</a><!@TM:1557476618> | Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk1\.plol_cnt[19:0] 
+@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:909:3:909:9:@N:MO231:@XP_MSG">serdes_sync_1_softlogic.v(909)</a><!@TM:1557476618> | Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.genblk3\.rxr_wt_cnt[11:0] 
+@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:527:3:527:9:@N:MO231:@XP_MSG">serdes_sync_1_softlogic.v(527)</a><!@TM:1557476618> | Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk1\.genblk2\.txr_wt_cnt[11:0] 
+@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:778:3:778:9:@N:MO231:@XP_MSG">serdes_sync_1_softlogic.v(778)</a><!@TM:1557476618> | Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.rlols0_cnt[17:0] 
+@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:680:3:680:9:@N:MO231:@XP_MSG">serdes_sync_1_softlogic.v(680)</a><!@TM:1557476618> | Found counter in view:work.serdes_sync_1rsl_core_Z2_layer1(verilog) instance genblk2\.rlol1_cnt[18:0] 
+
+Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB)
+
+
+Starting gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 145MB peak: 146MB)
+
+@N:<a href="@N:FX1019:@XP_HELP">FX1019</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1988:0:1988:6:@N:FX1019:@XP_MSG">serdes_sync_1_softlogic.v(1988)</a><!@TM:1557476618> | Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+@N:<a href="@N:FX1019:@XP_HELP">FX1019</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1988:0:1988:6:@N:FX1019:@XP_MSG">serdes_sync_1_softlogic.v(1988)</a><!@TM:1557476618> | Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+@N:<a href="@N:FX1019:@XP_HELP">FX1019</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1988:0:1988:6:@N:FX1019:@XP_MSG">serdes_sync_1_softlogic.v(1988)</a><!@TM:1557476618> | Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+
+Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
+
+Pass            CPU time               Worst Slack             Luts / Registers
+------------------------------------------------------------
+   1           0h:00m:01s                   5.35ns              151 /       220
+@N:<a href="@N:FX1019:@XP_HELP">FX1019</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1988:0:1988:6:@N:FX1019:@XP_MSG">serdes_sync_1_softlogic.v(1988)</a><!@TM:1557476618> | Adding ASYNC_REG property on synchronizing instance sll_inst.phb_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+@N:<a href="@N:FX1019:@XP_HELP">FX1019</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1988:0:1988:6:@N:FX1019:@XP_MSG">serdes_sync_1_softlogic.v(1988)</a><!@TM:1557476618> | Adding ASYNC_REG property on synchronizing instance sll_inst.rtc_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+@N:<a href="@N:FX1019:@XP_HELP">FX1019</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v:1988:0:1988:6:@N:FX1019:@XP_MSG">serdes_sync_1_softlogic.v(1988)</a><!@TM:1557476618> | Adding ASYNC_REG property on synchronizing instance sll_inst.pdiff_sync_inst.data_p1 (in view: work.serdes_sync_1(v1)).
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
+
+@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1557476618> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
+
+
+
+@S |Clock Optimization Summary
+
+
+<a name=clockReport9></a>#### START OF CLOCK OPTIMIZATION REPORT #####[</a>
+
+3 non-gated/non-generated clock tree(s) driving 220 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+============================================= Non-Gated/Non-Generated Clocks =============================================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance                                   
+--------------------------------------------------------------------------------------------------------------------------
+<a href="@|S:pll_refclki@|E:rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001  @XP_NAMES_BY_PROP">ClockId0001 </a>       pll_refclki         port                   90         rsl_inst.genblk1\.genblk2\.mfor\[0\]\.txpr_appd[0]
+<a href="@|S:rxrefclk@|E:rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]@|F:@syn_sample_clock_path==CKID0002@|M:ClockId0002  @XP_NAMES_BY_PROP">ClockId0002 </a>       rxrefclk            port                   77         rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]
+<a href="@|S:DCU0_inst@|E:sll_inst.pcount_diff[21]@|F:@syn_sample_clock_path==CKID0003@|M:ClockId0003  @XP_NAMES_BY_PROP">ClockId0003 </a>       DCU0_inst           DCUA                   53         sll_inst.pcount_diff[21]                          
+==========================================================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######]
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 111MB peak: 148MB)
+
+Writing Analyst data base /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 148MB)
+
+Writing EDIF Netlist and constraint files
+@N:<a href="@N:FX1056:@XP_HELP">FX1056</a> : <!@TM:1557476618> | Writing EDF file: /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.edn 
+M-2017.03L-SP1-1
+@N:<a href="@N:BW106:@XP_HELP">BW106</a> : <!@TM:1557476618> | Synplicity Constraint File capacitance units using default value of 1pF  
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 152MB)
+
+Writing Verilog Simulation files
+
+Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 152MB)
+
+Writing VHDL Simulation files
+
+Finished Writing VHDL Simulation files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB)
+
+<font color=#A52A2A>@W:<a href="@W:MT246:@XP_HELP">MT246</a> : <a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd:160:4:160:13:@W:MT246:@XP_MSG">serdes_sync_1.vhd(160)</a><!@TM:1557476618> | Blackbox DCUA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) </font>
+<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1557476618> | Found inferred clock serdes_sync_1|rxrefclk with period 10.00ns. Please declare a user-defined clock on object "p:rxrefclk"</font> 
+<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1557476618> | Found inferred clock serdes_sync_1|pll_refclki with period 10.00ns. Please declare a user-defined clock on object "p:pll_refclki"</font> 
+<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1557476618> | Found inferred clock serdes_sync_1|tx_pclk_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:tx_pclk"</font> 
+
+
+<a name=timingReport10></a>##### START OF TIMING REPORT #####[</a>
+# Timing Report written on Fri May 10 10:23:38 2019
+#
+
+
+Top view:               serdes_sync_1
+Requested Frequency:    100.0 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    /home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.fdc
+                       
+@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1557476618> | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 
+
+@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1557476618> | Clock constraints include only register-to-register paths associated with each individual clock. 
+
+
+
+<a name=performanceSummary11></a>Performance Summary</a>
+*******************
+
+
+Worst slack in design: 4.079
+
+@N:<a href="@N:MT286:@XP_HELP">MT286</a> : <!@TM:1557476618> | System clock period 0.000 stretches to negative invalid value -- ignoring stretching. 
+                                         Requested     Estimated     Requested     Estimated               Clock        Clock              
+Starting Clock                           Frequency     Frequency     Period        Period        Slack     Type         Group              
+-------------------------------------------------------------------------------------------------------------------------------------------
+serdes_sync_1|pll_refclki                100.0 MHz     168.9 MHz     10.000        5.921         4.079     inferred     Inferred_clkgroup_0
+serdes_sync_1|rxrefclk                   100.0 MHz     170.5 MHz     10.000        5.864         4.136     inferred     Inferred_clkgroup_1
+serdes_sync_1|tx_pclk_inferred_clock     100.0 MHz     237.5 MHz     10.000        4.211         5.789     inferred     Inferred_clkgroup_2
+System                                   100.0 MHz     840.7 MHz     10.000        1.190         8.810     system       system_clkgroup    
+===========================================================================================================================================
+
+
+
+
+
+<a name=clockRelationships12></a>Clock Relationships</a>
+*******************
+
+Clocks                                                                      |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Starting                              Ending                                |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------
+System                                System                                |  10.000      10.000  |  No paths    -      |  No paths    -      |  No paths    -    
+System                                serdes_sync_1|rxrefclk                |  10.000      8.811   |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|pll_refclki             System                                |  10.000      8.307   |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|pll_refclki             serdes_sync_1|pll_refclki             |  10.000      4.079   |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|pll_refclki             serdes_sync_1|tx_pclk_inferred_clock  |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|rxrefclk                System                                |  10.000      8.193   |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|rxrefclk                serdes_sync_1|rxrefclk                |  10.000      4.136   |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|tx_pclk_inferred_clock  serdes_sync_1|pll_refclki             |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
+serdes_sync_1|tx_pclk_inferred_clock  serdes_sync_1|tx_pclk_inferred_clock  |  10.000      5.789   |  No paths    -      |  No paths    -      |  No paths    -    
+===================================================================================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+<a name=interfaceInfo13></a>Interface Information </a>
+*********************
+
+No IO constraint found
+
+
+
+====================================
+<a name=clockReport14></a>Detailed Report for Clock: serdes_sync_1|pll_refclki</a>
+====================================
+
+
+
+<a name=startingSlack15></a>Starting Points with Worst Slack</a>
+********************************
+
+                                   Starting                                                           Arrival          
+Instance                           Reference                     Type        Pin     Net              Time        Slack
+                                   Clock                                                                               
+-----------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[1]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[1]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[6]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[6]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[7]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[7]      0.907       4.079
+rsl_inst.genblk1\.plol_cnt[12]     serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[12]     0.907       4.079
+rsl_inst.genblk1\.plol_cnt[2]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[2]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[3]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[3]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[4]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[4]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[5]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[5]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[8]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[8]      0.907       4.684
+rsl_inst.genblk1\.plol_cnt[9]      serdes_sync_1|pll_refclki     FD1S3DX     Q       plol_cnt[9]      0.907       4.684
+=======================================================================================================================
+
+
+<a name=endingSlack16></a>Ending Points with Worst Slack</a>
+******************************
+
+                                   Starting                                                             Required          
+Instance                           Reference                     Type        Pin     Net                Time         Slack
+                                   Clock                                                                                  
+--------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[19]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[19]     9.946        4.079
+rsl_inst.genblk1\.plol_cnt[17]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[17]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[18]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[18]     9.946        4.139
+rsl_inst.genblk1\.plol_cnt[15]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[15]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[16]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[16]     9.946        4.200
+rsl_inst.genblk1\.plol_cnt[13]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[13]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[14]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[14]     9.946        4.261
+rsl_inst.genblk1\.plol_cnt[11]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[11]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[12]     serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[12]     9.946        4.322
+rsl_inst.genblk1\.plol_cnt[9]      serdes_sync_1|pll_refclki     FD1S3DX     D       plol_cnt_s[9]      9.946        4.383
+==========================================================================================================================
+
+
+
+<a name=worstPaths17></a>Worst Path Information</a>
+<a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srr:srsf/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srs:fp:64416:69408:@XP_NAMES_GATE">View Worst Path in Analyst</a>
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.867
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     4.079
+
+    Number of logic level(s):                15
+    Starting point:                          rsl_inst.genblk1\.plol_cnt[1] / Q
+    Ending point:                            rsl_inst.genblk1\.plol_cnt[19] / D
+    The start point is clocked by            serdes_sync_1|pll_refclki [rising] on pin CK
+    The end   point is clocked by            serdes_sync_1|pll_refclki [rising] on pin CK
+
+Instance / Net                                        Pin      Pin               Arrival     No. of    
+Name                                     Type         Name     Dir     Delay     Time        Fan Out(s)
+-------------------------------------------------------------------------------------------------------
+rsl_inst.genblk1\.plol_cnt[1]            FD1S3DX      Q        Out     0.907     0.907       -         
+plol_cnt[1]                              Net          -        -       -         -           2         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_10     ORCALUT4     Z        Out     0.606     1.513       -         
+un1_plol_cnt_tc_10                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc_14     ORCALUT4     Z        Out     0.606     2.119       -         
+un1_plol_cnt_tc_14                       Net          -        -       -         -           1         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.genblk1\.un1_plol_cnt_tc        ORCALUT4     Z        Out     0.762     2.881       -         
+un1_plol_cnt_tc                          Net          -        -       -         -           5         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     B        In      0.000     2.881       -         
+rsl_inst.genblk1\.plol_cnt11_i           ORCALUT4     Z        Out     0.840     3.721       -         
+plol_cnt                                 Net          -        -       -         -           21        
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.721       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.621       -         
+plol_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.621       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.682       -         
+plol_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.682       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.743       -         
+plol_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.743       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.804       -         
+plol_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.804       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.865       -         
+plol_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.865       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.926       -         
+plol_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.926       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.987       -         
+plol_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.987       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.048       -         
+plol_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.048       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.109       -         
+plol_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.109       -         
+rsl_inst.genblk1\.plol_cnt_cry_0[17]     CCU2C        COUT     Out     0.061     5.170       -         
+plol_cnt_cry[18]                         Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        CIN      In      0.000     5.170       -         
+rsl_inst.genblk1\.plol_cnt_s_0[19]       CCU2C        S0       Out     0.698     5.867       -         
+plol_cnt_s[19]                           Net          -        -       -         -           1         
+rsl_inst.genblk1\.plol_cnt[19]           FD1S3DX      D        In      0.000     5.867       -         
+=======================================================================================================
+
+
+
+
+====================================
+<a name=clockReport18></a>Detailed Report for Clock: serdes_sync_1|rxrefclk</a>
+====================================
+
+
+
+<a name=startingSlack19></a>Starting Points with Worst Slack</a>
+********************************
+
+                                     Starting                                                          Arrival          
+Instance                             Reference                  Type        Pin     Net                Time        Slack
+                                     Clock                                                                              
+------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[14]      serdes_sync_1|rxrefclk     FD1P3DX     Q       rlol1_cnt[14]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[15]      serdes_sync_1|rxrefclk     FD1P3DX     Q       rlol1_cnt[15]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[16]      serdes_sync_1|rxrefclk     FD1P3DX     Q       rlol1_cnt[16]      0.907       4.136
+rsl_inst.genblk2\.rlol1_cnt[17]      serdes_sync_1|rxrefclk     FD1P3DX     Q       rlol1_cnt[17]      0.907       4.136
+rsl_inst.genblk2\.rlols0_cnt[9]      serdes_sync_1|rxrefclk     FD1P3DX     Q       rlols0_cnt[9]      0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[11]     serdes_sync_1|rxrefclk     FD1P3DX     Q       rlols0_cnt[11]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[12]     serdes_sync_1|rxrefclk     FD1P3DX     Q       rlols0_cnt[12]     0.907       4.170
+rsl_inst.genblk2\.rlols0_cnt[13]     serdes_sync_1|rxrefclk     FD1P3DX     Q       rlols0_cnt[13]     0.907       4.170
+rsl_inst.genblk2\.rlol1_cnt[0]       serdes_sync_1|rxrefclk     FD1P3DX     Q       rlol1_cnt[0]       0.907       4.742
+rsl_inst.genblk2\.rlol1_cnt[1]       serdes_sync_1|rxrefclk     FD1P3DX     Q       rlol1_cnt[1]       0.907       4.742
+========================================================================================================================
+
+
+<a name=endingSlack20></a>Ending Points with Worst Slack</a>
+******************************
+
+                                     Starting                                                            Required          
+Instance                             Reference                  Type        Pin     Net                  Time         Slack
+                                     Clock                                                                                 
+---------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[17]      serdes_sync_1|rxrefclk     FD1P3DX     D       rlol1_cnt_s[17]      9.946        4.136
+rsl_inst.genblk2\.rlol1_cnt[18]      serdes_sync_1|rxrefclk     FD1P3DX     D       rlol1_cnt_s[18]      9.946        4.136
+rsl_inst.genblk2\.rlols0_cnt[17]     serdes_sync_1|rxrefclk     FD1P3DX     D       rlols0_cnt_s[17]     9.946        4.170
+rsl_inst.genblk2\.rlol1_cnt[15]      serdes_sync_1|rxrefclk     FD1P3DX     D       rlol1_cnt_s[15]      9.946        4.197
+rsl_inst.genblk2\.rlol1_cnt[16]      serdes_sync_1|rxrefclk     FD1P3DX     D       rlol1_cnt_s[16]      9.946        4.197
+rsl_inst.genblk2\.rlols0_cnt[15]     serdes_sync_1|rxrefclk     FD1P3DX     D       rlols0_cnt_s[15]     9.946        4.231
+rsl_inst.genblk2\.rlols0_cnt[16]     serdes_sync_1|rxrefclk     FD1P3DX     D       rlols0_cnt_s[16]     9.946        4.231
+rsl_inst.genblk2\.rlol1_cnt[13]      serdes_sync_1|rxrefclk     FD1P3DX     D       rlol1_cnt_s[13]      9.946        4.258
+rsl_inst.genblk2\.rlol1_cnt[14]      serdes_sync_1|rxrefclk     FD1P3DX     D       rlol1_cnt_s[14]      9.946        4.258
+rsl_inst.genblk2\.rlols0_cnt[13]     serdes_sync_1|rxrefclk     FD1P3DX     D       rlols0_cnt_s[13]     9.946        4.292
+===========================================================================================================================
+
+
+
+<a name=worstPaths21></a>Worst Path Information</a>
+<a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srr:srsf/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srs:fp:74615:79340:@XP_NAMES_GATE">View Worst Path in Analyst</a>
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      5.809
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 4.136
+
+    Number of logic level(s):                14
+    Starting point:                          rsl_inst.genblk2\.rlol1_cnt[14] / Q
+    Ending point:                            rsl_inst.genblk2\.rlol1_cnt[18] / D
+    The start point is clocked by            serdes_sync_1|rxrefclk [rising] on pin CK
+    The end   point is clocked by            serdes_sync_1|rxrefclk [rising] on pin CK
+
+Instance / Net                                         Pin      Pin               Arrival     No. of    
+Name                                      Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.rlol1_cnt[14]           FD1P3DX      Q        Out     0.907     0.907       -         
+rlol1_cnt[14]                             Net          -        -       -         -           2         
+rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     A        In      0.000     0.907       -         
+rsl_inst.rlol1_cnt_tc_1_10                ORCALUT4     Z        Out     0.606     1.513       -         
+rlol1_cnt_tc_1_10                         Net          -        -       -         -           1         
+rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     D        In      0.000     1.513       -         
+rsl_inst.rlol1_cnt_tc_1_14                ORCALUT4     Z        Out     0.606     2.119       -         
+rlol1_cnt_tc_1_14                         Net          -        -       -         -           1         
+rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     D        In      0.000     2.119       -         
+rsl_inst.rlol1_cnt_tc_1                   ORCALUT4     Z        Out     0.768     2.887       -         
+rlol1_cnt_tc_1                            Net          -        -       -         -           6         
+rsl_inst.genblk2\.rlos_db_p1_RNIS0OP      ORCALUT4     A        In      0.000     2.887       -         
+rsl_inst.genblk2\.rlos_db_p1_RNIS0OP      ORCALUT4     Z        Out     0.837     3.724       -         
+rlol1_cnt                                 Net          -        -       -         -           20        
+rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        A1       In      0.000     3.724       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[0]      CCU2C        COUT     Out     0.900     4.624       -         
+rlol1_cnt_cry[0]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        CIN      In      0.000     4.624       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[1]      CCU2C        COUT     Out     0.061     4.685       -         
+rlol1_cnt_cry[2]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        CIN      In      0.000     4.685       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[3]      CCU2C        COUT     Out     0.061     4.746       -         
+rlol1_cnt_cry[4]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        CIN      In      0.000     4.746       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[5]      CCU2C        COUT     Out     0.061     4.807       -         
+rlol1_cnt_cry[6]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        CIN      In      0.000     4.807       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[7]      CCU2C        COUT     Out     0.061     4.868       -         
+rlol1_cnt_cry[8]                          Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        CIN      In      0.000     4.868       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[9]      CCU2C        COUT     Out     0.061     4.929       -         
+rlol1_cnt_cry[10]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        CIN      In      0.000     4.929       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[11]     CCU2C        COUT     Out     0.061     4.990       -         
+rlol1_cnt_cry[12]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        CIN      In      0.000     4.990       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[13]     CCU2C        COUT     Out     0.061     5.051       -         
+rlol1_cnt_cry[14]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        CIN      In      0.000     5.051       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[15]     CCU2C        COUT     Out     0.061     5.112       -         
+rlol1_cnt_cry[16]                         Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        CIN      In      0.000     5.112       -         
+rsl_inst.genblk2\.rlol1_cnt_cry_0[17]     CCU2C        S1       Out     0.698     5.809       -         
+rlol1_cnt_s[18]                           Net          -        -       -         -           1         
+rsl_inst.genblk2\.rlol1_cnt[18]           FD1P3DX      D        In      0.000     5.809       -         
+========================================================================================================
+
+
+
+
+====================================
+<a name=clockReport22></a>Detailed Report for Clock: serdes_sync_1|tx_pclk_inferred_clock</a>
+====================================
+
+
+
+<a name=startingSlack23></a>Starting Points with Worst Slack</a>
+********************************
+
+                            Starting                                                                      Arrival          
+Instance                    Reference                                Type        Pin     Net              Time        Slack
+                            Clock                                                                                          
+---------------------------------------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1       serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p1     1.098       5.789
+sll_inst.ppul_sync_p2       serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     Q       ppul_sync_p2     1.098       5.789
+sll_inst.pcount_diff[0]     serdes_sync_1|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_0      0.985       6.147
+sll_inst.pcount[0]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[0]        0.955       6.178
+sll_inst.pcount_diff[1]     serdes_sync_1|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_1      0.955       6.239
+sll_inst.pcount_diff[2]     serdes_sync_1|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_2      0.955       6.239
+sll_inst.pcount[1]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[1]        0.907       6.287
+sll_inst.pcount[2]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     Q       pcount[2]        0.907       6.287
+sll_inst.pcount_diff[3]     serdes_sync_1|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_3      0.955       6.300
+sll_inst.pcount_diff[4]     serdes_sync_1|tx_pclk_inferred_clock     FD1P3BX     Q       un13_lock_4      0.955       6.300
+===========================================================================================================================
+
+
+<a name=endingSlack24></a>Ending Points with Worst Slack</a>
+******************************
+
+                             Starting                                                                                     Required          
+Instance                     Reference                                Type        Pin     Net                             Time         Slack
+                             Clock                                                                                                          
+--------------------------------------------------------------------------------------------------------------------------------------------
+sll_inst.pcount[21]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[21]                    9.946        5.789
+sll_inst.pcount[19]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[19]                    9.946        5.850
+sll_inst.pcount[20]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[20]                    9.946        5.850
+sll_inst.pcount[17]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[17]                    9.946        5.911
+sll_inst.pcount[18]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[18]                    9.946        5.911
+sll_inst.pcount[15]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[15]                    9.946        5.972
+sll_inst.pcount[16]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[16]                    9.946        5.972
+sll_inst.pcount[13]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[13]                    9.946        6.033
+sll_inst.pcount[14]          serdes_sync_1|tx_pclk_inferred_clock     FD1S3DX     D       pcount_s[14]                    9.946        6.033
+sll_inst.pcount_diff[21]     serdes_sync_1|tx_pclk_inferred_clock     FD1P3DX     D       un1_pcount_diff_1_s_21_0_S0     9.946        6.034
+============================================================================================================================================
+
+
+
+<a name=worstPaths25></a>Worst Path Information</a>
+<a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srr:srsf/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srs:fp:84832:88738:@XP_NAMES_GATE">View Worst Path in Analyst</a>
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.054
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.946
+
+    - Propagation time:                      4.157
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (non-critical) :                 5.789
+
+    Number of logic level(s):                13
+    Starting point:                          sll_inst.ppul_sync_p1 / Q
+    Ending point:                            sll_inst.pcount[21] / D
+    The start point is clocked by            serdes_sync_1|tx_pclk_inferred_clock [rising] on pin CK
+    The end   point is clocked by            serdes_sync_1|tx_pclk_inferred_clock [rising] on pin CK
+
+Instance / Net                             Pin      Pin               Arrival     No. of    
+Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
+--------------------------------------------------------------------------------------------
+sll_inst.ppul_sync_p1         FD1S3DX      Q        Out     1.098     1.098       -         
+ppul_sync_p1                  Net          -        -       -         -           25        
+sll_inst.pcount10_0_o3        ORCALUT4     A        In      0.000     1.098       -         
+sll_inst.pcount10_0_o3        ORCALUT4     Z        Out     0.851     1.950       -         
+N_8                           Net          -        -       -         -           25        
+sll_inst.pcount_cry_0[0]      CCU2C        A1       In      0.000     1.950       -         
+sll_inst.pcount_cry_0[0]      CCU2C        COUT     Out     0.900     2.850       -         
+pcount_cry[0]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[1]      CCU2C        CIN      In      0.000     2.850       -         
+sll_inst.pcount_cry_0[1]      CCU2C        COUT     Out     0.061     2.911       -         
+pcount_cry[2]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[3]      CCU2C        CIN      In      0.000     2.911       -         
+sll_inst.pcount_cry_0[3]      CCU2C        COUT     Out     0.061     2.972       -         
+pcount_cry[4]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[5]      CCU2C        CIN      In      0.000     2.972       -         
+sll_inst.pcount_cry_0[5]      CCU2C        COUT     Out     0.061     3.033       -         
+pcount_cry[6]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[7]      CCU2C        CIN      In      0.000     3.033       -         
+sll_inst.pcount_cry_0[7]      CCU2C        COUT     Out     0.061     3.094       -         
+pcount_cry[8]                 Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[9]      CCU2C        CIN      In      0.000     3.094       -         
+sll_inst.pcount_cry_0[9]      CCU2C        COUT     Out     0.061     3.155       -         
+pcount_cry[10]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[11]     CCU2C        CIN      In      0.000     3.155       -         
+sll_inst.pcount_cry_0[11]     CCU2C        COUT     Out     0.061     3.216       -         
+pcount_cry[12]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[13]     CCU2C        CIN      In      0.000     3.216       -         
+sll_inst.pcount_cry_0[13]     CCU2C        COUT     Out     0.061     3.277       -         
+pcount_cry[14]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[15]     CCU2C        CIN      In      0.000     3.277       -         
+sll_inst.pcount_cry_0[15]     CCU2C        COUT     Out     0.061     3.338       -         
+pcount_cry[16]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[17]     CCU2C        CIN      In      0.000     3.338       -         
+sll_inst.pcount_cry_0[17]     CCU2C        COUT     Out     0.061     3.399       -         
+pcount_cry[18]                Net          -        -       -         -           1         
+sll_inst.pcount_cry_0[19]     CCU2C        CIN      In      0.000     3.399       -         
+sll_inst.pcount_cry_0[19]     CCU2C        COUT     Out     0.061     3.460       -         
+pcount_cry[20]                Net          -        -       -         -           1         
+sll_inst.pcount_s_0[21]       CCU2C        CIN      In      0.000     3.460       -         
+sll_inst.pcount_s_0[21]       CCU2C        S0       Out     0.698     4.157       -         
+pcount_s[21]                  Net          -        -       -         -           1         
+sll_inst.pcount[21]           FD1S3DX      D        In      0.000     4.157       -         
+============================================================================================
+
+
+
+
+====================================
+<a name=clockReport26></a>Detailed Report for Clock: System</a>
+====================================
+
+
+
+<a name=startingSlack27></a>Starting Points with Worst Slack</a>
+********************************
+
+              Starting                                                   Arrival           
+Instance      Reference     Type     Pin                Net              Time        Slack 
+              Clock                                                                        
+-------------------------------------------------------------------------------------------
+DCU0_inst     System        DCUA     CH0_FFS_RLOL       rx_cdr_lol_s     0.000       8.810 
+DCU0_inst     System        DCUA     CH0_FFS_RLOS       rx_los_low_s     0.000       8.810 
+DCU0_inst     System        DCUA     CH0_FF_RX_PCLK     rx_pclk          0.000       10.000
+===========================================================================================
+
+
+<a name=endingSlack28></a>Ending Points with Worst Slack</a>
+******************************
+
+                                                       Starting                                                                       Required           
+Instance                                               Reference     Type        Pin                Net                               Time         Slack 
+                                                       Clock                                                                                             
+---------------------------------------------------------------------------------------------------------------------------------------------------------
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     SP                 un2_rdo_serdes_rst_dual_c_2_i     9.806        8.810 
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]     System        FD1P3DX     D                  un2_rdo_serdes_rst_dual_c_1       9.946        9.556 
+rsl_inst.genblk2\.rlol_p1                              System        FD1S3DX     D                  rx_cdr_lol_s                      9.946        9.946 
+rsl_inst.genblk2\.rlos_p1                              System        FD1S3DX     D                  rx_los_low_s                      9.946        9.946 
+DCU0_inst                                              System        DCUA        CH0_FF_RXI_CLK     rx_pclk                           10.000       10.000
+=========================================================================================================================================================
+
+
+
+<a name=worstPaths29></a>Worst Path Information</a>
+<a href="/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srr:srsf/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1.srs:fp:92628:93798:@XP_NAMES_GATE">View Worst Path in Analyst</a>
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      10.000
+    - Setup time:                            0.194
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         9.806
+
+    - Propagation time:                      0.996
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 8.810
+
+    Number of logic level(s):                2
+    Starting point:                          DCU0_inst / CH0_FFS_RLOL
+    Ending point:                            rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0] / SP
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            serdes_sync_1|rxrefclk [rising] on pin CK
+
+Instance / Net                                                          Pin              Pin               Arrival     No. of    
+Name                                                       Type         Name             Dir     Delay     Time        Fan Out(s)
+---------------------------------------------------------------------------------------------------------------------------------
+DCU0_inst                                                  DCUA         CH0_FFS_RLOL     Out     0.000     0.000       -         
+rx_cdr_lol_s                                               Net          -                -       -         -           4         
+rsl_inst.un2_rdo_serdes_rst_dual_c_2_0                     ORCALUT4     B                In      0.000     0.000       -         
+rsl_inst.un2_rdo_serdes_rst_dual_c_2_0                     ORCALUT4     Z                Out     0.606     0.606       -         
+un2_rdo_serdes_rst_dual_c_2_0                              Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO[0]     ORCALUT4     B                In      0.000     0.606       -         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd_RNO[0]     ORCALUT4     Z                Out     0.390     0.996       -         
+un2_rdo_serdes_rst_dual_c_2_i                              Net          -                -       -         -           1         
+rsl_inst.genblk2\.genblk3\.lfor\[0\]\.rxpr_appd[0]         FD1P3DX      SP               In      0.000     0.996       -         
+=================================================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+None
+
+Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 152MB)
+
+---------------------------------------
+<a name=resourceUsage30></a>Resource Usage Report</a>
+Part: lfe5um_25f-6
+
+Register bits: 220 of 24288 (1%)
+PIC Latch:       0
+I/O cells:       0
+
+
+Details:
+CCU2C:          113
+DCUA:           1
+FD1P3BX:        20
+FD1P3DX:        92
+FD1S3BX:        12
+FD1S3DX:        96
+GSR:            1
+INV:            3
+ORCALUT4:       150
+PFUMX:          2
+PUR:            1
+VHI:            6
+VLO:            6
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 35MB peak: 152MB)
+
+Process took 0h:00m:03s realtime, 0h:00m:03s cputime
+# Fri May 10 10:23:38 2019
+
+###########################################################]
+
+</pre></samp></body></html>

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_toc.htm b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_toc.htm
new file mode 100644 (file)
index 0000000..9abc35f
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_toc.htm
@@ -0,0 +1,60 @@
+ <html> 
+  <head>
+    <script type="text/javascript" src="file:///home/soft/lattice/diamond/3.10_x64/synpbase/lib/report/reportlog_tree.js"></script>
+    <link rel="stylesheet" type="text/css" href="file:///home/soft/lattice/diamond/3.10_x64/synpbase/lib/report/reportlog_tree.css" />  
+  </head> 
+
+  <body style="background-color:#e0e0ff;">
+   <script type="text/javascript"> reportLogObj.loadImage("closed.png", "open.png")</script>
+    <ul id="syn_results-menu" class="treeview" style="padding-left:12;">
+        <li style="font-size:12; font-style:normal"> <b style="background-color:#a2bff0; font-weight:bold">serdes_sync_1 (syn_results)</b> 
+         <ul rel="open" style="font-size:small;">
+
+<li style="font-size:12; font-style:normal"><b style="background-color:#a2bff0; font-weight:bold">Synthesis -  </b> 
+<ul rel="open">
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_srr.htm#compilerReport1" target="srrFrame" title="">Compiler Report</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_srr.htm#compilerReport4" target="srrFrame" title="">Compiler Constraint Applicator</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_srr.htm#mapperReport6" target="srrFrame" title="">Pre-mapping Report</a>  
+<ul rel="open" >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_srr.htm#mapperReport7" target="srrFrame" title="">Clock Summary</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_srr.htm#mapperReport8" target="srrFrame" title="">Mapper Report</a>  
+<ul rel="open" >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_srr.htm#clockReport9" target="srrFrame" title="">Clock Conversion</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_srr.htm#timingReport10" target="srrFrame" title="">Timing Report</a>  
+<ul rel="open" >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_srr.htm#performanceSummary11" target="srrFrame" title="">Performance Summary</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_srr.htm#clockRelationships12" target="srrFrame" title="">Clock Relationships</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_srr.htm#interfaceInfo13" target="srrFrame" title="">Interface Information</a>  </li>
+<li><a href="file://#" target="srrFrame" title="">Detailed Report for Clocks</a>  
+<ul  >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_srr.htm#clockReport14" target="srrFrame" title="">Clock: serdes_sync_1|pll_refclki</a>  
+<ul  >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_srr.htm#startingSlack15" target="srrFrame" title="">Starting Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_srr.htm#endingSlack16" target="srrFrame" title="">Ending Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_srr.htm#worstPaths17" target="srrFrame" title="">Worst Path Information</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_srr.htm#clockReport18" target="srrFrame" title="">Clock: serdes_sync_1|rxrefclk</a>  
+<ul  >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_srr.htm#startingSlack19" target="srrFrame" title="">Starting Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_srr.htm#endingSlack20" target="srrFrame" title="">Ending Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_srr.htm#worstPaths21" target="srrFrame" title="">Worst Path Information</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_srr.htm#clockReport22" target="srrFrame" title="">Clock: serdes_sync_1|tx_pclk_inferred_clock</a>  
+<ul  >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_srr.htm#startingSlack23" target="srrFrame" title="">Starting Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_srr.htm#endingSlack24" target="srrFrame" title="">Ending Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_srr.htm#worstPaths25" target="srrFrame" title="">Worst Path Information</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_srr.htm#clockReport26" target="srrFrame" title="">Clock: System</a>  
+<ul  >
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_srr.htm#startingSlack27" target="srrFrame" title="">Starting Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_srr.htm#endingSlack28" target="srrFrame" title="">Ending Points with Worst Slack</a>  </li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_srr.htm#worstPaths29" target="srrFrame" title="">Worst Path Information</a>  </li></ul></li></ul></li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/serdes_sync_1_srr.htm#resourceUsage30" target="srrFrame" title="">Resource Utilization</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/serdes_sync_1_cck.rpt" target="srrFrame" title="">Constraint Checker Report (10:23 10-May)</a>  </li></ul></li>
+<li><a href="file:///home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/stdout.log" target="srrFrame" title="">Session Log (10:23 10-May)</a>  
+<ul  ></ul></li>         </ul>
+        </li>
+   </ul>
+
+   <script type="text/javascript"> reportLogObj.generateLog("syn_results-menu")</script>
+
+  </body>
+ </html>
\ No newline at end of file

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/statusReport.html b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/statusReport.html
new file mode 100644 (file)
index 0000000..1a6a0b4
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/syntmp/statusReport.html
@@ -0,0 +1,115 @@
+<html> 
+                       <head>                  <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1" />
+                       <title>Project Status Summary Page</title>
+                       <link rel="stylesheet" type="text/css" href="projectstatuspage.css" />
+                       <script type = "text/javascript" src="projectstatuspage.js"></script>
+                       </head>
+
+                       <body style="background-color:#f0f0ff;">
+                       
+<table style="border:none;" width="100%" ><tr> <td class="outline">
+<table width="100%" border="0" cellspacing="0" cellpadding="0">             <thead class="tablehead"><tr><th colspan="4">Project Settings</th><tr> 
+ <tr> <td class="optionTitle" align="left"> Project Name</td> <td> serdes_sync_1</td> <td class="optionTitle" align="left"> Device Name</td> <td> syn_results: Lattice ECP5UM : LFE5UM_25F</td> </tr>
+<tr> <td class="optionTitle" align="left"> Implementation Name</td> <td> syn_results</td> <td class="optionTitle" align="left"> Top Module</td> <td> serdes_sync_1</td> </tr>
+                </thead> 
+                <tbody> <tr> <td class="optionTitle" align="left"> Pipelining</td> <td> 0</td> <td class="optionTitle" align="left"> Retiming</td> <td> 0</td> </tr>
+<tr> <td class="optionTitle" align="left"> Resource Sharing</td> <td> 1</td> <td class="optionTitle" align="left"> Fanout Guide</td> <td> 50</td> </tr>
+<tr> <td class="optionTitle" align="left"> Disable I/O Insertion</td> <td> 1</td> <td class="optionTitle" align="left"> Disable Sequential Optimizations</td> <td> 0</td> </tr>
+<tr> <td class="optionTitle" align="left"> Clock Conversion</td> <td> 1</td> <td class="optionTitle" align="left"> FSM Compiler</td> <td> 1</td> </tr>
+ 
+</tbody> 
+  </table><br>  <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
+                                  <thead class="tablehead"><tr><th   colspan="9">Run Status</th></tr></thead>
+         <tbody>
+               <tr>
+                       <th align="left" width="17%">Job Name</th>
+                       <th align="left">Status</th>
+                       <td class="lnote" align="center" title="Notes"></td>
+                       <td class="lwarn" align="center" title="Warnings"></td>
+                       <td class="lerror" align="center" title="Errors"></td>
+                       <th align="left">CPU Time</th>
+                       <th align="left">Real Time</th>
+                       <th align="left">Memory</th>
+                       <th align="left">Date/Time</th>
+         </tr>
+  <tr>
+  <td class="optionTitle"> (compiler)</td><td>Complete</td>
+ <td>15</td>
+ <td>77</td>
+<td>0</td>
+<td>-</td>
+<td>00m:02s</td>
+<td>-</td>
+<td><font size="-1">5/10/19</font><br/><font size="-2">10:23 AM</font></td>
+</tr> 
+
+ <tr>
+  <td class="optionTitle"> (premap)</td><td>Complete</td>
+ <td>8</td>
+ <td>3</td>
+<td>0</td>
+<td>0m:00s</td>
+<td>0m:00s</td>
+<td>145MB</td>
+<td><font size="-1">5/10/19</font><br/><font size="-2">10:23 AM</font></td>
+</tr> 
+
+ <tr>
+  <td class="optionTitle"> (fpga_mapper)</td><td>Complete</td>
+ <td>23</td>
+ <td>4</td>
+<td>0</td>
+<td>0m:03s</td>
+<td>0m:03s</td>
+<td>152MB</td>
+<td><font size="-1">5/10/19</font><br/><font size="-2">10:23 AM</font></td>
+</tr> 
+
+<tr>
+  <td class="optionTitle">Multi-srs Generator</td>
+  <td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td></td><td class="empty"></td><td class="empty"></td><td><font size="-1">5/10/19</font><br/><font size="-2">10:23 AM</font></td>             </tbody>
+     </table>
+ <br> 
+ <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
+                                  <thead class="tablehead"><tr><th   colspan="4">Area Summary</th></tr></thead>
+<tfoot> <tr> <td class="optionTitle" colspan="4"></td></tr> 
+ </tfoot> 
+ <tbody> <tr> 
+<td title ="Total Register bits used" class="optionTitle" align="left">Register bits</td> <td>220</td>
+<td title ="Total I/O cells used" class="optionTitle" align="left">I/O cells</td> <td>0</td>
+</tr>
+<tr> 
+<td title ="Total Block RAMs used" class="optionTitle" align="left">Block RAMs
+(v_ram)</td> <td>0</td>
+<td title ="Total DSPs used" class="optionTitle" align="left">DSPs
+(dsp_used)</td> <td>0</td>
+</tr>
+<tr> 
+<td title ="Total ORCA LUTs used" class="optionTitle" align="left">ORCA LUTs
+(total_luts)</td> <td>150</td>
+<td class="optionTitle"></td><td></td></tr> 
+</tbody>
+    </table><br>
+ <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
+                                  <thead class="tablehead"><tr><th   colspan="4">Timing Summary</th></tr></thead>
+<tfoot> <tr> <td class="optionTitle" colspan="2"></td></tr> 
+ </tfoot> 
+<tbody> 
+   <tr><th class="optionTitle" align= "left ">Clock Name</th><th class="optionTitle" align= "left ">Req Freq</th><th class="optionTitle" align= "left ">Est Freq</th><th class="optionTitle" align= "left ">Slack</th></tr> 
+<tr> <td  align="left">serdes_sync_1|pll_refclki</td><td  align="left">100.0 MHz</td><td  align="left">168.9 MHz</td><td  align="left">4.079</td></tr> 
+<tr> <td  align="left">serdes_sync_1|rxrefclk</td><td  align="left">100.0 MHz</td><td  align="left">170.5 MHz</td><td  align="left">4.136</td></tr> 
+<tr> <td  align="left">serdes_sync_1|tx_pclk_inferred_clock</td><td  align="left">100.0 MHz</td><td  align="left">237.5 MHz</td><td  align="left">5.789</td></tr> 
+<tr> <td  align="left">System</td><td  align="left">100.0 MHz</td><td  align="left">840.7 MHz</td><td  align="left">8.810</td></tr> 
+</tbody> 
+ </table>
+<br>
+ <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
+                                  <thead class="tablehead"><tr><th   colspan="4">Optimizations Summary</th></tr></thead>
+ <tbody> <tr> 
+<td title ="Non-gated/non-generated clock trees / Gated/generated clock trees" class="optionTitle" align="left">Combined Clock Conversion</td> <td>3 / 0</td>
+<td class="optionTitle"></td><td></td></tr> 
+</tbody>
+    </table><br>
+<br> 
+</td></tr></table></body> 
+ </html>
\ No newline at end of file

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/.cckTransfer b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/.cckTransfer
new file mode 100644 (file)
index 0000000..0c7a019
Binary files /dev/null and b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/.cckTransfer differ

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/_mh_info b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/_mh_info
new file mode 100644 (file)
index 0000000..c32d2a3
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/_mh_info
@@ -0,0 +1,2 @@
+|/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.info|
+|2|

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/_verilog_hintfile b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/_verilog_hintfile
new file mode 100644 (file)
index 0000000..9515999
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/_verilog_hintfile
@@ -0,0 +1,65 @@
+%%% protect protected_file
+#OPTIONS:"|-bldtbl|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
+#CUR:"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":1557476609
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599
+@E8lFkRDC#8CsC##_$_MO4H
+DLssN$FRIsF    
+kk0b08REFbk0RF4
+kk0b08REFMk0RH4
+M0bkRHE8M4bR
+bHMkE0R8MHMRH4
+M0bkRssGCDVO   
+R4Fbk0ks0RGO_bD4       R
+0FkbRk00bG_ORD 4M
+HbRk00NG80UNR
+bHMk00RGR_     4M
+HbRk00VG_FCsO_#8Hb
+R4HkMb0GR0_#8HbC_#D
+R4Fbk0ks0RG08NN
+RUFbk0ks0RGR_  4k
+F00bkR_sG8bH#_sCsRF4
+kk0b0GRs__OPCRss4M
+HbRk00HG_8_DCO
+R4HkMb0HR#oDMN_08CC_O0O
+R4Fbk0ks0RGF_D#F_DIR_#4k
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+HbRk00bG_Ibsk_4OR
+bHMks0RGI_bs_kbO
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+M0bkRH#O_8N8s
+RnFbk0k#0ROsH_808NN
+RUHkMb0OR#HM_C_N8kD
+R4HkMb0OR#HC_#Dk_8N4DR
+bHMk#0ROCH_M
+R4HkMb0OR#HC_#D
+R4HkMb0OR#H8_sRH4
+M0bkRH#O_MIsRF4
+kk0b0OR#HM_H0
+R4HkMb0$RON0I#M
+R4HkMb0CR#s#8C_Lb8RH4
+M0bkRDbD_VsCOHD        RH4
+M0bkRDs#_#8HNCLDRH4
+M0bkRDs#_0s#RH4
+M0bkRs#C8_C#s_#08DkN_4OR
+bHMks0R#80_k_NDO
+R4HkMb0GR0_s#C8_C#s_#0O
+R4HkMb0GR0_#bO_0s#_4OR
+0FkbRk0b_DDDRFD4k
+F00bkRDs#__0GsR8$4M
+HbRk0s#G_CCs8##_s0R_O4M
+HbRk0sbG_Os#_#O0_RF4
+kk0b0#RsDG_s_$s8RC4
+MF8l8CkD
+
+@ 

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer0.fdep b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer0.fdep
new file mode 100644 (file)
index 0000000..9be0f86
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer0.fdep
@@ -0,0 +1,33 @@
+#defaultlanguage:vhdl
+#OPTIONS:"|-mixedhdl|-top|serdes_sync_1|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610
+#CUR:"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":1557476609
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599
+0 "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd" vhdl
+
+# Dependency Lists (Uses list)
+0 -1
+
+# Dependency Lists (Users Of)
+0 -1
+
+# Design Unit to File Association
+arch work serdes_sync_1 v1 0
+module work serdes_sync_1 0
+
+# Unbound Instances to File Association
+inst work serdes_sync_1 serdes_sync_1sll_core 0
+inst work serdes_sync_1 serdes_sync_1rsl_core 0
+inst work serdes_sync_1 dcua 0
+
+
+# Configuration files used

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer0.fdeporig b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer0.fdeporig
new file mode 100644 (file)
index 0000000..515792e
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer0.fdeporig
@@ -0,0 +1,29 @@
+#defaultlanguage:vhdl
+#OPTIONS:"|-mixedhdl|-top|serdes_sync_1|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610
+#CUR:"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":1557476609
+0 "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd" vhdl
+
+# Dependency Lists (Uses list)
+0 -1
+
+# Dependency Lists (Users Of)
+0 -1
+
+# Design Unit to File Association
+arch work serdes_sync_1 v1 0
+module work serdes_sync_1 0
+
+# Unbound Instances to File Association
+inst work serdes_sync_1 serdes_sync_1sll_core 0
+inst work serdes_sync_1 serdes_sync_1rsl_core 0
+inst work serdes_sync_1 dcua 0

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer0.srs b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer0.srs
new file mode 100644 (file)
index 0000000..8872fa1
Binary files /dev/null and b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer0.srs differ

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer0.tlg b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer0.tlg
new file mode 100644 (file)
index 0000000..e304b8e
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer0.tlg
@@ -0,0 +1,2 @@
+@N: CD630 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":30:7:30:19|Synthesizing work.serdes_sync_1.v1.
+Post processing for work.serdes_sync_1.v1

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer0.tlg.db b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer0.tlg.db
new file mode 100644 (file)
index 0000000..8bff010
Binary files /dev/null and b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer0.tlg.db differ

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.fdep b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.fdep
new file mode 100644 (file)
index 0000000..b1d0c36
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.fdep
@@ -0,0 +1,22 @@
+#OPTIONS:"|-mixedhdl|-modhint|/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/_verilog_hintfile|-top|work.serdes_sync_1sll_core|-top|work.serdes_sync_1rsl_core|-mpparams|/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/_mh_params|-layerid|1|-orig_srs|/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/|-I|/home/soft/lattice/diamond/3.10_x64/synpbase/lib|-v2001|-devicelib|/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v|-devicelib|/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_ver":1542167761
+#CUR:"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/_verilog_hintfile":1557476610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v":1542167595
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v":1542167597
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v":1542167630
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v":1542167630
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v":1542167630
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh":1542167630
+#CUR:"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1557476609
+#numinternalfiles:6
+#defaultlanguage:verilog
+0                      "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v" verilog
+#Dependency Lists(Uses List)
+0 -1
+#Dependency Lists(Users Of)
+0 -1
+#Design Unit to File Association
+module work serdes_sync_1rsl_core 0
+module work sync 0
+module work serdes_sync_1sll_core 0
+#Unbound instances to file Association.

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.fdepxmr b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.fdepxmr
new file mode 100644 (file)
index 0000000..37d628b
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.fdepxmr
@@ -0,0 +1 @@
+#XMR Information

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.info b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.info
new file mode 100644 (file)
index 0000000..de9b528
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.info
@@ -0,0 +1,2 @@
+|work.serdes_sync_1rsl_core|parameter pnum_channels 1;,parameter pprotocol "G8B10B";,parameter pserdes_mode "RX AND TX";,parameter pport_tx_rdy "ENABLED";,parameter pwait_tx_rdy 3000;,parameter pport_rx_rdy "ENABLED";,parameter pwait_rx_rdy 3000;|
+|work.serdes_sync_1sll_core|parameter PPROTOCOL "G8B10B";,parameter PLOL_SETTING 1;,parameter PDYN_RATE_CTRL "DISABLED";,parameter PPCIE_MAX_RATE "2.5";,parameter PDIFF_VAL_LOCK 39;,parameter PDIFF_VAL_UNLOCK 262;,parameter PPCLK_TC 131072;,parameter PDIFF_DIV11_VAL_LOCK 0;,parameter PDIFF_DIV11_VAL_UNLOCK 0;,parameter PPCLK_DIV11_TC 0;|

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.srs b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.srs
new file mode 100644 (file)
index 0000000..85e7f27
Binary files /dev/null and b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.srs differ

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.tlg b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.tlg
new file mode 100644 (file)
index 0000000..3424f4c
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.tlg
@@ -0,0 +1,252 @@
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1968:7:1968:10|Synthesizing module sync in library work.
+
+       PDATA_RST_VAL=32'b00000000000000000000000000000000
+   Generated name = sync_0s
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1051:7:1051:27|Synthesizing module serdes_sync_1sll_core in library work.
+
+       PPROTOCOL=48'b010001110011100001000010001100010011000001000010
+       PLOL_SETTING=32'b00000000000000000000000000000001
+       PDYN_RATE_CTRL=64'b0100010001001001010100110100000101000010010011000100010101000100
+       PPCIE_MAX_RATE=24'b001100100010111000110101
+       PDIFF_VAL_LOCK=32'b00000000000000000000000000100111
+       PDIFF_VAL_UNLOCK=32'b00000000000000000000000100000110
+       PPCLK_TC=32'b00000000000000100000000000000000
+       PDIFF_DIV11_VAL_LOCK=32'b00000000000000000000000000000000
+       PDIFF_DIV11_VAL_UNLOCK=32'b00000000000000000000000000000000
+       PPCLK_DIV11_TC=32'b00000000000000000000000000000000
+       LPLL_LOSS_ST=2'b00
+       LPLL_PRELOSS_ST=2'b01
+       LPLL_PRELOCK_ST=2'b10
+       LPLL_LOCK_ST=2'b11
+       LRCLK_TC=16'b1111111111111111
+       LRCLK_TC_PUL_WIDTH=16'b0000000000110010
+       LHB_WAIT_CNT=8'b11111111
+       LPCLK_TC_0=32'b00000000000000001000000000000000
+       LPCLK_TC_1=32'b00000000000000010000000000000000
+       LPCLK_TC_2=32'b00000000000000100000000000000000
+       LPCLK_TC_3=32'b00000000000000101000000000000000
+       LPCLK_TC_4=32'b00000000000000010000000000000000
+       LPDIFF_LOCK_00=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_10=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_20=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_30=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_40=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_01=32'b00000000000000000000000000001001
+       LPDIFF_LOCK_11=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_21=32'b00000000000000000000000000100111
+       LPDIFF_LOCK_31=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_41=32'b00000000000000000000000000010011
+       LPDIFF_LOCK_02=32'b00000000000000000000000000110001
+       LPDIFF_LOCK_12=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_22=32'b00000000000000000000000011000100
+       LPDIFF_LOCK_32=32'b00000000000000000000000011110101
+       LPDIFF_LOCK_42=32'b00000000000000000000000001100010
+       LPDIFF_LOCK_03=32'b00000000000000000000000010000011
+       LPDIFF_LOCK_13=32'b00000000000000000000000100000110
+       LPDIFF_LOCK_23=32'b00000000000000000000001000001100
+       LPDIFF_LOCK_33=32'b00000000000000000000001010001111
+       LPDIFF_LOCK_43=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_00=32'b00000000000000000000000000010011
+       LPDIFF_UNLOCK_10=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_20=32'b00000000000000000000000001001110
+       LPDIFF_UNLOCK_30=32'b00000000000000000000000001100010
+       LPDIFF_UNLOCK_40=32'b00000000000000000000000000100111
+       LPDIFF_UNLOCK_01=32'b00000000000000000000000001000001
+       LPDIFF_UNLOCK_11=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_21=32'b00000000000000000000000100000110
+       LPDIFF_UNLOCK_31=32'b00000000000000000000000101000111
+       LPDIFF_UNLOCK_41=32'b00000000000000000000000010000011
+       LPDIFF_UNLOCK_02=32'b00000000000000000000000001001000
+       LPDIFF_UNLOCK_12=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_22=32'b00000000000000000000000100100000
+       LPDIFF_UNLOCK_32=32'b00000000000000000000000101101000
+       LPDIFF_UNLOCK_42=32'b00000000000000000000000010010000
+       LPDIFF_UNLOCK_03=32'b00000000000000000000000011000100
+       LPDIFF_UNLOCK_13=32'b00000000000000000000000110001001
+       LPDIFF_UNLOCK_23=32'b00000000000000000000001100010010
+       LPDIFF_UNLOCK_33=32'b00000000000000000000001111010111
+       LPDIFF_UNLOCK_43=32'b00000000000000000000000110001001
+   Generated name = serdes_sync_1sll_core_Z1_layer1
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1287:54:1287:59|Removing redundant assignment.
+@N: CG179 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1293:52:1293:55|Removing redundant assignment.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1350:0:1350:5|Pruning unused register rcpri_mod_ch_st. Make sure that there are no unused intermediate registers.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_unlock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rdiff_comp_lock[15:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 0 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 1 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 2 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 3 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 4 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 5 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 6 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 7 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 8 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 9 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 10 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 11 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 12 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 13 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 14 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 15 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 16 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 18 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 19 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 20 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+@W: CL208 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|All reachable assignments to bit 21 of genblk5.rcount_tc[21:0] assign 0, register removed by optimization.
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+Could not match passed parameter, trying a case insensitive search ...
+@N: CG364 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":92:7:92:27|Synthesizing module serdes_sync_1rsl_core in library work.
+
+       pnum_channels=32'b00000000000000000000000000000001
+       pprotocol=48'b010001110011100001000010001100010011000001000010
+       pserdes_mode=72'b010100100101100000100000010000010100111001000100001000000101010001011000
+       pport_tx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_tx_rdy=32'b00000000000000000000101110111000
+       pport_rx_rdy=56'b01000101010011100100000101000010010011000100010101000100
+       pwait_rx_rdy=32'b00000000000000000000101110111000
+       wa_num_cycles=32'b00000000000000000000010000000000
+       dac_num_cycles=32'b00000000000000000000000000000011
+       lreset_pwidth=32'b00000000000000000000000000000011
+       lwait_b4_trst=32'b00000000000010111110101111000010
+       lwait_b4_trst_s=32'b00000000000000000000001100001101
+       lplol_cnt_width=32'b00000000000000000000000000010100
+       lwait_after_plol0=32'b00000000000000000000000000000100
+       lwait_b4_rrst=32'b00000000000000101100000000000000
+       lrrst_wait_width=32'b00000000000000000000000000010100
+       lwait_after_rrst=32'b00000000000011000011010100000000
+       lwait_b4_rrst_s=32'b00000000000000000000000111001100
+       lrlol_cnt_width=32'b00000000000000000000000000010011
+       lwait_after_lols=32'b00000000000000001100010000000000
+       lwait_after_lols_s=32'b00000000000000000000000010010110
+       llols_cnt_width=32'b00000000000000000000000000010010
+       lrdb_max=32'b00000000000000000000000000001111
+       ltxr_wait_width=32'b00000000000000000000000000001100
+       lrxr_wait_width=32'b00000000000000000000000000001100
+   Generated name = serdes_sync_1rsl_core_Z2_layer1
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":326:33:326:40|Object rrst_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":327:33:327:43|Removing wire rrst_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":328:33:328:41|Object rrst_wait is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":341:33:341:39|Object rxp_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":342:33:342:39|Object rxp_rst is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":343:33:343:42|Removing wire rxp_cnt_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":346:33:346:42|Object rlolsz_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":347:33:347:45|Removing wire rlolsz_cnt_tc, as there is no assignment to it.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":350:33:350:43|Removing wire rxp_cnt2_tc, as there is no assignment to it.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":351:33:351:47|Object data_loop_b_cnt is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG133 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":352:33:352:43|Object data_loop_b is declared but not assigned. Either assign a value or remove the declaration.
+@W: CG360 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":353:33:353:46|Removing wire data_loop_b_tc, as there is no assignment to it.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":806:3:806:8|Pruning unused register genblk2.rxp_cnt2[2:0]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlol_p3. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":567:3:567:8|Pruning unused register genblk2.rlos_p3. Make sure that there are no unused intermediate registers.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":694:3:694:8|Optimizing register bit genblk2.rxs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":461:3:461:8|Optimizing register bit genblk1.txp_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL190 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":422:3:422:8|Optimizing register bit genblk1.txs_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":422:3:422:8|Pruning register bit 2 of genblk1.txs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":461:3:461:8|Pruning register bit 2 of genblk1.txp_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL260 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":694:3:694:8|Pruning register bit 2 of genblk2.rxs_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":200:33:200:48|Input port bits 3 to 1 of rui_tx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":204:33:204:51|Input port bits 3 to 1 of rui_rx_serdes_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":205:33:205:48|Input port bits 3 to 1 of rui_rx_pcs_rst_c[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":206:33:206:48|Input port bits 3 to 1 of rdi_rx_los_low_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL246 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":207:33:207:48|Input port bits 3 to 1 of rdi_rx_cdr_lol_s[3:0] are unused. Assign logic for all port bits or change the input port size.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning register bits 8 to 7 of genblk5.rdiff_comp_unlock[8:6]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL279 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning register bits 5 to 3 of genblk5.rdiff_comp_lock[5:2]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rdiff_comp_unlock[6]. Make sure that there are no unused intermediate registers.
+@W: CL169 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1739:0:1739:5|Pruning unused register genblk5.rcount_tc[17]. Make sure that there are no unused intermediate registers.
+@N: CL201 :"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1801:0:1801:5|Trying to extract state machine for register sll_state.
+Extracted state machine for register sll_state
+State machine has 3 reachable states with original encodings of:
+   00
+   01
+   11

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.tlg.db b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.tlg.db
new file mode 100644 (file)
index 0000000..fb6e8bd
Binary files /dev/null and b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/layer1.tlg.db differ

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/modulechange.db b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/modulechange.db
new file mode 100644 (file)
index 0000000..ecb6053
Binary files /dev/null and b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/modulechange.db differ

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/modulechange_mixhdl/layer0/modulechange.db b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/modulechange_mixhdl/layer0/modulechange.db
new file mode 100644 (file)
index 0000000..40d228d
Binary files /dev/null and b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/modulechange_mixhdl/layer0/modulechange.db differ

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/modulechange_mixhdl/layer1/modulechange.db b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/modulechange_mixhdl/layer1/modulechange.db
new file mode 100644 (file)
index 0000000..bec0f3d
Binary files /dev/null and b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/modulechange_mixhdl/layer1/modulechange.db differ

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.fdep b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.fdep
new file mode 100644 (file)
index 0000000..ad612f4
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.fdep
@@ -0,0 +1,37 @@
+#OPTIONS:"|-mixedhdl|-top|serdes_sync_1|-layerid|0|-orig_srs|/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_vhdl":1542167766
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/location.map":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/snps_haps_pkg.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/std1164.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/numeric.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/umr_capim.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/arith.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/unsigned.vhd":1542167610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vhd/hyperents.vhd":1542167610
+#CUR:"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd":1557476609
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.vhd":1542167599
+#OPTIONS:"|-mixedhdl|-modhint|/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/_verilog_hintfile|-top|work.serdes_sync_1sll_core|-top|work.serdes_sync_1rsl_core|-mpparams|/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/_mh_params|-layerid|1|-orig_srs|/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.srs|-prodtype|synplify_pro|-dspmac|-fixsmult|-infer_seqShift|-nram|-sdff_counter|-divnmod|-nostructver|-I|/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/|-I|/home/soft/lattice/diamond/3.10_x64/synpbase/lib|-v2001|-devicelib|/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v|-devicelib|/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-lib|work"
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/linux_a_64/c_ver":1542167761
+#CUR:"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/_verilog_hintfile":1557476610
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v":1542167595
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/lucent/pmi_def.v":1542167597
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/hypermods.v":1542167630
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/umr_capim.v":1542167630
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_objects.v":1542167630
+#CUR:"/home/soft/lattice/diamond/3.10_x64/synpbase/lib/vlog/scemi_pipes.svh":1542167630
+#CUR:"/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v":1557476609
+0                      "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd" vhdl
+1                      "/home/adrian/git/trb5sc/template/project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v" verilog
+#Dependency Lists(Uses List)
+0 1
+1 -1
+#Dependency Lists(Users Of)
+0 -1
+1 0
+#Design Unit to File Association
+module work serdes_sync_1sll_core 1
+module work sync 1
+module work serdes_sync_1rsl_core 1
+module work serdes_sync_1 0
+arch work serdes_sync_1 v1 0

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.linkerlog b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.linkerlog
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.srs b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.srs
new file mode 100644 (file)
index 0000000..6cc931d
Binary files /dev/null and b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_comp.srs differ

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_m.srm b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_m.srm
new file mode 100644 (file)
index 0000000..75dd84e
Binary files /dev/null and b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_m.srm differ

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_m_srm/1.srm b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_m_srm/1.srm
new file mode 100644 (file)
index 0000000..f71b526
Binary files /dev/null and b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_m_srm/1.srm differ

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_m_srm/fileinfo.srm b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_m_srm/fileinfo.srm
new file mode 100644 (file)
index 0000000..3862103
Binary files /dev/null and b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_m_srm/fileinfo.srm differ

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_mult.srs b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_mult.srs
new file mode 100644 (file)
index 0000000..4da2ca9
Binary files /dev/null and b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_mult.srs differ

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_mult_srs/1.srs b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_mult_srs/1.srs
new file mode 100644 (file)
index 0000000..5077130
Binary files /dev/null and b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_mult_srs/1.srs differ

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_mult_srs/fileinfo.srs b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_mult_srs/fileinfo.srs
new file mode 100644 (file)
index 0000000..cb42455
Binary files /dev/null and b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_mult_srs/fileinfo.srs differ

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_mult_srs/skeleton.srs b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_mult_srs/skeleton.srs
new file mode 100644 (file)
index 0000000..9e03e8c
Binary files /dev/null and b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_mult_srs/skeleton.srs differ

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_prem.fse b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_prem.fse
new file mode 100644 (file)
index 0000000..f4aa273
--- /dev/null
+++ b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_prem.fse
@@ -0,0 +1,10 @@
+
+fsm_encoding {61801018011} sequential
+
+fsm_state_encoding {61801018011} LPLL_LOSS_ST {00}
+
+fsm_state_encoding {61801018011} LPLL_PRELOSS_ST {01}
+
+fsm_state_encoding {61801018011} LPLL_LOCK_ST {10}
+
+fsm_registers {61801018011} {sll_state[1]}  {sll_state[0]} 

diff --git a/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_prem.srd b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_prem.srd
new file mode 100644 (file)
index 0000000..13e868b
Binary files /dev/null and b/gbe/cores/test_sfp/serdes_sync_0/serdes_sync_1/syn_results/synwork/serdes_sync_1_prem.srd differ

diff --git a/gbe/trb5sc_gbe.prj b/gbe/trb5sc_gbe.prj
index 7559ba8da2ad350704cdc79eb3d7e923dfdc28af..c9745c95aca629f69cbf1335fd6f6e8d168b8b9c 100644 (file)
--- a/gbe/trb5sc_gbe.prj
+++ b/gbe/trb5sc_gbe.prj
@@ -63,7 +63,7 @@ add_file -vhdl -lib work "tdc_release/tdc_version.vhd"
 
 #Basic Infrastructure
 add_file -vhdl -lib work "../../dirich/cores/pll_240_100/pll_240_100.vhd"
-#add_file -vhdl -lib work "./project/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd"
+#add_file -vhdl -lib work "./cores/pll_200_200_125_100/pll_200_125_100/pll_200_125_100.vhd"
 add_file -vhdl -lib work "../../dirich/code/clock_reset_handler.vhd"
 add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd"
@@ -142,8 +142,8 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd"
 #channel 1, SFP
 add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd"
 add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v"
-add_file -vhdl -lib work "./project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd"
-add_file -verilog -lib work "./project/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v"
+add_file -vhdl -lib work "./cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1.vhd"
+add_file -verilog -lib work "./cores/test_sfp/serdes_sync_0/serdes_sync_1/serdes_sync_1_softlogic.v"
 
 add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs2.vhd"
@@ -216,7 +216,7 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_
 add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_KillPing.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/media/ecp5/sgmii_ecp5_txpllLoLdeleted.vhd"  
-#add_file -vhdl -lib work "./project/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd" #200MHz
+#add_file -vhdl -lib work "./cores/test_gbepcs/sgmii_ecp5/sgmii_ecp5.vhd" #200MHz
 add_file -vhdl -lib work "../../trbnet/gbe_trb/media/serdes_gbe_4ch.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/media/ecp5/pcs_sync_reset.vhd"
 #add_file -vhdl -lib work "../../trbnet/gbe_trb/media/ecp5/test/sgmii_channel_smi_core.vhd"
@@ -227,14 +227,14 @@ add_file -verilog -lib work "../../trbnet/gbe_trb/media/reset_controller_cdr.v"
 add_file -verilog -lib work "../../trbnet/gbe_trb/media/register_interface_hb.v"
 add_file -verilog -lib work "../../trbnet/gbe_trb/media/rate_resolution.v"
 add_file -verilog -lib work "../../trbnet/gbe_trb/media/ecp5/sgmii_ecp5_softlogic.v"  
-#add_file -verilog -lib work "./project/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v"#200MHz
+#add_file -verilog -lib work "./cores/test_gbepcs/sgmii_ecp5/sgmii_ecp5_softlogic.v"#200MHz
 #add_file -verilog -lib work "../../trbnet/gbe_trb/media/ecp5/tsmac35.v"
 #add_file -vhdl -lib work "/opt/lattice/diamond/3.10_x64/cae_library/synthesis/vhdl/ecp5um.vhd"
 
 #GbE ExtRefClk
-#add_file -vhdl -lib work "./project/GbePcsExtrefclk/GbePcsExtrefclk.vhd"
-#add_file -vhdl -lib work "./project/GbePcsExtrefclk/extref/extref.vhd"
-#add_file -vhdl -lib work "./project/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd"
+#add_file -vhdl -lib work "./cores/GbePcsExtrefclk/GbePcsExtrefclk.vhd"
+#add_file -vhdl -lib work "./cores/GbePcsExtrefclk/extref/extref.vhd"
+#add_file -vhdl -lib work "./cores/GbePcsExtrefclk/sgmii_ecp5/sgmii_ecp5.vhd"
 #END GbE ExtRefClk
 
 add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9.vhd"
@@ -301,7 +301,7 @@ add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x32_OutReg/FIFO_
 add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in125_out33/pll_in125_out33.vhd"
 #add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.vhd"
 
-add_file -vhdl -lib work "./project/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd"
+add_file -vhdl -lib work "./cores/sgmii/pll_in125_out125_out33/pll_in125_out125_out33.vhd"
 
 add_file -vhdl -lib work "./trb5sc_gbe.vhd"
 #add_file -fpga_constraint "./synplify.fdc"