clock cleanup, only one clock left

diff --git a/gbe_trb/base/gbe_logic_wrapper.vhd b/gbe_trb/base/gbe_logic_wrapper.vhd
index dc73c2ac69340fc213f61deb9ec5c8225f42b47f..cfd24f827c2e24cc7e8dcd8197572ce9c102f433 100644 (file)
--- a/gbe_trb/base/gbe_logic_wrapper.vhd
+++ b/gbe_trb/base/gbe_logic_wrapper.vhd
@@ -22,9 +22,7 @@ entity gbe_logic_wrapper is
     SLOWCTRL_BUFFER_SIZE      : integer range 1 to 4        := 1
   );
   port(
-    CLK_SYS_IN               : in  std_logic;
     CLK_125_IN               : in  std_logic;
-    CLK_RX_125_IN            : in  std_logic; -- DO NOT USE
     RESET                    : in  std_logic;
     GSR_N                    : in  std_logic;
     MY_MAC_IN                : in  std_logic_vector(47 downto 0);
@@ -250,12 +248,12 @@ architecture RTL of gbe_logic_wrapper is
 
 begin
 
-  reset_sync : process(GSR_N, CLK_SYS_IN)
+  reset_sync : process(GSR_N, CLK_125_IN)
   begin
     if (GSR_N = '0') then
       ff    <= '0';
       rst_n <= '0';
-    elsif rising_edge(CLK_SYS_IN) then
+    elsif rising_edge(CLK_125_IN) then
       ff    <= '1';
       rst_n <= ff;
     end if;

diff --git a/gbe_trb_ecp3/base/gbe_wrapper_fifo.vhd b/gbe_trb_ecp3/base/gbe_wrapper_fifo.vhd
index 45eb39fba1a776d791853c156abf933ec53994cd..abd6fd7464c2896a104f308a75d3956b477f15d7 100644 (file)
--- a/gbe_trb_ecp3/base/gbe_wrapper_fifo.vhd
+++ b/gbe_trb_ecp3/base/gbe_wrapper_fifo.vhd
@@ -13,18 +13,7 @@ use work.trb_net_gbe_protocols.all;
 
 entity gbe_wrapper_fifo is
   generic(
-    DO_SIMULATION             : integer range 0 to 1         := 0;
-    INCLUDE_DEBUG             : integer range 0 to 1         := 0;
-    USE_INTERNAL_TRBNET_DUMMY : integer range 0 to 1         := 0; -- only for debugging
-    USE_EXTERNAL_TRBNET_DUMMY : integer range 0 to 1         := 0; -- only for debugging
-    RX_PATH_ENABLE            : integer range 0 to 1         := 1; -- 
-    FIXED_SIZE_MODE           : integer range 0 to 1         := 1; -- only for debugging
-    INCREMENTAL_MODE          : integer range 0 to 1         := 0; -- only for debugging
-    FIXED_SIZE                : integer range 0 to 65535     := 10; -- only for debugging
-    FIXED_DELAY_MODE          : integer range 0 to 1         := 1; -- only for debugging
-    UP_DOWN_MODE              : integer range 0 to 1         := 0; -- only for debugging
-    UP_DOWN_LIMIT             : integer range 0 to 16777215  := 0; -- only for debugging
-    FIXED_DELAY               : integer range 0 to 16777215  := 16777215; -- only for debugging
+    LINK_HAS_READOUT          : std_logic                    := '1';
     LINK_HAS_PING             : std_logic                    := '1';
     LINK_HAS_ARP              : std_logic                    := '1';
     LINK_HAS_DHCP             : std_logic                    := '1';
@@ -33,7 +22,6 @@ entity gbe_wrapper_fifo is
     LINK_HAS_FWD              : std_logic                    := '1'
   );
   port(
-    CLK_SYS_IN                : in  std_logic;
     CLK_125_IN                : in  std_logic;
     RESET                     : in  std_logic;
     GSR_N                     : in  std_logic;
@@ -192,36 +180,36 @@ architecture RTL of gbe_wrapper_fifo is
   signal sum_tx_packets             : std_logic_vector(31 downto 0);
   signal sum_dropped                : std_logic_vector(31 downto 0);
 
-  signal busip0                                               : CTRLBUS_TX;
+  signal busip0                     : CTRLBUS_TX;
 
-  signal dummy_event                                        : std_logic_vector(15 downto 0);
-  signal dummy_mode                                         : std_logic;
-  signal make_reset0                                        : std_logic := '0';
-  signal monitor_gen_dbg                                    : std_logic_vector(c_MAX_PROTOCOLS * 64 - 1 downto 0);
+  signal dummy_event                : std_logic_vector(15 downto 0);
+  signal dummy_mode                 : std_logic;
+  signal make_reset0                : std_logic := '0';
+  signal monitor_gen_dbg            : std_logic_vector(c_MAX_PROTOCOLS * 64 - 1 downto 0);
 
-  signal cfg_autothrottle   : std_logic;
-  signal cfg_throttle_pause : std_logic_vector(15 downto 0);
-  
-  signal issue_reboot : std_logic;
-  signal my_ip        : std_logic_vector(127 downto 0);
-  signal debug        : std_logic_vector(127 downto 0);
+  signal cfg_autothrottle           : std_logic;
+  signal cfg_throttle_pause         : std_logic_vector(15 downto 0);
   
-  signal frame_active     : std_Logic;
-  signal frame_written    : std_logic;
-  signal rx_fifo_wr       : std_logic;
-  signal frame_requested  : std_logic;
-  signal fifo_empty       : std_logic;
-  signal fifo_data        : std_logic_vector(8 downto 0);
-  signal tx_data_read     : std_Logic;
-  signal normal_read_ack  : std_logic;
-  signal empty_read_ack   : std_Logic;
-  signal fifo_wr_int      : std_logic;
-  signal sof_int          : std_logic;
-  signal tx_done_int      : std_logic_vector(7 downto 0);
+  signal issue_reboot               : std_logic;
+  signal my_ip                      : std_logic_vector(127 downto 0);
+  signal debug                      : std_logic_vector(127 downto 0);
   
-  signal ft_tx_data       : std_logic_vector(8 downto 0);
-  signal ft_tx_wr         : std_logic;
-  signal ft_tx_fifofull   : std_logic;
+  signal frame_active               : std_Logic;
+  signal frame_written              : std_logic;
+  signal rx_fifo_wr                 : std_logic;
+  signal frame_requested            : std_logic;
+  signal fifo_empty                 : std_logic;
+  signal fifo_data                  : std_logic_vector(8 downto 0);
+  signal tx_data_read               : std_Logic;
+  signal normal_read_ack            : std_logic;
+  signal empty_read_ack             : std_Logic;
+  signal fifo_wr_int                : std_logic;
+  signal sof_int                    : std_logic;
+  signal tx_done_int                : std_logic_vector(7 downto 0);
+                                    
+  signal ft_tx_data                 : std_logic_vector(8 downto 0);
+  signal ft_tx_wr                   : std_logic;
+  signal ft_tx_fifofull             : std_logic;
   
 begin
 
@@ -290,19 +278,17 @@ begin
   
   gbe_inst : entity work.gbe_logic_wrapper
   generic map(
-    INCLUDE_READOUT           => LINK_HAS_READOUT,
-    INCLUDE_SLOWCTRL          => LINK_HAS_SLOWCTRL,
-    INCLUDE_DHCP              => LINK_HAS_DHCP,
-    INCLUDE_ARP               => LINK_HAS_ARP,
-    INCLUDE_PING              => LINK_HAS_PING,
-    INCLUDE_FWD               => LINK_HAS_FWD,
-    READOUT_BUFFER_SIZE       => 4,
-    SLOWCTRL_BUFFER_SIZE      => 2
+    INCLUDE_READOUT          => LINK_HAS_READOUT,
+    INCLUDE_SLOWCTRL         => LINK_HAS_SLOWCTRL,
+    INCLUDE_DHCP             => LINK_HAS_DHCP,
+    INCLUDE_ARP              => LINK_HAS_ARP,
+    INCLUDE_PING             => LINK_HAS_PING,
+    INCLUDE_FWD              => LINK_HAS_FWD,
+    READOUT_BUFFER_SIZE      => 4,
+    SLOWCTRL_BUFFER_SIZE     => 2
   )
   port map(
-    CLK_SYS_IN               => CLK_SYS_IN,
     CLK_125_IN               => CLK_125_IN,
-    CLK_RX_125_IN            => CLK_125_IN,
     RESET                    => RESET,
     GSR_N                    => GSR_N,
     MY_MAC_IN                => mac_0,
@@ -408,19 +394,19 @@ begin
     MAKE_RESET_OUT           => make_reset0
   );
 
-  BUS_IP_TX.ack  <= busip0.ack  when rising_edge(CLK_SYS_IN);
-  BUS_IP_TX.nack <= busip0.nack when rising_edge(CLK_SYS_IN);
-  BUS_IP_TX.data <= busip0.data when rising_edge(CLK_SYS_IN);
+  BUS_IP_TX.ack  <= busip0.ack  when rising_edge(CLK_125_IN);
+  BUS_IP_TX.nack <= busip0.nack when rising_edge(CLK_125_IN);
+  BUS_IP_TX.data <= busip0.data when rising_edge(CLK_125_IN);
 
   ipu_mult : entity work.gbe_ipu_multiplexer
     generic map(
-      DO_SIMULATION       => DO_SIMULATION,
-      INCLUDE_DEBUG       => INCLUDE_DEBUG,
+      DO_SIMULATION       => 0,
+      INCLUDE_DEBUG       => 0,
       LINK_HAS_READOUT    => "000" & LINK_HAS_READOUT,
       NUMBER_OF_GBE_LINKS => 1
     )
     port map(
-      CLK_SYS_IN                  => CLK_SYS_IN,
+      CLK_SYS_IN                  => CLK_125_IN,
       RESET                       => RESET,
       CTS_NUMBER_IN               => CTS_NUMBER_IN,
       CTS_CODE_IN                 => CTS_CODE_IN,
@@ -459,7 +445,7 @@ begin
 
   SETUP : gbe_setup
   port map(
-    CLK                          => CLK_SYS_IN,
+    CLK                          => CLK_125_IN,
     RESET                        => RESET,
     -- interface to regio bus
     BUS_ADDR_IN                  => BUS_REG_RX.addr(7 downto 0),