\r
signal sync_q : std_logic_vector((DEPTH+1)*WIDTH-1 downto 0);\r
\r
+ attribute syn_preserve : boolean;\r
+ attribute syn_keep : boolean;\r
+ attribute syn_keep of sync_q : signal is true;\r
+ attribute syn_preserve of sync_q : signal is true;\r
+\r
+\r
begin\r
sync_q(WIDTH-1 downto 0) <= D_IN;\r
D_OUT <= sync_q((DEPTH+1)*WIDTH-1 downto DEPTH*WIDTH);\r
attribute syn_keep : boolean;
+ attribute syn_preserve : boolean;
+
attribute syn_keep of led_counter : signal is true;
+ attribute syn_preserve of led_counter : signal is true;
+ attribute syn_keep of byte_waiting : signal is true;
+ attribute syn_preserve of byte_waiting : signal is true;
+
begin
gen_normal_serdes : if REVERSE_ORDER = c_NO generate
\r
entity spi_databus_memory is\r
port(\r
- CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
-- Slave bus\r
- BUS_ADDR_IN : in std_logic_vector(5 downto 0);\r
- BUS_READ_IN : in std_logic;\r
- BUS_WRITE_IN : in std_logic;\r
+ BUS_ADDR_IN : in std_logic_vector(5 downto 0);\r
+ BUS_READ_IN : in std_logic;\r
+ BUS_WRITE_IN : in std_logic;\r
BUS_ACK_OUT : out std_logic;\r
- BUS_DATA_IN : in std_logic_vector(31 downto 0);\r
+ BUS_DATA_IN : in std_logic_vector(31 downto 0);\r
BUS_DATA_OUT : out std_logic_vector(31 downto 0);\r
-- state machine connections\r
- BRAM_ADDR_IN : in std_logic_vector(7 downto 0);\r
+ BRAM_ADDR_IN : in std_logic_vector(7 downto 0);\r
BRAM_WR_D_OUT : out std_logic_vector(7 downto 0);\r
- BRAM_RD_D_IN : in std_logic_vector(7 downto 0);\r
- BRAM_WE_IN : in std_logic;\r
+ BRAM_RD_D_IN : in std_logic_vector(7 downto 0);\r
+ BRAM_WE_IN : in std_logic;\r
-- Status lines\r
STAT : out std_logic_vector(63 downto 0) -- DEBUG\r
);\r
\r
architecture Behavioral of spi_databus_memory is\r
\r
-\r
-- Signals\r
type STATES is (SLEEP,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);\r
signal CURRENT_STATE, NEXT_STATE: STATES;\r
\r
-- slave bus signals\r
- signal BUS_ack_x : std_logic;\r
- signal BUS_ack : std_logic;\r
- signal store_wr_x : std_logic;\r
- signal store_wr : std_logic;\r
- signal store_rd_x : std_logic;\r
- signal store_rd : std_logic;\r
-\r
- signal wr_addr : std_logic_vector(6 downto 0); -- some bits are masked\r
- signal wr_data : std_logic_vector(15 downto 0);\r
- signal wr_we : std_logic;\r
- signal buf_BUS_data_out : std_logic_vector(31 downto 0);\r
-\r
- signal onewire_bsm : std_logic_vector(7 downto 0);\r
+ signal bus_ack_x : std_logic;\r
+ signal bus_ack : std_logic;\r
+ signal store_wr_x : std_logic;\r
+ signal store_wr : std_logic;\r
+ signal store_rd_x : std_logic;\r
+ signal store_rd : std_logic;\r
+ signal buf_bus_data_out : std_logic_vector(31 downto 0);\r
\r
begin\r
\r
\r
entity spi_master is\r
port(\r
- CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
-- Slave bus\r
- BUS_READ_IN : in std_logic;\r
- BUS_WRITE_IN : in std_logic;\r
- BUS_BUSY_OUT : out std_logic;\r
- BUS_ACK_OUT : out std_logic;\r
- BUS_ADDR_IN : in std_logic_vector(0 downto 0);\r
- BUS_DATA_IN : in std_logic_vector(31 downto 0);\r
- BUS_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ BUS_READ_IN : in std_logic;\r
+ BUS_WRITE_IN : in std_logic;\r
+ BUS_BUSY_OUT : out std_logic;\r
+ BUS_ACK_OUT : out std_logic;\r
+ BUS_ADDR_IN : in std_logic_vector(0 downto 0);\r
+ BUS_DATA_IN : in std_logic_vector(31 downto 0);\r
+ BUS_DATA_OUT : out std_logic_vector(31 downto 0);\r
-- SPI connections\r
- SPI_CS_OUT : out std_logic;\r
- SPI_SDI_IN : in std_logic;\r
- SPI_SDO_OUT : out std_logic;\r
- SPI_SCK_OUT : out std_logic;\r
+ SPI_CS_OUT : out std_logic;\r
+ SPI_SDI_IN : in std_logic;\r
+ SPI_SDO_OUT : out std_logic;\r
+ SPI_SCK_OUT : out std_logic;\r
-- BRAM for read/write data\r
- BRAM_A_OUT : out std_logic_vector(7 downto 0);\r
- BRAM_WR_D_IN : in std_logic_vector(7 downto 0);\r
- BRAM_RD_D_OUT : out std_logic_vector(7 downto 0);\r
- BRAM_WE_OUT : out std_logic;\r
+ BRAM_A_OUT : out std_logic_vector(7 downto 0);\r
+ BRAM_WR_D_IN : in std_logic_vector(7 downto 0);\r
+ BRAM_RD_D_OUT : out std_logic_vector(7 downto 0);\r
+ BRAM_WE_OUT : out std_logic;\r
-- Status lines\r
- STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
+ STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
);\r
end entity;\r
\r
type STATES is (SLEEP,RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);\r
signal CURRENT_STATE, NEXT_STATE: STATES;\r
\r
- signal status_data : std_logic_vector(31 downto 0);\r
- signal spi_busy : std_logic;\r
+ signal status_data : std_logic_vector(31 downto 0);\r
+ signal spi_busy : std_logic;\r
\r
signal reg_ctrl_data : std_logic_vector(31 downto 0); -- CMD, ADH, ADM, ADL\r
- signal reg_status_data : std_logic_vector(31 downto 0); -- MAX\r
+ signal reg_status_data : std_logic_vector(31 downto 0); -- MAX\r
\r
- signal reg_BUS_data_out : std_logic_vector(31 downto 0); -- readback\r
+ signal reg_bus_data_out : std_logic_vector(31 downto 0); -- readback\r
\r
- signal spi_bsm : std_logic_vector(7 downto 0);\r
+ signal spi_bsm : std_logic_vector(7 downto 0);\r
+ signal spi_debug : std_logic_vector(31 downto 0);\r
\r
- signal spi_start_x : std_logic;\r
+ signal spi_start_x : std_logic;\r
signal spi_start : std_logic;\r
\r
-- State machine signals\r
- signal BUS_busy_x : std_logic;\r
- signal BUS_busy : std_logic;\r
- signal BUS_ack_x : std_logic;\r
- signal BUS_ack : std_logic;\r
- signal store_wr_x : std_logic;\r
- signal store_wr : std_logic;\r
- signal store_rd_x : std_logic;\r
- signal store_rd : std_logic;\r
+ signal bus_busy_x : std_logic;\r
+ signal bus_busy : std_logic;\r
+ signal bus_ack_x : std_logic;\r
+ signal bus_ack : std_logic;\r
+ signal store_wr_x : std_logic;\r
+ signal store_wr : std_logic;\r
+ signal store_rd_x : std_logic;\r
+ signal store_rd : std_logic;\r
\r
begin\r
\r
---------------------------------------------------------\r
\r
THE_SPI_SLIM: spi_slim\r
- port map(\r
- SYSCLK => clk_in,\r
- RESET => reset_in,\r
- -- Command interface\r
- START_IN => spi_start, -- not really nice, but should work\r
- BUSY_OUT => spi_busy,\r
- CMD_IN => reg_ctrl_data(31 downto 24),\r
- ADH_IN => reg_ctrl_data(23 downto 16),\r
- ADM_IN => reg_ctrl_data(15 downto 8),\r
- ADL_IN => reg_ctrl_data(7 downto 0),\r
- MAX_IN => reg_status_data(31 downto 24),\r
- TXDATA_IN => bram_wr_d_in,\r
- TX_RD_OUT => open, -- not needed\r
- RXDATA_OUT => bram_rd_d_out,\r
- RX_WR_OUT => bram_we_out,\r
- TX_RX_A_OUT => bram_a_out,\r
- -- SPI interface\r
- SPI_SCK_OUT => spi_sck_out,\r
- SPI_CS_OUT => spi_cs_out,\r
- SPI_SDI_IN => spi_sdi_in,\r
- SPI_SDO_OUT => spi_sdo_out,\r
- -- DEBUG\r
- CLK_EN_OUT => open, -- not needed\r
- BSM_OUT => spi_bsm,\r
- DEBUG_OUT => open -- BUG\r
- );\r
+port map(\r
+ SYSCLK => clk_in,\r
+ RESET => reset_in,\r
+ -- Command interface\r
+ START_IN => spi_start, -- not really nice, but should work\r
+ BUSY_OUT => spi_busy,\r
+ CMD_IN => reg_ctrl_data(31 downto 24),\r
+ ADH_IN => reg_ctrl_data(23 downto 16),\r
+ ADM_IN => reg_ctrl_data(15 downto 8),\r
+ ADL_IN => reg_ctrl_data(7 downto 0),\r
+ MAX_IN => reg_status_data(31 downto 24),\r
+ TXDATA_IN => bram_wr_d_in,\r
+ TX_RD_OUT => open, -- not needed\r
+ RXDATA_OUT => bram_rd_d_out,\r
+ RX_WR_OUT => bram_we_out,\r
+ TX_RX_A_OUT => bram_a_out,\r
+ -- SPI interface\r
+ SPI_SCK_OUT => spi_sck_out,\r
+ SPI_CS_OUT => spi_cs_out,\r
+ SPI_SDI_IN => spi_sdi_in,\r
+ SPI_SDO_OUT => spi_sdo_out,\r
+ -- DEBUG\r
+ CLK_EN_OUT => open, -- not needed\r
+ BSM_OUT => spi_bsm,\r
+ DEBUG_OUT => spi_debug --open -- BUG\r
+);\r
\r
---------------------------------------------------------\r
-- Statemachine --\r
---------------------------------------------------------\r
- STATE_MEM: process( clk_in )\r
- begin\r
- if( rising_edge(clk_in) ) then\r
- if( reset_in = '1' ) then\r
- CURRENT_STATE <= SLEEP;\r
- BUS_busy <= '0';\r
- BUS_ack <= '0';\r
- store_wr <= '0';\r
- store_rd <= '0';\r
- else\r
- CURRENT_STATE <= NEXT_STATE;\r
- BUS_busy <= BUS_busy_x;\r
- BUS_ack <= BUS_ack_x;\r
- store_wr <= store_wr_x;\r
- store_rd <= store_rd_x;\r
- end if;\r
- end if;\r
- end process STATE_MEM;\r
-\r
- TRANSFORM: process(CURRENT_STATE, BUS_read_in, BUS_write_in, spi_busy )\r
- begin\r
- NEXT_STATE <= SLEEP;\r
- BUS_busy_x <= '0';\r
- BUS_ack_x <= '0';\r
- store_wr_x <= '0';\r
- store_rd_x <= '0';\r
- case CURRENT_STATE is\r
- when SLEEP =>\r
- if ( (spi_busy = '0') and (BUS_read_in = '1') ) then\r
- NEXT_STATE <= RD_RDY;\r
- store_rd_x <= '1';\r
- elsif( (spi_busy = '0') and (BUS_write_in = '1') ) then\r
- NEXT_STATE <= WR_RDY;\r
- store_wr_x <= '1';\r
- elsif( (spi_busy = '1') and (BUS_read_in = '1') ) then\r
- NEXT_STATE <= RD_BSY;\r
- BUS_busy_x <= '1';\r
- elsif( (spi_busy = '1') and (BUS_write_in = '1') ) then\r
- NEXT_STATE <= WR_BSY;\r
- BUS_busy_x <= '1';\r
- else\r
- NEXT_STATE <= SLEEP;\r
- end if;\r
- when RD_RDY =>\r
+STATE_MEM: process( clk_in )\r
+begin\r
+ if( rising_edge(clk_in) ) then\r
+ if( reset_in = '1' ) then\r
+ CURRENT_STATE <= SLEEP;\r
+ bus_busy <= '0';\r
+ bus_ack <= '0';\r
+ store_wr <= '0';\r
+ store_rd <= '0';\r
+ else\r
+ CURRENT_STATE <= NEXT_STATE;\r
+ bus_busy <= bus_busy_x;\r
+ bus_ack <= bus_ack_x;\r
+ store_wr <= store_wr_x;\r
+ store_rd <= store_rd_x;\r
+ end if;\r
+ end if;\r
+end process STATE_MEM;\r
+\r
+TRANSFORM: process(CURRENT_STATE, bus_read_in, bus_write_in, spi_busy, bus_addr_in )\r
+begin\r
+ NEXT_STATE <= SLEEP;\r
+ bus_busy_x <= '0';\r
+ bus_ack_x <= '0';\r
+ store_wr_x <= '0';\r
+ store_rd_x <= '0';\r
+ case CURRENT_STATE is\r
+ when SLEEP =>\r
+ if ( (spi_busy = '0') and (bus_read_in = '1') ) then\r
+ NEXT_STATE <= RD_RDY;\r
+ store_rd_x <= '1';\r
+ elsif( (spi_busy = '0') and (bus_write_in = '1') ) then\r
+ NEXT_STATE <= WR_RDY;\r
+ store_wr_x <= '1';\r
+ elsif( (bus_addr_in(0) = '0') and (spi_busy = '1') and (bus_read_in = '1') ) then\r
+ NEXT_STATE <= RD_BSY; -- CMD register is busy protected\r
+ bus_busy_x <= '1';\r
+ elsif( (bus_addr_in(0) = '0') and (spi_busy = '1') and (bus_write_in = '1') ) then\r
+ NEXT_STATE <= WR_BSY; -- CMD register is busy protected\r
+ bus_busy_x <= '1';\r
+ elsif( (bus_addr_in(0) = '1') and (spi_busy = '1') and (bus_read_in = '1') ) then\r
+ NEXT_STATE <= RD_RDY; -- STATUS register is not\r
+ store_rd_x <= '1';\r
+ elsif( (bus_addr_in(0) = '1') and (spi_busy = '1') and (bus_write_in = '1') ) then\r
+ NEXT_STATE <= WR_RDY; -- STATUS register is not\r
+ store_wr_x <= '1';\r
+ else\r
+ NEXT_STATE <= SLEEP;\r
+ end if;\r
+ when RD_RDY =>\r
+ NEXT_STATE <= RD_ACK;\r
+ bus_ack_x <= '1';\r
+ when WR_RDY =>\r
+ NEXT_STATE <= WR_ACK;\r
+ bus_ack_x <= '1';\r
+ when RD_ACK =>\r
+ if( bus_read_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ else\r
NEXT_STATE <= RD_ACK;\r
- BUS_ack_x <= '1';\r
- when WR_RDY =>\r
+ bus_ack_x <= '1';\r
+ end if;\r
+ when WR_ACK =>\r
+ if( bus_write_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ else\r
NEXT_STATE <= WR_ACK;\r
- BUS_ack_x <= '1';\r
- when RD_ACK =>\r
- if( BUS_read_in = '0' ) then\r
- NEXT_STATE <= DONE;\r
- else\r
- NEXT_STATE <= RD_ACK;\r
- BUS_ack_x <= '1';\r
- end if;\r
- when WR_ACK =>\r
- if( BUS_write_in = '0' ) then\r
- NEXT_STATE <= DONE;\r
- else\r
- NEXT_STATE <= WR_ACK;\r
- BUS_ack_x <= '1';\r
- end if;\r
- when RD_BSY =>\r
- if( BUS_read_in = '0' ) then\r
- NEXT_STATE <= DONE;\r
- else\r
- NEXT_STATE <= RD_BSY;\r
- BUS_busy_x <= '1';\r
- end if;\r
- when WR_BSY =>\r
- if( BUS_write_in = '0' ) then\r
- NEXT_STATE <= DONE;\r
- else\r
- NEXT_STATE <= WR_BSY;\r
- BUS_busy_x <= '1';\r
- end if;\r
- when DONE =>\r
- NEXT_STATE <= SLEEP;\r
+ bus_ack_x <= '1';\r
+ end if;\r
+ when RD_BSY =>\r
+ if( bus_read_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ else\r
+ NEXT_STATE <= RD_BSY;\r
+ bus_busy_x <= '1';\r
+ end if;\r
+ when WR_BSY =>\r
+ if( bus_write_in = '0' ) then\r
+ NEXT_STATE <= DONE;\r
+ else\r
+ NEXT_STATE <= WR_BSY;\r
+ bus_busy_x <= '1';\r
+ end if;\r
+ when DONE =>\r
+ NEXT_STATE <= SLEEP;\r
\r
- when others =>\r
- NEXT_STATE <= SLEEP;\r
- end case;\r
- end process TRANSFORM;\r
+ when others =>\r
+ NEXT_STATE <= SLEEP;\r
+ end case;\r
+end process TRANSFORM;\r
\r
---------------------------------------------------------\r
-- data handling --\r
reg_ctrl_data <= (others => '0');\r
reg_status_data <= (others => '0');\r
spi_start <= '0';\r
- elsif( (store_wr = '1') and (BUS_addr_in(0) = '0') ) then\r
- reg_ctrl_data <= BUS_data_in;\r
- elsif( (store_wr = '1') and (BUS_addr_in(0) = '1') ) then\r
- reg_status_data <= BUS_data_in;\r
+ elsif( (store_wr = '1') and (bus_addr_in(0) = '0') ) then\r
+ reg_ctrl_data <= bus_data_in;\r
+ spi_start <= spi_start_x;\r
+ elsif( (store_wr = '1') and (bus_addr_in(0) = '1') ) then\r
+ reg_status_data <= bus_data_in;\r
+ spi_start <= spi_start_x;\r
+ else\r
+ spi_start <= spi_start_x;\r
end if;\r
- spi_start <= spi_start_x;\r
end if;\r
end process THE_WRITE_REG_PROC;\r
\r
-spi_start_x <= '1' when ( (store_wr = '1') and (BUS_addr_in(0) = '0') ) else '0';\r
+spi_start_x <= '1' when ( (store_wr = '1') and (bus_addr_in(0) = '0') ) else '0';\r
\r
-- register read\r
THE_READ_REG_PROC: process( clk_in )\r
begin\r
if( rising_edge(clk_in) ) then\r
if ( reset_in = '1' ) then\r
- reg_BUS_data_out <= (others => '0');\r
- elsif( (store_rd = '1') and (BUS_addr_in(0) = '0') ) then\r
- reg_BUS_data_out <= reg_ctrl_data;\r
- elsif( (store_rd = '1') and (BUS_addr_in(0) = '1') ) then\r
- reg_BUS_data_out(31 downto 24) <= reg_status_data(31 downto 24);\r
- reg_BUS_data_out(23 downto 16) <= x"00";\r
- reg_BUS_data_out(15 downto 8) <= x"00";\r
- reg_BUS_data_out(7 downto 0) <= spi_bsm;\r
+ reg_bus_data_out <= (others => '0');\r
+ elsif( (store_rd = '1') and (bus_addr_in(0) = '0') ) then\r
+ reg_bus_data_out <= reg_ctrl_data;\r
+ elsif( (store_rd = '1') and (bus_addr_in(0) = '1') ) then\r
+ reg_bus_data_out(31 downto 24) <= reg_status_data(31 downto 24);\r
+ reg_bus_data_out(23 downto 16) <= x"00";\r
+ reg_bus_data_out(15 downto 8) <= x"00";\r
+ reg_bus_data_out(7 downto 0) <= spi_bsm;\r
end if;\r
end if;\r
end process THE_READ_REG_PROC;\r
status_data(22 downto 0) <= (others => '0');\r
\r
-- output signals\r
-BUS_ack_out <= BUS_ack;\r
-BUS_busy_out <= BUS_busy;\r
-BUS_data_out <= reg_BUS_data_out;\r
-stat <= status_data;\r
+bus_ack_out <= bus_ack;\r
+bus_busy_out <= bus_busy;\r
+bus_data_out <= reg_bus_data_out;\r
+stat(31 downto 3) <= spi_debug(31 downto 3); --status_data;\r
+stat(2) <= spi_start;\r
+stat(1) <= bus_write_in;\r
+stat(0) <= bus_read_in;\r
\r
end Behavioral;\r
RESET : in std_logic; -- synchronous reset\r
-- Command interface\r
START_IN : in std_logic; -- one start pulse\r
- BUSY_OUT : out std_logic; -- SPI transactions are ongoing\r
+ BUSY_OUT : out std_logic; -- SPI transactions are ongoing\r
CMD_IN : in std_logic_vector(7 downto 0); -- SPI command byte\r
ADL_IN : in std_logic_vector(7 downto 0); -- low address byte\r
ADM_IN : in std_logic_vector(7 downto 0); -- mid address byte\r
ADH_IN : in std_logic_vector(7 downto 0); -- high address byte\r
MAX_IN : in std_logic_vector(7 downto 0); -- number of bytes to write / read (PP/RDCMD)\r
TXDATA_IN : in std_logic_vector(7 downto 0); -- byte to be transmitted next\r
- TX_RD_OUT : out std_logic;\r
- RXDATA_OUT : out std_logic_vector(7 downto 0); -- current received byte\r
- RX_WR_OUT : out std_logic;\r
- TX_RX_A_OUT : out std_logic_vector(7 downto 0); -- memory block counter for PP/RDCMD\r
+ TX_RD_OUT : out std_logic;\r
+ RXDATA_OUT : out std_logic_vector(7 downto 0); -- current received byte\r
+ RX_WR_OUT : out std_logic;\r
+ TX_RX_A_OUT : out std_logic_vector(7 downto 0); -- memory block counter for PP/RDCMD\r
-- SPI interface\r
- SPI_SCK_OUT : out std_logic;\r
- SPI_CS_OUT : out std_logic;\r
+ SPI_SCK_OUT : out std_logic;\r
+ SPI_CS_OUT : out std_logic;\r
SPI_SDI_IN : in std_logic;\r
- SPI_SDO_OUT : out std_logic;\r
+ SPI_SDO_OUT : out std_logic;\r
-- DEBUG\r
- CLK_EN_OUT : out std_logic;\r
- BSM_OUT : out std_logic_vector(7 downto 0);\r
- DEBUG_OUT : out std_logic_vector(31 downto 0)\r
+ CLK_EN_OUT : out std_logic;\r
+ BSM_OUT : out std_logic_vector(7 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(31 downto 0)\r
);\r
end entity;\r
\r
architecture Behavioral of spi_slim is\r
\r
-- new clock divider\r
-signal div_counter : std_logic_vector(1 downto 0);\r
-signal div_done_x : std_logic;\r
-signal div_done : std_logic; -- same as clk_en\r
-signal clk_en : std_logic; -- same as div_done\r
+signal div_counter : std_logic_vector(1 downto 0);\r
+signal div_done_x : std_logic;\r
+signal div_done : std_logic; -- same as clk_en\r
+signal clk_en : std_logic; -- same as div_done\r
\r
-- Statemachine signals\r
type state_t is (IDLE,CSL,TXCMD,TXADD_H,TXADD_M,TXADD_L,TXDATA,RXDATA,\r
WAIT1,WAIT2,WAIT3,WAIT4,WAIT5,WAIT6,WAIT7,WAIT8,CSH);\r
signal STATE, NEXT_STATE : state_t;\r
\r
-signal rx_ena_x : std_logic;\r
-signal rx_ena : std_logic;\r
-signal tx_ena_x : std_logic;\r
-signal tx_ena : std_logic;\r
-signal busy_x : std_logic;\r
-signal busy : std_logic;\r
-signal spi_cs_x : std_logic; -- SPI chip select (low active)\r
-signal spi_cs : std_logic;\r
-signal spi_sck_x : std_logic; -- SPI clock (rising edge active, from counter)\r
-signal spi_sck : std_logic;\r
-signal tx_load_x : std_logic; -- load TX shift register\r
-signal tx_load : std_logic;\r
-signal tx_done_x : std_logic; -- one memory byte sent\r
-signal tx_done : std_logic;\r
-signal tx_sel_x : std_logic_vector(2 downto 0); -- select TX content\r
-signal tx_sel : std_logic_vector(2 downto 0);\r
-signal rx_store_x : std_logic; -- store RX shift register\r
-signal rx_store : std_logic;\r
-signal rx_complete : std_logic;\r
-signal rst_addr_x : std_logic; -- reset address counter\r
-signal rst_addr : std_logic;\r
-\r
-signal inc_addr_rx_x : std_logic;\r
-signal inc_addr_rx : std_logic;\r
-signal inc_addr_tx_x : std_logic;\r
-signal inc_addr_tx : std_logic;\r
-signal ce_addr_x : std_logic;\r
-signal ce_addr : std_logic;\r
-\r
-signal addr_ctr : std_logic_vector(7 downto 0);\r
-signal data_done_x : std_logic;\r
-signal data_done : std_logic_vector(2 downto 0);\r
-\r
-signal last_tx_bit_x : std_logic;\r
-signal last_tx_bit : std_logic;\r
-signal is_data_x : std_logic;\r
-signal is_data : std_logic;\r
+signal rx_ena_x : std_logic;\r
+signal rx_ena : std_logic;\r
+signal tx_ena_x : std_logic;\r
+signal tx_ena : std_logic;\r
+signal busy_x : std_logic;\r
+signal busy : std_logic;\r
+signal spi_cs_x : std_logic; -- SPI chip select (low active)\r
+signal spi_cs : std_logic;\r
+signal spi_sck_x : std_logic; -- SPI clock (rising edge active, from counter)\r
+signal spi_sck : std_logic;\r
+signal tx_load_x : std_logic; -- load TX shift register\r
+signal tx_load : std_logic;\r
+signal tx_done_x : std_logic; -- one memory byte sent\r
+signal tx_done : std_logic;\r
+signal tx_sel_x : std_logic_vector(2 downto 0); -- select TX content\r
+signal tx_sel : std_logic_vector(2 downto 0);\r
+signal rx_store_x : std_logic; -- store RX shift register\r
+signal rx_store : std_logic;\r
+signal rx_complete : std_logic;\r
+signal rst_addr_x : std_logic; -- reset address counter\r
+signal rst_addr : std_logic;\r
+\r
+signal inc_addr_rx_x : std_logic;\r
+signal inc_addr_rx : std_logic;\r
+signal inc_addr_tx_x : std_logic;\r
+signal inc_addr_tx : std_logic;\r
+signal ce_addr_x : std_logic;\r
+signal ce_addr : std_logic;\r
+\r
+signal addr_ctr : std_logic_vector(7 downto 0);\r
+signal data_done_x : std_logic;\r
+signal data_done : std_logic_vector(2 downto 0);\r
+\r
+signal last_tx_bit_x : std_logic;\r
+signal last_tx_bit : std_logic;\r
+signal is_data_x : std_logic;\r
+signal is_data : std_logic;\r
\r
-- debug signals\r
-signal bsm_x : std_logic_vector(7 downto 0);\r
-signal debug_x : std_logic_vector(31 downto 0);\r
+signal bsm_x : std_logic_vector(7 downto 0);\r
+signal debug_x : std_logic_vector(31 downto 0);\r
\r
-signal start : std_logic; -- buffered start_in signal, as we have a clocked down state machine\r
-signal cmd_int : std_logic_vector(7 downto 0); -- internal command and address bytes\r
-signal adh_int : std_logic_vector(7 downto 0); -- internal command and address bytes\r
-signal adm_int : std_logic_vector(7 downto 0); -- internal command and address bytes\r
-signal adl_int : std_logic_vector(7 downto 0); -- internal command and address bytes\r
-signal max_int : std_logic_vector(7 downto 0);\r
+signal start : std_logic; -- buffered start_in signal, as we have a clocked down state machine\r
+signal cmd_int : std_logic_vector(7 downto 0); -- internal command and address bytes\r
+signal adh_int : std_logic_vector(7 downto 0); -- internal command and address bytes\r
+signal adm_int : std_logic_vector(7 downto 0); -- internal command and address bytes\r
+signal adl_int : std_logic_vector(7 downto 0); -- internal command and address bytes\r
+signal max_int : std_logic_vector(7 downto 0);\r
\r
-- transmitter\r
-signal tx_sreg : std_logic_vector(7 downto 0);\r
-signal tx_reg_comb : std_logic_vector(7 downto 0); -- multiplexer\r
-signal tx_bit_cnt : std_logic_vector(3 downto 0);\r
+signal tx_sreg : std_logic_vector(7 downto 0);\r
+signal tx_reg_comb : std_logic_vector(7 downto 0); -- multiplexer\r
+signal tx_bit_cnt : std_logic_vector(3 downto 0);\r
\r
-- receiver\r
-signal rx_sreg : std_logic_vector(7 downto 0);\r
-signal rx_ready_set : std_logic;\r
-signal rx_bit_cnt_clr : std_logic;\r
-signal rx_bit_cnt : std_logic_vector(3 downto 0);\r
-\r
-signal rd_data : std_logic;\r
-signal rd_data1 : std_logic;\r
-signal rd_data2 : std_logic;\r
-\r
-\r
+signal rx_sreg : std_logic_vector(7 downto 0);\r
+signal rx_bit_cnt_clr : std_logic;\r
+signal rx_bit_cnt : std_logic_vector(3 downto 0);\r
\r
-- registers\r
signal rx_data : std_logic_vector(7 downto 0);\r
-- FLASH commands\r
-- single byte commands\r
constant NOP : std_logic_vector(7 downto 0) := x"FF"; -- no cmd to execute\r
-constant WREN : std_logic_vector(7 downto 0) := x"06"; -- write enable -- OK -- CMD\r
-constant WRDI : std_logic_vector(7 downto 0) := x"04"; -- write disable -- OK -- CMD\r
-constant ERASE : std_logic_vector(7 downto 0) := x"C7"; -- chip erase -- OK -- CMD\r
+constant WREN : std_logic_vector(7 downto 0) := x"06"; -- write enable -- OK -- CMD\r
+constant WRDI : std_logic_vector(7 downto 0) := x"04"; -- write disable -- OK -- CMD\r
+constant ERASE : std_logic_vector(7 downto 0) := x"C7"; -- chip erase -- OK -- CMD\r
constant DPD : std_logic_vector(7 downto 0) := x"b9"; -- deep powerdown -- OK -- CMD\r
-constant RDPD : std_logic_vector(7 downto 0) := x"ab"; -- resume powerdown -- OK -- CMD\r
+constant RDPD : std_logic_vector(7 downto 0) := x"ab"; -- resume powerdown -- OK -- CMD\r
\r
-constant RDID : std_logic_vector(7 downto 0) := x"9f"; -- read signature -- OK -- CMD + readbyte(n)\r
-constant RDSR : std_logic_vector(7 downto 0) := x"05"; -- read status reg -- OK -- CMD + readbyte(n)\r
+constant RDID : std_logic_vector(7 downto 0) := x"9f"; -- read signature -- OK -- CMD + readbyte(n)\r
+constant RDSR : std_logic_vector(7 downto 0) := x"05"; -- read status reg -- OK -- CMD + readbyte(n)\r
\r
-constant WRSR : std_logic_vector(7 downto 0) := x"01"; -- write stat. reg -- OK -- CMD + writebyte(1)\r
+constant WRSR : std_logic_vector(7 downto 0) := x"01"; -- write stat. reg -- OK -- CMD + writebyte(1)\r
\r
-constant SE64 : std_logic_vector(7 downto 0) := x"d8"; -- sector erase 64kB -- OK -- CMD + ADH + ADM + ADL\r
-constant SE32 : std_logic_vector(7 downto 0) := x"52"; -- sector erase 32kB -- OK -- CMD + ADH + ADM + ADL\r
+constant SE64 : std_logic_vector(7 downto 0) := x"d8"; -- sector erase 64kB -- OK -- CMD + ADH + ADM + ADL\r
+constant SE32 : std_logic_vector(7 downto 0) := x"52"; -- sector erase 32kB -- OK -- CMD + ADH + ADM + ADL\r
constant SE4 : std_logic_vector(7 downto 0) := x"20"; -- sector erase 32kB -- OK -- CMD + ADH + ADM + ADL\r
-constant SECP : std_logic_vector(7 downto 0) := x"36"; -- sector protect -- OK -- CMD + ADH + ADM + ADL\r
-constant SECU : std_logic_vector(7 downto 0) := x"39"; -- sector unprotect -- OK -- CMD + ADH + ADM + ADL\r
+constant SECP : std_logic_vector(7 downto 0) := x"36"; -- sector protect -- OK -- CMD + ADH + ADM + ADL\r
+constant SECU : std_logic_vector(7 downto 0) := x"39"; -- sector unprotect -- OK -- CMD + ADH + ADM + ADL\r
\r
-constant RDCMD : std_logic_vector(7 downto 0) := x"03"; -- read data -- OK -- CMD + ADH + ADM + ADL + readbyte(n)\r
-constant RDSPR : std_logic_vector(7 downto 0) := x"3c"; -- read sect. prot. -- -- CMD + ADH + ADM + ADL + readbye(n)\r
-constant PP : std_logic_vector(7 downto 0) := x"02"; -- page program -- OK -- CMD + ADH + ADM + ADL + writebyte(n)\r
+constant RDCMD : std_logic_vector(7 downto 0) := x"03"; -- read data -- OK -- CMD + ADH + ADM + ADL + readbyte(n)\r
+constant RDSPR : std_logic_vector(7 downto 0) := x"3c"; -- read sect. prot. -- -- CMD + ADH + ADM + ADL + readbye(n)\r
+constant PP : std_logic_vector(7 downto 0) := x"02"; -- page program -- OK -- CMD + ADH + ADM + ADL + writebyte(n)\r
\r
\r
begin\r
-----------------------------------------------------------\r
-- Debug signals\r
-----------------------------------------------------------\r
-debug_x(31 downto 24) <= tx_sreg; --(others => '0');\r
+debug_x(31 downto 24) <= bsm_x; --(others => '0');\r
debug_x(23 downto 20) <= tx_bit_cnt; --(others => '0');\r
debug_x(19 downto 16) <= rx_bit_cnt; --(others => '0');\r
-debug_x(15) <= '0';\r
-debug_x(14) <= '0';\r
+debug_x(15) <= busy;\r
+debug_x(14) <= start;\r
debug_x(13) <= inc_addr_tx;\r
debug_x(12) <= inc_addr_rx;\r
debug_x(11) <= last_tx_bit;\r
rx_bit_cnt_clr <= '1';\r
\r
case STATE is\r
- when IDLE => bsm_x <= x"00";\r
- when CSL => bsm_x <= x"09";\r
- when TXCMD => bsm_x <= x"01";\r
- when TXDATA => bsm_x <= x"02";\r
- when TXADD_H => bsm_x <= x"03";\r
- when TXADD_M => bsm_x <= x"04";\r
- when TXADD_L => bsm_x <= x"05";\r
- when RXDATA => bsm_x <= x"07";\r
- when WAIT1 => bsm_x <= x"10";\r
- when WAIT2 => bsm_x <= x"11";\r
- when WAIT3 => bsm_x <= x"12";\r
- when WAIT4 => bsm_x <= x"13";\r
- when WAIT8 => bsm_x <= x"17";\r
- when WAIT6 => bsm_x <= x"15";\r
- when WAIT5 => bsm_x <= x"14";\r
- when WAIT7 => bsm_x <= x"16";\r
- when CSH => bsm_x <= x"08";\r
- when others => bsm_x <= x"ff";\r
+ when IDLE => bsm_x <= x"00";\r
+ when CSL => bsm_x <= x"09";\r
+ when TXCMD => bsm_x <= x"01";\r
+ when TXDATA => bsm_x <= x"02";\r
+ when TXADD_H => bsm_x <= x"03";\r
+ when TXADD_M => bsm_x <= x"04";\r
+ when TXADD_L => bsm_x <= x"05";\r
+ when RXDATA => bsm_x <= x"07";\r
+ when WAIT1 => bsm_x <= x"10";\r
+ when WAIT2 => bsm_x <= x"11";\r
+ when WAIT3 => bsm_x <= x"12";\r
+ when WAIT4 => bsm_x <= x"13";\r
+ when WAIT8 => bsm_x <= x"17";\r
+ when WAIT6 => bsm_x <= x"15";\r
+ when WAIT5 => bsm_x <= x"14";\r
+ when WAIT7 => bsm_x <= x"16";\r
+ when CSH => bsm_x <= x"08";\r
+ when others => bsm_x <= x"ff";\r
end case;\r
end process THE_STATEMACHINE_OUT;\r
\r
when "101" => tx_reg_comb <= x"ee"; -- unused\r
when "110" => tx_reg_comb <= x"00"; -- fixed value\r
when "111" => tx_reg_comb <= x"ff"; -- fixed value\r
- when others => tx_reg_comb <= x"00";\r
+ when others => tx_reg_comb <= x"00";\r
end case;\r
end process THE_TXREG_MUX;\r
\r
LVL1_TRG_INFORMATION_OUT : out std_logic_vector(7 downto 0);
LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0) := x"00000000";
LVL1_TRG_RELEASE_IN : in std_logic := '0';
+ LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);
--Data Port
REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
REGIO_REGISTERS_IN : in std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');
REGIO_REGISTERS_OUT : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
+ COMMON_STAT_REG_STROBE : out std_logic_vector(2**(std_COMSTATREG)-1 downto 0);
+ COMMON_CTRL_REG_STROBE : out std_logic_vector(2**(std_COMCTRLREG)-1 downto 0);
+ STAT_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);
+ CTRL_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
--following ports only used when using internal data port
REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0);
REGIO_READ_ENABLE_OUT : out std_logic;
-- for the connection to the multiplexer
signal MED_IO_DATAREADY_IN : std_logic_vector(3 downto 0);
-signal MED_IO_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0);
-signal MED_IO_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0);
+signal MED_IO_DATA_IN : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
+signal MED_IO_PACKET_NUM_IN : std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
signal MED_IO_READ_OUT : std_logic_vector(3 downto 0);
signal MED_IO_DATAREADY_OUT : std_logic_vector(7 downto 0);
signal buf_IDRAM_WR_IN : std_logic;
signal reset_no_link : std_logic;
+ signal buf_COMMON_STAT_REG_STROBE : std_logic_vector(2**(std_COMSTATREG)-1 downto 0);
+ signal buf_COMMON_CTRL_REG_STROBE : std_logic_vector(2**(std_COMCTRLREG)-1 downto 0);
+ signal buf_STAT_REG_STROBE : std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);
+ signal buf_CTRL_REG_STROBE : std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
+ signal int_trigger_num : std_logic_vector(15 downto 0);
+
+ signal buf_LVL1_TRG_TYPE_OUT : std_logic_vector(3 downto 0);
+ signal buf_LVL1_TRG_RECEIVED_OUT : std_logic;
+ signal buf_LVL1_TRG_NUMBER_OUT : std_logic_vector(15 downto 0);
+ signal buf_LVL1_TRG_CODE_OUT : std_logic_vector(7 downto 0);
+ signal buf_LVL1_TRG_INFORMATION_OUT : std_logic_vector(7 downto 0);
+ signal last_LVL1_TRG_RECEIVED_OUT : std_logic;
+ signal LVL1_TRG_RECEIVED_OUT_rising : std_logic;
+ signal buf_LVL1_ERROR_PATTERN_IN : std_logic_vector(31 downto 0);
+
+ signal temperature : std_logic_vector(11 downto 0);
+ signal got_timing_trigger : std_logic;
+ signal trigger_number_match : std_logic;
+
begin
reset_no_link <= MED_STAT_OP_IN(14) or RESET;
MED_INIT_READ_IN => MED_IO_READ_IN(i*2),
MED_DATAREADY_IN => MED_IO_DATAREADY_IN(i),
- MED_DATA_IN => MED_IO_DATA_IN,
- MED_PACKET_NUM_IN => MED_IO_PACKET_NUM_IN,
+ MED_DATA_IN => MED_IO_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ MED_PACKET_NUM_IN => MED_IO_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
MED_READ_OUT => MED_IO_READ_OUT(i),
MED_ERROR_IN => MED_STAT_OP_IN(2 downto 0),
INT_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
INT_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
INT_READ_OUT => buf_to_apl_INIT_READ(i),
- TRG_RECEIVED_OUT => LVL1_TRG_RECEIVED_OUT,
- TRG_TYPE_OUT => LVL1_TRG_TYPE_OUT,
- TRG_NUMBER_OUT => LVL1_TRG_NUMBER_OUT,
- TRG_CODE_OUT => LVL1_TRG_CODE_OUT,
- TRG_INFORMATION_OUT => LVL1_TRG_INFORMATION_OUT,
+ TRG_RECEIVED_OUT => buf_LVL1_TRG_RECEIVED_OUT,
+ TRG_TYPE_OUT => buf_LVL1_TRG_TYPE_OUT,
+ TRG_NUMBER_OUT => buf_LVL1_TRG_NUMBER_OUT,
+ TRG_CODE_OUT => buf_LVL1_TRG_CODE_OUT,
+ TRG_INFORMATION_OUT => buf_LVL1_TRG_INFORMATION_OUT,
TRG_RELEASE_IN => LVL1_TRG_RELEASE_IN,
- TRG_ERROR_PATTERN_IN => LVL1_ERROR_PATTERN_IN
+ TRG_ERROR_PATTERN_IN => buf_LVL1_ERROR_PATTERN_IN
);
end generate;
--Custom Register in / out
REGISTERS_IN => REGIO_REGISTERS_IN,
REGISTERS_OUT => REGIO_REGISTERS_OUT,
+ COMMON_STAT_REG_STROBE => buf_COMMON_STAT_REG_STROBE,
+ COMMON_CTRL_REG_STROBE => buf_COMMON_CTRL_REG_STROBE,
+ STAT_REG_STROBE => buf_STAT_REG_STROBE,
+ CTRL_REG_STROBE => buf_CTRL_REG_STROBE,
--following ports only used when no internal register is accessed
DAT_ADDR_OUT => REGIO_ADDR_OUT,
DAT_READ_ENABLE_OUT => REGIO_READ_ENABLE_OUT,
REGIO_IDRAM_DATA_OUT <= buf_IDRAM_DATA_OUT;
REGIO_ONEWIRE_INOUT <= '0';
REGIO_ONEWIRE_MONITOR_OUT <= '0';
- buf_COMMON_STAT_REG_IN <= REGIO_COMMON_STAT_REG_IN;
+
end generate;
gen_1wire : if REGIO_USE_1WIRE_INTERFACE = c_YES generate
- buf_COMMON_STAT_REG_IN(19 downto 0) <= REGIO_COMMON_STAT_REG_IN(19 downto 0);
- buf_COMMON_STAT_REG_IN(REGIO_COMMON_STAT_REG_IN'left downto 32) <=
- REGIO_COMMON_STAT_REG_IN(REGIO_COMMON_STAT_REG_IN'left downto 32);
+
REGIO_IDRAM_DATA_OUT <= (others => '0');
DATA_OUT => buf_IDRAM_DATA_IN,
ADDR_OUT => buf_IDRAM_ADDR_IN,
WRITE_OUT=> buf_IDRAM_WR_IN,
- TEMP_OUT => buf_COMMON_STAT_REG_IN(31 downto 20),
+ TEMP_OUT => temperature,
STAT => STAT_ONEWIRE
);
end generate;
gen_1wire_monitor : if REGIO_USE_1WIRE_INTERFACE = c_MONITOR generate
- buf_COMMON_STAT_REG_IN(19 downto 0) <= REGIO_COMMON_STAT_REG_IN(19 downto 0);
- buf_COMMON_STAT_REG_IN(REGIO_COMMON_STAT_REG_IN'left downto 32) <=
- REGIO_COMMON_STAT_REG_IN(REGIO_COMMON_STAT_REG_IN'left downto 32);
REGIO_IDRAM_DATA_OUT <= (others => '0');
REGIO_ONEWIRE_MONITOR_OUT <= '0';
DATA_OUT => buf_IDRAM_DATA_IN,
ADDR_OUT => buf_IDRAM_ADDR_IN,
WRITE_OUT=> buf_IDRAM_WR_IN,
- TEMP_OUT => buf_COMMON_STAT_REG_IN(31 downto 20),
+ TEMP_OUT => temperature,
STAT => STAT_ONEWIRE
);
end generate;
RESET => reset_no_link,
CLK_EN => CLK_EN,
MED_DATAREADY_IN => MED_IO_DATAREADY_IN(i),
- MED_DATA_IN => MED_IO_DATA_IN,
- MED_PACKET_NUM_IN => MED_IO_PACKET_NUM_IN,
+ MED_DATA_IN => MED_IO_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ MED_PACKET_NUM_IN => MED_IO_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
MED_READ_OUT => MED_IO_READ_OUT(i),
MED_INIT_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2),
CTRL => CTRL_MPLEX
);
-buf_CTRL_GEN <= IOBUF_CTRL_GEN;
-REGIO_COMMON_CTRL_REG_OUT <= buf_REGIO_COMMON_CTRL_REG_OUT;
-
-STAT_DEBUG_1 <= REGIO_REGIO_STAT;
-STAT_DEBUG_2(3 downto 0) <= MED_IO_DATA_OUT(7*16+3 downto 7*16);
-STAT_DEBUG_2(7 downto 4) <= apl_to_buf_REPLY_DATA(3*16+3 downto 3*16);
-STAT_DEBUG_2(8) <= apl_to_buf_REPLY_DATAREADY(3);
-STAT_DEBUG_2(11 downto 9) <= apl_to_buf_REPLY_PACKET_NUM(3*3+2 downto 3*3);
-STAT_DEBUG_2(15 downto 12) <= (others => '0');
-STAT_DEBUG_2(31 downto 16) <= buf_STAT_INIT_BUFFER(3*32+15 downto 3*32);
-
-end trb_net16_endpoint_hades_full_arch;
+ proc_gen_common_stat_regs : process(REGIO_COMMON_STAT_REG_IN, trigger_number_match, temperature, int_trigger_num)
+ begin
+ buf_COMMON_STAT_REG_IN(3 downto 0) <= REGIO_COMMON_STAT_REG_IN(3 downto 0);
+ buf_COMMON_STAT_REG_IN(4) <= not trigger_number_match;
+ buf_COMMON_STAT_REG_IN(19 downto 5) <= REGIO_COMMON_STAT_REG_IN(19 downto 5);
+ if REGIO_USE_1WIRE_INTERFACE = c_NO then
+ buf_COMMON_STAT_REG_IN(31 downto 20) <= REGIO_COMMON_STAT_REG_IN(31 downto 20);
+ else
+ buf_COMMON_STAT_REG_IN(31 downto 20) <= temperature;
+ end if;
+ buf_COMMON_STAT_REG_IN(47 downto 32) <= int_trigger_num;
+ buf_COMMON_STAT_REG_IN(REGIO_COMMON_STAT_REG_IN'left downto 48) <=
+ REGIO_COMMON_STAT_REG_IN(REGIO_COMMON_STAT_REG_IN'left downto 48);
+ end process;
+
+-------------------------------------------------
+-- Check LVL1 trigger number
+-------------------------------------------------
+ proc_internal_trigger_number : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ int_trigger_num <= (others => '1');
+ else
+ if buf_COMMON_CTRL_REG_STROBE(1) = '1' then
+ int_trigger_num <= buf_REGIO_COMMON_CTRL_REG_OUT(47 downto 32);
+ elsif TRIGGER_MONITOR_IN = '1' then
+ int_trigger_num <= int_trigger_num + 1;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ proc_check_trigger_number : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ trigger_number_match <= '1';
+ else
+ if LVL1_TRG_RECEIVED_OUT_rising = '1' then
+ if int_trigger_num = buf_LVL1_TRG_NUMBER_OUT then
+ trigger_number_match <= '1';
+ else
+ trigger_number_match <= '0';
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+ proc_detect_trigger_receive : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ last_LVL1_TRG_RECEIVED_OUT <= buf_LVL1_TRG_RECEIVED_OUT;
+ LVL1_TRG_RECEIVED_OUT_rising <= buf_LVL1_TRG_RECEIVED_OUT and not last_LVL1_TRG_RECEIVED_OUT;
+
+ if RESET = '1' or LVL1_TRG_RELEASE_IN = '1' then
+ got_timing_trigger <= '0';
+ elsif TRIGGER_MONITOR_IN = '1' then
+ got_timing_trigger <= '1';
+ end if;
+ end if;
+ end process;
+
+
+ proc_gen_lvl1_error_pattern : process(LVL1_ERROR_PATTERN_IN, trigger_number_match, got_timing_trigger )
+ begin
+ buf_LVL1_ERROR_PATTERN_IN <= LVL1_ERROR_PATTERN_IN;
+ buf_LVL1_ERROR_PATTERN_IN(16) <= not trigger_number_match;
+ buf_LVL1_ERROR_PATTERN_IN(17) <= not got_timing_trigger or LVL1_ERROR_PATTERN_IN(17);
+ end process;
+
+
+-------------------------------------------------
+-- Connect Outputs
+-------------------------------------------------
+
+ LVL1_TRG_RECEIVED_OUT <= buf_LVL1_TRG_RECEIVED_OUT;
+ LVL1_TRG_TYPE_OUT <= buf_LVL1_TRG_TYPE_OUT;
+ LVL1_TRG_NUMBER_OUT <= buf_LVL1_TRG_NUMBER_OUT;
+ LVL1_TRG_CODE_OUT <= buf_LVL1_TRG_CODE_OUT;
+ LVL1_TRG_INFORMATION_OUT <= buf_LVL1_TRG_INFORMATION_OUT;
+ LVL1_INT_TRG_NUMBER_OUT <= int_trigger_num;
+
+ COMMON_STAT_REG_STROBE <= buf_COMMON_STAT_REG_STROBE;
+ COMMON_CTRL_REG_STROBE <= buf_COMMON_CTRL_REG_STROBE;
+ STAT_REG_STROBE <= buf_STAT_REG_STROBE;
+ CTRL_REG_STROBE <= buf_CTRL_REG_STROBE;
+
+
+
+ buf_CTRL_GEN <= IOBUF_CTRL_GEN;
+ REGIO_COMMON_CTRL_REG_OUT <= buf_REGIO_COMMON_CTRL_REG_OUT;
+
+ STAT_DEBUG_1 <= REGIO_REGIO_STAT;
+ STAT_DEBUG_2(3 downto 0) <= MED_IO_DATA_OUT(7*16+3 downto 7*16);
+ STAT_DEBUG_2(7 downto 4) <= apl_to_buf_REPLY_DATA(3*16+3 downto 3*16);
+ STAT_DEBUG_2(8) <= apl_to_buf_REPLY_DATAREADY(3);
+ STAT_DEBUG_2(11 downto 9) <= apl_to_buf_REPLY_PACKET_NUM(3*3+2 downto 3*3);
+ STAT_DEBUG_2(15 downto 12) <= (others => '0');
+ STAT_DEBUG_2(31 downto 16) <= buf_STAT_INIT_BUFFER(3*32+15 downto 3*32);
+
+end architecture;
signal m_PACKET_NUM_OUT: std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)*c_NUM_WIDTH-1 downto 0);
signal m_READ_IN : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)-1 downto 0);
signal m_DATAREADY_IN : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH-1)-1 downto 0);
- signal m_DATA_IN : std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
- signal m_PACKET_NUM_IN : std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
+ signal m_DATA_IN : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0);
+ signal m_PACKET_NUM_IN : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0);
signal m_READ_OUT : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH-1)-1 downto 0);
signal m_ERROR_IN : std_logic_vector (MII_NUMBER*3-1 downto 0);
signal DAT_UNKNOWN_ADDR_IN : std_logic := '0';
signal DAT_TIMEOUT_OUT : std_logic;
+ attribute syn_preserve : boolean;
+ attribute syn_keep : boolean;
+ attribute syn_preserve of m_DATA_IN : signal is true;
+ attribute syn_keep of m_DATA_IN : signal is true;
+ attribute syn_preserve of m_DATAREADY_IN : signal is true;
+ attribute syn_keep of m_DATAREADY_IN : signal is true;
+
+
+
begin
MED_PACKET_NUM_OUT => buf_MED_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
MED_READ_IN => MED_READ_IN(i),
INT_DATAREADY_OUT => m_DATAREADY_IN((i+1)*2**(c_MUX_WIDTH-1)-1 downto i*2**(c_MUX_WIDTH-1)),
- INT_DATA_OUT => m_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_PACKET_NUM_OUT => m_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
+ INT_DATA_OUT => m_DATA_IN((i+1)*2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH*2**(c_MUX_WIDTH-1)),
+ INT_PACKET_NUM_OUT => m_PACKET_NUM_IN((i+1)*2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH*2**(c_MUX_WIDTH-1)),
INT_READ_IN => m_READ_OUT((i+1)*2**(c_MUX_WIDTH-1)-1 downto i*2**(c_MUX_WIDTH-1)),
INT_DATAREADY_IN => m_DATAREADY_OUT((i+1)*2**c_MUX_WIDTH-1 downto i*2**c_MUX_WIDTH),
INT_DATA_IN => m_DATA_OUT((i+1)*c_DATA_WIDTH*2**c_MUX_WIDTH-1 downto i*c_DATA_WIDTH*2**c_MUX_WIDTH),
MED_REPLY_PACKET_NUM_OUT=> m_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH),
MED_REPLY_READ_IN => m_READ_IN(i*2+1),
MED_DATAREADY_IN => m_DATAREADY_IN(i),
- MED_DATA_IN => m_DATA_IN((j+1)*c_DATA_WIDTH-1 downto j*c_DATA_WIDTH),
- MED_PACKET_NUM_IN => m_PACKET_NUM_IN((j+1)*c_NUM_WIDTH-1 downto j*c_NUM_WIDTH),
+ MED_DATA_IN => m_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ MED_PACKET_NUM_IN => m_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
MED_READ_OUT => m_READ_OUT(i),
MED_ERROR_IN => m_ERROR_IN((j+1)*3-1 downto j*3),
MED_REPLY_PACKET_NUM_OUT=> m_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH),
MED_REPLY_READ_IN => m_READ_IN(i*2+1),
MED_DATAREADY_IN => m_DATAREADY_IN(i),
- MED_DATA_IN => m_DATA_IN((j+1)*c_DATA_WIDTH-1 downto j*c_DATA_WIDTH),
- MED_PACKET_NUM_IN => m_PACKET_NUM_IN((j+1)*c_NUM_WIDTH-1 downto j*c_NUM_WIDTH),
+ MED_DATA_IN => m_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ MED_PACKET_NUM_IN => m_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
MED_READ_OUT => m_READ_OUT(i)
);
end generate;
signal reply_compare_start : std_logic;
signal reg_reply_compare_start : std_logic;
signal reply_compare_finished : std_logic;
- signal reply_compare_result : std_logic_vector(17-1 downto 0);
- signal reply_compare_flag : std_logic;
- signal reply_compare_input : std_logic_vector(17-1 downto 0);
+ --signal reply_compare_result : std_logic_vector(17-1 downto 0);
+ --signal reply_compare_flag : std_logic;
+ --signal reply_compare_input : std_logic_vector(17-1 downto 0);
signal dhdr_addr : std_logic_vector(2 downto 0);
signal dhdr_data : std_logic_vector(16*POINT_NUMBER-1 downto 0);
signal timeout_counter : timeout_counter_t;
signal timeout_counter_reset : std_logic_vector(POINT_NUMBER-1 downto 0);
signal connection_timed_out : std_logic_vector(POINT_NUMBER-1 downto 0);
+ signal timeout_found : std_logic;
signal saved_auto_reading_DHDR : std_logic_vector(POINT_NUMBER-1 downto 0);
signal last_REPLY_PACKET_NUM_IN : std_logic_vector(POINT_NUMBER*3-1 downto 0);
or reg_current_reply_reading_HDR(i) --current_reply_reading_HDR(i)
or reg_current_reply_auto_reading_DHDR(i)
or saved_reading_padding(i)
- or (reply_mux_reading(i) and REPLY_POOL_next_read and not packet_counter(2));
+ or (reply_mux_reading(i) and REPLY_POOL_next_read and not packet_counter(2))
+ or not locked;
-- or (reply_fsm_state(4) and reply_reading_H0(i));
PROC_auto_read_DHDR : process(reg_current_reply_reading_HDR, enable_packing,
- last_REPLY_PACKET_NUM_IN, saved_auto_reading_DHDR)
+ last_REPLY_PACKET_NUM_IN,reg_current_reply_reading_dhdr)
begin
reg_current_reply_auto_reading_DHDR(i) <= '0';
if reg_current_reply_reading_HDR(i) = '1' then
begin
if rising_edge(CLK) then
connection_timed_out(i) <= '0';
+ timeout_found <= or_all(connection_timed_out);
if REPLY_DATAREADY_IN(i) = '1' or real_activepoints(i) = '0' or locked = '0' then
timeout_counter(i) <= (others => '0');
elsif timeout_counter(i)(timeout_counter(i)'left) = '1' then
- timeout_counter(i) <= timeout_counter(i);
connection_timed_out(i) <= '1';
else
timeout_counter(i) <= timeout_counter(i) + to_unsigned(1,1);
--saving (D)HDR
----------------------------------
gen_saving_dhdr : for i in 0 to POINT_NUMBER-1 generate
- hdrram_write_enable(i) <= (reg_current_reply_reading_HDR(i) or reg_current_reply_reading_DHDR(i)) and not reply_reading_H0(i);
+ hdrram_write_enable(i) <= (reg_current_reply_reading_HDR(i) or reg_current_reply_reading_DHDR(i)) and not reply_reading_H0(i) and REPLY_DATAREADY_IN(i);
hdrram_address(i*3+1 downto i*3) <= REPLY_PACKET_NUM_IN((i)*c_NUM_WIDTH+1 downto i*c_NUM_WIDTH);
hdrram_address(i*3+2) <= '1' when current_reply_reading_DHDR(i)='1' else '0';
tmpF2 := tmpF2 or (REPLY_DATA_IN(i*c_DATA_WIDTH+j) and reply_reading_F2(i) and reg_current_reply_reading_TRM(i));
tmpF3 := tmpF3 or (REPLY_DATA_IN(i*c_DATA_WIDTH+j) and reply_reading_F3(i) and reg_current_reply_reading_TRM(i));
end loop;
- reply_combined_trm_F1(j) <= reply_combined_trm_F1(j) or tmpF1;
+ if j = 3 then
+ reply_combined_trm_F1(j) <= reply_combined_trm_F1(j) or tmpF1 or timeout_found;
+ else
+ reply_combined_trm_F1(j) <= reply_combined_trm_F1(j) or tmpF1;
+ end if;
+
reply_combined_trm_F2(j) <= reply_combined_trm_F2(j) or tmpF2;
reply_combined_trm_F3(j) <= reply_combined_trm_F3(j) or tmpF3;
end if;
begin
if rising_edge(CLK) then
if reply_data_counter_reset = '1' then
- reply_data_counter <= (others => '0'); --length/source word is not included in word count, so this is word -1
+ if enable_packing = '0' or DISABLE_PACKING = 1 then
+ reply_data_counter <= (others => '0');
+ else
+ reply_data_counter <= (0 => '1', others => '0');
+ end if;
elsif enable_reply_data_counter = '1' then
reply_data_counter <= reply_data_counter + 1;
end if;
next_waiting_for_DHDR_word <= waiting_for_DHDR_word and real_activepoints
and not (reg_current_reply_reading_DHDR and reply_reading_F2);
dhdr_addr <= "000";
- next_current_waiting_for_reply <= current_waiting_for_reply and not reg_current_reply_reading_HDR and real_activepoints;
+-- next_current_waiting_for_reply <= current_waiting_for_reply and not reg_current_reply_reading_HDR and real_activepoints;
next_reply_adder_start <= '0';
reply_arbiter_enable <= '0';
next_reply_compare_start <= '0';
case current_state is
when IDLE => --wait for init transfer
next_waiting_for_DHDR_word <= not (locking_point or not real_activepoints);
- next_current_waiting_for_reply <= not (locking_point or not real_activepoints);
+-- next_current_waiting_for_reply <= not (locking_point or not real_activepoints);
if locked = '1' then
next_state <= WAIT_FOR_REPLY;
end if;
comb_REPLY_POOL_DATA <= MY_ADDRESS_IN;
comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read;
when c_F1 =>
- comb_REPLY_POOL_DATA <= x"FFFF"; --sender address is not known!
+ comb_REPLY_POOL_DATA <= x"FFFF";
comb_REPLY_POOL_DATAREADY <= REPLY_POOL_next_read;
when c_F2 =>
comb_REPLY_POOL_DATAREADY <= '0';
current_state <= IDLE;
REPLY_POOL_next_read <= '0';
waiting_for_DHDR_word <= (others => '1');
- current_waiting_for_reply <= (others => '1');
- got_all_reply_starts <= '0';
+-- current_waiting_for_reply <= (others => '1');
+-- got_all_reply_starts <= '0';
reply_adder_final_result <= (others => '0');
last_reply_adder_ready <= '0';
else
current_state <= next_state;
REPLY_POOL_next_read <= comb_REPLY_POOL_next_read;
waiting_for_DHDR_word <= next_waiting_for_DHDR_word;
- current_waiting_for_reply <= next_current_waiting_for_reply;
- got_all_reply_starts <= not or_all(current_waiting_for_reply);
+-- current_waiting_for_reply <= next_current_waiting_for_reply;
+-- got_all_reply_starts <= not or_all(current_waiting_for_reply);
not_reading_HDR <= not or_all(current_reply_reading_HDR);
number_of_replies <= to_unsigned(count_ones(expected_replies),5);
expected_replies <= real_activepoints and not locking_point;
STAT_DEBUG(25) <= reg_current_reply_reading_DHDR(1);
STAT_DEBUG(26) <= reg_current_reply_reading_HDR(1);
STAT_DEBUG(27) <= got_all_DHDR;
- STAT_DEBUG(28) <= got_all_reply_starts;
+ STAT_DEBUG(28) <= '0'; --got_all_reply_starts;
STAT_DEBUG(31 downto 29) <= last_REPLY_PACKET_NUM_IN(5 downto 3);
--STAT(15 downto 8) <= data_counter;
signal timeout_counter : timeout_counter_t;
signal timeout_counter_reset : std_logic_vector(POINT_NUMBER-1 downto 0);
signal connection_timed_out : std_logic_vector(POINT_NUMBER-1 downto 0);
+ signal timeout_found : std_logic;
begin
tmpF3 := tmpF3 or (reply_data_in_i(i*c_DATA_WIDTH+j) and reading_trmF3(i));
end loop;
REPLY_combined_trm_F1(j) <= REPLY_combined_trm_F1(j) or tmpF1;
- REPLY_combined_trm_F2(j) <= REPLY_combined_trm_F2(j) or tmpF2;
+ if j = 6 then
+ reply_combined_trm_F2(j) <= reply_combined_trm_F2(j) or tmpF2 or timeout_found;
+ else
+ reply_combined_trm_F2(j) <= reply_combined_trm_F2(j) or tmpF2;
+ end if;
REPLY_combined_trm_F3(j) <= REPLY_combined_trm_F3(j) or tmpF3;
end if;
end if;
begin
if rising_edge(CLK) then
connection_timed_out(i) <= '0';
+ timeout_found <= or_all(connection_timed_out);
if REPLY_DATAREADY_IN(i) = '1' or real_activepoints(i) = '0' or locked = '0' then
timeout_counter(i) <= (others => '0');
elsif timeout_counter(i)(timeout_counter(i)'left) = '1' then
- timeout_counter(i) <= timeout_counter(i);
connection_timed_out(i) <= '1';
else
timeout_counter(i) <= timeout_counter(i) + to_unsigned(1,1);
signal fifo_write, fifo_read : std_logic;
signal fifo_full, fifo_empty : std_logic;
- signal current_packet_type : std_logic_vector(3 downto 0);
signal saved_packet_type : std_logic_vector(3 downto 0);
signal current_fifo_packet_type : std_logic_vector(3 downto 0);
signal saved_fifo_packet_type : std_logic_vector(3 downto 0);
signal reply_word_waiting : std_logic;
signal init_word_waiting : std_logic;
+ signal is_h0 : std_logic;
+
attribute syn_preserve : boolean;
attribute syn_keep : boolean;
attribute syn_sharing : string;
attribute syn_keep of reg_med_dataready_in : signal is true;
attribute syn_keep of reg_med_packet_num_in : signal is true;
attribute syn_keep of saved_packet_type : signal is true;
+ attribute syn_keep of is_h0 : signal is true;
attribute syn_preserve of reg_med_data_in : signal is true;
attribute syn_preserve of reg_med_dataready_in : signal is true;
attribute syn_preserve of reg_med_packet_num_in : signal is true;
attribute syn_preserve of saved_packet_type : signal is true;
+ attribute syn_preserve of is_h0 : signal is true;
+
+
begin
--check incoming data for ACK & fifo status check
------------------------
+ is_h0 <= MED_PACKET_NUM_IN(2) and not MED_PACKET_NUM_IN(1) and not MED_PACKET_NUM_IN(0);
+ --'1' when MED_PACKET_NUM_IN = c_H0 else '0';
+
proc_store_input_packet_type : process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
saved_packet_type <= '1' & TYPE_ILLEGAL;
- elsif MED_PACKET_NUM_IN = c_H0 then
+ elsif is_h0 = '1' then
saved_packet_type <= MED_DATA_IN(3 downto 0);
end if;
end if;
library work;
use work.trb_net_std.all;
+use work.trb_net_components.all;
entity trb_net16_io_multiplexer is
MED_READ_IN : in STD_LOGIC;
-- Internal direction port
- INT_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
- INT_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
+ INT_DATA_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0);
+ INT_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0);
INT_DATAREADY_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0);
INT_READ_IN : in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0);
INT_DATAREADY_IN : in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0);
- INT_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH*(2**c_MUX_WIDTH)-1 downto 0);
- INT_PACKET_NUM_IN : in STD_LOGIC_VECTOR (c_NUM_WIDTH*(2**c_MUX_WIDTH)-1 downto 0);
+ INT_DATA_IN : in STD_LOGIC_VECTOR (2**c_MUX_WIDTH*c_DATA_WIDTH-1 downto 0);
+ INT_PACKET_NUM_IN : in STD_LOGIC_VECTOR (2**c_MUX_WIDTH*c_NUM_WIDTH-1 downto 0);
INT_READ_OUT : out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0);
-- Status and control port
architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is
-
- component trb_net16_sbuf is
- generic (
- VERSION : integer := 0
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- -- port to combinatorial logic
- COMB_DATAREADY_IN : in STD_LOGIC;
- COMB_next_READ_OUT: out STD_LOGIC;
- COMB_READ_IN : in STD_LOGIC;
- COMB_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
- COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0);
- -- Port to synchronous output.
- SYN_DATAREADY_OUT : out STD_LOGIC;
- SYN_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
- SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(c_NUM_WIDTH-1 downto 0);
- SYN_READ_IN : in STD_LOGIC;
- -- Status and control port
- STAT_BUFFER : out STD_LOGIC
- );
- end component;
-
- component trb_net_priority_arbiter is
- generic (
- WIDTH : integer := 8
- );
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- INPUT_IN : in std_logic_vector (WIDTH-1 downto 0);
- RESULT_OUT: out std_logic_vector (WIDTH-1 downto 0);
- ENABLE : in std_logic;
- CTRL : in std_logic_vector (9 downto 0)
- );
- end component;
-
signal current_demux_READ : STD_LOGIC_VECTOR ((2**c_MUX_WIDTH-1)-1 downto 0);
signal next_demux_dr, next_demux_dr_tmp, demux_dr_tmp: STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0);
signal buf_INT_DATAREADY_OUT : STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0);
signal current_mux_packet_number : std_logic_vector (c_NUM_WIDTH-1 downto 0) := c_H0;
signal last_mux_enable : std_logic;
signal arbiter_CLK_EN : std_logic;
- signal buf_INT_DATA_OUT: STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
- signal buf_INT_PACKET_NUM_OUT: STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
+ signal buf_INT_DATA_OUT: STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0);
+ signal buf_INT_PACKET_NUM_OUT: STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0);
signal sbuf_status : std_logic;
-- Placer Directives
-- for whole architecture
attribute HGROUP of trb_net16_io_multiplexer_arch : architecture is "MUX_group";
+ attribute syn_preserve : boolean;
+ attribute syn_keep : boolean;
+ attribute syn_preserve of buf_INT_DATA_OUT : signal is true;
+ attribute syn_keep of buf_INT_DATA_OUT : signal is true;
+ attribute syn_preserve of buf_INT_DATAREADY_OUT : signal is true;
+ attribute syn_keep of buf_INT_DATAREADY_OUT : signal is true;
+ attribute syn_preserve of current_INT_READ_OUT : signal is true;
+ attribute syn_keep of current_INT_READ_OUT : signal is true;
+ attribute syn_preserve of final_INT_READ_OUT : signal is true;
+ attribute syn_keep of final_INT_READ_OUT : signal is true;
+
+ attribute syn_hier : string;
+ attribute syn_hier of trb_net16_io_multiplexer_arch : architecture is "firm";
begin
-------------------------------------------------------------------------------
-- DEMUX
process(CLK)
begin
if rising_edge(CLK) then
- if RESET = '1' then
- buf_INT_DATA_OUT ((c_DATA_WIDTH)-1 downto 0) <= (others => '0');
- buf_INT_PACKET_NUM_OUT(c_NUM_WIDTH-1 downto 0) <= (others => '0');
- else
- buf_INT_DATA_OUT ((c_DATA_WIDTH)-1 downto 0) <= MED_DATA_IN;
- buf_INT_PACKET_NUM_OUT(c_NUM_WIDTH-1 downto 0) <= MED_PACKET_NUM_IN;
- end if;
+ buf_INT_DATA_OUT <= MED_DATA_IN & MED_DATA_IN & MED_DATA_IN & MED_DATA_IN;
+ buf_INT_PACKET_NUM_OUT <= MED_PACKET_NUM_IN & MED_PACKET_NUM_IN & MED_PACKET_NUM_IN & MED_PACKET_NUM_IN;
end if;
end process;
+
G2: for i in 0 to 2**(c_MUX_WIDTH-1)-1 generate
process(CLK)
begin
-- define next DRx
-- the output of the pattern generator is only valid for packet number 00!
--- DEFDR: trb_net_pattern_gen
--- generic map (
--- WIDTH => c_MUX_WIDTH-1
--- )
--- port map (
--- INPUT_IN => MED_DATA_IN(4+c_MUX_WIDTH-2 downto 4),
--- RESULT_OUT => next_demux_dr_tmp -- this will have a 1 in ANY case
--- );
+
gen_no_demux : if c_MUX_WIDTH = 1 generate
next_demux_dr_tmp <= (others => '1');
end generate;
end if;
end process;
--- process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if RESET = '1' then
--- final_INT_READ_OUT <= (others => '0');
--- elsif endpoint_locked = '0' then
--- final_INT_READ_OUT <= tmp_INT_READ_OUT;
--- end if;
--- end if;
--- end process;
-
process(CLK)
begin
if rising_edge(CLK) then
process(final_INT_READ_OUT, last_mux_enable)
begin
- current_INT_READ_OUT <= final_INT_READ_OUT;
if last_mux_enable = '0' then
current_INT_READ_OUT <= (others => '0');
+ else
+ current_INT_READ_OUT <= final_INT_READ_OUT;
end if;
end process;
--- current_INT_READ_OUT <= tmp_INT_READ_OUT when endpoint_locked = '0'
--- else final_INT_READ_OUT;
+
STAT(7 downto 0) <= INT_DATAREADY_IN(7 downto 0);
STAT(15 downto 8) <= current_INT_READ_OUT(7 downto 0);
-- attribute HGROUP of trb_net16_iobuf_arch : architecture is "IOBUF_group";
-
+ attribute syn_hier : string;
+ attribute syn_hier of trb_net16_iobuf_arch : architecture is "firm";
-- internal signals for the INITIBUF
signal IBUF_error: STD_LOGIC_VECTOR (2 downto 0); -- error watch needed!
CTRL_OP : in std_logic_vector(15 downto 0);
STAT_DEBUG : out std_logic_vector(63 downto 0)
);
+ attribute syn_useioff : boolean;
+ attribute syn_useioff of DATA_OUT : signal is true;
+ attribute syn_useioff of DATA_VALID_OUT : signal is true;
+ attribute syn_useioff of DATA_CTRL_OUT : signal is true;
+ attribute syn_useioff of DATA_IN : signal is true;
+ attribute syn_useioff of DATA_VALID_IN : signal is true;
+ attribute syn_useioff of DATA_CTRL_IN : signal is true;
+
end entity;
architecture trb_net16_med_16_CC_arch of trb_net16_med_16_CC is
);
end component;
+ signal buf_DATA_IN : std_logic_vector(15 downto 0);
+ signal buf_DATA_VALID_IN : std_logic;
+ signal buf_DATA_CTRL_IN : std_logic;
signal reg_DATA_IN : std_logic_vector(15 downto 0);
signal reg_DATA_VALID_IN : std_logic;
signal state_bits : std_logic_vector(2 downto 0);
signal make_reset : std_logic;
+
begin
-----------------------
--Receiver
-----------------------
+
+ PROC_RX_INPUT : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ buf_DATA_IN <= DATA_IN;
+ buf_DATA_VALID_IN <= DATA_VALID_IN;
+ buf_DATA_CTRL_IN <= DATA_CTRL_IN;
+ end if;
+ end process;
+
THE_RX_SIGNAL_SYNC: signal_sync
generic map(
DEPTH => 2,
)
port map(
RESET => RESET,
- D_IN(15 downto 0) => DATA_IN,
- D_IN(16) => DATA_VALID_IN,
- D_IN(17) => DATA_CTRL_IN,
+ D_IN(15 downto 0) => buf_DATA_IN,
+ D_IN(16) => buf_DATA_VALID_IN,
+ D_IN(17) => buf_DATA_CTRL_IN,
CLK0 => CLK,
CLK1 => CLK,
D_OUT(15 downto 0) => reg_DATA_IN,
attribute HGROUP : string;
-- for whole architecture
attribute HGROUP of trb_net16_obuf_arch : architecture is "OBUF_group";
+ attribute syn_hier : string;
+ attribute syn_hier of trb_net16_obuf_arch : architecture is "flatten, firm";
component trb_net16_sbuf is
generic (
USE IEEE.std_logic_UNSIGNED.ALL;
library work;
use work.trb_net_std.all;
+use work.trb_net_components.all;
--Custom Register in / out
REGISTERS_IN : in std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_STAT_REGS)-1 downto 0);
REGISTERS_OUT : out std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0);
+ --strobes for r/w operations on regio registers
+ COMMON_STAT_REG_STROBE : out std_logic_vector(2**(std_COMSTATREG)-1 downto 0);
+ COMMON_CTRL_REG_STROBE : out std_logic_vector(2**(std_COMCTRLREG)-1 downto 0);
+ STAT_REG_STROBE : out std_logic_vector(2**(NUM_STAT_REGS)-1 downto 0);
+ CTRL_REG_STROBE : out std_logic_vector(2**(NUM_CTRL_REGS)-1 downto 0);
--Internal Data Port
DAT_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0);
DAT_READ_ENABLE_OUT : out std_logic;
attribute HGROUP of trb_net16_regIO_arch : architecture is "RegIO_group";
- component trb_net_pattern_gen is
- generic (
- WIDTH : integer := 6
- );
- port(
- INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
- RESULT_OUT: out STD_LOGIC_VECTOR (2**WIDTH-1 downto 0)
- );
- end component;
-
- component trb_net16_addresses is
- generic(
- INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";
- INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";
- INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222";
- INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"
- );
- port(
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- API_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
- API_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
- API_DATAREADY_IN : in std_logic;
- API_READ_OUT : out std_logic;
- RAM_DATA_IN : in std_logic_vector(15 downto 0);
- RAM_DATA_OUT : out std_logic_vector(15 downto 0);
- RAM_ADDR_IN : in std_logic_vector(2 downto 0);
- RAM_WR_IN : in std_logic;
- API_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
- API_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
- API_DATAREADY_OUT : out std_logic;
- API_READ_IN : in std_logic;
- ADDRESS_REJECTED : out std_logic;
- DONT_UNDERSTAND_OUT : out std_logic;
- API_SEND_OUT : out std_logic;
- ADDRESS_OUT : out std_logic_vector(15 downto 0);
- STAT_DEBUG : out std_logic_vector(15 downto 0)
- );
- end component;
-
- component rom_16x8 is
- generic(
- INIT0 : std_logic_vector(15 downto 0) := x"0000";
- INIT1 : std_logic_vector(15 downto 0) := x"0000";
- INIT2 : std_logic_vector(15 downto 0) := x"0000";
- INIT3 : std_logic_vector(15 downto 0) := x"0000";
- INIT4 : std_logic_vector(15 downto 0) := x"0000";
- INIT5 : std_logic_vector(15 downto 0) := x"0000";
- INIT6 : std_logic_vector(15 downto 0) := x"0000";
- INIT7 : std_logic_vector(15 downto 0) := x"0000"
- );
- port(
- CLK : in std_logic;
- a : in std_logic_vector(2 downto 0);
- dout : out std_logic_vector(15 downto 0)
- );
- end component;
type fsm_state_t is (IDLE, HEADER_RECV, REG_READ, REG_WRITE, ONE_READ, ONE_WRITE, SEND_REPLY_SHORT_TRANSFER, MEM_START_WRITE,
MEM_READ, MEM_WRITE, DAT_START_READ, DAT_READ, SEND_REPLY_DATA_finish, ADDRESS_ACK, ADDRESS_RECV,
signal local_time_i : std_logic_vector(7 downto 0) := (others => '0');
signal us_tick_i : std_logic := '0';
signal global_time_write, next_global_time_write : std_logic;
-
+ signal next_COMMON_STAT_REG_STROBE : std_logic_vector(2**(std_COMSTATREG)-1 downto 0);
+ signal next_COMMON_CTRL_REG_STROBE : std_logic_vector(2**(std_COMCTRLREG)-1 downto 0);
+ signal next_next_COMMON_CTRL_REG_STROBE : std_logic_vector(2**(std_COMCTRLREG)-1 downto 0);
+ signal next_STAT_REG_STROBE : std_logic_vector(2**(NUM_STAT_REGS)-1 downto 0);
+ signal next_CTRL_REG_STROBE : std_logic_vector(2**(NUM_CTRL_REGS)-1 downto 0);
+ signal next_next_CTRL_REG_STROBE : std_logic_vector(2**(NUM_CTRL_REGS)-1 downto 0);
begin
next_API_READ_OUT <= '1';
next_dat_data_counter <= dat_data_counter;
next_global_time_write <= '0';
+ next_COMMON_STAT_REG_STROBE <= (others => '0');
+ next_next_COMMON_CTRL_REG_STROBE <= (others => '0');
+ next_STAT_REG_STROBE <= (others => '0');
+ next_next_CTRL_REG_STROBE <= (others => '0');
case current_state is
when IDLE =>
case address(7 downto 4) is
when x"C" | x"D" | x"E" | x"F" =>
next_REGISTERS_OUT_write_enable <= reg_enable_pattern(2**NUM_CTRL_REGS-1 downto 0);
+ next_next_CTRL_REG_STROBE(regnum_CTRL) <= API_READ_IN;
when x"2" | x"3" =>
next_COMMON_REGISTERS_OUT_write_enable <= reg_enable_pattern(std_COMCTRLREG-1 downto 0);
+ next_next_COMMON_CTRL_REG_STROBE(regnum_cCTRL) <= API_READ_IN;
when x"5" =>
if address(3 downto 0) = x"0" then
next_global_time_write <= '1';
case address(7 downto 4) is
when x"0" | x"1" =>
next_API_DATA_OUT <= COMMON_STAT_REG_IN(regnum_cSTAT*c_REGIO_REG_WIDTH+15 downto regnum_cSTAT*c_REGIO_REG_WIDTH);
+ next_COMMON_STAT_REG_STROBE(regnum_cSTAT) <= API_READ_IN;
when x"2" | x"3" =>
next_API_DATA_OUT <= buf_COMMON_CTRL_REG_OUT(regnum_cCTRL*c_REGIO_REG_WIDTH+15 downto regnum_cCTRL*c_REGIO_REG_WIDTH);
when x"4" =>
end case;
when x"8" | x"9" | x"A" | x"B" =>
next_API_DATA_OUT <= REGISTERS_IN(regnum_STAT*c_REGIO_REG_WIDTH+15 downto regnum_STAT*c_REGIO_REG_WIDTH);
+ next_STAT_REG_STROBE(regnum_STAT) <= API_READ_IN;
when x"C" | x"D" | x"E" | x"F" =>
next_API_DATA_OUT <= buf_REGISTERS_OUT(regnum_CTRL*c_REGIO_REG_WIDTH+15 downto regnum_CTRL*c_REGIO_REG_WIDTH);
when others =>
REGISTERS_OUT <= buf_REGISTERS_OUT;
COMMON_CTRL_REG_OUT <= buf_COMMON_CTRL_REG_OUT;
+
+ PROC_STROBES : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ COMMON_STAT_REG_STROBE <= next_COMMON_STAT_REG_STROBE;
+ COMMON_CTRL_REG_STROBE <= next_COMMON_CTRL_REG_STROBE;
+ STAT_REG_STROBE <= next_STAT_REG_STROBE;
+ CTRL_REG_STROBE <= next_CTRL_REG_STROBE;
+ next_COMMON_CTRL_REG_STROBE <= next_next_COMMON_CTRL_REG_STROBE;
+ next_CTRL_REG_STROBE <= next_next_CTRL_REG_STROBE;
+ end if;
+ end process;
+
+
+
buf_DAT_ADDR_OUT <= address;
buf_DAT_DATA_OUT <= saved_Reg_high & saved_Reg_low;
-- Placer Directives
attribute HGROUP : string;
-- for whole architecture
- attribute HGROUP of trb_net16_term_buf_arch : architecture is "IOBUF_group";
+ attribute HGROUP of trb_net16_term_buf_arch : architecture is "TRMBUF_group";
signal INIT_SEQNR, next_INIT_SEQNR : std_logic_vector(7 downto 0);
signal saved_packet_type : std_logic_vector(3 downto 0);
+ component trb_net16_addresses is
+ generic(
+ INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF";
+ INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";
+ INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222";
+ INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"
+ );
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ API_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ API_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ API_DATAREADY_IN : in std_logic;
+ API_READ_OUT : out std_logic;
+ RAM_DATA_IN : in std_logic_vector(15 downto 0);
+ RAM_DATA_OUT : out std_logic_vector(15 downto 0);
+ RAM_ADDR_IN : in std_logic_vector(2 downto 0);
+ RAM_WR_IN : in std_logic;
+ API_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ API_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ API_DATAREADY_OUT : out std_logic;
+ API_READ_IN : in std_logic;
+ ADDRESS_REJECTED : out std_logic;
+ DONT_UNDERSTAND_OUT : out std_logic;
+ API_SEND_OUT : out std_logic;
+ ADDRESS_OUT : out std_logic_vector(15 downto 0);
+ STAT_DEBUG : out std_logic_vector(15 downto 0)
+ );
+ end component;
+
+
+
+
+
+
component trb_net16_api_base is
generic (
API_TYPE : integer range 0 to 1 := c_API_PASSIVE;
LVL1_TRG_INFORMATION_OUT : out std_logic_vector(7 downto 0);
LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0) := x"00000000";
LVL1_TRG_RELEASE_IN : in std_logic := '0';
-
+ LVL1_INT_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0);
--Data Port
IPU_NUMBER_OUT : out std_logic_vector (15 downto 0);
REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
REGIO_REGISTERS_IN : in std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');
REGIO_REGISTERS_OUT : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
+
+ COMMON_STAT_REG_STROBE : out std_logic_vector(2**(std_COMSTATREG)-1 downto 0);
+ COMMON_CTRL_REG_STROBE : out std_logic_vector(2**(std_COMCTRLREG)-1 downto 0);
+ STAT_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);
+ CTRL_REG_STROBE : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
--following ports only used when using internal data port
REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0);
REGIO_READ_ENABLE_OUT : out std_logic;
+
+
+
component fifo_dualclock_width_16_reg is
port (
Data: in std_logic_vector(17 downto 0);
end component;
+
+
+
+
+
component trb_net16_ibuf is
generic (
DEPTH : integer range 0 to 7 := c_FIFO_BRAM;
MED_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
MED_READ_IN : in STD_LOGIC;
-- Internal direction port
- INT_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
- INT_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
+ INT_DATA_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0);
+ INT_PACKET_NUM_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0);
INT_DATAREADY_OUT : out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0);
INT_READ_IN : in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0);
INT_DATAREADY_IN : in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0);
+ component trb_net16_med_16_IC is
+ port(
+ CLK : in std_logic;
+ CLK_EN : in std_logic;
+ RESET : in std_logic;
+
+ --Internal Connection
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ MED_DATAREADY_IN : in std_logic;
+ MED_READ_OUT : out std_logic;
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ MED_DATAREADY_OUT : out std_logic;
+ MED_READ_IN : in std_logic;
+
+ DATA_OUT : out std_logic_vector(15 downto 0);
+ DATA_VALID_OUT : out std_logic;
+ DATA_CTRL_OUT : out std_logic;
+ DATA_CLK_OUT : out std_logic;
+ DATA_IN : in std_logic_vector(15 downto 0);
+ DATA_VALID_IN : in std_logic;
+ DATA_CTRL_IN : in std_logic;
+ DATA_CLK_IN : in std_logic;
+
+ STAT_OP : out std_logic_vector(15 downto 0);
+ CTRL_OP : in std_logic_vector(15 downto 0);
+ STAT_DEBUG : out std_logic_vector(63 downto 0)
+ );
+ end component;
+
+
+
component trb_net16_med_tlk is
port (
+ component trb_net_pattern_gen is
+ generic (
+ WIDTH : integer := 6
+ );
+ port(
+ INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
+ RESULT_OUT: out STD_LOGIC_VECTOR (2**WIDTH-1 downto 0)
+ );
+ end component;
+
+
+
+
+
component trb_net_priority_arbiter is
generic (
--Custom Register in / out
REGISTERS_IN : in std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_STAT_REGS)-1 downto 0);
REGISTERS_OUT : out std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0);
+ COMMON_STAT_REG_STROBE : out std_logic_vector(2**(std_COMSTATREG)-1 downto 0);
+ COMMON_CTRL_REG_STROBE : out std_logic_vector(2**(std_COMCTRLREG)-1 downto 0);
+ STAT_REG_STROBE : out std_logic_vector(2**(NUM_STAT_REGS)-1 downto 0);
+ CTRL_REG_STROBE : out std_logic_vector(2**(NUM_CTRL_REGS)-1 downto 0);
--Internal Data Port
DAT_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0);
DAT_READ_ENABLE_OUT : out std_logic;
+ component rom_16x8 is
+ generic(
+ INIT0 : std_logic_vector(15 downto 0) := x"0000";
+ INIT1 : std_logic_vector(15 downto 0) := x"0000";
+ INIT2 : std_logic_vector(15 downto 0) := x"0000";
+ INIT3 : std_logic_vector(15 downto 0) := x"0000";
+ INIT4 : std_logic_vector(15 downto 0) := x"0000";
+ INIT5 : std_logic_vector(15 downto 0) := x"0000";
+ INIT6 : std_logic_vector(15 downto 0) := x"0000";
+ INIT7 : std_logic_vector(15 downto 0) := x"0000"
+ );
+ port(
+ CLK : in std_logic;
+ a : in std_logic_vector(2 downto 0);
+ dout : out std_logic_vector(15 downto 0)
+ );
+ end component;
+
+
+
+
component trb_net16_sbuf is
generic (
signal state : state_t;
signal state_bits : std_logic_vector(3 downto 0);
+
+ -- Placer Directives
+ attribute HGROUP : string;
+ -- for whole architecture
+ attribute HGROUP of arch : architecture is "ONEWIRE_group";
+
+
begin
signal combined_COMB_DATAREADY_IN: std_logic;
signal use_current_b1_buffer: std_logic;
+ attribute syn_preserve : boolean;
+ attribute syn_keep : boolean;
+ attribute syn_preserve of current_SYN_DATAREADY_OUT : signal is true;
+ attribute syn_keep of current_SYN_DATAREADY_OUT : signal is true;
+ attribute syn_preserve of current_next_READ_OUT : signal is true;
+ attribute syn_keep of current_next_READ_OUT : signal is true;
+ attribute syn_hier : string;
+ attribute syn_hier of trb_net_sbuf_arch : architecture is "flatten, firm";
+
+
begin
SYN_DATA_OUT <= current_b2_buffer;
combined_COMB_DATAREADY_IN <= (COMB_DATAREADY_IN and COMB_READ_IN);
- GEN1: if VERSION = 0 generate
- MUX: process (use_current_b1_buffer,
- COMB_DATA_IN, current_b1_buffer)
+ MUX: process (use_current_b1_buffer,
+ COMB_DATA_IN, current_b1_buffer)
begin -- simple MUX
if use_current_b1_buffer = '1' then
next_b2_buffer <= current_b1_buffer;
next_b2_buffer <= COMB_DATA_IN;
end if;
end process;
- end generate;
- GEN2: if VERSION = 1 generate
- next_b2_buffer <= COMB_DATA_IN;
- end generate;
COMB: process (current_buffer_state, SYN_READ_IN, COMB_DATA_IN,
current_SYN_DATAREADY_OUT, current_got_overflow,
begin -- process COMB
next_buffer_state <= current_buffer_state;
next_next_READ_OUT <= '1';
- if VERSION = 0 then
- next_b1_buffer <= COMB_DATA_IN;
- move_b1_buffer <= '0';
- end if;
+ next_b1_buffer <= COMB_DATA_IN;
+ move_b1_buffer <= '0';
use_current_b1_buffer <= '0'; --by default COMB_DATA_IN;
move_b2_buffer <= '0';
if combined_COMB_DATAREADY_IN = '1' then
-- COMB logic is writing into the sbuf
next_buffer_state <= BUFFER_B2_FULL;
- if VERSION = 1 then
- next_next_READ_OUT <= '0';
- end if;
move_b2_buffer <= '1';
next_SYN_DATAREADY_OUT <= '1';
end if;
if combined_COMB_DATAREADY_IN = '1' and SYN_READ_IN = '1' then
-- COMB logic is writing into the sbuf
-- at the same time syn port is reading
- if VERSION = 1 then
- next_next_READ_OUT <= '0';
- end if;
move_b2_buffer <= '1';
next_SYN_DATAREADY_OUT <= '1';
elsif combined_COMB_DATAREADY_IN = '1' and SYN_READ_IN = '0' then
end if;
end if;
-
- -- for version1 it is more complicated: we have to gate
- -- the signal: when somebody is writing, we have to stop
- -- all the activity. I do this in the following way: If I
- -- promised to take the data, I stop the data taking in the
- -- following cycle. This reduces the bandwidth by a factor of
- -- 2
-
- if VERSION = 1 then
- if current_next_READ_OUT = '1' then
- next_next_READ_OUT <= '0';
- end if;
- end if;
-
end process COMB;
-- the next lines are an emergency stop
EM_STOP : process(current_next_READ_OUT, SYN_READ_IN, current_SYN_DATAREADY_OUT,
current_buffer_state)
begin
- if VERSION = 0 then
- if SYN_READ_IN = '0' and current_SYN_DATAREADY_OUT = '1' and current_buffer_state = BUFFER_B2_FULL then
- COMB_next_READ_OUT <= '0';
- elsif SYN_READ_IN = '1' and current_SYN_DATAREADY_OUT = '1' and current_buffer_state = BUFFER_B1_FULL then
- COMB_next_READ_OUT <= '1';
- else
- COMB_next_READ_OUT <= current_next_READ_OUT;
- end if;
+ if SYN_READ_IN = '0' and current_SYN_DATAREADY_OUT = '1' and current_buffer_state = BUFFER_B2_FULL then
+ COMB_next_READ_OUT <= '0';
+ elsif SYN_READ_IN = '1' and current_SYN_DATAREADY_OUT = '1' and current_buffer_state = BUFFER_B1_FULL then
+ COMB_next_READ_OUT <= '1';
else
COMB_next_READ_OUT <= current_next_READ_OUT;
end if;
end if;
end process;
- GEN6: if VERSION = 0 generate
- REG2 : process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- current_b1_buffer <= (others => '0');
- elsif move_b1_buffer = '1' then
- current_b1_buffer <= next_b1_buffer;
- end if;
+ REG2 : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if move_b1_buffer = '1' then
+ current_b1_buffer <= next_b1_buffer;
end if;
- end process;
- end generate;
+ end if;
+ end process;
REG3 : process(CLK)
begin
if rising_edge(CLK) then
- if RESET = '1' then
- current_b2_buffer <= (others => '0');
- elsif move_b2_buffer = '1' then
+ if move_b2_buffer = '1' then
current_b2_buffer <= next_b2_buffer;
end if;
end if;
jspc29 / trbnet.git / commitdiff