just a tiny change to the gray converter. Everything seems to be working still.

diff --git a/mupix/Mupix8/sources/Datapath/Gray2Binary.vhd b/mupix/Mupix8/sources/Datapath/Gray2Binary.vhd
index a16f3de2c7524ba86094542fdbbe9aab5127a156..087873fd6376904afcec56d42ecb732196b9e7e5 100644 (file)
--- a/mupix/Mupix8/sources/Datapath/Gray2Binary.vhd
+++ b/mupix/Mupix8/sources/Datapath/Gray2Binary.vhd
@@ -21,26 +21,33 @@ end gray_to_binary;
 
 architecture rtl of gray_to_binary is
 
+  signal decoded_i : std_logic_vector(NBITS - 1 downto 0) := (others => '0');
+
 begin
 
-  process(clk)
-    variable decoding : std_logic_vector(NBITS - 1 downto 0);
+  decode : process(gray_in)
+    variable decoded : std_logic_vector(NBITS - 1 downto 0);
+  begin
+      decoded(NBITS - 1) := gray_in(NBITS - 1);
+      for i in NBITS - 2 downto 0 loop
+        decoded(i) := gray_in(i) xor decoded(i + 1);
+      end loop;
+      decoded_i <= decoded;
+  end process decode;
+
+  seq_out : process(clk)
   begin
     if rising_edge(clk) then
       if reset = '1' then
         bin_out <= (others => '0');
       else
-        decoding(NBITS - 1) := gray_in(NBITS - 1);
-        for i in NBITS - 2 downto 0 loop
-          decoding(i) := gray_in(i) xor decoding(i + 1);
-        end loop;
         if bypass = '1' then
             bin_out <= gray_in;
         else
-            bin_out <= decoding;
+            bin_out <= decoded_i;
         end if;
       end if;
     end if;
-  end process;
+  end process seq_out;
 
 end rtl;

diff --git a/mupix/Mupix8/tb/DataDecoder_TB.vhd b/mupix/Mupix8/tb/DataDecoder_TB.vhd
index dd1997459fe0fea395a2fab4840d3f1732b10b83..cfb8564d97f540ebb5d67992fe572f05a34cd42e 100644 (file)
--- a/mupix/Mupix8/tb/DataDecoder_TB.vhd
+++ b/mupix/Mupix8/tb/DataDecoder_TB.vhd
@@ -10,10 +10,10 @@ use IEEE.NUMERIC_STD.ALL;
 
 entity DataDecoder_TB is
     generic (
-        D_W   : integer := 32;
-        Pix_W : integer := 8;
-        ToT_W : integer := 6;
-        TS_W  : integer := 10;
+        DWidth   : integer := 32;
+        PixWidth : integer := 8;
+        ToTWidth : integer := 6;
+        TSWidth  : integer := 10;
         LINKS : integer := 4;
         clkcyc: time    := 10 ns
     );
@@ -36,27 +36,27 @@ end component;
 
 component DataDecoder is
     generic (
-        D_W   : integer := 32;  -- width of full data word
-        Pix_W : integer := 8;   -- col/row address width
-        ToT_W : integer := 6;   -- time over threshold width
-        TS_W  : integer := 10;  -- timestamp width
+        DWidth   : integer := 32;
+        PixWidth : integer := 8;
+        ToTWidth : integer := 6;
+        TSWidth  : integer := 10;
         LINKS : integer := 4    -- number of links (data + counters)
     );
     port (
         clk           : in std_logic;
         reset         : in std_logic;
         bypass        : in std_logic;
-        datain        : in std_logic_vector(D_W - 1 downto 0);   -- incoming data word
+        datain        : in std_logic_vector(DWidth - 1 downto 0);   -- incoming data word
         datain_valid  : in std_logic;                            -- valid signal for input data
-        counterA_in   : in std_logic_vector(D_W - 1 downto 0);   -- last counter value link A
-        counterB_in   : in std_logic_vector(D_W - 1 downto 0);   -- last counter value link B
-        counterC_in   : in std_logic_vector(D_W - 1 downto 0);   -- last counter value link B
-        
-        dataout       : out std_logic_vector(D_W - 1 downto 0);  -- decoded data word
+        counterA_in   : in std_logic_vector(DWidth - 1 downto 0);   -- last counter value link A
+        counterB_in   : in std_logic_vector(DWidth - 1 downto 0);   -- last counter value link B
+        counterC_in   : in std_logic_vector(DWidth - 1 downto 0);   -- last counter value link B
+
+        dataout       : out std_logic_vector(DWidth - 1 downto 0);  -- decoded data word
         dataout_valid : out std_logic;                           -- valid output data
-        counterA_out  : out std_logic_vector(D_W - 1 downto 0);  -- last counter value link A
-        counterB_out  : out std_logic_vector(D_W - 1 downto 0);  -- last counter value link B
-        counterC_out  : out std_logic_vector(D_W - 1 downto 0)   -- last counter value link B
+        counterA_out  : out std_logic_vector(DWidth - 1 downto 0);  -- last counter value link A
+        counterB_out  : out std_logic_vector(DWidth - 1 downto 0);  -- last counter value link B
+        counterC_out  : out std_logic_vector(DWidth - 1 downto 0)   -- last counter value link B
     );
 end component;
 
@@ -65,20 +65,20 @@ signal reset               : std_logic                          := '0';
 signal bypass              : std_logic                          := '0';
 signal datain_filter       : std_logic_vector(39 downto 0)      := (others => '0');
 signal datain_v_filter     : std_logic                          := '0';
-signal datain_converter    : std_logic_vector(D_W - 1 downto 0) := (others => '0');
+signal datain_converter    : std_logic_vector(DWidth - 1 downto 0) := (others => '0');
 signal enable_converter    : std_logic                          := '0';
 signal counterA_valid_i    : std_logic                          := '0';
 signal counterB_valid_i    : std_logic                          := '0';
 signal counterC_valid_i    : std_logic                          := '0';
-signal ctrAin_converter    : std_logic_vector(D_W - 1 downto 0) := (others => '0');
-signal ctrBin_converter    : std_logic_vector(D_W - 1 downto 0) := (others => '0');
-signal ctrCin_converter    : std_logic_vector(D_W - 1 downto 0) := (others => '0');
+signal ctrAin_converter    : std_logic_vector(DWidth - 1 downto 0) := (others => '0');
+signal ctrBin_converter    : std_logic_vector(DWidth - 1 downto 0) := (others => '0');
+signal ctrCin_converter    : std_logic_vector(DWidth - 1 downto 0) := (others => '0');
 
-signal dataout_converter   : std_logic_vector(D_W - 1 downto 0);
+signal dataout_converter   : std_logic_vector(DWidth - 1 downto 0);
 signal dataout_v_converter : std_logic;
-signal ctrAout_converter   : std_logic_vector(D_W - 1 downto 0);
-signal ctrBout_converter   : std_logic_vector(D_W - 1 downto 0);
-signal ctrCout_converter   : std_logic_vector(D_W - 1 downto 0);
+signal ctrAout_converter   : std_logic_vector(DWidth - 1 downto 0);
+signal ctrBout_converter   : std_logic_vector(DWidth - 1 downto 0);
+signal ctrCout_converter   : std_logic_vector(DWidth - 1 downto 0);
 
 begin
 
@@ -94,15 +94,8 @@ begin
             counterB       => ctrBin_converter,
             counterC       => ctrCin_converter
         );
-    
+
     decoder : DataDecoder
-        generic map(
-            D_W   => D_W,
-            Pix_W => Pix_W,
-            ToT_W => ToT_W,
-            TS_W  => TS_W,
-            LINKS => LINKS
-        )
         port map (
             clk           => clk,
             reset         => reset,
@@ -124,7 +117,7 @@ begin
         wait for clkcyc/2;
         clk <= not clk;
     end process takt;
-    
+
     stim : process
     begin
         wait for 100 ns;
@@ -155,10 +148,10 @@ begin
         wait for clkcyc;
         datain_v_filter <= '0';
         wait for 10*clkcyc;
-        
+
         reset <= '1', '0' after 2*clkcyc;
         wait for 4*clkcyc;
-        
+
         -- now w/o converter
         bypass <= '1';
         wait for 2*clkcyc;