attribute syn_useioff of FPGA2_COMM : signal is true;
attribute syn_useioff of FPGA3_COMM : signal is true;
attribute syn_useioff of FPGA4_COMM : signal is true;
-
-
+ attribute syn_useioff of CLK_MNGR1_USER : signal is false;
+ attribute syn_useioff of CLK_MNGR2_USER : signal is false;
+ attribute syn_useioff of TRIGGER_SELECT : signal is false;
+ attribute syn_useioff of CLOCK_SELECT : signal is false;
end entity;
architecture trb3_central_arch of trb3_central is
signal cts_ext_trigger : std_logic;
signal cts_ext_status : std_logic_vector(31 downto 0) := (others => '0');
signal cts_ext_control : std_logic_vector(31 downto 0);
+ signal cts_ext_debug : std_logic_vector(31 downto 0);
signal cts_rdo_additional_data : std_logic_vector(31 downto 0);
signal cts_rdo_additional_write : std_logic := '0';
signal trigger_busy_i : std_logic;
signal trigger_in_buf_i : std_logic_vector(3 downto 0);
+ signal select_tc : std_logic_vector(31 downto 0);
+ signal select_tc_data_in : std_logic_vector(31 downto 0);
+ signal select_tc_write : std_logic;
+ signal select_tc_read : std_logic;
+ signal select_tc_ack : std_logic;
+
component mbs_vulom_recv is
port(
CLK : in std_logic; -- e.g. 100 MHz
FINISHED_OUT => cts_rdo_additional_finished,
CONTROL_REG_IN => cts_ext_control,
- STATUS_REG_OUT => cts_ext_status
+ STATUS_REG_OUT => cts_ext_status,
- -- DEBUG => ''
+ DEBUG => cts_ext_debug
);
trigger_in_buf_i(1 downto 0) <= CLK_EXT;
SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock
PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
RESET_IN => '0', -- general reset signal (SYSCLK)
- TRB_RESET_IN => '0', -- TRBnet reset signal (SYSCLK)
+ TRB_RESET_IN => trb_reset_in, -- TRBnet reset signal (SYSCLK)
CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!
RESET_OUT => reset_i_temp, -- synchronous reset out (SYSCLK)
DEBUG_OUT => open
);
-trb_reset_in <= reset_via_gbe_delayed(2) or MED_STAT_OP(4*16+13);
-reset_i <= reset_i_temp or trb_reset_in;
+trb_reset_in <= reset_via_gbe or MED_STAT_OP(4*16+13); --_delayed(2)
+reset_i <= reset_i_temp; -- or trb_reset_in;
process begin
wait until rising_edge(clk_100_i);
BROADCAST_SPECIAL_ADDR => x"35",
RDO_ADDITIONAL_PORT => c_YES,
RDO_DATA_BUFFER_DEPTH => 9,
- RDO_DATA_BUFFER_FULL_THRESH => 2**8,
+ RDO_DATA_BUFFER_FULL_THRESH => 2**9-128,
RDO_HEADER_BUFFER_DEPTH => 9,
- RDO_HEADER_BUFFER_FULL_THRESH => 2**8
+ RDO_HEADER_BUFFER_FULL_THRESH => 2**9-128
)
port map(
CLK => clk_100_i,
---------------------------------------------------------------------------
THE_BUS_HANDLER : trb_net16_regio_bus_handler
generic map(
- PORT_NUMBER => 5,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"8100", 3 => x"8300", 4 => x"a000", others => x"0000"),
- PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 8, 3 => 8, 4 => 9, others => 0)
+ PORT_NUMBER => 6,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"8100", 3 => x"8300", 4 => x"a000", 5 => x"d300", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 8, 3 => 8, 4 => 9, 5 => 0, others => 0)
)
port map(
CLK => clk_100_i,
BUS_WRITE_ACK_IN(4) => cts_regio_write_ack,
BUS_NO_MORE_DATA_IN(4) => '0',
BUS_UNKNOWN_ADDR_IN(4) => cts_regio_unknown_addr,
+
+ -- Trigger and Clock Manager Settings
+ BUS_ADDR_OUT(6*16-1 downto 5*16) => open,
+ BUS_DATA_OUT(6*32-1 downto 5*32) => select_tc_data_in,
+ BUS_READ_ENABLE_OUT(5) => select_tc_read,
+ BUS_WRITE_ENABLE_OUT(5) => select_tc_write,
+ BUS_TIMEOUT_OUT(5) => open,
+ BUS_DATA_IN(6*32-1 downto 5*32) => select_tc,
+ BUS_DATAREADY_IN(5) => select_tc_ack,
+ BUS_WRITE_ACK_IN(5) => select_tc_ack,
+ BUS_NO_MORE_DATA_IN(5) => '0',
+ BUS_UNKNOWN_ADDR_IN(5) => '0',
STAT_DEBUG => open
);
---------------------------------------------------------------------------
-- Clock and Trigger Configuration
---------------------------------------------------------------------------
- TRIGGER_SELECT <= '1'; --always internal trigger source
- CLOCK_SELECT <= '0'; --use on-board oscillator
- CLK_MNGR1_USER <= (others => '0');
- CLK_MNGR2_USER <= (others => '0');
+
+process begin
+ wait until rising_edge(clk_100_i);
+ if reset_i = '1' then
+ select_tc <= x"00000001"; --always internal trigger source
+ elsif select_tc_write = '1' then
+ select_tc <= select_tc_data_in;
+ end if;
+ select_tc_ack <= select_tc_read or select_tc_write;
+end process;
+
+ TRIGGER_SELECT <= select_tc(0);
+ CLOCK_SELECT <= select_tc(8); --use on-board oscillator
+ CLK_MNGR1_USER <= select_tc(19 downto 16);
+ CLK_MNGR2_USER <= select_tc(27 downto 24);
+
TRIGGER_OUT <= cts_trigger_out;
TRIGGER_OUT2 <= cts_trigger_out;
TEST_LINE(31 downto 0) <= (others => '0');
+-- TEST_LINE(31 downto 0) <= cts_ext_debug;
---------------------------------------------------------------------------
LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ; \r
LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ;\r
\r
+REGION "REGION_CTS" "R42C38D" 37 57 DEVSIZE;\r
+# UGROUP "cts_group" \r
+# BLKNAME THE_CTS;\r
+# LOCATE UGROUP "cts_group" REGION "REGION_CTS"; \r
+MULTICYCLE TO CELL "THE_CMB/trg_sync" 20 ns;\r
+\r
\r
#TrbNet Hub \r
-REGION "REGION_IOBUF" "R20C96D" 88 86 DEVSIZE;\r
+REGION "REGION_IOBUF" "R54C90D" 60 86 DEVSIZE;\r
LOCATE UGROUP "THE_HUB/THE_HUB/gen_muxes_0_MPLEX/MUX_group" REGION "REGION_IOBUF" ;\r
LOCATE UGROUP "THE_HUB/THE_HUB/gen_muxes_1_MPLEX/MUX_group" REGION "REGION_IOBUF" ;\r
LOCATE UGROUP "THE_HUB/THE_HUB/gen_muxes_2_MPLEX/MUX_group" REGION "REGION_IOBUF" ;\r
BLKNAME GBE/setup_imp_gen_SETUP;\r
\r
\r
-REGION "GBE_REGION" "R40C2D" 35 40 DEVSIZE;\r
-REGION "MED0" "R75C2D" 30 45 DEVSIZE;\r
+REGION "GBE_REGION" "R50C2D" 25 35 DEVSIZE;\r
+REGION "MED0" "R81C10D" 34 40 DEVSIZE;\r
LOCATE UGROUP "gbe_rx_tx" REGION "GBE_REGION" ;\r
FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/un1_PCS_SERDES_1" 125.000000 MHz ;\r
FREQUENCY NET "GBE/serdes_clk_125_c" 125.000000 MHz ;\r
-REGION "GBE_MAIN_REGION" "R74C50C" 38 36 DEVSIZE;\r
+REGION "GBE_MAIN_REGION" "R78C50C" 37 34 DEVSIZE;\r
LOCATE UGROUP "controllers" REGION "GBE_MAIN_REGION" ;\r
LOCATE UGROUP "tsmac" REGION "MED0" ;\r
BLOCK JTAGPATHS ;\r
jspc29 / trb3.git / commitdiff