entity med_ecp3_sfp_sync_125M is
generic(
SERDES_NUM : integer range 0 to 3 := 0;
- USE_RETRANSMISSION : integer := c_NO;
IS_SYNC_SLAVE : integer := c_NO --select slave mode
);
port(
attribute nopad : string;
attribute nopad of hdinp, hdinn, hdoutp, hdoutn : signal is "true";
-signal mii_tx_i : CTRLBUS_TX;
-signal mii_rx_i : CTRLBUS_RX;
-
-signal loc_bus_rx : CTRLBUS_RX;
-signal loc_bus_tx : CTRLBUS_TX;
-
begin
THE_MED_CONTROL : entity work.med_sync_control
generic map(
IS_SYNC_SLAVE => IS_SYNC_SLAVE,
- USE_RETRANSMISSION => USE_RETRANSMISSION,
IS_TX_RESET => 1
)
port map(
STAT_RX_CONTROL => stat_rx_control_i,
DEBUG_TX_CONTROL => debug_tx_control_i,
DEBUG_RX_CONTROL => debug_rx_control_i,
- STAT_RESET => stat_fsm_reset_i,
-
- BUS_RX => mii_rx_i,
- BUS_TX => mii_tx_i
-
+ STAT_RESET => stat_fsm_reset_i
);
THE_SCI_READER : entity work.sci_reader
--Slowcontrol
BUS_RX => BUS_RX,
BUS_TX => BUS_TX,
-
- LOC_BUS_RX => loc_BUS_RX,
- LOC_BUS_TX => loc_BUS_TX,
- --MEDIA_STATUS_REG_IN(31 downto 0) => stat_rx_control_i,
- --MEDIA_STATUS_REG_IN(63 downto 32) => stat_tx_control_i,
- --MEDIA_STATUS_REG_IN(95 downto 64) => stat_fsm_reset_i,
- --MEDIA_STATUS_REG_IN(255 downto 96) => (others => '0'),
+ MEDIA_STATUS_REG_IN(31 downto 0) => stat_rx_control_i,
+ MEDIA_STATUS_REG_IN(63 downto 32) => stat_tx_control_i,
+ MEDIA_STATUS_REG_IN(95 downto 64) => stat_fsm_reset_i,
+ MEDIA_STATUS_REG_IN(255 downto 96) => (others => '0'),
DEBUG_OUT => open
);
-
-BUS_WRITER : process
- begin
- wait until rising_edge(SYSCLK);
- loc_BUS_TX.unknown <= '0';
- loc_BUS_TX.rack <= '0';
- loc_BUS_TX.wack <= '0';
- loc_BUS_TX.data <= x"00000000";
- loc_BUS_TX.ack <= '0';
-
- mii_rx_i.data <= loc_BUS_RX.data;
- mii_rx_i.addr <= loc_BUS_RX.addr;
- mii_rx_i.read <= '0';
- mii_rx_i.write <= '0';
-
- if loc_BUS_RX.addr(2) = '0' then
- if loc_BUS_RX.read = '1' then
- loc_BUS_TX.ack <= '1';
--- case loc_BUS_RX.addr(4 downto 0) is
--- when "00000" => loc_BUS_TX.data <= stat_rx_control_i(31 downto 0);
--- when "00001" => loc_BUS_TX.data <= stat_tx_control_i(31 downto 0);
--- when "00010" => loc_BUS_TX.data <= stat_fsm_reset_i(31 downto 0);
- -- end case;
- end if;
- else
- if mii_tx_i.ack = '1' then
- loc_BUS_TX.data <= mii_tx_i.data;
- loc_BUS_TX.ack <= '1';
- loc_BUS_TX.unknown <= mii_tx_i.unknown;
- end if;
- mii_rx_i.read <= loc_BUS_RX.read;
- mii_rx_i.write <= loc_BUS_RX.write;
- end if;
-end process;
-
-
-- STAT_DEBUG(4 downto 0) <= debug_rx_control_i(4 downto 0);
-- STAT_DEBUG(6 downto 5) <= stat_fsm_reset_i(9 downto 8);
-- STAT_DEBUG(7) <= '0';
entity med_ecp3_sfp_sync_4_125M is
generic(
IS_SYNC_SLAVE : int_array_t(0 to 3) := (c_NO, c_NO, c_NO, c_NO); --select slave mode
- IS_USED : int_array_t(0 to 3) := (c_YES,c_YES,c_YES,c_YES);
- USE_RETRANSMISSION : integer := c_NO
+ IS_USED : int_array_t(0 to 3) := (c_YES,c_YES,c_YES,c_YES)
);
port(
CLK_REF_FULL : in std_logic; -- 200 MHz reference clock
SD_PRSNT_N_IN : in std_logic_vector(3 downto 0); -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
SD_LOS_IN : in std_logic_vector(3 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
SD_TXDIS_OUT : out std_logic_vector(3 downto 0); -- SFP disable
-
--Control Interface
BUS_RX : in CTRLBUS_RX;
BUS_TX : out CTRLBUS_TX;
-
+
-- Status and control port
STAT_DEBUG : out std_logic_vector (63 downto 0);
CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
signal debug_rx_control_i : std_logic_vector(4*32-1 downto 0);
signal debug_tx_control_i : std_logic_vector(4*32-1 downto 0);
signal stat_fsm_reset_i : std_logic_vector(4*32-1 downto 0);
-signal debug_retrans_i : std_logic_vector(4*32-1 downto 0);
-
+
signal hdinp, hdinn, hdoutp, hdoutn : std_logic_vector(3 downto 0);
attribute nopad : string;
attribute nopad of hdinp, hdinn, hdoutp, hdoutn : signal is "true";
-signal mii_tx_i : CTRLBUS_TX_array_t(0 to 3);
-signal mii_rx_i : CTRLBUS_RX_array_t(0 to 3);
-
-signal loc_bus_rx : CTRLBUS_RX;
-signal loc_bus_tx : CTRLBUS_TX;
-
type u8_arr is array (0 to 3) of unsigned(7 downto 0);
signal cv_cnt, cv_cnt_sys : u8_arr;
rst_qd_c => rst_qd(0),
serdes_rst_qd_c => '0',
tx_sync_qd_c => '0'
+
);
+
+
+
gen_control : for i in 0 to 3 generate
gen_used_control : if IS_USED(i) = c_YES generate
THE_MED_CONTROL : entity work.med_sync_control
generic map(
IS_SYNC_SLAVE => IS_SYNC_SLAVE(i),
- IS_TX_RESET => 1,
- USE_RETRANSMISSION => USE_RETRANSMISSION
+ IS_TX_RESET => 1
)
port map(
CLK_SYS => SYSCLK,
STAT_RX_CONTROL => stat_rx_control_i(i*32+31 downto i*32),
DEBUG_TX_CONTROL => debug_tx_control_i(i*32+31 downto i*32),
DEBUG_RX_CONTROL => debug_rx_control_i(i*32+31 downto i*32),
- STAT_RESET => stat_fsm_reset_i(i*32+31 downto i*32),
-
- DEBUG_RETRANS_OUT => debug_retrans_i(i*32+31 downto i*32),
-
- BUS_RX => mii_rx_i(i),
- BUS_TX => mii_tx_i(i)
+ STAT_RESET => stat_fsm_reset_i(i*32+31 downto i*32)
);
cv_cnt(i) <= cv_cnt(i) + 1 when rx_error(i) = '1' and rising_edge(clk_rx_full(i));
MEDIA_MED2INT(i).dataready <= '0';
MEDIA_MED2INT(i).tx_read <= '1';
MEDIA_MED2INT(i).stat_op <= x"0007";
- mii_tx_i(i).data <= x"00000000";
- mii_tx_i(i).ack <= '0';
end generate;
end generate;
--Slowcontrol
BUS_RX => BUS_RX,
BUS_TX => BUS_TX,
-
- LOC_BUS_RX => loc_BUS_RX,
- LOC_BUS_TX => loc_BUS_TX,
-
- --MEDIA_STATUS_REG_IN(31 downto 0) => stat_rx_control_i(31 downto 0),
- --MEDIA_STATUS_REG_IN(63 downto 32) => stat_tx_control_i(31 downto 0),
-
- --MEDIA_STATUS_REG_IN(191 downto 64) => stat_fsm_reset_i(127 downto 0),
- --MEDIA_STATUS_REG_IN(199 downto 192) => cv_cnt_sys(0),
- --MEDIA_STATUS_REG_IN(207 downto 200) => cv_cnt_sys(1),
- --MEDIA_STATUS_REG_IN(215 downto 208) => cv_cnt_sys(2),
- --MEDIA_STATUS_REG_IN(223 downto 216) => cv_cnt_sys(3),
+ MEDIA_STATUS_REG_IN(31 downto 0) => stat_rx_control_i(31 downto 0),
+ MEDIA_STATUS_REG_IN(63 downto 32) => stat_tx_control_i(31 downto 0),
+ MEDIA_STATUS_REG_IN(191 downto 64) => stat_fsm_reset_i(127 downto 0),
+ MEDIA_STATUS_REG_IN(199 downto 192) => cv_cnt_sys(0),
+ MEDIA_STATUS_REG_IN(207 downto 200) => cv_cnt_sys(1),
+ MEDIA_STATUS_REG_IN(215 downto 208) => cv_cnt_sys(2),
+ MEDIA_STATUS_REG_IN(223 downto 216) => cv_cnt_sys(3),
- --MEDIA_STATUS_REG_IN(255 downto 224) => (others => '0'),
-
- --MEDIA_STATUS_REG_IN(383 downto 256) => debug_retrans_i,
- --MEDIA_STATUS_REG_IN(511 downto 384) => (others => '0'),
-
+ MEDIA_STATUS_REG_IN(255 downto 224) => (others => '0'),
DEBUG_OUT => open
);
-BUS_WRITER : process
- begin
- wait until rising_edge(SYSCLK);
- loc_BUS_TX.unknown <= '0';
- loc_BUS_TX.rack <= '0';
- loc_BUS_TX.wack <= '0';
- loc_BUS_TX.data <= x"00000000";
- loc_BUS_TX.ack <= '0';
- mii_rx_i(0).data <= loc_BUS_RX.data;
- mii_rx_i(1).data <= loc_BUS_RX.data;
- mii_rx_i(2).data <= loc_BUS_RX.data;
- mii_rx_i(3).data <= loc_BUS_RX.data;
- mii_rx_i(0).addr <= loc_BUS_RX.addr;
- mii_rx_i(1).addr <= loc_BUS_RX.addr;
- mii_rx_i(2).addr <= loc_BUS_RX.addr;
- mii_rx_i(3).addr <= loc_BUS_RX.addr;
- mii_rx_i(0).read <= '0';
- mii_rx_i(1).read <= '0';
- mii_rx_i(2).read <= '0';
- mii_rx_i(3).read <= '0';
- mii_rx_i(0).write <= '0';
- mii_rx_i(1).write <= '0';
- mii_rx_i(2).write <= '0';
- mii_rx_i(3).write <= '0';
-
- --000 stat
- --001
- --010
- --011
- --100 med_ctrl
- -- ...
- --111
-
- if loc_BUS_RX.addr(2) = '0' then
- if loc_BUS_RX.read = '1' then
- loc_BUS_TX.ack <= '1';
- case loc_BUS_RX.addr(4 downto 0) is
- --when "00000" => loc_BUS_TX.data <= stat_rx_control_i(31 downto 0);
- --when "00001" => loc_BUS_TX.data <= stat_tx_control_i(31 downto 0);
- --when "01000" => loc_BUS_TX.data <= stat_rx_control_i(63 downto 32);
- --when "01001" => loc_BUS_TX.data <= stat_tx_control_i(63 downto 32);
- --when "10000" => loc_BUS_TX.data <= stat_rx_control_i(95 downto 64);
- --when "10001" => loc_BUS_TX.data <= stat_tx_control_i(95 downto 64);
- --when "11000" => loc_BUS_TX.data <= stat_rx_control_i(127 downto 96);
- --when "11001" => loc_BUS_TX.data <= stat_tx_control_i(127 downto 96);
-
- --when "00010" => loc_BUS_TX.data <= stat_fsm_reset_i(31 downto 0);
-
- when "00011" => loc_BUS_TX.data <= x"000000" & std_logic_vector(cv_cnt_sys(0));
- when "01011" => loc_BUS_TX.data <= x"000000" & std_logic_vector(cv_cnt_sys(1));
- when "10011" => loc_BUS_TX.data <= x"000000" & std_logic_vector(cv_cnt_sys(2));
- when "11011" => loc_BUS_TX.data <= x"000000" & std_logic_vector(cv_cnt_sys(3));
- end case;
- end if;
- else
- if mii_tx_i(0).ack = '1' then
- loc_BUS_TX.data <= mii_tx_i(0).data;
- loc_BUS_TX.ack <= '1';
- loc_BUS_TX.unknown <= mii_tx_i(0).unknown;
- elsif mii_tx_i(1).ack = '1' then
- loc_BUS_TX.data <= mii_tx_i(1).data;
- loc_BUS_TX.ack <= '1';
- loc_BUS_TX.unknown <= mii_tx_i(1).unknown;
- elsif mii_tx_i(2).ack = '1' then
- loc_BUS_TX.data <= mii_tx_i(2).data;
- loc_BUS_TX.ack <= '1';
- loc_BUS_TX.unknown <= mii_tx_i(2).unknown;
- elsif mii_tx_i(3).ack = '1' then
- loc_BUS_TX.data <= mii_tx_i(3).data;
- loc_BUS_TX.ack <= '1';
- loc_BUS_TX.unknown <= mii_tx_i(3).unknown;
- end if;
- if loc_BUS_RX.read = '1' then
- if loc_BUS_RX.addr(4 downto 3) = "00" then
- mii_rx_i(0).read <= '1';
- elsif loc_BUS_RX.addr(4 downto 3) = "01" then
- mii_rx_i(1).read <= '1';
- elsif loc_BUS_RX.addr(4 downto 3) = "10" then
- mii_rx_i(2).read <= '1';
- elsif loc_BUS_RX.addr(4 downto 3) = "11" then
- mii_rx_i(3).read <= '1';
- end if;
- elsif loc_BUS_RX.write = '1' then
- if loc_BUS_RX.addr(4 downto 3) = "00" then
- mii_rx_i(0).write <= '1';
- elsif loc_BUS_RX.addr(4 downto 3) = "01" then
- mii_rx_i(1).write <= '1';
- elsif loc_BUS_RX.addr(4 downto 3) = "10" then
- mii_rx_i(2).write <= '1';
- elsif loc_BUS_RX.addr(4 downto 3) = "11" then
- mii_rx_i(3).write <= '1';
- end if;
- end if;
- end if;
-end process;
-
-
cv_cnt_sys <= cv_cnt when rising_edge(SYSCLK);
wa_position <= (others => '0');
entity med_ecp3_sfp_sync_4_slave3_125M is
generic(
IS_SYNC_SLAVE : int_array_t(0 to 3) := (c_NO, c_NO, c_NO, c_NO); --select slave mode
- IS_USED : int_array_t(0 to 3) := (c_YES,c_YES,c_YES,c_YES);
- USE_RETRANSMISSION : integer := c_NO;
- REG_OFFSET : std_logic_vector(7 downto 0) := x"00"
- );
+ IS_USED : int_array_t(0 to 3) := (c_YES,c_YES,c_YES,c_YES)
+ );
port(
- CLK_REF_FULL : in std_logic; -- 200 MHz reference clock
- CLK_INTERNAL_FULL : in std_logic; -- internal 200 MHz, always on
+ CLK_REF_FULL : in std_logic; -- 125 MHz reference clock
+ CLK_INTERNAL_FULL : in std_logic; -- internal 125 MHz, always on
SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
RESET : in std_logic; -- synchronous reset
CLEAR : in std_logic; -- asynchronous reset
+
--Internal Connection TX
MEDIA_MED2INT : out med2int_array_t(0 to 3);
MEDIA_INT2MED : in int2med_array_t(0 to 3);
signal debug_rx_control_i : std_logic_vector(4*32-1 downto 0);
signal debug_tx_control_i : std_logic_vector(4*32-1 downto 0);
signal stat_fsm_reset_i : std_logic_vector(4*32-1 downto 0);
-signal debug_retrans_i : std_logic_vector(4*32-1 downto 0);
-
+
signal hdinp, hdinn, hdoutp, hdoutn : std_logic_vector(3 downto 0);
attribute nopad : string;
attribute nopad of hdinp, hdinn, hdoutp, hdoutn : signal is "true";
-signal mii_tx_i : CTRLBUS_TX_array_t(0 to 3);
-signal mii_rx_i : CTRLBUS_RX_array_t(0 to 3);
-
-signal loc_bus_rx : CTRLBUS_RX;
-signal loc_bus_tx : CTRLBUS_TX;
-
-
begin
SD_TXDIS_OUT <= (others =>'0'); --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready
hdinn_ch0 => hdinn (0),
hdoutp_ch0 => hdoutp(0),
hdoutn_ch0 => hdoutn(0),
- txiclk_ch0 => CLK_REF_FULL, --clk_tx_full(0),
- rxiclk_ch0 => clk_rx_full(0), --CLK_REF_FULL,
+ txiclk_ch0 => CLK_REF_FULL,
+ rxiclk_ch0 => clk_rx_full(0),
rx_full_clk_ch0 => clk_rx_full(0),
rx_half_clk_ch0 => clk_rx_half(0),
tx_full_clk_ch0 => clk_tx_full(0),
hdinn_ch1 => hdinn (1),
hdoutp_ch1 => hdoutp(1),
hdoutn_ch1 => hdoutn(1),
- txiclk_ch1 => CLK_REF_FULL, --clk_tx_full(1),
- rxiclk_ch1 => clk_rx_full(1), --CLK_REF_FULL,
+ txiclk_ch1 => CLK_REF_FULL,
+ rxiclk_ch1 => clk_rx_full(1),
rx_full_clk_ch1 => clk_rx_full(1),
rx_half_clk_ch1 => clk_rx_half(1),
tx_full_clk_ch1 => clk_tx_full(1),
hdinn_ch2 => hdinn (2),
hdoutp_ch2 => hdoutp(2),
hdoutn_ch2 => hdoutn(2),
- txiclk_ch2 => CLK_REF_FULL, --clk_tx_full(2),
- rxiclk_ch2 => clk_rx_full(2), --CLK_REF_FULL,
+ txiclk_ch2 => CLK_REF_FULL,
+ rxiclk_ch2 => clk_rx_full(2),
rx_full_clk_ch2 => clk_rx_full(2),
rx_half_clk_ch2 => clk_rx_half(2),
tx_full_clk_ch2 => clk_tx_full(2),
hdinn_ch3 => hdinn (3),
hdoutp_ch3 => hdoutp(3),
hdoutn_ch3 => hdoutn(3),
- txiclk_ch3 => CLK_REF_FULL, --clk_tx_full(3),
- rxiclk_ch3 => clk_rx_full(3), --CLK_REF_FULL,
- rx_full_clk_ch3 => clk_rx_full(3), --clk_rx_full(3),
+ txiclk_ch3 => CLK_REF_FULL,
+ rxiclk_ch3 => clk_rx_full(3),
+ rx_full_clk_ch3 => clk_rx_full(3),
rx_half_clk_ch3 => clk_rx_half(3),
tx_full_clk_ch3 => clk_tx_full(3),
tx_half_clk_ch3 => clk_tx_half(3),
rst_qd_c => rst_qd(0),
serdes_rst_qd_c => '0',
tx_sync_qd_c => '0'
- );
--- clk_rxi <= (0 => CLK_REF_FULL,1 => CLK_REF_FULL,2 => CLK_REF_FULL,3 => clk_rx_full(3));
-
+ );
+
gen_control : for i in 0 to 3 generate
gen_used_control : if IS_USED(i) = c_YES generate
THE_MED_CONTROL : entity work.med_sync_control
generic map(
IS_SYNC_SLAVE => IS_SYNC_SLAVE(i),
- IS_TX_RESET => 1,
- USE_RETRANSMISSION => USE_RETRANSMISSION
+ IS_TX_RESET => 1
)
port map(
CLK_SYS => SYSCLK,
STAT_RX_CONTROL => stat_rx_control_i(i*32+31 downto i*32),
DEBUG_TX_CONTROL => debug_tx_control_i(i*32+31 downto i*32),
DEBUG_RX_CONTROL => debug_rx_control_i(i*32+31 downto i*32),
- STAT_RESET => stat_fsm_reset_i(i*32+31 downto i*32),
-
- DEBUG_RETRANS_OUT => debug_retrans_i(i*32+31 downto i*32),
-
- BUS_RX => mii_rx_i(i),
- BUS_TX => mii_tx_i(i)
+ STAT_RESET => stat_fsm_reset_i(i*32+31 downto i*32)
);
end generate;
MEDIA_MED2INT(i).dataready <= '0';
MEDIA_MED2INT(i).tx_read <= '1';
MEDIA_MED2INT(i).stat_op <= x"0007";
- mii_tx_i(i).data <= x"00000000";
- mii_tx_i(i).ack <= '0';
end generate;
end generate;
--Slowcontrol
BUS_RX => BUS_RX,
BUS_TX => BUS_TX,
-
- LOC_BUS_RX => loc_BUS_RX,
- LOC_BUS_TX => loc_BUS_TX,
-
- --MEDIA_STATUS_REG_IN(31 downto 0) => stat_rx_control_i(31 downto 0),
- --MEDIA_STATUS_REG_IN(63 downto 32) => stat_tx_control_i(31 downto 0),
- --MEDIA_STATUS_REG_IN(95 downto 64) => stat_fsm_reset_i(31 downto 0),
- --MEDIA_STATUS_REG_IN(255 downto 96) => (others => '0'),
-
- --MEDIA_STATUS_REG_IN(383 downto 256) => debug_retrans_i,
- --MEDIA_STATUS_REG_IN(511 downto 384) => (others => '0'),
-
+ MEDIA_STATUS_REG_IN(31 downto 0) => stat_rx_control_i(31 downto 0),
+ MEDIA_STATUS_REG_IN(63 downto 32) => stat_tx_control_i(31 downto 0),
+ MEDIA_STATUS_REG_IN(95 downto 64) => stat_fsm_reset_i(31 downto 0),
+ MEDIA_STATUS_REG_IN(255 downto 96) => (others => '0'),
DEBUG_OUT => open
);
-BUS_WRITER : process
- begin
- wait until rising_edge(SYSCLK);
- loc_BUS_TX.unknown <= '0';
- loc_BUS_TX.rack <= '0';
- loc_BUS_TX.wack <= '0';
- loc_BUS_TX.data <= x"00000000";
- loc_BUS_TX.ack <= '0';
- mii_rx_i(0).data <= loc_BUS_RX.data;
- mii_rx_i(1).data <= loc_BUS_RX.data;
- mii_rx_i(2).data <= loc_BUS_RX.data;
- mii_rx_i(3).data <= loc_BUS_RX.data;
- mii_rx_i(0).addr <= loc_BUS_RX.addr;
- mii_rx_i(1).addr <= loc_BUS_RX.addr;
- mii_rx_i(2).addr <= loc_BUS_RX.addr;
- mii_rx_i(3).addr <= loc_BUS_RX.addr;
- mii_rx_i(0).read <= '0';
- mii_rx_i(1).read <= '0';
- mii_rx_i(2).read <= '0';
- mii_rx_i(3).read <= '0';
- mii_rx_i(0).write <= '0';
- mii_rx_i(1).write <= '0';
- mii_rx_i(2).write <= '0';
- mii_rx_i(3).write <= '0';
-
- if loc_BUS_RX.addr(2) = '0' then
- if loc_BUS_RX.read = '1' then
- loc_BUS_TX.ack <= '1';
- case loc_BUS_RX.addr(4 downto 0) is
- when "00000" => loc_BUS_TX.data <= stat_rx_control_i(31 downto 0);
- when "00001" => loc_BUS_TX.data <= stat_tx_control_i(31 downto 0);
- when "00010" => loc_BUS_TX.data <= stat_fsm_reset_i(31 downto 0);
- end case;
- end if;
- else
- if mii_tx_i(0).ack = '1' then
- loc_BUS_TX.data <= mii_tx_i(0).data;
- loc_BUS_TX.ack <= '1';
- loc_BUS_TX.unknown <= mii_tx_i(0).unknown;
- elsif mii_tx_i(1).ack = '1' then
- loc_BUS_TX.data <= mii_tx_i(1).data;
- loc_BUS_TX.ack <= '1';
- loc_BUS_TX.unknown <= mii_tx_i(1).unknown;
- elsif mii_tx_i(2).ack = '1' then
- loc_BUS_TX.data <= mii_tx_i(2).data;
- loc_BUS_TX.ack <= '1';
- loc_BUS_TX.unknown <= mii_tx_i(2).unknown;
- elsif mii_tx_i(3).ack = '1' then
- loc_BUS_TX.data <= mii_tx_i(3).data;
- loc_BUS_TX.ack <= '1';
- loc_BUS_TX.unknown <= mii_tx_i(3).unknown;
- end if;
- if loc_BUS_RX.read = '1' then
- if loc_BUS_RX.addr(4 downto 3) = "00" then
- mii_rx_i(0).read <= '1';
- elsif loc_BUS_RX.addr(4 downto 3) = "01" then
- mii_rx_i(1).read <= '1';
- elsif loc_BUS_RX.addr(4 downto 3) = "10" then
- mii_rx_i(2).read <= '1';
- elsif loc_BUS_RX.addr(4 downto 3) = "11" then
- mii_rx_i(3).read <= '1';
- end if;
- elsif loc_BUS_RX.write = '1' then
- if loc_BUS_RX.addr(4 downto 3) = "00" then
- mii_rx_i(0).write <= '1';
- elsif loc_BUS_RX.addr(4 downto 3) = "01" then
- mii_rx_i(1).write <= '1';
- elsif loc_BUS_RX.addr(4 downto 3) = "10" then
- mii_rx_i(2).write <= '1';
- elsif loc_BUS_RX.addr(4 downto 3) = "11" then
- mii_rx_i(3).write <= '1';
- end if;
- end if;
- end if;
-
-
-end process;
-
wa_position <= (others => '0');
STAT_DEBUG(13 downto 0) <= debug_tx_control_i(13 downto 0);
---Media interface for Lattice ECP5 using PCS at 2GHz
+-- Media interface for Lattice ECP5 using PCS at 1.25GHz
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
entity med_ecp5_sfp_sync_125M is
generic(
SERDES_NUM : integer range 0 to 3 := 0;
- USE_RETRANSMISSION : integer := c_NO;
- IS_SYNC_SLAVE : integer := c_YES --select slave mode
- );
+ IS_SYNC_SLAVE : integer := c_YES -- select slave mode
+ );
port(
- CLK_REF_FULL : in std_logic; -- 200 MHz reference clock
- CLK_INTERNAL_FULL : in std_logic; -- internal 200 MHz, always on
+ CLK_REF_FULL : in std_logic; -- 125 MHz reference clock
+ CLK_INTERNAL_FULL : in std_logic; -- internal 125 MHz, always on
SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
RESET : in std_logic; -- synchronous reset
CLEAR : in std_logic; -- asynchronous reset
- --Internal Connection TX
+ -- Internal Connection TX
MEDIA_MED2INT : out MED2INT;
MEDIA_INT2MED : in INT2MED;
-
- --Sync operation
+ -- Sync operation
RX_DLM : out std_logic := '0';
RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00";
TX_DLM : in std_logic := '0';
TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00";
-
- --SFP Connection
+ -- SFP Connection
SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable
-
- --Control Interface
+ -- Control Interface
BUS_RX : in CTRLBUS_RX;
BUS_TX : out CTRLBUS_TX;
-
-- Status and control port
STAT_DEBUG : out std_logic_vector (63 downto 0);
CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
- );
+ );
end entity;
-
architecture med_ecp5_sfp_sync_arch of med_ecp5_sfp_sync_125M is
-- Placer Directives
attribute syn_hier : string;
attribute syn_hier of med_ecp5_sfp_sync_arch : architecture is "hard";
-signal clk_200_ref : std_logic;
signal clk_rx_full : std_logic;
signal clk_tx_full : std_logic;
signal reset_n : std_logic;
signal stat_med : std_logic_vector(31 downto 0);
-signal mii_tx_i : CTRLBUS_TX;
-signal mii_rx_i : CTRLBUS_RX;
-
-signal loc_bus_rx : CTRLBUS_RX;
-signal loc_bus_tx : CTRLBUS_TX;
-
-
begin
reset_n <= not RESET;
-clk_200_ref <= CLK_REF_FULL;
SD_TXDIS_OUT <= not rx_ready when IS_SYNC_SLAVE = 1 else '0'; --slave only switches on when RX is ready
--- gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
--- clk_200_i <= clk_rx_full;
--- end generate;
---
--- gen_master_clock : if IS_SYNC_SLAVE = c_NO generate
--- clk_200_i <= clk_200_internal;
--- end generate;
-
-------------------------------------------------
-- Serdes
-------------------------------------------------
-gen_pcs0 : if SERDES_NUM = SERDES_NUM generate -- same entity in any case
+gen_pcs0 : if SERDES_NUM = 0 or SERDES_NUM = 1 generate -- same entity in any case
THE_SERDES : entity work.pcs_125M
port map(
serdes_sync_0_hdinp => hdinp,
serdes_sync_0_tx_pcs_rst_c => tx_pcs_rst,
serdes_sync_0_rx_serdes_rst_c => rx_serdes_rst,
-
serdes_sync_0_sci_wrdata => sci_data_in_i,
serdes_sync_0_sci_rddata => sci_data_out_i,
serdes_sync_0_sci_addr => sci_addr_i,
serdes_sync_0_rsl_rst => '0',
serdes_sync_0_rsl_rx_rdy => rx_ready,
serdes_sync_0_rsl_tx_rdy => tx_ready
- );
+ );
end generate;
assert not(SERDES_NUM > 1) report "ECP5 SerDes 125MHz not yet defined" severity failure;
THE_MED_CONTROL : entity work.med_sync_control
generic map(
IS_SYNC_SLAVE => IS_SYNC_SLAVE,
- USE_RETRANSMISSION => USE_RETRANSMISSION,
IS_TX_RESET => 1
- )
+ )
port map(
CLK_SYS => SYSCLK,
CLK_RXI => clk_rx_full,
DEBUG_TX_CONTROL => debug_tx_control_i,
DEBUG_RX_CONTROL => debug_rx_control_i,
STAT_RESET => stat_fsm_reset_i,
- DEBUG_OUT => debug_med_sync_control_i,
-
- BUS_RX => mii_rx_i,
- BUS_TX => mii_tx_i
- );
+ DEBUG_OUT => debug_med_sync_control_i
+ );
THE_SCI_READER : entity work.sci_reader
port map(
CLK => SYSCLK,
RESET => RESET,
-
- --SCI
+ -- SCI
SCI_WRDATA => sci_data_in_i,
SCI_RDDATA => sci_data_out_i,
SCI_ADDR => sci_addr_i,
SCI_SEL => sci_ch_i,
SCI_RD => sci_read_i,
SCI_WR => sci_write_i,
-
WA_POS_OUT => wa_position,
-
- --Slowcontrol
+ -- Slowcontrol
BUS_RX => BUS_RX,
BUS_TX => BUS_TX,
-
- LOC_BUS_RX => loc_BUS_RX,
- LOC_BUS_TX => loc_BUS_TX,
-
- --MEDIA_STATUS_REG_IN(31 downto 0) => stat_rx_control_i,
- --MEDIA_STATUS_REG_IN(63 downto 32) => stat_tx_control_i,
- --MEDIA_STATUS_REG_IN(95 downto 64) => stat_fsm_reset_i,
- --MEDIA_STATUS_REG_IN(127 downto 96) => stat_med,
- --MEDIA_STATUS_REG_IN(255 downto 128) => (others => '0'),
+ --
+ MEDIA_STATUS_REG_IN(31 downto 0) => stat_rx_control_i,
+ MEDIA_STATUS_REG_IN(63 downto 32) => stat_tx_control_i,
+ MEDIA_STATUS_REG_IN(95 downto 64) => stat_fsm_reset_i,
+ MEDIA_STATUS_REG_IN(127 downto 96) => stat_med,
+ MEDIA_STATUS_REG_IN(255 downto 128) => (others => '0'),
DEBUG_OUT => open
- );
-
+ );
-BUS_WRITER : process
- begin
- wait until rising_edge(SYSCLK);
- loc_BUS_TX.unknown <= '0';
- loc_BUS_TX.rack <= '0';
- loc_BUS_TX.wack <= '0';
- loc_BUS_TX.data <= x"00000000";
- loc_BUS_TX.ack <= '0';
-
- mii_rx_i.data <= loc_BUS_RX.data;
- mii_rx_i.addr <= loc_BUS_RX.addr;
- mii_rx_i.read <= '0';
- mii_rx_i.write <= '0';
-
- if loc_BUS_RX.addr(2) = '0' then
- if loc_BUS_RX.read = '1' then
- loc_BUS_TX.ack <= '1';
- loc_BUS_TX.unknown <= '1';
--- case loc_BUS_RX.addr(4 downto 0) is
--- when "00000" => loc_BUS_TX.data <= stat_rx_control_i(31 downto 0);
--- when "00001" => loc_BUS_TX.data <= stat_tx_control_i(31 downto 0);
--- when "00010" => loc_BUS_TX.data <= stat_fsm_reset_i(31 downto 0);
--- end case;
- end if;
- else
- if mii_tx_i.ack = '1' then
- loc_BUS_TX.data <= mii_tx_i.data;
- loc_BUS_TX.ack <= '1';
- loc_BUS_TX.unknown <= mii_tx_i.unknown;
- end if;
- mii_rx_i.read <= loc_BUS_RX.read;
- mii_rx_i.write <= loc_BUS_RX.write;
- end if;
-end process;
-
-
STAT_DEBUG(11 downto 0) <= debug_med_sync_control_i(11 downto 0);
STAT_DEBUG(15 downto 12) <= (others => '0');
STAT_DEBUG(31 downto 16) <= wa_position;
STAT_DEBUG(63 downto 32) <= (others => '0');
-
stat_med(0) <= rst_qd;
stat_med(1) <= rx_pcs_rst;
stat_med(2) <= tx_pcs_rst;
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