rx/tx_reset_fsm: Synchronize reset input

The asynchronous reset inputs were used without synchronization to reset
both state machines, leading to potential errors.

diff --git a/media_interfaces/sync/rx_reset_fsm.vhd b/media_interfaces/sync/rx_reset_fsm.vhd
index fd71f6d2ebeab7b84afbbfefb8a92a19ae204c72..3da773b4ada89933aef14651e127dc20496bf2e4 100644 (file)
--- a/media_interfaces/sync/rx_reset_fsm.vhd
+++ b/media_interfaces/sync/rx_reset_fsm.vhd
@@ -28,6 +28,9 @@ type statetype is ( WAIT_FOR_PLOL, RX_SERDES_RESET, WAIT_FOR_TIMER1, CHECK_LOL_L
 signal cs : statetype;  -- current state of lsm
 signal ns : statetype;  -- next state of lsm
                                                                                               
+signal rst_n_refclk_meta : std_logic := '1';
+signal rst_n_refclk : std_logic := '1';
+
 signal tx_pll_lol_qd_q        : std_logic;
 signal rx_cdr_lol_ch_q        : std_logic;
 signal rx_los_low_ch_q        : std_logic;
@@ -47,6 +50,17 @@ signal counter2               : unsigned(19 downto 0);
 signal timer2                 : std_logic;
                                                                                               
 begin
+
+process (RST_N, RX_REFCLK) is
+begin
+  if RST_N = '0' then
+    rst_n_refclk_meta <= '0';
+    rst_n_refclk <= '0';
+  elsif rising_edge(RX_REFCLK) then
+    rst_n_refclk_meta <= '1';
+    rst_n_refclk <= rst_n_refclk_meta;
+  end if;
+end process;
                                                                                               
 rx_lol_los <= rx_cdr_lol_ch_q or rx_los_low_ch_q ;
                                                                                               
@@ -86,7 +100,7 @@ end process THE_TIMER2_PROC;
 THE_FSM_PROC: process( RX_REFCLK )
 begin
   if rising_edge(RX_REFCLK) then
-    if RST_N = '0' then
+    if rst_n_refclk = '0' then
       cs <= WAIT_FOR_PLOL;
       rx_lol_los_int <= '1';
       rx_lol_los_del <= '1';

diff --git a/media_interfaces/sync/tx_reset_fsm.vhd b/media_interfaces/sync/tx_reset_fsm.vhd
index 0bc22d3851e333d533565d1c295873886b12ce6e..e35b8711a1bdd21feac09ad2b375c09d6799e53d 100644 (file)
--- a/media_interfaces/sync/tx_reset_fsm.vhd
+++ b/media_interfaces/sync/tx_reset_fsm.vhd
@@ -25,6 +25,9 @@ type statetype is ( QUAD_RESET, WAIT_FOR_TIMER1, CHECK_PLOL, WAIT_FOR_TIMER2, NO
 signal cs : statetype;  -- current state of lsm
 signal ns : statetype;  -- next state of lsm
                                                                                               
+signal rst_n_refclk_meta : std_logic := '1';
+signal rst_n_refclk : std_logic := '1';
+
 signal tx_pll_lol_qd_s_int  : std_logic;
 signal tx_pcs_rst_ch_c_int  : std_logic;
 signal rst_qd_c_int         : std_logic;
@@ -39,6 +42,17 @@ signal counter2             : unsigned(19 downto 0);
 signal timer2               : std_logic;
                                                                                               
 begin
+
+process (RST_N, TX_REFCLK) is
+begin
+  if RST_N = '0' then
+    rst_n_refclk_meta <= '0';
+    rst_n_refclk <= '0';
+  elsif rising_edge(TX_REFCLK) then
+    rst_n_refclk_meta <= '1';
+    rst_n_refclk <= rst_n_refclk_meta;
+  end if;
+end process;
                                                                                               
 sync_sfp_sigs : entity work.signal_sync port map(RESET => '0',CLK0 => TX_REFCLK, CLK1 => TX_REFCLK,
                                         D_IN(0)  => TX_PLL_LOL_QD_S, 
@@ -92,9 +106,9 @@ begin
 end process THE_TIMER2_PROC;
 
 -- State machine clocked process
-THE_FSM_PROC: process( TX_REFCLK, RST_N )
+THE_FSM_PROC: process( TX_REFCLK, rst_n_refclk )
 begin
-  if RST_N = '0' then
+  if rst_n_refclk = '0' then
     cs <= QUAD_RESET;
     tx_pcs_rst_ch_c <= '1';
     RST_QD_C <= '1';