No RX-FIFO's. Semi stable; trb errors can usually (?) be restored with 'trbcmd reset'.

Some times a fault appears that causes the calibration value to max-out (0xffff); not understood
Resets need more study.

diff --git a/soda_client.ldf b/soda_client.ldf
index c711e8d5286947807765f77825053c4ad9b8cbef..063fc821634cd8d8fd239081f5b5993c73c9f64a 100644 (file)
--- a/soda_client.ldf
+++ b/soda_client.ldf
@@ -4,7 +4,7 @@
         <Option name="HDL type" value="VHDL"/>
     </Options>
     <Implementation title="soda_client" dir="soda_client" description="soda_client" default_strategy="Strategy1">
-        <Options top="trb3_periph_sodaclient"/>
+        <Options def_top="trb3_periph_sodaclient" top="trb3_periph_sodaclient"/>
         <Source name="source/version.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>

diff --git a/soda_client.lpf b/soda_client.lpf
index 3f53e01f729098f7037559aa4a6ec6a1d8d9c9b3..e7e32a2d3830de090d1e4b013698043c63cfd41f 100644 (file)
--- a/soda_client.lpf
+++ b/soda_client.lpf
@@ -1,4 +1,4 @@
-rvl_alias "reveal_ist_380" "the_sync_link/clk_rx_full";
+rvl_alias "reveal_ist_458" "the_sync_link/clk_rx_full";
 RVL_ALIAS "reveal_ist_260" "the_sync_link/the_serdes/rx_full_clk_ch0"; 
 BLOCK RESETPATHS ;
 BLOCK ASYNCPATHS ;

diff --git a/source/med_ecp3_sfp_sync_up.vhd b/source/med_ecp3_sfp_sync_up.vhd
index 7cebc5ffb70fa3646b4a03a581b6de755580b61f..7295d518d7e548829152009191da19cf00d3b8ae 100644 (file)
--- a/source/med_ecp3_sfp_sync_up.vhd
+++ b/source/med_ecp3_sfp_sync_up.vhd
@@ -222,7 +222,7 @@ THE_SERDES : entity work.serdes_sync_upstream
     hdinn_ch0            => SD_RXD_N_IN,
     hdoutp_ch0           => SD_TXD_P_OUT,
     hdoutn_ch0           => SD_TXD_N_OUT,
-    rxiclk_ch0           => clk_200_i,
+--    rxiclk_ch0           => clk_200_i,       -- no more RX-fifo
     txiclk_ch0           => clk_200_i,
     rx_full_clk_ch0      => clk_rx_full,
     rx_half_clk_ch0      => clk_rx_half,

diff --git a/source/serdes_sync_upstream.ipx b/source/serdes_sync_upstream.ipx
index 026cff934bc30d06c5f3f3b9e701c32b7bbbc510..17c7119cbb9576ed62206f5eae4b8b1a7967fe51 100644 (file)
--- a/source/serdes_sync_upstream.ipx
+++ b/source/serdes_sync_upstream.ipx
@@ -1,11 +1,11 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_sync_upstream" module="serdes_sync_upstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 12 24 11:32:51.099" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="serdes_sync_upstream" module="serdes_sync_upstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 01 16 15:35:13.845" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
   <Package>
-               <File name="serdes_sync_upstream.lpc" type="lpc" modified="2013 12 24 11:32:48.000"/>
-               <File name="serdes_sync_upstream.pp" type="pp" modified="2013 12 24 11:32:48.000"/>
-               <File name="serdes_sync_upstream.sym" type="sym" modified="2013 12 24 11:32:48.000"/>
-               <File name="serdes_sync_upstream.tft" type="tft" modified="2013 12 16 15:43:22.000"/>
-               <File name="serdes_sync_upstream.txt" type="pcs_module" modified="2013 12 24 11:32:48.000"/>
-               <File name="serdes_sync_upstream.vhd" type="top_level_vhdl" modified="2013 12 16 15:43:22.000"/>
+               <File name="serdes_sync_upstream.lpc" type="lpc" modified="2014 01 16 15:35:12.000"/>
+               <File name="serdes_sync_upstream.pp" type="pp" modified="2014 01 16 15:35:12.000"/>
+               <File name="serdes_sync_upstream.sym" type="sym" modified="2014 01 16 15:35:12.000"/>
+               <File name="serdes_sync_upstream.tft" type="tft" modified="2014 01 16 15:34:47.000"/>
+               <File name="serdes_sync_upstream.txt" type="pcs_module" modified="2014 01 16 15:35:12.000"/>
+               <File name="serdes_sync_upstream.vhd" type="top_level_vhdl" modified="2014 01 16 15:34:47.000"/>
   </Package>
 </DiamondModule>

diff --git a/source/serdes_sync_upstream.lpc b/source/serdes_sync_upstream.lpc
index 7526f9f38f811ac705fa9d88aaf8bfb678e9185f..df0331cba62450540b588344515a6558525aa4fe 100644 (file)
--- a/source/serdes_sync_upstream.lpc
+++ b/source/serdes_sync_upstream.lpc
@@ -16,8 +16,8 @@ CoreRevision=8.1
 ModuleName=serdes_sync_upstream
 SourceFormat=VHDL
 ParameterFileVersion=1.0
-Date=12/24/2013
-Time=11:32:48
+Date=01/16/2014
+Time=15:35:12
 
 [Parameters]
 Verilog=0
@@ -91,7 +91,7 @@ _rx_data_width0=8
 _rx_data_width1=8
 _rx_data_width2=8
 _rx_data_width3=8
-_rx_fifo0=ENABLED
+_rx_fifo0=DISABLED
 _rx_fifo1=ENABLED
 _rx_fifo2=ENABLED
 _rx_fifo3=ENABLED

diff --git a/source/serdes_sync_upstream.txt b/source/serdes_sync_upstream.txt
index e488a33952b7e86c5db949db9f4521b6f75cb1ab..940e01a9f7ce44ace3facf6567a565473f0e620a 100644 (file)
--- a/source/serdes_sync_upstream.txt
+++ b/source/serdes_sync_upstream.txt
@@ -20,7 +20,7 @@ CH0_TX_DATA_RATE        "FULL"
 CH0_TX_DATA_WIDTH       "8"
 CH0_RX_DATA_WIDTH        "8"
 CH0_TX_FIFO       "ENABLED"
-CH0_RX_FIFO        "ENABLED"
+CH0_RX_FIFO        "DISABLED"
 CH0_TDRV      "0"
 #CH0_TX_FICLK_RATE      200.0
 #CH0_RXREFCLK_RATE        "200.0"

diff --git a/source/serdes_sync_upstream.vhd b/source/serdes_sync_upstream.vhd
index 539e0c588f71057338ee753b08e202d185a3df37..02b4eba5c5e07688eb55cf8cdd4d8d209cfb5c25 100644 (file)
--- a/source/serdes_sync_upstream.vhd
+++ b/source/serdes_sync_upstream.vhd
@@ -1538,7 +1538,6 @@ entity serdes_sync_upstream is
     hdinp_ch0, hdinn_ch0    :   in std_logic;
     hdoutp_ch0, hdoutn_ch0   :   out std_logic;
     sci_sel_ch0    :   in std_logic;
-    rxiclk_ch0    :   in std_logic;
     txiclk_ch0    :   in std_logic;
     rx_full_clk_ch0   :   out std_logic;
     rx_half_clk_ch0   :   out std_logic;
@@ -2199,7 +2198,7 @@ port map  (
   PCIE_PHYSTATUS_0 => open,
   SCISELCH0 => sci_sel_ch0,
   SCIENCH0 => fpsc_vhi,
-  FF_RXI_CLK_0 => rxiclk_ch0,
+  FF_RXI_CLK_0 => fpsc_vlo,
   FF_TXI_CLK_0 => txiclk_ch0,
   FF_EBRD_CLK_0 => fpsc_vlo,
   FF_RX_F_CLK_0 => rx_full_clk_ch0,

diff --git a/source/soda_calibration_timer.vhd b/source/soda_calibration_timer.vhd
index 0f1269fc97ed63f268ea788112008fc841238a47..c4135b2977eca28d94d4d01db6ce83e0e7874186 100644 (file)
--- a/source/soda_calibration_timer.vhd
+++ b/source/soda_calibration_timer.vhd
@@ -20,14 +20,14 @@ entity soda_calibration_timer is
                START_CALIBRATION                       : in    std_logic := '0';\r
                END_CALIBRATION                 : in    std_logic := '0';\r
                CALIB_VALID_OUT                 : out   std_logic := '0';       -- 
-               CALIB_TIME_OUT                          : out   std_logic_vector(7 downto 0) := (others => '0')\r
+               CALIB_TIME_OUT                          : out   std_logic_vector(15 downto 0) := (others => '0')\r
        );\r
 end soda_calibration_timer;\r
 \r
 architecture Behavioral of soda_calibration_timer is\r
 
        signal  calibration_running_S   : std_logic     := '0';\r
-       signal  calibration_timer_S             : std_logic_vector(7 downto 0)  := (others => '0');             -- from super-burst-nr-generator\r
+       signal  calibration_timer_S             : std_logic_vector(15 downto 0) := (others => '0');             -- from super-burst-nr-generator\r
 \r
 begin\r
 \r
@@ -49,7 +49,7 @@ begin
                                        calibration_running_S           <= '0';
                                        CALIB_VALID_OUT                         <= '1';\r
                                        CALIB_TIME_OUT                                  <= calibration_timer_S;
-                               elsif (calibration_timer_S= 255) then
+                               elsif (calibration_timer_S= 65535) then
                                        calibration_running_S           <= '0';
                                        CALIB_VALID_OUT                         <= '1';\r
                                        CALIB_TIME_OUT                                  <= calibration_timer_S;

diff --git a/source/soda_components.vhd b/source/soda_components.vhd
index 92296691092da14dcd3f8cd8d73a73064daf1190..de2882560b7fe912f2c32fdafc68644057220745 100644 (file)
--- a/source/soda_components.vhd
+++ b/source/soda_components.vhd
@@ -219,7 +219,7 @@ package soda_components is
                        START_CALIBRATION                       : in    std_logic := '0';\r
                        END_CALIBRATION                 : in    std_logic := '0';\r
                        CALIB_VALID_OUT                 : out   std_logic := '0';       -- 
-                       CALIB_TIME_OUT                          : out   std_logic_vector(7 downto 0) := (others => '0')\r
+                       CALIB_TIME_OUT                          : out   std_logic_vector(15 downto 0) := (others => '0')\r
                );\r
        end component;\r
 \r

diff --git a/source/soda_reply_handler.vhd b/source/soda_reply_handler.vhd
index 5324d9046531b8b35bbabff7dbb25f940d48e026..b96b4edb0b6c1c69834c96bec6c289727f16f221 100644 (file)
--- a/source/soda_reply_handler.vhd
+++ b/source/soda_reply_handler.vhd
@@ -26,7 +26,7 @@ end soda_reply_handler;
 architecture Behavioral of soda_reply_handler is
 
        type            packet_state_type is (  c_RST, c_IDLE, c_ERROR, c_REPLY, c_DONE);
-       signal  packet_state_S                          :       packet_state_type := c_IDLE;
+       signal  reply_recv_state_S                              :       packet_state_type := c_IDLE;
 
 begin
 
@@ -36,13 +36,13 @@ begin
                        if (RESET='1') then
                                REPLY_VALID_OUT <= '0';
                                REPLY_OK_OUT            <= '0';
-                               packet_state_S          <= c_IDLE;
+                               reply_recv_state_S              <= c_IDLE;
                        else
                                REPLY_VALID_OUT <= '0';
-                               case packet_state_S is\r
+                               case reply_recv_state_S is\r
                                        when c_IDLE     =>\r
                                                if (RX_DLM_IN='1') then
-                                                       packet_state_S          <= c_REPLY;
+                                                       reply_recv_state_S              <= c_REPLY;
                                                        REPLY_VALID_OUT <= '1';
                                                        if (EXPECTED_REPLY_IN = RX_DLM_WORD_IN) then
                                                                REPLY_OK_OUT    <= '1';
@@ -53,16 +53,16 @@ begin
                                        when c_REPLY =>
                                                if (RX_DLM_IN='0') then\r
                                                        REPLY_VALID_OUT <= '1';
-                                                       packet_state_S          <= c_IDLE;
+                                                       reply_recv_state_S              <= c_IDLE;
                                                else
-                                                       packet_state_S          <= c_ERROR;\r
+                                                       reply_recv_state_S              <= c_ERROR;\r
                                                end if;
                                        when c_ERROR    =>
-                                               packet_state_S                  <= c_IDLE;
+                                               reply_recv_state_S                      <= c_IDLE;
                                                REPLY_OK_OUT    <= '0';
                                                REPLY_OK_OUT                    <= '0';
                                        when others =>
-                                               packet_state_S                  <= c_IDLE;
+                                               reply_recv_state_S                      <= c_IDLE;
                                                REPLY_OK_OUT    <= '0';
                                end case;
                        end if;\r

diff --git a/source/soda_source.vhd b/source/soda_source.vhd
index 6fb51adec7eb9ba35cddb49e42aa5d9a69f13b04..f89e144e783c44d9e9d2914efa88f8fa6a685a3a 100644 (file)
--- a/source/soda_source.vhd
+++ b/source/soda_source.vhd
@@ -67,8 +67,9 @@ architecture Behavioral of soda_source is
        signal start_calibration_S              : std_logic;
 
        signal calibration_valid_s              : std_logic;
-       signal calibration_time_s               : std_logic_vector(7 downto 0)  := (others => '0');
+       signal calibration_time_s               : std_logic_vector(15 downto 0) := (others => '0');
        signal calib_register_s                 : std_logic_vector(31 downto 0) := (others => '0');
+--     signal calib_register_rst_s     : std_logic     := '0'; -- read of calibration register resets contents to 0
 
 begin
        
@@ -127,13 +128,13 @@ begin
                        CALIB_TIME_OUT                          =>      calibration_time_S
                );
                
-       src_store_calib_proc  : process(SYSCLK)
+       src_store_calib_proc  : process(SYSCLK) -- converting to sysclk domain
        begin
                if rising_edge(SYSCLK) then
                        if( RESET = '1' ) then
                                calib_register_S                                        <= (others => '0');
                        else
-                               calib_register_S(7 downto 0)    <= calibration_time_S;
+                               calib_register_S(15 downto 0)   <= calibration_time_S;
                        end if;
                end if;
        end process;
@@ -244,15 +245,18 @@ soda_cmd_strobe_posedge_to_pulse: posedge_to_pulse
        begin
                if( rising_edge(SYSCLK) ) then
                        if   ( RESET = '1' ) then
-                               buf_bus_data_out        <= (others => '0');
+                               buf_bus_data_out                <= (others => '0');
                        elsif( (store_rd = '1') and (SODA_ADDR_IN = "0000") ) then
-                               buf_bus_data_out        <= '0' & soda_cmd_word_S;
+                               buf_bus_data_out                <= '0' & soda_cmd_word_S;
                        elsif( (store_rd = '1') and (SODA_ADDR_IN = "0001") ) then
-                               buf_bus_data_out        <= '0' & super_burst_nr_S;
+                               buf_bus_data_out                <= '0' & super_burst_nr_S;
                        elsif( (store_rd = '1') and (SODA_ADDR_IN = "0010") ) then
-                               buf_bus_data_out        <= calib_register_S;
+                               buf_bus_data_out                <= calib_register_S;
+--                             calib_register_rst_S    <= '1';
                        elsif( (store_rd = '1') and (SODA_ADDR_IN = "0011") ) then
-                               buf_bus_data_out        <= LEDregister_i;
+                               buf_bus_data_out                <= LEDregister_i;\r
+--                     else\r
+--                             calib_register_rst_S    <= '0';
                        end if;
                end if;
        end process THE_READ_REG_PROC;