]> jspc29.x-matter.uni-frankfurt.de Git - trb3.git/commitdiff
*** empty log message ***
authorhadaq <hadaq>
Wed, 16 Nov 2011 10:40:46 +0000 (10:40 +0000)
committerhadaq <hadaq>
Wed, 16 Nov 2011 10:40:46 +0000 (10:40 +0000)
tdc_test/nodes_lxhadeb05.txt [new file with mode: 0644]
tdc_test/trb3_periph.vhd

diff --git a/tdc_test/nodes_lxhadeb05.txt b/tdc_test/nodes_lxhadeb05.txt
new file mode 100644 (file)
index 0000000..62a4fb3
--- /dev/null
@@ -0,0 +1,7 @@
+// nodes file for parallel place&route
+
+[lxhadeb05]
+SYSTEM = linux
+CORENUM = 24
+ENV = /home/cugur/hades27/bin/diamond_setup.sh
+WORKDIR = /home/cugur/hades27/Projects/TDC_on_TRB3/trb3/tdc_test/diamond/trb3_periph
\ No newline at end of file
index 70d14d39587a9a0f00cfe7f8dd45258fe225edf6..82325d866f1a84fb15061d94b426bd0fbe1172ae 100644 (file)
@@ -590,7 +590,7 @@ begin
 
   THE_TDC : TDC
     generic map (
-      CHANNEL_NUMBER        => 8,       -- Number of TDC channels
+      CHANNEL_NUMBER        => 16,       -- Number of TDC channels
       TRG_WIN_PRE           => x"0023",  -- Pre-Trigger window width
       TRG_WIN_POST          => x"0023")  -- Post-Trigger window width
     port map (
@@ -598,7 +598,7 @@ begin
       CLK_TDC               => CLK_PCLK_LEFT,  -- Clock used for the time measurement
       CLK_READOUT           => clk_100_i,  -- Clock for the readout
       REFERENCE_TIME        => timing_trg_received_i,  -- Reference time input
-      HIT_IN                => DQLL(6 downto 0),  -- Channel start signals
+      HIT_IN                => DQLL(14 downto 0),  -- Channel start signals
       TRG_DATA_VALID_IN     => trg_data_valid_i,  -- trig data valid signal
                                         -- from trbnet
       VALID_TIMING_TRG_IN   => trg_timing_valid_i,  -- valid timing trigger