few more corrections

diff --git a/doku/doc_standalone.pdf b/doku/doc_standalone.pdf
index 0b24a23b18c667180d39cb3bb0ea2d1ea2e80aca..6ca2cb660a76711ac6d7a9729b0b8aa7c8915972 100644 (file)
Binary files a/doku/doc_standalone.pdf and b/doku/doc_standalone.pdf differ

diff --git a/doku/doc_standalone.tex b/doku/doc_standalone.tex
index fb7afe072efeaf837ad9c0ab71ee47c1ec429c66..14b0c0bc22962938bbb4e318a2a3b0b1a1d48d7f 100644 (file)
--- a/doku/doc_standalone.tex
+++ b/doku/doc_standalone.tex
@@ -32,7 +32,7 @@
 \usepackage{rotating}
 \usepackage{framed}
 \title{Dokumentation: JTAG-Chain-Controller (für TRB V3) und JTAG-Monitor}
-\author{Bertram Neumann}
+\author{Bertram Neumann, Jan Michel}
 
 \makeatletter
 \let\thetitle\@title

diff --git a/doku/jtag_chain_controller.tex b/doku/jtag_chain_controller.tex
index 88ebb8080fb0d5390fa203f87936f13881361cda..daf6abc8657615aef20d030e9b05a1891348cda4 100644 (file)
--- a/doku/jtag_chain_controller.tex
+++ b/doku/jtag_chain_controller.tex
@@ -154,7 +154,7 @@ label=jtag\_cmd\_m26c Port,labelposition=all,commandchars=\\\{\}]
 
 \clearpage
 \subsection{TrbNet Interface}
-Der Bus Handler akzeptiert 9-bit-Adressen. Die Adressen liegen damit zwischen 0x000 und 0x1FF.
+Der Bus Handler akzeptiert 10-bit-Adressen. Die Adressen liegen damit zwischen 0x000 und 0x3FF.
 \begin{table}[H]
 \renewcommand{\arraystretch}{1.4} 
 \begin{tabular}{ll}
@@ -184,7 +184,9 @@ Geschrieben werden kann nur, wenn der JTAG-Chain-Controller gestoppt ist (\textt
 \renewcommand{\arraystretch}{1.4} 
 \begin{tabular}{p{3.5cm}lp{8cm}}
 Name & Adresse & Beschreibung\\
-RAM1AWORD(0-255) & 0x000-0x0FF & Wenn \texttt{m26cs\_stopped} = 1, kann ram1a über diese Register beschrieben, sonst nur ausgelesen werden. Der Bereich von \textbf{ram1a}, das auf diese Register abgebildet wird, wird durch das Register RAM\_BASEADDR (siehe Tabelle \ref{table:control_addrs}) eingestellt.\\
+RAM1AWORD(0-255) & 0x000-0x0FF & Wenn \texttt{m26cs\_stopped} = 1, kann ram1a über diese Register
+beschrieben, sonst nur ausgelesen werden. Der Bereich von \textbf{ram1a}, das auf diese Register
+abgebildet wird, wird durch das Register RAM\_BASEADDR eingestellt.\\
 \end{tabular}
 \caption{Register im RAM-Adressbereich.}
 \label{table:ram_addrs}
@@ -274,7 +276,8 @@ Kopie des Registers \texttt{chain\_status}, zu dem Zeitpunkt, zu dem die Kopie \
  \includegraphics[width=0.4\textwidth]{./ram3block.pdf}
  % schrader_overview.pdf: 720x540 pixel, 72dpi, 25.40x19.05 cm, bb=0 0 720 540
 %\setcapwidth[c]{0.9\textwidth}
- \caption{32 bit Zählerstände in \textbf{ram3a}/\textbf{ram3b}. Gezeigt ist der Block für einen Sensor.}
+ \caption{32 bit Zählerstände in \textbf{ram3a}/\textbf{ram3b}. Gezeigt ist der Block für einen
+Sensor mit 64 Worten.}
  \label{fig:ram3block}
 \end{wrapfigure}
 Abbildung \ref{fig:ram3block} zeigt das RAM-Layout für das Speichern der Fehlerzählerstände 

diff --git a/vhdl/code/jtag_cmd_m26c.vhd b/vhdl/code/jtag_cmd_m26c.vhd
index c0a1becda06f20fba671ba729e3bc676b2b1b62f..479beb859d514bede1ab2d8ba334c977fd28c3c1 100644 (file)
--- a/vhdl/code/jtag_cmd_m26c.vhd
+++ b/vhdl/code/jtag_cmd_m26c.vhd
@@ -97,19 +97,19 @@ constant MAX_REGLEN_PLUS_ONE_LD                  : integer := log2_ceil(MAX_REGL
 constant JTAG_M26_IRLEN_LD        : integer := log2_ceil(JTAG_M26_IRLEN); -- ld of value, rounded up
 constant JTAG_TDO_EXPECTED_MAXDELAY_PLUS_ONE_LD : integer := log2_ceil(JTAG_TDO_EXPECTED_MAXDELAY+1); -- ceil of ld( value plus one)
 
-constant STATUS_JTAG_ERROR     : integer := 0; -- length MAX_NUMCHIPS
-constant STATUS_WRITE_ERROR    : integer := MAX_NUMCHIPS;
-constant STATUS_WRITE_ERROR2   : integer := 2*MAX_NUMCHIPS;
-constant STATUS_READ_ERROR     : integer := 3*MAX_NUMCHIPS;
-constant STATUS_READ_ERROR2    : integer := 4*MAX_NUMCHIPS;
-constant STATUS_DATA_CHANGED   : integer := 5*MAX_NUMCHIPS;
-
-constant WRITE_STATUS_JTAG_ERROR     : integer := 0; -- length MAX_NUMCHIPS
-constant WRITE_STATUS_DATA_CHANGED     : integer := MAX_NUMCHIPS; -- length MAX_NUMCHIPS
-constant WRITE_STATUS_DATA_CHANGED_OVER_THRESHOLD     : integer := 2*MAX_NUMCHIPS; -- length MAX_NUMCHIPS
-constant READ_STATUS_JTAG_ERROR                   : integer := 0; -- length MAX_NUMCHIPS
-constant READ_STATUS_BIT_ERROR                    : integer := MAX_NUMCHIPS; -- length MAX_NUMCHIPS
-constant READ_STATUS_BIT_ERROR_OVER_THRESHOLD     : integer := 2*MAX_NUMCHIPS; -- length MAX_NUMCHIPS
+-- constant STATUS_JTAG_ERROR     : integer := 0; -- length MAX_NUMCHIPS
+-- constant STATUS_WRITE_ERROR    : integer := MAX_NUMCHIPS;
+-- constant STATUS_WRITE_ERROR2   : integer := 2*MAX_NUMCHIPS;
+-- constant STATUS_READ_ERROR     : integer := 3*MAX_NUMCHIPS;
+-- constant STATUS_READ_ERROR2    : integer := 4*MAX_NUMCHIPS;
+-- constant STATUS_DATA_CHANGED   : integer := 5*MAX_NUMCHIPS;
+
+-- constant WRITE_STATUS_JTAG_ERROR     : integer := 0; -- length MAX_NUMCHIPS
+-- constant WRITE_STATUS_DATA_CHANGED     : integer := MAX_NUMCHIPS; -- length MAX_NUMCHIPS
+-- constant WRITE_STATUS_DATA_CHANGED_OVER_THRESHOLD     : integer := 2*MAX_NUMCHIPS; -- length MAX_NUMCHIPS
+-- constant READ_STATUS_JTAG_ERROR                   : integer := 0; -- length MAX_NUMCHIPS
+-- constant READ_STATUS_BIT_ERROR                    : integer := MAX_NUMCHIPS; -- length MAX_NUMCHIPS
+-- constant READ_STATUS_BIT_ERROR_OVER_THRESHOLD     : integer := 2*MAX_NUMCHIPS; -- length MAX_NUMCHIPS
 
 constant RAM_MATCH_DIFF_COUNT_DEPTH   : integer := MAX_NUMCHIPS_LD + MAX_REGISTERS_PLUS_ONE_LD + 1;--9; 
     -- maximum 32 counts / chip (one for read DEV_ID register, rest for read/write data registers), maximum 16 chips, each count 32 bits
@@ -604,11 +604,11 @@ the_bus_handler : trb_net16_regio_bus_handler
     BUS_WRITE_ACK_IN(3)               => '0',
     BUS_NO_MORE_DATA_IN(0)            => bus2_ram_nack_in,
     BUS_NO_MORE_DATA_IN(1)            => bus_ram1c_nack,
-    BUS_NO_MORE_DATA_IN(2)            => '0',
+    BUS_NO_MORE_DATA_IN(2)            => bus_command_retry,
     BUS_NO_MORE_DATA_IN(3)            => bus_ram3b_nack,
     BUS_UNKNOWN_ADDR_IN(0)            => '0',
     BUS_UNKNOWN_ADDR_IN(1)            => bus_ram1c_unkwn,
-    BUS_UNKNOWN_ADDR_IN(2)            => bus_command_retry,
+    BUS_UNKNOWN_ADDR_IN(2)            => bus_command_nack,
     BUS_UNKNOWN_ADDR_IN(3)            => bus_ram3b_unkwn
     );
 

diff --git a/vhdl/code/jtag_update_error_counts_ram3a.vhd b/vhdl/code/jtag_update_error_counts_ram3a.vhd
index 5cd826a17616e8462de29d992692f38e559d05ac..c6896b7be13351d6660904d6a3d47d3f66076a2d 100644 (file)
--- a/vhdl/code/jtag_update_error_counts_ram3a.vhd
+++ b/vhdl/code/jtag_update_error_counts_ram3a.vhd
@@ -63,12 +63,18 @@ end entity;
 architecture jtag_update_error_counts_ram3a_arch of jtag_update_error_counts_ram3a is
 type upd_state_type is (UPD_IDLE,
 -- upd1s*: update DATA_CHANGED counts
-UPD1S_START_REG, UPD1S_SETUP_READ_DATA_CH, UPD1S_SETUP_READ_DATA_CH_OV_TH, UPD1S_READ_DATA_CH_OV_TH, UPD1S_WRITE_CALC_NEW_DATA_CHANGED, UPD1S_WRITE_DR_DATA_CHANGED, UPD1S_WRITE_DR_DATA_CHANGED_OV_TH, UPD1S_START_FINISH, UPD1S_FINISH_SETUP_READ_DATA_CH, UPD1S_FINISH_SETUP_READ_WAIT, UPD1S_FINISH_READ_DATA_CH_OV_TH, UPD1S_FINISH_CALC_NEW_DATA_CHANGED, UPD1S_FINISH_WRITE_DATA_CHANGED, UPD1S_FINISH_WRITE_DATA_CHANGED_OV_TH,
+UPD1S_START_REG, UPD1S_SETUP_READ_DATA_CH, UPD1S_SETUP_READ_DATA_CH_OV_TH, UPD1S_READ_DATA_CH_OV_TH, 
+UPD1S_WRITE_CALC_NEW_DATA_CHANGED, UPD1S_WRITE_DR_DATA_CHANGED, UPD1S_WRITE_DR_DATA_CHANGED_OV_TH, 
+UPD1S_START_FINISH, UPD1S_FINISH_SETUP_READ_DATA_CH, UPD1S_FINISH_SETUP_READ_WAIT, UPD1S_FINISH_READ_DATA_CH_OV_TH, 
+UPD1S_FINISH_CALC_NEW_DATA_CHANGED, UPD1S_FINISH_WRITE_DATA_CHANGED, UPD1S_FINISH_WRITE_DATA_CHANGED_OV_TH,
 
-UPD3S_START_REG, UPD3S_SETUP_READ_DATA_CH, UPD3S_SETUP_READ_DATA_CH_OV_TH, UPD3S_READ_DATA_CH_OV_TH, UPD3S_WRITE_CALC_NEW_DATA_CHANGED, UPD3S_WRITE_DR_DATA_CHANGED, UPD3S_WRITE_DR_DATA_CHANGED_OV_TH, UPD3S_START_FINISH, UPD3S_FINISH_SETUP_READ_DATA_CH, UPD3S_FINISH_SETUP_READ_WAIT, UPD3S_FINISH_READ_DATA_CH_OV_TH, UPD3S_FINISH_CALC_NEW_DATA_CHANGED, UPD3S_FINISH_WRITE_DATA_CHANGED, UPD3S_FINISH_WRITE_DATA_CHANGED_OV_TH,
+UPD3S_START_REG, UPD3S_SETUP_READ_DATA_CH, UPD3S_SETUP_READ_DATA_CH_OV_TH, UPD3S_READ_DATA_CH_OV_TH, 
+UPD3S_WRITE_CALC_NEW_DATA_CHANGED, UPD3S_WRITE_DR_DATA_CHANGED, UPD3S_WRITE_DR_DATA_CHANGED_OV_TH, 
+UPD3S_START_FINISH, UPD3S_FINISH_SETUP_READ_DATA_CH, UPD3S_FINISH_SETUP_READ_WAIT, UPD3S_FINISH_READ_DATA_CH_OV_TH, 
+UPD3S_FINISH_CALC_NEW_DATA_CHANGED, UPD3S_FINISH_WRITE_DATA_CHANGED, UPD3S_FINISH_WRITE_DATA_CHANGED_OV_TH,
 
-
-UPD2S_START_REG, UPD2S_SETUP_READ_DATA_CH, UPD2S_SETUP_READ_DATA_CH_OV_TH, UPD2S_READ_DATA_CH_OV_TH, UPD2S_WRITE_CALC_NEW_DATA_CHANGED, UPD2S_WRITE_DR_DATA_CHANGED, UPD2S_WRITE_DR_DATA_CHANGED_OV_TH,
+UPD2S_START_REG, UPD2S_SETUP_READ_DATA_CH, UPD2S_SETUP_READ_DATA_CH_OV_TH, UPD2S_READ_DATA_CH_OV_TH, 
+UPD2S_WRITE_CALC_NEW_DATA_CHANGED, UPD2S_WRITE_DR_DATA_CHANGED, UPD2S_WRITE_DR_DATA_CHANGED_OV_TH,
 -- upd2s*: update READ_ERROR counts
 --,UPD2S_SETUP,UPD2S_READ_MCOUNT, UPD2S_READ_DCOUNT,
 -- upd3s*: update WRITE_ERROR counts