do_reboot_i <= common_ctrl_regs(15) or reboot_from_gbe; -- or killswitch_reboot_i;
- -- if jttl(15) is stabily high for 1.28us: issue reboot
- THE_KILLSWITCH_PROC : process
- variable stab_counter : unsigned(7 downto 0);
- variable inp, inp_delay : std_logic := '0';
- begin
- wait until rising_edge(clk_100_i);
-
- if inp_delay = inp then
- stab_counter := stab_counter + 1;
- else
- stab_counter := 0;
- end if;
-
- inp_delay := inp;
- inp := JTTL(15);
- killswitch_reboot_i <= stab_counter(stab_counter'high) and inp;
- end process;
+-- -- if jttl(15) is stabily high for 1.28us: issue reboot
+-- THE_KILLSWITCH_PROC : process
+-- variable stab_counter : unsigned(7 downto 0);
+-- variable inp, inp_delay : std_logic := '0';
+-- begin
+-- wait until rising_edge(clk_100_i);
+--
+-- if inp_delay = inp then
+-- stab_counter := stab_counter + 1;
+-- else
+-- stab_counter := 0;
+-- end if;
+--
+-- inp_delay := inp;
+-- inp := JTTL(15);
+-- killswitch_reboot_i <= stab_counter(stab_counter'high) and inp;
+-- end process;
-------------------------------------------------------------------------------
-- TDC
-------------------------------------------------------------------------------
- GEN_TDC : if INCLUDE_TDC = c_YES generate
- -- generates hits for calibration uncorrelated with tdc clk
- -- also used for the trigger and clock selection procoess
- OSCInst0 : OSCF -- internal oscillator with frequency of 2.5MHz
- port map (
- OSC => osc_int
- );
-
- THE_TDC : TDC
- generic map (
- CHANNEL_NUMBER => TDC_CHANNEL_NUMBER, -- Number of TDC channels
- STATUS_REG_NR => 21, -- Number of status regs
- CONTROL_REG_NR => 8, -- Number of control regs - higher than 8 check tdc_ctrl_addr
- DEBUG => c_NO
- )
- port map (
- RESET => reset_i,
- CLK_TDC => CLK_PCLK_RIGHT, -- Clock used for the time measurement
- CLK_READOUT => clk_100_i, -- Clock for the readout
- REFERENCE_TIME => cts_trigger_out, -- Reference time input
- HIT_IN => tdc_inputs, -- Channel start signals
- HIT_CAL_IN => osc_int, --clk_20_i, -- Hits for calibrating the TDC
- TRG_WIN_PRE => tdc_ctrl_reg(42 downto 32), -- Pre-Trigger window width
- TRG_WIN_POST => tdc_ctrl_reg(58 downto 48), -- Post-Trigger window width
- --
- -- Trigger signals from handler
- TRG_DATA_VALID_IN => cts_rdo_trg_data_valid, -- trig data valid signal from trbnet
- VALID_TIMING_TRG_IN => cts_rdo_valid_timing_trg, -- valid timing trigger signal from trbnet
- VALID_NOTIMING_TRG_IN => cts_rdo_valid_notiming_trg, -- valid notiming signal from trbnet
- INVALID_TRG_IN => cts_rdo_invalid_trg, -- invalid trigger signal from trbnet
- TMGTRG_TIMEOUT_IN => '0', -- timing trigger timeout signal from trbnet
- SPIKE_DETECTED_IN => '0',
- MULTI_TMG_TRG_IN => '0',
- SPURIOUS_TRG_IN => '0',
- --
- TRG_NUMBER_IN => cts_rdo_trg_number, -- LVL1 trigger information package
- TRG_CODE_IN => cts_rdo_trg_code, --
- TRG_INFORMATION_IN => cts_rdo_trg_information, --
- TRG_TYPE_IN => cts_rdo_trg_type, -- LVL1 trigger information package
- --Response to handler
- -- TRG_RELEASE_OUT => fee_trg_release_i, -- trigger release signal
- TRG_RELEASE_OUT => open,
- TRG_STATUSBIT_OUT => cts_rdo_additional(1).statusbits,
- DATA_OUT => cts_rdo_additional(1).data,
- DATA_WRITE_OUT => cts_rdo_additional(1).data_write,
- DATA_FINISHED_OUT => cts_rdo_additional(1).data_finished,
- --Hit Counter Bus
- HCB_READ_EN_IN => hitreg_read_en, -- bus read en strobe
- HCB_WRITE_EN_IN => hitreg_write_en, -- bus write en strobe
- HCB_ADDR_IN => hitreg_addr, -- bus address
- HCB_DATA_OUT => hitreg_data_out, -- bus data
- HCB_DATAREADY_OUT => hitreg_data_ready, -- bus data ready strobe
- HCB_UNKNOWN_ADDR_OUT => hitreg_invalid, -- bus invalid addr
- --Status Registers Bus
- SRB_READ_EN_IN => srb_read_en, -- bus read en strobe
- SRB_WRITE_EN_IN => srb_write_en, -- bus write en strobe
- SRB_ADDR_IN => srb_addr, -- bus address
- SRB_DATA_OUT => srb_data_out, -- bus data
- SRB_DATAREADY_OUT => srb_data_ready, -- bus data ready strobe
- SRB_UNKNOWN_ADDR_OUT => srb_invalid, -- bus invalid addr
- --Encoder Start Registers Bus
- ESB_READ_EN_IN => esb_read_en, -- bus read en strobe
- ESB_WRITE_EN_IN => esb_write_en, -- bus write en strobe
- ESB_ADDR_IN => esb_addr, -- bus address
- ESB_DATA_OUT => esb_data_out, -- bus data
- ESB_DATAREADY_OUT => esb_data_ready, -- bus data ready strobe
- ESB_UNKNOWN_ADDR_OUT => esb_invalid, -- bus invalid addr
- --Fifo Write Registers Bus
- EFB_READ_EN_IN => fwb_read_en, -- bus read en strobe
- EFB_WRITE_EN_IN => fwb_write_en, -- bus write en strobe
- EFB_ADDR_IN => fwb_addr, -- bus address
- EFB_DATA_OUT => fwb_data_out, -- bus data
- EFB_DATAREADY_OUT => fwb_data_ready, -- bus data ready strobe
- EFB_UNKNOWN_ADDR_OUT => fwb_invalid, -- bus invalid addr
- --Lost Hit Registers Bus
- LHB_READ_EN_IN => '0', -- lhb_read_en, -- bus read en strobe
- LHB_WRITE_EN_IN => '0', -- lhb_write_en, -- bus write en strobe
- LHB_ADDR_IN => (others => '0'), -- lhb_addr, -- bus address
- LHB_DATA_OUT => open, -- lhb_data_out, -- bus data
- LHB_DATAREADY_OUT => open, -- lhb_data_ready, -- bus data ready strobe
- LHB_UNKNOWN_ADDR_OUT => open, -- lhb_invalid, -- bus invalid addr
- -- Channel Debug
- CDB_READ_EN_IN => '0', -- in std_logic;
- CDB_WRITE_EN_IN => '1', -- in std_logic;
- CDB_ADDR_IN => "0000000", -- in std_logic_vector(6 downto 0);
- CDB_DATA_OUT => open, -- out std_logic_vector(31 downto 0);
- CDB_DATAREADY_OUT => open, -- out std_logic;
- CDB_UNKNOWN_ADDR_OUT => open, -- out std_logic;
- --
- LOGIC_ANALYSER_OUT => tdc_debug,
- CONTROL_REG_IN => tdc_ctrl_reg
- );
-
- --tdc_inputs(1) used by CBM-MBS ETM
--- tdc_inputs(2) <= cbm_sync_pulser_i;
--- tdc_inputs(3) <= cbm_sync_timing_trigger_i;
- tdc_inputs(4) <= JINLVDS(0); --NIM_IN(0);
- --JTTL(0 downto 15) <= (others => '0');
-
+-- GEN_TDC : if INCLUDE_TDC = c_YES generate
+-- -- generates hits for calibration uncorrelated with tdc clk
+-- -- also used for the trigger and clock selection procoess
+-- OSCInst0 : OSCF -- internal oscillator with frequency of 2.5MHz
+-- port map (
+-- OSC => osc_int
+-- );
+--
+-- THE_TDC : TDC
+-- generic map (
+-- CHANNEL_NUMBER => TDC_CHANNEL_NUMBER, -- Number of TDC channels
+-- STATUS_REG_NR => 21, -- Number of status regs
+-- CONTROL_REG_NR => 8, -- Number of control regs - higher than 8 check tdc_ctrl_addr
+-- DEBUG => c_NO
+-- )
+-- port map (
+-- RESET => reset_i,
+-- CLK_TDC => CLK_PCLK_RIGHT, -- Clock used for the time measurement
+-- CLK_READOUT => clk_100_i, -- Clock for the readout
+-- REFERENCE_TIME => cts_trigger_out, -- Reference time input
+-- HIT_IN => tdc_inputs, -- Channel start signals
+-- HIT_CAL_IN => osc_int, --clk_20_i, -- Hits for calibrating the TDC
+-- TRG_WIN_PRE => tdc_ctrl_reg(42 downto 32), -- Pre-Trigger window width
+-- TRG_WIN_POST => tdc_ctrl_reg(58 downto 48), -- Post-Trigger window width
+-- --
+-- -- Trigger signals from handler
+-- TRG_DATA_VALID_IN => cts_rdo_trg_data_valid, -- trig data valid signal from trbnet
+-- VALID_TIMING_TRG_IN => cts_rdo_valid_timing_trg, -- valid timing trigger signal from trbnet
+-- VALID_NOTIMING_TRG_IN => cts_rdo_valid_notiming_trg, -- valid notiming signal from trbnet
+-- INVALID_TRG_IN => cts_rdo_invalid_trg, -- invalid trigger signal from trbnet
+-- TMGTRG_TIMEOUT_IN => '0', -- timing trigger timeout signal from trbnet
+-- SPIKE_DETECTED_IN => '0',
+-- MULTI_TMG_TRG_IN => '0',
+-- SPURIOUS_TRG_IN => '0',
+-- --
+-- TRG_NUMBER_IN => cts_rdo_trg_number, -- LVL1 trigger information package
+-- TRG_CODE_IN => cts_rdo_trg_code, --
+-- TRG_INFORMATION_IN => cts_rdo_trg_information, --
+-- TRG_TYPE_IN => cts_rdo_trg_type, -- LVL1 trigger information package
+-- --Response to handler
+-- -- TRG_RELEASE_OUT => fee_trg_release_i, -- trigger release signal
+-- TRG_RELEASE_OUT => open,
+-- TRG_STATUSBIT_OUT => cts_rdo_additional(1).statusbits,
+-- DATA_OUT => cts_rdo_additional(1).data,
+-- DATA_WRITE_OUT => cts_rdo_additional(1).data_write,
+-- DATA_FINISHED_OUT => cts_rdo_additional(1).data_finished,
+-- --Hit Counter Bus
+-- HCB_READ_EN_IN => hitreg_read_en, -- bus read en strobe
+-- HCB_WRITE_EN_IN => hitreg_write_en, -- bus write en strobe
+-- HCB_ADDR_IN => hitreg_addr, -- bus address
+-- HCB_DATA_OUT => hitreg_data_out, -- bus data
+-- HCB_DATAREADY_OUT => hitreg_data_ready, -- bus data ready strobe
+-- HCB_UNKNOWN_ADDR_OUT => hitreg_invalid, -- bus invalid addr
+-- --Status Registers Bus
+-- SRB_READ_EN_IN => srb_read_en, -- bus read en strobe
+-- SRB_WRITE_EN_IN => srb_write_en, -- bus write en strobe
+-- SRB_ADDR_IN => srb_addr, -- bus address
+-- SRB_DATA_OUT => srb_data_out, -- bus data
+-- SRB_DATAREADY_OUT => srb_data_ready, -- bus data ready strobe
+-- SRB_UNKNOWN_ADDR_OUT => srb_invalid, -- bus invalid addr
+-- --Encoder Start Registers Bus
+-- ESB_READ_EN_IN => esb_read_en, -- bus read en strobe
+-- ESB_WRITE_EN_IN => esb_write_en, -- bus write en strobe
+-- ESB_ADDR_IN => esb_addr, -- bus address
+-- ESB_DATA_OUT => esb_data_out, -- bus data
+-- ESB_DATAREADY_OUT => esb_data_ready, -- bus data ready strobe
+-- ESB_UNKNOWN_ADDR_OUT => esb_invalid, -- bus invalid addr
+-- --Fifo Write Registers Bus
+-- EFB_READ_EN_IN => fwb_read_en, -- bus read en strobe
+-- EFB_WRITE_EN_IN => fwb_write_en, -- bus write en strobe
+-- EFB_ADDR_IN => fwb_addr, -- bus address
+-- EFB_DATA_OUT => fwb_data_out, -- bus data
+-- EFB_DATAREADY_OUT => fwb_data_ready, -- bus data ready strobe
+-- EFB_UNKNOWN_ADDR_OUT => fwb_invalid, -- bus invalid addr
+-- --Lost Hit Registers Bus
+-- LHB_READ_EN_IN => '0', -- lhb_read_en, -- bus read en strobe
+-- LHB_WRITE_EN_IN => '0', -- lhb_write_en, -- bus write en strobe
+-- LHB_ADDR_IN => (others => '0'), -- lhb_addr, -- bus address
+-- LHB_DATA_OUT => open, -- lhb_data_out, -- bus data
+-- LHB_DATAREADY_OUT => open, -- lhb_data_ready, -- bus data ready strobe
+-- LHB_UNKNOWN_ADDR_OUT => open, -- lhb_invalid, -- bus invalid addr
+-- -- Channel Debug
+-- CDB_READ_EN_IN => '0', -- in std_logic;
+-- CDB_WRITE_EN_IN => '1', -- in std_logic;
+-- CDB_ADDR_IN => "0000000", -- in std_logic_vector(6 downto 0);
+-- CDB_DATA_OUT => open, -- out std_logic_vector(31 downto 0);
+-- CDB_DATAREADY_OUT => open, -- out std_logic;
+-- CDB_UNKNOWN_ADDR_OUT => open, -- out std_logic;
+-- --
+-- LOGIC_ANALYSER_OUT => tdc_debug,
+-- CONTROL_REG_IN => tdc_ctrl_reg
+-- );
+--
+-- --tdc_inputs(1) used by CBM-MBS ETM
+-- -- tdc_inputs(2) <= cbm_sync_pulser_i;
+-- -- tdc_inputs(3) <= cbm_sync_timing_trigger_i;
+-- tdc_inputs(4) <= JINLVDS(0); --NIM_IN(0);
+-- --JTTL(0 downto 15) <= (others => '0');
+--
+--
+-- PROC_TDC_CTRL_REG : process
+-- variable pos : integer;
+-- begin
+-- wait until rising_edge(clk_100_i);
+-- pos := to_integer(unsigned(tdc_ctrl_addr))*32;
+-- tdc_ctrl_data_out <= tdc_ctrl_reg(pos+31 downto pos);
+-- last_tdc_ctrl_read <= tdc_ctrl_read;
+-- if tdc_ctrl_write = '1' then
+-- tdc_ctrl_reg(pos+31 downto pos) <= tdc_ctrl_data_in;
+-- end if;
+-- end process;
+-- end generate;
- PROC_TDC_CTRL_REG : process
- variable pos : integer;
- begin
- wait until rising_edge(clk_100_i);
- pos := to_integer(unsigned(tdc_ctrl_addr))*32;
- tdc_ctrl_data_out <= tdc_ctrl_reg(pos+31 downto pos);
- last_tdc_ctrl_read <= tdc_ctrl_read;
- if tdc_ctrl_write = '1' then
- tdc_ctrl_reg(pos+31 downto pos) <= tdc_ctrl_data_in;
- end if;
- end process;
- end generate;
+assert INCLUDE_TDC = c_NO report "TDC not supported in TRB3" severity error;
GEN_NO_TDC : if INCLUDE_TDC = c_NO generate
srb_data_ready <= '0';
jspc29 / trb3.git / commitdiff